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TARGET_MAX32625NEXPAQ/TOOLCHAIN_IAR/ioman_regs.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
169:a7c7b631e539 | 1 | /******************************************************************************* |
| Anna Bridge |
169:a7c7b631e539 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Anna Bridge |
169:a7c7b631e539 | 3 | * |
| Anna Bridge |
169:a7c7b631e539 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Anna Bridge |
169:a7c7b631e539 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Anna Bridge |
169:a7c7b631e539 | 6 | * to deal in the Software without restriction, including without limitation |
| Anna Bridge |
169:a7c7b631e539 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Anna Bridge |
169:a7c7b631e539 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Anna Bridge |
169:a7c7b631e539 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Anna Bridge |
169:a7c7b631e539 | 10 | * |
| Anna Bridge |
169:a7c7b631e539 | 11 | * The above copyright notice and this permission notice shall be included |
| Anna Bridge |
169:a7c7b631e539 | 12 | * in all copies or substantial portions of the Software. |
| Anna Bridge |
169:a7c7b631e539 | 13 | * |
| Anna Bridge |
169:a7c7b631e539 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Anna Bridge |
169:a7c7b631e539 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Anna Bridge |
169:a7c7b631e539 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Anna Bridge |
169:a7c7b631e539 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Anna Bridge |
169:a7c7b631e539 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Anna Bridge |
169:a7c7b631e539 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Anna Bridge |
169:a7c7b631e539 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Anna Bridge |
169:a7c7b631e539 | 21 | * |
| Anna Bridge |
169:a7c7b631e539 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Anna Bridge |
169:a7c7b631e539 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Anna Bridge |
169:a7c7b631e539 | 24 | * Products, Inc. Branding Policy. |
| Anna Bridge |
169:a7c7b631e539 | 25 | * |
| Anna Bridge |
169:a7c7b631e539 | 26 | * The mere transfer of this software does not imply any licenses |
| Anna Bridge |
169:a7c7b631e539 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Anna Bridge |
169:a7c7b631e539 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Anna Bridge |
169:a7c7b631e539 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Anna Bridge |
169:a7c7b631e539 | 30 | * ownership rights. |
| Anna Bridge |
169:a7c7b631e539 | 31 | ******************************************************************************/ |
| Anna Bridge |
169:a7c7b631e539 | 32 | |
| Anna Bridge |
169:a7c7b631e539 | 33 | #ifndef _MXC_IOMAN_REGS_H_ |
| Anna Bridge |
169:a7c7b631e539 | 34 | #define _MXC_IOMAN_REGS_H_ |
| Anna Bridge |
169:a7c7b631e539 | 35 | |
| Anna Bridge |
169:a7c7b631e539 | 36 | #ifdef __cplusplus |
| Anna Bridge |
169:a7c7b631e539 | 37 | extern "C" { |
| Anna Bridge |
169:a7c7b631e539 | 38 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 39 | |
| Anna Bridge |
169:a7c7b631e539 | 40 | #include <stdint.h> |
| Anna Bridge |
169:a7c7b631e539 | 41 | #include "mxc_device.h" |
| Anna Bridge |
169:a7c7b631e539 | 42 | |
| Anna Bridge |
169:a7c7b631e539 | 43 | /* |
| Anna Bridge |
169:a7c7b631e539 | 44 | If types are not defined elsewhere (CMSIS) define them here |
| Anna Bridge |
169:a7c7b631e539 | 45 | */ |
| Anna Bridge |
169:a7c7b631e539 | 46 | #ifndef __IO |
| Anna Bridge |
169:a7c7b631e539 | 47 | #define __IO volatile |
| Anna Bridge |
169:a7c7b631e539 | 48 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 49 | #ifndef __I |
| Anna Bridge |
169:a7c7b631e539 | 50 | #define __I volatile const |
| Anna Bridge |
169:a7c7b631e539 | 51 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 52 | #ifndef __O |
| Anna Bridge |
169:a7c7b631e539 | 53 | #define __O volatile |
| Anna Bridge |
169:a7c7b631e539 | 54 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 55 | |
| Anna Bridge |
169:a7c7b631e539 | 56 | |
| Anna Bridge |
169:a7c7b631e539 | 57 | /* |
| Anna Bridge |
169:a7c7b631e539 | 58 | Bitfield structs for registers in this module |
| Anna Bridge |
169:a7c7b631e539 | 59 | */ |
| Anna Bridge |
169:a7c7b631e539 | 60 | |
| Anna Bridge |
169:a7c7b631e539 | 61 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 62 | uint32_t wud_req_p0 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 63 | uint32_t wud_req_p1 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 64 | uint32_t wud_req_p2 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 65 | uint32_t wud_req_p3 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 66 | } mxc_ioman_wud_req0_t; |
| Anna Bridge |
169:a7c7b631e539 | 67 | |
| Anna Bridge |
169:a7c7b631e539 | 68 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 69 | uint32_t wud_req_p4 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 70 | uint32_t : 24; |
| Anna Bridge |
169:a7c7b631e539 | 71 | } mxc_ioman_wud_req1_t; |
| Anna Bridge |
169:a7c7b631e539 | 72 | |
| Anna Bridge |
169:a7c7b631e539 | 73 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 74 | uint32_t wud_ack_p0 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 75 | uint32_t wud_ack_p1 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 76 | uint32_t wud_ack_p2 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 77 | uint32_t wud_ack_p3 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 78 | } mxc_ioman_wud_ack0_t; |
| Anna Bridge |
169:a7c7b631e539 | 79 | |
| Anna Bridge |
169:a7c7b631e539 | 80 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 81 | uint32_t wud_ack_p4 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 82 | uint32_t : 24; |
| Anna Bridge |
169:a7c7b631e539 | 83 | } mxc_ioman_wud_ack1_t; |
| Anna Bridge |
169:a7c7b631e539 | 84 | |
| Anna Bridge |
169:a7c7b631e539 | 85 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 86 | uint32_t ali_req_p0 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 87 | uint32_t ali_req_p1 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 88 | uint32_t ali_req_p2 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 89 | uint32_t ali_req_p3 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 90 | } mxc_ioman_ali_req0_t; |
| Anna Bridge |
169:a7c7b631e539 | 91 | |
| Anna Bridge |
169:a7c7b631e539 | 92 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 93 | uint32_t ali_req_p4 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 94 | uint32_t : 24; |
| Anna Bridge |
169:a7c7b631e539 | 95 | } mxc_ioman_ali_req1_t; |
| Anna Bridge |
169:a7c7b631e539 | 96 | |
| Anna Bridge |
169:a7c7b631e539 | 97 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 98 | uint32_t ali_ack_p0 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 99 | uint32_t ali_ack_p1 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 100 | uint32_t ali_ack_p2 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 101 | uint32_t ali_ack_p3 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 102 | } mxc_ioman_ali_ack0_t; |
| Anna Bridge |
169:a7c7b631e539 | 103 | |
| Anna Bridge |
169:a7c7b631e539 | 104 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 105 | uint32_t ali_ack_p4 : 8; |
| Anna Bridge |
169:a7c7b631e539 | 106 | uint32_t : 24; |
| Anna Bridge |
169:a7c7b631e539 | 107 | } mxc_ioman_ali_ack1_t; |
| Anna Bridge |
169:a7c7b631e539 | 108 | |
| Anna Bridge |
169:a7c7b631e539 | 109 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 110 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 111 | uint32_t core_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 112 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 113 | uint32_t ss0_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 114 | uint32_t ss1_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 115 | uint32_t ss2_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 116 | uint32_t : 1; |
| Anna Bridge |
169:a7c7b631e539 | 117 | uint32_t quad_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 118 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 119 | uint32_t fast_mode : 1; |
| Anna Bridge |
169:a7c7b631e539 | 120 | uint32_t : 15; |
| Anna Bridge |
169:a7c7b631e539 | 121 | } mxc_ioman_spix_req_t; |
| Anna Bridge |
169:a7c7b631e539 | 122 | |
| Anna Bridge |
169:a7c7b631e539 | 123 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 124 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 125 | uint32_t core_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 126 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 127 | uint32_t ss0_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 128 | uint32_t ss1_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 129 | uint32_t ss2_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 130 | uint32_t : 1; |
| Anna Bridge |
169:a7c7b631e539 | 131 | uint32_t quad_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 132 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 133 | uint32_t fast_mode : 1; |
| Anna Bridge |
169:a7c7b631e539 | 134 | uint32_t : 15; |
| Anna Bridge |
169:a7c7b631e539 | 135 | } mxc_ioman_spix_ack_t; |
| Anna Bridge |
169:a7c7b631e539 | 136 | |
| Anna Bridge |
169:a7c7b631e539 | 137 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 138 | uint32_t io_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 139 | uint32_t cts_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 140 | uint32_t rts_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 141 | uint32_t : 1; |
| Anna Bridge |
169:a7c7b631e539 | 142 | uint32_t io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 143 | uint32_t cts_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 144 | uint32_t rts_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 145 | uint32_t : 25; |
| Anna Bridge |
169:a7c7b631e539 | 146 | } mxc_ioman_uart0_req_t; |
| Anna Bridge |
169:a7c7b631e539 | 147 | |
| Anna Bridge |
169:a7c7b631e539 | 148 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 149 | uint32_t io_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 150 | uint32_t cts_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 151 | uint32_t rts_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 152 | uint32_t : 1; |
| Anna Bridge |
169:a7c7b631e539 | 153 | uint32_t io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 154 | uint32_t cts_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 155 | uint32_t rts_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 156 | uint32_t : 25; |
| Anna Bridge |
169:a7c7b631e539 | 157 | } mxc_ioman_uart0_ack_t; |
| Anna Bridge |
169:a7c7b631e539 | 158 | |
| Anna Bridge |
169:a7c7b631e539 | 159 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 160 | uint32_t io_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 161 | uint32_t cts_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 162 | uint32_t rts_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 163 | uint32_t : 1; |
| Anna Bridge |
169:a7c7b631e539 | 164 | uint32_t io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 165 | uint32_t cts_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 166 | uint32_t rts_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 167 | uint32_t : 25; |
| Anna Bridge |
169:a7c7b631e539 | 168 | } mxc_ioman_uart1_req_t; |
| Anna Bridge |
169:a7c7b631e539 | 169 | |
| Anna Bridge |
169:a7c7b631e539 | 170 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 171 | uint32_t io_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 172 | uint32_t cts_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 173 | uint32_t rts_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 174 | uint32_t : 1; |
| Anna Bridge |
169:a7c7b631e539 | 175 | uint32_t io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 176 | uint32_t cts_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 177 | uint32_t rts_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 178 | uint32_t : 25; |
| Anna Bridge |
169:a7c7b631e539 | 179 | } mxc_ioman_uart1_ack_t; |
| Anna Bridge |
169:a7c7b631e539 | 180 | |
| Anna Bridge |
169:a7c7b631e539 | 181 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 182 | uint32_t io_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 183 | uint32_t cts_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 184 | uint32_t rts_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 185 | uint32_t : 1; |
| Anna Bridge |
169:a7c7b631e539 | 186 | uint32_t io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 187 | uint32_t cts_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 188 | uint32_t rts_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 189 | uint32_t : 25; |
| Anna Bridge |
169:a7c7b631e539 | 190 | } mxc_ioman_uart2_req_t; |
| Anna Bridge |
169:a7c7b631e539 | 191 | |
| Anna Bridge |
169:a7c7b631e539 | 192 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 193 | uint32_t io_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 194 | uint32_t cts_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 195 | uint32_t rts_map : 1; |
| Anna Bridge |
169:a7c7b631e539 | 196 | uint32_t : 1; |
| Anna Bridge |
169:a7c7b631e539 | 197 | uint32_t io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 198 | uint32_t cts_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 199 | uint32_t rts_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 200 | uint32_t : 25; |
| Anna Bridge |
169:a7c7b631e539 | 201 | } mxc_ioman_uart2_ack_t; |
| Anna Bridge |
169:a7c7b631e539 | 202 | |
| Anna Bridge |
169:a7c7b631e539 | 203 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 204 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 205 | uint32_t mapping_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 206 | uint32_t scl_push_pull : 1; |
| Anna Bridge |
169:a7c7b631e539 | 207 | uint32_t : 26; |
| Anna Bridge |
169:a7c7b631e539 | 208 | } mxc_ioman_i2cm0_req_t; |
| Anna Bridge |
169:a7c7b631e539 | 209 | |
| Anna Bridge |
169:a7c7b631e539 | 210 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 211 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 212 | uint32_t mapping_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 213 | uint32_t : 27; |
| Anna Bridge |
169:a7c7b631e539 | 214 | } mxc_ioman_i2cm0_ack_t; |
| Anna Bridge |
169:a7c7b631e539 | 215 | |
| Anna Bridge |
169:a7c7b631e539 | 216 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 217 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 218 | uint32_t mapping_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 219 | uint32_t scl_push_pull : 1; |
| Anna Bridge |
169:a7c7b631e539 | 220 | uint32_t : 26; |
| Anna Bridge |
169:a7c7b631e539 | 221 | } mxc_ioman_i2cm1_req_t; |
| Anna Bridge |
169:a7c7b631e539 | 222 | |
| Anna Bridge |
169:a7c7b631e539 | 223 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 224 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 225 | uint32_t mapping_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 226 | uint32_t : 27; |
| Anna Bridge |
169:a7c7b631e539 | 227 | } mxc_ioman_i2cm1_ack_t; |
| Anna Bridge |
169:a7c7b631e539 | 228 | |
| Anna Bridge |
169:a7c7b631e539 | 229 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 230 | uint32_t io_sel : 2; |
| Anna Bridge |
169:a7c7b631e539 | 231 | uint32_t : 2; |
| Anna Bridge |
169:a7c7b631e539 | 232 | uint32_t mapping_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 233 | uint32_t : 27; |
| Anna Bridge |
169:a7c7b631e539 | 234 | } mxc_ioman_i2cs_req_t; |
| Anna Bridge |
169:a7c7b631e539 | 235 | |
| Anna Bridge |
169:a7c7b631e539 | 236 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 237 | uint32_t io_sel : 2; |
| Anna Bridge |
169:a7c7b631e539 | 238 | uint32_t : 2; |
| Anna Bridge |
169:a7c7b631e539 | 239 | uint32_t mapping_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 240 | uint32_t : 27; |
| Anna Bridge |
169:a7c7b631e539 | 241 | } mxc_ioman_i2cs_ack_t; |
| Anna Bridge |
169:a7c7b631e539 | 242 | |
| Anna Bridge |
169:a7c7b631e539 | 243 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 244 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 245 | uint32_t core_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 246 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 247 | uint32_t ss0_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 248 | uint32_t ss1_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 249 | uint32_t ss2_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 250 | uint32_t ss3_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 251 | uint32_t ss4_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 252 | uint32_t : 7; |
| Anna Bridge |
169:a7c7b631e539 | 253 | uint32_t quad_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 254 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 255 | uint32_t fast_mode : 1; |
| Anna Bridge |
169:a7c7b631e539 | 256 | uint32_t : 7; |
| Anna Bridge |
169:a7c7b631e539 | 257 | } mxc_ioman_spim0_req_t; |
| Anna Bridge |
169:a7c7b631e539 | 258 | |
| Anna Bridge |
169:a7c7b631e539 | 259 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 260 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 261 | uint32_t core_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 262 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 263 | uint32_t ss0_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 264 | uint32_t ss1_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 265 | uint32_t ss2_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 266 | uint32_t ss3_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 267 | uint32_t ss4_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 268 | uint32_t : 7; |
| Anna Bridge |
169:a7c7b631e539 | 269 | uint32_t quad_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 270 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 271 | uint32_t fast_mode : 1; |
| Anna Bridge |
169:a7c7b631e539 | 272 | uint32_t : 7; |
| Anna Bridge |
169:a7c7b631e539 | 273 | } mxc_ioman_spim0_ack_t; |
| Anna Bridge |
169:a7c7b631e539 | 274 | |
| Anna Bridge |
169:a7c7b631e539 | 275 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 276 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 277 | uint32_t core_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 278 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 279 | uint32_t ss0_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 280 | uint32_t ss1_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 281 | uint32_t ss2_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 282 | uint32_t : 9; |
| Anna Bridge |
169:a7c7b631e539 | 283 | uint32_t quad_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 284 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 285 | uint32_t fast_mode : 1; |
| Anna Bridge |
169:a7c7b631e539 | 286 | uint32_t : 7; |
| Anna Bridge |
169:a7c7b631e539 | 287 | } mxc_ioman_spim1_req_t; |
| Anna Bridge |
169:a7c7b631e539 | 288 | |
| Anna Bridge |
169:a7c7b631e539 | 289 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 290 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 291 | uint32_t core_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 292 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 293 | uint32_t ss0_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 294 | uint32_t ss1_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 295 | uint32_t ss2_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 296 | uint32_t : 9; |
| Anna Bridge |
169:a7c7b631e539 | 297 | uint32_t quad_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 298 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 299 | uint32_t fast_mode : 1; |
| Anna Bridge |
169:a7c7b631e539 | 300 | uint32_t : 7; |
| Anna Bridge |
169:a7c7b631e539 | 301 | } mxc_ioman_spim1_ack_t; |
| Anna Bridge |
169:a7c7b631e539 | 302 | |
| Anna Bridge |
169:a7c7b631e539 | 303 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 304 | uint32_t mapping_req : 2; // 1:0 |
| Anna Bridge |
169:a7c7b631e539 | 305 | uint32_t : 1; // 2:3 |
| Anna Bridge |
169:a7c7b631e539 | 306 | uint32_t core_io_req : 1; // 4 |
| Anna Bridge |
169:a7c7b631e539 | 307 | uint32_t : 3; // 5:7 |
| Anna Bridge |
169:a7c7b631e539 | 308 | uint32_t ss0_io_req : 1; // 8 |
| Anna Bridge |
169:a7c7b631e539 | 309 | uint32_t ss1_io_req : 1; // 9 |
| Anna Bridge |
169:a7c7b631e539 | 310 | uint32_t ss2_io_req : 1; // 10 |
| Anna Bridge |
169:a7c7b631e539 | 311 | uint32_t : 5; // 11:15 |
| Anna Bridge |
169:a7c7b631e539 | 312 | uint32_t sr0_io_req : 1; // 16 |
| Anna Bridge |
169:a7c7b631e539 | 313 | uint32_t sr1_io_req : 1; // 17 |
| Anna Bridge |
169:a7c7b631e539 | 314 | uint32_t : 2; // 18:19 |
| Anna Bridge |
169:a7c7b631e539 | 315 | uint32_t quad_io_req : 1; // 20 |
| Anna Bridge |
169:a7c7b631e539 | 316 | uint32_t : 3; // 21:23 |
| Anna Bridge |
169:a7c7b631e539 | 317 | uint32_t fast_mode : 1; // 24 |
| Anna Bridge |
169:a7c7b631e539 | 318 | uint32_t : 7; // 25:31 |
| Anna Bridge |
169:a7c7b631e539 | 319 | } mxc_ioman_spim2_req_t; |
| Anna Bridge |
169:a7c7b631e539 | 320 | |
| Anna Bridge |
169:a7c7b631e539 | 321 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 322 | uint32_t mapping_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 323 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 324 | uint32_t core_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 325 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 326 | uint32_t ss0_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 327 | uint32_t ss1_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 328 | uint32_t ss2_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 329 | uint32_t : 5; |
| Anna Bridge |
169:a7c7b631e539 | 330 | uint32_t sr0_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 331 | uint32_t sr1_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 332 | uint32_t : 2; |
| Anna Bridge |
169:a7c7b631e539 | 333 | uint32_t quad_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 334 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 335 | uint32_t fast_mode : 1; |
| Anna Bridge |
169:a7c7b631e539 | 336 | uint32_t : 7; |
| Anna Bridge |
169:a7c7b631e539 | 337 | } mxc_ioman_spim2_ack_t; |
| Anna Bridge |
169:a7c7b631e539 | 338 | |
| Anna Bridge |
169:a7c7b631e539 | 339 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 340 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 341 | uint32_t mapping_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 342 | uint32_t epu_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 343 | uint32_t : 26; |
| Anna Bridge |
169:a7c7b631e539 | 344 | } mxc_ioman_owm_req_t; |
| Anna Bridge |
169:a7c7b631e539 | 345 | |
| Anna Bridge |
169:a7c7b631e539 | 346 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 347 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 348 | uint32_t mapping_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 349 | uint32_t epu_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 350 | uint32_t : 26; |
| Anna Bridge |
169:a7c7b631e539 | 351 | } mxc_ioman_owm_ack_t; |
| Anna Bridge |
169:a7c7b631e539 | 352 | |
| Anna Bridge |
169:a7c7b631e539 | 353 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 354 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 355 | uint32_t core_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 356 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 357 | uint32_t quad_io_req : 1; |
| Anna Bridge |
169:a7c7b631e539 | 358 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 359 | uint32_t fast_mode : 1; |
| Anna Bridge |
169:a7c7b631e539 | 360 | uint32_t : 19; |
| Anna Bridge |
169:a7c7b631e539 | 361 | } mxc_ioman_spis_req_t; |
| Anna Bridge |
169:a7c7b631e539 | 362 | |
| Anna Bridge |
169:a7c7b631e539 | 363 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 364 | uint32_t : 4; |
| Anna Bridge |
169:a7c7b631e539 | 365 | uint32_t core_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 366 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 367 | uint32_t quad_io_ack : 1; |
| Anna Bridge |
169:a7c7b631e539 | 368 | uint32_t : 3; |
| Anna Bridge |
169:a7c7b631e539 | 369 | uint32_t fast_mode : 1; |
| Anna Bridge |
169:a7c7b631e539 | 370 | uint32_t : 19; |
| Anna Bridge |
169:a7c7b631e539 | 371 | } mxc_ioman_spis_ack_t; |
| Anna Bridge |
169:a7c7b631e539 | 372 | |
| Anna Bridge |
169:a7c7b631e539 | 373 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 374 | uint32_t slow_mode : 1; |
| Anna Bridge |
169:a7c7b631e539 | 375 | uint32_t alt_rcvr_mode : 1; |
| Anna Bridge |
169:a7c7b631e539 | 376 | uint32_t : 30; |
| Anna Bridge |
169:a7c7b631e539 | 377 | } mxc_ioman_pad_mode_t; |
| Anna Bridge |
169:a7c7b631e539 | 378 | |
| Anna Bridge |
169:a7c7b631e539 | 379 | |
| Anna Bridge |
169:a7c7b631e539 | 380 | /* |
| Anna Bridge |
169:a7c7b631e539 | 381 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| Anna Bridge |
169:a7c7b631e539 | 382 | access to each register in module. |
| Anna Bridge |
169:a7c7b631e539 | 383 | */ |
| Anna Bridge |
169:a7c7b631e539 | 384 | |
| Anna Bridge |
169:a7c7b631e539 | 385 | /* Offset Register Description |
| Anna Bridge |
169:a7c7b631e539 | 386 | ============= ============================================================================ */ |
| Anna Bridge |
169:a7c7b631e539 | 387 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 388 | __IO uint32_t wud_req0; /* 0x0000 Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) */ |
| Anna Bridge |
169:a7c7b631e539 | 389 | __IO uint32_t wud_req1; /* 0x0004 Wakeup Detect Mode Request Register 1 (P4) */ |
| Anna Bridge |
169:a7c7b631e539 | 390 | __IO uint32_t wud_ack0; /* 0x0008 Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) */ |
| Anna Bridge |
169:a7c7b631e539 | 391 | __IO uint32_t wud_ack1; /* 0x000C Wakeup Detect Mode Acknowledge Register 1 (P4) */ |
| Anna Bridge |
169:a7c7b631e539 | 392 | __IO uint32_t ali_req0; /* 0x0010 Analog Input Request Register 0 (P0/P1/P2/P3) */ |
| Anna Bridge |
169:a7c7b631e539 | 393 | __IO uint32_t ali_req1; /* 0x0014 Analog Input Request Register 1 (P4) */ |
| Anna Bridge |
169:a7c7b631e539 | 394 | __IO uint32_t ali_ack0; /* 0x0018 Analog Input Acknowledge Register 0 (P0/P1/P2/P3) */ |
| Anna Bridge |
169:a7c7b631e539 | 395 | __IO uint32_t ali_ack1; /* 0x001C Analog Input Acknowledge Register 1 (P4) */ |
| Anna Bridge |
169:a7c7b631e539 | 396 | __IO uint32_t ali_connect0; /* 0x0020 Analog I/O Connection Control Register 0 */ |
| Anna Bridge |
169:a7c7b631e539 | 397 | __IO uint32_t ali_connect1; /* 0x0024 Analog I/O Connection Control Register 1 */ |
| Anna Bridge |
169:a7c7b631e539 | 398 | __IO uint32_t spix_req; /* 0x0028 SPIX I/O Mode Request */ |
| Anna Bridge |
169:a7c7b631e539 | 399 | __IO uint32_t spix_ack; /* 0x002C SPIX I/O Mode Acknowledge */ |
| Anna Bridge |
169:a7c7b631e539 | 400 | __IO uint32_t uart0_req; /* 0x0030 UART0 I/O Mode Request */ |
| Anna Bridge |
169:a7c7b631e539 | 401 | __IO uint32_t uart0_ack; /* 0x0034 UART0 I/O Mode Acknowledge */ |
| Anna Bridge |
169:a7c7b631e539 | 402 | __IO uint32_t uart1_req; /* 0x0038 UART1 I/O Mode Request */ |
| Anna Bridge |
169:a7c7b631e539 | 403 | __IO uint32_t uart1_ack; /* 0x003C UART1 I/O Mode Acknowledge */ |
| Anna Bridge |
169:a7c7b631e539 | 404 | __IO uint32_t uart2_req; /* 0x0040 UART2 I/O Mode Request */ |
| Anna Bridge |
169:a7c7b631e539 | 405 | __IO uint32_t uart2_ack; /* 0x0044 UART2 I/O Mode Acknowledge */ |
| Anna Bridge |
169:a7c7b631e539 | 406 | __I uint32_t rsv048[2]; /* 0x0048-0x004C */ |
| Anna Bridge |
169:a7c7b631e539 | 407 | __IO uint32_t i2cm0_req; /* 0x0050 I2C Master 0 I/O Request */ |
| Anna Bridge |
169:a7c7b631e539 | 408 | __IO uint32_t i2cm0_ack; /* 0x0054 I2C Master 0 I/O Acknowledge */ |
| Anna Bridge |
169:a7c7b631e539 | 409 | __IO uint32_t i2cm1_req; /* 0x0058 I2C Master 1 I/O Request */ |
| Anna Bridge |
169:a7c7b631e539 | 410 | __IO uint32_t i2cm1_ack; /* 0x005C I2C Master 1 I/O Acknowledge */ |
| Anna Bridge |
169:a7c7b631e539 | 411 | __I uint32_t rsv060[2]; /* 0x0060-0x0064 */ |
| Anna Bridge |
169:a7c7b631e539 | 412 | __IO uint32_t i2cs_req; /* 0x0068 I2C Slave I/O Request */ |
| Anna Bridge |
169:a7c7b631e539 | 413 | __IO uint32_t i2cs_ack; /* 0x006C I2C Slave I/O Acknowledge */ |
| Anna Bridge |
169:a7c7b631e539 | 414 | __IO uint32_t spim0_req; /* 0x0070 SPI Master 0 I/O Mode Request */ |
| Anna Bridge |
169:a7c7b631e539 | 415 | __IO uint32_t spim0_ack; /* 0x0074 SPI Master 0 I/O Mode Acknowledge */ |
| Anna Bridge |
169:a7c7b631e539 | 416 | __IO uint32_t spim1_req; /* 0x0078 SPI Master 1 I/O Mode Request */ |
| Anna Bridge |
169:a7c7b631e539 | 417 | __IO uint32_t spim1_ack; /* 0x007C SPI Master 1 I/O Mode Acknowledge */ |
| Anna Bridge |
169:a7c7b631e539 | 418 | __IO uint32_t spim2_req; /* 0x0080 SPI Master 2 I/O Mode Request */ |
| Anna Bridge |
169:a7c7b631e539 | 419 | __IO uint32_t spim2_ack; /* 0x0084 SPI Master 2 I/O Mode Acknowledge */ |
| Anna Bridge |
169:a7c7b631e539 | 420 | __I uint32_t rsv088[2]; /* 0x0088-0x008C */ |
| Anna Bridge |
169:a7c7b631e539 | 421 | __IO uint32_t owm_req; /* 0x0090 1-Wire Master I/O Mode Request */ |
| Anna Bridge |
169:a7c7b631e539 | 422 | __IO uint32_t owm_ack; /* 0x0094 1-Wire Master I/O Mode Acknowledge */ |
| Anna Bridge |
169:a7c7b631e539 | 423 | __IO uint32_t spis_req; /* 0x0098 SPI Slave I/O Mode Request */ |
| Anna Bridge |
169:a7c7b631e539 | 424 | __IO uint32_t spis_ack; /* 0x009C SPI Slave I/O Mode Acknowledge */ |
| Anna Bridge |
169:a7c7b631e539 | 425 | __I uint32_t rsv0A0[24]; /* 0x00A0-0x00FC */ |
| Anna Bridge |
169:a7c7b631e539 | 426 | __IO uint32_t use_vddioh_0; /* 0x0100 Enable VDDIOH Register 0 */ |
| Anna Bridge |
169:a7c7b631e539 | 427 | __IO uint32_t use_vddioh_1; /* 0x0104 Enable VDDIOH Register 1 */ |
| Anna Bridge |
169:a7c7b631e539 | 428 | __I uint32_t rsv108[2]; /* 0x0108-0x010C */ |
| Anna Bridge |
169:a7c7b631e539 | 429 | __IO uint32_t pad_mode; /* 0x0110 Pad Mode Control Register */ |
| Anna Bridge |
169:a7c7b631e539 | 430 | } mxc_ioman_regs_t; |
| Anna Bridge |
169:a7c7b631e539 | 431 | |
| Anna Bridge |
169:a7c7b631e539 | 432 | |
| Anna Bridge |
169:a7c7b631e539 | 433 | /* |
| Anna Bridge |
169:a7c7b631e539 | 434 | Register offsets for module IOMAN. |
| Anna Bridge |
169:a7c7b631e539 | 435 | */ |
| Anna Bridge |
169:a7c7b631e539 | 436 | |
| Anna Bridge |
169:a7c7b631e539 | 437 | #define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) |
| Anna Bridge |
169:a7c7b631e539 | 438 | #define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) |
| Anna Bridge |
169:a7c7b631e539 | 439 | #define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) |
| Anna Bridge |
169:a7c7b631e539 | 440 | #define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) |
| Anna Bridge |
169:a7c7b631e539 | 441 | #define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) |
| Anna Bridge |
169:a7c7b631e539 | 442 | #define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) |
| Anna Bridge |
169:a7c7b631e539 | 443 | #define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) |
| Anna Bridge |
169:a7c7b631e539 | 444 | #define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) |
| Anna Bridge |
169:a7c7b631e539 | 445 | #define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x00000020UL) |
| Anna Bridge |
169:a7c7b631e539 | 446 | #define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000024UL) |
| Anna Bridge |
169:a7c7b631e539 | 447 | #define MXC_R_IOMAN_OFFS_SPIX_REQ ((uint32_t)0x00000028UL) |
| Anna Bridge |
169:a7c7b631e539 | 448 | #define MXC_R_IOMAN_OFFS_SPIX_ACK ((uint32_t)0x0000002CUL) |
| Anna Bridge |
169:a7c7b631e539 | 449 | #define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000030UL) |
| Anna Bridge |
169:a7c7b631e539 | 450 | #define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x00000034UL) |
| Anna Bridge |
169:a7c7b631e539 | 451 | #define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000038UL) |
| Anna Bridge |
169:a7c7b631e539 | 452 | #define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x0000003CUL) |
| Anna Bridge |
169:a7c7b631e539 | 453 | #define MXC_R_IOMAN_OFFS_UART2_REQ ((uint32_t)0x00000040UL) |
| Anna Bridge |
169:a7c7b631e539 | 454 | #define MXC_R_IOMAN_OFFS_UART2_ACK ((uint32_t)0x00000044UL) |
| Anna Bridge |
169:a7c7b631e539 | 455 | #define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000050UL) |
| Anna Bridge |
169:a7c7b631e539 | 456 | #define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x00000054UL) |
| Anna Bridge |
169:a7c7b631e539 | 457 | #define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000058UL) |
| Anna Bridge |
169:a7c7b631e539 | 458 | #define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x0000005CUL) |
| Anna Bridge |
169:a7c7b631e539 | 459 | #define MXC_R_IOMAN_OFFS_I2CS_REQ ((uint32_t)0x00000068UL) |
| Anna Bridge |
169:a7c7b631e539 | 460 | #define MXC_R_IOMAN_OFFS_I2CS_ACK ((uint32_t)0x0000006CUL) |
| Anna Bridge |
169:a7c7b631e539 | 461 | #define MXC_R_IOMAN_OFFS_SPIM0_REQ ((uint32_t)0x00000070UL) |
| Anna Bridge |
169:a7c7b631e539 | 462 | #define MXC_R_IOMAN_OFFS_SPIM0_ACK ((uint32_t)0x00000074UL) |
| Anna Bridge |
169:a7c7b631e539 | 463 | #define MXC_R_IOMAN_OFFS_SPIM1_REQ ((uint32_t)0x00000078UL) |
| Anna Bridge |
169:a7c7b631e539 | 464 | #define MXC_R_IOMAN_OFFS_SPIM1_ACK ((uint32_t)0x0000007CUL) |
| Anna Bridge |
169:a7c7b631e539 | 465 | #define MXC_R_IOMAN_OFFS_SPIM2_REQ ((uint32_t)0x00000080UL) |
| Anna Bridge |
169:a7c7b631e539 | 466 | #define MXC_R_IOMAN_OFFS_SPIM2_ACK ((uint32_t)0x00000084UL) |
| Anna Bridge |
169:a7c7b631e539 | 467 | #define MXC_R_IOMAN_OFFS_OWM_REQ ((uint32_t)0x00000090UL) |
| Anna Bridge |
169:a7c7b631e539 | 468 | #define MXC_R_IOMAN_OFFS_OWM_ACK ((uint32_t)0x00000094UL) |
| Anna Bridge |
169:a7c7b631e539 | 469 | #define MXC_R_IOMAN_OFFS_SPIS_REQ ((uint32_t)0x00000098UL) |
| Anna Bridge |
169:a7c7b631e539 | 470 | #define MXC_R_IOMAN_OFFS_SPIS_ACK ((uint32_t)0x0000009CUL) |
| Anna Bridge |
169:a7c7b631e539 | 471 | #define MXC_R_IOMAN_OFFS_USE_VDDIOH_0 ((uint32_t)0x00000100UL) |
| Anna Bridge |
169:a7c7b631e539 | 472 | #define MXC_R_IOMAN_OFFS_USE_VDDIOH_1 ((uint32_t)0x00000104UL) |
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169:a7c7b631e539 | 473 | #define MXC_R_IOMAN_OFFS_PAD_MODE ((uint32_t)0x00000110UL) |
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169:a7c7b631e539 | 474 | |
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169:a7c7b631e539 | 475 | |
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169:a7c7b631e539 | 476 | /* |
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169:a7c7b631e539 | 477 | Field positions and masks for module IOMAN. |
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169:a7c7b631e539 | 478 | */ |
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169:a7c7b631e539 | 479 | |
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169:a7c7b631e539 | 480 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS 0 |
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169:a7c7b631e539 | 481 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS)) |
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169:a7c7b631e539 | 482 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 483 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS)) |
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169:a7c7b631e539 | 484 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 485 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 486 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 487 | #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS)) |
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169:a7c7b631e539 | 488 | |
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169:a7c7b631e539 | 489 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 490 | #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS)) |
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169:a7c7b631e539 | 491 | |
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169:a7c7b631e539 | 492 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 493 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 494 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 495 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 496 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 497 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 498 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 499 | #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 500 | |
| Anna Bridge |
169:a7c7b631e539 | 501 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 502 | #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 503 | |
| Anna Bridge |
169:a7c7b631e539 | 504 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 505 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 506 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 507 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 508 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 509 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 510 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 511 | #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 512 | |
| Anna Bridge |
169:a7c7b631e539 | 513 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 514 | #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 515 | |
| Anna Bridge |
169:a7c7b631e539 | 516 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 517 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 518 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 519 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 520 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 521 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 522 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 523 | #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 524 | |
| Anna Bridge |
169:a7c7b631e539 | 525 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 526 | #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 527 | |
| Anna Bridge |
169:a7c7b631e539 | 528 | #define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 529 | #define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 530 | #define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 531 | #define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 532 | #define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS 9 |
| Anna Bridge |
169:a7c7b631e539 | 533 | #define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 534 | #define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS 10 |
| Anna Bridge |
169:a7c7b631e539 | 535 | #define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 536 | #define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS 12 |
| Anna Bridge |
169:a7c7b631e539 | 537 | #define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 538 | #define MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 539 | #define MXC_F_IOMAN_SPIX_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 540 | |
| Anna Bridge |
169:a7c7b631e539 | 541 | #define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 542 | #define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 543 | #define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 544 | #define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 545 | #define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS 9 |
| Anna Bridge |
169:a7c7b631e539 | 546 | #define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 547 | #define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS 10 |
| Anna Bridge |
169:a7c7b631e539 | 548 | #define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 549 | #define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS 12 |
| Anna Bridge |
169:a7c7b631e539 | 550 | #define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 551 | #define MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 552 | #define MXC_F_IOMAN_SPIX_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 553 | |
| Anna Bridge |
169:a7c7b631e539 | 554 | #define MXC_F_IOMAN_UART0_REQ_IO_MAP_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 555 | #define MXC_F_IOMAN_UART0_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 556 | #define MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS 1 |
| Anna Bridge |
169:a7c7b631e539 | 557 | #define MXC_F_IOMAN_UART0_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 558 | #define MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 559 | #define MXC_F_IOMAN_UART0_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 560 | #define MXC_F_IOMAN_UART0_REQ_IO_REQ_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 561 | #define MXC_F_IOMAN_UART0_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 562 | #define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 563 | #define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 564 | #define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS 6 |
| Anna Bridge |
169:a7c7b631e539 | 565 | #define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 566 | |
| Anna Bridge |
169:a7c7b631e539 | 567 | #define MXC_F_IOMAN_UART0_ACK_IO_MAP_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 568 | #define MXC_F_IOMAN_UART0_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 569 | #define MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS 1 |
| Anna Bridge |
169:a7c7b631e539 | 570 | #define MXC_F_IOMAN_UART0_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 571 | #define MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 572 | #define MXC_F_IOMAN_UART0_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 573 | #define MXC_F_IOMAN_UART0_ACK_IO_ACK_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 574 | #define MXC_F_IOMAN_UART0_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 575 | #define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 576 | #define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 577 | #define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS 6 |
| Anna Bridge |
169:a7c7b631e539 | 578 | #define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 579 | |
| Anna Bridge |
169:a7c7b631e539 | 580 | #define MXC_F_IOMAN_UART1_REQ_IO_MAP_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 581 | #define MXC_F_IOMAN_UART1_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 582 | #define MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS 1 |
| Anna Bridge |
169:a7c7b631e539 | 583 | #define MXC_F_IOMAN_UART1_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 584 | #define MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 585 | #define MXC_F_IOMAN_UART1_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 586 | #define MXC_F_IOMAN_UART1_REQ_IO_REQ_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 587 | #define MXC_F_IOMAN_UART1_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 588 | #define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 589 | #define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 590 | #define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS 6 |
| Anna Bridge |
169:a7c7b631e539 | 591 | #define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 592 | |
| Anna Bridge |
169:a7c7b631e539 | 593 | #define MXC_F_IOMAN_UART1_ACK_IO_MAP_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 594 | #define MXC_F_IOMAN_UART1_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 595 | #define MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS 1 |
| Anna Bridge |
169:a7c7b631e539 | 596 | #define MXC_F_IOMAN_UART1_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 597 | #define MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 598 | #define MXC_F_IOMAN_UART1_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 599 | #define MXC_F_IOMAN_UART1_ACK_IO_ACK_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 600 | #define MXC_F_IOMAN_UART1_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 601 | #define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 602 | #define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 603 | #define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS 6 |
| Anna Bridge |
169:a7c7b631e539 | 604 | #define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 605 | |
| Anna Bridge |
169:a7c7b631e539 | 606 | #define MXC_F_IOMAN_UART2_REQ_IO_MAP_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 607 | #define MXC_F_IOMAN_UART2_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 608 | #define MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS 1 |
| Anna Bridge |
169:a7c7b631e539 | 609 | #define MXC_F_IOMAN_UART2_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 610 | #define MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 611 | #define MXC_F_IOMAN_UART2_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 612 | #define MXC_F_IOMAN_UART2_REQ_IO_REQ_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 613 | #define MXC_F_IOMAN_UART2_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 614 | #define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 615 | #define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 616 | #define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS 6 |
| Anna Bridge |
169:a7c7b631e539 | 617 | #define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 618 | |
| Anna Bridge |
169:a7c7b631e539 | 619 | #define MXC_F_IOMAN_UART2_ACK_IO_MAP_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 620 | #define MXC_F_IOMAN_UART2_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 621 | #define MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS 1 |
| Anna Bridge |
169:a7c7b631e539 | 622 | #define MXC_F_IOMAN_UART2_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 623 | #define MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 624 | #define MXC_F_IOMAN_UART2_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 625 | #define MXC_F_IOMAN_UART2_ACK_IO_ACK_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 626 | #define MXC_F_IOMAN_UART2_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 627 | #define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 628 | #define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 629 | #define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS 6 |
| Anna Bridge |
169:a7c7b631e539 | 630 | #define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 631 | |
| Anna Bridge |
169:a7c7b631e539 | 632 | #define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 633 | #define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 634 | #define MXC_F_IOMAN_I2CM0_REQ_SCL_PUSH_PULL_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 635 | #define MXC_F_IOMAN_I2CM0_REQ_SCL_PUSH_PULL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_SCL_PUSH_PULL_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 636 | |
| Anna Bridge |
169:a7c7b631e539 | 637 | #define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 638 | #define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 639 | |
| Anna Bridge |
169:a7c7b631e539 | 640 | #define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 641 | #define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 642 | #define MXC_F_IOMAN_I2CM1_REQ_SCL_PUSH_PULL_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 643 | #define MXC_F_IOMAN_I2CM1_REQ_SCL_PUSH_PULL ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_SCL_PUSH_PULL_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 644 | |
| Anna Bridge |
169:a7c7b631e539 | 645 | #define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 646 | #define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 647 | |
| Anna Bridge |
169:a7c7b631e539 | 648 | #define MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 649 | #define MXC_F_IOMAN_I2CS_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 650 | #define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 651 | #define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 652 | |
| Anna Bridge |
169:a7c7b631e539 | 653 | #define MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 654 | #define MXC_F_IOMAN_I2CS_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 655 | #define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 656 | #define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 657 | |
| Anna Bridge |
169:a7c7b631e539 | 658 | #define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 659 | #define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 660 | #define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 661 | #define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 662 | #define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS 9 |
| Anna Bridge |
169:a7c7b631e539 | 663 | #define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 664 | #define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS 10 |
| Anna Bridge |
169:a7c7b631e539 | 665 | #define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 666 | #define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS 11 |
| Anna Bridge |
169:a7c7b631e539 | 667 | #define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 668 | #define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS 12 |
| Anna Bridge |
169:a7c7b631e539 | 669 | #define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 670 | #define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS 20 |
| Anna Bridge |
169:a7c7b631e539 | 671 | #define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 672 | #define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 673 | #define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 674 | |
| Anna Bridge |
169:a7c7b631e539 | 675 | #define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 676 | #define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 677 | #define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 678 | #define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 679 | #define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS 9 |
| Anna Bridge |
169:a7c7b631e539 | 680 | #define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 681 | #define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS 10 |
| Anna Bridge |
169:a7c7b631e539 | 682 | #define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 683 | #define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS 11 |
| Anna Bridge |
169:a7c7b631e539 | 684 | #define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 685 | #define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS 12 |
| Anna Bridge |
169:a7c7b631e539 | 686 | #define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 687 | #define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS 20 |
| Anna Bridge |
169:a7c7b631e539 | 688 | #define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 689 | #define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 690 | #define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 691 | |
| Anna Bridge |
169:a7c7b631e539 | 692 | #define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 693 | #define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 694 | #define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 695 | #define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 696 | #define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS 9 |
| Anna Bridge |
169:a7c7b631e539 | 697 | #define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 698 | #define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS 10 |
| Anna Bridge |
169:a7c7b631e539 | 699 | #define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 700 | #define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS 20 |
| Anna Bridge |
169:a7c7b631e539 | 701 | #define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 702 | #define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 703 | #define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 704 | |
| Anna Bridge |
169:a7c7b631e539 | 705 | #define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 706 | #define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 707 | #define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 708 | #define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 709 | #define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS 9 |
| Anna Bridge |
169:a7c7b631e539 | 710 | #define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 711 | #define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS 10 |
| Anna Bridge |
169:a7c7b631e539 | 712 | #define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 713 | #define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS 20 |
| Anna Bridge |
169:a7c7b631e539 | 714 | #define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 715 | #define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 716 | #define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 717 | |
| Anna Bridge |
169:a7c7b631e539 | 718 | #define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 719 | #define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 720 | #define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 721 | #define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 722 | #define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 723 | #define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 724 | #define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS 9 |
| Anna Bridge |
169:a7c7b631e539 | 725 | #define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 726 | #define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS 10 |
| Anna Bridge |
169:a7c7b631e539 | 727 | #define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 728 | #define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 729 | #define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 730 | #define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS 17 |
| Anna Bridge |
169:a7c7b631e539 | 731 | #define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 732 | #define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 733 | #define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 734 | |
| Anna Bridge |
169:a7c7b631e539 | 735 | #define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 736 | #define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 737 | #define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 738 | #define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 739 | #define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 740 | #define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 741 | #define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS 9 |
| Anna Bridge |
169:a7c7b631e539 | 742 | #define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 743 | #define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS 10 |
| Anna Bridge |
169:a7c7b631e539 | 744 | #define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 745 | #define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_ACK_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 746 | #define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 747 | #define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_ACK_POS 17 |
| Anna Bridge |
169:a7c7b631e539 | 748 | #define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR1_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 749 | #define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 750 | #define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 751 | |
| Anna Bridge |
169:a7c7b631e539 | 752 | #define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 753 | #define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 754 | #define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 755 | #define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 756 | |
| Anna Bridge |
169:a7c7b631e539 | 757 | #define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 758 | #define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 759 | #define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 760 | #define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 761 | |
| Anna Bridge |
169:a7c7b631e539 | 762 | #define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 763 | #define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 764 | #define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 765 | #define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 766 | #define MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS 12 |
| Anna Bridge |
169:a7c7b631e539 | 767 | #define MXC_F_IOMAN_SPIS_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 768 | |
| Anna Bridge |
169:a7c7b631e539 | 769 | #define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 770 | #define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 771 | #define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 772 | #define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 773 | #define MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS 12 |
| Anna Bridge |
169:a7c7b631e539 | 774 | #define MXC_F_IOMAN_SPIS_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 775 | |
| Anna Bridge |
169:a7c7b631e539 | 776 | #define MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 777 | #define MXC_F_IOMAN_PAD_MODE_SLOW_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 778 | #define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS 1 |
| Anna Bridge |
169:a7c7b631e539 | 779 | #define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 780 | |
| Anna Bridge |
169:a7c7b631e539 | 781 | /* |
| Anna Bridge |
169:a7c7b631e539 | 782 | Generic field positions and masks for module IOMAN. |
| Anna Bridge |
169:a7c7b631e539 | 783 | */ |
| Anna Bridge |
169:a7c7b631e539 | 784 | #define MXC_F_IOMAN_UART_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 785 | #define MXC_F_IOMAN_UART_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 786 | #define MXC_F_IOMAN_UART_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 787 | #define MXC_F_IOMAN_UART_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 788 | #define MXC_F_IOMAN_UART_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 789 | #define MXC_F_IOMAN_UART_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 790 | |
| Anna Bridge |
169:a7c7b631e539 | 791 | #define MXC_F_IOMAN_UART_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 792 | #define MXC_F_IOMAN_UART_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 793 | #define MXC_F_IOMAN_UART_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 794 | #define MXC_F_IOMAN_UART_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 795 | #define MXC_F_IOMAN_UART_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 796 | #define MXC_F_IOMAN_UART_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 797 | |
| Anna Bridge |
169:a7c7b631e539 | 798 | #define MXC_F_IOMAN_I2CM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 799 | #define MXC_F_IOMAN_I2CM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 800 | |
| Anna Bridge |
169:a7c7b631e539 | 801 | #define MXC_F_IOMAN_SPIM_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 802 | #define MXC_F_IOMAN_SPIM_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 803 | #define MXC_F_IOMAN_SPIM_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 804 | #define MXC_F_IOMAN_SPIM_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 805 | #define MXC_F_IOMAN_SPIM_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 806 | #define MXC_F_IOMAN_SPIM_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 807 | #define MXC_F_IOMAN_SPIM_ACK_SR0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 808 | #define MXC_F_IOMAN_SPIM_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 809 | #define MXC_F_IOMAN_SPIM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 810 | |
| Anna Bridge |
169:a7c7b631e539 | 811 | #ifdef __cplusplus |
| Anna Bridge |
169:a7c7b631e539 | 812 | } |
| Anna Bridge |
169:a7c7b631e539 | 813 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 814 | |
| Anna Bridge |
169:a7c7b631e539 | 815 | #endif /* _MXC_IOMAN_REGS_H_ */ |
| Anna Bridge |
169:a7c7b631e539 | 816 |
