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TARGET_MAX32625NEXPAQ/TOOLCHAIN_GCC_ARM/pmu_regs.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
169:a7c7b631e539 | 1 | /******************************************************************************* |
| Anna Bridge |
169:a7c7b631e539 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Anna Bridge |
169:a7c7b631e539 | 3 | * |
| Anna Bridge |
169:a7c7b631e539 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Anna Bridge |
169:a7c7b631e539 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Anna Bridge |
169:a7c7b631e539 | 6 | * to deal in the Software without restriction, including without limitation |
| Anna Bridge |
169:a7c7b631e539 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Anna Bridge |
169:a7c7b631e539 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Anna Bridge |
169:a7c7b631e539 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Anna Bridge |
169:a7c7b631e539 | 10 | * |
| Anna Bridge |
169:a7c7b631e539 | 11 | * The above copyright notice and this permission notice shall be included |
| Anna Bridge |
169:a7c7b631e539 | 12 | * in all copies or substantial portions of the Software. |
| Anna Bridge |
169:a7c7b631e539 | 13 | * |
| Anna Bridge |
169:a7c7b631e539 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Anna Bridge |
169:a7c7b631e539 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Anna Bridge |
169:a7c7b631e539 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Anna Bridge |
169:a7c7b631e539 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Anna Bridge |
169:a7c7b631e539 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Anna Bridge |
169:a7c7b631e539 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Anna Bridge |
169:a7c7b631e539 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Anna Bridge |
169:a7c7b631e539 | 21 | * |
| Anna Bridge |
169:a7c7b631e539 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Anna Bridge |
169:a7c7b631e539 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Anna Bridge |
169:a7c7b631e539 | 24 | * Products, Inc. Branding Policy. |
| Anna Bridge |
169:a7c7b631e539 | 25 | * |
| Anna Bridge |
169:a7c7b631e539 | 26 | * The mere transfer of this software does not imply any licenses |
| Anna Bridge |
169:a7c7b631e539 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Anna Bridge |
169:a7c7b631e539 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Anna Bridge |
169:a7c7b631e539 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Anna Bridge |
169:a7c7b631e539 | 30 | * ownership rights. |
| Anna Bridge |
169:a7c7b631e539 | 31 | ******************************************************************************/ |
| Anna Bridge |
169:a7c7b631e539 | 32 | |
| Anna Bridge |
169:a7c7b631e539 | 33 | #ifndef _MXC_PMU_REGS_H_ |
| Anna Bridge |
169:a7c7b631e539 | 34 | #define _MXC_PMU_REGS_H_ |
| Anna Bridge |
169:a7c7b631e539 | 35 | |
| Anna Bridge |
169:a7c7b631e539 | 36 | #ifdef __cplusplus |
| Anna Bridge |
169:a7c7b631e539 | 37 | extern "C" { |
| Anna Bridge |
169:a7c7b631e539 | 38 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 39 | |
| Anna Bridge |
169:a7c7b631e539 | 40 | #include <stdint.h> |
| Anna Bridge |
169:a7c7b631e539 | 41 | #include "mxc_device.h" |
| Anna Bridge |
169:a7c7b631e539 | 42 | |
| Anna Bridge |
169:a7c7b631e539 | 43 | /* |
| Anna Bridge |
169:a7c7b631e539 | 44 | If types are not defined elsewhere (CMSIS) define them here |
| Anna Bridge |
169:a7c7b631e539 | 45 | */ |
| Anna Bridge |
169:a7c7b631e539 | 46 | #ifndef __IO |
| Anna Bridge |
169:a7c7b631e539 | 47 | #define __IO volatile |
| Anna Bridge |
169:a7c7b631e539 | 48 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 49 | #ifndef __I |
| Anna Bridge |
169:a7c7b631e539 | 50 | #define __I volatile const |
| Anna Bridge |
169:a7c7b631e539 | 51 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 52 | #ifndef __O |
| Anna Bridge |
169:a7c7b631e539 | 53 | #define __O volatile |
| Anna Bridge |
169:a7c7b631e539 | 54 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 55 | |
| Anna Bridge |
169:a7c7b631e539 | 56 | /* |
| Anna Bridge |
169:a7c7b631e539 | 57 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| Anna Bridge |
169:a7c7b631e539 | 58 | access to each register in module. |
| Anna Bridge |
169:a7c7b631e539 | 59 | */ |
| Anna Bridge |
169:a7c7b631e539 | 60 | |
| Anna Bridge |
169:a7c7b631e539 | 61 | /* Offset Register Description |
| Anna Bridge |
169:a7c7b631e539 | 62 | ============= ============================================================================ */ |
| Anna Bridge |
169:a7c7b631e539 | 63 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 64 | __IO uint32_t dscadr; /* 0x0000 PMU Channel Next Descriptor Address */ |
| Anna Bridge |
169:a7c7b631e539 | 65 | __IO uint32_t cfg; /* 0x0004 PMU Channel Configuration */ |
| Anna Bridge |
169:a7c7b631e539 | 66 | __IO uint32_t loop; /* 0x0008 PMU Channel Loop Counters */ |
| Anna Bridge |
169:a7c7b631e539 | 67 | __I uint32_t rsv00C[5]; /* 0x000C-0x001C */ |
| Anna Bridge |
169:a7c7b631e539 | 68 | } mxc_pmu_regs_t; |
| Anna Bridge |
169:a7c7b631e539 | 69 | |
| Anna Bridge |
169:a7c7b631e539 | 70 | |
| Anna Bridge |
169:a7c7b631e539 | 71 | /* |
| Anna Bridge |
169:a7c7b631e539 | 72 | Register offsets for module PMU. |
| Anna Bridge |
169:a7c7b631e539 | 73 | */ |
| Anna Bridge |
169:a7c7b631e539 | 74 | |
| Anna Bridge |
169:a7c7b631e539 | 75 | #define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL) |
| Anna Bridge |
169:a7c7b631e539 | 76 | #define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL) |
| Anna Bridge |
169:a7c7b631e539 | 77 | #define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL) |
| Anna Bridge |
169:a7c7b631e539 | 78 | |
| Anna Bridge |
169:a7c7b631e539 | 79 | |
| Anna Bridge |
169:a7c7b631e539 | 80 | /* |
| Anna Bridge |
169:a7c7b631e539 | 81 | Field positions and masks for module PMU. |
| Anna Bridge |
169:a7c7b631e539 | 82 | */ |
| Anna Bridge |
169:a7c7b631e539 | 83 | |
| Anna Bridge |
169:a7c7b631e539 | 84 | #define MXC_F_PMU_CFG_ENABLE_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 85 | #define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 86 | #define MXC_F_PMU_CFG_LL_STOPPED_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 87 | #define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 88 | #define MXC_F_PMU_CFG_MANUAL_POS 3 |
| Anna Bridge |
169:a7c7b631e539 | 89 | #define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 90 | #define MXC_F_PMU_CFG_BUS_ERROR_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 91 | #define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 92 | #define MXC_F_PMU_CFG_TO_STAT_POS 6 |
| Anna Bridge |
169:a7c7b631e539 | 93 | #define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 94 | #define MXC_F_PMU_CFG_TO_SEL_POS 11 |
| Anna Bridge |
169:a7c7b631e539 | 95 | #define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 96 | #define MXC_F_PMU_CFG_PS_SEL_POS 14 |
| Anna Bridge |
169:a7c7b631e539 | 97 | #define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 98 | #define MXC_F_PMU_CFG_INTERRUPT_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 99 | #define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 100 | #define MXC_F_PMU_CFG_INT_EN_POS 17 |
| Anna Bridge |
169:a7c7b631e539 | 101 | #define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 102 | #define MXC_F_PMU_CFG_BURST_SIZE_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 103 | #define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 104 | |
| Anna Bridge |
169:a7c7b631e539 | 105 | #define MXC_F_PMU_LOOP_COUNTER_0_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 106 | #define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 107 | #define MXC_F_PMU_LOOP_COUNTER_1_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 108 | #define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 109 | |
| Anna Bridge |
169:a7c7b631e539 | 110 | /* |
| Anna Bridge |
169:a7c7b631e539 | 111 | Field values |
| Anna Bridge |
169:a7c7b631e539 | 112 | */ |
| Anna Bridge |
169:a7c7b631e539 | 113 | |
| Anna Bridge |
169:a7c7b631e539 | 114 | #define MXC_V_PMU_CFG_TO_SEL_TICKS_4 ((uint32_t)(0x00000000UL)) |
| Anna Bridge |
169:a7c7b631e539 | 115 | #define MXC_V_PMU_CFG_TO_SEL_TICKS_8 ((uint32_t)(0x00000001UL)) |
| Anna Bridge |
169:a7c7b631e539 | 116 | #define MXC_V_PMU_CFG_TO_SEL_TICKS_16 ((uint32_t)(0x00000002UL)) |
| Anna Bridge |
169:a7c7b631e539 | 117 | #define MXC_V_PMU_CFG_TO_SEL_TICKS_32 ((uint32_t)(0x00000003UL)) |
| Anna Bridge |
169:a7c7b631e539 | 118 | #define MXC_V_PMU_CFG_TO_SEL_TICKS_64 ((uint32_t)(0x00000004UL)) |
| Anna Bridge |
169:a7c7b631e539 | 119 | #define MXC_V_PMU_CFG_TO_SEL_TICKS_128 ((uint32_t)(0x00000005UL)) |
| Anna Bridge |
169:a7c7b631e539 | 120 | #define MXC_V_PMU_CFG_TO_SEL_TICKS_256 ((uint32_t)(0x00000006UL)) |
| Anna Bridge |
169:a7c7b631e539 | 121 | #define MXC_V_PMU_CFG_TO_SEL_TICKS_512 ((uint32_t)(0x00000007UL)) |
| Anna Bridge |
169:a7c7b631e539 | 122 | |
| Anna Bridge |
169:a7c7b631e539 | 123 | #define MXC_V_PMU_CFG_PS_SEL_DISABLE ((uint32_t)(0x00000000UL)) |
| Anna Bridge |
169:a7c7b631e539 | 124 | #define MXC_V_PMU_CFG_PS_SEL_DIV_2_8 ((uint32_t)(0x00000001UL)) |
| Anna Bridge |
169:a7c7b631e539 | 125 | #define MXC_V_PMU_CFG_PS_SEL_DIV_2_16 ((uint32_t)(0x00000002UL)) |
| Anna Bridge |
169:a7c7b631e539 | 126 | #define MXC_V_PMU_CFG_PS_SEL_DIV_2_24 ((uint32_t)(0x00000003UL)) |
| Anna Bridge |
169:a7c7b631e539 | 127 | |
| Anna Bridge |
169:a7c7b631e539 | 128 | /* Op codes */ |
| Anna Bridge |
169:a7c7b631e539 | 129 | #define PMU_MOVE_OP 0 |
| Anna Bridge |
169:a7c7b631e539 | 130 | #define PMU_WRITE_OP 1 |
| Anna Bridge |
169:a7c7b631e539 | 131 | #define PMU_WAIT_OP 2 |
| Anna Bridge |
169:a7c7b631e539 | 132 | #define PMU_JUMP_OP 3 |
| Anna Bridge |
169:a7c7b631e539 | 133 | #define PMU_LOOP_OP 4 |
| Anna Bridge |
169:a7c7b631e539 | 134 | #define PMU_POLL_OP 5 |
| Anna Bridge |
169:a7c7b631e539 | 135 | #define PMU_BRANCH_OP 6 |
| Anna Bridge |
169:a7c7b631e539 | 136 | #define PMU_TRANSFER_OP 7 |
| Anna Bridge |
169:a7c7b631e539 | 137 | |
| Anna Bridge |
169:a7c7b631e539 | 138 | /* Bit values used in all decroptiors */ |
| Anna Bridge |
169:a7c7b631e539 | 139 | #define PMU_NO_INTERRUPT 0 /* Interrupt flag is NOT set at end of channel execution */ |
| Anna Bridge |
169:a7c7b631e539 | 140 | #define PMU_INTERRUPT 1 /* Interrupt flag is set at end of channel execution */ |
| Anna Bridge |
169:a7c7b631e539 | 141 | |
| Anna Bridge |
169:a7c7b631e539 | 142 | #define PMU_NO_STOP 0 /* Do not stop channel after this descriptor ends */ |
| Anna Bridge |
169:a7c7b631e539 | 143 | #define PMU_STOP 1 /* Halt PMU channel after this descriptor ends */ |
| Anna Bridge |
169:a7c7b631e539 | 144 | |
| Anna Bridge |
169:a7c7b631e539 | 145 | /* Interrupt and Stop bit positions */ |
| Anna Bridge |
169:a7c7b631e539 | 146 | #define PMU_INT_POS 3 |
| Anna Bridge |
169:a7c7b631e539 | 147 | #define PMU_STOP_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 148 | |
| Anna Bridge |
169:a7c7b631e539 | 149 | /* MOVE descriptor bit values */ |
| Anna Bridge |
169:a7c7b631e539 | 150 | #define PMU_MOVE_READ_8_BIT 0 /* Read size = 8 */ |
| Anna Bridge |
169:a7c7b631e539 | 151 | #define PMU_MOVE_READ_16_BIT 1 /* Read size = 16 */ |
| Anna Bridge |
169:a7c7b631e539 | 152 | #define PMU_MOVE_READ_32_BIT 2 /* Read size = 32 */ |
| Anna Bridge |
169:a7c7b631e539 | 153 | |
| Anna Bridge |
169:a7c7b631e539 | 154 | #define PMU_MOVE_READ_NO_INC 0 /* read address not incremented */ |
| Anna Bridge |
169:a7c7b631e539 | 155 | #define PMU_MOVE_READ_INC 1 /* Auto-Increment read address */ |
| Anna Bridge |
169:a7c7b631e539 | 156 | |
| Anna Bridge |
169:a7c7b631e539 | 157 | #define PMU_MOVE_WRITE_8_BIT 0 /* Write Size = 8 */ |
| Anna Bridge |
169:a7c7b631e539 | 158 | #define PMU_MOVE_WRITE_16_BIT 1 /* Write Size = 16 */ |
| Anna Bridge |
169:a7c7b631e539 | 159 | #define PMU_MOVE_WRITE_32_BIT 2 /* Write Size = 32 */ |
| Anna Bridge |
169:a7c7b631e539 | 160 | |
| Anna Bridge |
169:a7c7b631e539 | 161 | #define PMU_MOVE_WRITE_NO_INC 0 /* Write address not incremented */ |
| Anna Bridge |
169:a7c7b631e539 | 162 | #define PMU_MOVE_WRITE_INC 1 /* Auto_Increment write address */ |
| Anna Bridge |
169:a7c7b631e539 | 163 | |
| Anna Bridge |
169:a7c7b631e539 | 164 | #define PMU_MOVE_NO_CONT 0 /* MOVE does not rely on previous MOVE */ |
| Anna Bridge |
169:a7c7b631e539 | 165 | #define PMU_MOVE_CONT 1 /* MOVE continues from read/write address */ |
| Anna Bridge |
169:a7c7b631e539 | 166 | /* and INC values defined in previous MOVE */ |
| Anna Bridge |
169:a7c7b631e539 | 167 | |
| Anna Bridge |
169:a7c7b631e539 | 168 | /* MOVE bit positions */ |
| Anna Bridge |
169:a7c7b631e539 | 169 | #define PMU_MOVE_READS_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 170 | #define PMU_MOVE_READI_POS 7 |
| Anna Bridge |
169:a7c7b631e539 | 171 | #define PMU_MOVE_WRITES_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 172 | #define PMU_MOVE_WRITEI_POS 10 |
| Anna Bridge |
169:a7c7b631e539 | 173 | #define PMU_MOVE_CONT_POS 11 |
| Anna Bridge |
169:a7c7b631e539 | 174 | #define PMU_MOVE_LEN_POS 12 |
| Anna Bridge |
169:a7c7b631e539 | 175 | |
| Anna Bridge |
169:a7c7b631e539 | 176 | /* WRITE descriptor bit values */ |
| Anna Bridge |
169:a7c7b631e539 | 177 | #define PMU_WRITE_MASKED_WRITE_VALUE 0 /* Value = READ_VALUE & (~WRITE_MASK) | WRITE_VALUE */ |
| Anna Bridge |
169:a7c7b631e539 | 178 | #define PMU_WRITE_PLUS_1 1 /* Value = READ_VALUE + 1 */ |
| Anna Bridge |
169:a7c7b631e539 | 179 | #define PMU_WRITE_MINUS_1 2 /* Value = READ_VALUE - 1 */ |
| Anna Bridge |
169:a7c7b631e539 | 180 | #define PMU_WRITE_SHIFT_RT_1 3 /* Value = READ_VALUE >> 1 */ |
| Anna Bridge |
169:a7c7b631e539 | 181 | #define PMU_WRITE_SHIFT_LT_1 4 /* Value = READ_VALUE << 1 */ |
| Anna Bridge |
169:a7c7b631e539 | 182 | #define PMU_WRITE_ROTATE_RT_1 5 /* Value = READ_VALUE rotated right by 1 (bit 0 becomes bit 31) */ |
| Anna Bridge |
169:a7c7b631e539 | 183 | #define PMU_WRITE_ROTATE_LT_1 6 /* Value = READ_VALUE rotated left by 1 (bit 31 becomes bit 0) */ |
| Anna Bridge |
169:a7c7b631e539 | 184 | #define PMU_WRITE_NOT_READ_VAL 7 /* Value = ~READ_VALUE */ |
| Anna Bridge |
169:a7c7b631e539 | 185 | #define PMU_WRITE_XOR_MASK 8 /* Value = READ_VALUE XOR WRITE_MASK */ |
| Anna Bridge |
169:a7c7b631e539 | 186 | #define PMU_WRITE_OR_MASK 9 /* Value = READ_VALUE | WRITE_MASK */ |
| Anna Bridge |
169:a7c7b631e539 | 187 | #define PMU_WRITE_AND_MASK 10 /* Value = READ_VALUE & WRITE_MASK */ |
| Anna Bridge |
169:a7c7b631e539 | 188 | |
| Anna Bridge |
169:a7c7b631e539 | 189 | /* WRITE bit positions */ |
| Anna Bridge |
169:a7c7b631e539 | 190 | #define PMU_WRITE_METHOD_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 191 | |
| Anna Bridge |
169:a7c7b631e539 | 192 | /* WAIT descriptor bit values */ |
| Anna Bridge |
169:a7c7b631e539 | 193 | #define PMU_WAIT_SEL_0 0 /* Select the interrupt source */ |
| Anna Bridge |
169:a7c7b631e539 | 194 | #define PMU_WAIT_SEL_1 1 |
| Anna Bridge |
169:a7c7b631e539 | 195 | |
| Anna Bridge |
169:a7c7b631e539 | 196 | /* WAIT bit positions */ |
| Anna Bridge |
169:a7c7b631e539 | 197 | #define PMU_WAIT_WAIT_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 198 | #define PMU_WAIT_SEL_POS 6 |
| Anna Bridge |
169:a7c7b631e539 | 199 | |
| Anna Bridge |
169:a7c7b631e539 | 200 | /* LOOP descriptor bit values */ |
| Anna Bridge |
169:a7c7b631e539 | 201 | #define PMU_LOOP_SEL_COUNTER0 0 /* select Counter0 to count down from */ |
| Anna Bridge |
169:a7c7b631e539 | 202 | #define PMU_LOOP_SEL_COUNTER1 1 /* select Counter1 to count down from */ |
| Anna Bridge |
169:a7c7b631e539 | 203 | |
| Anna Bridge |
169:a7c7b631e539 | 204 | /* LOOP bit positions */ |
| Anna Bridge |
169:a7c7b631e539 | 205 | #define PMU_LOOP_SEL_COUNTER_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 206 | |
| Anna Bridge |
169:a7c7b631e539 | 207 | /* POLL descriptor bit values */ |
| Anna Bridge |
169:a7c7b631e539 | 208 | #define PMU_POLL_OR 0 /* polling ends when at least one mask bit matches expected data */ |
| Anna Bridge |
169:a7c7b631e539 | 209 | #define PMU_POLL_AND 1 /* polling ends when all mask bits matches expected data */ |
| Anna Bridge |
169:a7c7b631e539 | 210 | |
| Anna Bridge |
169:a7c7b631e539 | 211 | /* POLL bit positions */ |
| Anna Bridge |
169:a7c7b631e539 | 212 | #define PMU_POLL_AND_POS 7 |
| Anna Bridge |
169:a7c7b631e539 | 213 | |
| Anna Bridge |
169:a7c7b631e539 | 214 | /* BRANCH descriptor bit values */ |
| Anna Bridge |
169:a7c7b631e539 | 215 | #define PMU_BRANCH_OR 0 /* branch when any mask bit = or != expected data (based on = or != branch type) */ |
| Anna Bridge |
169:a7c7b631e539 | 216 | #define PMU_BRANCH_AND 1 /* branch when all mask bit = or != expected data (based on = or != branch type) */ |
| Anna Bridge |
169:a7c7b631e539 | 217 | |
| Anna Bridge |
169:a7c7b631e539 | 218 | #define PMU_BRANCH_TYPE_NOT_EQUAL 0 /* Branch when polled data != expected data */ |
| Anna Bridge |
169:a7c7b631e539 | 219 | #define PMU_BRANCH_TYPE_EQUAL 1 /* Branch when polled data = expected data */ |
| Anna Bridge |
169:a7c7b631e539 | 220 | #define PMU_BRANCH_TYPE_LESS_OR_EQUAL 2 /* Branch when polled data <= expected data */ |
| Anna Bridge |
169:a7c7b631e539 | 221 | #define PMU_BRANCH_TYPE_GREAT_OR_EQUAL 3 /* Branch when polled data >= expected data */ |
| Anna Bridge |
169:a7c7b631e539 | 222 | #define PMU_BRANCH_TYPE_LESSER 4 /* Branch when polled data < expected data */ |
| Anna Bridge |
169:a7c7b631e539 | 223 | #define PMU_BRANCH_TYPE_GREATER 5 /* Branch when polled data > expected data */ |
| Anna Bridge |
169:a7c7b631e539 | 224 | |
| Anna Bridge |
169:a7c7b631e539 | 225 | /* BRANCH bit positions */ |
| Anna Bridge |
169:a7c7b631e539 | 226 | #define PMU_BRANCH_AND_POS 7 |
| Anna Bridge |
169:a7c7b631e539 | 227 | #define PMU_BRANCH_TYPE_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 228 | |
| Anna Bridge |
169:a7c7b631e539 | 229 | /* TRANSFER descriptor bit values */ |
| Anna Bridge |
169:a7c7b631e539 | 230 | #define PMU_TX_READ_8_BIT 0 /* Read size = 8 */ |
| Anna Bridge |
169:a7c7b631e539 | 231 | #define PMU_TX_READ_16_BIT 1 /* Read size = 16 */ |
| Anna Bridge |
169:a7c7b631e539 | 232 | #define PMU_TX_READ_32_BIT 2 /* Read size = 32 */ |
| Anna Bridge |
169:a7c7b631e539 | 233 | |
| Anna Bridge |
169:a7c7b631e539 | 234 | #define PMU_TX_READ_NO_INC 0 /* read address not incremented */ |
| Anna Bridge |
169:a7c7b631e539 | 235 | #define PMU_TX_READ_INC 1 /* Auto-Increment read address */ |
| Anna Bridge |
169:a7c7b631e539 | 236 | |
| Anna Bridge |
169:a7c7b631e539 | 237 | #define PMU_TX_WRITE_8_BIT 0 /* Write Size = 8 */ |
| Anna Bridge |
169:a7c7b631e539 | 238 | #define PMU_TX_WRITE_16_BIT 1 /* Write Size = 16 */ |
| Anna Bridge |
169:a7c7b631e539 | 239 | #define PMU_TX_WRITE_32_BIT 2 /* Write Size = 32 */ |
| Anna Bridge |
169:a7c7b631e539 | 240 | |
| Anna Bridge |
169:a7c7b631e539 | 241 | #define PMU_TX_WRITE_NO_INC 0 /* Write address not incremented */ |
| Anna Bridge |
169:a7c7b631e539 | 242 | #define PMU_TX_WRITE_INC 1 /* Auto_Increment write address */ |
| Anna Bridge |
169:a7c7b631e539 | 243 | |
| Anna Bridge |
169:a7c7b631e539 | 244 | /* TRANSFER bit positions */ |
| Anna Bridge |
169:a7c7b631e539 | 245 | #define PMU_TX_READS_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 246 | #define PMU_TX_READI_POS 7 |
| Anna Bridge |
169:a7c7b631e539 | 247 | #define PMU_TX_WRITES_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 248 | #define PMU_TX_WRITEI_POS 10 |
| Anna Bridge |
169:a7c7b631e539 | 249 | #define PMU_TX_LEN_POS 12 |
| Anna Bridge |
169:a7c7b631e539 | 250 | #define PMU_TX_BS_POS 26 |
| Anna Bridge |
169:a7c7b631e539 | 251 | |
| Anna Bridge |
169:a7c7b631e539 | 252 | /* PMU interrupt sources for the WAIT opcode */ |
| Anna Bridge |
169:a7c7b631e539 | 253 | #define PMU_WAIT_IRQ_MASK1_SEL0_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0)) |
| Anna Bridge |
169:a7c7b631e539 | 254 | #define PMU_WAIT_IRQ_MASK1_SEL0_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1)) |
| Anna Bridge |
169:a7c7b631e539 | 255 | #define PMU_WAIT_IRQ_MASK1_SEL0_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2)) |
| Anna Bridge |
169:a7c7b631e539 | 256 | #define PMU_WAIT_IRQ_MASK1_SEL0_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3)) |
| Anna Bridge |
169:a7c7b631e539 | 257 | #define PMU_WAIT_IRQ_MASK1_SEL0_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4)) |
| Anna Bridge |
169:a7c7b631e539 | 258 | #define PMU_WAIT_IRQ_MASK1_SEL0_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5)) |
| Anna Bridge |
169:a7c7b631e539 | 259 | #define PMU_WAIT_IRQ_MASK1_SEL0_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6)) |
| Anna Bridge |
169:a7c7b631e539 | 260 | #define PMU_WAIT_IRQ_MASK1_SEL0_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7)) |
| Anna Bridge |
169:a7c7b631e539 | 261 | #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8)) |
| Anna Bridge |
169:a7c7b631e539 | 262 | #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9)) |
| Anna Bridge |
169:a7c7b631e539 | 263 | #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10)) |
| Anna Bridge |
169:a7c7b631e539 | 264 | #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11)) |
| Anna Bridge |
169:a7c7b631e539 | 265 | #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12)) |
| Anna Bridge |
169:a7c7b631e539 | 266 | #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13)) |
| Anna Bridge |
169:a7c7b631e539 | 267 | #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14)) |
| Anna Bridge |
169:a7c7b631e539 | 268 | #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15)) |
| Anna Bridge |
169:a7c7b631e539 | 269 | #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 16)) |
| Anna Bridge |
169:a7c7b631e539 | 270 | #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 17)) |
| Anna Bridge |
169:a7c7b631e539 | 271 | #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 18)) |
| Anna Bridge |
169:a7c7b631e539 | 272 | #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 19)) |
| Anna Bridge |
169:a7c7b631e539 | 273 | #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_RX_STALLED ((uint32_t)(0x00000001UL << 20)) |
| Anna Bridge |
169:a7c7b631e539 | 274 | #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_RX_STALLED ((uint32_t)(0x00000001UL << 21)) |
| Anna Bridge |
169:a7c7b631e539 | 275 | #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_RX_STALLED ((uint32_t)(0x00000001UL << 22)) |
| Anna Bridge |
169:a7c7b631e539 | 276 | #define PMU_WAIT_IRQ_MASK1_SEL0_SPIB ((uint32_t)(0x00000001UL << 23)) |
| Anna Bridge |
169:a7c7b631e539 | 277 | #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_DONE ((uint32_t)(0x00000001UL << 24)) |
| Anna Bridge |
169:a7c7b631e539 | 278 | #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_DONE ((uint32_t)(0x00000001UL << 25)) |
| Anna Bridge |
169:a7c7b631e539 | 279 | #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_DONE ((uint32_t)(0x00000001UL << 26)) |
| Anna Bridge |
169:a7c7b631e539 | 280 | #define PMU_WAIT_IRQ_MASK1_SEL0_I2CS ((uint32_t)(0x00000001UL << 27)) |
| Anna Bridge |
169:a7c7b631e539 | 281 | #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_DONE ((uint32_t)(0x00000001UL << 28)) |
| Anna Bridge |
169:a7c7b631e539 | 282 | #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_READY ((uint32_t)(0x00000001UL << 29)) |
| Anna Bridge |
169:a7c7b631e539 | 283 | #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_HI ((uint32_t)(0x00000001UL << 30)) |
| Anna Bridge |
169:a7c7b631e539 | 284 | #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_LOW ((uint32_t)(0x00000001UL << 31)) |
| Anna Bridge |
169:a7c7b631e539 | 285 | #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP0 ((uint32_t)(0x00000001UL << 0)) |
| Anna Bridge |
169:a7c7b631e539 | 286 | #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP1 ((uint32_t)(0x00000001UL << 1)) |
| Anna Bridge |
169:a7c7b631e539 | 287 | #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_PRESCALE ((uint32_t)(0x00000001UL << 2)) |
| Anna Bridge |
169:a7c7b631e539 | 288 | #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_OVERFLOW ((uint32_t)(0x00000001UL << 3)) |
| Anna Bridge |
169:a7c7b631e539 | 289 | #define PMU_WAIT_IRQ_MASK2_SEL0_PT0_DISABLED ((uint32_t)(0x00000001UL << 4)) |
| Anna Bridge |
169:a7c7b631e539 | 290 | #define PMU_WAIT_IRQ_MASK2_SEL0_PT1_DISABLED ((uint32_t)(0x00000001UL << 5)) |
| Anna Bridge |
169:a7c7b631e539 | 291 | #define PMU_WAIT_IRQ_MASK2_SEL0_PT2_DISABLED ((uint32_t)(0x00000001UL << 6)) |
| Anna Bridge |
169:a7c7b631e539 | 292 | #define PMU_WAIT_IRQ_MASK2_SEL0_PT3_DISABLED ((uint32_t)(0x00000001UL << 7)) |
| Anna Bridge |
169:a7c7b631e539 | 293 | #define PMU_WAIT_IRQ_MASK2_SEL0_PT4_DISABLED ((uint32_t)(0x00000001UL << 8)) |
| Anna Bridge |
169:a7c7b631e539 | 294 | #define PMU_WAIT_IRQ_MASK2_SEL0_PT5_DISABLED ((uint32_t)(0x00000001UL << 9)) |
| Anna Bridge |
169:a7c7b631e539 | 295 | #define PMU_WAIT_IRQ_MASK2_SEL0_PT6_DISABLED ((uint32_t)(0x00000001UL << 10)) |
| Anna Bridge |
169:a7c7b631e539 | 296 | #define PMU_WAIT_IRQ_MASK2_SEL0_PT7_DISABLED ((uint32_t)(0x00000001UL << 11)) |
| Anna Bridge |
169:a7c7b631e539 | 297 | #define PMU_WAIT_IRQ_MASK2_SEL0_PT8_DISABLED ((uint32_t)(0x00000001UL << 12)) |
| Anna Bridge |
169:a7c7b631e539 | 298 | #define PMU_WAIT_IRQ_MASK2_SEL0_PT9_DISABLED ((uint32_t)(0x00000001UL << 13)) |
| Anna Bridge |
169:a7c7b631e539 | 299 | #define PMU_WAIT_IRQ_MASK2_SEL0_PT10_DISABLED ((uint32_t)(0x00000001UL << 14)) |
| Anna Bridge |
169:a7c7b631e539 | 300 | #define PMU_WAIT_IRQ_MASK2_SEL0_PT11_DISABLED ((uint32_t)(0x00000001UL << 15)) |
| Anna Bridge |
169:a7c7b631e539 | 301 | #define PMU_WAIT_IRQ_MASK2_SEL0_TMR0 ((uint32_t)(0x00000001UL << 16)) |
| Anna Bridge |
169:a7c7b631e539 | 302 | #define PMU_WAIT_IRQ_MASK2_SEL0_TMR1 ((uint32_t)(0x00000001UL << 17)) |
| Anna Bridge |
169:a7c7b631e539 | 303 | #define PMU_WAIT_IRQ_MASK2_SEL0_TMR2 ((uint32_t)(0x00000001UL << 18)) |
| Anna Bridge |
169:a7c7b631e539 | 304 | #define PMU_WAIT_IRQ_MASK2_SEL0_TMR3 ((uint32_t)(0x00000001UL << 19)) |
| Anna Bridge |
169:a7c7b631e539 | 305 | #define PMU_WAIT_IRQ_MASK2_SEL0_TMR4 ((uint32_t)(0x00000001UL << 20)) |
| Anna Bridge |
169:a7c7b631e539 | 306 | #define PMU_WAIT_IRQ_MASK2_SEL0_TMR5 ((uint32_t)(0x00000001UL << 21)) |
| Anna Bridge |
169:a7c7b631e539 | 307 | #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO0 ((uint32_t)(0x00000001UL << 22)) |
| Anna Bridge |
169:a7c7b631e539 | 308 | #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO1 ((uint32_t)(0x00000001UL << 23)) |
| Anna Bridge |
169:a7c7b631e539 | 309 | #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO2 ((uint32_t)(0x00000001UL << 24)) |
| Anna Bridge |
169:a7c7b631e539 | 310 | #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO3 ((uint32_t)(0x00000001UL << 25)) |
| Anna Bridge |
169:a7c7b631e539 | 311 | #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO4 ((uint32_t)(0x00000001UL << 26)) |
| Anna Bridge |
169:a7c7b631e539 | 312 | #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO5 ((uint32_t)(0x00000001UL << 27)) |
| Anna Bridge |
169:a7c7b631e539 | 313 | #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO6 ((uint32_t)(0x00000001UL << 28)) |
| Anna Bridge |
169:a7c7b631e539 | 314 | #define PMU_WAIT_IRQ_MASK2_SEL0_AES ((uint32_t)(0x00000001UL << 29)) |
| Anna Bridge |
169:a7c7b631e539 | 315 | #define PMU_WAIT_IRQ_MASK2_SEL0_MAA_DONE ((uint32_t)(0x00000001UL << 30)) |
| Anna Bridge |
169:a7c7b631e539 | 316 | #define PMU_WAIT_IRQ_MASK2_SEL0_OWM ((uint32_t)(0x00000001UL << 31)) |
| Anna Bridge |
169:a7c7b631e539 | 317 | #define PMU_WAIT_IRQ_MASK1_SEL1_GPIO7 ((uint32_t)(0x00000001UL << 0)) |
| Anna Bridge |
169:a7c7b631e539 | 318 | #define PMU_WAIT_IRQ_MASK1_SEL1_GPIO8 ((uint32_t)(0x00000001UL << 1)) |
| Anna Bridge |
169:a7c7b631e539 | 319 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT12_DISABLED ((uint32_t)(0x00000001UL << 2)) |
| Anna Bridge |
169:a7c7b631e539 | 320 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT13_DISABLED ((uint32_t)(0x00000001UL << 3)) |
| Anna Bridge |
169:a7c7b631e539 | 321 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT14_DISABLED ((uint32_t)(0x00000001UL << 4)) |
| Anna Bridge |
169:a7c7b631e539 | 322 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT15_DISABLED ((uint32_t)(0x00000001UL << 5)) |
| Anna Bridge |
169:a7c7b631e539 | 323 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT0_INT ((uint32_t)(0x00000001UL << 6)) |
| Anna Bridge |
169:a7c7b631e539 | 324 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT1_INT ((uint32_t)(0x00000001UL << 7)) |
| Anna Bridge |
169:a7c7b631e539 | 325 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT2_INT ((uint32_t)(0x00000001UL << 8)) |
| Anna Bridge |
169:a7c7b631e539 | 326 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT3_INT ((uint32_t)(0x00000001UL << 9)) |
| Anna Bridge |
169:a7c7b631e539 | 327 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT4_INT ((uint32_t)(0x00000001UL << 10)) |
| Anna Bridge |
169:a7c7b631e539 | 328 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT5_INT ((uint32_t)(0x00000001UL << 11)) |
| Anna Bridge |
169:a7c7b631e539 | 329 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT6_INT ((uint32_t)(0x00000001UL << 12)) |
| Anna Bridge |
169:a7c7b631e539 | 330 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT7_INT ((uint32_t)(0x00000001UL << 13)) |
| Anna Bridge |
169:a7c7b631e539 | 331 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT8_INT ((uint32_t)(0x00000001UL << 14)) |
| Anna Bridge |
169:a7c7b631e539 | 332 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT9_INT ((uint32_t)(0x00000001UL << 15)) |
| Anna Bridge |
169:a7c7b631e539 | 333 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT10_INT ((uint32_t)(0x00000001UL << 16)) |
| Anna Bridge |
169:a7c7b631e539 | 334 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT11_INT ((uint32_t)(0x00000001UL << 17)) |
| Anna Bridge |
169:a7c7b631e539 | 335 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT12_INT ((uint32_t)(0x00000001UL << 18)) |
| Anna Bridge |
169:a7c7b631e539 | 336 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT13_INT ((uint32_t)(0x00000001UL << 19)) |
| Anna Bridge |
169:a7c7b631e539 | 337 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT14_INT ((uint32_t)(0x00000001UL << 20)) |
| Anna Bridge |
169:a7c7b631e539 | 338 | #define PMU_WAIT_IRQ_MASK1_SEL1_PT15_INT ((uint32_t)(0x00000001UL << 21)) |
| Anna Bridge |
169:a7c7b631e539 | 339 | #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 22)) |
| Anna Bridge |
169:a7c7b631e539 | 340 | #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 23)) |
| Anna Bridge |
169:a7c7b631e539 | 341 | #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_NO_DATA ((uint32_t)(0x00000001UL << 24)) |
| Anna Bridge |
169:a7c7b631e539 | 342 | #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_DATA_LOST ((uint32_t)(0x00000001UL << 25)) |
| Anna Bridge |
169:a7c7b631e539 | 343 | #define PMU_WAIT_IRQ_MASK1_SEL1_SPI0_TX_READY ((uint32_t)(0x00000001UL << 26)) |
| Anna Bridge |
169:a7c7b631e539 | 344 | #define PMU_WAIT_IRQ_MASK1_SEL1_SPI1_TX_READY ((uint32_t)(0x00000001UL << 27)) |
| Anna Bridge |
169:a7c7b631e539 | 345 | #define PMU_WAIT_IRQ_MASK1_SEL1_SPI2_TX_READY ((uint32_t)(0x00000001UL << 28)) |
| Anna Bridge |
169:a7c7b631e539 | 346 | #define PMU_WAIT_IRQ_MASK1_SEL1_UART0_TX_DONE ((uint32_t)(0x00000001UL << 29)) |
| Anna Bridge |
169:a7c7b631e539 | 347 | #define PMU_WAIT_IRQ_MASK1_SEL1_UART1_TX_DONE ((uint32_t)(0x00000001UL << 30)) |
| Anna Bridge |
169:a7c7b631e539 | 348 | #define PMU_WAIT_IRQ_MASK1_SEL1_UART2_TX_DONE ((uint32_t)(0x00000001UL << 31)) |
| Anna Bridge |
169:a7c7b631e539 | 349 | #define PMU_WAIT_IRQ_MASK2_SEL1_UART3_TX_DONE ((uint32_t)(0x00000001UL << 0)) |
| Anna Bridge |
169:a7c7b631e539 | 350 | #define PMU_WAIT_IRQ_MASK2_SEL1_UART0_RX_DATA_READY ((uint32_t)(0x00000001UL << 1)) |
| Anna Bridge |
169:a7c7b631e539 | 351 | #define PMU_WAIT_IRQ_MASK2_SEL1_UART1_RX_DATA_READY ((uint32_t)(0x00000001UL << 2)) |
| Anna Bridge |
169:a7c7b631e539 | 352 | #define PMU_WAIT_IRQ_MASK2_SEL1_UART2_RX_DATA_READY ((uint32_t)(0x00000001UL << 3)) |
| Anna Bridge |
169:a7c7b631e539 | 353 | #define PMU_WAIT_IRQ_MASK2_SEL1_UART3_RX_DATA_READY ((uint32_t)(0x00000001UL << 4)) |
| Anna Bridge |
169:a7c7b631e539 | 354 | |
| Anna Bridge |
169:a7c7b631e539 | 355 | /* PMU interrupt sources for the TRANSFER opcode */ |
| Anna Bridge |
169:a7c7b631e539 | 356 | #define PMU_TRANSFER_IRQ_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0)) |
| Anna Bridge |
169:a7c7b631e539 | 357 | #define PMU_TRANSFER_IRQ_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1)) |
| Anna Bridge |
169:a7c7b631e539 | 358 | #define PMU_TRANSFER_IRQ_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2)) |
| Anna Bridge |
169:a7c7b631e539 | 359 | #define PMU_TRANSFER_IRQ_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3)) |
| Anna Bridge |
169:a7c7b631e539 | 360 | #define PMU_TRANSFER_IRQ_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4)) |
| Anna Bridge |
169:a7c7b631e539 | 361 | #define PMU_TRANSFER_IRQ_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5)) |
| Anna Bridge |
169:a7c7b631e539 | 362 | #define PMU_TRANSFER_IRQ_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6)) |
| Anna Bridge |
169:a7c7b631e539 | 363 | #define PMU_TRANSFER_IRQ_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7)) |
| Anna Bridge |
169:a7c7b631e539 | 364 | #define PMU_TRANSFER_IRQ_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8)) |
| Anna Bridge |
169:a7c7b631e539 | 365 | #define PMU_TRANSFER_IRQ_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9)) |
| Anna Bridge |
169:a7c7b631e539 | 366 | #define PMU_TRANSFER_IRQ_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10)) |
| Anna Bridge |
169:a7c7b631e539 | 367 | #define PMU_TRANSFER_IRQ_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11)) |
| Anna Bridge |
169:a7c7b631e539 | 368 | #define PMU_TRANSFER_IRQ_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12)) |
| Anna Bridge |
169:a7c7b631e539 | 369 | #define PMU_TRANSFER_IRQ_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13)) |
| Anna Bridge |
169:a7c7b631e539 | 370 | #define PMU_TRANSFER_IRQ_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14)) |
| Anna Bridge |
169:a7c7b631e539 | 371 | #define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15)) |
| Anna Bridge |
169:a7c7b631e539 | 372 | #define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 16)) |
| Anna Bridge |
169:a7c7b631e539 | 373 | #define PMU_TRANSFER_IRQ_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 17)) |
| Anna Bridge |
169:a7c7b631e539 | 374 | #define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 18)) |
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169:a7c7b631e539 | 375 | #define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 19)) |
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169:a7c7b631e539 | 376 | #define PMU_TRANSFER_IRQ_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 20)) |
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169:a7c7b631e539 | 377 | #define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 21)) |
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169:a7c7b631e539 | 378 | #define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 22)) |
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169:a7c7b631e539 | 379 | #define PMU_TRANSFER_IRQ_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 23)) |
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169:a7c7b631e539 | 380 | #define PMU_TRANSFER_IRQ_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 24)) |
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169:a7c7b631e539 | 381 | |
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169:a7c7b631e539 | 382 | |
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169:a7c7b631e539 | 383 | #ifdef __cplusplus |
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169:a7c7b631e539 | 384 | } |
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169:a7c7b631e539 | 385 | #endif |
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169:a7c7b631e539 | 386 | |
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169:a7c7b631e539 | 387 | #endif /* _MXC_PMU_REGS_H_ */ |
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169:a7c7b631e539 | 388 |
