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TARGET_MAX32625NEXPAQ/TOOLCHAIN_ARM_STD/spix_regs.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
169:a7c7b631e539 | 1 | /******************************************************************************* |
| Anna Bridge |
169:a7c7b631e539 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Anna Bridge |
169:a7c7b631e539 | 3 | * |
| Anna Bridge |
169:a7c7b631e539 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Anna Bridge |
169:a7c7b631e539 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Anna Bridge |
169:a7c7b631e539 | 6 | * to deal in the Software without restriction, including without limitation |
| Anna Bridge |
169:a7c7b631e539 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Anna Bridge |
169:a7c7b631e539 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Anna Bridge |
169:a7c7b631e539 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Anna Bridge |
169:a7c7b631e539 | 10 | * |
| Anna Bridge |
169:a7c7b631e539 | 11 | * The above copyright notice and this permission notice shall be included |
| Anna Bridge |
169:a7c7b631e539 | 12 | * in all copies or substantial portions of the Software. |
| Anna Bridge |
169:a7c7b631e539 | 13 | * |
| Anna Bridge |
169:a7c7b631e539 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Anna Bridge |
169:a7c7b631e539 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Anna Bridge |
169:a7c7b631e539 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Anna Bridge |
169:a7c7b631e539 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Anna Bridge |
169:a7c7b631e539 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Anna Bridge |
169:a7c7b631e539 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Anna Bridge |
169:a7c7b631e539 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Anna Bridge |
169:a7c7b631e539 | 21 | * |
| Anna Bridge |
169:a7c7b631e539 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Anna Bridge |
169:a7c7b631e539 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Anna Bridge |
169:a7c7b631e539 | 24 | * Products, Inc. Branding Policy. |
| Anna Bridge |
169:a7c7b631e539 | 25 | * |
| Anna Bridge |
169:a7c7b631e539 | 26 | * The mere transfer of this software does not imply any licenses |
| Anna Bridge |
169:a7c7b631e539 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Anna Bridge |
169:a7c7b631e539 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Anna Bridge |
169:a7c7b631e539 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Anna Bridge |
169:a7c7b631e539 | 30 | * ownership rights. |
| Anna Bridge |
169:a7c7b631e539 | 31 | ******************************************************************************/ |
| Anna Bridge |
169:a7c7b631e539 | 32 | |
| Anna Bridge |
169:a7c7b631e539 | 33 | #ifndef _MXC_SPIX_REGS_H_ |
| Anna Bridge |
169:a7c7b631e539 | 34 | #define _MXC_SPIX_REGS_H_ |
| Anna Bridge |
169:a7c7b631e539 | 35 | |
| Anna Bridge |
169:a7c7b631e539 | 36 | #ifdef __cplusplus |
| Anna Bridge |
169:a7c7b631e539 | 37 | extern "C" { |
| Anna Bridge |
169:a7c7b631e539 | 38 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 39 | |
| Anna Bridge |
169:a7c7b631e539 | 40 | #include <stdint.h> |
| Anna Bridge |
169:a7c7b631e539 | 41 | #include "mxc_device.h" |
| Anna Bridge |
169:a7c7b631e539 | 42 | |
| Anna Bridge |
169:a7c7b631e539 | 43 | /* |
| Anna Bridge |
169:a7c7b631e539 | 44 | If types are not defined elsewhere (CMSIS) define them here |
| Anna Bridge |
169:a7c7b631e539 | 45 | */ |
| Anna Bridge |
169:a7c7b631e539 | 46 | #ifndef __IO |
| Anna Bridge |
169:a7c7b631e539 | 47 | #define __IO volatile |
| Anna Bridge |
169:a7c7b631e539 | 48 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 49 | #ifndef __I |
| Anna Bridge |
169:a7c7b631e539 | 50 | #define __I volatile const |
| Anna Bridge |
169:a7c7b631e539 | 51 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 52 | #ifndef __O |
| Anna Bridge |
169:a7c7b631e539 | 53 | #define __O volatile |
| Anna Bridge |
169:a7c7b631e539 | 54 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 55 | |
| Anna Bridge |
169:a7c7b631e539 | 56 | |
| Anna Bridge |
169:a7c7b631e539 | 57 | /* |
| Anna Bridge |
169:a7c7b631e539 | 58 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| Anna Bridge |
169:a7c7b631e539 | 59 | access to each register in module. |
| Anna Bridge |
169:a7c7b631e539 | 60 | */ |
| Anna Bridge |
169:a7c7b631e539 | 61 | |
| Anna Bridge |
169:a7c7b631e539 | 62 | /* Offset Register Description |
| Anna Bridge |
169:a7c7b631e539 | 63 | ============= ============================================================================ */ |
| Anna Bridge |
169:a7c7b631e539 | 64 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 65 | __IO uint32_t master_cfg; /* 0x0000 SPIX Master Configuration */ |
| Anna Bridge |
169:a7c7b631e539 | 66 | __IO uint32_t fetch_ctrl; /* 0x0004 SPIX Fetch Control */ |
| Anna Bridge |
169:a7c7b631e539 | 67 | __IO uint32_t mode_ctrl; /* 0x0008 SPIX Mode Control */ |
| Anna Bridge |
169:a7c7b631e539 | 68 | __IO uint32_t mode_data; /* 0x000C SPIX Mode Data */ |
| Anna Bridge |
169:a7c7b631e539 | 69 | __IO uint32_t sck_fb_ctrl; /* 0x0010 SPIX SCK_FB Control Register */ |
| Anna Bridge |
169:a7c7b631e539 | 70 | } mxc_spix_regs_t; |
| Anna Bridge |
169:a7c7b631e539 | 71 | |
| Anna Bridge |
169:a7c7b631e539 | 72 | |
| Anna Bridge |
169:a7c7b631e539 | 73 | /* |
| Anna Bridge |
169:a7c7b631e539 | 74 | Register offsets for module SPIX. |
| Anna Bridge |
169:a7c7b631e539 | 75 | */ |
| Anna Bridge |
169:a7c7b631e539 | 76 | |
| Anna Bridge |
169:a7c7b631e539 | 77 | #define MXC_R_SPIX_OFFS_MASTER_CFG ((uint32_t)0x00000000UL) |
| Anna Bridge |
169:a7c7b631e539 | 78 | #define MXC_R_SPIX_OFFS_FETCH_CTRL ((uint32_t)0x00000004UL) |
| Anna Bridge |
169:a7c7b631e539 | 79 | #define MXC_R_SPIX_OFFS_MODE_CTRL ((uint32_t)0x00000008UL) |
| Anna Bridge |
169:a7c7b631e539 | 80 | #define MXC_R_SPIX_OFFS_MODE_DATA ((uint32_t)0x0000000CUL) |
| Anna Bridge |
169:a7c7b631e539 | 81 | #define MXC_R_SPIX_OFFS_SCK_FB_CTRL ((uint32_t)0x00000010UL) |
| Anna Bridge |
169:a7c7b631e539 | 82 | |
| Anna Bridge |
169:a7c7b631e539 | 83 | |
| Anna Bridge |
169:a7c7b631e539 | 84 | /* |
| Anna Bridge |
169:a7c7b631e539 | 85 | Field positions and masks for module SPIX. |
| Anna Bridge |
169:a7c7b631e539 | 86 | */ |
| Anna Bridge |
169:a7c7b631e539 | 87 | |
| Anna Bridge |
169:a7c7b631e539 | 88 | #define MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 89 | #define MXC_F_SPIX_MASTER_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 90 | #define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 91 | #define MXC_F_SPIX_MASTER_CFG_SS_ACT_LO ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 92 | #define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS 3 |
| Anna Bridge |
169:a7c7b631e539 | 93 | #define MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN ((uint32_t)(0x00000001UL << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 94 | #define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 95 | #define MXC_F_SPIX_MASTER_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIX_MASTER_CFG_SLAVE_SEL_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 96 | #define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 97 | #define MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_LO_CLK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 98 | #define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS 12 |
| Anna Bridge |
169:a7c7b631e539 | 99 | #define MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SCK_HI_CLK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 100 | #define MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 101 | #define MXC_F_SPIX_MASTER_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 102 | #define MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS 18 |
| Anna Bridge |
169:a7c7b631e539 | 103 | #define MXC_F_SPIX_MASTER_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 104 | #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS 20 |
| Anna Bridge |
169:a7c7b631e539 | 105 | #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_LO_CLK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 106 | #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 107 | #define MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_ALT_SCK_HI_CLK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 108 | #define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS 28 |
| Anna Bridge |
169:a7c7b631e539 | 109 | #define MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MASTER_CFG_SDIO_SAMPLE_POINT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 110 | |
| Anna Bridge |
169:a7c7b631e539 | 111 | #define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 112 | #define MXC_F_SPIX_FETCH_CTRL_CMD_VALUE ((uint32_t)(0x000000FFUL << MXC_F_SPIX_FETCH_CTRL_CMD_VALUE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 113 | #define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 114 | #define MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 115 | #define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS 10 |
| Anna Bridge |
169:a7c7b631e539 | 116 | #define MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 117 | #define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS 12 |
| Anna Bridge |
169:a7c7b631e539 | 118 | #define MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 119 | #define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 120 | #define MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR ((uint32_t)(0x00000001UL << MXC_F_SPIX_FETCH_CTRL_FOUR_BYTE_ADDR_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 121 | |
| Anna Bridge |
169:a7c7b631e539 | 122 | #define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 123 | #define MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS ((uint32_t)(0x0000000FUL << MXC_F_SPIX_MODE_CTRL_MODE_CLOCKS_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 124 | #define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 125 | #define MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_MODE_CTRL_NO_CMD_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 126 | |
| Anna Bridge |
169:a7c7b631e539 | 127 | #define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 128 | #define MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_BITS_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 129 | #define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 130 | #define MXC_F_SPIX_MODE_DATA_MODE_DATA_OE ((uint32_t)(0x0000FFFFUL << MXC_F_SPIX_MODE_DATA_MODE_DATA_OE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 131 | |
| Anna Bridge |
169:a7c7b631e539 | 132 | #define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 133 | #define MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_ENABLE_SCK_FB_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 134 | #define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS 1 |
| Anna Bridge |
169:a7c7b631e539 | 135 | #define MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIX_SCK_FB_CTRL_INVERT_SCK_FB_CLK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 136 | |
| Anna Bridge |
169:a7c7b631e539 | 137 | #if(MXC_SPIX_REV == 0) |
| Anna Bridge |
169:a7c7b631e539 | 138 | #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 139 | #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 140 | #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS 12 |
| Anna Bridge |
169:a7c7b631e539 | 141 | #define MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD ((uint32_t)(0x0000003FUL << MXC_F_SPIX_SCK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 142 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 143 | |
| Anna Bridge |
169:a7c7b631e539 | 144 | |
| Anna Bridge |
169:a7c7b631e539 | 145 | /* |
| Anna Bridge |
169:a7c7b631e539 | 146 | Field values and shifted values for module SPIX. |
| Anna Bridge |
169:a7c7b631e539 | 147 | */ |
| Anna Bridge |
169:a7c7b631e539 | 148 | |
| Anna Bridge |
169:a7c7b631e539 | 149 | #define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(0x00000000UL)) |
| Anna Bridge |
169:a7c7b631e539 | 150 | #define MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(0x00000003UL)) |
| Anna Bridge |
169:a7c7b631e539 | 151 | |
| Anna Bridge |
169:a7c7b631e539 | 152 | #define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_HI_SAMPLE_RISING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 153 | #define MXC_S_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SPI_MODE_SCK_LO_SAMPLE_FALLING << MXC_F_SPIX_MASTER_CFG_SPI_MODE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 154 | |
| Anna Bridge |
169:a7c7b631e539 | 155 | #define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(0x00000000UL)) |
| Anna Bridge |
169:a7c7b631e539 | 156 | #define MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(0x00000001UL)) |
| Anna Bridge |
169:a7c7b631e539 | 157 | |
| Anna Bridge |
169:a7c7b631e539 | 158 | #define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_HIGH << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 159 | #define MXC_S_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW ((uint32_t)(MXC_V_SPIX_MASTER_CFG_SS_ACT_LO_ACTIVE_LOW << MXC_F_SPIX_MASTER_CFG_SS_ACT_LO_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 160 | |
| Anna Bridge |
169:a7c7b631e539 | 161 | #define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(0x00000000UL)) |
| Anna Bridge |
169:a7c7b631e539 | 162 | #define MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(0x00000001UL)) |
| Anna Bridge |
169:a7c7b631e539 | 163 | |
| Anna Bridge |
169:a7c7b631e539 | 164 | #define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_DISABLED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 165 | #define MXC_S_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ALT_TIMING_EN_ENABLED_AS_NEEDED << MXC_F_SPIX_MASTER_CFG_ALT_TIMING_EN_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 166 | |
| Anna Bridge |
169:a7c7b631e539 | 167 | #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(0x00000000UL)) |
| Anna Bridge |
169:a7c7b631e539 | 168 | #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) |
| Anna Bridge |
169:a7c7b631e539 | 169 | #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) |
| Anna Bridge |
169:a7c7b631e539 | 170 | #define MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) |
| Anna Bridge |
169:a7c7b631e539 | 171 | |
| Anna Bridge |
169:a7c7b631e539 | 172 | #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 173 | #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 174 | #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 175 | #define MXC_S_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_ACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_ACT_DELAY_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 176 | |
| Anna Bridge |
169:a7c7b631e539 | 177 | #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(0x00000000UL)) |
| Anna Bridge |
169:a7c7b631e539 | 178 | #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(0x00000001UL)) |
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169:a7c7b631e539 | 179 | #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(0x00000002UL)) |
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169:a7c7b631e539 | 180 | #define MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(0x00000003UL)) |
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169:a7c7b631e539 | 181 | |
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169:a7c7b631e539 | 182 | #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_OFF ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_OFF << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) |
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169:a7c7b631e539 | 183 | #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_2_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) |
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169:a7c7b631e539 | 184 | #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_4_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) |
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169:a7c7b631e539 | 185 | #define MXC_S_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK ((uint32_t)(MXC_V_SPIX_MASTER_CFG_INACT_DELAY_FOR_8_MOD_CLK << MXC_F_SPIX_MASTER_CFG_INACT_DELAY_POS)) |
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169:a7c7b631e539 | 186 | |
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169:a7c7b631e539 | 187 | #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) |
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169:a7c7b631e539 | 188 | #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) |
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169:a7c7b631e539 | 189 | #define MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) |
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169:a7c7b631e539 | 190 | |
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169:a7c7b631e539 | 191 | #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) |
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169:a7c7b631e539 | 192 | #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) |
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169:a7c7b631e539 | 193 | #define MXC_S_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_CMD_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_CMD_WIDTH_POS)) |
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169:a7c7b631e539 | 194 | |
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169:a7c7b631e539 | 195 | #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) |
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169:a7c7b631e539 | 196 | #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) |
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169:a7c7b631e539 | 197 | #define MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) |
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169:a7c7b631e539 | 198 | |
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169:a7c7b631e539 | 199 | #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) |
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169:a7c7b631e539 | 200 | #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) |
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169:a7c7b631e539 | 201 | #define MXC_S_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_ADDR_WIDTH_POS)) |
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169:a7c7b631e539 | 202 | |
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169:a7c7b631e539 | 203 | #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(0x00000000UL)) |
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169:a7c7b631e539 | 204 | #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(0x00000001UL)) |
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169:a7c7b631e539 | 205 | #define MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(0x00000002UL)) |
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169:a7c7b631e539 | 206 | |
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169:a7c7b631e539 | 207 | #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) |
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169:a7c7b631e539 | 208 | #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) |
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169:a7c7b631e539 | 209 | #define MXC_S_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)(MXC_V_SPIX_FETCH_CTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIX_FETCH_CTRL_DATA_WIDTH_POS)) |
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169:a7c7b631e539 | 210 | |
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169:a7c7b631e539 | 211 | |
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169:a7c7b631e539 | 212 | |
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169:a7c7b631e539 | 213 | #ifdef __cplusplus |
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169:a7c7b631e539 | 214 | } |
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169:a7c7b631e539 | 215 | #endif |
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169:a7c7b631e539 | 216 | |
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169:a7c7b631e539 | 217 | #endif /* _MXC_SPIX_REGS_H_ */ |
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169:a7c7b631e539 | 218 |
