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TARGET_MAX32625NEXPAQ/TOOLCHAIN_ARM_STD/i2cm_regs.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
169:a7c7b631e539 | 1 | /******************************************************************************* |
| Anna Bridge |
169:a7c7b631e539 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Anna Bridge |
169:a7c7b631e539 | 3 | * |
| Anna Bridge |
169:a7c7b631e539 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Anna Bridge |
169:a7c7b631e539 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Anna Bridge |
169:a7c7b631e539 | 6 | * to deal in the Software without restriction, including without limitation |
| Anna Bridge |
169:a7c7b631e539 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Anna Bridge |
169:a7c7b631e539 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Anna Bridge |
169:a7c7b631e539 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Anna Bridge |
169:a7c7b631e539 | 10 | * |
| Anna Bridge |
169:a7c7b631e539 | 11 | * The above copyright notice and this permission notice shall be included |
| Anna Bridge |
169:a7c7b631e539 | 12 | * in all copies or substantial portions of the Software. |
| Anna Bridge |
169:a7c7b631e539 | 13 | * |
| Anna Bridge |
169:a7c7b631e539 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Anna Bridge |
169:a7c7b631e539 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Anna Bridge |
169:a7c7b631e539 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Anna Bridge |
169:a7c7b631e539 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Anna Bridge |
169:a7c7b631e539 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Anna Bridge |
169:a7c7b631e539 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Anna Bridge |
169:a7c7b631e539 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Anna Bridge |
169:a7c7b631e539 | 21 | * |
| Anna Bridge |
169:a7c7b631e539 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Anna Bridge |
169:a7c7b631e539 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Anna Bridge |
169:a7c7b631e539 | 24 | * Products, Inc. Branding Policy. |
| Anna Bridge |
169:a7c7b631e539 | 25 | * |
| Anna Bridge |
169:a7c7b631e539 | 26 | * The mere transfer of this software does not imply any licenses |
| Anna Bridge |
169:a7c7b631e539 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Anna Bridge |
169:a7c7b631e539 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Anna Bridge |
169:a7c7b631e539 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Anna Bridge |
169:a7c7b631e539 | 30 | * ownership rights. |
| Anna Bridge |
169:a7c7b631e539 | 31 | ******************************************************************************/ |
| Anna Bridge |
169:a7c7b631e539 | 32 | |
| Anna Bridge |
169:a7c7b631e539 | 33 | #ifndef _MXC_I2CM_REGS_H_ |
| Anna Bridge |
169:a7c7b631e539 | 34 | #define _MXC_I2CM_REGS_H_ |
| Anna Bridge |
169:a7c7b631e539 | 35 | |
| Anna Bridge |
169:a7c7b631e539 | 36 | #ifdef __cplusplus |
| Anna Bridge |
169:a7c7b631e539 | 37 | extern "C" { |
| Anna Bridge |
169:a7c7b631e539 | 38 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 39 | |
| Anna Bridge |
169:a7c7b631e539 | 40 | #include <stdint.h> |
| Anna Bridge |
169:a7c7b631e539 | 41 | #include "mxc_device.h" |
| Anna Bridge |
169:a7c7b631e539 | 42 | |
| Anna Bridge |
169:a7c7b631e539 | 43 | /* |
| Anna Bridge |
169:a7c7b631e539 | 44 | If types are not defined elsewhere (CMSIS) define them here |
| Anna Bridge |
169:a7c7b631e539 | 45 | */ |
| Anna Bridge |
169:a7c7b631e539 | 46 | #ifndef __IO |
| Anna Bridge |
169:a7c7b631e539 | 47 | #define __IO volatile |
| Anna Bridge |
169:a7c7b631e539 | 48 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 49 | #ifndef __I |
| Anna Bridge |
169:a7c7b631e539 | 50 | #define __I volatile const |
| Anna Bridge |
169:a7c7b631e539 | 51 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 52 | #ifndef __O |
| Anna Bridge |
169:a7c7b631e539 | 53 | #define __O volatile |
| Anna Bridge |
169:a7c7b631e539 | 54 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 55 | |
| Anna Bridge |
169:a7c7b631e539 | 56 | |
| Anna Bridge |
169:a7c7b631e539 | 57 | #define MXC_S_I2CM_TRANS_TAG_START 0x000 |
| Anna Bridge |
169:a7c7b631e539 | 58 | #define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100 |
| Anna Bridge |
169:a7c7b631e539 | 59 | #define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200 |
| Anna Bridge |
169:a7c7b631e539 | 60 | #define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400 |
| Anna Bridge |
169:a7c7b631e539 | 61 | #define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500 |
| Anna Bridge |
169:a7c7b631e539 | 62 | #define MXC_S_I2CM_TRANS_TAG_STOP 0x700 |
| Anna Bridge |
169:a7c7b631e539 | 63 | #define MXC_S_I2CM_RSTLS_TAG_DATA 0x100 |
| Anna Bridge |
169:a7c7b631e539 | 64 | #define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200 |
| Anna Bridge |
169:a7c7b631e539 | 65 | |
| Anna Bridge |
169:a7c7b631e539 | 66 | /* |
| Anna Bridge |
169:a7c7b631e539 | 67 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| Anna Bridge |
169:a7c7b631e539 | 68 | access to each register in module. |
| Anna Bridge |
169:a7c7b631e539 | 69 | */ |
| Anna Bridge |
169:a7c7b631e539 | 70 | |
| Anna Bridge |
169:a7c7b631e539 | 71 | /* Offset Register Description |
| Anna Bridge |
169:a7c7b631e539 | 72 | ============= ============================================================================ */ |
| Anna Bridge |
169:a7c7b631e539 | 73 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 74 | __IO uint32_t fs_clk_div; /* 0x0000 I2C Master Full Speed SCL Clock Settings */ |
| Anna Bridge |
169:a7c7b631e539 | 75 | __I uint32_t rsv004[2]; /* 0x0004-0x0008 */ |
| Anna Bridge |
169:a7c7b631e539 | 76 | __IO uint32_t timeout; /* 0x000C I2C Master Timeout and Auto-Stop Settings */ |
| Anna Bridge |
169:a7c7b631e539 | 77 | __IO uint32_t ctrl; /* 0x0010 I2C Master Control Register */ |
| Anna Bridge |
169:a7c7b631e539 | 78 | __IO uint32_t trans; /* 0x0014 I2C Master Transaction Start and Status Flags */ |
| Anna Bridge |
169:a7c7b631e539 | 79 | __IO uint32_t intfl; /* 0x0018 I2C Master Interrupt Flags */ |
| Anna Bridge |
169:a7c7b631e539 | 80 | __IO uint32_t inten; /* 0x001C I2C Master Interrupt Enable/Disable Controls */ |
| Anna Bridge |
169:a7c7b631e539 | 81 | __I uint32_t rsv020[2]; /* 0x0020-0x0024 */ |
| Anna Bridge |
169:a7c7b631e539 | 82 | __IO uint32_t bb; /* 0x0028 I2C Master Bit-Bang Control Register */ |
| Anna Bridge |
169:a7c7b631e539 | 83 | } mxc_i2cm_regs_t; |
| Anna Bridge |
169:a7c7b631e539 | 84 | |
| Anna Bridge |
169:a7c7b631e539 | 85 | |
| Anna Bridge |
169:a7c7b631e539 | 86 | /* Offset Register Description |
| Anna Bridge |
169:a7c7b631e539 | 87 | ============= ============================================================================ */ |
| Anna Bridge |
169:a7c7b631e539 | 88 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 89 | union { /* 0x0000-0x07FC FIFO Write Point for Data to Transmit */ |
| Anna Bridge |
169:a7c7b631e539 | 90 | __IO uint16_t tx; |
| Anna Bridge |
169:a7c7b631e539 | 91 | __IO uint8_t tx_8[2048]; |
| Anna Bridge |
169:a7c7b631e539 | 92 | __IO uint16_t tx_16[1024]; |
| Anna Bridge |
169:a7c7b631e539 | 93 | __IO uint32_t tx_32[512]; |
| Anna Bridge |
169:a7c7b631e539 | 94 | }; |
| Anna Bridge |
169:a7c7b631e539 | 95 | union { /* 0x0800-0x0FFC FIFO Read Point for Received Data */ |
| Anna Bridge |
169:a7c7b631e539 | 96 | __IO uint16_t rx; |
| Anna Bridge |
169:a7c7b631e539 | 97 | __IO uint8_t rx_8[2048]; |
| Anna Bridge |
169:a7c7b631e539 | 98 | __IO uint16_t rx_16[1024]; |
| Anna Bridge |
169:a7c7b631e539 | 99 | __IO uint32_t rx_32[512]; |
| Anna Bridge |
169:a7c7b631e539 | 100 | }; |
| Anna Bridge |
169:a7c7b631e539 | 101 | } mxc_i2cm_fifo_regs_t; |
| Anna Bridge |
169:a7c7b631e539 | 102 | |
| Anna Bridge |
169:a7c7b631e539 | 103 | |
| Anna Bridge |
169:a7c7b631e539 | 104 | /* |
| Anna Bridge |
169:a7c7b631e539 | 105 | Register offsets for module I2CM. |
| Anna Bridge |
169:a7c7b631e539 | 106 | */ |
| Anna Bridge |
169:a7c7b631e539 | 107 | |
| Anna Bridge |
169:a7c7b631e539 | 108 | #define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL) |
| Anna Bridge |
169:a7c7b631e539 | 109 | #define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL) |
| Anna Bridge |
169:a7c7b631e539 | 110 | #define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL) |
| Anna Bridge |
169:a7c7b631e539 | 111 | #define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL) |
| Anna Bridge |
169:a7c7b631e539 | 112 | #define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL) |
| Anna Bridge |
169:a7c7b631e539 | 113 | #define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL) |
| Anna Bridge |
169:a7c7b631e539 | 114 | #define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL) |
| Anna Bridge |
169:a7c7b631e539 | 115 | #define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) |
| Anna Bridge |
169:a7c7b631e539 | 116 | #define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) |
| Anna Bridge |
169:a7c7b631e539 | 117 | |
| Anna Bridge |
169:a7c7b631e539 | 118 | |
| Anna Bridge |
169:a7c7b631e539 | 119 | /* |
| Anna Bridge |
169:a7c7b631e539 | 120 | Field positions and masks for module I2CM. |
| Anna Bridge |
169:a7c7b631e539 | 121 | */ |
| Anna Bridge |
169:a7c7b631e539 | 122 | |
| Anna Bridge |
169:a7c7b631e539 | 123 | #define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 124 | #define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 125 | #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 126 | #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 127 | #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS 20 |
| Anna Bridge |
169:a7c7b631e539 | 128 | #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 129 | |
| Anna Bridge |
169:a7c7b631e539 | 130 | #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16 |
| Anna Bridge |
169:a7c7b631e539 | 131 | #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 132 | #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24 |
| Anna Bridge |
169:a7c7b631e539 | 133 | #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 134 | |
| Anna Bridge |
169:a7c7b631e539 | 135 | #define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 136 | #define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 137 | #define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3 |
| Anna Bridge |
169:a7c7b631e539 | 138 | #define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 139 | #define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7 |
| Anna Bridge |
169:a7c7b631e539 | 140 | #define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 141 | |
| Anna Bridge |
169:a7c7b631e539 | 142 | #define MXC_F_I2CM_TRANS_TX_START_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 143 | #define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 144 | #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1 |
| Anna Bridge |
169:a7c7b631e539 | 145 | #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 146 | #define MXC_F_I2CM_TRANS_TX_DONE_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 147 | #define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 148 | #define MXC_F_I2CM_TRANS_TX_NACKED_POS 3 |
| Anna Bridge |
169:a7c7b631e539 | 149 | #define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 150 | #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 151 | #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 152 | #define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 153 | #define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 154 | |
| Anna Bridge |
169:a7c7b631e539 | 155 | #define MXC_F_I2CM_INTFL_TX_DONE_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 156 | #define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 157 | #define MXC_F_I2CM_INTFL_TX_NACKED_POS 1 |
| Anna Bridge |
169:a7c7b631e539 | 158 | #define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 159 | #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 160 | #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 161 | #define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3 |
| Anna Bridge |
169:a7c7b631e539 | 162 | #define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 163 | #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 164 | #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 165 | #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 166 | #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 167 | #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6 |
| Anna Bridge |
169:a7c7b631e539 | 168 | #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 169 | #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7 |
| Anna Bridge |
169:a7c7b631e539 | 170 | #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 171 | #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 172 | #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 173 | #define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9 |
| Anna Bridge |
169:a7c7b631e539 | 174 | #define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 175 | |
| Anna Bridge |
169:a7c7b631e539 | 176 | #define MXC_F_I2CM_INTEN_TX_DONE_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 177 | #define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 178 | #define MXC_F_I2CM_INTEN_TX_NACKED_POS 1 |
| Anna Bridge |
169:a7c7b631e539 | 179 | #define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 180 | #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 181 | #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 182 | #define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3 |
| Anna Bridge |
169:a7c7b631e539 | 183 | #define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 184 | #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 185 | #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 186 | #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5 |
| Anna Bridge |
169:a7c7b631e539 | 187 | #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 188 | #define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS 6 |
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169:a7c7b631e539 | 189 | #define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS)) |
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169:a7c7b631e539 | 190 | #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7 |
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169:a7c7b631e539 | 191 | #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS)) |
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169:a7c7b631e539 | 192 | #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8 |
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169:a7c7b631e539 | 193 | #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS)) |
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169:a7c7b631e539 | 194 | #define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9 |
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169:a7c7b631e539 | 195 | #define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS)) |
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169:a7c7b631e539 | 196 | |
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169:a7c7b631e539 | 197 | #define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0 |
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169:a7c7b631e539 | 198 | #define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS)) |
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169:a7c7b631e539 | 199 | #define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1 |
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169:a7c7b631e539 | 200 | #define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS)) |
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169:a7c7b631e539 | 201 | #define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2 |
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169:a7c7b631e539 | 202 | #define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS)) |
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169:a7c7b631e539 | 203 | #define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3 |
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169:a7c7b631e539 | 204 | #define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS)) |
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169:a7c7b631e539 | 205 | #define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16 |
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169:a7c7b631e539 | 206 | #define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS)) |
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169:a7c7b631e539 | 207 | |
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169:a7c7b631e539 | 208 | |
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169:a7c7b631e539 | 209 | |
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169:a7c7b631e539 | 210 | #ifdef __cplusplus |
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169:a7c7b631e539 | 211 | } |
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169:a7c7b631e539 | 212 | #endif |
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169:a7c7b631e539 | 213 | |
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169:a7c7b631e539 | 214 | #endif /* _MXC_I2CM_REGS_H_ */ |
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169:a7c7b631e539 | 215 |
