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TARGET_MAX32625NEXPAQ/TOOLCHAIN_ARM_STD/core_sc000.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file core_sc000.h
AnnaBridge 171:3a7713b1edbc 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
AnnaBridge 171:3a7713b1edbc 4 * @version V5.0.5
AnnaBridge 171:3a7713b1edbc 5 * @date 28. May 2018
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7 /*
AnnaBridge 171:3a7713b1edbc 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 171:3a7713b1edbc 13 * not use this file except in compliance with the License.
AnnaBridge 171:3a7713b1edbc 14 * You may obtain a copy of the License at
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 171:3a7713b1edbc 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 171:3a7713b1edbc 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 171:3a7713b1edbc 21 * See the License for the specific language governing permissions and
AnnaBridge 171:3a7713b1edbc 22 * limitations under the License.
AnnaBridge 171:3a7713b1edbc 23 */
AnnaBridge 171:3a7713b1edbc 24
AnnaBridge 171:3a7713b1edbc 25 #if defined ( __ICCARM__ )
AnnaBridge 171:3a7713b1edbc 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 171:3a7713b1edbc 27 #elif defined (__clang__)
AnnaBridge 171:3a7713b1edbc 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 171:3a7713b1edbc 29 #endif
AnnaBridge 171:3a7713b1edbc 30
AnnaBridge 171:3a7713b1edbc 31 #ifndef __CORE_SC000_H_GENERIC
AnnaBridge 171:3a7713b1edbc 32 #define __CORE_SC000_H_GENERIC
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 37 extern "C" {
AnnaBridge 171:3a7713b1edbc 38 #endif
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 /**
AnnaBridge 171:3a7713b1edbc 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 171:3a7713b1edbc 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 171:3a7713b1edbc 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 171:3a7713b1edbc 48 Unions are used for effective representation of core registers.
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 171:3a7713b1edbc 51 Function-like macros are used to allow more efficient code.
AnnaBridge 171:3a7713b1edbc 52 */
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 56 * CMSIS definitions
AnnaBridge 171:3a7713b1edbc 57 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 58 /**
AnnaBridge 171:3a7713b1edbc 59 \ingroup SC000
AnnaBridge 171:3a7713b1edbc 60 @{
AnnaBridge 171:3a7713b1edbc 61 */
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 #include "cmsis_version.h"
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 /* CMSIS SC000 definitions */
AnnaBridge 171:3a7713b1edbc 66 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
AnnaBridge 171:3a7713b1edbc 67 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 171:3a7713b1edbc 68 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 171:3a7713b1edbc 69 __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 #define __CORTEX_SC (000U) /*!< Cortex secure core */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 171:3a7713b1edbc 74 This core does not support an FPU at all
AnnaBridge 171:3a7713b1edbc 75 */
AnnaBridge 171:3a7713b1edbc 76 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 79 #if defined __TARGET_FPU_VFP
AnnaBridge 171:3a7713b1edbc 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 81 #endif
AnnaBridge 171:3a7713b1edbc 82
AnnaBridge 171:3a7713b1edbc 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 172:65be27845400 84 #if defined __ARM_FP
AnnaBridge 171:3a7713b1edbc 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 86 #endif
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 #elif defined ( __GNUC__ )
AnnaBridge 171:3a7713b1edbc 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 171:3a7713b1edbc 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 91 #endif
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 #elif defined ( __ICCARM__ )
AnnaBridge 171:3a7713b1edbc 94 #if defined __ARMVFP__
AnnaBridge 171:3a7713b1edbc 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 96 #endif
AnnaBridge 171:3a7713b1edbc 97
AnnaBridge 171:3a7713b1edbc 98 #elif defined ( __TI_ARM__ )
AnnaBridge 171:3a7713b1edbc 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 171:3a7713b1edbc 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 101 #endif
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 #elif defined ( __TASKING__ )
AnnaBridge 171:3a7713b1edbc 104 #if defined __FPU_VFP__
AnnaBridge 171:3a7713b1edbc 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 106 #endif
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 #elif defined ( __CSMC__ )
AnnaBridge 171:3a7713b1edbc 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 171:3a7713b1edbc 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 111 #endif
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 #endif
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 119 }
AnnaBridge 171:3a7713b1edbc 120 #endif
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 #endif /* __CORE_SC000_H_GENERIC */
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 #ifndef __CMSIS_GENERIC
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 #ifndef __CORE_SC000_H_DEPENDANT
AnnaBridge 171:3a7713b1edbc 127 #define __CORE_SC000_H_DEPENDANT
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 130 extern "C" {
AnnaBridge 171:3a7713b1edbc 131 #endif
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 /* check device defines and use defaults */
AnnaBridge 171:3a7713b1edbc 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 171:3a7713b1edbc 135 #ifndef __SC000_REV
AnnaBridge 171:3a7713b1edbc 136 #define __SC000_REV 0x0000U
AnnaBridge 171:3a7713b1edbc 137 #warning "__SC000_REV not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 138 #endif
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 #ifndef __MPU_PRESENT
AnnaBridge 171:3a7713b1edbc 141 #define __MPU_PRESENT 0U
AnnaBridge 171:3a7713b1edbc 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 143 #endif
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 #ifndef __NVIC_PRIO_BITS
AnnaBridge 171:3a7713b1edbc 146 #define __NVIC_PRIO_BITS 2U
AnnaBridge 171:3a7713b1edbc 147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 148 #endif
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 #ifndef __Vendor_SysTickConfig
AnnaBridge 171:3a7713b1edbc 151 #define __Vendor_SysTickConfig 0U
AnnaBridge 171:3a7713b1edbc 152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 153 #endif
AnnaBridge 171:3a7713b1edbc 154 #endif
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 171:3a7713b1edbc 157 /**
AnnaBridge 171:3a7713b1edbc 158 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 171:3a7713b1edbc 161 \li to specify the access to peripheral variables.
AnnaBridge 171:3a7713b1edbc 162 \li for automatic generation of peripheral register debug information.
AnnaBridge 171:3a7713b1edbc 163 */
AnnaBridge 171:3a7713b1edbc 164 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 165 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 171:3a7713b1edbc 166 #else
AnnaBridge 171:3a7713b1edbc 167 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 171:3a7713b1edbc 168 #endif
AnnaBridge 171:3a7713b1edbc 169 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 171:3a7713b1edbc 170 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 /* following defines should be used for structure members */
AnnaBridge 171:3a7713b1edbc 173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 171:3a7713b1edbc 174 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 171:3a7713b1edbc 175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 /*@} end of group SC000 */
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180
AnnaBridge 171:3a7713b1edbc 181 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 182 * Register Abstraction
AnnaBridge 171:3a7713b1edbc 183 Core Register contain:
AnnaBridge 171:3a7713b1edbc 184 - Core Register
AnnaBridge 171:3a7713b1edbc 185 - Core NVIC Register
AnnaBridge 171:3a7713b1edbc 186 - Core SCB Register
AnnaBridge 171:3a7713b1edbc 187 - Core SysTick Register
AnnaBridge 171:3a7713b1edbc 188 - Core MPU Register
AnnaBridge 171:3a7713b1edbc 189 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 190 /**
AnnaBridge 171:3a7713b1edbc 191 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 171:3a7713b1edbc 192 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 171:3a7713b1edbc 193 */
AnnaBridge 171:3a7713b1edbc 194
AnnaBridge 171:3a7713b1edbc 195 /**
AnnaBridge 171:3a7713b1edbc 196 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 197 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 171:3a7713b1edbc 198 \brief Core Register type definitions.
AnnaBridge 171:3a7713b1edbc 199 @{
AnnaBridge 171:3a7713b1edbc 200 */
AnnaBridge 171:3a7713b1edbc 201
AnnaBridge 171:3a7713b1edbc 202 /**
AnnaBridge 171:3a7713b1edbc 203 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 171:3a7713b1edbc 204 */
AnnaBridge 171:3a7713b1edbc 205 typedef union
AnnaBridge 171:3a7713b1edbc 206 {
AnnaBridge 171:3a7713b1edbc 207 struct
AnnaBridge 171:3a7713b1edbc 208 {
AnnaBridge 171:3a7713b1edbc 209 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 171:3a7713b1edbc 210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 171:3a7713b1edbc 211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 171:3a7713b1edbc 212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 171:3a7713b1edbc 213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 171:3a7713b1edbc 214 } b; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 215 uint32_t w; /*!< Type used for word access */
AnnaBridge 171:3a7713b1edbc 216 } APSR_Type;
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /* APSR Register Definitions */
AnnaBridge 171:3a7713b1edbc 219 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 171:3a7713b1edbc 220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 171:3a7713b1edbc 221
AnnaBridge 171:3a7713b1edbc 222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 171:3a7713b1edbc 223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 171:3a7713b1edbc 224
AnnaBridge 171:3a7713b1edbc 225 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 171:3a7713b1edbc 226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 171:3a7713b1edbc 229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232 /**
AnnaBridge 171:3a7713b1edbc 233 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 171:3a7713b1edbc 234 */
AnnaBridge 171:3a7713b1edbc 235 typedef union
AnnaBridge 171:3a7713b1edbc 236 {
AnnaBridge 171:3a7713b1edbc 237 struct
AnnaBridge 171:3a7713b1edbc 238 {
AnnaBridge 171:3a7713b1edbc 239 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 171:3a7713b1edbc 240 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 171:3a7713b1edbc 241 } b; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 242 uint32_t w; /*!< Type used for word access */
AnnaBridge 171:3a7713b1edbc 243 } IPSR_Type;
AnnaBridge 171:3a7713b1edbc 244
AnnaBridge 171:3a7713b1edbc 245 /* IPSR Register Definitions */
AnnaBridge 171:3a7713b1edbc 246 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 171:3a7713b1edbc 247 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 171:3a7713b1edbc 248
AnnaBridge 171:3a7713b1edbc 249
AnnaBridge 171:3a7713b1edbc 250 /**
AnnaBridge 171:3a7713b1edbc 251 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 171:3a7713b1edbc 252 */
AnnaBridge 171:3a7713b1edbc 253 typedef union
AnnaBridge 171:3a7713b1edbc 254 {
AnnaBridge 171:3a7713b1edbc 255 struct
AnnaBridge 171:3a7713b1edbc 256 {
AnnaBridge 171:3a7713b1edbc 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 171:3a7713b1edbc 258 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 171:3a7713b1edbc 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 171:3a7713b1edbc 260 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 171:3a7713b1edbc 261 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 171:3a7713b1edbc 262 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 171:3a7713b1edbc 263 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 171:3a7713b1edbc 264 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 171:3a7713b1edbc 265 } b; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 266 uint32_t w; /*!< Type used for word access */
AnnaBridge 171:3a7713b1edbc 267 } xPSR_Type;
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 /* xPSR Register Definitions */
AnnaBridge 171:3a7713b1edbc 270 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 171:3a7713b1edbc 271 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 171:3a7713b1edbc 272
AnnaBridge 171:3a7713b1edbc 273 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 171:3a7713b1edbc 274 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 171:3a7713b1edbc 277 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 171:3a7713b1edbc 280 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 171:3a7713b1edbc 281
AnnaBridge 171:3a7713b1edbc 282 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 171:3a7713b1edbc 283 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 171:3a7713b1edbc 284
AnnaBridge 171:3a7713b1edbc 285 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 171:3a7713b1edbc 286 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 171:3a7713b1edbc 287
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 /**
AnnaBridge 171:3a7713b1edbc 290 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 171:3a7713b1edbc 291 */
AnnaBridge 171:3a7713b1edbc 292 typedef union
AnnaBridge 171:3a7713b1edbc 293 {
AnnaBridge 171:3a7713b1edbc 294 struct
AnnaBridge 171:3a7713b1edbc 295 {
AnnaBridge 171:3a7713b1edbc 296 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 171:3a7713b1edbc 297 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 171:3a7713b1edbc 298 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 171:3a7713b1edbc 299 } b; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 300 uint32_t w; /*!< Type used for word access */
AnnaBridge 171:3a7713b1edbc 301 } CONTROL_Type;
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 /* CONTROL Register Definitions */
AnnaBridge 171:3a7713b1edbc 304 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 171:3a7713b1edbc 305 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 171:3a7713b1edbc 306
AnnaBridge 171:3a7713b1edbc 307 /*@} end of group CMSIS_CORE */
AnnaBridge 171:3a7713b1edbc 308
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 /**
AnnaBridge 171:3a7713b1edbc 311 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 312 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 171:3a7713b1edbc 313 \brief Type definitions for the NVIC Registers
AnnaBridge 171:3a7713b1edbc 314 @{
AnnaBridge 171:3a7713b1edbc 315 */
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 /**
AnnaBridge 171:3a7713b1edbc 318 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 171:3a7713b1edbc 319 */
AnnaBridge 171:3a7713b1edbc 320 typedef struct
AnnaBridge 171:3a7713b1edbc 321 {
AnnaBridge 171:3a7713b1edbc 322 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 171:3a7713b1edbc 323 uint32_t RESERVED0[31U];
AnnaBridge 171:3a7713b1edbc 324 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 171:3a7713b1edbc 325 uint32_t RSERVED1[31U];
AnnaBridge 171:3a7713b1edbc 326 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 171:3a7713b1edbc 327 uint32_t RESERVED2[31U];
AnnaBridge 171:3a7713b1edbc 328 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 171:3a7713b1edbc 329 uint32_t RESERVED3[31U];
AnnaBridge 171:3a7713b1edbc 330 uint32_t RESERVED4[64U];
AnnaBridge 171:3a7713b1edbc 331 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 171:3a7713b1edbc 332 } NVIC_Type;
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334 /*@} end of group CMSIS_NVIC */
AnnaBridge 171:3a7713b1edbc 335
AnnaBridge 171:3a7713b1edbc 336
AnnaBridge 171:3a7713b1edbc 337 /**
AnnaBridge 171:3a7713b1edbc 338 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 339 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 171:3a7713b1edbc 340 \brief Type definitions for the System Control Block Registers
AnnaBridge 171:3a7713b1edbc 341 @{
AnnaBridge 171:3a7713b1edbc 342 */
AnnaBridge 171:3a7713b1edbc 343
AnnaBridge 171:3a7713b1edbc 344 /**
AnnaBridge 171:3a7713b1edbc 345 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 171:3a7713b1edbc 346 */
AnnaBridge 171:3a7713b1edbc 347 typedef struct
AnnaBridge 171:3a7713b1edbc 348 {
AnnaBridge 171:3a7713b1edbc 349 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 171:3a7713b1edbc 350 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 171:3a7713b1edbc 351 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 171:3a7713b1edbc 352 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 171:3a7713b1edbc 353 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 171:3a7713b1edbc 354 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 171:3a7713b1edbc 355 uint32_t RESERVED0[1U];
AnnaBridge 171:3a7713b1edbc 356 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 171:3a7713b1edbc 357 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 171:3a7713b1edbc 358 uint32_t RESERVED1[154U];
AnnaBridge 171:3a7713b1edbc 359 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
AnnaBridge 171:3a7713b1edbc 360 } SCB_Type;
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 /* SCB CPUID Register Definitions */
AnnaBridge 171:3a7713b1edbc 363 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 171:3a7713b1edbc 364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 171:3a7713b1edbc 365
AnnaBridge 171:3a7713b1edbc 366 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 171:3a7713b1edbc 367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 171:3a7713b1edbc 368
AnnaBridge 171:3a7713b1edbc 369 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 171:3a7713b1edbc 370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 171:3a7713b1edbc 371
AnnaBridge 171:3a7713b1edbc 372 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 171:3a7713b1edbc 373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 171:3a7713b1edbc 374
AnnaBridge 171:3a7713b1edbc 375 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 171:3a7713b1edbc 376 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 171:3a7713b1edbc 377
AnnaBridge 171:3a7713b1edbc 378 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 171:3a7713b1edbc 379 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 171:3a7713b1edbc 380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 171:3a7713b1edbc 381
AnnaBridge 171:3a7713b1edbc 382 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 171:3a7713b1edbc 383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 171:3a7713b1edbc 386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 171:3a7713b1edbc 387
AnnaBridge 171:3a7713b1edbc 388 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 171:3a7713b1edbc 389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 171:3a7713b1edbc 390
AnnaBridge 171:3a7713b1edbc 391 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 171:3a7713b1edbc 392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 171:3a7713b1edbc 395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 171:3a7713b1edbc 396
AnnaBridge 171:3a7713b1edbc 397 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 171:3a7713b1edbc 398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 171:3a7713b1edbc 399
AnnaBridge 171:3a7713b1edbc 400 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 171:3a7713b1edbc 401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 171:3a7713b1edbc 402
AnnaBridge 171:3a7713b1edbc 403 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 171:3a7713b1edbc 404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 405
AnnaBridge 171:3a7713b1edbc 406 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 171:3a7713b1edbc 407 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 171:3a7713b1edbc 408 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 171:3a7713b1edbc 409
AnnaBridge 171:3a7713b1edbc 410 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 411 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 171:3a7713b1edbc 412 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 171:3a7713b1edbc 413
AnnaBridge 171:3a7713b1edbc 414 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 171:3a7713b1edbc 415 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 171:3a7713b1edbc 416
AnnaBridge 171:3a7713b1edbc 417 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 171:3a7713b1edbc 418 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 171:3a7713b1edbc 419
AnnaBridge 171:3a7713b1edbc 420 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 171:3a7713b1edbc 421 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 171:3a7713b1edbc 422
AnnaBridge 171:3a7713b1edbc 423 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 171:3a7713b1edbc 424 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 425
AnnaBridge 171:3a7713b1edbc 426 /* SCB System Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 427 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 171:3a7713b1edbc 428 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 171:3a7713b1edbc 429
AnnaBridge 171:3a7713b1edbc 430 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 171:3a7713b1edbc 431 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 171:3a7713b1edbc 432
AnnaBridge 171:3a7713b1edbc 433 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 171:3a7713b1edbc 434 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 171:3a7713b1edbc 435
AnnaBridge 171:3a7713b1edbc 436 /* SCB Configuration Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 437 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 171:3a7713b1edbc 438 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 171:3a7713b1edbc 439
AnnaBridge 171:3a7713b1edbc 440 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 171:3a7713b1edbc 441 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 171:3a7713b1edbc 442
AnnaBridge 171:3a7713b1edbc 443 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 171:3a7713b1edbc 444 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 171:3a7713b1edbc 445 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 171:3a7713b1edbc 446
AnnaBridge 171:3a7713b1edbc 447 /*@} end of group CMSIS_SCB */
AnnaBridge 171:3a7713b1edbc 448
AnnaBridge 171:3a7713b1edbc 449
AnnaBridge 171:3a7713b1edbc 450 /**
AnnaBridge 171:3a7713b1edbc 451 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 452 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 171:3a7713b1edbc 453 \brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge 171:3a7713b1edbc 454 @{
AnnaBridge 171:3a7713b1edbc 455 */
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 /**
AnnaBridge 171:3a7713b1edbc 458 \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge 171:3a7713b1edbc 459 */
AnnaBridge 171:3a7713b1edbc 460 typedef struct
AnnaBridge 171:3a7713b1edbc 461 {
AnnaBridge 171:3a7713b1edbc 462 uint32_t RESERVED0[2U];
AnnaBridge 171:3a7713b1edbc 463 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
AnnaBridge 171:3a7713b1edbc 464 } SCnSCB_Type;
AnnaBridge 171:3a7713b1edbc 465
AnnaBridge 171:3a7713b1edbc 466 /* Auxiliary Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 467 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
AnnaBridge 171:3a7713b1edbc 468 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
AnnaBridge 171:3a7713b1edbc 469
AnnaBridge 171:3a7713b1edbc 470 /*@} end of group CMSIS_SCnotSCB */
AnnaBridge 171:3a7713b1edbc 471
AnnaBridge 171:3a7713b1edbc 472
AnnaBridge 171:3a7713b1edbc 473 /**
AnnaBridge 171:3a7713b1edbc 474 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 475 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 171:3a7713b1edbc 476 \brief Type definitions for the System Timer Registers.
AnnaBridge 171:3a7713b1edbc 477 @{
AnnaBridge 171:3a7713b1edbc 478 */
AnnaBridge 171:3a7713b1edbc 479
AnnaBridge 171:3a7713b1edbc 480 /**
AnnaBridge 171:3a7713b1edbc 481 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 171:3a7713b1edbc 482 */
AnnaBridge 171:3a7713b1edbc 483 typedef struct
AnnaBridge 171:3a7713b1edbc 484 {
AnnaBridge 171:3a7713b1edbc 485 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 171:3a7713b1edbc 486 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 171:3a7713b1edbc 487 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 171:3a7713b1edbc 488 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 171:3a7713b1edbc 489 } SysTick_Type;
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 /* SysTick Control / Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 492 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 171:3a7713b1edbc 493 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 171:3a7713b1edbc 496 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 171:3a7713b1edbc 497
AnnaBridge 171:3a7713b1edbc 498 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 171:3a7713b1edbc 499 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 171:3a7713b1edbc 500
AnnaBridge 171:3a7713b1edbc 501 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 171:3a7713b1edbc 502 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 503
AnnaBridge 171:3a7713b1edbc 504 /* SysTick Reload Register Definitions */
AnnaBridge 171:3a7713b1edbc 505 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 171:3a7713b1edbc 506 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 171:3a7713b1edbc 507
AnnaBridge 171:3a7713b1edbc 508 /* SysTick Current Register Definitions */
AnnaBridge 171:3a7713b1edbc 509 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 171:3a7713b1edbc 510 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 171:3a7713b1edbc 511
AnnaBridge 171:3a7713b1edbc 512 /* SysTick Calibration Register Definitions */
AnnaBridge 171:3a7713b1edbc 513 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 171:3a7713b1edbc 514 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 171:3a7713b1edbc 515
AnnaBridge 171:3a7713b1edbc 516 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 171:3a7713b1edbc 517 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 171:3a7713b1edbc 518
AnnaBridge 171:3a7713b1edbc 519 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 171:3a7713b1edbc 520 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 171:3a7713b1edbc 521
AnnaBridge 171:3a7713b1edbc 522 /*@} end of group CMSIS_SysTick */
AnnaBridge 171:3a7713b1edbc 523
AnnaBridge 171:3a7713b1edbc 524 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 525 /**
AnnaBridge 171:3a7713b1edbc 526 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 527 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 171:3a7713b1edbc 528 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 171:3a7713b1edbc 529 @{
AnnaBridge 171:3a7713b1edbc 530 */
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 /**
AnnaBridge 171:3a7713b1edbc 533 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 171:3a7713b1edbc 534 */
AnnaBridge 171:3a7713b1edbc 535 typedef struct
AnnaBridge 171:3a7713b1edbc 536 {
AnnaBridge 171:3a7713b1edbc 537 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 171:3a7713b1edbc 538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 171:3a7713b1edbc 539 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 171:3a7713b1edbc 540 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 171:3a7713b1edbc 541 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 171:3a7713b1edbc 542 } MPU_Type;
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544 /* MPU Type Register Definitions */
AnnaBridge 171:3a7713b1edbc 545 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 171:3a7713b1edbc 546 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 171:3a7713b1edbc 547
AnnaBridge 171:3a7713b1edbc 548 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 171:3a7713b1edbc 549 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 171:3a7713b1edbc 550
AnnaBridge 171:3a7713b1edbc 551 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 171:3a7713b1edbc 552 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 /* MPU Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 555 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 171:3a7713b1edbc 556 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 171:3a7713b1edbc 559 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 171:3a7713b1edbc 560
AnnaBridge 171:3a7713b1edbc 561 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 171:3a7713b1edbc 562 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 563
AnnaBridge 171:3a7713b1edbc 564 /* MPU Region Number Register Definitions */
AnnaBridge 171:3a7713b1edbc 565 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 171:3a7713b1edbc 566 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 171:3a7713b1edbc 567
AnnaBridge 171:3a7713b1edbc 568 /* MPU Region Base Address Register Definitions */
AnnaBridge 171:3a7713b1edbc 569 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
AnnaBridge 171:3a7713b1edbc 570 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 171:3a7713b1edbc 571
AnnaBridge 171:3a7713b1edbc 572 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
AnnaBridge 171:3a7713b1edbc 573 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 171:3a7713b1edbc 574
AnnaBridge 171:3a7713b1edbc 575 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
AnnaBridge 171:3a7713b1edbc 576 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 171:3a7713b1edbc 577
AnnaBridge 171:3a7713b1edbc 578 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 171:3a7713b1edbc 579 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 171:3a7713b1edbc 580 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 171:3a7713b1edbc 581
AnnaBridge 171:3a7713b1edbc 582 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 171:3a7713b1edbc 583 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 171:3a7713b1edbc 584
AnnaBridge 171:3a7713b1edbc 585 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 171:3a7713b1edbc 586 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 171:3a7713b1edbc 587
AnnaBridge 171:3a7713b1edbc 588 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 171:3a7713b1edbc 589 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 171:3a7713b1edbc 590
AnnaBridge 171:3a7713b1edbc 591 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 171:3a7713b1edbc 592 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 171:3a7713b1edbc 595 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 171:3a7713b1edbc 598 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 171:3a7713b1edbc 599
AnnaBridge 171:3a7713b1edbc 600 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 171:3a7713b1edbc 601 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 171:3a7713b1edbc 602
AnnaBridge 171:3a7713b1edbc 603 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
AnnaBridge 171:3a7713b1edbc 604 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 171:3a7713b1edbc 605
AnnaBridge 171:3a7713b1edbc 606 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
AnnaBridge 171:3a7713b1edbc 607 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 171:3a7713b1edbc 608
AnnaBridge 171:3a7713b1edbc 609 /*@} end of group CMSIS_MPU */
AnnaBridge 171:3a7713b1edbc 610 #endif
AnnaBridge 171:3a7713b1edbc 611
AnnaBridge 171:3a7713b1edbc 612
AnnaBridge 171:3a7713b1edbc 613 /**
AnnaBridge 171:3a7713b1edbc 614 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 615 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 171:3a7713b1edbc 616 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 171:3a7713b1edbc 617 Therefore they are not covered by the SC000 header file.
AnnaBridge 171:3a7713b1edbc 618 @{
AnnaBridge 171:3a7713b1edbc 619 */
AnnaBridge 171:3a7713b1edbc 620 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 171:3a7713b1edbc 621
AnnaBridge 171:3a7713b1edbc 622
AnnaBridge 171:3a7713b1edbc 623 /**
AnnaBridge 171:3a7713b1edbc 624 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 625 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 171:3a7713b1edbc 626 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 171:3a7713b1edbc 627 @{
AnnaBridge 171:3a7713b1edbc 628 */
AnnaBridge 171:3a7713b1edbc 629
AnnaBridge 171:3a7713b1edbc 630 /**
AnnaBridge 171:3a7713b1edbc 631 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 171:3a7713b1edbc 632 \param[in] field Name of the register bit field.
AnnaBridge 171:3a7713b1edbc 633 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 171:3a7713b1edbc 634 \return Masked and shifted value.
AnnaBridge 171:3a7713b1edbc 635 */
AnnaBridge 171:3a7713b1edbc 636 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 171:3a7713b1edbc 637
AnnaBridge 171:3a7713b1edbc 638 /**
AnnaBridge 171:3a7713b1edbc 639 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 171:3a7713b1edbc 640 \param[in] field Name of the register bit field.
AnnaBridge 171:3a7713b1edbc 641 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 171:3a7713b1edbc 642 \return Masked and shifted bit field value.
AnnaBridge 171:3a7713b1edbc 643 */
AnnaBridge 171:3a7713b1edbc 644 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 171:3a7713b1edbc 645
AnnaBridge 171:3a7713b1edbc 646 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 171:3a7713b1edbc 647
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 /**
AnnaBridge 171:3a7713b1edbc 650 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 651 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 171:3a7713b1edbc 652 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 171:3a7713b1edbc 653 @{
AnnaBridge 171:3a7713b1edbc 654 */
AnnaBridge 171:3a7713b1edbc 655
AnnaBridge 171:3a7713b1edbc 656 /* Memory mapping of Core Hardware */
AnnaBridge 171:3a7713b1edbc 657 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 171:3a7713b1edbc 658 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 171:3a7713b1edbc 659 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 171:3a7713b1edbc 660 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 171:3a7713b1edbc 661
AnnaBridge 171:3a7713b1edbc 662 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 171:3a7713b1edbc 663 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 171:3a7713b1edbc 664 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 171:3a7713b1edbc 665 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 171:3a7713b1edbc 666
AnnaBridge 171:3a7713b1edbc 667 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 668 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 171:3a7713b1edbc 669 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 171:3a7713b1edbc 670 #endif
AnnaBridge 171:3a7713b1edbc 671
AnnaBridge 171:3a7713b1edbc 672 /*@} */
AnnaBridge 171:3a7713b1edbc 673
AnnaBridge 171:3a7713b1edbc 674
AnnaBridge 171:3a7713b1edbc 675
AnnaBridge 171:3a7713b1edbc 676 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 677 * Hardware Abstraction Layer
AnnaBridge 171:3a7713b1edbc 678 Core Function Interface contains:
AnnaBridge 171:3a7713b1edbc 679 - Core NVIC Functions
AnnaBridge 171:3a7713b1edbc 680 - Core SysTick Functions
AnnaBridge 171:3a7713b1edbc 681 - Core Register Access Functions
AnnaBridge 171:3a7713b1edbc 682 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 683 /**
AnnaBridge 171:3a7713b1edbc 684 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 171:3a7713b1edbc 685 */
AnnaBridge 171:3a7713b1edbc 686
AnnaBridge 171:3a7713b1edbc 687
AnnaBridge 171:3a7713b1edbc 688
AnnaBridge 171:3a7713b1edbc 689 /* ########################## NVIC functions #################################### */
AnnaBridge 171:3a7713b1edbc 690 /**
AnnaBridge 171:3a7713b1edbc 691 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 692 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 171:3a7713b1edbc 693 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 171:3a7713b1edbc 694 @{
AnnaBridge 171:3a7713b1edbc 695 */
AnnaBridge 171:3a7713b1edbc 696
AnnaBridge 171:3a7713b1edbc 697 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 171:3a7713b1edbc 698 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 171:3a7713b1edbc 699 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 171:3a7713b1edbc 700 #endif
AnnaBridge 171:3a7713b1edbc 701 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 171:3a7713b1edbc 702 #else
AnnaBridge 171:3a7713b1edbc 703 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
AnnaBridge 171:3a7713b1edbc 704 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
AnnaBridge 171:3a7713b1edbc 705 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 171:3a7713b1edbc 706 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 171:3a7713b1edbc 707 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 171:3a7713b1edbc 708 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 171:3a7713b1edbc 709 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 171:3a7713b1edbc 710 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 171:3a7713b1edbc 711 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
AnnaBridge 171:3a7713b1edbc 712 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 171:3a7713b1edbc 713 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 171:3a7713b1edbc 714 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 171:3a7713b1edbc 715 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 171:3a7713b1edbc 716
AnnaBridge 171:3a7713b1edbc 717 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 171:3a7713b1edbc 718 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 171:3a7713b1edbc 719 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 171:3a7713b1edbc 720 #endif
AnnaBridge 171:3a7713b1edbc 721 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 171:3a7713b1edbc 722 #else
AnnaBridge 171:3a7713b1edbc 723 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 171:3a7713b1edbc 724 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 171:3a7713b1edbc 725 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 171:3a7713b1edbc 726
AnnaBridge 171:3a7713b1edbc 727 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 171:3a7713b1edbc 728
AnnaBridge 171:3a7713b1edbc 729
AnnaBridge 171:3a7713b1edbc 730 /* The following EXC_RETURN values are saved the LR on exception entry */
AnnaBridge 171:3a7713b1edbc 731 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
AnnaBridge 171:3a7713b1edbc 732 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
AnnaBridge 171:3a7713b1edbc 733 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
AnnaBridge 171:3a7713b1edbc 734
AnnaBridge 171:3a7713b1edbc 735
AnnaBridge 171:3a7713b1edbc 736 /* Interrupt Priorities are WORD accessible only under Armv6-M */
AnnaBridge 171:3a7713b1edbc 737 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 171:3a7713b1edbc 738 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 171:3a7713b1edbc 739 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 171:3a7713b1edbc 740 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 171:3a7713b1edbc 741
AnnaBridge 171:3a7713b1edbc 742
AnnaBridge 171:3a7713b1edbc 743 /**
AnnaBridge 171:3a7713b1edbc 744 \brief Enable Interrupt
AnnaBridge 171:3a7713b1edbc 745 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 171:3a7713b1edbc 746 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 747 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 748 */
AnnaBridge 171:3a7713b1edbc 749 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 750 {
AnnaBridge 171:3a7713b1edbc 751 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 752 {
AnnaBridge 171:3a7713b1edbc 753 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 754 }
AnnaBridge 171:3a7713b1edbc 755 }
AnnaBridge 171:3a7713b1edbc 756
AnnaBridge 171:3a7713b1edbc 757
AnnaBridge 171:3a7713b1edbc 758 /**
AnnaBridge 171:3a7713b1edbc 759 \brief Get Interrupt Enable status
AnnaBridge 171:3a7713b1edbc 760 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 171:3a7713b1edbc 761 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 762 \return 0 Interrupt is not enabled.
AnnaBridge 171:3a7713b1edbc 763 \return 1 Interrupt is enabled.
AnnaBridge 171:3a7713b1edbc 764 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 765 */
AnnaBridge 171:3a7713b1edbc 766 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 767 {
AnnaBridge 171:3a7713b1edbc 768 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 769 {
AnnaBridge 171:3a7713b1edbc 770 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 771 }
AnnaBridge 171:3a7713b1edbc 772 else
AnnaBridge 171:3a7713b1edbc 773 {
AnnaBridge 171:3a7713b1edbc 774 return(0U);
AnnaBridge 171:3a7713b1edbc 775 }
AnnaBridge 171:3a7713b1edbc 776 }
AnnaBridge 171:3a7713b1edbc 777
AnnaBridge 171:3a7713b1edbc 778
AnnaBridge 171:3a7713b1edbc 779 /**
AnnaBridge 171:3a7713b1edbc 780 \brief Disable Interrupt
AnnaBridge 171:3a7713b1edbc 781 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 171:3a7713b1edbc 782 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 783 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 784 */
AnnaBridge 171:3a7713b1edbc 785 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 786 {
AnnaBridge 171:3a7713b1edbc 787 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 788 {
AnnaBridge 171:3a7713b1edbc 789 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 790 __DSB();
AnnaBridge 171:3a7713b1edbc 791 __ISB();
AnnaBridge 171:3a7713b1edbc 792 }
AnnaBridge 171:3a7713b1edbc 793 }
AnnaBridge 171:3a7713b1edbc 794
AnnaBridge 171:3a7713b1edbc 795
AnnaBridge 171:3a7713b1edbc 796 /**
AnnaBridge 171:3a7713b1edbc 797 \brief Get Pending Interrupt
AnnaBridge 171:3a7713b1edbc 798 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 171:3a7713b1edbc 799 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 800 \return 0 Interrupt status is not pending.
AnnaBridge 171:3a7713b1edbc 801 \return 1 Interrupt status is pending.
AnnaBridge 171:3a7713b1edbc 802 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 803 */
AnnaBridge 171:3a7713b1edbc 804 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 805 {
AnnaBridge 171:3a7713b1edbc 806 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 807 {
AnnaBridge 171:3a7713b1edbc 808 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 809 }
AnnaBridge 171:3a7713b1edbc 810 else
AnnaBridge 171:3a7713b1edbc 811 {
AnnaBridge 171:3a7713b1edbc 812 return(0U);
AnnaBridge 171:3a7713b1edbc 813 }
AnnaBridge 171:3a7713b1edbc 814 }
AnnaBridge 171:3a7713b1edbc 815
AnnaBridge 171:3a7713b1edbc 816
AnnaBridge 171:3a7713b1edbc 817 /**
AnnaBridge 171:3a7713b1edbc 818 \brief Set Pending Interrupt
AnnaBridge 171:3a7713b1edbc 819 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 171:3a7713b1edbc 820 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 821 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 822 */
AnnaBridge 171:3a7713b1edbc 823 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 824 {
AnnaBridge 171:3a7713b1edbc 825 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 826 {
AnnaBridge 171:3a7713b1edbc 827 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 828 }
AnnaBridge 171:3a7713b1edbc 829 }
AnnaBridge 171:3a7713b1edbc 830
AnnaBridge 171:3a7713b1edbc 831
AnnaBridge 171:3a7713b1edbc 832 /**
AnnaBridge 171:3a7713b1edbc 833 \brief Clear Pending Interrupt
AnnaBridge 171:3a7713b1edbc 834 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 171:3a7713b1edbc 835 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 836 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 837 */
AnnaBridge 171:3a7713b1edbc 838 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 839 {
AnnaBridge 171:3a7713b1edbc 840 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 841 {
AnnaBridge 171:3a7713b1edbc 842 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 843 }
AnnaBridge 171:3a7713b1edbc 844 }
AnnaBridge 171:3a7713b1edbc 845
AnnaBridge 171:3a7713b1edbc 846
AnnaBridge 171:3a7713b1edbc 847 /**
AnnaBridge 171:3a7713b1edbc 848 \brief Set Interrupt Priority
AnnaBridge 171:3a7713b1edbc 849 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 171:3a7713b1edbc 850 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 851 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 852 \param [in] IRQn Interrupt number.
AnnaBridge 171:3a7713b1edbc 853 \param [in] priority Priority to set.
AnnaBridge 171:3a7713b1edbc 854 \note The priority cannot be set for every processor exception.
AnnaBridge 171:3a7713b1edbc 855 */
AnnaBridge 171:3a7713b1edbc 856 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 171:3a7713b1edbc 857 {
AnnaBridge 171:3a7713b1edbc 858 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 859 {
AnnaBridge 171:3a7713b1edbc 860 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 171:3a7713b1edbc 861 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 171:3a7713b1edbc 862 }
AnnaBridge 171:3a7713b1edbc 863 else
AnnaBridge 171:3a7713b1edbc 864 {
AnnaBridge 171:3a7713b1edbc 865 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 171:3a7713b1edbc 866 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 171:3a7713b1edbc 867 }
AnnaBridge 171:3a7713b1edbc 868 }
AnnaBridge 171:3a7713b1edbc 869
AnnaBridge 171:3a7713b1edbc 870
AnnaBridge 171:3a7713b1edbc 871 /**
AnnaBridge 171:3a7713b1edbc 872 \brief Get Interrupt Priority
AnnaBridge 171:3a7713b1edbc 873 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 171:3a7713b1edbc 874 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 875 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 876 \param [in] IRQn Interrupt number.
AnnaBridge 171:3a7713b1edbc 877 \return Interrupt Priority.
AnnaBridge 171:3a7713b1edbc 878 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 171:3a7713b1edbc 879 */
AnnaBridge 171:3a7713b1edbc 880 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 881 {
AnnaBridge 171:3a7713b1edbc 882
AnnaBridge 171:3a7713b1edbc 883 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 884 {
AnnaBridge 171:3a7713b1edbc 885 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 171:3a7713b1edbc 886 }
AnnaBridge 171:3a7713b1edbc 887 else
AnnaBridge 171:3a7713b1edbc 888 {
AnnaBridge 171:3a7713b1edbc 889 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 171:3a7713b1edbc 890 }
AnnaBridge 171:3a7713b1edbc 891 }
AnnaBridge 171:3a7713b1edbc 892
AnnaBridge 171:3a7713b1edbc 893
AnnaBridge 171:3a7713b1edbc 894 /**
AnnaBridge 171:3a7713b1edbc 895 \brief Set Interrupt Vector
AnnaBridge 171:3a7713b1edbc 896 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 171:3a7713b1edbc 897 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 898 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 899 VTOR must been relocated to SRAM before.
AnnaBridge 171:3a7713b1edbc 900 \param [in] IRQn Interrupt number
AnnaBridge 171:3a7713b1edbc 901 \param [in] vector Address of interrupt handler function
AnnaBridge 171:3a7713b1edbc 902 */
AnnaBridge 171:3a7713b1edbc 903 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 171:3a7713b1edbc 904 {
AnnaBridge 171:3a7713b1edbc 905 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 171:3a7713b1edbc 906 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 171:3a7713b1edbc 907 }
AnnaBridge 171:3a7713b1edbc 908
AnnaBridge 171:3a7713b1edbc 909
AnnaBridge 171:3a7713b1edbc 910 /**
AnnaBridge 171:3a7713b1edbc 911 \brief Get Interrupt Vector
AnnaBridge 171:3a7713b1edbc 912 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 171:3a7713b1edbc 913 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 914 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 915 \param [in] IRQn Interrupt number.
AnnaBridge 171:3a7713b1edbc 916 \return Address of interrupt handler function
AnnaBridge 171:3a7713b1edbc 917 */
AnnaBridge 171:3a7713b1edbc 918 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 919 {
AnnaBridge 171:3a7713b1edbc 920 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 171:3a7713b1edbc 921 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 171:3a7713b1edbc 922 }
AnnaBridge 171:3a7713b1edbc 923
AnnaBridge 171:3a7713b1edbc 924
AnnaBridge 171:3a7713b1edbc 925 /**
AnnaBridge 171:3a7713b1edbc 926 \brief System Reset
AnnaBridge 171:3a7713b1edbc 927 \details Initiates a system reset request to reset the MCU.
AnnaBridge 171:3a7713b1edbc 928 */
AnnaBridge 171:3a7713b1edbc 929 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 171:3a7713b1edbc 930 {
AnnaBridge 171:3a7713b1edbc 931 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 171:3a7713b1edbc 932 buffered write are completed before reset */
AnnaBridge 171:3a7713b1edbc 933 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 171:3a7713b1edbc 934 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 171:3a7713b1edbc 935 __DSB(); /* Ensure completion of memory access */
AnnaBridge 171:3a7713b1edbc 936
AnnaBridge 171:3a7713b1edbc 937 for(;;) /* wait until reset */
AnnaBridge 171:3a7713b1edbc 938 {
AnnaBridge 171:3a7713b1edbc 939 __NOP();
AnnaBridge 171:3a7713b1edbc 940 }
AnnaBridge 171:3a7713b1edbc 941 }
AnnaBridge 171:3a7713b1edbc 942
AnnaBridge 171:3a7713b1edbc 943 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 171:3a7713b1edbc 944
AnnaBridge 171:3a7713b1edbc 945
AnnaBridge 171:3a7713b1edbc 946 /* ########################## FPU functions #################################### */
AnnaBridge 171:3a7713b1edbc 947 /**
AnnaBridge 171:3a7713b1edbc 948 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 949 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 171:3a7713b1edbc 950 \brief Function that provides FPU type.
AnnaBridge 171:3a7713b1edbc 951 @{
AnnaBridge 171:3a7713b1edbc 952 */
AnnaBridge 171:3a7713b1edbc 953
AnnaBridge 171:3a7713b1edbc 954 /**
AnnaBridge 171:3a7713b1edbc 955 \brief get FPU type
AnnaBridge 171:3a7713b1edbc 956 \details returns the FPU type
AnnaBridge 171:3a7713b1edbc 957 \returns
AnnaBridge 171:3a7713b1edbc 958 - \b 0: No FPU
AnnaBridge 171:3a7713b1edbc 959 - \b 1: Single precision FPU
AnnaBridge 171:3a7713b1edbc 960 - \b 2: Double + Single precision FPU
AnnaBridge 171:3a7713b1edbc 961 */
AnnaBridge 171:3a7713b1edbc 962 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 171:3a7713b1edbc 963 {
AnnaBridge 171:3a7713b1edbc 964 return 0U; /* No FPU */
AnnaBridge 171:3a7713b1edbc 965 }
AnnaBridge 171:3a7713b1edbc 966
AnnaBridge 171:3a7713b1edbc 967
AnnaBridge 171:3a7713b1edbc 968 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 171:3a7713b1edbc 969
AnnaBridge 171:3a7713b1edbc 970
AnnaBridge 171:3a7713b1edbc 971
AnnaBridge 171:3a7713b1edbc 972 /* ################################## SysTick function ############################################ */
AnnaBridge 171:3a7713b1edbc 973 /**
AnnaBridge 171:3a7713b1edbc 974 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 975 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 171:3a7713b1edbc 976 \brief Functions that configure the System.
AnnaBridge 171:3a7713b1edbc 977 @{
AnnaBridge 171:3a7713b1edbc 978 */
AnnaBridge 171:3a7713b1edbc 979
AnnaBridge 171:3a7713b1edbc 980 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 171:3a7713b1edbc 981
AnnaBridge 171:3a7713b1edbc 982 /**
AnnaBridge 171:3a7713b1edbc 983 \brief System Tick Configuration
AnnaBridge 171:3a7713b1edbc 984 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 171:3a7713b1edbc 985 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 171:3a7713b1edbc 986 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 171:3a7713b1edbc 987 \return 0 Function succeeded.
AnnaBridge 171:3a7713b1edbc 988 \return 1 Function failed.
AnnaBridge 171:3a7713b1edbc 989 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 171:3a7713b1edbc 990 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 171:3a7713b1edbc 991 must contain a vendor-specific implementation of this function.
AnnaBridge 171:3a7713b1edbc 992 */
AnnaBridge 171:3a7713b1edbc 993 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 171:3a7713b1edbc 994 {
AnnaBridge 171:3a7713b1edbc 995 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 171:3a7713b1edbc 996 {
AnnaBridge 171:3a7713b1edbc 997 return (1UL); /* Reload value impossible */
AnnaBridge 171:3a7713b1edbc 998 }
AnnaBridge 171:3a7713b1edbc 999
AnnaBridge 171:3a7713b1edbc 1000 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 171:3a7713b1edbc 1001 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 171:3a7713b1edbc 1002 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 171:3a7713b1edbc 1003 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 171:3a7713b1edbc 1004 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 171:3a7713b1edbc 1005 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 171:3a7713b1edbc 1006 return (0UL); /* Function successful */
AnnaBridge 171:3a7713b1edbc 1007 }
AnnaBridge 171:3a7713b1edbc 1008
AnnaBridge 171:3a7713b1edbc 1009 #endif
AnnaBridge 171:3a7713b1edbc 1010
AnnaBridge 171:3a7713b1edbc 1011 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 171:3a7713b1edbc 1012
AnnaBridge 171:3a7713b1edbc 1013
AnnaBridge 171:3a7713b1edbc 1014
AnnaBridge 171:3a7713b1edbc 1015
AnnaBridge 171:3a7713b1edbc 1016 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 1017 }
AnnaBridge 171:3a7713b1edbc 1018 #endif
AnnaBridge 171:3a7713b1edbc 1019
AnnaBridge 171:3a7713b1edbc 1020 #endif /* __CORE_SC000_H_DEPENDANT */
AnnaBridge 171:3a7713b1edbc 1021
AnnaBridge 171:3a7713b1edbc 1022 #endif /* __CMSIS_GENERIC */