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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file cmsis_armclang.h
AnnaBridge 171:3a7713b1edbc 3 * @brief CMSIS compiler armclang (Arm Compiler 6) header file
AnnaBridge 171:3a7713b1edbc 4 * @version V5.0.4
AnnaBridge 171:3a7713b1edbc 5 * @date 10. January 2018
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7 /*
AnnaBridge 171:3a7713b1edbc 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 171:3a7713b1edbc 13 * not use this file except in compliance with the License.
AnnaBridge 171:3a7713b1edbc 14 * You may obtain a copy of the License at
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 171:3a7713b1edbc 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 171:3a7713b1edbc 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 171:3a7713b1edbc 21 * See the License for the specific language governing permissions and
AnnaBridge 171:3a7713b1edbc 22 * limitations under the License.
AnnaBridge 171:3a7713b1edbc 23 */
AnnaBridge 171:3a7713b1edbc 24
AnnaBridge 171:3a7713b1edbc 25 /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
AnnaBridge 171:3a7713b1edbc 26
AnnaBridge 171:3a7713b1edbc 27 #ifndef __CMSIS_ARMCLANG_H
AnnaBridge 171:3a7713b1edbc 28 #define __CMSIS_ARMCLANG_H
AnnaBridge 171:3a7713b1edbc 29
AnnaBridge 171:3a7713b1edbc 30 #pragma clang system_header /* treat file as system include file */
AnnaBridge 171:3a7713b1edbc 31
AnnaBridge 171:3a7713b1edbc 32 #ifndef __ARM_COMPAT_H
AnnaBridge 171:3a7713b1edbc 33 #include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
AnnaBridge 171:3a7713b1edbc 34 #endif
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* CMSIS compiler specific defines */
AnnaBridge 171:3a7713b1edbc 37 #ifndef __ASM
AnnaBridge 171:3a7713b1edbc 38 #define __ASM __asm
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40 #ifndef __INLINE
AnnaBridge 171:3a7713b1edbc 41 #define __INLINE __inline
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43 #ifndef __STATIC_INLINE
AnnaBridge 171:3a7713b1edbc 44 #define __STATIC_INLINE static __inline
AnnaBridge 171:3a7713b1edbc 45 #endif
AnnaBridge 171:3a7713b1edbc 46 #ifndef __STATIC_FORCEINLINE
AnnaBridge 171:3a7713b1edbc 47 #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
AnnaBridge 171:3a7713b1edbc 48 #endif
AnnaBridge 171:3a7713b1edbc 49 #ifndef __NO_RETURN
AnnaBridge 171:3a7713b1edbc 50 #define __NO_RETURN __attribute__((__noreturn__))
AnnaBridge 171:3a7713b1edbc 51 #endif
AnnaBridge 171:3a7713b1edbc 52 #ifndef __USED
AnnaBridge 171:3a7713b1edbc 53 #define __USED __attribute__((used))
AnnaBridge 171:3a7713b1edbc 54 #endif
AnnaBridge 171:3a7713b1edbc 55 #ifndef __WEAK
AnnaBridge 171:3a7713b1edbc 56 #define __WEAK __attribute__((weak))
AnnaBridge 171:3a7713b1edbc 57 #endif
AnnaBridge 171:3a7713b1edbc 58 #ifndef __PACKED
AnnaBridge 171:3a7713b1edbc 59 #define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge 171:3a7713b1edbc 60 #endif
AnnaBridge 171:3a7713b1edbc 61 #ifndef __PACKED_STRUCT
AnnaBridge 171:3a7713b1edbc 62 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge 171:3a7713b1edbc 63 #endif
AnnaBridge 171:3a7713b1edbc 64 #ifndef __PACKED_UNION
AnnaBridge 171:3a7713b1edbc 65 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
AnnaBridge 171:3a7713b1edbc 66 #endif
AnnaBridge 171:3a7713b1edbc 67 #ifndef __UNALIGNED_UINT32 /* deprecated */
AnnaBridge 171:3a7713b1edbc 68 #pragma clang diagnostic push
AnnaBridge 171:3a7713b1edbc 69 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 171:3a7713b1edbc 70 /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
AnnaBridge 171:3a7713b1edbc 71 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
AnnaBridge 171:3a7713b1edbc 72 #pragma clang diagnostic pop
AnnaBridge 171:3a7713b1edbc 73 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
AnnaBridge 171:3a7713b1edbc 74 #endif
AnnaBridge 171:3a7713b1edbc 75 #ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge 171:3a7713b1edbc 76 #pragma clang diagnostic push
AnnaBridge 171:3a7713b1edbc 77 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 171:3a7713b1edbc 78 /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
AnnaBridge 171:3a7713b1edbc 79 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge 171:3a7713b1edbc 80 #pragma clang diagnostic pop
AnnaBridge 171:3a7713b1edbc 81 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 171:3a7713b1edbc 82 #endif
AnnaBridge 171:3a7713b1edbc 83 #ifndef __UNALIGNED_UINT16_READ
AnnaBridge 171:3a7713b1edbc 84 #pragma clang diagnostic push
AnnaBridge 171:3a7713b1edbc 85 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 171:3a7713b1edbc 86 /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
AnnaBridge 171:3a7713b1edbc 87 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge 171:3a7713b1edbc 88 #pragma clang diagnostic pop
AnnaBridge 171:3a7713b1edbc 89 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
AnnaBridge 171:3a7713b1edbc 90 #endif
AnnaBridge 171:3a7713b1edbc 91 #ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge 171:3a7713b1edbc 92 #pragma clang diagnostic push
AnnaBridge 171:3a7713b1edbc 93 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 171:3a7713b1edbc 94 /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
AnnaBridge 171:3a7713b1edbc 95 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge 171:3a7713b1edbc 96 #pragma clang diagnostic pop
AnnaBridge 171:3a7713b1edbc 97 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 171:3a7713b1edbc 98 #endif
AnnaBridge 171:3a7713b1edbc 99 #ifndef __UNALIGNED_UINT32_READ
AnnaBridge 171:3a7713b1edbc 100 #pragma clang diagnostic push
AnnaBridge 171:3a7713b1edbc 101 #pragma clang diagnostic ignored "-Wpacked"
AnnaBridge 171:3a7713b1edbc 102 /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
AnnaBridge 171:3a7713b1edbc 103 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge 171:3a7713b1edbc 104 #pragma clang diagnostic pop
AnnaBridge 171:3a7713b1edbc 105 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
AnnaBridge 171:3a7713b1edbc 106 #endif
AnnaBridge 171:3a7713b1edbc 107 #ifndef __ALIGNED
AnnaBridge 171:3a7713b1edbc 108 #define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge 171:3a7713b1edbc 109 #endif
AnnaBridge 171:3a7713b1edbc 110 #ifndef __RESTRICT
AnnaBridge 171:3a7713b1edbc 111 #define __RESTRICT __restrict
AnnaBridge 171:3a7713b1edbc 112 #endif
AnnaBridge 171:3a7713b1edbc 113
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 /* ########################### Core Function Access ########################### */
AnnaBridge 171:3a7713b1edbc 116 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 117 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge 171:3a7713b1edbc 118 @{
AnnaBridge 171:3a7713b1edbc 119 */
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 /**
AnnaBridge 171:3a7713b1edbc 122 \brief Enable IRQ Interrupts
AnnaBridge 171:3a7713b1edbc 123 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge 171:3a7713b1edbc 124 Can only be executed in Privileged modes.
AnnaBridge 171:3a7713b1edbc 125 */
AnnaBridge 171:3a7713b1edbc 126 /* intrinsic void __enable_irq(); see arm_compat.h */
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129 /**
AnnaBridge 171:3a7713b1edbc 130 \brief Disable IRQ Interrupts
AnnaBridge 171:3a7713b1edbc 131 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge 171:3a7713b1edbc 132 Can only be executed in Privileged modes.
AnnaBridge 171:3a7713b1edbc 133 */
AnnaBridge 171:3a7713b1edbc 134 /* intrinsic void __disable_irq(); see arm_compat.h */
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 /**
AnnaBridge 171:3a7713b1edbc 138 \brief Get Control Register
AnnaBridge 171:3a7713b1edbc 139 \details Returns the content of the Control Register.
AnnaBridge 171:3a7713b1edbc 140 \return Control Register value
AnnaBridge 171:3a7713b1edbc 141 */
AnnaBridge 171:3a7713b1edbc 142 __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
AnnaBridge 171:3a7713b1edbc 143 {
AnnaBridge 171:3a7713b1edbc 144 uint32_t result;
AnnaBridge 171:3a7713b1edbc 145
AnnaBridge 171:3a7713b1edbc 146 __ASM volatile ("MRS %0, control" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 147 return(result);
AnnaBridge 171:3a7713b1edbc 148 }
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 152 /**
AnnaBridge 171:3a7713b1edbc 153 \brief Get Control Register (non-secure)
AnnaBridge 171:3a7713b1edbc 154 \details Returns the content of the non-secure Control Register when in secure mode.
AnnaBridge 171:3a7713b1edbc 155 \return non-secure Control Register value
AnnaBridge 171:3a7713b1edbc 156 */
AnnaBridge 171:3a7713b1edbc 157 __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
AnnaBridge 171:3a7713b1edbc 158 {
AnnaBridge 171:3a7713b1edbc 159 uint32_t result;
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 162 return(result);
AnnaBridge 171:3a7713b1edbc 163 }
AnnaBridge 171:3a7713b1edbc 164 #endif
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166
AnnaBridge 171:3a7713b1edbc 167 /**
AnnaBridge 171:3a7713b1edbc 168 \brief Set Control Register
AnnaBridge 171:3a7713b1edbc 169 \details Writes the given value to the Control Register.
AnnaBridge 171:3a7713b1edbc 170 \param [in] control Control Register value to set
AnnaBridge 171:3a7713b1edbc 171 */
AnnaBridge 171:3a7713b1edbc 172 __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
AnnaBridge 171:3a7713b1edbc 173 {
AnnaBridge 171:3a7713b1edbc 174 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
AnnaBridge 171:3a7713b1edbc 175 }
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 179 /**
AnnaBridge 171:3a7713b1edbc 180 \brief Set Control Register (non-secure)
AnnaBridge 171:3a7713b1edbc 181 \details Writes the given value to the non-secure Control Register when in secure state.
AnnaBridge 171:3a7713b1edbc 182 \param [in] control Control Register value to set
AnnaBridge 171:3a7713b1edbc 183 */
AnnaBridge 171:3a7713b1edbc 184 __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
AnnaBridge 171:3a7713b1edbc 185 {
AnnaBridge 171:3a7713b1edbc 186 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
AnnaBridge 171:3a7713b1edbc 187 }
AnnaBridge 171:3a7713b1edbc 188 #endif
AnnaBridge 171:3a7713b1edbc 189
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 /**
AnnaBridge 171:3a7713b1edbc 192 \brief Get IPSR Register
AnnaBridge 171:3a7713b1edbc 193 \details Returns the content of the IPSR Register.
AnnaBridge 171:3a7713b1edbc 194 \return IPSR Register value
AnnaBridge 171:3a7713b1edbc 195 */
AnnaBridge 171:3a7713b1edbc 196 __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
AnnaBridge 171:3a7713b1edbc 197 {
AnnaBridge 171:3a7713b1edbc 198 uint32_t result;
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 201 return(result);
AnnaBridge 171:3a7713b1edbc 202 }
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 /**
AnnaBridge 171:3a7713b1edbc 206 \brief Get APSR Register
AnnaBridge 171:3a7713b1edbc 207 \details Returns the content of the APSR Register.
AnnaBridge 171:3a7713b1edbc 208 \return APSR Register value
AnnaBridge 171:3a7713b1edbc 209 */
AnnaBridge 171:3a7713b1edbc 210 __STATIC_FORCEINLINE uint32_t __get_APSR(void)
AnnaBridge 171:3a7713b1edbc 211 {
AnnaBridge 171:3a7713b1edbc 212 uint32_t result;
AnnaBridge 171:3a7713b1edbc 213
AnnaBridge 171:3a7713b1edbc 214 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 215 return(result);
AnnaBridge 171:3a7713b1edbc 216 }
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218
AnnaBridge 171:3a7713b1edbc 219 /**
AnnaBridge 171:3a7713b1edbc 220 \brief Get xPSR Register
AnnaBridge 171:3a7713b1edbc 221 \details Returns the content of the xPSR Register.
AnnaBridge 171:3a7713b1edbc 222 \return xPSR Register value
AnnaBridge 171:3a7713b1edbc 223 */
AnnaBridge 171:3a7713b1edbc 224 __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
AnnaBridge 171:3a7713b1edbc 225 {
AnnaBridge 171:3a7713b1edbc 226 uint32_t result;
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 229 return(result);
AnnaBridge 171:3a7713b1edbc 230 }
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 /**
AnnaBridge 171:3a7713b1edbc 234 \brief Get Process Stack Pointer
AnnaBridge 171:3a7713b1edbc 235 \details Returns the current value of the Process Stack Pointer (PSP).
AnnaBridge 171:3a7713b1edbc 236 \return PSP Register value
AnnaBridge 171:3a7713b1edbc 237 */
AnnaBridge 171:3a7713b1edbc 238 __STATIC_FORCEINLINE uint32_t __get_PSP(void)
AnnaBridge 171:3a7713b1edbc 239 {
AnnaBridge 171:3a7713b1edbc 240 uint32_t result;
AnnaBridge 171:3a7713b1edbc 241
AnnaBridge 171:3a7713b1edbc 242 __ASM volatile ("MRS %0, psp" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 243 return(result);
AnnaBridge 171:3a7713b1edbc 244 }
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246
AnnaBridge 171:3a7713b1edbc 247 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 248 /**
AnnaBridge 171:3a7713b1edbc 249 \brief Get Process Stack Pointer (non-secure)
AnnaBridge 171:3a7713b1edbc 250 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge 171:3a7713b1edbc 251 \return PSP Register value
AnnaBridge 171:3a7713b1edbc 252 */
AnnaBridge 171:3a7713b1edbc 253 __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
AnnaBridge 171:3a7713b1edbc 254 {
AnnaBridge 171:3a7713b1edbc 255 uint32_t result;
AnnaBridge 171:3a7713b1edbc 256
AnnaBridge 171:3a7713b1edbc 257 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 258 return(result);
AnnaBridge 171:3a7713b1edbc 259 }
AnnaBridge 171:3a7713b1edbc 260 #endif
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 /**
AnnaBridge 171:3a7713b1edbc 264 \brief Set Process Stack Pointer
AnnaBridge 171:3a7713b1edbc 265 \details Assigns the given value to the Process Stack Pointer (PSP).
AnnaBridge 171:3a7713b1edbc 266 \param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge 171:3a7713b1edbc 267 */
AnnaBridge 171:3a7713b1edbc 268 __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 171:3a7713b1edbc 269 {
AnnaBridge 171:3a7713b1edbc 270 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
AnnaBridge 171:3a7713b1edbc 271 }
AnnaBridge 171:3a7713b1edbc 272
AnnaBridge 171:3a7713b1edbc 273
AnnaBridge 171:3a7713b1edbc 274 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 275 /**
AnnaBridge 171:3a7713b1edbc 276 \brief Set Process Stack Pointer (non-secure)
AnnaBridge 171:3a7713b1edbc 277 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge 171:3a7713b1edbc 278 \param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge 171:3a7713b1edbc 279 */
AnnaBridge 171:3a7713b1edbc 280 __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
AnnaBridge 171:3a7713b1edbc 281 {
AnnaBridge 171:3a7713b1edbc 282 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
AnnaBridge 171:3a7713b1edbc 283 }
AnnaBridge 171:3a7713b1edbc 284 #endif
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 /**
AnnaBridge 171:3a7713b1edbc 288 \brief Get Main Stack Pointer
AnnaBridge 171:3a7713b1edbc 289 \details Returns the current value of the Main Stack Pointer (MSP).
AnnaBridge 171:3a7713b1edbc 290 \return MSP Register value
AnnaBridge 171:3a7713b1edbc 291 */
AnnaBridge 171:3a7713b1edbc 292 __STATIC_FORCEINLINE uint32_t __get_MSP(void)
AnnaBridge 171:3a7713b1edbc 293 {
AnnaBridge 171:3a7713b1edbc 294 uint32_t result;
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 __ASM volatile ("MRS %0, msp" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 297 return(result);
AnnaBridge 171:3a7713b1edbc 298 }
AnnaBridge 171:3a7713b1edbc 299
AnnaBridge 171:3a7713b1edbc 300
AnnaBridge 171:3a7713b1edbc 301 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 302 /**
AnnaBridge 171:3a7713b1edbc 303 \brief Get Main Stack Pointer (non-secure)
AnnaBridge 171:3a7713b1edbc 304 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge 171:3a7713b1edbc 305 \return MSP Register value
AnnaBridge 171:3a7713b1edbc 306 */
AnnaBridge 171:3a7713b1edbc 307 __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
AnnaBridge 171:3a7713b1edbc 308 {
AnnaBridge 171:3a7713b1edbc 309 uint32_t result;
AnnaBridge 171:3a7713b1edbc 310
AnnaBridge 171:3a7713b1edbc 311 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 312 return(result);
AnnaBridge 171:3a7713b1edbc 313 }
AnnaBridge 171:3a7713b1edbc 314 #endif
AnnaBridge 171:3a7713b1edbc 315
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 /**
AnnaBridge 171:3a7713b1edbc 318 \brief Set Main Stack Pointer
AnnaBridge 171:3a7713b1edbc 319 \details Assigns the given value to the Main Stack Pointer (MSP).
AnnaBridge 171:3a7713b1edbc 320 \param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge 171:3a7713b1edbc 321 */
AnnaBridge 171:3a7713b1edbc 322 __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
AnnaBridge 171:3a7713b1edbc 323 {
AnnaBridge 171:3a7713b1edbc 324 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
AnnaBridge 171:3a7713b1edbc 325 }
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327
AnnaBridge 171:3a7713b1edbc 328 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 329 /**
AnnaBridge 171:3a7713b1edbc 330 \brief Set Main Stack Pointer (non-secure)
AnnaBridge 171:3a7713b1edbc 331 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge 171:3a7713b1edbc 332 \param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge 171:3a7713b1edbc 333 */
AnnaBridge 171:3a7713b1edbc 334 __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
AnnaBridge 171:3a7713b1edbc 335 {
AnnaBridge 171:3a7713b1edbc 336 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
AnnaBridge 171:3a7713b1edbc 337 }
AnnaBridge 171:3a7713b1edbc 338 #endif
AnnaBridge 171:3a7713b1edbc 339
AnnaBridge 171:3a7713b1edbc 340
AnnaBridge 171:3a7713b1edbc 341 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 342 /**
AnnaBridge 171:3a7713b1edbc 343 \brief Get Stack Pointer (non-secure)
AnnaBridge 171:3a7713b1edbc 344 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge 171:3a7713b1edbc 345 \return SP Register value
AnnaBridge 171:3a7713b1edbc 346 */
AnnaBridge 171:3a7713b1edbc 347 __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
AnnaBridge 171:3a7713b1edbc 348 {
AnnaBridge 171:3a7713b1edbc 349 uint32_t result;
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 352 return(result);
AnnaBridge 171:3a7713b1edbc 353 }
AnnaBridge 171:3a7713b1edbc 354
AnnaBridge 171:3a7713b1edbc 355
AnnaBridge 171:3a7713b1edbc 356 /**
AnnaBridge 171:3a7713b1edbc 357 \brief Set Stack Pointer (non-secure)
AnnaBridge 171:3a7713b1edbc 358 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge 171:3a7713b1edbc 359 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 171:3a7713b1edbc 360 */
AnnaBridge 171:3a7713b1edbc 361 __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
AnnaBridge 171:3a7713b1edbc 362 {
AnnaBridge 171:3a7713b1edbc 363 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
AnnaBridge 171:3a7713b1edbc 364 }
AnnaBridge 171:3a7713b1edbc 365 #endif
AnnaBridge 171:3a7713b1edbc 366
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 /**
AnnaBridge 171:3a7713b1edbc 369 \brief Get Priority Mask
AnnaBridge 171:3a7713b1edbc 370 \details Returns the current state of the priority mask bit from the Priority Mask Register.
AnnaBridge 171:3a7713b1edbc 371 \return Priority Mask value
AnnaBridge 171:3a7713b1edbc 372 */
AnnaBridge 171:3a7713b1edbc 373 __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
AnnaBridge 171:3a7713b1edbc 374 {
AnnaBridge 171:3a7713b1edbc 375 uint32_t result;
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 __ASM volatile ("MRS %0, primask" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 378 return(result);
AnnaBridge 171:3a7713b1edbc 379 }
AnnaBridge 171:3a7713b1edbc 380
AnnaBridge 171:3a7713b1edbc 381
AnnaBridge 171:3a7713b1edbc 382 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 383 /**
AnnaBridge 171:3a7713b1edbc 384 \brief Get Priority Mask (non-secure)
AnnaBridge 171:3a7713b1edbc 385 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
AnnaBridge 171:3a7713b1edbc 386 \return Priority Mask value
AnnaBridge 171:3a7713b1edbc 387 */
AnnaBridge 171:3a7713b1edbc 388 __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
AnnaBridge 171:3a7713b1edbc 389 {
AnnaBridge 171:3a7713b1edbc 390 uint32_t result;
AnnaBridge 171:3a7713b1edbc 391
AnnaBridge 171:3a7713b1edbc 392 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 393 return(result);
AnnaBridge 171:3a7713b1edbc 394 }
AnnaBridge 171:3a7713b1edbc 395 #endif
AnnaBridge 171:3a7713b1edbc 396
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 /**
AnnaBridge 171:3a7713b1edbc 399 \brief Set Priority Mask
AnnaBridge 171:3a7713b1edbc 400 \details Assigns the given value to the Priority Mask Register.
AnnaBridge 171:3a7713b1edbc 401 \param [in] priMask Priority Mask
AnnaBridge 171:3a7713b1edbc 402 */
AnnaBridge 171:3a7713b1edbc 403 __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
AnnaBridge 171:3a7713b1edbc 404 {
AnnaBridge 171:3a7713b1edbc 405 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
AnnaBridge 171:3a7713b1edbc 406 }
AnnaBridge 171:3a7713b1edbc 407
AnnaBridge 171:3a7713b1edbc 408
AnnaBridge 171:3a7713b1edbc 409 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 410 /**
AnnaBridge 171:3a7713b1edbc 411 \brief Set Priority Mask (non-secure)
AnnaBridge 171:3a7713b1edbc 412 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
AnnaBridge 171:3a7713b1edbc 413 \param [in] priMask Priority Mask
AnnaBridge 171:3a7713b1edbc 414 */
AnnaBridge 171:3a7713b1edbc 415 __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
AnnaBridge 171:3a7713b1edbc 416 {
AnnaBridge 171:3a7713b1edbc 417 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
AnnaBridge 171:3a7713b1edbc 418 }
AnnaBridge 171:3a7713b1edbc 419 #endif
AnnaBridge 171:3a7713b1edbc 420
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 423 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 424 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 171:3a7713b1edbc 425 /**
AnnaBridge 171:3a7713b1edbc 426 \brief Enable FIQ
AnnaBridge 171:3a7713b1edbc 427 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 171:3a7713b1edbc 428 Can only be executed in Privileged modes.
AnnaBridge 171:3a7713b1edbc 429 */
AnnaBridge 171:3a7713b1edbc 430 #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
AnnaBridge 171:3a7713b1edbc 431
AnnaBridge 171:3a7713b1edbc 432
AnnaBridge 171:3a7713b1edbc 433 /**
AnnaBridge 171:3a7713b1edbc 434 \brief Disable FIQ
AnnaBridge 171:3a7713b1edbc 435 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 171:3a7713b1edbc 436 Can only be executed in Privileged modes.
AnnaBridge 171:3a7713b1edbc 437 */
AnnaBridge 171:3a7713b1edbc 438 #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
AnnaBridge 171:3a7713b1edbc 439
AnnaBridge 171:3a7713b1edbc 440
AnnaBridge 171:3a7713b1edbc 441 /**
AnnaBridge 171:3a7713b1edbc 442 \brief Get Base Priority
AnnaBridge 171:3a7713b1edbc 443 \details Returns the current value of the Base Priority register.
AnnaBridge 171:3a7713b1edbc 444 \return Base Priority register value
AnnaBridge 171:3a7713b1edbc 445 */
AnnaBridge 171:3a7713b1edbc 446 __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
AnnaBridge 171:3a7713b1edbc 447 {
AnnaBridge 171:3a7713b1edbc 448 uint32_t result;
AnnaBridge 171:3a7713b1edbc 449
AnnaBridge 171:3a7713b1edbc 450 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 451 return(result);
AnnaBridge 171:3a7713b1edbc 452 }
AnnaBridge 171:3a7713b1edbc 453
AnnaBridge 171:3a7713b1edbc 454
AnnaBridge 171:3a7713b1edbc 455 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 456 /**
AnnaBridge 171:3a7713b1edbc 457 \brief Get Base Priority (non-secure)
AnnaBridge 171:3a7713b1edbc 458 \details Returns the current value of the non-secure Base Priority register when in secure state.
AnnaBridge 171:3a7713b1edbc 459 \return Base Priority register value
AnnaBridge 171:3a7713b1edbc 460 */
AnnaBridge 171:3a7713b1edbc 461 __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
AnnaBridge 171:3a7713b1edbc 462 {
AnnaBridge 171:3a7713b1edbc 463 uint32_t result;
AnnaBridge 171:3a7713b1edbc 464
AnnaBridge 171:3a7713b1edbc 465 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 466 return(result);
AnnaBridge 171:3a7713b1edbc 467 }
AnnaBridge 171:3a7713b1edbc 468 #endif
AnnaBridge 171:3a7713b1edbc 469
AnnaBridge 171:3a7713b1edbc 470
AnnaBridge 171:3a7713b1edbc 471 /**
AnnaBridge 171:3a7713b1edbc 472 \brief Set Base Priority
AnnaBridge 171:3a7713b1edbc 473 \details Assigns the given value to the Base Priority register.
AnnaBridge 171:3a7713b1edbc 474 \param [in] basePri Base Priority value to set
AnnaBridge 171:3a7713b1edbc 475 */
AnnaBridge 171:3a7713b1edbc 476 __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
AnnaBridge 171:3a7713b1edbc 477 {
AnnaBridge 171:3a7713b1edbc 478 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
AnnaBridge 171:3a7713b1edbc 479 }
AnnaBridge 171:3a7713b1edbc 480
AnnaBridge 171:3a7713b1edbc 481
AnnaBridge 171:3a7713b1edbc 482 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 483 /**
AnnaBridge 171:3a7713b1edbc 484 \brief Set Base Priority (non-secure)
AnnaBridge 171:3a7713b1edbc 485 \details Assigns the given value to the non-secure Base Priority register when in secure state.
AnnaBridge 171:3a7713b1edbc 486 \param [in] basePri Base Priority value to set
AnnaBridge 171:3a7713b1edbc 487 */
AnnaBridge 171:3a7713b1edbc 488 __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
AnnaBridge 171:3a7713b1edbc 489 {
AnnaBridge 171:3a7713b1edbc 490 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
AnnaBridge 171:3a7713b1edbc 491 }
AnnaBridge 171:3a7713b1edbc 492 #endif
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 /**
AnnaBridge 171:3a7713b1edbc 496 \brief Set Base Priority with condition
AnnaBridge 171:3a7713b1edbc 497 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
AnnaBridge 171:3a7713b1edbc 498 or the new value increases the BASEPRI priority level.
AnnaBridge 171:3a7713b1edbc 499 \param [in] basePri Base Priority value to set
AnnaBridge 171:3a7713b1edbc 500 */
AnnaBridge 171:3a7713b1edbc 501 __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
AnnaBridge 171:3a7713b1edbc 502 {
AnnaBridge 171:3a7713b1edbc 503 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
AnnaBridge 171:3a7713b1edbc 504 }
AnnaBridge 171:3a7713b1edbc 505
AnnaBridge 171:3a7713b1edbc 506
AnnaBridge 171:3a7713b1edbc 507 /**
AnnaBridge 171:3a7713b1edbc 508 \brief Get Fault Mask
AnnaBridge 171:3a7713b1edbc 509 \details Returns the current value of the Fault Mask register.
AnnaBridge 171:3a7713b1edbc 510 \return Fault Mask register value
AnnaBridge 171:3a7713b1edbc 511 */
AnnaBridge 171:3a7713b1edbc 512 __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
AnnaBridge 171:3a7713b1edbc 513 {
AnnaBridge 171:3a7713b1edbc 514 uint32_t result;
AnnaBridge 171:3a7713b1edbc 515
AnnaBridge 171:3a7713b1edbc 516 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 517 return(result);
AnnaBridge 171:3a7713b1edbc 518 }
AnnaBridge 171:3a7713b1edbc 519
AnnaBridge 171:3a7713b1edbc 520
AnnaBridge 171:3a7713b1edbc 521 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 522 /**
AnnaBridge 171:3a7713b1edbc 523 \brief Get Fault Mask (non-secure)
AnnaBridge 171:3a7713b1edbc 524 \details Returns the current value of the non-secure Fault Mask register when in secure state.
AnnaBridge 171:3a7713b1edbc 525 \return Fault Mask register value
AnnaBridge 171:3a7713b1edbc 526 */
AnnaBridge 171:3a7713b1edbc 527 __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
AnnaBridge 171:3a7713b1edbc 528 {
AnnaBridge 171:3a7713b1edbc 529 uint32_t result;
AnnaBridge 171:3a7713b1edbc 530
AnnaBridge 171:3a7713b1edbc 531 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 532 return(result);
AnnaBridge 171:3a7713b1edbc 533 }
AnnaBridge 171:3a7713b1edbc 534 #endif
AnnaBridge 171:3a7713b1edbc 535
AnnaBridge 171:3a7713b1edbc 536
AnnaBridge 171:3a7713b1edbc 537 /**
AnnaBridge 171:3a7713b1edbc 538 \brief Set Fault Mask
AnnaBridge 171:3a7713b1edbc 539 \details Assigns the given value to the Fault Mask register.
AnnaBridge 171:3a7713b1edbc 540 \param [in] faultMask Fault Mask value to set
AnnaBridge 171:3a7713b1edbc 541 */
AnnaBridge 171:3a7713b1edbc 542 __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
AnnaBridge 171:3a7713b1edbc 543 {
AnnaBridge 171:3a7713b1edbc 544 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
AnnaBridge 171:3a7713b1edbc 545 }
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547
AnnaBridge 171:3a7713b1edbc 548 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 549 /**
AnnaBridge 171:3a7713b1edbc 550 \brief Set Fault Mask (non-secure)
AnnaBridge 171:3a7713b1edbc 551 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
AnnaBridge 171:3a7713b1edbc 552 \param [in] faultMask Fault Mask value to set
AnnaBridge 171:3a7713b1edbc 553 */
AnnaBridge 171:3a7713b1edbc 554 __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
AnnaBridge 171:3a7713b1edbc 555 {
AnnaBridge 171:3a7713b1edbc 556 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
AnnaBridge 171:3a7713b1edbc 557 }
AnnaBridge 171:3a7713b1edbc 558 #endif
AnnaBridge 171:3a7713b1edbc 559
AnnaBridge 171:3a7713b1edbc 560 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 561 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 562 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 171:3a7713b1edbc 563
AnnaBridge 171:3a7713b1edbc 564
AnnaBridge 171:3a7713b1edbc 565 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 566 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 171:3a7713b1edbc 567
AnnaBridge 171:3a7713b1edbc 568 /**
AnnaBridge 171:3a7713b1edbc 569 \brief Get Process Stack Pointer Limit
AnnaBridge 171:3a7713b1edbc 570 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge 171:3a7713b1edbc 571 Stack Pointer Limit register hence zero is returned always in non-secure
AnnaBridge 171:3a7713b1edbc 572 mode.
AnnaBridge 171:3a7713b1edbc 573
AnnaBridge 171:3a7713b1edbc 574 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
AnnaBridge 171:3a7713b1edbc 575 \return PSPLIM Register value
AnnaBridge 171:3a7713b1edbc 576 */
AnnaBridge 171:3a7713b1edbc 577 __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
AnnaBridge 171:3a7713b1edbc 578 {
AnnaBridge 171:3a7713b1edbc 579 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
AnnaBridge 171:3a7713b1edbc 580 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
AnnaBridge 171:3a7713b1edbc 581 // without main extensions, the non-secure PSPLIM is RAZ/WI
AnnaBridge 171:3a7713b1edbc 582 return 0U;
AnnaBridge 171:3a7713b1edbc 583 #else
AnnaBridge 171:3a7713b1edbc 584 uint32_t result;
AnnaBridge 171:3a7713b1edbc 585 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 586 return result;
AnnaBridge 171:3a7713b1edbc 587 #endif
AnnaBridge 171:3a7713b1edbc 588 }
AnnaBridge 171:3a7713b1edbc 589
AnnaBridge 171:3a7713b1edbc 590 #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 591 /**
AnnaBridge 171:3a7713b1edbc 592 \brief Get Process Stack Pointer Limit (non-secure)
AnnaBridge 171:3a7713b1edbc 593 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge 171:3a7713b1edbc 594 Stack Pointer Limit register hence zero is returned always in non-secure
AnnaBridge 171:3a7713b1edbc 595 mode.
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge 171:3a7713b1edbc 598 \return PSPLIM Register value
AnnaBridge 171:3a7713b1edbc 599 */
AnnaBridge 171:3a7713b1edbc 600 __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
AnnaBridge 171:3a7713b1edbc 601 {
AnnaBridge 171:3a7713b1edbc 602 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
AnnaBridge 171:3a7713b1edbc 603 // without main extensions, the non-secure PSPLIM is RAZ/WI
AnnaBridge 171:3a7713b1edbc 604 return 0U;
AnnaBridge 171:3a7713b1edbc 605 #else
AnnaBridge 171:3a7713b1edbc 606 uint32_t result;
AnnaBridge 171:3a7713b1edbc 607 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 608 return result;
AnnaBridge 171:3a7713b1edbc 609 #endif
AnnaBridge 171:3a7713b1edbc 610 }
AnnaBridge 171:3a7713b1edbc 611 #endif
AnnaBridge 171:3a7713b1edbc 612
AnnaBridge 171:3a7713b1edbc 613
AnnaBridge 171:3a7713b1edbc 614 /**
AnnaBridge 171:3a7713b1edbc 615 \brief Set Process Stack Pointer Limit
AnnaBridge 171:3a7713b1edbc 616 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge 171:3a7713b1edbc 617 Stack Pointer Limit register hence the write is silently ignored in non-secure
AnnaBridge 171:3a7713b1edbc 618 mode.
AnnaBridge 171:3a7713b1edbc 619
AnnaBridge 171:3a7713b1edbc 620 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
AnnaBridge 171:3a7713b1edbc 621 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge 171:3a7713b1edbc 622 */
AnnaBridge 171:3a7713b1edbc 623 __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
AnnaBridge 171:3a7713b1edbc 624 {
AnnaBridge 171:3a7713b1edbc 625 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
AnnaBridge 171:3a7713b1edbc 626 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
AnnaBridge 171:3a7713b1edbc 627 // without main extensions, the non-secure PSPLIM is RAZ/WI
AnnaBridge 171:3a7713b1edbc 628 (void)ProcStackPtrLimit;
AnnaBridge 171:3a7713b1edbc 629 #else
AnnaBridge 171:3a7713b1edbc 630 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
AnnaBridge 171:3a7713b1edbc 631 #endif
AnnaBridge 171:3a7713b1edbc 632 }
AnnaBridge 171:3a7713b1edbc 633
AnnaBridge 171:3a7713b1edbc 634
AnnaBridge 171:3a7713b1edbc 635 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 636 /**
AnnaBridge 171:3a7713b1edbc 637 \brief Set Process Stack Pointer (non-secure)
AnnaBridge 171:3a7713b1edbc 638 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge 171:3a7713b1edbc 639 Stack Pointer Limit register hence the write is silently ignored in non-secure
AnnaBridge 171:3a7713b1edbc 640 mode.
AnnaBridge 171:3a7713b1edbc 641
AnnaBridge 171:3a7713b1edbc 642 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge 171:3a7713b1edbc 643 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge 171:3a7713b1edbc 644 */
AnnaBridge 171:3a7713b1edbc 645 __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
AnnaBridge 171:3a7713b1edbc 646 {
AnnaBridge 171:3a7713b1edbc 647 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
AnnaBridge 171:3a7713b1edbc 648 // without main extensions, the non-secure PSPLIM is RAZ/WI
AnnaBridge 171:3a7713b1edbc 649 (void)ProcStackPtrLimit;
AnnaBridge 171:3a7713b1edbc 650 #else
AnnaBridge 171:3a7713b1edbc 651 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
AnnaBridge 171:3a7713b1edbc 652 #endif
AnnaBridge 171:3a7713b1edbc 653 }
AnnaBridge 171:3a7713b1edbc 654 #endif
AnnaBridge 171:3a7713b1edbc 655
AnnaBridge 171:3a7713b1edbc 656
AnnaBridge 171:3a7713b1edbc 657 /**
AnnaBridge 171:3a7713b1edbc 658 \brief Get Main Stack Pointer Limit
AnnaBridge 171:3a7713b1edbc 659 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge 171:3a7713b1edbc 660 Stack Pointer Limit register hence zero is returned always.
AnnaBridge 171:3a7713b1edbc 661
AnnaBridge 171:3a7713b1edbc 662 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
AnnaBridge 171:3a7713b1edbc 663 \return MSPLIM Register value
AnnaBridge 171:3a7713b1edbc 664 */
AnnaBridge 171:3a7713b1edbc 665 __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
AnnaBridge 171:3a7713b1edbc 666 {
AnnaBridge 171:3a7713b1edbc 667 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
AnnaBridge 171:3a7713b1edbc 668 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
AnnaBridge 171:3a7713b1edbc 669 // without main extensions, the non-secure MSPLIM is RAZ/WI
AnnaBridge 171:3a7713b1edbc 670 return 0U;
AnnaBridge 171:3a7713b1edbc 671 #else
AnnaBridge 171:3a7713b1edbc 672 uint32_t result;
AnnaBridge 171:3a7713b1edbc 673 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 674 return result;
AnnaBridge 171:3a7713b1edbc 675 #endif
AnnaBridge 171:3a7713b1edbc 676 }
AnnaBridge 171:3a7713b1edbc 677
AnnaBridge 171:3a7713b1edbc 678
AnnaBridge 171:3a7713b1edbc 679 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 680 /**
AnnaBridge 171:3a7713b1edbc 681 \brief Get Main Stack Pointer Limit (non-secure)
AnnaBridge 171:3a7713b1edbc 682 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge 171:3a7713b1edbc 683 Stack Pointer Limit register hence zero is returned always.
AnnaBridge 171:3a7713b1edbc 684
AnnaBridge 171:3a7713b1edbc 685 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
AnnaBridge 171:3a7713b1edbc 686 \return MSPLIM Register value
AnnaBridge 171:3a7713b1edbc 687 */
AnnaBridge 171:3a7713b1edbc 688 __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
AnnaBridge 171:3a7713b1edbc 689 {
AnnaBridge 171:3a7713b1edbc 690 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
AnnaBridge 171:3a7713b1edbc 691 // without main extensions, the non-secure MSPLIM is RAZ/WI
AnnaBridge 171:3a7713b1edbc 692 return 0U;
AnnaBridge 171:3a7713b1edbc 693 #else
AnnaBridge 171:3a7713b1edbc 694 uint32_t result;
AnnaBridge 171:3a7713b1edbc 695 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
AnnaBridge 171:3a7713b1edbc 696 return result;
AnnaBridge 171:3a7713b1edbc 697 #endif
AnnaBridge 171:3a7713b1edbc 698 }
AnnaBridge 171:3a7713b1edbc 699 #endif
AnnaBridge 171:3a7713b1edbc 700
AnnaBridge 171:3a7713b1edbc 701
AnnaBridge 171:3a7713b1edbc 702 /**
AnnaBridge 171:3a7713b1edbc 703 \brief Set Main Stack Pointer Limit
AnnaBridge 171:3a7713b1edbc 704 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge 171:3a7713b1edbc 705 Stack Pointer Limit register hence the write is silently ignored.
AnnaBridge 171:3a7713b1edbc 706
AnnaBridge 171:3a7713b1edbc 707 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
AnnaBridge 171:3a7713b1edbc 708 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
AnnaBridge 171:3a7713b1edbc 709 */
AnnaBridge 171:3a7713b1edbc 710 __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
AnnaBridge 171:3a7713b1edbc 711 {
AnnaBridge 171:3a7713b1edbc 712 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
AnnaBridge 171:3a7713b1edbc 713 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
AnnaBridge 171:3a7713b1edbc 714 // without main extensions, the non-secure MSPLIM is RAZ/WI
AnnaBridge 171:3a7713b1edbc 715 (void)MainStackPtrLimit;
AnnaBridge 171:3a7713b1edbc 716 #else
AnnaBridge 171:3a7713b1edbc 717 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
AnnaBridge 171:3a7713b1edbc 718 #endif
AnnaBridge 171:3a7713b1edbc 719 }
AnnaBridge 171:3a7713b1edbc 720
AnnaBridge 171:3a7713b1edbc 721
AnnaBridge 171:3a7713b1edbc 722 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 171:3a7713b1edbc 723 /**
AnnaBridge 171:3a7713b1edbc 724 \brief Set Main Stack Pointer Limit (non-secure)
AnnaBridge 171:3a7713b1edbc 725 Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
AnnaBridge 171:3a7713b1edbc 726 Stack Pointer Limit register hence the write is silently ignored.
AnnaBridge 171:3a7713b1edbc 727
AnnaBridge 171:3a7713b1edbc 728 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
AnnaBridge 171:3a7713b1edbc 729 \param [in] MainStackPtrLimit Main Stack Pointer value to set
AnnaBridge 171:3a7713b1edbc 730 */
AnnaBridge 171:3a7713b1edbc 731 __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
AnnaBridge 171:3a7713b1edbc 732 {
AnnaBridge 171:3a7713b1edbc 733 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
AnnaBridge 171:3a7713b1edbc 734 // without main extensions, the non-secure MSPLIM is RAZ/WI
AnnaBridge 171:3a7713b1edbc 735 (void)MainStackPtrLimit;
AnnaBridge 171:3a7713b1edbc 736 #else
AnnaBridge 171:3a7713b1edbc 737 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
AnnaBridge 171:3a7713b1edbc 738 #endif
AnnaBridge 171:3a7713b1edbc 739 }
AnnaBridge 171:3a7713b1edbc 740 #endif
AnnaBridge 171:3a7713b1edbc 741
AnnaBridge 171:3a7713b1edbc 742 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 743 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 171:3a7713b1edbc 744
AnnaBridge 171:3a7713b1edbc 745 /**
AnnaBridge 171:3a7713b1edbc 746 \brief Get FPSCR
AnnaBridge 171:3a7713b1edbc 747 \details Returns the current value of the Floating Point Status/Control register.
AnnaBridge 171:3a7713b1edbc 748 \return Floating Point Status/Control register value
AnnaBridge 171:3a7713b1edbc 749 */
AnnaBridge 171:3a7713b1edbc 750 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 171:3a7713b1edbc 751 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 171:3a7713b1edbc 752 #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
AnnaBridge 171:3a7713b1edbc 753 #else
AnnaBridge 171:3a7713b1edbc 754 #define __get_FPSCR() ((uint32_t)0U)
AnnaBridge 171:3a7713b1edbc 755 #endif
AnnaBridge 171:3a7713b1edbc 756
AnnaBridge 171:3a7713b1edbc 757 /**
AnnaBridge 171:3a7713b1edbc 758 \brief Set FPSCR
AnnaBridge 171:3a7713b1edbc 759 \details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge 171:3a7713b1edbc 760 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 171:3a7713b1edbc 761 */
AnnaBridge 171:3a7713b1edbc 762 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 171:3a7713b1edbc 763 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
AnnaBridge 171:3a7713b1edbc 764 #define __set_FPSCR __builtin_arm_set_fpscr
AnnaBridge 171:3a7713b1edbc 765 #else
AnnaBridge 171:3a7713b1edbc 766 #define __set_FPSCR(x) ((void)(x))
AnnaBridge 171:3a7713b1edbc 767 #endif
AnnaBridge 171:3a7713b1edbc 768
AnnaBridge 171:3a7713b1edbc 769
AnnaBridge 171:3a7713b1edbc 770 /*@} end of CMSIS_Core_RegAccFunctions */
AnnaBridge 171:3a7713b1edbc 771
AnnaBridge 171:3a7713b1edbc 772
AnnaBridge 171:3a7713b1edbc 773 /* ########################## Core Instruction Access ######################### */
AnnaBridge 171:3a7713b1edbc 774 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
AnnaBridge 171:3a7713b1edbc 775 Access to dedicated instructions
AnnaBridge 171:3a7713b1edbc 776 @{
AnnaBridge 171:3a7713b1edbc 777 */
AnnaBridge 171:3a7713b1edbc 778
AnnaBridge 171:3a7713b1edbc 779 /* Define macros for porting to both thumb1 and thumb2.
AnnaBridge 171:3a7713b1edbc 780 * For thumb1, use low register (r0-r7), specified by constraint "l"
AnnaBridge 171:3a7713b1edbc 781 * Otherwise, use general registers, specified by constraint "r" */
AnnaBridge 171:3a7713b1edbc 782 #if defined (__thumb__) && !defined (__thumb2__)
AnnaBridge 171:3a7713b1edbc 783 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
AnnaBridge 171:3a7713b1edbc 784 #define __CMSIS_GCC_USE_REG(r) "l" (r)
AnnaBridge 171:3a7713b1edbc 785 #else
AnnaBridge 171:3a7713b1edbc 786 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
AnnaBridge 171:3a7713b1edbc 787 #define __CMSIS_GCC_USE_REG(r) "r" (r)
AnnaBridge 171:3a7713b1edbc 788 #endif
AnnaBridge 171:3a7713b1edbc 789
AnnaBridge 171:3a7713b1edbc 790 /**
AnnaBridge 171:3a7713b1edbc 791 \brief No Operation
AnnaBridge 171:3a7713b1edbc 792 \details No Operation does nothing. This instruction can be used for code alignment purposes.
AnnaBridge 171:3a7713b1edbc 793 */
AnnaBridge 171:3a7713b1edbc 794 #define __NOP __builtin_arm_nop
AnnaBridge 171:3a7713b1edbc 795
AnnaBridge 171:3a7713b1edbc 796 /**
AnnaBridge 171:3a7713b1edbc 797 \brief Wait For Interrupt
AnnaBridge 171:3a7713b1edbc 798 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
AnnaBridge 171:3a7713b1edbc 799 */
AnnaBridge 171:3a7713b1edbc 800 #define __WFI __builtin_arm_wfi
AnnaBridge 171:3a7713b1edbc 801
AnnaBridge 171:3a7713b1edbc 802
AnnaBridge 171:3a7713b1edbc 803 /**
AnnaBridge 171:3a7713b1edbc 804 \brief Wait For Event
AnnaBridge 171:3a7713b1edbc 805 \details Wait For Event is a hint instruction that permits the processor to enter
AnnaBridge 171:3a7713b1edbc 806 a low-power state until one of a number of events occurs.
AnnaBridge 171:3a7713b1edbc 807 */
AnnaBridge 171:3a7713b1edbc 808 #define __WFE __builtin_arm_wfe
AnnaBridge 171:3a7713b1edbc 809
AnnaBridge 171:3a7713b1edbc 810
AnnaBridge 171:3a7713b1edbc 811 /**
AnnaBridge 171:3a7713b1edbc 812 \brief Send Event
AnnaBridge 171:3a7713b1edbc 813 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
AnnaBridge 171:3a7713b1edbc 814 */
AnnaBridge 171:3a7713b1edbc 815 #define __SEV __builtin_arm_sev
AnnaBridge 171:3a7713b1edbc 816
AnnaBridge 171:3a7713b1edbc 817
AnnaBridge 171:3a7713b1edbc 818 /**
AnnaBridge 171:3a7713b1edbc 819 \brief Instruction Synchronization Barrier
AnnaBridge 171:3a7713b1edbc 820 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge 171:3a7713b1edbc 821 so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge 171:3a7713b1edbc 822 after the instruction has been completed.
AnnaBridge 171:3a7713b1edbc 823 */
AnnaBridge 171:3a7713b1edbc 824 #define __ISB() __builtin_arm_isb(0xF);
AnnaBridge 171:3a7713b1edbc 825
AnnaBridge 171:3a7713b1edbc 826 /**
AnnaBridge 171:3a7713b1edbc 827 \brief Data Synchronization Barrier
AnnaBridge 171:3a7713b1edbc 828 \details Acts as a special kind of Data Memory Barrier.
AnnaBridge 171:3a7713b1edbc 829 It completes when all explicit memory accesses before this instruction complete.
AnnaBridge 171:3a7713b1edbc 830 */
AnnaBridge 171:3a7713b1edbc 831 #define __DSB() __builtin_arm_dsb(0xF);
AnnaBridge 171:3a7713b1edbc 832
AnnaBridge 171:3a7713b1edbc 833
AnnaBridge 171:3a7713b1edbc 834 /**
AnnaBridge 171:3a7713b1edbc 835 \brief Data Memory Barrier
AnnaBridge 171:3a7713b1edbc 836 \details Ensures the apparent order of the explicit memory operations before
AnnaBridge 171:3a7713b1edbc 837 and after the instruction, without ensuring their completion.
AnnaBridge 171:3a7713b1edbc 838 */
AnnaBridge 171:3a7713b1edbc 839 #define __DMB() __builtin_arm_dmb(0xF);
AnnaBridge 171:3a7713b1edbc 840
AnnaBridge 171:3a7713b1edbc 841
AnnaBridge 171:3a7713b1edbc 842 /**
AnnaBridge 171:3a7713b1edbc 843 \brief Reverse byte order (32 bit)
AnnaBridge 171:3a7713b1edbc 844 \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
AnnaBridge 171:3a7713b1edbc 845 \param [in] value Value to reverse
AnnaBridge 171:3a7713b1edbc 846 \return Reversed value
AnnaBridge 171:3a7713b1edbc 847 */
AnnaBridge 171:3a7713b1edbc 848 #define __REV(value) __builtin_bswap32(value)
AnnaBridge 171:3a7713b1edbc 849
AnnaBridge 171:3a7713b1edbc 850
AnnaBridge 171:3a7713b1edbc 851 /**
AnnaBridge 171:3a7713b1edbc 852 \brief Reverse byte order (16 bit)
AnnaBridge 171:3a7713b1edbc 853 \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
AnnaBridge 171:3a7713b1edbc 854 \param [in] value Value to reverse
AnnaBridge 171:3a7713b1edbc 855 \return Reversed value
AnnaBridge 171:3a7713b1edbc 856 */
AnnaBridge 171:3a7713b1edbc 857 #define __REV16(value) __ROR(__REV(value), 16)
AnnaBridge 171:3a7713b1edbc 858
AnnaBridge 171:3a7713b1edbc 859
AnnaBridge 171:3a7713b1edbc 860 /**
AnnaBridge 171:3a7713b1edbc 861 \brief Reverse byte order (16 bit)
AnnaBridge 171:3a7713b1edbc 862 \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
AnnaBridge 171:3a7713b1edbc 863 \param [in] value Value to reverse
AnnaBridge 171:3a7713b1edbc 864 \return Reversed value
AnnaBridge 171:3a7713b1edbc 865 */
AnnaBridge 171:3a7713b1edbc 866 #define __REVSH(value) (int16_t)__builtin_bswap16(value)
AnnaBridge 171:3a7713b1edbc 867
AnnaBridge 171:3a7713b1edbc 868
AnnaBridge 171:3a7713b1edbc 869 /**
AnnaBridge 171:3a7713b1edbc 870 \brief Rotate Right in unsigned value (32 bit)
AnnaBridge 171:3a7713b1edbc 871 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge 171:3a7713b1edbc 872 \param [in] op1 Value to rotate
AnnaBridge 171:3a7713b1edbc 873 \param [in] op2 Number of Bits to rotate
AnnaBridge 171:3a7713b1edbc 874 \return Rotated value
AnnaBridge 171:3a7713b1edbc 875 */
AnnaBridge 171:3a7713b1edbc 876 __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 877 {
AnnaBridge 171:3a7713b1edbc 878 op2 %= 32U;
AnnaBridge 171:3a7713b1edbc 879 if (op2 == 0U)
AnnaBridge 171:3a7713b1edbc 880 {
AnnaBridge 171:3a7713b1edbc 881 return op1;
AnnaBridge 171:3a7713b1edbc 882 }
AnnaBridge 171:3a7713b1edbc 883 return (op1 >> op2) | (op1 << (32U - op2));
AnnaBridge 171:3a7713b1edbc 884 }
AnnaBridge 171:3a7713b1edbc 885
AnnaBridge 171:3a7713b1edbc 886
AnnaBridge 171:3a7713b1edbc 887 /**
AnnaBridge 171:3a7713b1edbc 888 \brief Breakpoint
AnnaBridge 171:3a7713b1edbc 889 \details Causes the processor to enter Debug state.
AnnaBridge 171:3a7713b1edbc 890 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
AnnaBridge 171:3a7713b1edbc 891 \param [in] value is ignored by the processor.
AnnaBridge 171:3a7713b1edbc 892 If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge 171:3a7713b1edbc 893 */
AnnaBridge 171:3a7713b1edbc 894 #define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge 171:3a7713b1edbc 895
AnnaBridge 171:3a7713b1edbc 896
AnnaBridge 171:3a7713b1edbc 897 /**
AnnaBridge 171:3a7713b1edbc 898 \brief Reverse bit order of value
AnnaBridge 171:3a7713b1edbc 899 \details Reverses the bit order of the given value.
AnnaBridge 171:3a7713b1edbc 900 \param [in] value Value to reverse
AnnaBridge 171:3a7713b1edbc 901 \return Reversed value
AnnaBridge 171:3a7713b1edbc 902 */
AnnaBridge 171:3a7713b1edbc 903 #define __RBIT __builtin_arm_rbit
AnnaBridge 171:3a7713b1edbc 904
AnnaBridge 171:3a7713b1edbc 905 /**
AnnaBridge 171:3a7713b1edbc 906 \brief Count leading zeros
AnnaBridge 171:3a7713b1edbc 907 \details Counts the number of leading zeros of a data value.
AnnaBridge 171:3a7713b1edbc 908 \param [in] value Value to count the leading zeros
AnnaBridge 171:3a7713b1edbc 909 \return number of leading zeros in value
AnnaBridge 171:3a7713b1edbc 910 */
AnnaBridge 171:3a7713b1edbc 911 #define __CLZ (uint8_t)__builtin_clz
AnnaBridge 171:3a7713b1edbc 912
AnnaBridge 171:3a7713b1edbc 913
AnnaBridge 171:3a7713b1edbc 914 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 915 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 916 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 917 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 171:3a7713b1edbc 918 /**
AnnaBridge 171:3a7713b1edbc 919 \brief LDR Exclusive (8 bit)
AnnaBridge 171:3a7713b1edbc 920 \details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge 171:3a7713b1edbc 921 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 922 \return value of type uint8_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 923 */
AnnaBridge 171:3a7713b1edbc 924 #define __LDREXB (uint8_t)__builtin_arm_ldrex
AnnaBridge 171:3a7713b1edbc 925
AnnaBridge 171:3a7713b1edbc 926
AnnaBridge 171:3a7713b1edbc 927 /**
AnnaBridge 171:3a7713b1edbc 928 \brief LDR Exclusive (16 bit)
AnnaBridge 171:3a7713b1edbc 929 \details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge 171:3a7713b1edbc 930 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 931 \return value of type uint16_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 932 */
AnnaBridge 171:3a7713b1edbc 933 #define __LDREXH (uint16_t)__builtin_arm_ldrex
AnnaBridge 171:3a7713b1edbc 934
AnnaBridge 171:3a7713b1edbc 935
AnnaBridge 171:3a7713b1edbc 936 /**
AnnaBridge 171:3a7713b1edbc 937 \brief LDR Exclusive (32 bit)
AnnaBridge 171:3a7713b1edbc 938 \details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge 171:3a7713b1edbc 939 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 940 \return value of type uint32_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 941 */
AnnaBridge 171:3a7713b1edbc 942 #define __LDREXW (uint32_t)__builtin_arm_ldrex
AnnaBridge 171:3a7713b1edbc 943
AnnaBridge 171:3a7713b1edbc 944
AnnaBridge 171:3a7713b1edbc 945 /**
AnnaBridge 171:3a7713b1edbc 946 \brief STR Exclusive (8 bit)
AnnaBridge 171:3a7713b1edbc 947 \details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge 171:3a7713b1edbc 948 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 949 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 950 \return 0 Function succeeded
AnnaBridge 171:3a7713b1edbc 951 \return 1 Function failed
AnnaBridge 171:3a7713b1edbc 952 */
AnnaBridge 171:3a7713b1edbc 953 #define __STREXB (uint32_t)__builtin_arm_strex
AnnaBridge 171:3a7713b1edbc 954
AnnaBridge 171:3a7713b1edbc 955
AnnaBridge 171:3a7713b1edbc 956 /**
AnnaBridge 171:3a7713b1edbc 957 \brief STR Exclusive (16 bit)
AnnaBridge 171:3a7713b1edbc 958 \details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge 171:3a7713b1edbc 959 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 960 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 961 \return 0 Function succeeded
AnnaBridge 171:3a7713b1edbc 962 \return 1 Function failed
AnnaBridge 171:3a7713b1edbc 963 */
AnnaBridge 171:3a7713b1edbc 964 #define __STREXH (uint32_t)__builtin_arm_strex
AnnaBridge 171:3a7713b1edbc 965
AnnaBridge 171:3a7713b1edbc 966
AnnaBridge 171:3a7713b1edbc 967 /**
AnnaBridge 171:3a7713b1edbc 968 \brief STR Exclusive (32 bit)
AnnaBridge 171:3a7713b1edbc 969 \details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge 171:3a7713b1edbc 970 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 971 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 972 \return 0 Function succeeded
AnnaBridge 171:3a7713b1edbc 973 \return 1 Function failed
AnnaBridge 171:3a7713b1edbc 974 */
AnnaBridge 171:3a7713b1edbc 975 #define __STREXW (uint32_t)__builtin_arm_strex
AnnaBridge 171:3a7713b1edbc 976
AnnaBridge 171:3a7713b1edbc 977
AnnaBridge 171:3a7713b1edbc 978 /**
AnnaBridge 171:3a7713b1edbc 979 \brief Remove the exclusive lock
AnnaBridge 171:3a7713b1edbc 980 \details Removes the exclusive lock which is created by LDREX.
AnnaBridge 171:3a7713b1edbc 981 */
AnnaBridge 171:3a7713b1edbc 982 #define __CLREX __builtin_arm_clrex
AnnaBridge 171:3a7713b1edbc 983
AnnaBridge 171:3a7713b1edbc 984 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 985 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 986 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 987 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 171:3a7713b1edbc 988
AnnaBridge 171:3a7713b1edbc 989
AnnaBridge 171:3a7713b1edbc 990 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 991 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 992 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 171:3a7713b1edbc 993
AnnaBridge 171:3a7713b1edbc 994 /**
AnnaBridge 171:3a7713b1edbc 995 \brief Signed Saturate
AnnaBridge 171:3a7713b1edbc 996 \details Saturates a signed value.
AnnaBridge 171:3a7713b1edbc 997 \param [in] value Value to be saturated
AnnaBridge 171:3a7713b1edbc 998 \param [in] sat Bit position to saturate to (1..32)
AnnaBridge 171:3a7713b1edbc 999 \return Saturated value
AnnaBridge 171:3a7713b1edbc 1000 */
AnnaBridge 171:3a7713b1edbc 1001 #define __SSAT __builtin_arm_ssat
AnnaBridge 171:3a7713b1edbc 1002
AnnaBridge 171:3a7713b1edbc 1003
AnnaBridge 171:3a7713b1edbc 1004 /**
AnnaBridge 171:3a7713b1edbc 1005 \brief Unsigned Saturate
AnnaBridge 171:3a7713b1edbc 1006 \details Saturates an unsigned value.
AnnaBridge 171:3a7713b1edbc 1007 \param [in] value Value to be saturated
AnnaBridge 171:3a7713b1edbc 1008 \param [in] sat Bit position to saturate to (0..31)
AnnaBridge 171:3a7713b1edbc 1009 \return Saturated value
AnnaBridge 171:3a7713b1edbc 1010 */
AnnaBridge 171:3a7713b1edbc 1011 #define __USAT __builtin_arm_usat
AnnaBridge 171:3a7713b1edbc 1012
AnnaBridge 171:3a7713b1edbc 1013
AnnaBridge 171:3a7713b1edbc 1014 /**
AnnaBridge 171:3a7713b1edbc 1015 \brief Rotate Right with Extend (32 bit)
AnnaBridge 171:3a7713b1edbc 1016 \details Moves each bit of a bitstring right by one bit.
AnnaBridge 171:3a7713b1edbc 1017 The carry input is shifted in at the left end of the bitstring.
AnnaBridge 171:3a7713b1edbc 1018 \param [in] value Value to rotate
AnnaBridge 171:3a7713b1edbc 1019 \return Rotated value
AnnaBridge 171:3a7713b1edbc 1020 */
AnnaBridge 171:3a7713b1edbc 1021 __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
AnnaBridge 171:3a7713b1edbc 1022 {
AnnaBridge 171:3a7713b1edbc 1023 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1024
AnnaBridge 171:3a7713b1edbc 1025 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 171:3a7713b1edbc 1026 return(result);
AnnaBridge 171:3a7713b1edbc 1027 }
AnnaBridge 171:3a7713b1edbc 1028
AnnaBridge 171:3a7713b1edbc 1029
AnnaBridge 171:3a7713b1edbc 1030 /**
AnnaBridge 171:3a7713b1edbc 1031 \brief LDRT Unprivileged (8 bit)
AnnaBridge 171:3a7713b1edbc 1032 \details Executes a Unprivileged LDRT instruction for 8 bit value.
AnnaBridge 171:3a7713b1edbc 1033 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 1034 \return value of type uint8_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 1035 */
AnnaBridge 171:3a7713b1edbc 1036 __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
AnnaBridge 171:3a7713b1edbc 1037 {
AnnaBridge 171:3a7713b1edbc 1038 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1039
AnnaBridge 171:3a7713b1edbc 1040 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 171:3a7713b1edbc 1041 return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge 171:3a7713b1edbc 1042 }
AnnaBridge 171:3a7713b1edbc 1043
AnnaBridge 171:3a7713b1edbc 1044
AnnaBridge 171:3a7713b1edbc 1045 /**
AnnaBridge 171:3a7713b1edbc 1046 \brief LDRT Unprivileged (16 bit)
AnnaBridge 171:3a7713b1edbc 1047 \details Executes a Unprivileged LDRT instruction for 16 bit values.
AnnaBridge 171:3a7713b1edbc 1048 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 1049 \return value of type uint16_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 1050 */
AnnaBridge 171:3a7713b1edbc 1051 __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
AnnaBridge 171:3a7713b1edbc 1052 {
AnnaBridge 171:3a7713b1edbc 1053 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1054
AnnaBridge 171:3a7713b1edbc 1055 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 171:3a7713b1edbc 1056 return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge 171:3a7713b1edbc 1057 }
AnnaBridge 171:3a7713b1edbc 1058
AnnaBridge 171:3a7713b1edbc 1059
AnnaBridge 171:3a7713b1edbc 1060 /**
AnnaBridge 171:3a7713b1edbc 1061 \brief LDRT Unprivileged (32 bit)
AnnaBridge 171:3a7713b1edbc 1062 \details Executes a Unprivileged LDRT instruction for 32 bit values.
AnnaBridge 171:3a7713b1edbc 1063 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 1064 \return value of type uint32_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 1065 */
AnnaBridge 171:3a7713b1edbc 1066 __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
AnnaBridge 171:3a7713b1edbc 1067 {
AnnaBridge 171:3a7713b1edbc 1068 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1069
AnnaBridge 171:3a7713b1edbc 1070 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 171:3a7713b1edbc 1071 return(result);
AnnaBridge 171:3a7713b1edbc 1072 }
AnnaBridge 171:3a7713b1edbc 1073
AnnaBridge 171:3a7713b1edbc 1074
AnnaBridge 171:3a7713b1edbc 1075 /**
AnnaBridge 171:3a7713b1edbc 1076 \brief STRT Unprivileged (8 bit)
AnnaBridge 171:3a7713b1edbc 1077 \details Executes a Unprivileged STRT instruction for 8 bit values.
AnnaBridge 171:3a7713b1edbc 1078 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 1079 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 1080 */
AnnaBridge 171:3a7713b1edbc 1081 __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
AnnaBridge 171:3a7713b1edbc 1082 {
AnnaBridge 171:3a7713b1edbc 1083 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 171:3a7713b1edbc 1084 }
AnnaBridge 171:3a7713b1edbc 1085
AnnaBridge 171:3a7713b1edbc 1086
AnnaBridge 171:3a7713b1edbc 1087 /**
AnnaBridge 171:3a7713b1edbc 1088 \brief STRT Unprivileged (16 bit)
AnnaBridge 171:3a7713b1edbc 1089 \details Executes a Unprivileged STRT instruction for 16 bit values.
AnnaBridge 171:3a7713b1edbc 1090 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 1091 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 1092 */
AnnaBridge 171:3a7713b1edbc 1093 __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
AnnaBridge 171:3a7713b1edbc 1094 {
AnnaBridge 171:3a7713b1edbc 1095 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 171:3a7713b1edbc 1096 }
AnnaBridge 171:3a7713b1edbc 1097
AnnaBridge 171:3a7713b1edbc 1098
AnnaBridge 171:3a7713b1edbc 1099 /**
AnnaBridge 171:3a7713b1edbc 1100 \brief STRT Unprivileged (32 bit)
AnnaBridge 171:3a7713b1edbc 1101 \details Executes a Unprivileged STRT instruction for 32 bit values.
AnnaBridge 171:3a7713b1edbc 1102 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 1103 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 1104 */
AnnaBridge 171:3a7713b1edbc 1105 __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
AnnaBridge 171:3a7713b1edbc 1106 {
AnnaBridge 171:3a7713b1edbc 1107 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
AnnaBridge 171:3a7713b1edbc 1108 }
AnnaBridge 171:3a7713b1edbc 1109
AnnaBridge 171:3a7713b1edbc 1110 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 1111 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 1112 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 171:3a7713b1edbc 1113
AnnaBridge 171:3a7713b1edbc 1114 /**
AnnaBridge 171:3a7713b1edbc 1115 \brief Signed Saturate
AnnaBridge 171:3a7713b1edbc 1116 \details Saturates a signed value.
AnnaBridge 171:3a7713b1edbc 1117 \param [in] value Value to be saturated
AnnaBridge 171:3a7713b1edbc 1118 \param [in] sat Bit position to saturate to (1..32)
AnnaBridge 171:3a7713b1edbc 1119 \return Saturated value
AnnaBridge 171:3a7713b1edbc 1120 */
AnnaBridge 171:3a7713b1edbc 1121 __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
AnnaBridge 171:3a7713b1edbc 1122 {
AnnaBridge 171:3a7713b1edbc 1123 if ((sat >= 1U) && (sat <= 32U))
AnnaBridge 171:3a7713b1edbc 1124 {
AnnaBridge 171:3a7713b1edbc 1125 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
AnnaBridge 171:3a7713b1edbc 1126 const int32_t min = -1 - max ;
AnnaBridge 171:3a7713b1edbc 1127 if (val > max)
AnnaBridge 171:3a7713b1edbc 1128 {
AnnaBridge 171:3a7713b1edbc 1129 return max;
AnnaBridge 171:3a7713b1edbc 1130 }
AnnaBridge 171:3a7713b1edbc 1131 else if (val < min)
AnnaBridge 171:3a7713b1edbc 1132 {
AnnaBridge 171:3a7713b1edbc 1133 return min;
AnnaBridge 171:3a7713b1edbc 1134 }
AnnaBridge 171:3a7713b1edbc 1135 }
AnnaBridge 171:3a7713b1edbc 1136 return val;
AnnaBridge 171:3a7713b1edbc 1137 }
AnnaBridge 171:3a7713b1edbc 1138
AnnaBridge 171:3a7713b1edbc 1139 /**
AnnaBridge 171:3a7713b1edbc 1140 \brief Unsigned Saturate
AnnaBridge 171:3a7713b1edbc 1141 \details Saturates an unsigned value.
AnnaBridge 171:3a7713b1edbc 1142 \param [in] value Value to be saturated
AnnaBridge 171:3a7713b1edbc 1143 \param [in] sat Bit position to saturate to (0..31)
AnnaBridge 171:3a7713b1edbc 1144 \return Saturated value
AnnaBridge 171:3a7713b1edbc 1145 */
AnnaBridge 171:3a7713b1edbc 1146 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
AnnaBridge 171:3a7713b1edbc 1147 {
AnnaBridge 171:3a7713b1edbc 1148 if (sat <= 31U)
AnnaBridge 171:3a7713b1edbc 1149 {
AnnaBridge 171:3a7713b1edbc 1150 const uint32_t max = ((1U << sat) - 1U);
AnnaBridge 171:3a7713b1edbc 1151 if (val > (int32_t)max)
AnnaBridge 171:3a7713b1edbc 1152 {
AnnaBridge 171:3a7713b1edbc 1153 return max;
AnnaBridge 171:3a7713b1edbc 1154 }
AnnaBridge 171:3a7713b1edbc 1155 else if (val < 0)
AnnaBridge 171:3a7713b1edbc 1156 {
AnnaBridge 171:3a7713b1edbc 1157 return 0U;
AnnaBridge 171:3a7713b1edbc 1158 }
AnnaBridge 171:3a7713b1edbc 1159 }
AnnaBridge 171:3a7713b1edbc 1160 return (uint32_t)val;
AnnaBridge 171:3a7713b1edbc 1161 }
AnnaBridge 171:3a7713b1edbc 1162
AnnaBridge 171:3a7713b1edbc 1163 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 1164 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 1165 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 171:3a7713b1edbc 1166
AnnaBridge 171:3a7713b1edbc 1167
AnnaBridge 171:3a7713b1edbc 1168 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 1169 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 171:3a7713b1edbc 1170 /**
AnnaBridge 171:3a7713b1edbc 1171 \brief Load-Acquire (8 bit)
AnnaBridge 171:3a7713b1edbc 1172 \details Executes a LDAB instruction for 8 bit value.
AnnaBridge 171:3a7713b1edbc 1173 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 1174 \return value of type uint8_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 1175 */
AnnaBridge 171:3a7713b1edbc 1176 __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
AnnaBridge 171:3a7713b1edbc 1177 {
AnnaBridge 171:3a7713b1edbc 1178 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1179
AnnaBridge 171:3a7713b1edbc 1180 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 171:3a7713b1edbc 1181 return ((uint8_t) result);
AnnaBridge 171:3a7713b1edbc 1182 }
AnnaBridge 171:3a7713b1edbc 1183
AnnaBridge 171:3a7713b1edbc 1184
AnnaBridge 171:3a7713b1edbc 1185 /**
AnnaBridge 171:3a7713b1edbc 1186 \brief Load-Acquire (16 bit)
AnnaBridge 171:3a7713b1edbc 1187 \details Executes a LDAH instruction for 16 bit values.
AnnaBridge 171:3a7713b1edbc 1188 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 1189 \return value of type uint16_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 1190 */
AnnaBridge 171:3a7713b1edbc 1191 __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
AnnaBridge 171:3a7713b1edbc 1192 {
AnnaBridge 171:3a7713b1edbc 1193 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1194
AnnaBridge 171:3a7713b1edbc 1195 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 171:3a7713b1edbc 1196 return ((uint16_t) result);
AnnaBridge 171:3a7713b1edbc 1197 }
AnnaBridge 171:3a7713b1edbc 1198
AnnaBridge 171:3a7713b1edbc 1199
AnnaBridge 171:3a7713b1edbc 1200 /**
AnnaBridge 171:3a7713b1edbc 1201 \brief Load-Acquire (32 bit)
AnnaBridge 171:3a7713b1edbc 1202 \details Executes a LDA instruction for 32 bit values.
AnnaBridge 171:3a7713b1edbc 1203 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 1204 \return value of type uint32_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 1205 */
AnnaBridge 171:3a7713b1edbc 1206 __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
AnnaBridge 171:3a7713b1edbc 1207 {
AnnaBridge 171:3a7713b1edbc 1208 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1209
AnnaBridge 171:3a7713b1edbc 1210 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 171:3a7713b1edbc 1211 return(result);
AnnaBridge 171:3a7713b1edbc 1212 }
AnnaBridge 171:3a7713b1edbc 1213
AnnaBridge 171:3a7713b1edbc 1214
AnnaBridge 171:3a7713b1edbc 1215 /**
AnnaBridge 171:3a7713b1edbc 1216 \brief Store-Release (8 bit)
AnnaBridge 171:3a7713b1edbc 1217 \details Executes a STLB instruction for 8 bit values.
AnnaBridge 171:3a7713b1edbc 1218 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 1219 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 1220 */
AnnaBridge 171:3a7713b1edbc 1221 __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge 171:3a7713b1edbc 1222 {
AnnaBridge 171:3a7713b1edbc 1223 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 171:3a7713b1edbc 1224 }
AnnaBridge 171:3a7713b1edbc 1225
AnnaBridge 171:3a7713b1edbc 1226
AnnaBridge 171:3a7713b1edbc 1227 /**
AnnaBridge 171:3a7713b1edbc 1228 \brief Store-Release (16 bit)
AnnaBridge 171:3a7713b1edbc 1229 \details Executes a STLH instruction for 16 bit values.
AnnaBridge 171:3a7713b1edbc 1230 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 1231 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 1232 */
AnnaBridge 171:3a7713b1edbc 1233 __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge 171:3a7713b1edbc 1234 {
AnnaBridge 171:3a7713b1edbc 1235 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 171:3a7713b1edbc 1236 }
AnnaBridge 171:3a7713b1edbc 1237
AnnaBridge 171:3a7713b1edbc 1238
AnnaBridge 171:3a7713b1edbc 1239 /**
AnnaBridge 171:3a7713b1edbc 1240 \brief Store-Release (32 bit)
AnnaBridge 171:3a7713b1edbc 1241 \details Executes a STL instruction for 32 bit values.
AnnaBridge 171:3a7713b1edbc 1242 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 1243 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 1244 */
AnnaBridge 171:3a7713b1edbc 1245 __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
AnnaBridge 171:3a7713b1edbc 1246 {
AnnaBridge 171:3a7713b1edbc 1247 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 171:3a7713b1edbc 1248 }
AnnaBridge 171:3a7713b1edbc 1249
AnnaBridge 171:3a7713b1edbc 1250
AnnaBridge 171:3a7713b1edbc 1251 /**
AnnaBridge 171:3a7713b1edbc 1252 \brief Load-Acquire Exclusive (8 bit)
AnnaBridge 171:3a7713b1edbc 1253 \details Executes a LDAB exclusive instruction for 8 bit value.
AnnaBridge 171:3a7713b1edbc 1254 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 1255 \return value of type uint8_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 1256 */
AnnaBridge 171:3a7713b1edbc 1257 #define __LDAEXB (uint8_t)__builtin_arm_ldaex
AnnaBridge 171:3a7713b1edbc 1258
AnnaBridge 171:3a7713b1edbc 1259
AnnaBridge 171:3a7713b1edbc 1260 /**
AnnaBridge 171:3a7713b1edbc 1261 \brief Load-Acquire Exclusive (16 bit)
AnnaBridge 171:3a7713b1edbc 1262 \details Executes a LDAH exclusive instruction for 16 bit values.
AnnaBridge 171:3a7713b1edbc 1263 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 1264 \return value of type uint16_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 1265 */
AnnaBridge 171:3a7713b1edbc 1266 #define __LDAEXH (uint16_t)__builtin_arm_ldaex
AnnaBridge 171:3a7713b1edbc 1267
AnnaBridge 171:3a7713b1edbc 1268
AnnaBridge 171:3a7713b1edbc 1269 /**
AnnaBridge 171:3a7713b1edbc 1270 \brief Load-Acquire Exclusive (32 bit)
AnnaBridge 171:3a7713b1edbc 1271 \details Executes a LDA exclusive instruction for 32 bit values.
AnnaBridge 171:3a7713b1edbc 1272 \param [in] ptr Pointer to data
AnnaBridge 171:3a7713b1edbc 1273 \return value of type uint32_t at (*ptr)
AnnaBridge 171:3a7713b1edbc 1274 */
AnnaBridge 171:3a7713b1edbc 1275 #define __LDAEX (uint32_t)__builtin_arm_ldaex
AnnaBridge 171:3a7713b1edbc 1276
AnnaBridge 171:3a7713b1edbc 1277
AnnaBridge 171:3a7713b1edbc 1278 /**
AnnaBridge 171:3a7713b1edbc 1279 \brief Store-Release Exclusive (8 bit)
AnnaBridge 171:3a7713b1edbc 1280 \details Executes a STLB exclusive instruction for 8 bit values.
AnnaBridge 171:3a7713b1edbc 1281 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 1282 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 1283 \return 0 Function succeeded
AnnaBridge 171:3a7713b1edbc 1284 \return 1 Function failed
AnnaBridge 171:3a7713b1edbc 1285 */
AnnaBridge 171:3a7713b1edbc 1286 #define __STLEXB (uint32_t)__builtin_arm_stlex
AnnaBridge 171:3a7713b1edbc 1287
AnnaBridge 171:3a7713b1edbc 1288
AnnaBridge 171:3a7713b1edbc 1289 /**
AnnaBridge 171:3a7713b1edbc 1290 \brief Store-Release Exclusive (16 bit)
AnnaBridge 171:3a7713b1edbc 1291 \details Executes a STLH exclusive instruction for 16 bit values.
AnnaBridge 171:3a7713b1edbc 1292 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 1293 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 1294 \return 0 Function succeeded
AnnaBridge 171:3a7713b1edbc 1295 \return 1 Function failed
AnnaBridge 171:3a7713b1edbc 1296 */
AnnaBridge 171:3a7713b1edbc 1297 #define __STLEXH (uint32_t)__builtin_arm_stlex
AnnaBridge 171:3a7713b1edbc 1298
AnnaBridge 171:3a7713b1edbc 1299
AnnaBridge 171:3a7713b1edbc 1300 /**
AnnaBridge 171:3a7713b1edbc 1301 \brief Store-Release Exclusive (32 bit)
AnnaBridge 171:3a7713b1edbc 1302 \details Executes a STL exclusive instruction for 32 bit values.
AnnaBridge 171:3a7713b1edbc 1303 \param [in] value Value to store
AnnaBridge 171:3a7713b1edbc 1304 \param [in] ptr Pointer to location
AnnaBridge 171:3a7713b1edbc 1305 \return 0 Function succeeded
AnnaBridge 171:3a7713b1edbc 1306 \return 1 Function failed
AnnaBridge 171:3a7713b1edbc 1307 */
AnnaBridge 171:3a7713b1edbc 1308 #define __STLEX (uint32_t)__builtin_arm_stlex
AnnaBridge 171:3a7713b1edbc 1309
AnnaBridge 171:3a7713b1edbc 1310 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 171:3a7713b1edbc 1311 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 171:3a7713b1edbc 1312
AnnaBridge 171:3a7713b1edbc 1313 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
AnnaBridge 171:3a7713b1edbc 1314
AnnaBridge 171:3a7713b1edbc 1315
AnnaBridge 171:3a7713b1edbc 1316 /* ################### Compiler specific Intrinsics ########################### */
AnnaBridge 171:3a7713b1edbc 1317 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
AnnaBridge 171:3a7713b1edbc 1318 Access to dedicated SIMD instructions
AnnaBridge 171:3a7713b1edbc 1319 @{
AnnaBridge 171:3a7713b1edbc 1320 */
AnnaBridge 171:3a7713b1edbc 1321
AnnaBridge 171:3a7713b1edbc 1322 #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
AnnaBridge 171:3a7713b1edbc 1323
AnnaBridge 171:3a7713b1edbc 1324 __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1325 {
AnnaBridge 171:3a7713b1edbc 1326 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1327
AnnaBridge 171:3a7713b1edbc 1328 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1329 return(result);
AnnaBridge 171:3a7713b1edbc 1330 }
AnnaBridge 171:3a7713b1edbc 1331
AnnaBridge 171:3a7713b1edbc 1332 __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1333 {
AnnaBridge 171:3a7713b1edbc 1334 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1335
AnnaBridge 171:3a7713b1edbc 1336 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1337 return(result);
AnnaBridge 171:3a7713b1edbc 1338 }
AnnaBridge 171:3a7713b1edbc 1339
AnnaBridge 171:3a7713b1edbc 1340 __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1341 {
AnnaBridge 171:3a7713b1edbc 1342 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1343
AnnaBridge 171:3a7713b1edbc 1344 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1345 return(result);
AnnaBridge 171:3a7713b1edbc 1346 }
AnnaBridge 171:3a7713b1edbc 1347
AnnaBridge 171:3a7713b1edbc 1348 __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1349 {
AnnaBridge 171:3a7713b1edbc 1350 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1351
AnnaBridge 171:3a7713b1edbc 1352 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1353 return(result);
AnnaBridge 171:3a7713b1edbc 1354 }
AnnaBridge 171:3a7713b1edbc 1355
AnnaBridge 171:3a7713b1edbc 1356 __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1357 {
AnnaBridge 171:3a7713b1edbc 1358 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1359
AnnaBridge 171:3a7713b1edbc 1360 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1361 return(result);
AnnaBridge 171:3a7713b1edbc 1362 }
AnnaBridge 171:3a7713b1edbc 1363
AnnaBridge 171:3a7713b1edbc 1364 __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1365 {
AnnaBridge 171:3a7713b1edbc 1366 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1367
AnnaBridge 171:3a7713b1edbc 1368 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1369 return(result);
AnnaBridge 171:3a7713b1edbc 1370 }
AnnaBridge 171:3a7713b1edbc 1371
AnnaBridge 171:3a7713b1edbc 1372
AnnaBridge 171:3a7713b1edbc 1373 __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1374 {
AnnaBridge 171:3a7713b1edbc 1375 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1376
AnnaBridge 171:3a7713b1edbc 1377 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1378 return(result);
AnnaBridge 171:3a7713b1edbc 1379 }
AnnaBridge 171:3a7713b1edbc 1380
AnnaBridge 171:3a7713b1edbc 1381 __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1382 {
AnnaBridge 171:3a7713b1edbc 1383 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1384
AnnaBridge 171:3a7713b1edbc 1385 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1386 return(result);
AnnaBridge 171:3a7713b1edbc 1387 }
AnnaBridge 171:3a7713b1edbc 1388
AnnaBridge 171:3a7713b1edbc 1389 __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1390 {
AnnaBridge 171:3a7713b1edbc 1391 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1392
AnnaBridge 171:3a7713b1edbc 1393 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1394 return(result);
AnnaBridge 171:3a7713b1edbc 1395 }
AnnaBridge 171:3a7713b1edbc 1396
AnnaBridge 171:3a7713b1edbc 1397 __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1398 {
AnnaBridge 171:3a7713b1edbc 1399 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1400
AnnaBridge 171:3a7713b1edbc 1401 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1402 return(result);
AnnaBridge 171:3a7713b1edbc 1403 }
AnnaBridge 171:3a7713b1edbc 1404
AnnaBridge 171:3a7713b1edbc 1405 __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1406 {
AnnaBridge 171:3a7713b1edbc 1407 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1408
AnnaBridge 171:3a7713b1edbc 1409 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1410 return(result);
AnnaBridge 171:3a7713b1edbc 1411 }
AnnaBridge 171:3a7713b1edbc 1412
AnnaBridge 171:3a7713b1edbc 1413 __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1414 {
AnnaBridge 171:3a7713b1edbc 1415 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1416
AnnaBridge 171:3a7713b1edbc 1417 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1418 return(result);
AnnaBridge 171:3a7713b1edbc 1419 }
AnnaBridge 171:3a7713b1edbc 1420
AnnaBridge 171:3a7713b1edbc 1421
AnnaBridge 171:3a7713b1edbc 1422 __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1423 {
AnnaBridge 171:3a7713b1edbc 1424 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1425
AnnaBridge 171:3a7713b1edbc 1426 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1427 return(result);
AnnaBridge 171:3a7713b1edbc 1428 }
AnnaBridge 171:3a7713b1edbc 1429
AnnaBridge 171:3a7713b1edbc 1430 __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1431 {
AnnaBridge 171:3a7713b1edbc 1432 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1433
AnnaBridge 171:3a7713b1edbc 1434 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1435 return(result);
AnnaBridge 171:3a7713b1edbc 1436 }
AnnaBridge 171:3a7713b1edbc 1437
AnnaBridge 171:3a7713b1edbc 1438 __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1439 {
AnnaBridge 171:3a7713b1edbc 1440 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1441
AnnaBridge 171:3a7713b1edbc 1442 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1443 return(result);
AnnaBridge 171:3a7713b1edbc 1444 }
AnnaBridge 171:3a7713b1edbc 1445
AnnaBridge 171:3a7713b1edbc 1446 __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1447 {
AnnaBridge 171:3a7713b1edbc 1448 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1449
AnnaBridge 171:3a7713b1edbc 1450 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1451 return(result);
AnnaBridge 171:3a7713b1edbc 1452 }
AnnaBridge 171:3a7713b1edbc 1453
AnnaBridge 171:3a7713b1edbc 1454 __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1455 {
AnnaBridge 171:3a7713b1edbc 1456 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1457
AnnaBridge 171:3a7713b1edbc 1458 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1459 return(result);
AnnaBridge 171:3a7713b1edbc 1460 }
AnnaBridge 171:3a7713b1edbc 1461
AnnaBridge 171:3a7713b1edbc 1462 __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1463 {
AnnaBridge 171:3a7713b1edbc 1464 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1465
AnnaBridge 171:3a7713b1edbc 1466 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1467 return(result);
AnnaBridge 171:3a7713b1edbc 1468 }
AnnaBridge 171:3a7713b1edbc 1469
AnnaBridge 171:3a7713b1edbc 1470 __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1471 {
AnnaBridge 171:3a7713b1edbc 1472 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1473
AnnaBridge 171:3a7713b1edbc 1474 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1475 return(result);
AnnaBridge 171:3a7713b1edbc 1476 }
AnnaBridge 171:3a7713b1edbc 1477
AnnaBridge 171:3a7713b1edbc 1478 __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1479 {
AnnaBridge 171:3a7713b1edbc 1480 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1481
AnnaBridge 171:3a7713b1edbc 1482 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1483 return(result);
AnnaBridge 171:3a7713b1edbc 1484 }
AnnaBridge 171:3a7713b1edbc 1485
AnnaBridge 171:3a7713b1edbc 1486 __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1487 {
AnnaBridge 171:3a7713b1edbc 1488 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1489
AnnaBridge 171:3a7713b1edbc 1490 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1491 return(result);
AnnaBridge 171:3a7713b1edbc 1492 }
AnnaBridge 171:3a7713b1edbc 1493
AnnaBridge 171:3a7713b1edbc 1494 __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1495 {
AnnaBridge 171:3a7713b1edbc 1496 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1497
AnnaBridge 171:3a7713b1edbc 1498 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1499 return(result);
AnnaBridge 171:3a7713b1edbc 1500 }
AnnaBridge 171:3a7713b1edbc 1501
AnnaBridge 171:3a7713b1edbc 1502 __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1503 {
AnnaBridge 171:3a7713b1edbc 1504 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1505
AnnaBridge 171:3a7713b1edbc 1506 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1507 return(result);
AnnaBridge 171:3a7713b1edbc 1508 }
AnnaBridge 171:3a7713b1edbc 1509
AnnaBridge 171:3a7713b1edbc 1510 __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1511 {
AnnaBridge 171:3a7713b1edbc 1512 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1513
AnnaBridge 171:3a7713b1edbc 1514 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1515 return(result);
AnnaBridge 171:3a7713b1edbc 1516 }
AnnaBridge 171:3a7713b1edbc 1517
AnnaBridge 171:3a7713b1edbc 1518 __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1519 {
AnnaBridge 171:3a7713b1edbc 1520 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1521
AnnaBridge 171:3a7713b1edbc 1522 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1523 return(result);
AnnaBridge 171:3a7713b1edbc 1524 }
AnnaBridge 171:3a7713b1edbc 1525
AnnaBridge 171:3a7713b1edbc 1526 __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1527 {
AnnaBridge 171:3a7713b1edbc 1528 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1529
AnnaBridge 171:3a7713b1edbc 1530 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1531 return(result);
AnnaBridge 171:3a7713b1edbc 1532 }
AnnaBridge 171:3a7713b1edbc 1533
AnnaBridge 171:3a7713b1edbc 1534 __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1535 {
AnnaBridge 171:3a7713b1edbc 1536 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1537
AnnaBridge 171:3a7713b1edbc 1538 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1539 return(result);
AnnaBridge 171:3a7713b1edbc 1540 }
AnnaBridge 171:3a7713b1edbc 1541
AnnaBridge 171:3a7713b1edbc 1542 __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1543 {
AnnaBridge 171:3a7713b1edbc 1544 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1545
AnnaBridge 171:3a7713b1edbc 1546 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1547 return(result);
AnnaBridge 171:3a7713b1edbc 1548 }
AnnaBridge 171:3a7713b1edbc 1549
AnnaBridge 171:3a7713b1edbc 1550 __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1551 {
AnnaBridge 171:3a7713b1edbc 1552 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1553
AnnaBridge 171:3a7713b1edbc 1554 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1555 return(result);
AnnaBridge 171:3a7713b1edbc 1556 }
AnnaBridge 171:3a7713b1edbc 1557
AnnaBridge 171:3a7713b1edbc 1558 __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1559 {
AnnaBridge 171:3a7713b1edbc 1560 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1561
AnnaBridge 171:3a7713b1edbc 1562 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1563 return(result);
AnnaBridge 171:3a7713b1edbc 1564 }
AnnaBridge 171:3a7713b1edbc 1565
AnnaBridge 171:3a7713b1edbc 1566 __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1567 {
AnnaBridge 171:3a7713b1edbc 1568 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1569
AnnaBridge 171:3a7713b1edbc 1570 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1571 return(result);
AnnaBridge 171:3a7713b1edbc 1572 }
AnnaBridge 171:3a7713b1edbc 1573
AnnaBridge 171:3a7713b1edbc 1574 __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1575 {
AnnaBridge 171:3a7713b1edbc 1576 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1577
AnnaBridge 171:3a7713b1edbc 1578 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1579 return(result);
AnnaBridge 171:3a7713b1edbc 1580 }
AnnaBridge 171:3a7713b1edbc 1581
AnnaBridge 171:3a7713b1edbc 1582 __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1583 {
AnnaBridge 171:3a7713b1edbc 1584 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1585
AnnaBridge 171:3a7713b1edbc 1586 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1587 return(result);
AnnaBridge 171:3a7713b1edbc 1588 }
AnnaBridge 171:3a7713b1edbc 1589
AnnaBridge 171:3a7713b1edbc 1590 __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1591 {
AnnaBridge 171:3a7713b1edbc 1592 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1593
AnnaBridge 171:3a7713b1edbc 1594 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1595 return(result);
AnnaBridge 171:3a7713b1edbc 1596 }
AnnaBridge 171:3a7713b1edbc 1597
AnnaBridge 171:3a7713b1edbc 1598 __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1599 {
AnnaBridge 171:3a7713b1edbc 1600 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1601
AnnaBridge 171:3a7713b1edbc 1602 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1603 return(result);
AnnaBridge 171:3a7713b1edbc 1604 }
AnnaBridge 171:3a7713b1edbc 1605
AnnaBridge 171:3a7713b1edbc 1606 __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1607 {
AnnaBridge 171:3a7713b1edbc 1608 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1609
AnnaBridge 171:3a7713b1edbc 1610 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1611 return(result);
AnnaBridge 171:3a7713b1edbc 1612 }
AnnaBridge 171:3a7713b1edbc 1613
AnnaBridge 171:3a7713b1edbc 1614 __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1615 {
AnnaBridge 171:3a7713b1edbc 1616 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1617
AnnaBridge 171:3a7713b1edbc 1618 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1619 return(result);
AnnaBridge 171:3a7713b1edbc 1620 }
AnnaBridge 171:3a7713b1edbc 1621
AnnaBridge 171:3a7713b1edbc 1622 __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 171:3a7713b1edbc 1623 {
AnnaBridge 171:3a7713b1edbc 1624 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1625
AnnaBridge 171:3a7713b1edbc 1626 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 171:3a7713b1edbc 1627 return(result);
AnnaBridge 171:3a7713b1edbc 1628 }
AnnaBridge 171:3a7713b1edbc 1629
AnnaBridge 171:3a7713b1edbc 1630 #define __SSAT16(ARG1,ARG2) \
AnnaBridge 171:3a7713b1edbc 1631 ({ \
AnnaBridge 171:3a7713b1edbc 1632 int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 171:3a7713b1edbc 1633 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 171:3a7713b1edbc 1634 __RES; \
AnnaBridge 171:3a7713b1edbc 1635 })
AnnaBridge 171:3a7713b1edbc 1636
AnnaBridge 171:3a7713b1edbc 1637 #define __USAT16(ARG1,ARG2) \
AnnaBridge 171:3a7713b1edbc 1638 ({ \
AnnaBridge 171:3a7713b1edbc 1639 uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 171:3a7713b1edbc 1640 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 171:3a7713b1edbc 1641 __RES; \
AnnaBridge 171:3a7713b1edbc 1642 })
AnnaBridge 171:3a7713b1edbc 1643
AnnaBridge 171:3a7713b1edbc 1644 __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
AnnaBridge 171:3a7713b1edbc 1645 {
AnnaBridge 171:3a7713b1edbc 1646 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1647
AnnaBridge 171:3a7713b1edbc 1648 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge 171:3a7713b1edbc 1649 return(result);
AnnaBridge 171:3a7713b1edbc 1650 }
AnnaBridge 171:3a7713b1edbc 1651
AnnaBridge 171:3a7713b1edbc 1652 __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1653 {
AnnaBridge 171:3a7713b1edbc 1654 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1655
AnnaBridge 171:3a7713b1edbc 1656 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1657 return(result);
AnnaBridge 171:3a7713b1edbc 1658 }
AnnaBridge 171:3a7713b1edbc 1659
AnnaBridge 171:3a7713b1edbc 1660 __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
AnnaBridge 171:3a7713b1edbc 1661 {
AnnaBridge 171:3a7713b1edbc 1662 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1663
AnnaBridge 171:3a7713b1edbc 1664 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge 171:3a7713b1edbc 1665 return(result);
AnnaBridge 171:3a7713b1edbc 1666 }
AnnaBridge 171:3a7713b1edbc 1667
AnnaBridge 171:3a7713b1edbc 1668 __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1669 {
AnnaBridge 171:3a7713b1edbc 1670 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1671
AnnaBridge 171:3a7713b1edbc 1672 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1673 return(result);
AnnaBridge 171:3a7713b1edbc 1674 }
AnnaBridge 171:3a7713b1edbc 1675
AnnaBridge 171:3a7713b1edbc 1676 __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1677 {
AnnaBridge 171:3a7713b1edbc 1678 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1679
AnnaBridge 171:3a7713b1edbc 1680 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1681 return(result);
AnnaBridge 171:3a7713b1edbc 1682 }
AnnaBridge 171:3a7713b1edbc 1683
AnnaBridge 171:3a7713b1edbc 1684 __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1685 {
AnnaBridge 171:3a7713b1edbc 1686 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1687
AnnaBridge 171:3a7713b1edbc 1688 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1689 return(result);
AnnaBridge 171:3a7713b1edbc 1690 }
AnnaBridge 171:3a7713b1edbc 1691
AnnaBridge 171:3a7713b1edbc 1692 __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 171:3a7713b1edbc 1693 {
AnnaBridge 171:3a7713b1edbc 1694 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1695
AnnaBridge 171:3a7713b1edbc 1696 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 171:3a7713b1edbc 1697 return(result);
AnnaBridge 171:3a7713b1edbc 1698 }
AnnaBridge 171:3a7713b1edbc 1699
AnnaBridge 171:3a7713b1edbc 1700 __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 171:3a7713b1edbc 1701 {
AnnaBridge 171:3a7713b1edbc 1702 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1703
AnnaBridge 171:3a7713b1edbc 1704 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 171:3a7713b1edbc 1705 return(result);
AnnaBridge 171:3a7713b1edbc 1706 }
AnnaBridge 171:3a7713b1edbc 1707
AnnaBridge 171:3a7713b1edbc 1708 __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 171:3a7713b1edbc 1709 {
AnnaBridge 171:3a7713b1edbc 1710 union llreg_u{
AnnaBridge 171:3a7713b1edbc 1711 uint32_t w32[2];
AnnaBridge 171:3a7713b1edbc 1712 uint64_t w64;
AnnaBridge 171:3a7713b1edbc 1713 } llr;
AnnaBridge 171:3a7713b1edbc 1714 llr.w64 = acc;
AnnaBridge 171:3a7713b1edbc 1715
AnnaBridge 171:3a7713b1edbc 1716 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 171:3a7713b1edbc 1717 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 171:3a7713b1edbc 1718 #else /* Big endian */
AnnaBridge 171:3a7713b1edbc 1719 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 171:3a7713b1edbc 1720 #endif
AnnaBridge 171:3a7713b1edbc 1721
AnnaBridge 171:3a7713b1edbc 1722 return(llr.w64);
AnnaBridge 171:3a7713b1edbc 1723 }
AnnaBridge 171:3a7713b1edbc 1724
AnnaBridge 171:3a7713b1edbc 1725 __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 171:3a7713b1edbc 1726 {
AnnaBridge 171:3a7713b1edbc 1727 union llreg_u{
AnnaBridge 171:3a7713b1edbc 1728 uint32_t w32[2];
AnnaBridge 171:3a7713b1edbc 1729 uint64_t w64;
AnnaBridge 171:3a7713b1edbc 1730 } llr;
AnnaBridge 171:3a7713b1edbc 1731 llr.w64 = acc;
AnnaBridge 171:3a7713b1edbc 1732
AnnaBridge 171:3a7713b1edbc 1733 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 171:3a7713b1edbc 1734 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 171:3a7713b1edbc 1735 #else /* Big endian */
AnnaBridge 171:3a7713b1edbc 1736 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 171:3a7713b1edbc 1737 #endif
AnnaBridge 171:3a7713b1edbc 1738
AnnaBridge 171:3a7713b1edbc 1739 return(llr.w64);
AnnaBridge 171:3a7713b1edbc 1740 }
AnnaBridge 171:3a7713b1edbc 1741
AnnaBridge 171:3a7713b1edbc 1742 __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1743 {
AnnaBridge 171:3a7713b1edbc 1744 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1745
AnnaBridge 171:3a7713b1edbc 1746 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1747 return(result);
AnnaBridge 171:3a7713b1edbc 1748 }
AnnaBridge 171:3a7713b1edbc 1749
AnnaBridge 171:3a7713b1edbc 1750 __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1751 {
AnnaBridge 171:3a7713b1edbc 1752 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1753
AnnaBridge 171:3a7713b1edbc 1754 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1755 return(result);
AnnaBridge 171:3a7713b1edbc 1756 }
AnnaBridge 171:3a7713b1edbc 1757
AnnaBridge 171:3a7713b1edbc 1758 __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 171:3a7713b1edbc 1759 {
AnnaBridge 171:3a7713b1edbc 1760 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1761
AnnaBridge 171:3a7713b1edbc 1762 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 171:3a7713b1edbc 1763 return(result);
AnnaBridge 171:3a7713b1edbc 1764 }
AnnaBridge 171:3a7713b1edbc 1765
AnnaBridge 171:3a7713b1edbc 1766 __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 171:3a7713b1edbc 1767 {
AnnaBridge 171:3a7713b1edbc 1768 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1769
AnnaBridge 171:3a7713b1edbc 1770 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 171:3a7713b1edbc 1771 return(result);
AnnaBridge 171:3a7713b1edbc 1772 }
AnnaBridge 171:3a7713b1edbc 1773
AnnaBridge 171:3a7713b1edbc 1774 __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 171:3a7713b1edbc 1775 {
AnnaBridge 171:3a7713b1edbc 1776 union llreg_u{
AnnaBridge 171:3a7713b1edbc 1777 uint32_t w32[2];
AnnaBridge 171:3a7713b1edbc 1778 uint64_t w64;
AnnaBridge 171:3a7713b1edbc 1779 } llr;
AnnaBridge 171:3a7713b1edbc 1780 llr.w64 = acc;
AnnaBridge 171:3a7713b1edbc 1781
AnnaBridge 171:3a7713b1edbc 1782 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 171:3a7713b1edbc 1783 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 171:3a7713b1edbc 1784 #else /* Big endian */
AnnaBridge 171:3a7713b1edbc 1785 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 171:3a7713b1edbc 1786 #endif
AnnaBridge 171:3a7713b1edbc 1787
AnnaBridge 171:3a7713b1edbc 1788 return(llr.w64);
AnnaBridge 171:3a7713b1edbc 1789 }
AnnaBridge 171:3a7713b1edbc 1790
AnnaBridge 171:3a7713b1edbc 1791 __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 171:3a7713b1edbc 1792 {
AnnaBridge 171:3a7713b1edbc 1793 union llreg_u{
AnnaBridge 171:3a7713b1edbc 1794 uint32_t w32[2];
AnnaBridge 171:3a7713b1edbc 1795 uint64_t w64;
AnnaBridge 171:3a7713b1edbc 1796 } llr;
AnnaBridge 171:3a7713b1edbc 1797 llr.w64 = acc;
AnnaBridge 171:3a7713b1edbc 1798
AnnaBridge 171:3a7713b1edbc 1799 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 171:3a7713b1edbc 1800 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 171:3a7713b1edbc 1801 #else /* Big endian */
AnnaBridge 171:3a7713b1edbc 1802 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 171:3a7713b1edbc 1803 #endif
AnnaBridge 171:3a7713b1edbc 1804
AnnaBridge 171:3a7713b1edbc 1805 return(llr.w64);
AnnaBridge 171:3a7713b1edbc 1806 }
AnnaBridge 171:3a7713b1edbc 1807
AnnaBridge 171:3a7713b1edbc 1808 __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
AnnaBridge 171:3a7713b1edbc 1809 {
AnnaBridge 171:3a7713b1edbc 1810 uint32_t result;
AnnaBridge 171:3a7713b1edbc 1811
AnnaBridge 171:3a7713b1edbc 1812 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1813 return(result);
AnnaBridge 171:3a7713b1edbc 1814 }
AnnaBridge 171:3a7713b1edbc 1815
AnnaBridge 171:3a7713b1edbc 1816 __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
AnnaBridge 171:3a7713b1edbc 1817 {
AnnaBridge 171:3a7713b1edbc 1818 int32_t result;
AnnaBridge 171:3a7713b1edbc 1819
AnnaBridge 171:3a7713b1edbc 1820 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1821 return(result);
AnnaBridge 171:3a7713b1edbc 1822 }
AnnaBridge 171:3a7713b1edbc 1823
AnnaBridge 171:3a7713b1edbc 1824 __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
AnnaBridge 171:3a7713b1edbc 1825 {
AnnaBridge 171:3a7713b1edbc 1826 int32_t result;
AnnaBridge 171:3a7713b1edbc 1827
AnnaBridge 171:3a7713b1edbc 1828 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 171:3a7713b1edbc 1829 return(result);
AnnaBridge 171:3a7713b1edbc 1830 }
AnnaBridge 171:3a7713b1edbc 1831
AnnaBridge 171:3a7713b1edbc 1832 #if 0
AnnaBridge 171:3a7713b1edbc 1833 #define __PKHBT(ARG1,ARG2,ARG3) \
AnnaBridge 171:3a7713b1edbc 1834 ({ \
AnnaBridge 171:3a7713b1edbc 1835 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge 171:3a7713b1edbc 1836 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge 171:3a7713b1edbc 1837 __RES; \
AnnaBridge 171:3a7713b1edbc 1838 })
AnnaBridge 171:3a7713b1edbc 1839
AnnaBridge 171:3a7713b1edbc 1840 #define __PKHTB(ARG1,ARG2,ARG3) \
AnnaBridge 171:3a7713b1edbc 1841 ({ \
AnnaBridge 171:3a7713b1edbc 1842 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge 171:3a7713b1edbc 1843 if (ARG3 == 0) \
AnnaBridge 171:3a7713b1edbc 1844 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
AnnaBridge 171:3a7713b1edbc 1845 else \
AnnaBridge 171:3a7713b1edbc 1846 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge 171:3a7713b1edbc 1847 __RES; \
AnnaBridge 171:3a7713b1edbc 1848 })
AnnaBridge 171:3a7713b1edbc 1849 #endif
AnnaBridge 171:3a7713b1edbc 1850
AnnaBridge 171:3a7713b1edbc 1851 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
AnnaBridge 171:3a7713b1edbc 1852 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
AnnaBridge 171:3a7713b1edbc 1853
AnnaBridge 171:3a7713b1edbc 1854 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
AnnaBridge 171:3a7713b1edbc 1855 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
AnnaBridge 171:3a7713b1edbc 1856
AnnaBridge 171:3a7713b1edbc 1857 __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
AnnaBridge 171:3a7713b1edbc 1858 {
AnnaBridge 171:3a7713b1edbc 1859 int32_t result;
AnnaBridge 171:3a7713b1edbc 1860
AnnaBridge 171:3a7713b1edbc 1861 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 171:3a7713b1edbc 1862 return(result);
AnnaBridge 171:3a7713b1edbc 1863 }
AnnaBridge 171:3a7713b1edbc 1864
AnnaBridge 171:3a7713b1edbc 1865 #endif /* (__ARM_FEATURE_DSP == 1) */
AnnaBridge 171:3a7713b1edbc 1866 /*@} end of group CMSIS_SIMD_intrinsics */
AnnaBridge 171:3a7713b1edbc 1867
AnnaBridge 171:3a7713b1edbc 1868
AnnaBridge 171:3a7713b1edbc 1869 #endif /* __CMSIS_ARMCLANG_H */