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TARGET_LPC812/TOOLCHAIN_ARM_MICRO/LPC8xx.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /****************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
AnnaBridge 171:3a7713b1edbc 3 * Project: NXP LPC8xx software example
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 * Description:
AnnaBridge 171:3a7713b1edbc 6 * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
AnnaBridge 171:3a7713b1edbc 7 * NXP LPC800 Device Series
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 ****************************************************************************
AnnaBridge 171:3a7713b1edbc 10 * Software that is described herein is for illustrative purposes only
AnnaBridge 171:3a7713b1edbc 11 * which provides customers with programming information regarding the
AnnaBridge 171:3a7713b1edbc 12 * products. This software is supplied "AS IS" without any warranties.
AnnaBridge 171:3a7713b1edbc 13 * NXP Semiconductors assumes no responsibility or liability for the
AnnaBridge 171:3a7713b1edbc 14 * use of the software, conveys no license or title under any patent,
AnnaBridge 171:3a7713b1edbc 15 * copyright, or mask work right to the product. NXP Semiconductors
AnnaBridge 171:3a7713b1edbc 16 * reserves the right to make changes in the software without
AnnaBridge 171:3a7713b1edbc 17 * notification. NXP Semiconductors also make no representation or
AnnaBridge 171:3a7713b1edbc 18 * warranty that such application will be suitable for the specified
AnnaBridge 171:3a7713b1edbc 19 * use without further testing or modification.
AnnaBridge 171:3a7713b1edbc 20
AnnaBridge 171:3a7713b1edbc 21 * Permission to use, copy, modify, and distribute this software and its
AnnaBridge 171:3a7713b1edbc 22 * documentation is hereby granted, under NXP Semiconductors'
AnnaBridge 171:3a7713b1edbc 23 * relevant copyright in the software, without fee, provided that it
AnnaBridge 171:3a7713b1edbc 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
AnnaBridge 171:3a7713b1edbc 25 * copyright, permission, and disclaimer notice must appear in all copies of
AnnaBridge 171:3a7713b1edbc 26 * this code.
AnnaBridge 171:3a7713b1edbc 27 ****************************************************************************/
AnnaBridge 171:3a7713b1edbc 28 #ifndef __LPC8xx_H__
AnnaBridge 171:3a7713b1edbc 29 #define __LPC8xx_H__
AnnaBridge 171:3a7713b1edbc 30
AnnaBridge 171:3a7713b1edbc 31 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 32 extern "C" {
AnnaBridge 171:3a7713b1edbc 33 #endif
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35 /** @addtogroup LPC8xx_Definitions LPC8xx Definitions
AnnaBridge 171:3a7713b1edbc 36 This file defines all structures and symbols for LPC8xx:
AnnaBridge 171:3a7713b1edbc 37 - Registers and bitfields
AnnaBridge 171:3a7713b1edbc 38 - peripheral base address
AnnaBridge 171:3a7713b1edbc 39 - PIO definitions
AnnaBridge 171:3a7713b1edbc 40 @{
AnnaBridge 171:3a7713b1edbc 41 */
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 45 /* Processor and Core Peripherals */
AnnaBridge 171:3a7713b1edbc 46 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
AnnaBridge 171:3a7713b1edbc 48 Configuration of the Cortex-M0+ Processor and Core Peripherals
AnnaBridge 171:3a7713b1edbc 49 @{
AnnaBridge 171:3a7713b1edbc 50 */
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 /*
AnnaBridge 171:3a7713b1edbc 53 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 54 * ---------- Interrupt Number Definition -----------------------------------
AnnaBridge 171:3a7713b1edbc 55 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 56 */
AnnaBridge 171:3a7713b1edbc 57 typedef enum IRQn
AnnaBridge 171:3a7713b1edbc 58 {
AnnaBridge 171:3a7713b1edbc 59 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
AnnaBridge 171:3a7713b1edbc 60 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
AnnaBridge 171:3a7713b1edbc 61 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 62 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 63 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 64 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 65 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /****** LPC8xx Specific Interrupt Numbers ********************************************************/
AnnaBridge 171:3a7713b1edbc 68 SPI0_IRQn = 0, /*!< SPI0 */
AnnaBridge 171:3a7713b1edbc 69 SPI1_IRQn = 1, /*!< SPI1 */
AnnaBridge 171:3a7713b1edbc 70 Reserved0_IRQn = 2, /*!< Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 71 UART0_IRQn = 3, /*!< USART0 */
AnnaBridge 171:3a7713b1edbc 72 UART1_IRQn = 4, /*!< USART1 */
AnnaBridge 171:3a7713b1edbc 73 UART2_IRQn = 5, /*!< USART2 */
AnnaBridge 171:3a7713b1edbc 74 Reserved1_IRQn = 6, /*!< Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 75 Reserved2_IRQn = 7, /*!< Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 76 I2C_IRQn = 8, /*!< I2C */
AnnaBridge 171:3a7713b1edbc 77 SCT_IRQn = 9, /*!< SCT */
AnnaBridge 171:3a7713b1edbc 78 MRT_IRQn = 10, /*!< MRT */
AnnaBridge 171:3a7713b1edbc 79 CMP_IRQn = 11, /*!< CMP */
AnnaBridge 171:3a7713b1edbc 80 WDT_IRQn = 12, /*!< WDT */
AnnaBridge 171:3a7713b1edbc 81 BOD_IRQn = 13, /*!< BOD */
AnnaBridge 171:3a7713b1edbc 82 Reserved3_IRQn = 14, /*!< Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 83 WKT_IRQn = 15, /*!< WKT Interrupt */
AnnaBridge 171:3a7713b1edbc 84 Reserved4_IRQn = 16, /*!< Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 85 Reserved5_IRQn = 17, /*!< Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 86 Reserved6_IRQn = 18, /*!< Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 87 Reserved7_IRQn = 19, /*!< Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 88 Reserved8_IRQn = 20, /*!< Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 89 Reserved9_IRQn = 21, /*!< Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 90 Reserved10_IRQn = 22, /*!< Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 91 Reserved11_IRQn = 23, /*!< Reserved Interrupt */
AnnaBridge 171:3a7713b1edbc 92 PININT0_IRQn = 24, /*!< External Interrupt 0 */
AnnaBridge 171:3a7713b1edbc 93 PININT1_IRQn = 25, /*!< External Interrupt 1 */
AnnaBridge 171:3a7713b1edbc 94 PININT2_IRQn = 26, /*!< External Interrupt 2 */
AnnaBridge 171:3a7713b1edbc 95 PININT3_IRQn = 27, /*!< External Interrupt 3 */
AnnaBridge 171:3a7713b1edbc 96 PININT4_IRQn = 28, /*!< External Interrupt 4 */
AnnaBridge 171:3a7713b1edbc 97 PININT5_IRQn = 29, /*!< External Interrupt 5 */
AnnaBridge 171:3a7713b1edbc 98 PININT6_IRQn = 30, /*!< External Interrupt 6 */
AnnaBridge 171:3a7713b1edbc 99 PININT7_IRQn = 31, /*!< External Interrupt 7 */
AnnaBridge 171:3a7713b1edbc 100 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 /*
AnnaBridge 171:3a7713b1edbc 103 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 104 * ----------- Processor and Core Peripheral Section ------------------------
AnnaBridge 171:3a7713b1edbc 105 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 106 */
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 /* Configuration of the Cortex-M0+ Processor and Core Peripherals */
AnnaBridge 171:3a7713b1edbc 109 #define __MPU_PRESENT 0 /*!< MPU present or not */
AnnaBridge 171:3a7713b1edbc 110 #define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */
AnnaBridge 171:3a7713b1edbc 111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
AnnaBridge 171:3a7713b1edbc 112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 113
AnnaBridge 171:3a7713b1edbc 114 /*@}*/ /* end of group LPC8xx_CMSIS */
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 118 #include "system_LPC8xx.h" /* System Header */
AnnaBridge 171:3a7713b1edbc 119
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 122 /* Device Specific Peripheral Registers structures */
AnnaBridge 171:3a7713b1edbc 123 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 126 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 127 #endif
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129 /*------------- System Control (SYSCON) --------------------------------------*/
AnnaBridge 171:3a7713b1edbc 130 /** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
AnnaBridge 171:3a7713b1edbc 131 @{
AnnaBridge 171:3a7713b1edbc 132 */
AnnaBridge 171:3a7713b1edbc 133 typedef struct
AnnaBridge 171:3a7713b1edbc 134 {
AnnaBridge 171:3a7713b1edbc 135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
AnnaBridge 171:3a7713b1edbc 136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
AnnaBridge 171:3a7713b1edbc 137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
AnnaBridge 171:3a7713b1edbc 138 __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
AnnaBridge 171:3a7713b1edbc 139 uint32_t RESERVED0[4];
AnnaBridge 171:3a7713b1edbc 140
AnnaBridge 171:3a7713b1edbc 141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
AnnaBridge 171:3a7713b1edbc 142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
AnnaBridge 171:3a7713b1edbc 143 uint32_t RESERVED1[2];
AnnaBridge 171:3a7713b1edbc 144 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
AnnaBridge 171:3a7713b1edbc 145 uint32_t RESERVED2[3];
AnnaBridge 171:3a7713b1edbc 146 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
AnnaBridge 171:3a7713b1edbc 147 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
AnnaBridge 171:3a7713b1edbc 148 uint32_t RESERVED3[10];
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
AnnaBridge 171:3a7713b1edbc 151 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
AnnaBridge 171:3a7713b1edbc 152 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
AnnaBridge 171:3a7713b1edbc 153 uint32_t RESERVED4[1];
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
AnnaBridge 171:3a7713b1edbc 156 uint32_t RESERVED5[4];
AnnaBridge 171:3a7713b1edbc 157 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
AnnaBridge 171:3a7713b1edbc 158 uint32_t RESERVED6[18];
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
AnnaBridge 171:3a7713b1edbc 161 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
AnnaBridge 171:3a7713b1edbc 162 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
AnnaBridge 171:3a7713b1edbc 163 uint32_t RESERVED7;
AnnaBridge 171:3a7713b1edbc 164 __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
AnnaBridge 171:3a7713b1edbc 165 __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
AnnaBridge 171:3a7713b1edbc 166 uint32_t RESERVED8[1];
AnnaBridge 171:3a7713b1edbc 167 __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
AnnaBridge 171:3a7713b1edbc 168 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
AnnaBridge 171:3a7713b1edbc 169 uint32_t RESERVED9[12];
AnnaBridge 171:3a7713b1edbc 170 __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
AnnaBridge 171:3a7713b1edbc 171 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
AnnaBridge 171:3a7713b1edbc 172 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
AnnaBridge 171:3a7713b1edbc 173 uint32_t RESERVED10[6];
AnnaBridge 171:3a7713b1edbc 174 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
AnnaBridge 171:3a7713b1edbc 175 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
AnnaBridge 171:3a7713b1edbc 176 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
AnnaBridge 171:3a7713b1edbc 177 uint32_t RESERVED11[27];
AnnaBridge 171:3a7713b1edbc 178 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
AnnaBridge 171:3a7713b1edbc 179 uint32_t RESERVED12[3];
AnnaBridge 171:3a7713b1edbc 180 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
AnnaBridge 171:3a7713b1edbc 181 uint32_t RESERVED13[6];
AnnaBridge 171:3a7713b1edbc 182 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
AnnaBridge 171:3a7713b1edbc 183 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
AnnaBridge 171:3a7713b1edbc 184 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
AnnaBridge 171:3a7713b1edbc 185 uint32_t RESERVED14[110];
AnnaBridge 171:3a7713b1edbc 186 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
AnnaBridge 171:3a7713b1edbc 187 } LPC_SYSCON_TypeDef;
AnnaBridge 171:3a7713b1edbc 188 /*@}*/ /* end of group LPC8xx_SYSCON */
AnnaBridge 171:3a7713b1edbc 189
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 /**
AnnaBridge 171:3a7713b1edbc 192 * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
AnnaBridge 171:3a7713b1edbc 193 */
AnnaBridge 171:3a7713b1edbc 194
AnnaBridge 171:3a7713b1edbc 195 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
AnnaBridge 171:3a7713b1edbc 196 __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
AnnaBridge 171:3a7713b1edbc 197 __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
AnnaBridge 171:3a7713b1edbc 198 __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
AnnaBridge 171:3a7713b1edbc 199 __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
AnnaBridge 171:3a7713b1edbc 200 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
AnnaBridge 171:3a7713b1edbc 201 __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
AnnaBridge 171:3a7713b1edbc 202 __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
AnnaBridge 171:3a7713b1edbc 203 __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
AnnaBridge 171:3a7713b1edbc 204 __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
AnnaBridge 171:3a7713b1edbc 205 __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
AnnaBridge 171:3a7713b1edbc 206 __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
AnnaBridge 171:3a7713b1edbc 207 __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
AnnaBridge 171:3a7713b1edbc 208 __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
AnnaBridge 171:3a7713b1edbc 209 __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
AnnaBridge 171:3a7713b1edbc 210 __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
AnnaBridge 171:3a7713b1edbc 211 __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
AnnaBridge 171:3a7713b1edbc 212 __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
AnnaBridge 171:3a7713b1edbc 213 __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
AnnaBridge 171:3a7713b1edbc 214 __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
AnnaBridge 171:3a7713b1edbc 215 } LPC_IOCON_TypeDef;
AnnaBridge 171:3a7713b1edbc 216 /*@}*/ /* end of group LPC8xx_IOCON */
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /**
AnnaBridge 171:3a7713b1edbc 219 * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL)
AnnaBridge 171:3a7713b1edbc 220 */
AnnaBridge 171:3a7713b1edbc 221 typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
AnnaBridge 171:3a7713b1edbc 222 __I uint32_t RESERVED0[4];
AnnaBridge 171:3a7713b1edbc 223 __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
AnnaBridge 171:3a7713b1edbc 224 __I uint32_t RESERVED1[3];
AnnaBridge 171:3a7713b1edbc 225 __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
AnnaBridge 171:3a7713b1edbc 226 __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
AnnaBridge 171:3a7713b1edbc 227 __I uint32_t RESERVED2;
AnnaBridge 171:3a7713b1edbc 228 __I uint32_t FMSW0;
AnnaBridge 171:3a7713b1edbc 229 } LPC_FLASHCTRL_TypeDef;
AnnaBridge 171:3a7713b1edbc 230 /*@}*/ /* end of group LPC8xx_FLASHCTRL */
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 /*------------- Power Management Unit (PMU) --------------------------*/
AnnaBridge 171:3a7713b1edbc 234 /** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
AnnaBridge 171:3a7713b1edbc 235 @{
AnnaBridge 171:3a7713b1edbc 236 */
AnnaBridge 171:3a7713b1edbc 237 typedef struct
AnnaBridge 171:3a7713b1edbc 238 {
AnnaBridge 171:3a7713b1edbc 239 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 240 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
AnnaBridge 171:3a7713b1edbc 241 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
AnnaBridge 171:3a7713b1edbc 242 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
AnnaBridge 171:3a7713b1edbc 243 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
AnnaBridge 171:3a7713b1edbc 244 __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
AnnaBridge 171:3a7713b1edbc 245 } LPC_PMU_TypeDef;
AnnaBridge 171:3a7713b1edbc 246 /*@}*/ /* end of group LPC8xx_PMU */
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248
AnnaBridge 171:3a7713b1edbc 249 /*------------- Switch Matrix Port --------------------------*/
AnnaBridge 171:3a7713b1edbc 250 /** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
AnnaBridge 171:3a7713b1edbc 251 @{
AnnaBridge 171:3a7713b1edbc 252 */
AnnaBridge 171:3a7713b1edbc 253 typedef struct
AnnaBridge 171:3a7713b1edbc 254 {
AnnaBridge 171:3a7713b1edbc 255 union {
AnnaBridge 171:3a7713b1edbc 256 __IO uint32_t PINASSIGN[9];
AnnaBridge 171:3a7713b1edbc 257 struct {
AnnaBridge 171:3a7713b1edbc 258 __IO uint32_t PINASSIGN0;
AnnaBridge 171:3a7713b1edbc 259 __IO uint32_t PINASSIGN1;
AnnaBridge 171:3a7713b1edbc 260 __IO uint32_t PINASSIGN2;
AnnaBridge 171:3a7713b1edbc 261 __IO uint32_t PINASSIGN3;
AnnaBridge 171:3a7713b1edbc 262 __IO uint32_t PINASSIGN4;
AnnaBridge 171:3a7713b1edbc 263 __IO uint32_t PINASSIGN5;
AnnaBridge 171:3a7713b1edbc 264 __IO uint32_t PINASSIGN6;
AnnaBridge 171:3a7713b1edbc 265 __IO uint32_t PINASSIGN7;
AnnaBridge 171:3a7713b1edbc 266 __IO uint32_t PINASSIGN8;
AnnaBridge 171:3a7713b1edbc 267 };
AnnaBridge 171:3a7713b1edbc 268 };
AnnaBridge 171:3a7713b1edbc 269 __I uint32_t RESERVED0[103];
AnnaBridge 171:3a7713b1edbc 270 __IO uint32_t PINENABLE0;
AnnaBridge 171:3a7713b1edbc 271 } LPC_SWM_TypeDef;
AnnaBridge 171:3a7713b1edbc 272 /*@}*/ /* end of group LPC8xx_SWM */
AnnaBridge 171:3a7713b1edbc 273
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 276 // ----- GPIO_PORT -----
AnnaBridge 171:3a7713b1edbc 277 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279 /**
AnnaBridge 171:3a7713b1edbc 280 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
AnnaBridge 171:3a7713b1edbc 281 */
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 typedef struct {
AnnaBridge 171:3a7713b1edbc 284 __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */
AnnaBridge 171:3a7713b1edbc 285 __I uint16_t RESERVED0[2039];
AnnaBridge 171:3a7713b1edbc 286 __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */
AnnaBridge 171:3a7713b1edbc 287 uint32_t RESERVED1[1006];
AnnaBridge 171:3a7713b1edbc 288 __IO uint32_t DIR0; /* 0x2000 */
AnnaBridge 171:3a7713b1edbc 289 uint32_t RESERVED2[31];
AnnaBridge 171:3a7713b1edbc 290 __IO uint32_t MASK0; /* 0x2080 */
AnnaBridge 171:3a7713b1edbc 291 uint32_t RESERVED3[31];
AnnaBridge 171:3a7713b1edbc 292 __IO uint32_t PIN0; /* 0x2100 */
AnnaBridge 171:3a7713b1edbc 293 uint32_t RESERVED4[31];
AnnaBridge 171:3a7713b1edbc 294 __IO uint32_t MPIN0; /* 0x2180 */
AnnaBridge 171:3a7713b1edbc 295 uint32_t RESERVED5[31];
AnnaBridge 171:3a7713b1edbc 296 __IO uint32_t SET0; /* 0x2200 */
AnnaBridge 171:3a7713b1edbc 297 uint32_t RESERVED6[31];
AnnaBridge 171:3a7713b1edbc 298 __O uint32_t CLR0; /* 0x2280 */
AnnaBridge 171:3a7713b1edbc 299 uint32_t RESERVED7[31];
AnnaBridge 171:3a7713b1edbc 300 __O uint32_t NOT0; /* 0x2300 */
AnnaBridge 171:3a7713b1edbc 301
AnnaBridge 171:3a7713b1edbc 302 } LPC_GPIO_PORT_TypeDef;
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304
AnnaBridge 171:3a7713b1edbc 305 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 306 // ----- PIN_INT -----
AnnaBridge 171:3a7713b1edbc 307 // ------------------------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 308
AnnaBridge 171:3a7713b1edbc 309 /**
AnnaBridge 171:3a7713b1edbc 310 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT)
AnnaBridge 171:3a7713b1edbc 311 */
AnnaBridge 171:3a7713b1edbc 312
AnnaBridge 171:3a7713b1edbc 313 typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
AnnaBridge 171:3a7713b1edbc 314 __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
AnnaBridge 171:3a7713b1edbc 315 __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
AnnaBridge 171:3a7713b1edbc 316 __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
AnnaBridge 171:3a7713b1edbc 317 __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
AnnaBridge 171:3a7713b1edbc 318 __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
AnnaBridge 171:3a7713b1edbc 319 __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
AnnaBridge 171:3a7713b1edbc 320 __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
AnnaBridge 171:3a7713b1edbc 321 __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
AnnaBridge 171:3a7713b1edbc 322 __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
AnnaBridge 171:3a7713b1edbc 323 __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 324 __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
AnnaBridge 171:3a7713b1edbc 325 __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
AnnaBridge 171:3a7713b1edbc 326 __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
AnnaBridge 171:3a7713b1edbc 327 } LPC_PIN_INT_TypeDef;
AnnaBridge 171:3a7713b1edbc 328
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 /*------------- CRC Engine (CRC) -----------------------------------------*/
AnnaBridge 171:3a7713b1edbc 331 /** @addtogroup LPC8xx_CRC
AnnaBridge 171:3a7713b1edbc 332 @{
AnnaBridge 171:3a7713b1edbc 333 */
AnnaBridge 171:3a7713b1edbc 334 typedef struct
AnnaBridge 171:3a7713b1edbc 335 {
AnnaBridge 171:3a7713b1edbc 336 __IO uint32_t MODE;
AnnaBridge 171:3a7713b1edbc 337 __IO uint32_t SEED;
AnnaBridge 171:3a7713b1edbc 338 union {
AnnaBridge 171:3a7713b1edbc 339 __I uint32_t SUM;
AnnaBridge 171:3a7713b1edbc 340 __O uint32_t WR_DATA_DWORD;
AnnaBridge 171:3a7713b1edbc 341 __O uint16_t WR_DATA_WORD;
AnnaBridge 171:3a7713b1edbc 342 uint16_t RESERVED_WORD;
AnnaBridge 171:3a7713b1edbc 343 __O uint8_t WR_DATA_BYTE;
AnnaBridge 171:3a7713b1edbc 344 uint8_t RESERVED_BYTE[3];
AnnaBridge 171:3a7713b1edbc 345 };
AnnaBridge 171:3a7713b1edbc 346 } LPC_CRC_TypeDef;
AnnaBridge 171:3a7713b1edbc 347 /*@}*/ /* end of group LPC8xx_CRC */
AnnaBridge 171:3a7713b1edbc 348
AnnaBridge 171:3a7713b1edbc 349 /*------------- Comparator (CMP) --------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 350 /** @addtogroup LPC8xx_CMP LPC8xx Comparator
AnnaBridge 171:3a7713b1edbc 351 @{
AnnaBridge 171:3a7713b1edbc 352 */
AnnaBridge 171:3a7713b1edbc 353 typedef struct { /*!< (@ 0x40024000) CMP Structure */
AnnaBridge 171:3a7713b1edbc 354 __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
AnnaBridge 171:3a7713b1edbc 355 __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
AnnaBridge 171:3a7713b1edbc 356 } LPC_CMP_TypeDef;
AnnaBridge 171:3a7713b1edbc 357 /*@}*/ /* end of group LPC8xx_CMP */
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359
AnnaBridge 171:3a7713b1edbc 360 /*------------- Wakeup Timer (WKT) --------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 361 /** @addtogroup LPC8xx_WKT
AnnaBridge 171:3a7713b1edbc 362 @{
AnnaBridge 171:3a7713b1edbc 363 */
AnnaBridge 171:3a7713b1edbc 364 typedef struct { /*!< (@ 0x40028000) WKT Structure */
AnnaBridge 171:3a7713b1edbc 365 __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
AnnaBridge 171:3a7713b1edbc 366 uint32_t Reserved[2];
AnnaBridge 171:3a7713b1edbc 367 __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
AnnaBridge 171:3a7713b1edbc 368 } LPC_WKT_TypeDef;
AnnaBridge 171:3a7713b1edbc 369 /*@}*/ /* end of group LPC8xx_WKT */
AnnaBridge 171:3a7713b1edbc 370
AnnaBridge 171:3a7713b1edbc 371 /*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 372 //New, Copied from lpc824
AnnaBridge 171:3a7713b1edbc 373 /**
AnnaBridge 171:3a7713b1edbc 374 * @brief Multi-Rate Timer (MRT) (MRT)
AnnaBridge 171:3a7713b1edbc 375 */
AnnaBridge 171:3a7713b1edbc 376 typedef struct { /*!< (@ 0x40004000) MRT Structure */
AnnaBridge 171:3a7713b1edbc 377 __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
AnnaBridge 171:3a7713b1edbc 378 is loaded into the TIMER0 register. */
AnnaBridge 171:3a7713b1edbc 379 __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
AnnaBridge 171:3a7713b1edbc 380 value of the down-counter. */
AnnaBridge 171:3a7713b1edbc 381 __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
AnnaBridge 171:3a7713b1edbc 382 the MRT0 modes. */
AnnaBridge 171:3a7713b1edbc 383 __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */
AnnaBridge 171:3a7713b1edbc 384 __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
AnnaBridge 171:3a7713b1edbc 385 is loaded into the TIMER0 register. */
AnnaBridge 171:3a7713b1edbc 386 __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
AnnaBridge 171:3a7713b1edbc 387 value of the down-counter. */
AnnaBridge 171:3a7713b1edbc 388 __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
AnnaBridge 171:3a7713b1edbc 389 the MRT0 modes. */
AnnaBridge 171:3a7713b1edbc 390 __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */
AnnaBridge 171:3a7713b1edbc 391 __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
AnnaBridge 171:3a7713b1edbc 392 is loaded into the TIMER0 register. */
AnnaBridge 171:3a7713b1edbc 393 __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
AnnaBridge 171:3a7713b1edbc 394 value of the down-counter. */
AnnaBridge 171:3a7713b1edbc 395 __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
AnnaBridge 171:3a7713b1edbc 396 the MRT0 modes. */
AnnaBridge 171:3a7713b1edbc 397 __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */
AnnaBridge 171:3a7713b1edbc 398 __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
AnnaBridge 171:3a7713b1edbc 399 is loaded into the TIMER0 register. */
AnnaBridge 171:3a7713b1edbc 400 __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
AnnaBridge 171:3a7713b1edbc 401 value of the down-counter. */
AnnaBridge 171:3a7713b1edbc 402 __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
AnnaBridge 171:3a7713b1edbc 403 the MRT0 modes. */
AnnaBridge 171:3a7713b1edbc 404 __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */
AnnaBridge 171:3a7713b1edbc 405 __I uint32_t RESERVED0[45];
AnnaBridge 171:3a7713b1edbc 406 __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
AnnaBridge 171:3a7713b1edbc 407 the number of the first idle channel. */
AnnaBridge 171:3a7713b1edbc 408 __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */
AnnaBridge 171:3a7713b1edbc 409 } LPC_MRT_TypeDef;
AnnaBridge 171:3a7713b1edbc 410
AnnaBridge 171:3a7713b1edbc 411 /*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
AnnaBridge 171:3a7713b1edbc 412 /** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
AnnaBridge 171:3a7713b1edbc 413 @{
AnnaBridge 171:3a7713b1edbc 414 */
AnnaBridge 171:3a7713b1edbc 415 /**
AnnaBridge 171:3a7713b1edbc 416 * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART)
AnnaBridge 171:3a7713b1edbc 417 */
AnnaBridge 171:3a7713b1edbc 418 typedef struct
AnnaBridge 171:3a7713b1edbc 419 {
AnnaBridge 171:3a7713b1edbc 420 __IO uint32_t CFG; /* 0x00 */
AnnaBridge 171:3a7713b1edbc 421 __IO uint32_t CTRL;
AnnaBridge 171:3a7713b1edbc 422 __IO uint32_t STAT;
AnnaBridge 171:3a7713b1edbc 423 __IO uint32_t INTENSET;
AnnaBridge 171:3a7713b1edbc 424 __O uint32_t INTENCLR; /* 0x10 */
AnnaBridge 171:3a7713b1edbc 425 __I uint32_t RXDATA;
AnnaBridge 171:3a7713b1edbc 426 __I uint32_t RXDATA_STAT;
AnnaBridge 171:3a7713b1edbc 427 __IO uint32_t TXDATA;
AnnaBridge 171:3a7713b1edbc 428 __IO uint32_t BRG; /* 0x20 */
AnnaBridge 171:3a7713b1edbc 429 __IO uint32_t INTSTAT;
AnnaBridge 171:3a7713b1edbc 430 } LPC_USART_TypeDef;
AnnaBridge 171:3a7713b1edbc 431
AnnaBridge 171:3a7713b1edbc 432 /*@}*/ /* end of group LPC8xx_USART */
AnnaBridge 171:3a7713b1edbc 433
AnnaBridge 171:3a7713b1edbc 434
AnnaBridge 171:3a7713b1edbc 435 /*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
AnnaBridge 171:3a7713b1edbc 436 /** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
AnnaBridge 171:3a7713b1edbc 437 @{
AnnaBridge 171:3a7713b1edbc 438 */
AnnaBridge 171:3a7713b1edbc 439 typedef struct
AnnaBridge 171:3a7713b1edbc 440 {
AnnaBridge 171:3a7713b1edbc 441 __IO uint32_t CFG; /* 0x00 */
AnnaBridge 171:3a7713b1edbc 442 __IO uint32_t DLY;
AnnaBridge 171:3a7713b1edbc 443 __IO uint32_t STAT;
AnnaBridge 171:3a7713b1edbc 444 __IO uint32_t INTENSET;
AnnaBridge 171:3a7713b1edbc 445 __O uint32_t INTENCLR; /* 0x10 */
AnnaBridge 171:3a7713b1edbc 446 __I uint32_t RXDAT;
AnnaBridge 171:3a7713b1edbc 447 __IO uint32_t TXDATCTL;
AnnaBridge 171:3a7713b1edbc 448 __IO uint32_t TXDAT;
AnnaBridge 171:3a7713b1edbc 449 __IO uint32_t TXCTRL; /* 0x20 */
AnnaBridge 171:3a7713b1edbc 450 __IO uint32_t DIV;
AnnaBridge 171:3a7713b1edbc 451 __I uint32_t INTSTAT;
AnnaBridge 171:3a7713b1edbc 452 } LPC_SPI_TypeDef;
AnnaBridge 171:3a7713b1edbc 453 /*@}*/ /* end of group LPC8xx_SPI */
AnnaBridge 171:3a7713b1edbc 454
AnnaBridge 171:3a7713b1edbc 455
AnnaBridge 171:3a7713b1edbc 456 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
AnnaBridge 171:3a7713b1edbc 457 /** @addtogroup LPC8xx_I2C I2C-Bus Interface
AnnaBridge 171:3a7713b1edbc 458 @{
AnnaBridge 171:3a7713b1edbc 459 */
AnnaBridge 171:3a7713b1edbc 460 typedef struct
AnnaBridge 171:3a7713b1edbc 461 {
AnnaBridge 171:3a7713b1edbc 462 __IO uint32_t CFG; /* 0x00 */
AnnaBridge 171:3a7713b1edbc 463 __IO uint32_t STAT;
AnnaBridge 171:3a7713b1edbc 464 __IO uint32_t INTENSET;
AnnaBridge 171:3a7713b1edbc 465 __O uint32_t INTENCLR;
AnnaBridge 171:3a7713b1edbc 466 __IO uint32_t TIMEOUT; /* 0x10 */
AnnaBridge 171:3a7713b1edbc 467 __IO uint32_t DIV;
AnnaBridge 171:3a7713b1edbc 468 __IO uint32_t INTSTAT;
AnnaBridge 171:3a7713b1edbc 469 uint32_t Reserved0[1];
AnnaBridge 171:3a7713b1edbc 470 __IO uint32_t MSTCTL; /* 0x20 */
AnnaBridge 171:3a7713b1edbc 471 __IO uint32_t MSTTIME;
AnnaBridge 171:3a7713b1edbc 472 __IO uint32_t MSTDAT;
AnnaBridge 171:3a7713b1edbc 473 uint32_t Reserved1[5];
AnnaBridge 171:3a7713b1edbc 474 __IO uint32_t SLVCTL; /* 0x40 */
AnnaBridge 171:3a7713b1edbc 475 __IO uint32_t SLVDAT;
AnnaBridge 171:3a7713b1edbc 476 __IO uint32_t SLVADR0;
AnnaBridge 171:3a7713b1edbc 477 __IO uint32_t SLVADR1;
AnnaBridge 171:3a7713b1edbc 478 __IO uint32_t SLVADR2; /* 0x50 */
AnnaBridge 171:3a7713b1edbc 479 __IO uint32_t SLVADR3;
AnnaBridge 171:3a7713b1edbc 480 __IO uint32_t SLVQUAL0;
AnnaBridge 171:3a7713b1edbc 481 uint32_t Reserved2[9];
AnnaBridge 171:3a7713b1edbc 482 __I uint32_t MONRXDAT; /* 0x80 */
AnnaBridge 171:3a7713b1edbc 483 } LPC_I2C_TypeDef;
AnnaBridge 171:3a7713b1edbc 484
AnnaBridge 171:3a7713b1edbc 485 /*@}*/ /* end of group LPC8xx_I2C */
AnnaBridge 171:3a7713b1edbc 486
AnnaBridge 171:3a7713b1edbc 487 /**
AnnaBridge 171:3a7713b1edbc 488 * @brief State Configurable Timer (SCT) (SCT)
AnnaBridge 171:3a7713b1edbc 489 */
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 /**
AnnaBridge 171:3a7713b1edbc 492 * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
AnnaBridge 171:3a7713b1edbc 493 */
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 #define CONFIG_SCT_nEV (6) /* Number of events */
AnnaBridge 171:3a7713b1edbc 496 #define CONFIG_SCT_nRG (5) /* Number of match/compare registers */
AnnaBridge 171:3a7713b1edbc 497 #define CONFIG_SCT_nOU (4) /* Number of outputs */
AnnaBridge 171:3a7713b1edbc 498
AnnaBridge 171:3a7713b1edbc 499 typedef struct
AnnaBridge 171:3a7713b1edbc 500 {
AnnaBridge 171:3a7713b1edbc 501 __IO uint32_t CONFIG; /* 0x000 Configuration Register */
AnnaBridge 171:3a7713b1edbc 502 union {
AnnaBridge 171:3a7713b1edbc 503 __IO uint32_t CTRL_U; /* 0x004 Control Register */
AnnaBridge 171:3a7713b1edbc 504 struct {
AnnaBridge 171:3a7713b1edbc 505 __IO uint16_t CTRL_L; /* 0x004 low control register */
AnnaBridge 171:3a7713b1edbc 506 __IO uint16_t CTRL_H; /* 0x006 high control register */
AnnaBridge 171:3a7713b1edbc 507 };
AnnaBridge 171:3a7713b1edbc 508 };
AnnaBridge 171:3a7713b1edbc 509 __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
AnnaBridge 171:3a7713b1edbc 510 __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
AnnaBridge 171:3a7713b1edbc 511 __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
AnnaBridge 171:3a7713b1edbc 512 __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
AnnaBridge 171:3a7713b1edbc 513 __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
AnnaBridge 171:3a7713b1edbc 514 __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
AnnaBridge 171:3a7713b1edbc 515 __IO uint16_t START_L; /* 0x014 start register for counter L */
AnnaBridge 171:3a7713b1edbc 516 __IO uint16_t START_H; /* 0x016 start register for counter H */
AnnaBridge 171:3a7713b1edbc 517 uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
AnnaBridge 171:3a7713b1edbc 518 union {
AnnaBridge 171:3a7713b1edbc 519 __IO uint32_t COUNT_U; /* 0x040 counter register */
AnnaBridge 171:3a7713b1edbc 520 struct {
AnnaBridge 171:3a7713b1edbc 521 __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
AnnaBridge 171:3a7713b1edbc 522 __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
AnnaBridge 171:3a7713b1edbc 523 };
AnnaBridge 171:3a7713b1edbc 524 };
AnnaBridge 171:3a7713b1edbc 525 __IO uint16_t STATE_L; /* 0x044 state register for counter L */
AnnaBridge 171:3a7713b1edbc 526 __IO uint16_t STATE_H; /* 0x046 state register for counter H */
AnnaBridge 171:3a7713b1edbc 527 __I uint32_t INPUT; /* 0x048 input register */
AnnaBridge 171:3a7713b1edbc 528 __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
AnnaBridge 171:3a7713b1edbc 529 __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
AnnaBridge 171:3a7713b1edbc 530 __IO uint32_t OUTPUT; /* 0x050 output register */
AnnaBridge 171:3a7713b1edbc 531 __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
AnnaBridge 171:3a7713b1edbc 532 __IO uint32_t RES; /* 0x058 conflict resolution register */
AnnaBridge 171:3a7713b1edbc 533 uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */
AnnaBridge 171:3a7713b1edbc 534 __IO uint32_t EVEN; /* 0x0F0 event enable register */
AnnaBridge 171:3a7713b1edbc 535 __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
AnnaBridge 171:3a7713b1edbc 536 __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
AnnaBridge 171:3a7713b1edbc 537 __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
AnnaBridge 171:3a7713b1edbc 538
AnnaBridge 171:3a7713b1edbc 539 union {
AnnaBridge 171:3a7713b1edbc 540 __IO union { /* 0x100-... Match / Capture value */
AnnaBridge 171:3a7713b1edbc 541 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
AnnaBridge 171:3a7713b1edbc 542 struct {
AnnaBridge 171:3a7713b1edbc 543 uint16_t L; /* SCTMATCH[i].L Access to L value */
AnnaBridge 171:3a7713b1edbc 544 uint16_t H; /* SCTMATCH[i].H Access to H value */
AnnaBridge 171:3a7713b1edbc 545 };
AnnaBridge 171:3a7713b1edbc 546 } MATCH[CONFIG_SCT_nRG];
AnnaBridge 171:3a7713b1edbc 547 __I union {
AnnaBridge 171:3a7713b1edbc 548 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
AnnaBridge 171:3a7713b1edbc 549 struct {
AnnaBridge 171:3a7713b1edbc 550 uint16_t L; /* SCTCAP[i].L Access to H value */
AnnaBridge 171:3a7713b1edbc 551 uint16_t H; /* SCTCAP[i].H Access to H value */
AnnaBridge 171:3a7713b1edbc 552 };
AnnaBridge 171:3a7713b1edbc 553 } CAP[CONFIG_SCT_nRG];
AnnaBridge 171:3a7713b1edbc 554 };
AnnaBridge 171:3a7713b1edbc 555
AnnaBridge 171:3a7713b1edbc 556
AnnaBridge 171:3a7713b1edbc 557 uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
AnnaBridge 171:3a7713b1edbc 558
AnnaBridge 171:3a7713b1edbc 559 union {
AnnaBridge 171:3a7713b1edbc 560 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
AnnaBridge 171:3a7713b1edbc 561 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
AnnaBridge 171:3a7713b1edbc 562 };
AnnaBridge 171:3a7713b1edbc 563 uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
AnnaBridge 171:3a7713b1edbc 564 union {
AnnaBridge 171:3a7713b1edbc 565 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
AnnaBridge 171:3a7713b1edbc 566 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
AnnaBridge 171:3a7713b1edbc 567 };
AnnaBridge 171:3a7713b1edbc 568
AnnaBridge 171:3a7713b1edbc 569 uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
AnnaBridge 171:3a7713b1edbc 570
AnnaBridge 171:3a7713b1edbc 571
AnnaBridge 171:3a7713b1edbc 572 union {
AnnaBridge 171:3a7713b1edbc 573 __IO union { /* 0x200-... Match Reload / Capture Control value */
AnnaBridge 171:3a7713b1edbc 574 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
AnnaBridge 171:3a7713b1edbc 575 struct {
AnnaBridge 171:3a7713b1edbc 576 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
AnnaBridge 171:3a7713b1edbc 577 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
AnnaBridge 171:3a7713b1edbc 578 };
AnnaBridge 171:3a7713b1edbc 579 } MATCHREL[CONFIG_SCT_nRG];
AnnaBridge 171:3a7713b1edbc 580 __IO union {
AnnaBridge 171:3a7713b1edbc 581 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
AnnaBridge 171:3a7713b1edbc 582 struct {
AnnaBridge 171:3a7713b1edbc 583 uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
AnnaBridge 171:3a7713b1edbc 584 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
AnnaBridge 171:3a7713b1edbc 585 };
AnnaBridge 171:3a7713b1edbc 586 } CAPCTRL[CONFIG_SCT_nRG];
AnnaBridge 171:3a7713b1edbc 587 };
AnnaBridge 171:3a7713b1edbc 588
AnnaBridge 171:3a7713b1edbc 589 uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
AnnaBridge 171:3a7713b1edbc 590
AnnaBridge 171:3a7713b1edbc 591 union {
AnnaBridge 171:3a7713b1edbc 592 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
AnnaBridge 171:3a7713b1edbc 593 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
AnnaBridge 171:3a7713b1edbc 594 };
AnnaBridge 171:3a7713b1edbc 595 uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
AnnaBridge 171:3a7713b1edbc 596 union {
AnnaBridge 171:3a7713b1edbc 597 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
AnnaBridge 171:3a7713b1edbc 598 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
AnnaBridge 171:3a7713b1edbc 599 };
AnnaBridge 171:3a7713b1edbc 600 uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
AnnaBridge 171:3a7713b1edbc 601
AnnaBridge 171:3a7713b1edbc 602 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
AnnaBridge 171:3a7713b1edbc 603 uint32_t STATE; /* Event State Register */
AnnaBridge 171:3a7713b1edbc 604 uint32_t CTRL; /* Event Control Register */
AnnaBridge 171:3a7713b1edbc 605 } EVENT[CONFIG_SCT_nEV];
AnnaBridge 171:3a7713b1edbc 606
AnnaBridge 171:3a7713b1edbc 607 uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
AnnaBridge 171:3a7713b1edbc 608
AnnaBridge 171:3a7713b1edbc 609 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
AnnaBridge 171:3a7713b1edbc 610 uint32_t SET; /* Output n Set Register */
AnnaBridge 171:3a7713b1edbc 611 uint32_t CLR; /* Output n Clear Register */
AnnaBridge 171:3a7713b1edbc 612 } OUT[CONFIG_SCT_nOU];
AnnaBridge 171:3a7713b1edbc 613
AnnaBridge 171:3a7713b1edbc 614 uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
AnnaBridge 171:3a7713b1edbc 615
AnnaBridge 171:3a7713b1edbc 616 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
AnnaBridge 171:3a7713b1edbc 617
AnnaBridge 171:3a7713b1edbc 618 } LPC_SCT_TypeDef;
AnnaBridge 171:3a7713b1edbc 619 /*@}*/ /* end of group LPC8xx_SCT */
AnnaBridge 171:3a7713b1edbc 620
AnnaBridge 171:3a7713b1edbc 621
AnnaBridge 171:3a7713b1edbc 622 /*------------- Watchdog Timer (WWDT) -----------------------------------------*/
AnnaBridge 171:3a7713b1edbc 623 /** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
AnnaBridge 171:3a7713b1edbc 624 @{
AnnaBridge 171:3a7713b1edbc 625 */
AnnaBridge 171:3a7713b1edbc 626 typedef struct
AnnaBridge 171:3a7713b1edbc 627 {
AnnaBridge 171:3a7713b1edbc 628 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
AnnaBridge 171:3a7713b1edbc 629 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
AnnaBridge 171:3a7713b1edbc 630 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
AnnaBridge 171:3a7713b1edbc 631 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
AnnaBridge 171:3a7713b1edbc 632 uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
AnnaBridge 171:3a7713b1edbc 633 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
AnnaBridge 171:3a7713b1edbc 634 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
AnnaBridge 171:3a7713b1edbc 635 } LPC_WWDT_TypeDef;
AnnaBridge 171:3a7713b1edbc 636 /*@}*/ /* end of group LPC8xx_WDT */
AnnaBridge 171:3a7713b1edbc 637
AnnaBridge 171:3a7713b1edbc 638
AnnaBridge 171:3a7713b1edbc 639 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 640 #pragma no_anon_unions
AnnaBridge 171:3a7713b1edbc 641 #endif
AnnaBridge 171:3a7713b1edbc 642
AnnaBridge 171:3a7713b1edbc 643 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 644 /* Peripheral memory map */
AnnaBridge 171:3a7713b1edbc 645 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 646 /* Base addresses */
AnnaBridge 171:3a7713b1edbc 647 #define LPC_FLASH_BASE (0x00000000UL)
AnnaBridge 171:3a7713b1edbc 648 #define LPC_RAM_BASE (0x10000000UL)
AnnaBridge 171:3a7713b1edbc 649 #define LPC_ROM_BASE (0x1FFF0000UL)
AnnaBridge 171:3a7713b1edbc 650 #define LPC_APB0_BASE (0x40000000UL)
AnnaBridge 171:3a7713b1edbc 651 #define LPC_AHB_BASE (0x50000000UL)
AnnaBridge 171:3a7713b1edbc 652
AnnaBridge 171:3a7713b1edbc 653 /* APB0 peripherals */
AnnaBridge 171:3a7713b1edbc 654 #define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
AnnaBridge 171:3a7713b1edbc 655 #define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
AnnaBridge 171:3a7713b1edbc 656 #define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
AnnaBridge 171:3a7713b1edbc 657 #define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
AnnaBridge 171:3a7713b1edbc 658 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
AnnaBridge 171:3a7713b1edbc 659 #define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
AnnaBridge 171:3a7713b1edbc 660
AnnaBridge 171:3a7713b1edbc 661 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
AnnaBridge 171:3a7713b1edbc 662 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
AnnaBridge 171:3a7713b1edbc 663 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
AnnaBridge 171:3a7713b1edbc 664 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
AnnaBridge 171:3a7713b1edbc 665 #define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
AnnaBridge 171:3a7713b1edbc 666 #define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
AnnaBridge 171:3a7713b1edbc 667 #define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
AnnaBridge 171:3a7713b1edbc 668 #define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
AnnaBridge 171:3a7713b1edbc 669 #define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
AnnaBridge 171:3a7713b1edbc 670
AnnaBridge 171:3a7713b1edbc 671 /* AHB peripherals */
AnnaBridge 171:3a7713b1edbc 672 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
AnnaBridge 171:3a7713b1edbc 673 #define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
AnnaBridge 171:3a7713b1edbc 674
AnnaBridge 171:3a7713b1edbc 675 #define LPC_GPIO_PORT_BASE (0xA0000000)
AnnaBridge 171:3a7713b1edbc 676 #define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
AnnaBridge 171:3a7713b1edbc 677
AnnaBridge 171:3a7713b1edbc 678 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 679 /* Peripheral declaration */
AnnaBridge 171:3a7713b1edbc 680 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 681 #define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
AnnaBridge 171:3a7713b1edbc 682 #define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
AnnaBridge 171:3a7713b1edbc 683
AnnaBridge 171:3a7713b1edbc 684
AnnaBridge 171:3a7713b1edbc 685 #define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
AnnaBridge 171:3a7713b1edbc 686 #define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
AnnaBridge 171:3a7713b1edbc 687 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
AnnaBridge 171:3a7713b1edbc 688 #define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
AnnaBridge 171:3a7713b1edbc 689
AnnaBridge 171:3a7713b1edbc 690 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
AnnaBridge 171:3a7713b1edbc 691 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
AnnaBridge 171:3a7713b1edbc 692 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
AnnaBridge 171:3a7713b1edbc 693 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
AnnaBridge 171:3a7713b1edbc 694 #define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
AnnaBridge 171:3a7713b1edbc 695 #define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
AnnaBridge 171:3a7713b1edbc 696 #define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
AnnaBridge 171:3a7713b1edbc 697 #define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
AnnaBridge 171:3a7713b1edbc 698 #define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
AnnaBridge 171:3a7713b1edbc 699
AnnaBridge 171:3a7713b1edbc 700 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
AnnaBridge 171:3a7713b1edbc 701 #define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
AnnaBridge 171:3a7713b1edbc 702
AnnaBridge 171:3a7713b1edbc 703 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
AnnaBridge 171:3a7713b1edbc 704 #define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
AnnaBridge 171:3a7713b1edbc 705
AnnaBridge 171:3a7713b1edbc 706 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 707 }
AnnaBridge 171:3a7713b1edbc 708 #endif
AnnaBridge 171:3a7713b1edbc 709
AnnaBridge 171:3a7713b1edbc 710 #endif /* __LPC8xx_H__ */