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TARGET_LPC546XX/TOOLCHAIN_ARM_STD/LPC54628.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 163:e59c8e839560 | 1 | /* |
| AnnaBridge | 163:e59c8e839560 | 2 | ** ################################################################### |
| AnnaBridge | 163:e59c8e839560 | 3 | ** Processor: LPC54628J512ET180 |
| AnnaBridge | 163:e59c8e839560 | 4 | ** Compilers: Keil ARM C/C++ Compiler |
| AnnaBridge | 163:e59c8e839560 | 5 | ** GNU C Compiler |
| AnnaBridge | 163:e59c8e839560 | 6 | ** IAR ANSI C/C++ Compiler for ARM |
| AnnaBridge | 163:e59c8e839560 | 7 | ** MCUXpresso Compiler |
| AnnaBridge | 163:e59c8e839560 | 8 | ** |
| AnnaBridge | 163:e59c8e839560 | 9 | ** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017 |
| AnnaBridge | 163:e59c8e839560 | 10 | ** Version: rev. 1.2, 2017-06-08 |
| AnnaBridge | 163:e59c8e839560 | 11 | ** Build: b170609 |
| AnnaBridge | 163:e59c8e839560 | 12 | ** |
| AnnaBridge | 163:e59c8e839560 | 13 | ** Abstract: |
| AnnaBridge | 163:e59c8e839560 | 14 | ** CMSIS Peripheral Access Layer for LPC54628 |
| AnnaBridge | 163:e59c8e839560 | 15 | ** |
| AnnaBridge | 163:e59c8e839560 | 16 | ** Copyright 1997-2016 Freescale Semiconductor, Inc. |
| AnnaBridge | 163:e59c8e839560 | 17 | ** Copyright 2016-2017 NXP |
| AnnaBridge | 163:e59c8e839560 | 18 | ** Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 163:e59c8e839560 | 19 | ** are permitted provided that the following conditions are met: |
| AnnaBridge | 163:e59c8e839560 | 20 | ** |
| AnnaBridge | 163:e59c8e839560 | 21 | ** 1. Redistributions of source code must retain the above copyright notice, this list |
| AnnaBridge | 163:e59c8e839560 | 22 | ** of conditions and the following disclaimer. |
| AnnaBridge | 163:e59c8e839560 | 23 | ** |
| AnnaBridge | 163:e59c8e839560 | 24 | ** 2. Redistributions in binary form must reproduce the above copyright notice, this |
| AnnaBridge | 163:e59c8e839560 | 25 | ** list of conditions and the following disclaimer in the documentation and/or |
| AnnaBridge | 163:e59c8e839560 | 26 | ** other materials provided with the distribution. |
| AnnaBridge | 163:e59c8e839560 | 27 | ** |
| AnnaBridge | 163:e59c8e839560 | 28 | ** 3. Neither the name of the copyright holder nor the names of its |
| AnnaBridge | 163:e59c8e839560 | 29 | ** contributors may be used to endorse or promote products derived from this |
| AnnaBridge | 163:e59c8e839560 | 30 | ** software without specific prior written permission. |
| AnnaBridge | 163:e59c8e839560 | 31 | ** |
| AnnaBridge | 163:e59c8e839560 | 32 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| AnnaBridge | 163:e59c8e839560 | 33 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| AnnaBridge | 163:e59c8e839560 | 34 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 163:e59c8e839560 | 35 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
| AnnaBridge | 163:e59c8e839560 | 36 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| AnnaBridge | 163:e59c8e839560 | 37 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| AnnaBridge | 163:e59c8e839560 | 38 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
| AnnaBridge | 163:e59c8e839560 | 39 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| AnnaBridge | 163:e59c8e839560 | 40 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| AnnaBridge | 163:e59c8e839560 | 41 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 163:e59c8e839560 | 42 | ** |
| AnnaBridge | 163:e59c8e839560 | 43 | ** http: www.nxp.com |
| AnnaBridge | 163:e59c8e839560 | 44 | ** mail: support@nxp.com |
| AnnaBridge | 163:e59c8e839560 | 45 | ** |
| AnnaBridge | 163:e59c8e839560 | 46 | ** Revisions: |
| AnnaBridge | 163:e59c8e839560 | 47 | ** - rev. 1.0 (2016-08-12) |
| AnnaBridge | 163:e59c8e839560 | 48 | ** Initial version. |
| AnnaBridge | 163:e59c8e839560 | 49 | ** - rev. 1.1 (2016-11-25) |
| AnnaBridge | 163:e59c8e839560 | 50 | ** Update CANFD and Classic CAN register. |
| AnnaBridge | 163:e59c8e839560 | 51 | ** Add MAC TIMERSTAMP registers. |
| AnnaBridge | 163:e59c8e839560 | 52 | ** - rev. 1.2 (2017-06-08) |
| AnnaBridge | 163:e59c8e839560 | 53 | ** Remove RTC_CTRL_RTC_OSC_BYPASS. |
| AnnaBridge | 163:e59c8e839560 | 54 | ** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. |
| AnnaBridge | 163:e59c8e839560 | 55 | ** Remove RESET and HALT from SYSCON_AHBCLKDIV. |
| AnnaBridge | 163:e59c8e839560 | 56 | ** |
| AnnaBridge | 163:e59c8e839560 | 57 | ** ################################################################### |
| AnnaBridge | 163:e59c8e839560 | 58 | */ |
| AnnaBridge | 163:e59c8e839560 | 59 | |
| AnnaBridge | 163:e59c8e839560 | 60 | /*! |
| AnnaBridge | 163:e59c8e839560 | 61 | * @file LPC54628.h |
| AnnaBridge | 163:e59c8e839560 | 62 | * @version 1.2 |
| AnnaBridge | 163:e59c8e839560 | 63 | * @date 2017-06-08 |
| AnnaBridge | 163:e59c8e839560 | 64 | * @brief CMSIS Peripheral Access Layer for LPC54628 |
| AnnaBridge | 163:e59c8e839560 | 65 | * |
| AnnaBridge | 163:e59c8e839560 | 66 | * CMSIS Peripheral Access Layer for LPC54628 |
| AnnaBridge | 163:e59c8e839560 | 67 | */ |
| AnnaBridge | 163:e59c8e839560 | 68 | |
| AnnaBridge | 163:e59c8e839560 | 69 | #ifndef _LPC54628_H_ |
| AnnaBridge | 163:e59c8e839560 | 70 | #define _LPC54628_H_ /**< Symbol preventing repeated inclusion */ |
| AnnaBridge | 163:e59c8e839560 | 71 | |
| AnnaBridge | 163:e59c8e839560 | 72 | /** Memory map major version (memory maps with equal major version number are |
| AnnaBridge | 163:e59c8e839560 | 73 | * compatible) */ |
| AnnaBridge | 163:e59c8e839560 | 74 | #define MCU_MEM_MAP_VERSION 0x0100U |
| AnnaBridge | 163:e59c8e839560 | 75 | /** Memory map minor version */ |
| AnnaBridge | 163:e59c8e839560 | 76 | #define MCU_MEM_MAP_VERSION_MINOR 0x0002U |
| AnnaBridge | 163:e59c8e839560 | 77 | |
| AnnaBridge | 163:e59c8e839560 | 78 | |
| AnnaBridge | 163:e59c8e839560 | 79 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 80 | -- Interrupt vector numbers |
| AnnaBridge | 163:e59c8e839560 | 81 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 82 | |
| AnnaBridge | 163:e59c8e839560 | 83 | /*! |
| AnnaBridge | 163:e59c8e839560 | 84 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers |
| AnnaBridge | 163:e59c8e839560 | 85 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 86 | */ |
| AnnaBridge | 163:e59c8e839560 | 87 | |
| AnnaBridge | 163:e59c8e839560 | 88 | /** Interrupt Number Definitions */ |
| AnnaBridge | 163:e59c8e839560 | 89 | #define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */ |
| AnnaBridge | 163:e59c8e839560 | 90 | |
| AnnaBridge | 163:e59c8e839560 | 91 | typedef enum IRQn { |
| AnnaBridge | 163:e59c8e839560 | 92 | /* Auxiliary constants */ |
| AnnaBridge | 163:e59c8e839560 | 93 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 94 | |
| AnnaBridge | 163:e59c8e839560 | 95 | /* Core interrupts */ |
| AnnaBridge | 163:e59c8e839560 | 96 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 97 | HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 98 | MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 99 | BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 100 | UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 101 | SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 102 | DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 103 | PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 104 | SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 105 | |
| AnnaBridge | 163:e59c8e839560 | 106 | /* Device specific interrupts */ |
| AnnaBridge | 163:e59c8e839560 | 107 | WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */ |
| AnnaBridge | 163:e59c8e839560 | 108 | DMA0_IRQn = 1, /**< DMA controller */ |
| AnnaBridge | 163:e59c8e839560 | 109 | GINT0_IRQn = 2, /**< GPIO group 0 */ |
| AnnaBridge | 163:e59c8e839560 | 110 | GINT1_IRQn = 3, /**< GPIO group 1 */ |
| AnnaBridge | 163:e59c8e839560 | 111 | PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */ |
| AnnaBridge | 163:e59c8e839560 | 112 | PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */ |
| AnnaBridge | 163:e59c8e839560 | 113 | PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */ |
| AnnaBridge | 163:e59c8e839560 | 114 | PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */ |
| AnnaBridge | 163:e59c8e839560 | 115 | UTICK0_IRQn = 8, /**< Micro-tick Timer */ |
| AnnaBridge | 163:e59c8e839560 | 116 | MRT0_IRQn = 9, /**< Multi-rate timer */ |
| AnnaBridge | 163:e59c8e839560 | 117 | CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */ |
| AnnaBridge | 163:e59c8e839560 | 118 | CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */ |
| AnnaBridge | 163:e59c8e839560 | 119 | SCT0_IRQn = 12, /**< SCTimer/PWM */ |
| AnnaBridge | 163:e59c8e839560 | 120 | CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */ |
| AnnaBridge | 163:e59c8e839560 | 121 | FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ |
| AnnaBridge | 163:e59c8e839560 | 122 | FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ |
| AnnaBridge | 163:e59c8e839560 | 123 | FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ |
| AnnaBridge | 163:e59c8e839560 | 124 | FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ |
| AnnaBridge | 163:e59c8e839560 | 125 | FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ |
| AnnaBridge | 163:e59c8e839560 | 126 | FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */ |
| AnnaBridge | 163:e59c8e839560 | 127 | FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */ |
| AnnaBridge | 163:e59c8e839560 | 128 | FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */ |
| AnnaBridge | 163:e59c8e839560 | 129 | ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */ |
| AnnaBridge | 163:e59c8e839560 | 130 | ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */ |
| AnnaBridge | 163:e59c8e839560 | 131 | ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */ |
| AnnaBridge | 163:e59c8e839560 | 132 | DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */ |
| AnnaBridge | 163:e59c8e839560 | 133 | HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */ |
| AnnaBridge | 163:e59c8e839560 | 134 | USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 135 | USB0_IRQn = 28, /**< USB device */ |
| AnnaBridge | 163:e59c8e839560 | 136 | RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */ |
| AnnaBridge | 163:e59c8e839560 | 137 | Reserved46_IRQn = 30, /**< Reserved interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 138 | Reserved47_IRQn = 31, /**< Reserved interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 139 | PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */ |
| AnnaBridge | 163:e59c8e839560 | 140 | PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */ |
| AnnaBridge | 163:e59c8e839560 | 141 | PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */ |
| AnnaBridge | 163:e59c8e839560 | 142 | PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */ |
| AnnaBridge | 163:e59c8e839560 | 143 | CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */ |
| AnnaBridge | 163:e59c8e839560 | 144 | CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */ |
| AnnaBridge | 163:e59c8e839560 | 145 | RIT_IRQn = 38, /**< Repetitive Interrupt Timer */ |
| AnnaBridge | 163:e59c8e839560 | 146 | SPIFI0_IRQn = 39, /**< SPI flash interface */ |
| AnnaBridge | 163:e59c8e839560 | 147 | FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */ |
| AnnaBridge | 163:e59c8e839560 | 148 | FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */ |
| AnnaBridge | 163:e59c8e839560 | 149 | SDIO_IRQn = 42, /**< SD/MMC */ |
| AnnaBridge | 163:e59c8e839560 | 150 | CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */ |
| AnnaBridge | 163:e59c8e839560 | 151 | CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */ |
| AnnaBridge | 163:e59c8e839560 | 152 | CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */ |
| AnnaBridge | 163:e59c8e839560 | 153 | CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */ |
| AnnaBridge | 163:e59c8e839560 | 154 | USB1_IRQn = 47, /**< USB1 interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 155 | USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ |
| AnnaBridge | 163:e59c8e839560 | 156 | ETHERNET_IRQn = 49, /**< Ethernet */ |
| AnnaBridge | 163:e59c8e839560 | 157 | ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 158 | ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 159 | EEPROM_IRQn = 52, /**< EEPROM interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 160 | LCD_IRQn = 53, /**< LCD interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 161 | SHA_IRQn = 54, /**< SHA interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 162 | SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 163 | SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 164 | } IRQn_Type; |
| AnnaBridge | 163:e59c8e839560 | 165 | |
| AnnaBridge | 163:e59c8e839560 | 166 | /*! |
| AnnaBridge | 163:e59c8e839560 | 167 | * @} |
| AnnaBridge | 163:e59c8e839560 | 168 | */ /* end of group Interrupt_vector_numbers */ |
| AnnaBridge | 163:e59c8e839560 | 169 | |
| AnnaBridge | 163:e59c8e839560 | 170 | |
| AnnaBridge | 163:e59c8e839560 | 171 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 172 | -- Cortex M4 Core Configuration |
| AnnaBridge | 163:e59c8e839560 | 173 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 174 | |
| AnnaBridge | 163:e59c8e839560 | 175 | /*! |
| AnnaBridge | 163:e59c8e839560 | 176 | * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration |
| AnnaBridge | 163:e59c8e839560 | 177 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 178 | */ |
| AnnaBridge | 163:e59c8e839560 | 179 | |
| AnnaBridge | 163:e59c8e839560 | 180 | #define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ |
| AnnaBridge | 163:e59c8e839560 | 181 | #define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */ |
| AnnaBridge | 163:e59c8e839560 | 182 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ |
| AnnaBridge | 163:e59c8e839560 | 183 | #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ |
| AnnaBridge | 163:e59c8e839560 | 184 | |
| AnnaBridge | 163:e59c8e839560 | 185 | #include "core_cm4.h" /* Core Peripheral Access Layer */ |
| AnnaBridge | 163:e59c8e839560 | 186 | #include "system_LPC54628.h" /* Device specific configuration file */ |
| AnnaBridge | 163:e59c8e839560 | 187 | |
| AnnaBridge | 163:e59c8e839560 | 188 | /*! |
| AnnaBridge | 163:e59c8e839560 | 189 | * @} |
| AnnaBridge | 163:e59c8e839560 | 190 | */ /* end of group Cortex_Core_Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 191 | |
| AnnaBridge | 163:e59c8e839560 | 192 | |
| AnnaBridge | 163:e59c8e839560 | 193 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 194 | -- Device Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 195 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 196 | |
| AnnaBridge | 163:e59c8e839560 | 197 | /*! |
| AnnaBridge | 163:e59c8e839560 | 198 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 199 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 200 | */ |
| AnnaBridge | 163:e59c8e839560 | 201 | |
| AnnaBridge | 163:e59c8e839560 | 202 | |
| AnnaBridge | 163:e59c8e839560 | 203 | /* |
| AnnaBridge | 163:e59c8e839560 | 204 | ** Start of section using anonymous unions |
| AnnaBridge | 163:e59c8e839560 | 205 | */ |
| AnnaBridge | 163:e59c8e839560 | 206 | |
| AnnaBridge | 163:e59c8e839560 | 207 | #if defined(__ARMCC_VERSION) |
| AnnaBridge | 163:e59c8e839560 | 208 | #pragma push |
| AnnaBridge | 163:e59c8e839560 | 209 | #pragma anon_unions |
| AnnaBridge | 163:e59c8e839560 | 210 | #elif defined(__GNUC__) |
| AnnaBridge | 163:e59c8e839560 | 211 | /* anonymous unions are enabled by default */ |
| AnnaBridge | 163:e59c8e839560 | 212 | #elif defined(__IAR_SYSTEMS_ICC__) |
| AnnaBridge | 163:e59c8e839560 | 213 | #pragma language=extended |
| AnnaBridge | 163:e59c8e839560 | 214 | #else |
| AnnaBridge | 163:e59c8e839560 | 215 | #error Not supported compiler type |
| AnnaBridge | 163:e59c8e839560 | 216 | #endif |
| AnnaBridge | 163:e59c8e839560 | 217 | |
| AnnaBridge | 163:e59c8e839560 | 218 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 219 | -- ADC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 220 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 221 | |
| AnnaBridge | 163:e59c8e839560 | 222 | /*! |
| AnnaBridge | 163:e59c8e839560 | 223 | * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 224 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 225 | */ |
| AnnaBridge | 163:e59c8e839560 | 226 | |
| AnnaBridge | 163:e59c8e839560 | 227 | /** ADC - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 228 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 229 | __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 230 | __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 231 | __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 232 | __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 233 | uint8_t RESERVED_0[8]; |
| AnnaBridge | 163:e59c8e839560 | 234 | __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 235 | __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ |
| AnnaBridge | 163:e59c8e839560 | 236 | __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ |
| AnnaBridge | 163:e59c8e839560 | 237 | __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ |
| AnnaBridge | 163:e59c8e839560 | 238 | __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 239 | __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ |
| AnnaBridge | 163:e59c8e839560 | 240 | __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ |
| AnnaBridge | 163:e59c8e839560 | 241 | __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ |
| AnnaBridge | 163:e59c8e839560 | 242 | __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */ |
| AnnaBridge | 163:e59c8e839560 | 243 | __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */ |
| AnnaBridge | 163:e59c8e839560 | 244 | } ADC_Type; |
| AnnaBridge | 163:e59c8e839560 | 245 | |
| AnnaBridge | 163:e59c8e839560 | 246 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 247 | -- ADC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 248 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 249 | |
| AnnaBridge | 163:e59c8e839560 | 250 | /*! |
| AnnaBridge | 163:e59c8e839560 | 251 | * @addtogroup ADC_Register_Masks ADC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 252 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 253 | */ |
| AnnaBridge | 163:e59c8e839560 | 254 | |
| AnnaBridge | 163:e59c8e839560 | 255 | /*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ |
| AnnaBridge | 163:e59c8e839560 | 256 | #define ADC_CTRL_CLKDIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 257 | #define ADC_CTRL_CLKDIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 258 | #define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 259 | #define ADC_CTRL_ASYNMODE_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 260 | #define ADC_CTRL_ASYNMODE_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 261 | #define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 262 | #define ADC_CTRL_RESOL_MASK (0x600U) |
| AnnaBridge | 163:e59c8e839560 | 263 | #define ADC_CTRL_RESOL_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 264 | #define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 265 | #define ADC_CTRL_BYPASSCAL_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 266 | #define ADC_CTRL_BYPASSCAL_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 267 | #define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 268 | #define ADC_CTRL_TSAMP_MASK (0x7000U) |
| AnnaBridge | 163:e59c8e839560 | 269 | #define ADC_CTRL_TSAMP_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 270 | #define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 271 | |
| AnnaBridge | 163:e59c8e839560 | 272 | /*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */ |
| AnnaBridge | 163:e59c8e839560 | 273 | #define ADC_INSEL_SEL_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 274 | #define ADC_INSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 275 | #define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 276 | |
| AnnaBridge | 163:e59c8e839560 | 277 | /*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ |
| AnnaBridge | 163:e59c8e839560 | 278 | #define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) |
| AnnaBridge | 163:e59c8e839560 | 279 | #define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 280 | #define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 281 | #define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U) |
| AnnaBridge | 163:e59c8e839560 | 282 | #define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 283 | #define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) |
| AnnaBridge | 163:e59c8e839560 | 284 | #define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 285 | #define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 286 | #define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 287 | #define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 288 | #define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 289 | #define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 290 | #define ADC_SEQ_CTRL_START_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 291 | #define ADC_SEQ_CTRL_START_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 292 | #define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) |
| AnnaBridge | 163:e59c8e839560 | 293 | #define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 294 | #define ADC_SEQ_CTRL_BURST_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 295 | #define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 296 | #define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 297 | #define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 298 | #define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 299 | #define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 300 | #define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 301 | #define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 302 | #define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 303 | #define ADC_SEQ_CTRL_MODE_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 304 | #define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 305 | #define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 306 | #define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 307 | #define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 308 | |
| AnnaBridge | 163:e59c8e839560 | 309 | /* The count of ADC_SEQ_CTRL */ |
| AnnaBridge | 163:e59c8e839560 | 310 | #define ADC_SEQ_CTRL_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 311 | |
| AnnaBridge | 163:e59c8e839560 | 312 | /*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ |
| AnnaBridge | 163:e59c8e839560 | 313 | #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 314 | #define ADC_SEQ_GDAT_RESULT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 315 | #define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 316 | #define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) |
| AnnaBridge | 163:e59c8e839560 | 317 | #define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 318 | #define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 319 | #define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) |
| AnnaBridge | 163:e59c8e839560 | 320 | #define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 321 | #define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 322 | #define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) |
| AnnaBridge | 163:e59c8e839560 | 323 | #define ADC_SEQ_GDAT_CHN_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 324 | #define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 325 | #define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 326 | #define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 327 | #define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 328 | #define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 329 | #define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 330 | #define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 331 | |
| AnnaBridge | 163:e59c8e839560 | 332 | /* The count of ADC_SEQ_GDAT */ |
| AnnaBridge | 163:e59c8e839560 | 333 | #define ADC_SEQ_GDAT_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 334 | |
| AnnaBridge | 163:e59c8e839560 | 335 | /*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */ |
| AnnaBridge | 163:e59c8e839560 | 336 | #define ADC_DAT_RESULT_MASK (0xFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 337 | #define ADC_DAT_RESULT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 338 | #define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 339 | #define ADC_DAT_THCMPRANGE_MASK (0x30000U) |
| AnnaBridge | 163:e59c8e839560 | 340 | #define ADC_DAT_THCMPRANGE_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 341 | #define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 342 | #define ADC_DAT_THCMPCROSS_MASK (0xC0000U) |
| AnnaBridge | 163:e59c8e839560 | 343 | #define ADC_DAT_THCMPCROSS_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 344 | #define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 345 | #define ADC_DAT_CHANNEL_MASK (0x3C000000U) |
| AnnaBridge | 163:e59c8e839560 | 346 | #define ADC_DAT_CHANNEL_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 347 | #define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 348 | #define ADC_DAT_OVERRUN_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 349 | #define ADC_DAT_OVERRUN_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 350 | #define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 351 | #define ADC_DAT_DATAVALID_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 352 | #define ADC_DAT_DATAVALID_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 353 | #define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 354 | |
| AnnaBridge | 163:e59c8e839560 | 355 | /* The count of ADC_DAT */ |
| AnnaBridge | 163:e59c8e839560 | 356 | #define ADC_DAT_COUNT (12U) |
| AnnaBridge | 163:e59c8e839560 | 357 | |
| AnnaBridge | 163:e59c8e839560 | 358 | /*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ |
| AnnaBridge | 163:e59c8e839560 | 359 | #define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 360 | #define ADC_THR0_LOW_THRLOW_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 361 | #define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 362 | |
| AnnaBridge | 163:e59c8e839560 | 363 | /*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ |
| AnnaBridge | 163:e59c8e839560 | 364 | #define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 365 | #define ADC_THR1_LOW_THRLOW_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 366 | #define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 367 | |
| AnnaBridge | 163:e59c8e839560 | 368 | /*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ |
| AnnaBridge | 163:e59c8e839560 | 369 | #define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 370 | #define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 371 | #define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 372 | |
| AnnaBridge | 163:e59c8e839560 | 373 | /*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ |
| AnnaBridge | 163:e59c8e839560 | 374 | #define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 375 | #define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 376 | #define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 377 | |
| AnnaBridge | 163:e59c8e839560 | 378 | /*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ |
| AnnaBridge | 163:e59c8e839560 | 379 | #define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 380 | #define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 381 | #define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 382 | #define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 383 | #define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 384 | #define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 385 | #define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 386 | #define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 387 | #define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 388 | #define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 389 | #define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 390 | #define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 391 | #define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 392 | #define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 393 | #define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 394 | #define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 395 | #define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 396 | #define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 397 | #define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 398 | #define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 399 | #define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 400 | #define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 401 | #define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 402 | #define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 403 | #define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 404 | #define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 405 | #define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 406 | #define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 407 | #define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 408 | #define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 409 | #define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 410 | #define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 411 | #define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 412 | #define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 413 | #define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 414 | #define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 415 | |
| AnnaBridge | 163:e59c8e839560 | 416 | /*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ |
| AnnaBridge | 163:e59c8e839560 | 417 | #define ADC_INTEN_SEQA_INTEN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 418 | #define ADC_INTEN_SEQA_INTEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 419 | #define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 420 | #define ADC_INTEN_SEQB_INTEN_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 421 | #define ADC_INTEN_SEQB_INTEN_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 422 | #define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 423 | #define ADC_INTEN_OVR_INTEN_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 424 | #define ADC_INTEN_OVR_INTEN_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 425 | #define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 426 | #define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) |
| AnnaBridge | 163:e59c8e839560 | 427 | #define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 428 | #define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 429 | #define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) |
| AnnaBridge | 163:e59c8e839560 | 430 | #define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 431 | #define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 432 | #define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) |
| AnnaBridge | 163:e59c8e839560 | 433 | #define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 434 | #define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 435 | #define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) |
| AnnaBridge | 163:e59c8e839560 | 436 | #define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 437 | #define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 438 | #define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) |
| AnnaBridge | 163:e59c8e839560 | 439 | #define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 440 | #define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 441 | #define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) |
| AnnaBridge | 163:e59c8e839560 | 442 | #define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 443 | #define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 444 | #define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) |
| AnnaBridge | 163:e59c8e839560 | 445 | #define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 446 | #define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 447 | #define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) |
| AnnaBridge | 163:e59c8e839560 | 448 | #define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 449 | #define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) |
| AnnaBridge | 163:e59c8e839560 | 450 | #define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) |
| AnnaBridge | 163:e59c8e839560 | 451 | #define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 452 | #define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) |
| AnnaBridge | 163:e59c8e839560 | 453 | #define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) |
| AnnaBridge | 163:e59c8e839560 | 454 | #define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 455 | #define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) |
| AnnaBridge | 163:e59c8e839560 | 456 | #define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) |
| AnnaBridge | 163:e59c8e839560 | 457 | #define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 458 | #define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) |
| AnnaBridge | 163:e59c8e839560 | 459 | #define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) |
| AnnaBridge | 163:e59c8e839560 | 460 | #define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 461 | #define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) |
| AnnaBridge | 163:e59c8e839560 | 462 | |
| AnnaBridge | 163:e59c8e839560 | 463 | /*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ |
| AnnaBridge | 163:e59c8e839560 | 464 | #define ADC_FLAGS_THCMP0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 465 | #define ADC_FLAGS_THCMP0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 466 | #define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 467 | #define ADC_FLAGS_THCMP1_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 468 | #define ADC_FLAGS_THCMP1_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 469 | #define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 470 | #define ADC_FLAGS_THCMP2_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 471 | #define ADC_FLAGS_THCMP2_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 472 | #define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 473 | #define ADC_FLAGS_THCMP3_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 474 | #define ADC_FLAGS_THCMP3_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 475 | #define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 476 | #define ADC_FLAGS_THCMP4_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 477 | #define ADC_FLAGS_THCMP4_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 478 | #define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 479 | #define ADC_FLAGS_THCMP5_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 480 | #define ADC_FLAGS_THCMP5_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 481 | #define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 482 | #define ADC_FLAGS_THCMP6_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 483 | #define ADC_FLAGS_THCMP6_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 484 | #define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 485 | #define ADC_FLAGS_THCMP7_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 486 | #define ADC_FLAGS_THCMP7_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 487 | #define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) |
| AnnaBridge | 163:e59c8e839560 | 488 | #define ADC_FLAGS_THCMP8_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 489 | #define ADC_FLAGS_THCMP8_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 490 | #define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) |
| AnnaBridge | 163:e59c8e839560 | 491 | #define ADC_FLAGS_THCMP9_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 492 | #define ADC_FLAGS_THCMP9_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 493 | #define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) |
| AnnaBridge | 163:e59c8e839560 | 494 | #define ADC_FLAGS_THCMP10_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 495 | #define ADC_FLAGS_THCMP10_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 496 | #define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) |
| AnnaBridge | 163:e59c8e839560 | 497 | #define ADC_FLAGS_THCMP11_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 498 | #define ADC_FLAGS_THCMP11_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 499 | #define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) |
| AnnaBridge | 163:e59c8e839560 | 500 | #define ADC_FLAGS_OVERRUN0_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 501 | #define ADC_FLAGS_OVERRUN0_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 502 | #define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 503 | #define ADC_FLAGS_OVERRUN1_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 504 | #define ADC_FLAGS_OVERRUN1_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 505 | #define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 506 | #define ADC_FLAGS_OVERRUN2_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 507 | #define ADC_FLAGS_OVERRUN2_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 508 | #define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 509 | #define ADC_FLAGS_OVERRUN3_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 510 | #define ADC_FLAGS_OVERRUN3_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 511 | #define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 512 | #define ADC_FLAGS_OVERRUN4_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 513 | #define ADC_FLAGS_OVERRUN4_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 514 | #define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 515 | #define ADC_FLAGS_OVERRUN5_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 516 | #define ADC_FLAGS_OVERRUN5_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 517 | #define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 518 | #define ADC_FLAGS_OVERRUN6_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 519 | #define ADC_FLAGS_OVERRUN6_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 520 | #define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 521 | #define ADC_FLAGS_OVERRUN7_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 522 | #define ADC_FLAGS_OVERRUN7_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 523 | #define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) |
| AnnaBridge | 163:e59c8e839560 | 524 | #define ADC_FLAGS_OVERRUN8_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 525 | #define ADC_FLAGS_OVERRUN8_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 526 | #define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) |
| AnnaBridge | 163:e59c8e839560 | 527 | #define ADC_FLAGS_OVERRUN9_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 528 | #define ADC_FLAGS_OVERRUN9_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 529 | #define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) |
| AnnaBridge | 163:e59c8e839560 | 530 | #define ADC_FLAGS_OVERRUN10_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 531 | #define ADC_FLAGS_OVERRUN10_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 532 | #define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) |
| AnnaBridge | 163:e59c8e839560 | 533 | #define ADC_FLAGS_OVERRUN11_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 534 | #define ADC_FLAGS_OVERRUN11_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 535 | #define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) |
| AnnaBridge | 163:e59c8e839560 | 536 | #define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 537 | #define ADC_FLAGS_SEQA_OVR_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 538 | #define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 539 | #define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 540 | #define ADC_FLAGS_SEQB_OVR_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 541 | #define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 542 | #define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 543 | #define ADC_FLAGS_SEQA_INT_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 544 | #define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 545 | #define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 546 | #define ADC_FLAGS_SEQB_INT_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 547 | #define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 548 | #define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 549 | #define ADC_FLAGS_THCMP_INT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 550 | #define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 551 | #define ADC_FLAGS_OVR_INT_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 552 | #define ADC_FLAGS_OVR_INT_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 553 | #define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 554 | |
| AnnaBridge | 163:e59c8e839560 | 555 | /*! @name STARTUP - ADC Startup register. */ |
| AnnaBridge | 163:e59c8e839560 | 556 | #define ADC_STARTUP_ADC_ENA_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 557 | #define ADC_STARTUP_ADC_ENA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 558 | #define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 559 | #define ADC_STARTUP_ADC_INIT_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 560 | #define ADC_STARTUP_ADC_INIT_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 561 | #define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 562 | |
| AnnaBridge | 163:e59c8e839560 | 563 | /*! @name CALIB - ADC Calibration register. */ |
| AnnaBridge | 163:e59c8e839560 | 564 | #define ADC_CALIB_CALIB_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 565 | #define ADC_CALIB_CALIB_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 566 | #define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 567 | #define ADC_CALIB_CALREQD_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 568 | #define ADC_CALIB_CALREQD_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 569 | #define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 570 | #define ADC_CALIB_CALVALUE_MASK (0x1FCU) |
| AnnaBridge | 163:e59c8e839560 | 571 | #define ADC_CALIB_CALVALUE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 572 | #define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 573 | |
| AnnaBridge | 163:e59c8e839560 | 574 | |
| AnnaBridge | 163:e59c8e839560 | 575 | /*! |
| AnnaBridge | 163:e59c8e839560 | 576 | * @} |
| AnnaBridge | 163:e59c8e839560 | 577 | */ /* end of group ADC_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 578 | |
| AnnaBridge | 163:e59c8e839560 | 579 | |
| AnnaBridge | 163:e59c8e839560 | 580 | /* ADC - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 581 | /** Peripheral ADC0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 582 | #define ADC0_BASE (0x400A0000u) |
| AnnaBridge | 163:e59c8e839560 | 583 | /** Peripheral ADC0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 584 | #define ADC0 ((ADC_Type *)ADC0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 585 | /** Array initializer of ADC peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 586 | #define ADC_BASE_ADDRS { ADC0_BASE } |
| AnnaBridge | 163:e59c8e839560 | 587 | /** Array initializer of ADC peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 588 | #define ADC_BASE_PTRS { ADC0 } |
| AnnaBridge | 163:e59c8e839560 | 589 | /** Interrupt vectors for the ADC peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 590 | #define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 591 | #define ADC_THCMP_IRQS { ADC0_THCMP_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 592 | |
| AnnaBridge | 163:e59c8e839560 | 593 | /*! |
| AnnaBridge | 163:e59c8e839560 | 594 | * @} |
| AnnaBridge | 163:e59c8e839560 | 595 | */ /* end of group ADC_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 596 | |
| AnnaBridge | 163:e59c8e839560 | 597 | |
| AnnaBridge | 163:e59c8e839560 | 598 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 599 | -- ASYNC_SYSCON Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 600 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 601 | |
| AnnaBridge | 163:e59c8e839560 | 602 | /*! |
| AnnaBridge | 163:e59c8e839560 | 603 | * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 604 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 605 | */ |
| AnnaBridge | 163:e59c8e839560 | 606 | |
| AnnaBridge | 163:e59c8e839560 | 607 | /** ASYNC_SYSCON - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 608 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 609 | __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 610 | __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 611 | __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 612 | uint8_t RESERVED_0[4]; |
| AnnaBridge | 163:e59c8e839560 | 613 | __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 614 | __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 615 | __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 616 | uint8_t RESERVED_1[4]; |
| AnnaBridge | 163:e59c8e839560 | 617 | __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 618 | } ASYNC_SYSCON_Type; |
| AnnaBridge | 163:e59c8e839560 | 619 | |
| AnnaBridge | 163:e59c8e839560 | 620 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 621 | -- ASYNC_SYSCON Register Masks |
| AnnaBridge | 163:e59c8e839560 | 622 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 623 | |
| AnnaBridge | 163:e59c8e839560 | 624 | /*! |
| AnnaBridge | 163:e59c8e839560 | 625 | * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks |
| AnnaBridge | 163:e59c8e839560 | 626 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 627 | */ |
| AnnaBridge | 163:e59c8e839560 | 628 | |
| AnnaBridge | 163:e59c8e839560 | 629 | /*! @name ASYNCPRESETCTRL - Async peripheral reset control */ |
| AnnaBridge | 163:e59c8e839560 | 630 | #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 631 | #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 632 | #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 633 | #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 634 | #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 635 | #define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 636 | |
| AnnaBridge | 163:e59c8e839560 | 637 | /*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */ |
| AnnaBridge | 163:e59c8e839560 | 638 | #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 639 | #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 640 | #define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 641 | |
| AnnaBridge | 163:e59c8e839560 | 642 | /*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */ |
| AnnaBridge | 163:e59c8e839560 | 643 | #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 644 | #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 645 | #define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 646 | |
| AnnaBridge | 163:e59c8e839560 | 647 | /*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */ |
| AnnaBridge | 163:e59c8e839560 | 648 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 649 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 650 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 651 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 652 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 653 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 654 | |
| AnnaBridge | 163:e59c8e839560 | 655 | /*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */ |
| AnnaBridge | 163:e59c8e839560 | 656 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 657 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 658 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 659 | |
| AnnaBridge | 163:e59c8e839560 | 660 | /*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */ |
| AnnaBridge | 163:e59c8e839560 | 661 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 662 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 663 | #define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 664 | |
| AnnaBridge | 163:e59c8e839560 | 665 | /*! @name ASYNCAPBCLKSELA - Async APB clock source select A */ |
| AnnaBridge | 163:e59c8e839560 | 666 | #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 667 | #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 668 | #define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 669 | |
| AnnaBridge | 163:e59c8e839560 | 670 | |
| AnnaBridge | 163:e59c8e839560 | 671 | /*! |
| AnnaBridge | 163:e59c8e839560 | 672 | * @} |
| AnnaBridge | 163:e59c8e839560 | 673 | */ /* end of group ASYNC_SYSCON_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 674 | |
| AnnaBridge | 163:e59c8e839560 | 675 | |
| AnnaBridge | 163:e59c8e839560 | 676 | /* ASYNC_SYSCON - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 677 | /** Peripheral ASYNC_SYSCON base address */ |
| AnnaBridge | 163:e59c8e839560 | 678 | #define ASYNC_SYSCON_BASE (0x40040000u) |
| AnnaBridge | 163:e59c8e839560 | 679 | /** Peripheral ASYNC_SYSCON base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 680 | #define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE) |
| AnnaBridge | 163:e59c8e839560 | 681 | /** Array initializer of ASYNC_SYSCON peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 682 | #define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE } |
| AnnaBridge | 163:e59c8e839560 | 683 | /** Array initializer of ASYNC_SYSCON peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 684 | #define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON } |
| AnnaBridge | 163:e59c8e839560 | 685 | |
| AnnaBridge | 163:e59c8e839560 | 686 | /*! |
| AnnaBridge | 163:e59c8e839560 | 687 | * @} |
| AnnaBridge | 163:e59c8e839560 | 688 | */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 689 | |
| AnnaBridge | 163:e59c8e839560 | 690 | |
| AnnaBridge | 163:e59c8e839560 | 691 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 692 | -- CAN Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 693 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 694 | |
| AnnaBridge | 163:e59c8e839560 | 695 | /*! |
| AnnaBridge | 163:e59c8e839560 | 696 | * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 697 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 698 | */ |
| AnnaBridge | 163:e59c8e839560 | 699 | |
| AnnaBridge | 163:e59c8e839560 | 700 | /** CAN - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 701 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 702 | uint8_t RESERVED_0[12]; |
| AnnaBridge | 163:e59c8e839560 | 703 | __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 704 | __IO uint32_t TEST; /**< Test Register, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 705 | uint8_t RESERVED_1[4]; |
| AnnaBridge | 163:e59c8e839560 | 706 | __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 707 | __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 708 | __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 709 | __IO uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 710 | __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 711 | __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 712 | uint8_t RESERVED_2[16]; |
| AnnaBridge | 163:e59c8e839560 | 713 | __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 714 | __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */ |
| AnnaBridge | 163:e59c8e839560 | 715 | __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */ |
| AnnaBridge | 163:e59c8e839560 | 716 | uint8_t RESERVED_3[4]; |
| AnnaBridge | 163:e59c8e839560 | 717 | __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */ |
| AnnaBridge | 163:e59c8e839560 | 718 | __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */ |
| AnnaBridge | 163:e59c8e839560 | 719 | __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */ |
| AnnaBridge | 163:e59c8e839560 | 720 | __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 721 | uint8_t RESERVED_4[32]; |
| AnnaBridge | 163:e59c8e839560 | 722 | __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 723 | __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */ |
| AnnaBridge | 163:e59c8e839560 | 724 | __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */ |
| AnnaBridge | 163:e59c8e839560 | 725 | uint8_t RESERVED_5[4]; |
| AnnaBridge | 163:e59c8e839560 | 726 | __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */ |
| AnnaBridge | 163:e59c8e839560 | 727 | __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */ |
| AnnaBridge | 163:e59c8e839560 | 728 | __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */ |
| AnnaBridge | 163:e59c8e839560 | 729 | __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */ |
| AnnaBridge | 163:e59c8e839560 | 730 | __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */ |
| AnnaBridge | 163:e59c8e839560 | 731 | __IO uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */ |
| AnnaBridge | 163:e59c8e839560 | 732 | __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */ |
| AnnaBridge | 163:e59c8e839560 | 733 | __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */ |
| AnnaBridge | 163:e59c8e839560 | 734 | __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */ |
| AnnaBridge | 163:e59c8e839560 | 735 | __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */ |
| AnnaBridge | 163:e59c8e839560 | 736 | __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */ |
| AnnaBridge | 163:e59c8e839560 | 737 | __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */ |
| AnnaBridge | 163:e59c8e839560 | 738 | __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */ |
| AnnaBridge | 163:e59c8e839560 | 739 | __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */ |
| AnnaBridge | 163:e59c8e839560 | 740 | __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */ |
| AnnaBridge | 163:e59c8e839560 | 741 | __IO uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */ |
| AnnaBridge | 163:e59c8e839560 | 742 | __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */ |
| AnnaBridge | 163:e59c8e839560 | 743 | __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */ |
| AnnaBridge | 163:e59c8e839560 | 744 | __IO uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */ |
| AnnaBridge | 163:e59c8e839560 | 745 | __IO uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */ |
| AnnaBridge | 163:e59c8e839560 | 746 | __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */ |
| AnnaBridge | 163:e59c8e839560 | 747 | __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */ |
| AnnaBridge | 163:e59c8e839560 | 748 | uint8_t RESERVED_6[8]; |
| AnnaBridge | 163:e59c8e839560 | 749 | __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */ |
| AnnaBridge | 163:e59c8e839560 | 750 | __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */ |
| AnnaBridge | 163:e59c8e839560 | 751 | __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */ |
| AnnaBridge | 163:e59c8e839560 | 752 | uint8_t RESERVED_7[260]; |
| AnnaBridge | 163:e59c8e839560 | 753 | __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */ |
| AnnaBridge | 163:e59c8e839560 | 754 | uint8_t RESERVED_8[508]; |
| AnnaBridge | 163:e59c8e839560 | 755 | __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */ |
| AnnaBridge | 163:e59c8e839560 | 756 | uint8_t RESERVED_9[508]; |
| AnnaBridge | 163:e59c8e839560 | 757 | __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */ |
| AnnaBridge | 163:e59c8e839560 | 758 | } CAN_Type; |
| AnnaBridge | 163:e59c8e839560 | 759 | |
| AnnaBridge | 163:e59c8e839560 | 760 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 761 | -- CAN Register Masks |
| AnnaBridge | 163:e59c8e839560 | 762 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 763 | |
| AnnaBridge | 163:e59c8e839560 | 764 | /*! |
| AnnaBridge | 163:e59c8e839560 | 765 | * @addtogroup CAN_Register_Masks CAN Register Masks |
| AnnaBridge | 163:e59c8e839560 | 766 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 767 | */ |
| AnnaBridge | 163:e59c8e839560 | 768 | |
| AnnaBridge | 163:e59c8e839560 | 769 | /*! @name DBTP - Data Bit Timing Prescaler Register */ |
| AnnaBridge | 163:e59c8e839560 | 770 | #define CAN_DBTP_DSJW_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 771 | #define CAN_DBTP_DSJW_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 772 | #define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 773 | #define CAN_DBTP_DTSEG2_MASK (0xF0U) |
| AnnaBridge | 163:e59c8e839560 | 774 | #define CAN_DBTP_DTSEG2_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 775 | #define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 776 | #define CAN_DBTP_DTSEG1_MASK (0x1F00U) |
| AnnaBridge | 163:e59c8e839560 | 777 | #define CAN_DBTP_DTSEG1_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 778 | #define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 779 | #define CAN_DBTP_DBRP_MASK (0x1F0000U) |
| AnnaBridge | 163:e59c8e839560 | 780 | #define CAN_DBTP_DBRP_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 781 | #define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 782 | #define CAN_DBTP_TDC_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 783 | #define CAN_DBTP_TDC_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 784 | #define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 785 | |
| AnnaBridge | 163:e59c8e839560 | 786 | /*! @name TEST - Test Register */ |
| AnnaBridge | 163:e59c8e839560 | 787 | #define CAN_TEST_LBCK_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 788 | #define CAN_TEST_LBCK_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 789 | #define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 790 | #define CAN_TEST_TX_MASK (0x60U) |
| AnnaBridge | 163:e59c8e839560 | 791 | #define CAN_TEST_TX_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 792 | #define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 793 | #define CAN_TEST_RX_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 794 | #define CAN_TEST_RX_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 795 | #define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 796 | |
| AnnaBridge | 163:e59c8e839560 | 797 | /*! @name CCCR - CC Control Register */ |
| AnnaBridge | 163:e59c8e839560 | 798 | #define CAN_CCCR_INIT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 799 | #define CAN_CCCR_INIT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 800 | #define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 801 | #define CAN_CCCR_CCE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 802 | #define CAN_CCCR_CCE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 803 | #define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 804 | #define CAN_CCCR_ASM_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 805 | #define CAN_CCCR_ASM_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 806 | #define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 807 | #define CAN_CCCR_CSA_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 808 | #define CAN_CCCR_CSA_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 809 | #define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 810 | #define CAN_CCCR_CSR_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 811 | #define CAN_CCCR_CSR_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 812 | #define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 813 | #define CAN_CCCR_MON_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 814 | #define CAN_CCCR_MON_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 815 | #define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK) |
| AnnaBridge | 163:e59c8e839560 | 816 | #define CAN_CCCR_DAR_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 817 | #define CAN_CCCR_DAR_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 818 | #define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 819 | #define CAN_CCCR_TEST_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 820 | #define CAN_CCCR_TEST_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 821 | #define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 822 | #define CAN_CCCR_FDOE_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 823 | #define CAN_CCCR_FDOE_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 824 | #define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 825 | #define CAN_CCCR_BRSE_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 826 | #define CAN_CCCR_BRSE_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 827 | #define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 828 | #define CAN_CCCR_PXHD_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 829 | #define CAN_CCCR_PXHD_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 830 | #define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 831 | #define CAN_CCCR_EFBI_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 832 | #define CAN_CCCR_EFBI_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 833 | #define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 834 | #define CAN_CCCR_TXP_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 835 | #define CAN_CCCR_TXP_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 836 | #define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 837 | #define CAN_CCCR_NISO_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 838 | #define CAN_CCCR_NISO_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 839 | #define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 840 | |
| AnnaBridge | 163:e59c8e839560 | 841 | /*! @name NBTP - Nominal Bit Timing and Prescaler Register */ |
| AnnaBridge | 163:e59c8e839560 | 842 | #define CAN_NBTP_NTSEG2_MASK (0x7FU) |
| AnnaBridge | 163:e59c8e839560 | 843 | #define CAN_NBTP_NTSEG2_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 844 | #define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 845 | #define CAN_NBTP_NTSEG1_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 846 | #define CAN_NBTP_NTSEG1_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 847 | #define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 848 | #define CAN_NBTP_NBRP_MASK (0x1FF0000U) |
| AnnaBridge | 163:e59c8e839560 | 849 | #define CAN_NBTP_NBRP_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 850 | #define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 851 | #define CAN_NBTP_NSJW_MASK (0xFE000000U) |
| AnnaBridge | 163:e59c8e839560 | 852 | #define CAN_NBTP_NSJW_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 853 | #define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 854 | |
| AnnaBridge | 163:e59c8e839560 | 855 | /*! @name TSCC - Timestamp Counter Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 856 | #define CAN_TSCC_TSS_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 857 | #define CAN_TSCC_TSS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 858 | #define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 859 | #define CAN_TSCC_TCP_MASK (0xF0000U) |
| AnnaBridge | 163:e59c8e839560 | 860 | #define CAN_TSCC_TCP_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 861 | #define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 862 | |
| AnnaBridge | 163:e59c8e839560 | 863 | /*! @name TSCV - Timestamp Counter Value */ |
| AnnaBridge | 163:e59c8e839560 | 864 | #define CAN_TSCV_TSC_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 865 | #define CAN_TSCV_TSC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 866 | #define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 867 | |
| AnnaBridge | 163:e59c8e839560 | 868 | /*! @name TOCC - Timeout Counter Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 869 | #define CAN_TOCC_ETOC_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 870 | #define CAN_TOCC_ETOC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 871 | #define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 872 | #define CAN_TOCC_TOS_MASK (0x6U) |
| AnnaBridge | 163:e59c8e839560 | 873 | #define CAN_TOCC_TOS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 874 | #define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 875 | #define CAN_TOCC_TOP_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 876 | #define CAN_TOCC_TOP_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 877 | #define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 878 | |
| AnnaBridge | 163:e59c8e839560 | 879 | /*! @name TOCV - Timeout Counter Value */ |
| AnnaBridge | 163:e59c8e839560 | 880 | #define CAN_TOCV_TOC_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 881 | #define CAN_TOCV_TOC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 882 | #define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 883 | |
| AnnaBridge | 163:e59c8e839560 | 884 | /*! @name ECR - Error Counter Register */ |
| AnnaBridge | 163:e59c8e839560 | 885 | #define CAN_ECR_TEC_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 886 | #define CAN_ECR_TEC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 887 | #define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 888 | #define CAN_ECR_REC_MASK (0x7F00U) |
| AnnaBridge | 163:e59c8e839560 | 889 | #define CAN_ECR_REC_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 890 | #define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 891 | #define CAN_ECR_RP_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 892 | #define CAN_ECR_RP_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 893 | #define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 894 | #define CAN_ECR_CEL_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 895 | #define CAN_ECR_CEL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 896 | #define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 897 | |
| AnnaBridge | 163:e59c8e839560 | 898 | /*! @name PSR - Protocol Status Register */ |
| AnnaBridge | 163:e59c8e839560 | 899 | #define CAN_PSR_LEC_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 900 | #define CAN_PSR_LEC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 901 | #define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 902 | #define CAN_PSR_ACT_MASK (0x18U) |
| AnnaBridge | 163:e59c8e839560 | 903 | #define CAN_PSR_ACT_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 904 | #define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 905 | #define CAN_PSR_EP_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 906 | #define CAN_PSR_EP_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 907 | #define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 908 | #define CAN_PSR_EW_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 909 | #define CAN_PSR_EW_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 910 | #define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 911 | #define CAN_PSR_BO_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 912 | #define CAN_PSR_BO_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 913 | #define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 914 | #define CAN_PSR_DLEC_MASK (0x700U) |
| AnnaBridge | 163:e59c8e839560 | 915 | #define CAN_PSR_DLEC_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 916 | #define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 917 | #define CAN_PSR_RESI_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 918 | #define CAN_PSR_RESI_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 919 | #define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 920 | #define CAN_PSR_RBRS_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 921 | #define CAN_PSR_RBRS_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 922 | #define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 923 | #define CAN_PSR_RFDF_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 924 | #define CAN_PSR_RFDF_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 925 | #define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 926 | #define CAN_PSR_PXE_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 927 | #define CAN_PSR_PXE_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 928 | #define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 929 | #define CAN_PSR_TDCV_MASK (0x7F0000U) |
| AnnaBridge | 163:e59c8e839560 | 930 | #define CAN_PSR_TDCV_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 931 | #define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 932 | |
| AnnaBridge | 163:e59c8e839560 | 933 | /*! @name TDCR - Transmitter Delay Compensator Register */ |
| AnnaBridge | 163:e59c8e839560 | 934 | #define CAN_TDCR_TDCF_MASK (0x7FU) |
| AnnaBridge | 163:e59c8e839560 | 935 | #define CAN_TDCR_TDCF_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 936 | #define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 937 | #define CAN_TDCR_TDCO_MASK (0x7F00U) |
| AnnaBridge | 163:e59c8e839560 | 938 | #define CAN_TDCR_TDCO_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 939 | #define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 940 | |
| AnnaBridge | 163:e59c8e839560 | 941 | /*! @name IR - Interrupt Register */ |
| AnnaBridge | 163:e59c8e839560 | 942 | #define CAN_IR_RF0N_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 943 | #define CAN_IR_RF0N_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 944 | #define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 945 | #define CAN_IR_RF0W_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 946 | #define CAN_IR_RF0W_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 947 | #define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK) |
| AnnaBridge | 163:e59c8e839560 | 948 | #define CAN_IR_RF0F_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 949 | #define CAN_IR_RF0F_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 950 | #define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK) |
| AnnaBridge | 163:e59c8e839560 | 951 | #define CAN_IR_RF0L_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 952 | #define CAN_IR_RF0L_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 953 | #define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 954 | #define CAN_IR_RF1N_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 955 | #define CAN_IR_RF1N_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 956 | #define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 957 | #define CAN_IR_RF1W_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 958 | #define CAN_IR_RF1W_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 959 | #define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK) |
| AnnaBridge | 163:e59c8e839560 | 960 | #define CAN_IR_RF1F_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 961 | #define CAN_IR_RF1F_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 962 | #define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK) |
| AnnaBridge | 163:e59c8e839560 | 963 | #define CAN_IR_RF1L_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 964 | #define CAN_IR_RF1L_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 965 | #define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 966 | #define CAN_IR_HPM_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 967 | #define CAN_IR_HPM_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 968 | #define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 969 | #define CAN_IR_TC_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 970 | #define CAN_IR_TC_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 971 | #define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 972 | #define CAN_IR_TCF_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 973 | #define CAN_IR_TCF_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 974 | #define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 975 | #define CAN_IR_TFE_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 976 | #define CAN_IR_TFE_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 977 | #define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 978 | #define CAN_IR_TEFN_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 979 | #define CAN_IR_TEFN_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 980 | #define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 981 | #define CAN_IR_TEFW_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 982 | #define CAN_IR_TEFW_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 983 | #define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 984 | #define CAN_IR_TEFF_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 985 | #define CAN_IR_TEFF_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 986 | #define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 987 | #define CAN_IR_TEFL_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 988 | #define CAN_IR_TEFL_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 989 | #define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 990 | #define CAN_IR_TSW_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 991 | #define CAN_IR_TSW_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 992 | #define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 993 | #define CAN_IR_MRAF_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 994 | #define CAN_IR_MRAF_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 995 | #define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 996 | #define CAN_IR_TOO_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 997 | #define CAN_IR_TOO_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 998 | #define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 999 | #define CAN_IR_DRX_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 1000 | #define CAN_IR_DRX_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 1001 | #define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1002 | #define CAN_IR_BEC_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 1003 | #define CAN_IR_BEC_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 1004 | #define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1005 | #define CAN_IR_BEU_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 1006 | #define CAN_IR_BEU_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 1007 | #define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1008 | #define CAN_IR_ELO_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 1009 | #define CAN_IR_ELO_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 1010 | #define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1011 | #define CAN_IR_EP_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 1012 | #define CAN_IR_EP_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 1013 | #define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1014 | #define CAN_IR_EW_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 1015 | #define CAN_IR_EW_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 1016 | #define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1017 | #define CAN_IR_BO_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 1018 | #define CAN_IR_BO_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 1019 | #define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1020 | #define CAN_IR_WDI_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 1021 | #define CAN_IR_WDI_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 1022 | #define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1023 | #define CAN_IR_PEA_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 1024 | #define CAN_IR_PEA_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 1025 | #define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1026 | #define CAN_IR_PED_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 1027 | #define CAN_IR_PED_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 1028 | #define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1029 | #define CAN_IR_ARA_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 1030 | #define CAN_IR_ARA_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 1031 | #define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1032 | |
| AnnaBridge | 163:e59c8e839560 | 1033 | /*! @name IE - Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 1034 | #define CAN_IE_RF0NE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 1035 | #define CAN_IE_RF0NE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1036 | #define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1037 | #define CAN_IE_RF0WE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 1038 | #define CAN_IE_RF0WE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1039 | #define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1040 | #define CAN_IE_RF0FE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 1041 | #define CAN_IE_RF0FE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1042 | #define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1043 | #define CAN_IE_RF0LE_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 1044 | #define CAN_IE_RF0LE_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 1045 | #define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1046 | #define CAN_IE_RF1NE_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 1047 | #define CAN_IE_RF1NE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1048 | #define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1049 | #define CAN_IE_RF1WE_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 1050 | #define CAN_IE_RF1WE_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 1051 | #define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1052 | #define CAN_IE_RF1FE_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 1053 | #define CAN_IE_RF1FE_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 1054 | #define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1055 | #define CAN_IE_RF1LE_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 1056 | #define CAN_IE_RF1LE_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 1057 | #define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1058 | #define CAN_IE_HPME_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 1059 | #define CAN_IE_HPME_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 1060 | #define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1061 | #define CAN_IE_TCE_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 1062 | #define CAN_IE_TCE_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 1063 | #define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1064 | #define CAN_IE_TCFE_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 1065 | #define CAN_IE_TCFE_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 1066 | #define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1067 | #define CAN_IE_TFEE_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 1068 | #define CAN_IE_TFEE_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 1069 | #define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1070 | #define CAN_IE_TEFNE_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 1071 | #define CAN_IE_TEFNE_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 1072 | #define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1073 | #define CAN_IE_TEFWE_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 1074 | #define CAN_IE_TEFWE_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 1075 | #define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1076 | #define CAN_IE_TEFFE_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 1077 | #define CAN_IE_TEFFE_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 1078 | #define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1079 | #define CAN_IE_TEFLE_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 1080 | #define CAN_IE_TEFLE_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 1081 | #define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1082 | #define CAN_IE_TSWE_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 1083 | #define CAN_IE_TSWE_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 1084 | #define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1085 | #define CAN_IE_MRAFE_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 1086 | #define CAN_IE_MRAFE_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 1087 | #define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1088 | #define CAN_IE_TOOE_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 1089 | #define CAN_IE_TOOE_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 1090 | #define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1091 | #define CAN_IE_DRXE_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 1092 | #define CAN_IE_DRXE_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 1093 | #define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1094 | #define CAN_IE_BECE_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 1095 | #define CAN_IE_BECE_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 1096 | #define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1097 | #define CAN_IE_BEUE_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 1098 | #define CAN_IE_BEUE_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 1099 | #define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1100 | #define CAN_IE_ELOE_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 1101 | #define CAN_IE_ELOE_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 1102 | #define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1103 | #define CAN_IE_EPE_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 1104 | #define CAN_IE_EPE_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 1105 | #define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1106 | #define CAN_IE_EWE_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 1107 | #define CAN_IE_EWE_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 1108 | #define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1109 | #define CAN_IE_BOE_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 1110 | #define CAN_IE_BOE_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 1111 | #define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1112 | #define CAN_IE_WDIE_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 1113 | #define CAN_IE_WDIE_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 1114 | #define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1115 | #define CAN_IE_PEAE_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 1116 | #define CAN_IE_PEAE_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 1117 | #define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1118 | #define CAN_IE_PEDE_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 1119 | #define CAN_IE_PEDE_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 1120 | #define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1121 | #define CAN_IE_ARAE_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 1122 | #define CAN_IE_ARAE_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 1123 | #define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1124 | |
| AnnaBridge | 163:e59c8e839560 | 1125 | /*! @name ILS - Interrupt Line Select */ |
| AnnaBridge | 163:e59c8e839560 | 1126 | #define CAN_ILS_RF0NL_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 1127 | #define CAN_ILS_RF0NL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1128 | #define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1129 | #define CAN_ILS_RF0WL_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 1130 | #define CAN_ILS_RF0WL_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1131 | #define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1132 | #define CAN_ILS_RF0FL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 1133 | #define CAN_ILS_RF0FL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1134 | #define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1135 | #define CAN_ILS_RF0LL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 1136 | #define CAN_ILS_RF0LL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 1137 | #define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1138 | #define CAN_ILS_RF1NL_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 1139 | #define CAN_ILS_RF1NL_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1140 | #define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1141 | #define CAN_ILS_RF1WL_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 1142 | #define CAN_ILS_RF1WL_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 1143 | #define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1144 | #define CAN_ILS_RF1FL_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 1145 | #define CAN_ILS_RF1FL_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 1146 | #define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1147 | #define CAN_ILS_RF1LL_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 1148 | #define CAN_ILS_RF1LL_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 1149 | #define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1150 | #define CAN_ILS_HPML_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 1151 | #define CAN_ILS_HPML_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 1152 | #define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1153 | #define CAN_ILS_TCL_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 1154 | #define CAN_ILS_TCL_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 1155 | #define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1156 | #define CAN_ILS_TCFL_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 1157 | #define CAN_ILS_TCFL_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 1158 | #define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1159 | #define CAN_ILS_TFEL_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 1160 | #define CAN_ILS_TFEL_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 1161 | #define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1162 | #define CAN_ILS_TEFNL_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 1163 | #define CAN_ILS_TEFNL_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 1164 | #define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1165 | #define CAN_ILS_TEFWL_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 1166 | #define CAN_ILS_TEFWL_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 1167 | #define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1168 | #define CAN_ILS_TEFFL_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 1169 | #define CAN_ILS_TEFFL_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 1170 | #define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1171 | #define CAN_ILS_TEFLL_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 1172 | #define CAN_ILS_TEFLL_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 1173 | #define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1174 | #define CAN_ILS_TSWL_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 1175 | #define CAN_ILS_TSWL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 1176 | #define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1177 | #define CAN_ILS_MRAFL_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 1178 | #define CAN_ILS_MRAFL_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 1179 | #define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1180 | #define CAN_ILS_TOOL_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 1181 | #define CAN_ILS_TOOL_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 1182 | #define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1183 | #define CAN_ILS_DRXL_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 1184 | #define CAN_ILS_DRXL_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 1185 | #define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1186 | #define CAN_ILS_BECL_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 1187 | #define CAN_ILS_BECL_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 1188 | #define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1189 | #define CAN_ILS_BEUL_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 1190 | #define CAN_ILS_BEUL_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 1191 | #define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1192 | #define CAN_ILS_ELOL_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 1193 | #define CAN_ILS_ELOL_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 1194 | #define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1195 | #define CAN_ILS_EPL_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 1196 | #define CAN_ILS_EPL_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 1197 | #define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1198 | #define CAN_ILS_EWL_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 1199 | #define CAN_ILS_EWL_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 1200 | #define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1201 | #define CAN_ILS_BOL_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 1202 | #define CAN_ILS_BOL_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 1203 | #define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1204 | #define CAN_ILS_WDIL_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 1205 | #define CAN_ILS_WDIL_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 1206 | #define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1207 | #define CAN_ILS_PEAL_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 1208 | #define CAN_ILS_PEAL_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 1209 | #define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1210 | #define CAN_ILS_PEDL_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 1211 | #define CAN_ILS_PEDL_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 1212 | #define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1213 | #define CAN_ILS_ARAL_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 1214 | #define CAN_ILS_ARAL_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 1215 | #define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1216 | |
| AnnaBridge | 163:e59c8e839560 | 1217 | /*! @name ILE - Interrupt Line Enable */ |
| AnnaBridge | 163:e59c8e839560 | 1218 | #define CAN_ILE_EINT0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 1219 | #define CAN_ILE_EINT0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1220 | #define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1221 | #define CAN_ILE_EINT1_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 1222 | #define CAN_ILE_EINT1_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1223 | #define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1224 | |
| AnnaBridge | 163:e59c8e839560 | 1225 | /*! @name GFC - Global Filter Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1226 | #define CAN_GFC_RRFE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 1227 | #define CAN_GFC_RRFE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1228 | #define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1229 | #define CAN_GFC_RRFS_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 1230 | #define CAN_GFC_RRFS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1231 | #define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1232 | #define CAN_GFC_ANFE_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 1233 | #define CAN_GFC_ANFE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1234 | #define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1235 | #define CAN_GFC_ANFS_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 1236 | #define CAN_GFC_ANFS_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1237 | #define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1238 | |
| AnnaBridge | 163:e59c8e839560 | 1239 | /*! @name SIDFC - Standard ID Filter Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1240 | #define CAN_SIDFC_FLSSA_MASK (0xFFFCU) |
| AnnaBridge | 163:e59c8e839560 | 1241 | #define CAN_SIDFC_FLSSA_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1242 | #define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1243 | #define CAN_SIDFC_LSS_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 1244 | #define CAN_SIDFC_LSS_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 1245 | #define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1246 | |
| AnnaBridge | 163:e59c8e839560 | 1247 | /*! @name XIDFC - Extended ID Filter Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1248 | #define CAN_XIDFC_FLESA_MASK (0xFFFCU) |
| AnnaBridge | 163:e59c8e839560 | 1249 | #define CAN_XIDFC_FLESA_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1250 | #define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1251 | #define CAN_XIDFC_LSE_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 1252 | #define CAN_XIDFC_LSE_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 1253 | #define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1254 | |
| AnnaBridge | 163:e59c8e839560 | 1255 | /*! @name XIDAM - Extended ID AND Mask */ |
| AnnaBridge | 163:e59c8e839560 | 1256 | #define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1257 | #define CAN_XIDAM_EIDM_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1258 | #define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1259 | |
| AnnaBridge | 163:e59c8e839560 | 1260 | /*! @name HPMS - High Priority Message Status */ |
| AnnaBridge | 163:e59c8e839560 | 1261 | #define CAN_HPMS_BIDX_MASK (0x3FU) |
| AnnaBridge | 163:e59c8e839560 | 1262 | #define CAN_HPMS_BIDX_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1263 | #define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1264 | #define CAN_HPMS_MSI_MASK (0xC0U) |
| AnnaBridge | 163:e59c8e839560 | 1265 | #define CAN_HPMS_MSI_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 1266 | #define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1267 | #define CAN_HPMS_FIDX_MASK (0x7F00U) |
| AnnaBridge | 163:e59c8e839560 | 1268 | #define CAN_HPMS_FIDX_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 1269 | #define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1270 | #define CAN_HPMS_FLST_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 1271 | #define CAN_HPMS_FLST_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 1272 | #define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1273 | |
| AnnaBridge | 163:e59c8e839560 | 1274 | /*! @name NDAT1 - New Data 1 */ |
| AnnaBridge | 163:e59c8e839560 | 1275 | #define CAN_NDAT1_ND_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1276 | #define CAN_NDAT1_ND_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1277 | #define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1278 | |
| AnnaBridge | 163:e59c8e839560 | 1279 | /*! @name NDAT2 - New Data 2 */ |
| AnnaBridge | 163:e59c8e839560 | 1280 | #define CAN_NDAT2_ND_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1281 | #define CAN_NDAT2_ND_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1282 | #define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1283 | |
| AnnaBridge | 163:e59c8e839560 | 1284 | /*! @name RXF0C - Rx FIFO 0 Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1285 | #define CAN_RXF0C_F0SA_MASK (0xFFFCU) |
| AnnaBridge | 163:e59c8e839560 | 1286 | #define CAN_RXF0C_F0SA_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1287 | #define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1288 | #define CAN_RXF0C_F0S_MASK (0x7F0000U) |
| AnnaBridge | 163:e59c8e839560 | 1289 | #define CAN_RXF0C_F0S_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 1290 | #define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1291 | #define CAN_RXF0C_F0WM_MASK (0x7F000000U) |
| AnnaBridge | 163:e59c8e839560 | 1292 | #define CAN_RXF0C_F0WM_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 1293 | #define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1294 | #define CAN_RXF0C_F0OM_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 1295 | #define CAN_RXF0C_F0OM_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 1296 | #define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1297 | |
| AnnaBridge | 163:e59c8e839560 | 1298 | /*! @name RXF0S - Rx FIFO 0 Status */ |
| AnnaBridge | 163:e59c8e839560 | 1299 | #define CAN_RXF0S_F0FL_MASK (0x7FU) |
| AnnaBridge | 163:e59c8e839560 | 1300 | #define CAN_RXF0S_F0FL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1301 | #define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1302 | #define CAN_RXF0S_F0GI_MASK (0x3F00U) |
| AnnaBridge | 163:e59c8e839560 | 1303 | #define CAN_RXF0S_F0GI_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 1304 | #define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1305 | #define CAN_RXF0S_F0PI_MASK (0x3F0000U) |
| AnnaBridge | 163:e59c8e839560 | 1306 | #define CAN_RXF0S_F0PI_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 1307 | #define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1308 | #define CAN_RXF0S_F0F_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 1309 | #define CAN_RXF0S_F0F_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 1310 | #define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1311 | #define CAN_RXF0S_RF0L_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 1312 | #define CAN_RXF0S_RF0L_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 1313 | #define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1314 | |
| AnnaBridge | 163:e59c8e839560 | 1315 | /*! @name RXF0A - Rx FIFO 0 Acknowledge */ |
| AnnaBridge | 163:e59c8e839560 | 1316 | #define CAN_RXF0A_F0AI_MASK (0x3FU) |
| AnnaBridge | 163:e59c8e839560 | 1317 | #define CAN_RXF0A_F0AI_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1318 | #define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1319 | |
| AnnaBridge | 163:e59c8e839560 | 1320 | /*! @name RXBC - Rx Buffer Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1321 | #define CAN_RXBC_RBSA_MASK (0xFFFCU) |
| AnnaBridge | 163:e59c8e839560 | 1322 | #define CAN_RXBC_RBSA_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1323 | #define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1324 | |
| AnnaBridge | 163:e59c8e839560 | 1325 | /*! @name RXF1C - Rx FIFO 1 Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1326 | #define CAN_RXF1C_F1SA_MASK (0xFFFCU) |
| AnnaBridge | 163:e59c8e839560 | 1327 | #define CAN_RXF1C_F1SA_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1328 | #define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1329 | #define CAN_RXF1C_F1S_MASK (0x7F0000U) |
| AnnaBridge | 163:e59c8e839560 | 1330 | #define CAN_RXF1C_F1S_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 1331 | #define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1332 | #define CAN_RXF1C_F1WM_MASK (0x7F000000U) |
| AnnaBridge | 163:e59c8e839560 | 1333 | #define CAN_RXF1C_F1WM_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 1334 | #define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1335 | #define CAN_RXF1C_F1OM_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 1336 | #define CAN_RXF1C_F1OM_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 1337 | #define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1338 | |
| AnnaBridge | 163:e59c8e839560 | 1339 | /*! @name RXF1S - Rx FIFO 1 Status */ |
| AnnaBridge | 163:e59c8e839560 | 1340 | #define CAN_RXF1S_F1FL_MASK (0x7FU) |
| AnnaBridge | 163:e59c8e839560 | 1341 | #define CAN_RXF1S_F1FL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1342 | #define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1343 | #define CAN_RXF1S_F1GI_MASK (0x3F00U) |
| AnnaBridge | 163:e59c8e839560 | 1344 | #define CAN_RXF1S_F1GI_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 1345 | #define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1346 | #define CAN_RXF1S_F1PI_MASK (0x3F0000U) |
| AnnaBridge | 163:e59c8e839560 | 1347 | #define CAN_RXF1S_F1PI_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 1348 | #define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1349 | #define CAN_RXF1S_F1F_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 1350 | #define CAN_RXF1S_F1F_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 1351 | #define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1352 | #define CAN_RXF1S_RF1L_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 1353 | #define CAN_RXF1S_RF1L_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 1354 | #define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1355 | |
| AnnaBridge | 163:e59c8e839560 | 1356 | /*! @name RXF1A - Rx FIFO 1 Acknowledge */ |
| AnnaBridge | 163:e59c8e839560 | 1357 | #define CAN_RXF1A_F1AI_MASK (0x3FU) |
| AnnaBridge | 163:e59c8e839560 | 1358 | #define CAN_RXF1A_F1AI_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1359 | #define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1360 | |
| AnnaBridge | 163:e59c8e839560 | 1361 | /*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1362 | #define CAN_RXESC_F0DS_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 1363 | #define CAN_RXESC_F0DS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1364 | #define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1365 | #define CAN_RXESC_F1DS_MASK (0x70U) |
| AnnaBridge | 163:e59c8e839560 | 1366 | #define CAN_RXESC_F1DS_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1367 | #define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1368 | #define CAN_RXESC_RBDS_MASK (0x700U) |
| AnnaBridge | 163:e59c8e839560 | 1369 | #define CAN_RXESC_RBDS_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 1370 | #define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1371 | |
| AnnaBridge | 163:e59c8e839560 | 1372 | /*! @name TXBC - Tx Buffer Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1373 | #define CAN_TXBC_TBSA_MASK (0xFFFCU) |
| AnnaBridge | 163:e59c8e839560 | 1374 | #define CAN_TXBC_TBSA_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1375 | #define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1376 | #define CAN_TXBC_NDTB_MASK (0x3F0000U) |
| AnnaBridge | 163:e59c8e839560 | 1377 | #define CAN_TXBC_NDTB_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 1378 | #define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1379 | #define CAN_TXBC_TFQS_MASK (0x3F000000U) |
| AnnaBridge | 163:e59c8e839560 | 1380 | #define CAN_TXBC_TFQS_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 1381 | #define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1382 | #define CAN_TXBC_TFQM_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 1383 | #define CAN_TXBC_TFQM_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 1384 | #define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1385 | |
| AnnaBridge | 163:e59c8e839560 | 1386 | /*! @name TXFQS - Tx FIFO/Queue Status */ |
| AnnaBridge | 163:e59c8e839560 | 1387 | #define CAN_TXFQS_TFGI_MASK (0x1F00U) |
| AnnaBridge | 163:e59c8e839560 | 1388 | #define CAN_TXFQS_TFGI_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 1389 | #define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1390 | #define CAN_TXFQS_TFQPI_MASK (0x1F0000U) |
| AnnaBridge | 163:e59c8e839560 | 1391 | #define CAN_TXFQS_TFQPI_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 1392 | #define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1393 | #define CAN_TXFQS_TFQF_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 1394 | #define CAN_TXFQS_TFQF_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 1395 | #define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1396 | |
| AnnaBridge | 163:e59c8e839560 | 1397 | /*! @name TXESC - Tx Buffer Element Size Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1398 | #define CAN_TXESC_TBDS_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 1399 | #define CAN_TXESC_TBDS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1400 | #define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1401 | |
| AnnaBridge | 163:e59c8e839560 | 1402 | /*! @name TXBRP - Tx Buffer Request Pending */ |
| AnnaBridge | 163:e59c8e839560 | 1403 | #define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1404 | #define CAN_TXBRP_TRP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1405 | #define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1406 | |
| AnnaBridge | 163:e59c8e839560 | 1407 | /*! @name TXBAR - Tx Buffer Add Request */ |
| AnnaBridge | 163:e59c8e839560 | 1408 | #define CAN_TXBAR_AR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1409 | #define CAN_TXBAR_AR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1410 | #define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1411 | |
| AnnaBridge | 163:e59c8e839560 | 1412 | /*! @name TXBCR - Tx Buffer Cancellation Request */ |
| AnnaBridge | 163:e59c8e839560 | 1413 | #define CAN_TXBCR_CR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1414 | #define CAN_TXBCR_CR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1415 | #define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1416 | |
| AnnaBridge | 163:e59c8e839560 | 1417 | /*! @name TXBTO - Tx Buffer Transmission Occurred */ |
| AnnaBridge | 163:e59c8e839560 | 1418 | #define CAN_TXBTO_TO_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1419 | #define CAN_TXBTO_TO_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1420 | #define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1421 | |
| AnnaBridge | 163:e59c8e839560 | 1422 | /*! @name TXBCF - Tx Buffer Cancellation Finished */ |
| AnnaBridge | 163:e59c8e839560 | 1423 | #define CAN_TXBCF_TO_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1424 | #define CAN_TXBCF_TO_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1425 | #define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1426 | |
| AnnaBridge | 163:e59c8e839560 | 1427 | /*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 1428 | #define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1429 | #define CAN_TXBTIE_TIE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1430 | #define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1431 | |
| AnnaBridge | 163:e59c8e839560 | 1432 | /*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 1433 | #define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1434 | #define CAN_TXBCIE_CFIE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1435 | #define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1436 | |
| AnnaBridge | 163:e59c8e839560 | 1437 | /*! @name TXEFC - Tx Event FIFO Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1438 | #define CAN_TXEFC_EFSA_MASK (0xFFFCU) |
| AnnaBridge | 163:e59c8e839560 | 1439 | #define CAN_TXEFC_EFSA_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1440 | #define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1441 | #define CAN_TXEFC_EFS_MASK (0x3F0000U) |
| AnnaBridge | 163:e59c8e839560 | 1442 | #define CAN_TXEFC_EFS_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 1443 | #define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1444 | #define CAN_TXEFC_EFWM_MASK (0x3F000000U) |
| AnnaBridge | 163:e59c8e839560 | 1445 | #define CAN_TXEFC_EFWM_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 1446 | #define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1447 | |
| AnnaBridge | 163:e59c8e839560 | 1448 | /*! @name TXEFS - Tx Event FIFO Status */ |
| AnnaBridge | 163:e59c8e839560 | 1449 | #define CAN_TXEFS_EFFL_MASK (0x3FU) |
| AnnaBridge | 163:e59c8e839560 | 1450 | #define CAN_TXEFS_EFFL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1451 | #define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1452 | #define CAN_TXEFS_EFGI_MASK (0x1F00U) |
| AnnaBridge | 163:e59c8e839560 | 1453 | #define CAN_TXEFS_EFGI_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 1454 | #define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1455 | #define CAN_TXEFS_EFPI_MASK (0x3F0000U) |
| AnnaBridge | 163:e59c8e839560 | 1456 | #define CAN_TXEFS_EFPI_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 1457 | #define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1458 | #define CAN_TXEFS_EFF_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 1459 | #define CAN_TXEFS_EFF_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 1460 | #define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1461 | #define CAN_TXEFS_TEFL_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 1462 | #define CAN_TXEFS_TEFL_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 1463 | #define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1464 | |
| AnnaBridge | 163:e59c8e839560 | 1465 | /*! @name TXEFA - Tx Event FIFO Acknowledge */ |
| AnnaBridge | 163:e59c8e839560 | 1466 | #define CAN_TXEFA_EFAI_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 1467 | #define CAN_TXEFA_EFAI_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1468 | #define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1469 | |
| AnnaBridge | 163:e59c8e839560 | 1470 | /*! @name MRBA - CAN Message RAM Base Address */ |
| AnnaBridge | 163:e59c8e839560 | 1471 | #define CAN_MRBA_BA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1472 | #define CAN_MRBA_BA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1473 | #define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1474 | |
| AnnaBridge | 163:e59c8e839560 | 1475 | /*! @name ETSCC - External Timestamp Counter Configuration */ |
| AnnaBridge | 163:e59c8e839560 | 1476 | #define CAN_ETSCC_ETCP_MASK (0x7FFU) |
| AnnaBridge | 163:e59c8e839560 | 1477 | #define CAN_ETSCC_ETCP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1478 | #define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1479 | #define CAN_ETSCC_ETCE_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 1480 | #define CAN_ETSCC_ETCE_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 1481 | #define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1482 | |
| AnnaBridge | 163:e59c8e839560 | 1483 | /*! @name ETSCV - External Timestamp Counter Value */ |
| AnnaBridge | 163:e59c8e839560 | 1484 | #define CAN_ETSCV_ETSC_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1485 | #define CAN_ETSCV_ETSC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1486 | #define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1487 | |
| AnnaBridge | 163:e59c8e839560 | 1488 | |
| AnnaBridge | 163:e59c8e839560 | 1489 | /*! |
| AnnaBridge | 163:e59c8e839560 | 1490 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1491 | */ /* end of group CAN_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 1492 | |
| AnnaBridge | 163:e59c8e839560 | 1493 | |
| AnnaBridge | 163:e59c8e839560 | 1494 | /* CAN - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 1495 | /** Peripheral CAN0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 1496 | #define CAN0_BASE (0x4009D000u) |
| AnnaBridge | 163:e59c8e839560 | 1497 | /** Peripheral CAN0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 1498 | #define CAN0 ((CAN_Type *)CAN0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 1499 | /** Peripheral CAN1 base address */ |
| AnnaBridge | 163:e59c8e839560 | 1500 | #define CAN1_BASE (0x4009E000u) |
| AnnaBridge | 163:e59c8e839560 | 1501 | /** Peripheral CAN1 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 1502 | #define CAN1 ((CAN_Type *)CAN1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 1503 | /** Array initializer of CAN peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 1504 | #define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE } |
| AnnaBridge | 163:e59c8e839560 | 1505 | /** Array initializer of CAN peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 1506 | #define CAN_BASE_PTRS { CAN0, CAN1 } |
| AnnaBridge | 163:e59c8e839560 | 1507 | /** Interrupt vectors for the CAN peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 1508 | #define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } } |
| AnnaBridge | 163:e59c8e839560 | 1509 | |
| AnnaBridge | 163:e59c8e839560 | 1510 | /*! |
| AnnaBridge | 163:e59c8e839560 | 1511 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1512 | */ /* end of group CAN_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 1513 | |
| AnnaBridge | 163:e59c8e839560 | 1514 | |
| AnnaBridge | 163:e59c8e839560 | 1515 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 1516 | -- CRC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 1517 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 1518 | |
| AnnaBridge | 163:e59c8e839560 | 1519 | /*! |
| AnnaBridge | 163:e59c8e839560 | 1520 | * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 1521 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 1522 | */ |
| AnnaBridge | 163:e59c8e839560 | 1523 | |
| AnnaBridge | 163:e59c8e839560 | 1524 | /** CRC - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 1525 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 1526 | __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 1527 | __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 1528 | union { /* offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 1529 | __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 1530 | __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 1531 | }; |
| AnnaBridge | 163:e59c8e839560 | 1532 | } CRC_Type; |
| AnnaBridge | 163:e59c8e839560 | 1533 | |
| AnnaBridge | 163:e59c8e839560 | 1534 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 1535 | -- CRC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 1536 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 1537 | |
| AnnaBridge | 163:e59c8e839560 | 1538 | /*! |
| AnnaBridge | 163:e59c8e839560 | 1539 | * @addtogroup CRC_Register_Masks CRC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 1540 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 1541 | */ |
| AnnaBridge | 163:e59c8e839560 | 1542 | |
| AnnaBridge | 163:e59c8e839560 | 1543 | /*! @name MODE - CRC mode register */ |
| AnnaBridge | 163:e59c8e839560 | 1544 | #define CRC_MODE_CRC_POLY_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 1545 | #define CRC_MODE_CRC_POLY_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1546 | #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1547 | #define CRC_MODE_BIT_RVS_WR_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 1548 | #define CRC_MODE_BIT_RVS_WR_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1549 | #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1550 | #define CRC_MODE_CMPL_WR_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 1551 | #define CRC_MODE_CMPL_WR_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 1552 | #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1553 | #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 1554 | #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1555 | #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1556 | #define CRC_MODE_CMPL_SUM_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 1557 | #define CRC_MODE_CMPL_SUM_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 1558 | #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1559 | |
| AnnaBridge | 163:e59c8e839560 | 1560 | /*! @name SEED - CRC seed register */ |
| AnnaBridge | 163:e59c8e839560 | 1561 | #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1562 | #define CRC_SEED_CRC_SEED_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1563 | #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1564 | |
| AnnaBridge | 163:e59c8e839560 | 1565 | /*! @name SUM - CRC checksum register */ |
| AnnaBridge | 163:e59c8e839560 | 1566 | #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1567 | #define CRC_SUM_CRC_SUM_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1568 | #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1569 | |
| AnnaBridge | 163:e59c8e839560 | 1570 | /*! @name WR_DATA - CRC data register */ |
| AnnaBridge | 163:e59c8e839560 | 1571 | #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1572 | #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1573 | #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1574 | |
| AnnaBridge | 163:e59c8e839560 | 1575 | |
| AnnaBridge | 163:e59c8e839560 | 1576 | /*! |
| AnnaBridge | 163:e59c8e839560 | 1577 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1578 | */ /* end of group CRC_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 1579 | |
| AnnaBridge | 163:e59c8e839560 | 1580 | |
| AnnaBridge | 163:e59c8e839560 | 1581 | /* CRC - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 1582 | /** Peripheral CRC_ENGINE base address */ |
| AnnaBridge | 163:e59c8e839560 | 1583 | #define CRC_ENGINE_BASE (0x40095000u) |
| AnnaBridge | 163:e59c8e839560 | 1584 | /** Peripheral CRC_ENGINE base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 1585 | #define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE) |
| AnnaBridge | 163:e59c8e839560 | 1586 | /** Array initializer of CRC peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 1587 | #define CRC_BASE_ADDRS { CRC_ENGINE_BASE } |
| AnnaBridge | 163:e59c8e839560 | 1588 | /** Array initializer of CRC peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 1589 | #define CRC_BASE_PTRS { CRC_ENGINE } |
| AnnaBridge | 163:e59c8e839560 | 1590 | |
| AnnaBridge | 163:e59c8e839560 | 1591 | /*! |
| AnnaBridge | 163:e59c8e839560 | 1592 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1593 | */ /* end of group CRC_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 1594 | |
| AnnaBridge | 163:e59c8e839560 | 1595 | |
| AnnaBridge | 163:e59c8e839560 | 1596 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 1597 | -- CTIMER Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 1598 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 1599 | |
| AnnaBridge | 163:e59c8e839560 | 1600 | /*! |
| AnnaBridge | 163:e59c8e839560 | 1601 | * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 1602 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 1603 | */ |
| AnnaBridge | 163:e59c8e839560 | 1604 | |
| AnnaBridge | 163:e59c8e839560 | 1605 | /** CTIMER - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 1606 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 1607 | __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 1608 | __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 1609 | __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 1610 | __IO uint32_t PR; /**< Prescale Register, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 1611 | __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 1612 | __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 1613 | __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 1614 | __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 1615 | __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 1616 | __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ |
| AnnaBridge | 163:e59c8e839560 | 1617 | uint8_t RESERVED_0[48]; |
| AnnaBridge | 163:e59c8e839560 | 1618 | __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ |
| AnnaBridge | 163:e59c8e839560 | 1619 | __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ |
| AnnaBridge | 163:e59c8e839560 | 1620 | __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 1621 | } CTIMER_Type; |
| AnnaBridge | 163:e59c8e839560 | 1622 | |
| AnnaBridge | 163:e59c8e839560 | 1623 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 1624 | -- CTIMER Register Masks |
| AnnaBridge | 163:e59c8e839560 | 1625 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 1626 | |
| AnnaBridge | 163:e59c8e839560 | 1627 | /*! |
| AnnaBridge | 163:e59c8e839560 | 1628 | * @addtogroup CTIMER_Register_Masks CTIMER Register Masks |
| AnnaBridge | 163:e59c8e839560 | 1629 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 1630 | */ |
| AnnaBridge | 163:e59c8e839560 | 1631 | |
| AnnaBridge | 163:e59c8e839560 | 1632 | /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ |
| AnnaBridge | 163:e59c8e839560 | 1633 | #define CTIMER_IR_MR0INT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 1634 | #define CTIMER_IR_MR0INT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1635 | #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1636 | #define CTIMER_IR_MR1INT_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 1637 | #define CTIMER_IR_MR1INT_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1638 | #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1639 | #define CTIMER_IR_MR2INT_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 1640 | #define CTIMER_IR_MR2INT_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1641 | #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1642 | #define CTIMER_IR_MR3INT_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 1643 | #define CTIMER_IR_MR3INT_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 1644 | #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1645 | #define CTIMER_IR_CR0INT_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 1646 | #define CTIMER_IR_CR0INT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1647 | #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1648 | #define CTIMER_IR_CR1INT_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 1649 | #define CTIMER_IR_CR1INT_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 1650 | #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1651 | #define CTIMER_IR_CR2INT_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 1652 | #define CTIMER_IR_CR2INT_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 1653 | #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1654 | #define CTIMER_IR_CR3INT_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 1655 | #define CTIMER_IR_CR3INT_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 1656 | #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1657 | |
| AnnaBridge | 163:e59c8e839560 | 1658 | /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ |
| AnnaBridge | 163:e59c8e839560 | 1659 | #define CTIMER_TCR_CEN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 1660 | #define CTIMER_TCR_CEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1661 | #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1662 | #define CTIMER_TCR_CRST_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 1663 | #define CTIMER_TCR_CRST_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1664 | #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1665 | |
| AnnaBridge | 163:e59c8e839560 | 1666 | /*! @name TC - Timer Counter */ |
| AnnaBridge | 163:e59c8e839560 | 1667 | #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1668 | #define CTIMER_TC_TCVAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1669 | #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1670 | |
| AnnaBridge | 163:e59c8e839560 | 1671 | /*! @name PR - Prescale Register */ |
| AnnaBridge | 163:e59c8e839560 | 1672 | #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1673 | #define CTIMER_PR_PRVAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1674 | #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1675 | |
| AnnaBridge | 163:e59c8e839560 | 1676 | /*! @name PC - Prescale Counter */ |
| AnnaBridge | 163:e59c8e839560 | 1677 | #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1678 | #define CTIMER_PC_PCVAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1679 | #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1680 | |
| AnnaBridge | 163:e59c8e839560 | 1681 | /*! @name MCR - Match Control Register */ |
| AnnaBridge | 163:e59c8e839560 | 1682 | #define CTIMER_MCR_MR0I_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 1683 | #define CTIMER_MCR_MR0I_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1684 | #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1685 | #define CTIMER_MCR_MR0R_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 1686 | #define CTIMER_MCR_MR0R_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1687 | #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1688 | #define CTIMER_MCR_MR0S_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 1689 | #define CTIMER_MCR_MR0S_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1690 | #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1691 | #define CTIMER_MCR_MR1I_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 1692 | #define CTIMER_MCR_MR1I_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 1693 | #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1694 | #define CTIMER_MCR_MR1R_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 1695 | #define CTIMER_MCR_MR1R_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1696 | #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1697 | #define CTIMER_MCR_MR1S_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 1698 | #define CTIMER_MCR_MR1S_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 1699 | #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1700 | #define CTIMER_MCR_MR2I_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 1701 | #define CTIMER_MCR_MR2I_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 1702 | #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1703 | #define CTIMER_MCR_MR2R_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 1704 | #define CTIMER_MCR_MR2R_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 1705 | #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1706 | #define CTIMER_MCR_MR2S_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 1707 | #define CTIMER_MCR_MR2S_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 1708 | #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1709 | #define CTIMER_MCR_MR3I_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 1710 | #define CTIMER_MCR_MR3I_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 1711 | #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1712 | #define CTIMER_MCR_MR3R_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 1713 | #define CTIMER_MCR_MR3R_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 1714 | #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1715 | #define CTIMER_MCR_MR3S_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 1716 | #define CTIMER_MCR_MR3S_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 1717 | #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1718 | #define CTIMER_MCR_MR0RL_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 1719 | #define CTIMER_MCR_MR0RL_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 1720 | #define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1721 | #define CTIMER_MCR_MR1RL_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 1722 | #define CTIMER_MCR_MR1RL_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 1723 | #define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1724 | #define CTIMER_MCR_MR2RL_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 1725 | #define CTIMER_MCR_MR2RL_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 1726 | #define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1727 | #define CTIMER_MCR_MR3RL_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 1728 | #define CTIMER_MCR_MR3RL_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 1729 | #define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1730 | |
| AnnaBridge | 163:e59c8e839560 | 1731 | /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ |
| AnnaBridge | 163:e59c8e839560 | 1732 | #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1733 | #define CTIMER_MR_MATCH_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1734 | #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1735 | |
| AnnaBridge | 163:e59c8e839560 | 1736 | /* The count of CTIMER_MR */ |
| AnnaBridge | 163:e59c8e839560 | 1737 | #define CTIMER_MR_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1738 | |
| AnnaBridge | 163:e59c8e839560 | 1739 | /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ |
| AnnaBridge | 163:e59c8e839560 | 1740 | #define CTIMER_CCR_CAP0RE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 1741 | #define CTIMER_CCR_CAP0RE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1742 | #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1743 | #define CTIMER_CCR_CAP0FE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 1744 | #define CTIMER_CCR_CAP0FE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1745 | #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1746 | #define CTIMER_CCR_CAP0I_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 1747 | #define CTIMER_CCR_CAP0I_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1748 | #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1749 | #define CTIMER_CCR_CAP1RE_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 1750 | #define CTIMER_CCR_CAP1RE_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 1751 | #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1752 | #define CTIMER_CCR_CAP1FE_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 1753 | #define CTIMER_CCR_CAP1FE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1754 | #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1755 | #define CTIMER_CCR_CAP1I_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 1756 | #define CTIMER_CCR_CAP1I_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 1757 | #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1758 | #define CTIMER_CCR_CAP2RE_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 1759 | #define CTIMER_CCR_CAP2RE_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 1760 | #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1761 | #define CTIMER_CCR_CAP2FE_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 1762 | #define CTIMER_CCR_CAP2FE_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 1763 | #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1764 | #define CTIMER_CCR_CAP2I_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 1765 | #define CTIMER_CCR_CAP2I_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 1766 | #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1767 | #define CTIMER_CCR_CAP3RE_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 1768 | #define CTIMER_CCR_CAP3RE_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 1769 | #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1770 | #define CTIMER_CCR_CAP3FE_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 1771 | #define CTIMER_CCR_CAP3FE_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 1772 | #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1773 | #define CTIMER_CCR_CAP3I_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 1774 | #define CTIMER_CCR_CAP3I_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 1775 | #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1776 | |
| AnnaBridge | 163:e59c8e839560 | 1777 | /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ |
| AnnaBridge | 163:e59c8e839560 | 1778 | #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1779 | #define CTIMER_CR_CAP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1780 | #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1781 | |
| AnnaBridge | 163:e59c8e839560 | 1782 | /* The count of CTIMER_CR */ |
| AnnaBridge | 163:e59c8e839560 | 1783 | #define CTIMER_CR_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1784 | |
| AnnaBridge | 163:e59c8e839560 | 1785 | /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ |
| AnnaBridge | 163:e59c8e839560 | 1786 | #define CTIMER_EMR_EM0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 1787 | #define CTIMER_EMR_EM0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1788 | #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1789 | #define CTIMER_EMR_EM1_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 1790 | #define CTIMER_EMR_EM1_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1791 | #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1792 | #define CTIMER_EMR_EM2_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 1793 | #define CTIMER_EMR_EM2_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1794 | #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1795 | #define CTIMER_EMR_EM3_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 1796 | #define CTIMER_EMR_EM3_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 1797 | #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1798 | #define CTIMER_EMR_EMC0_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 1799 | #define CTIMER_EMR_EMC0_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1800 | #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1801 | #define CTIMER_EMR_EMC1_MASK (0xC0U) |
| AnnaBridge | 163:e59c8e839560 | 1802 | #define CTIMER_EMR_EMC1_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 1803 | #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1804 | #define CTIMER_EMR_EMC2_MASK (0x300U) |
| AnnaBridge | 163:e59c8e839560 | 1805 | #define CTIMER_EMR_EMC2_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 1806 | #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1807 | #define CTIMER_EMR_EMC3_MASK (0xC00U) |
| AnnaBridge | 163:e59c8e839560 | 1808 | #define CTIMER_EMR_EMC3_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 1809 | #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1810 | |
| AnnaBridge | 163:e59c8e839560 | 1811 | /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ |
| AnnaBridge | 163:e59c8e839560 | 1812 | #define CTIMER_CTCR_CTMODE_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 1813 | #define CTIMER_CTCR_CTMODE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1814 | #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1815 | #define CTIMER_CTCR_CINSEL_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 1816 | #define CTIMER_CTCR_CINSEL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1817 | #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1818 | #define CTIMER_CTCR_ENCC_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 1819 | #define CTIMER_CTCR_ENCC_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1820 | #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1821 | #define CTIMER_CTCR_SELCC_MASK (0xE0U) |
| AnnaBridge | 163:e59c8e839560 | 1822 | #define CTIMER_CTCR_SELCC_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 1823 | #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1824 | |
| AnnaBridge | 163:e59c8e839560 | 1825 | /*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ |
| AnnaBridge | 163:e59c8e839560 | 1826 | #define CTIMER_PWMC_PWMEN0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 1827 | #define CTIMER_PWMC_PWMEN0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1828 | #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1829 | #define CTIMER_PWMC_PWMEN1_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 1830 | #define CTIMER_PWMC_PWMEN1_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1831 | #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1832 | #define CTIMER_PWMC_PWMEN2_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 1833 | #define CTIMER_PWMC_PWMEN2_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1834 | #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1835 | #define CTIMER_PWMC_PWMEN3_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 1836 | #define CTIMER_PWMC_PWMEN3_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 1837 | #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1838 | |
| AnnaBridge | 163:e59c8e839560 | 1839 | /*! @name MSR - Match Shadow Register */ |
| AnnaBridge | 163:e59c8e839560 | 1840 | #define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1841 | #define CTIMER_MSR_SHADOWW_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1842 | #define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1843 | |
| AnnaBridge | 163:e59c8e839560 | 1844 | /* The count of CTIMER_MSR */ |
| AnnaBridge | 163:e59c8e839560 | 1845 | #define CTIMER_MSR_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 1846 | |
| AnnaBridge | 163:e59c8e839560 | 1847 | |
| AnnaBridge | 163:e59c8e839560 | 1848 | /*! |
| AnnaBridge | 163:e59c8e839560 | 1849 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1850 | */ /* end of group CTIMER_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 1851 | |
| AnnaBridge | 163:e59c8e839560 | 1852 | |
| AnnaBridge | 163:e59c8e839560 | 1853 | /* CTIMER - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 1854 | /** Peripheral CTIMER0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 1855 | #define CTIMER0_BASE (0x40008000u) |
| AnnaBridge | 163:e59c8e839560 | 1856 | /** Peripheral CTIMER0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 1857 | #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 1858 | /** Peripheral CTIMER1 base address */ |
| AnnaBridge | 163:e59c8e839560 | 1859 | #define CTIMER1_BASE (0x40009000u) |
| AnnaBridge | 163:e59c8e839560 | 1860 | /** Peripheral CTIMER1 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 1861 | #define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 1862 | /** Peripheral CTIMER2 base address */ |
| AnnaBridge | 163:e59c8e839560 | 1863 | #define CTIMER2_BASE (0x40028000u) |
| AnnaBridge | 163:e59c8e839560 | 1864 | /** Peripheral CTIMER2 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 1865 | #define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 1866 | /** Peripheral CTIMER3 base address */ |
| AnnaBridge | 163:e59c8e839560 | 1867 | #define CTIMER3_BASE (0x40048000u) |
| AnnaBridge | 163:e59c8e839560 | 1868 | /** Peripheral CTIMER3 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 1869 | #define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 1870 | /** Peripheral CTIMER4 base address */ |
| AnnaBridge | 163:e59c8e839560 | 1871 | #define CTIMER4_BASE (0x40049000u) |
| AnnaBridge | 163:e59c8e839560 | 1872 | /** Peripheral CTIMER4 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 1873 | #define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 1874 | /** Array initializer of CTIMER peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 1875 | #define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE } |
| AnnaBridge | 163:e59c8e839560 | 1876 | /** Array initializer of CTIMER peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 1877 | #define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 } |
| AnnaBridge | 163:e59c8e839560 | 1878 | /** Interrupt vectors for the CTIMER peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 1879 | #define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 1880 | |
| AnnaBridge | 163:e59c8e839560 | 1881 | /*! |
| AnnaBridge | 163:e59c8e839560 | 1882 | * @} |
| AnnaBridge | 163:e59c8e839560 | 1883 | */ /* end of group CTIMER_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 1884 | |
| AnnaBridge | 163:e59c8e839560 | 1885 | |
| AnnaBridge | 163:e59c8e839560 | 1886 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 1887 | -- DMA Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 1888 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 1889 | |
| AnnaBridge | 163:e59c8e839560 | 1890 | /*! |
| AnnaBridge | 163:e59c8e839560 | 1891 | * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 1892 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 1893 | */ |
| AnnaBridge | 163:e59c8e839560 | 1894 | |
| AnnaBridge | 163:e59c8e839560 | 1895 | /** DMA - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 1896 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 1897 | __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 1898 | __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 1899 | __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 1900 | uint8_t RESERVED_0[20]; |
| AnnaBridge | 163:e59c8e839560 | 1901 | struct { /* offset: 0x20, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1902 | __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1903 | uint8_t RESERVED_0[4]; |
| AnnaBridge | 163:e59c8e839560 | 1904 | __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1905 | uint8_t RESERVED_1[4]; |
| AnnaBridge | 163:e59c8e839560 | 1906 | __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1907 | uint8_t RESERVED_2[4]; |
| AnnaBridge | 163:e59c8e839560 | 1908 | __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1909 | uint8_t RESERVED_3[4]; |
| AnnaBridge | 163:e59c8e839560 | 1910 | __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1911 | uint8_t RESERVED_4[4]; |
| AnnaBridge | 163:e59c8e839560 | 1912 | __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1913 | uint8_t RESERVED_5[4]; |
| AnnaBridge | 163:e59c8e839560 | 1914 | __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1915 | uint8_t RESERVED_6[4]; |
| AnnaBridge | 163:e59c8e839560 | 1916 | __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1917 | uint8_t RESERVED_7[4]; |
| AnnaBridge | 163:e59c8e839560 | 1918 | __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1919 | uint8_t RESERVED_8[4]; |
| AnnaBridge | 163:e59c8e839560 | 1920 | __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1921 | uint8_t RESERVED_9[4]; |
| AnnaBridge | 163:e59c8e839560 | 1922 | __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1923 | uint8_t RESERVED_10[4]; |
| AnnaBridge | 163:e59c8e839560 | 1924 | __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 1925 | } COMMON[1]; |
| AnnaBridge | 163:e59c8e839560 | 1926 | uint8_t RESERVED_1[900]; |
| AnnaBridge | 163:e59c8e839560 | 1927 | struct { /* offset: 0x400, array step: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 1928 | __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 1929 | __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 1930 | __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 1931 | uint8_t RESERVED_0[4]; |
| AnnaBridge | 163:e59c8e839560 | 1932 | } CHANNEL[30]; |
| AnnaBridge | 163:e59c8e839560 | 1933 | } DMA_Type; |
| AnnaBridge | 163:e59c8e839560 | 1934 | |
| AnnaBridge | 163:e59c8e839560 | 1935 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 1936 | -- DMA Register Masks |
| AnnaBridge | 163:e59c8e839560 | 1937 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 1938 | |
| AnnaBridge | 163:e59c8e839560 | 1939 | /*! |
| AnnaBridge | 163:e59c8e839560 | 1940 | * @addtogroup DMA_Register_Masks DMA Register Masks |
| AnnaBridge | 163:e59c8e839560 | 1941 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 1942 | */ |
| AnnaBridge | 163:e59c8e839560 | 1943 | |
| AnnaBridge | 163:e59c8e839560 | 1944 | /*! @name CTRL - DMA control. */ |
| AnnaBridge | 163:e59c8e839560 | 1945 | #define DMA_CTRL_ENABLE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 1946 | #define DMA_CTRL_ENABLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1947 | #define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1948 | |
| AnnaBridge | 163:e59c8e839560 | 1949 | /*! @name INTSTAT - Interrupt status. */ |
| AnnaBridge | 163:e59c8e839560 | 1950 | #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 1951 | #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1952 | #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1953 | #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 1954 | #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 1955 | #define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1956 | |
| AnnaBridge | 163:e59c8e839560 | 1957 | /*! @name SRAMBASE - SRAM address of the channel configuration table. */ |
| AnnaBridge | 163:e59c8e839560 | 1958 | #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) |
| AnnaBridge | 163:e59c8e839560 | 1959 | #define DMA_SRAMBASE_OFFSET_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 1960 | #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1961 | |
| AnnaBridge | 163:e59c8e839560 | 1962 | /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ |
| AnnaBridge | 163:e59c8e839560 | 1963 | #define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1964 | #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1965 | #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1966 | |
| AnnaBridge | 163:e59c8e839560 | 1967 | /* The count of DMA_COMMON_ENABLESET */ |
| AnnaBridge | 163:e59c8e839560 | 1968 | #define DMA_COMMON_ENABLESET_COUNT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1969 | |
| AnnaBridge | 163:e59c8e839560 | 1970 | /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ |
| AnnaBridge | 163:e59c8e839560 | 1971 | #define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1972 | #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1973 | #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1974 | |
| AnnaBridge | 163:e59c8e839560 | 1975 | /* The count of DMA_COMMON_ENABLECLR */ |
| AnnaBridge | 163:e59c8e839560 | 1976 | #define DMA_COMMON_ENABLECLR_COUNT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1977 | |
| AnnaBridge | 163:e59c8e839560 | 1978 | /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ |
| AnnaBridge | 163:e59c8e839560 | 1979 | #define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1980 | #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1981 | #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1982 | |
| AnnaBridge | 163:e59c8e839560 | 1983 | /* The count of DMA_COMMON_ACTIVE */ |
| AnnaBridge | 163:e59c8e839560 | 1984 | #define DMA_COMMON_ACTIVE_COUNT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1985 | |
| AnnaBridge | 163:e59c8e839560 | 1986 | /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ |
| AnnaBridge | 163:e59c8e839560 | 1987 | #define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1988 | #define DMA_COMMON_BUSY_BSY_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1989 | #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1990 | |
| AnnaBridge | 163:e59c8e839560 | 1991 | /* The count of DMA_COMMON_BUSY */ |
| AnnaBridge | 163:e59c8e839560 | 1992 | #define DMA_COMMON_BUSY_COUNT (1U) |
| AnnaBridge | 163:e59c8e839560 | 1993 | |
| AnnaBridge | 163:e59c8e839560 | 1994 | /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ |
| AnnaBridge | 163:e59c8e839560 | 1995 | #define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 1996 | #define DMA_COMMON_ERRINT_ERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 1997 | #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 1998 | |
| AnnaBridge | 163:e59c8e839560 | 1999 | /* The count of DMA_COMMON_ERRINT */ |
| AnnaBridge | 163:e59c8e839560 | 2000 | #define DMA_COMMON_ERRINT_COUNT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2001 | |
| AnnaBridge | 163:e59c8e839560 | 2002 | /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ |
| AnnaBridge | 163:e59c8e839560 | 2003 | #define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 2004 | #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2005 | #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2006 | |
| AnnaBridge | 163:e59c8e839560 | 2007 | /* The count of DMA_COMMON_INTENSET */ |
| AnnaBridge | 163:e59c8e839560 | 2008 | #define DMA_COMMON_INTENSET_COUNT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2009 | |
| AnnaBridge | 163:e59c8e839560 | 2010 | /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ |
| AnnaBridge | 163:e59c8e839560 | 2011 | #define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 2012 | #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2013 | #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2014 | |
| AnnaBridge | 163:e59c8e839560 | 2015 | /* The count of DMA_COMMON_INTENCLR */ |
| AnnaBridge | 163:e59c8e839560 | 2016 | #define DMA_COMMON_INTENCLR_COUNT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2017 | |
| AnnaBridge | 163:e59c8e839560 | 2018 | /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ |
| AnnaBridge | 163:e59c8e839560 | 2019 | #define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 2020 | #define DMA_COMMON_INTA_IA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2021 | #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2022 | |
| AnnaBridge | 163:e59c8e839560 | 2023 | /* The count of DMA_COMMON_INTA */ |
| AnnaBridge | 163:e59c8e839560 | 2024 | #define DMA_COMMON_INTA_COUNT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2025 | |
| AnnaBridge | 163:e59c8e839560 | 2026 | /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ |
| AnnaBridge | 163:e59c8e839560 | 2027 | #define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 2028 | #define DMA_COMMON_INTB_IB_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2029 | #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2030 | |
| AnnaBridge | 163:e59c8e839560 | 2031 | /* The count of DMA_COMMON_INTB */ |
| AnnaBridge | 163:e59c8e839560 | 2032 | #define DMA_COMMON_INTB_COUNT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2033 | |
| AnnaBridge | 163:e59c8e839560 | 2034 | /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ |
| AnnaBridge | 163:e59c8e839560 | 2035 | #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 2036 | #define DMA_COMMON_SETVALID_SV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2037 | #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2038 | |
| AnnaBridge | 163:e59c8e839560 | 2039 | /* The count of DMA_COMMON_SETVALID */ |
| AnnaBridge | 163:e59c8e839560 | 2040 | #define DMA_COMMON_SETVALID_COUNT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2041 | |
| AnnaBridge | 163:e59c8e839560 | 2042 | /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ |
| AnnaBridge | 163:e59c8e839560 | 2043 | #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 2044 | #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2045 | #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2046 | |
| AnnaBridge | 163:e59c8e839560 | 2047 | /* The count of DMA_COMMON_SETTRIG */ |
| AnnaBridge | 163:e59c8e839560 | 2048 | #define DMA_COMMON_SETTRIG_COUNT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2049 | |
| AnnaBridge | 163:e59c8e839560 | 2050 | /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ |
| AnnaBridge | 163:e59c8e839560 | 2051 | #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 2052 | #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2053 | #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2054 | |
| AnnaBridge | 163:e59c8e839560 | 2055 | /* The count of DMA_COMMON_ABORT */ |
| AnnaBridge | 163:e59c8e839560 | 2056 | #define DMA_COMMON_ABORT_COUNT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2057 | |
| AnnaBridge | 163:e59c8e839560 | 2058 | /*! @name CHANNEL_CFG - Configuration register for DMA channel . */ |
| AnnaBridge | 163:e59c8e839560 | 2059 | #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2060 | #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2061 | #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2062 | #define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 2063 | #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2064 | #define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2065 | #define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 2066 | #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2067 | #define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2068 | #define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 2069 | #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 2070 | #define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2071 | #define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 2072 | #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 2073 | #define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2074 | #define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) |
| AnnaBridge | 163:e59c8e839560 | 2075 | #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 2076 | #define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2077 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 2078 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 2079 | #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2080 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 2081 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 2082 | #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2083 | #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) |
| AnnaBridge | 163:e59c8e839560 | 2084 | #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 2085 | #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2086 | |
| AnnaBridge | 163:e59c8e839560 | 2087 | /* The count of DMA_CHANNEL_CFG */ |
| AnnaBridge | 163:e59c8e839560 | 2088 | #define DMA_CHANNEL_CFG_COUNT (30U) |
| AnnaBridge | 163:e59c8e839560 | 2089 | |
| AnnaBridge | 163:e59c8e839560 | 2090 | /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ |
| AnnaBridge | 163:e59c8e839560 | 2091 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2092 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2093 | #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2094 | #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2095 | #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2096 | #define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2097 | |
| AnnaBridge | 163:e59c8e839560 | 2098 | /* The count of DMA_CHANNEL_CTLSTAT */ |
| AnnaBridge | 163:e59c8e839560 | 2099 | #define DMA_CHANNEL_CTLSTAT_COUNT (30U) |
| AnnaBridge | 163:e59c8e839560 | 2100 | |
| AnnaBridge | 163:e59c8e839560 | 2101 | /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ |
| AnnaBridge | 163:e59c8e839560 | 2102 | #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2103 | #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2104 | #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2105 | #define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 2106 | #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2107 | #define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2108 | #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2109 | #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2110 | #define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2111 | #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 2112 | #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 2113 | #define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2114 | #define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 2115 | #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2116 | #define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2117 | #define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 2118 | #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 2119 | #define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2120 | #define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) |
| AnnaBridge | 163:e59c8e839560 | 2121 | #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 2122 | #define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2123 | #define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) |
| AnnaBridge | 163:e59c8e839560 | 2124 | #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 2125 | #define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2126 | #define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) |
| AnnaBridge | 163:e59c8e839560 | 2127 | #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 2128 | #define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2129 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) |
| AnnaBridge | 163:e59c8e839560 | 2130 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 2131 | #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2132 | |
| AnnaBridge | 163:e59c8e839560 | 2133 | /* The count of DMA_CHANNEL_XFERCFG */ |
| AnnaBridge | 163:e59c8e839560 | 2134 | #define DMA_CHANNEL_XFERCFG_COUNT (30U) |
| AnnaBridge | 163:e59c8e839560 | 2135 | |
| AnnaBridge | 163:e59c8e839560 | 2136 | |
| AnnaBridge | 163:e59c8e839560 | 2137 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2138 | * @} |
| AnnaBridge | 163:e59c8e839560 | 2139 | */ /* end of group DMA_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 2140 | |
| AnnaBridge | 163:e59c8e839560 | 2141 | |
| AnnaBridge | 163:e59c8e839560 | 2142 | /* DMA - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 2143 | /** Peripheral DMA0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 2144 | #define DMA0_BASE (0x40082000u) |
| AnnaBridge | 163:e59c8e839560 | 2145 | /** Peripheral DMA0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 2146 | #define DMA0 ((DMA_Type *)DMA0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 2147 | /** Array initializer of DMA peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 2148 | #define DMA_BASE_ADDRS { DMA0_BASE } |
| AnnaBridge | 163:e59c8e839560 | 2149 | /** Array initializer of DMA peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 2150 | #define DMA_BASE_PTRS { DMA0 } |
| AnnaBridge | 163:e59c8e839560 | 2151 | /** Interrupt vectors for the DMA peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 2152 | #define DMA_IRQS { DMA0_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 2153 | |
| AnnaBridge | 163:e59c8e839560 | 2154 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2155 | * @} |
| AnnaBridge | 163:e59c8e839560 | 2156 | */ /* end of group DMA_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 2157 | |
| AnnaBridge | 163:e59c8e839560 | 2158 | |
| AnnaBridge | 163:e59c8e839560 | 2159 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 2160 | -- DMIC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 2161 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 2162 | |
| AnnaBridge | 163:e59c8e839560 | 2163 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2164 | * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 2165 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 2166 | */ |
| AnnaBridge | 163:e59c8e839560 | 2167 | |
| AnnaBridge | 163:e59c8e839560 | 2168 | /** DMIC - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 2169 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 2170 | struct { /* offset: 0x0, array step: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 2171 | __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 2172 | __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 2173 | __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 2174 | __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 2175 | __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 2176 | uint8_t RESERVED_0[108]; |
| AnnaBridge | 163:e59c8e839560 | 2177 | __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 2178 | __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 2179 | __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 2180 | __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 2181 | __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 2182 | uint8_t RESERVED_1[108]; |
| AnnaBridge | 163:e59c8e839560 | 2183 | } CHANNEL[2]; |
| AnnaBridge | 163:e59c8e839560 | 2184 | uint8_t RESERVED_0[3328]; |
| AnnaBridge | 163:e59c8e839560 | 2185 | __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */ |
| AnnaBridge | 163:e59c8e839560 | 2186 | uint8_t RESERVED_1[8]; |
| AnnaBridge | 163:e59c8e839560 | 2187 | __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */ |
| AnnaBridge | 163:e59c8e839560 | 2188 | __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */ |
| AnnaBridge | 163:e59c8e839560 | 2189 | uint8_t RESERVED_2[108]; |
| AnnaBridge | 163:e59c8e839560 | 2190 | __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */ |
| AnnaBridge | 163:e59c8e839560 | 2191 | __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */ |
| AnnaBridge | 163:e59c8e839560 | 2192 | __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */ |
| AnnaBridge | 163:e59c8e839560 | 2193 | __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */ |
| AnnaBridge | 163:e59c8e839560 | 2194 | __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */ |
| AnnaBridge | 163:e59c8e839560 | 2195 | __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */ |
| AnnaBridge | 163:e59c8e839560 | 2196 | __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */ |
| AnnaBridge | 163:e59c8e839560 | 2197 | uint8_t RESERVED_3[96]; |
| AnnaBridge | 163:e59c8e839560 | 2198 | __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */ |
| AnnaBridge | 163:e59c8e839560 | 2199 | } DMIC_Type; |
| AnnaBridge | 163:e59c8e839560 | 2200 | |
| AnnaBridge | 163:e59c8e839560 | 2201 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 2202 | -- DMIC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 2203 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 2204 | |
| AnnaBridge | 163:e59c8e839560 | 2205 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2206 | * @addtogroup DMIC_Register_Masks DMIC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 2207 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 2208 | */ |
| AnnaBridge | 163:e59c8e839560 | 2209 | |
| AnnaBridge | 163:e59c8e839560 | 2210 | /*! @name CHANNEL_OSR - Oversample Rate register 0 */ |
| AnnaBridge | 163:e59c8e839560 | 2211 | #define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 2212 | #define DMIC_CHANNEL_OSR_OSR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2213 | #define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2214 | |
| AnnaBridge | 163:e59c8e839560 | 2215 | /* The count of DMIC_CHANNEL_OSR */ |
| AnnaBridge | 163:e59c8e839560 | 2216 | #define DMIC_CHANNEL_OSR_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2217 | |
| AnnaBridge | 163:e59c8e839560 | 2218 | /*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */ |
| AnnaBridge | 163:e59c8e839560 | 2219 | #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2220 | #define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2221 | #define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2222 | |
| AnnaBridge | 163:e59c8e839560 | 2223 | /* The count of DMIC_CHANNEL_DIVHFCLK */ |
| AnnaBridge | 163:e59c8e839560 | 2224 | #define DMIC_CHANNEL_DIVHFCLK_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2225 | |
| AnnaBridge | 163:e59c8e839560 | 2226 | /*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */ |
| AnnaBridge | 163:e59c8e839560 | 2227 | #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 2228 | #define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2229 | #define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2230 | |
| AnnaBridge | 163:e59c8e839560 | 2231 | /* The count of DMIC_CHANNEL_PREAC2FSCOEF */ |
| AnnaBridge | 163:e59c8e839560 | 2232 | #define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2233 | |
| AnnaBridge | 163:e59c8e839560 | 2234 | /*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */ |
| AnnaBridge | 163:e59c8e839560 | 2235 | #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 2236 | #define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2237 | #define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2238 | |
| AnnaBridge | 163:e59c8e839560 | 2239 | /* The count of DMIC_CHANNEL_PREAC4FSCOEF */ |
| AnnaBridge | 163:e59c8e839560 | 2240 | #define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2241 | |
| AnnaBridge | 163:e59c8e839560 | 2242 | /*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */ |
| AnnaBridge | 163:e59c8e839560 | 2243 | #define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU) |
| AnnaBridge | 163:e59c8e839560 | 2244 | #define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2245 | #define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2246 | |
| AnnaBridge | 163:e59c8e839560 | 2247 | /* The count of DMIC_CHANNEL_GAINSHIFT */ |
| AnnaBridge | 163:e59c8e839560 | 2248 | #define DMIC_CHANNEL_GAINSHIFT_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2249 | |
| AnnaBridge | 163:e59c8e839560 | 2250 | /*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */ |
| AnnaBridge | 163:e59c8e839560 | 2251 | #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2252 | #define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2253 | #define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2254 | #define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 2255 | #define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2256 | #define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2257 | #define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2258 | #define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2259 | #define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2260 | #define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 2261 | #define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 2262 | #define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2263 | #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U) |
| AnnaBridge | 163:e59c8e839560 | 2264 | #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 2265 | #define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2266 | |
| AnnaBridge | 163:e59c8e839560 | 2267 | /* The count of DMIC_CHANNEL_FIFO_CTRL */ |
| AnnaBridge | 163:e59c8e839560 | 2268 | #define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2269 | |
| AnnaBridge | 163:e59c8e839560 | 2270 | /*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */ |
| AnnaBridge | 163:e59c8e839560 | 2271 | #define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2272 | #define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2273 | #define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2274 | #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 2275 | #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2276 | #define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2277 | #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2278 | #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2279 | #define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2280 | |
| AnnaBridge | 163:e59c8e839560 | 2281 | /* The count of DMIC_CHANNEL_FIFO_STATUS */ |
| AnnaBridge | 163:e59c8e839560 | 2282 | #define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2283 | |
| AnnaBridge | 163:e59c8e839560 | 2284 | /*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */ |
| AnnaBridge | 163:e59c8e839560 | 2285 | #define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 2286 | #define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2287 | #define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2288 | |
| AnnaBridge | 163:e59c8e839560 | 2289 | /* The count of DMIC_CHANNEL_FIFO_DATA */ |
| AnnaBridge | 163:e59c8e839560 | 2290 | #define DMIC_CHANNEL_FIFO_DATA_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2291 | |
| AnnaBridge | 163:e59c8e839560 | 2292 | /*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */ |
| AnnaBridge | 163:e59c8e839560 | 2293 | #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2294 | #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2295 | #define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2296 | #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 2297 | #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2298 | #define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2299 | |
| AnnaBridge | 163:e59c8e839560 | 2300 | /* The count of DMIC_CHANNEL_PHY_CTRL */ |
| AnnaBridge | 163:e59c8e839560 | 2301 | #define DMIC_CHANNEL_PHY_CTRL_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2302 | |
| AnnaBridge | 163:e59c8e839560 | 2303 | /*! @name CHANNEL_DC_CTRL - DC Control register 0 */ |
| AnnaBridge | 163:e59c8e839560 | 2304 | #define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 2305 | #define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2306 | #define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2307 | #define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U) |
| AnnaBridge | 163:e59c8e839560 | 2308 | #define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2309 | #define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2310 | #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 2311 | #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 2312 | #define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2313 | |
| AnnaBridge | 163:e59c8e839560 | 2314 | /* The count of DMIC_CHANNEL_DC_CTRL */ |
| AnnaBridge | 163:e59c8e839560 | 2315 | #define DMIC_CHANNEL_DC_CTRL_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2316 | |
| AnnaBridge | 163:e59c8e839560 | 2317 | /*! @name CHANEN - Channel Enable register */ |
| AnnaBridge | 163:e59c8e839560 | 2318 | #define DMIC_CHANEN_EN_CH0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2319 | #define DMIC_CHANEN_EN_CH0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2320 | #define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2321 | #define DMIC_CHANEN_EN_CH1_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 2322 | #define DMIC_CHANEN_EN_CH1_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2323 | #define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2324 | |
| AnnaBridge | 163:e59c8e839560 | 2325 | /*! @name IOCFG - I/O Configuration register */ |
| AnnaBridge | 163:e59c8e839560 | 2326 | #define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2327 | #define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2328 | #define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2329 | #define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 2330 | #define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2331 | #define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2332 | #define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2333 | #define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2334 | #define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2335 | |
| AnnaBridge | 163:e59c8e839560 | 2336 | /*! @name USE2FS - Use 2FS register */ |
| AnnaBridge | 163:e59c8e839560 | 2337 | #define DMIC_USE2FS_USE2FS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2338 | #define DMIC_USE2FS_USE2FS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2339 | #define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2340 | |
| AnnaBridge | 163:e59c8e839560 | 2341 | /*! @name HWVADGAIN - HWVAD input gain register */ |
| AnnaBridge | 163:e59c8e839560 | 2342 | #define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2343 | #define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2344 | #define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2345 | |
| AnnaBridge | 163:e59c8e839560 | 2346 | /*! @name HWVADHPFS - HWVAD filter control register */ |
| AnnaBridge | 163:e59c8e839560 | 2347 | #define DMIC_HWVADHPFS_HPFS_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 2348 | #define DMIC_HWVADHPFS_HPFS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2349 | #define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2350 | |
| AnnaBridge | 163:e59c8e839560 | 2351 | /*! @name HWVADST10 - HWVAD control register */ |
| AnnaBridge | 163:e59c8e839560 | 2352 | #define DMIC_HWVADST10_ST10_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2353 | #define DMIC_HWVADST10_ST10_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2354 | #define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2355 | |
| AnnaBridge | 163:e59c8e839560 | 2356 | /*! @name HWVADRSTT - HWVAD filter reset register */ |
| AnnaBridge | 163:e59c8e839560 | 2357 | #define DMIC_HWVADRSTT_RSTT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2358 | #define DMIC_HWVADRSTT_RSTT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2359 | #define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2360 | |
| AnnaBridge | 163:e59c8e839560 | 2361 | /*! @name HWVADTHGN - HWVAD noise estimator gain register */ |
| AnnaBridge | 163:e59c8e839560 | 2362 | #define DMIC_HWVADTHGN_THGN_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2363 | #define DMIC_HWVADTHGN_THGN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2364 | #define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2365 | |
| AnnaBridge | 163:e59c8e839560 | 2366 | /*! @name HWVADTHGS - HWVAD signal estimator gain register */ |
| AnnaBridge | 163:e59c8e839560 | 2367 | #define DMIC_HWVADTHGS_THGS_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2368 | #define DMIC_HWVADTHGS_THGS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2369 | #define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2370 | |
| AnnaBridge | 163:e59c8e839560 | 2371 | /*! @name HWVADLOWZ - HWVAD noise envelope estimator register */ |
| AnnaBridge | 163:e59c8e839560 | 2372 | #define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 2373 | #define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2374 | #define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2375 | |
| AnnaBridge | 163:e59c8e839560 | 2376 | /*! @name ID - Module Identification register */ |
| AnnaBridge | 163:e59c8e839560 | 2377 | #define DMIC_ID_ID_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 2378 | #define DMIC_ID_ID_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2379 | #define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2380 | |
| AnnaBridge | 163:e59c8e839560 | 2381 | |
| AnnaBridge | 163:e59c8e839560 | 2382 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2383 | * @} |
| AnnaBridge | 163:e59c8e839560 | 2384 | */ /* end of group DMIC_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 2385 | |
| AnnaBridge | 163:e59c8e839560 | 2386 | |
| AnnaBridge | 163:e59c8e839560 | 2387 | /* DMIC - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 2388 | /** Peripheral DMIC0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 2389 | #define DMIC0_BASE (0x40090000u) |
| AnnaBridge | 163:e59c8e839560 | 2390 | /** Peripheral DMIC0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 2391 | #define DMIC0 ((DMIC_Type *)DMIC0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 2392 | /** Array initializer of DMIC peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 2393 | #define DMIC_BASE_ADDRS { DMIC0_BASE } |
| AnnaBridge | 163:e59c8e839560 | 2394 | /** Array initializer of DMIC peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 2395 | #define DMIC_BASE_PTRS { DMIC0 } |
| AnnaBridge | 163:e59c8e839560 | 2396 | /** Interrupt vectors for the DMIC peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 2397 | #define DMIC_IRQS { DMIC0_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 2398 | #define DMIC_HWVAD_IRQS { HWVAD0_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 2399 | |
| AnnaBridge | 163:e59c8e839560 | 2400 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2401 | * @} |
| AnnaBridge | 163:e59c8e839560 | 2402 | */ /* end of group DMIC_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 2403 | |
| AnnaBridge | 163:e59c8e839560 | 2404 | |
| AnnaBridge | 163:e59c8e839560 | 2405 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 2406 | -- EEPROM Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 2407 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 2408 | |
| AnnaBridge | 163:e59c8e839560 | 2409 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2410 | * @addtogroup EEPROM_Peripheral_Access_Layer EEPROM Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 2411 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 2412 | */ |
| AnnaBridge | 163:e59c8e839560 | 2413 | |
| AnnaBridge | 163:e59c8e839560 | 2414 | /** EEPROM - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 2415 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 2416 | __IO uint32_t CMD; /**< EEPROM command register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 2417 | uint8_t RESERVED_0[4]; |
| AnnaBridge | 163:e59c8e839560 | 2418 | __IO uint32_t RWSTATE; /**< EEPROM read wait state register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 2419 | __IO uint32_t AUTOPROG; /**< EEPROM auto programming register, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 2420 | __IO uint32_t WSTATE; /**< EEPROM wait state register, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 2421 | __IO uint32_t CLKDIV; /**< EEPROM clock divider register, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 2422 | __IO uint32_t PWRDWN; /**< EEPROM power-down register, offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 2423 | uint8_t RESERVED_1[4028]; |
| AnnaBridge | 163:e59c8e839560 | 2424 | __O uint32_t INTENCLR; /**< EEPROM interrupt enable clear, offset: 0xFD8 */ |
| AnnaBridge | 163:e59c8e839560 | 2425 | __O uint32_t INTENSET; /**< EEPROM interrupt enable set, offset: 0xFDC */ |
| AnnaBridge | 163:e59c8e839560 | 2426 | __I uint32_t INTSTAT; /**< EEPROM interrupt status, offset: 0xFE0 */ |
| AnnaBridge | 163:e59c8e839560 | 2427 | __I uint32_t INTEN; /**< EEPROM interrupt enable, offset: 0xFE4 */ |
| AnnaBridge | 163:e59c8e839560 | 2428 | __O uint32_t INTSTATCLR; /**< EEPROM interrupt status clear, offset: 0xFE8 */ |
| AnnaBridge | 163:e59c8e839560 | 2429 | __O uint32_t INTSTATSET; /**< EEPROM interrupt status set, offset: 0xFEC */ |
| AnnaBridge | 163:e59c8e839560 | 2430 | } EEPROM_Type; |
| AnnaBridge | 163:e59c8e839560 | 2431 | |
| AnnaBridge | 163:e59c8e839560 | 2432 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 2433 | -- EEPROM Register Masks |
| AnnaBridge | 163:e59c8e839560 | 2434 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 2435 | |
| AnnaBridge | 163:e59c8e839560 | 2436 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2437 | * @addtogroup EEPROM_Register_Masks EEPROM Register Masks |
| AnnaBridge | 163:e59c8e839560 | 2438 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 2439 | */ |
| AnnaBridge | 163:e59c8e839560 | 2440 | |
| AnnaBridge | 163:e59c8e839560 | 2441 | /*! @name CMD - EEPROM command register */ |
| AnnaBridge | 163:e59c8e839560 | 2442 | #define EEPROM_CMD_CMD_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 2443 | #define EEPROM_CMD_CMD_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2444 | #define EEPROM_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2445 | |
| AnnaBridge | 163:e59c8e839560 | 2446 | /*! @name RWSTATE - EEPROM read wait state register */ |
| AnnaBridge | 163:e59c8e839560 | 2447 | #define EEPROM_RWSTATE_RPHASE2_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 2448 | #define EEPROM_RWSTATE_RPHASE2_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2449 | #define EEPROM_RWSTATE_RPHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE2_SHIFT)) & EEPROM_RWSTATE_RPHASE2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2450 | #define EEPROM_RWSTATE_RPHASE1_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 2451 | #define EEPROM_RWSTATE_RPHASE1_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 2452 | #define EEPROM_RWSTATE_RPHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE1_SHIFT)) & EEPROM_RWSTATE_RPHASE1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2453 | |
| AnnaBridge | 163:e59c8e839560 | 2454 | /*! @name AUTOPROG - EEPROM auto programming register */ |
| AnnaBridge | 163:e59c8e839560 | 2455 | #define EEPROM_AUTOPROG_AUTOPROG_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 2456 | #define EEPROM_AUTOPROG_AUTOPROG_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2457 | #define EEPROM_AUTOPROG_AUTOPROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_AUTOPROG_AUTOPROG_SHIFT)) & EEPROM_AUTOPROG_AUTOPROG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2458 | |
| AnnaBridge | 163:e59c8e839560 | 2459 | /*! @name WSTATE - EEPROM wait state register */ |
| AnnaBridge | 163:e59c8e839560 | 2460 | #define EEPROM_WSTATE_PHASE3_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 2461 | #define EEPROM_WSTATE_PHASE3_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2462 | #define EEPROM_WSTATE_PHASE3(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE3_SHIFT)) & EEPROM_WSTATE_PHASE3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2463 | #define EEPROM_WSTATE_PHASE2_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 2464 | #define EEPROM_WSTATE_PHASE2_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 2465 | #define EEPROM_WSTATE_PHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE2_SHIFT)) & EEPROM_WSTATE_PHASE2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2466 | #define EEPROM_WSTATE_PHASE1_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 2467 | #define EEPROM_WSTATE_PHASE1_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 2468 | #define EEPROM_WSTATE_PHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE1_SHIFT)) & EEPROM_WSTATE_PHASE1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2469 | #define EEPROM_WSTATE_LCK_PARWEP_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 2470 | #define EEPROM_WSTATE_LCK_PARWEP_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 2471 | #define EEPROM_WSTATE_LCK_PARWEP(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_LCK_PARWEP_SHIFT)) & EEPROM_WSTATE_LCK_PARWEP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2472 | |
| AnnaBridge | 163:e59c8e839560 | 2473 | /*! @name CLKDIV - EEPROM clock divider register */ |
| AnnaBridge | 163:e59c8e839560 | 2474 | #define EEPROM_CLKDIV_CLKDIV_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 2475 | #define EEPROM_CLKDIV_CLKDIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2476 | #define EEPROM_CLKDIV_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CLKDIV_CLKDIV_SHIFT)) & EEPROM_CLKDIV_CLKDIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2477 | |
| AnnaBridge | 163:e59c8e839560 | 2478 | /*! @name PWRDWN - EEPROM power-down register */ |
| AnnaBridge | 163:e59c8e839560 | 2479 | #define EEPROM_PWRDWN_PWRDWN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2480 | #define EEPROM_PWRDWN_PWRDWN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2481 | #define EEPROM_PWRDWN_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_PWRDWN_PWRDWN_SHIFT)) & EEPROM_PWRDWN_PWRDWN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2482 | |
| AnnaBridge | 163:e59c8e839560 | 2483 | /*! @name INTENCLR - EEPROM interrupt enable clear */ |
| AnnaBridge | 163:e59c8e839560 | 2484 | #define EEPROM_INTENCLR_PROG_CLR_EN_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2485 | #define EEPROM_INTENCLR_PROG_CLR_EN_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2486 | #define EEPROM_INTENCLR_PROG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENCLR_PROG_CLR_EN_SHIFT)) & EEPROM_INTENCLR_PROG_CLR_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2487 | |
| AnnaBridge | 163:e59c8e839560 | 2488 | /*! @name INTENSET - EEPROM interrupt enable set */ |
| AnnaBridge | 163:e59c8e839560 | 2489 | #define EEPROM_INTENSET_PROG_SET_EN_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2490 | #define EEPROM_INTENSET_PROG_SET_EN_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2491 | #define EEPROM_INTENSET_PROG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENSET_PROG_SET_EN_SHIFT)) & EEPROM_INTENSET_PROG_SET_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2492 | |
| AnnaBridge | 163:e59c8e839560 | 2493 | /*! @name INTSTAT - EEPROM interrupt status */ |
| AnnaBridge | 163:e59c8e839560 | 2494 | #define EEPROM_INTSTAT_END_OF_PROG_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2495 | #define EEPROM_INTSTAT_END_OF_PROG_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2496 | #define EEPROM_INTSTAT_END_OF_PROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTAT_END_OF_PROG_SHIFT)) & EEPROM_INTSTAT_END_OF_PROG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2497 | |
| AnnaBridge | 163:e59c8e839560 | 2498 | /*! @name INTEN - EEPROM interrupt enable */ |
| AnnaBridge | 163:e59c8e839560 | 2499 | #define EEPROM_INTEN_EE_PROG_DONE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2500 | #define EEPROM_INTEN_EE_PROG_DONE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2501 | #define EEPROM_INTEN_EE_PROG_DONE(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTEN_EE_PROG_DONE_SHIFT)) & EEPROM_INTEN_EE_PROG_DONE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2502 | |
| AnnaBridge | 163:e59c8e839560 | 2503 | /*! @name INTSTATCLR - EEPROM interrupt status clear */ |
| AnnaBridge | 163:e59c8e839560 | 2504 | #define EEPROM_INTSTATCLR_PROG_CLR_ST_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2505 | #define EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2506 | #define EEPROM_INTSTATCLR_PROG_CLR_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT)) & EEPROM_INTSTATCLR_PROG_CLR_ST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2507 | |
| AnnaBridge | 163:e59c8e839560 | 2508 | /*! @name INTSTATSET - EEPROM interrupt status set */ |
| AnnaBridge | 163:e59c8e839560 | 2509 | #define EEPROM_INTSTATSET_PROG_SET_ST_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2510 | #define EEPROM_INTSTATSET_PROG_SET_ST_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2511 | #define EEPROM_INTSTATSET_PROG_SET_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATSET_PROG_SET_ST_SHIFT)) & EEPROM_INTSTATSET_PROG_SET_ST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2512 | |
| AnnaBridge | 163:e59c8e839560 | 2513 | |
| AnnaBridge | 163:e59c8e839560 | 2514 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2515 | * @} |
| AnnaBridge | 163:e59c8e839560 | 2516 | */ /* end of group EEPROM_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 2517 | |
| AnnaBridge | 163:e59c8e839560 | 2518 | |
| AnnaBridge | 163:e59c8e839560 | 2519 | /* EEPROM - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 2520 | /** Peripheral EEPROM base address */ |
| AnnaBridge | 163:e59c8e839560 | 2521 | #define EEPROM_BASE (0x40014000u) |
| AnnaBridge | 163:e59c8e839560 | 2522 | /** Peripheral EEPROM base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 2523 | #define EEPROM ((EEPROM_Type *)EEPROM_BASE) |
| AnnaBridge | 163:e59c8e839560 | 2524 | /** Array initializer of EEPROM peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 2525 | #define EEPROM_BASE_ADDRS { EEPROM_BASE } |
| AnnaBridge | 163:e59c8e839560 | 2526 | /** Array initializer of EEPROM peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 2527 | #define EEPROM_BASE_PTRS { EEPROM } |
| AnnaBridge | 163:e59c8e839560 | 2528 | /** Interrupt vectors for the EEPROM peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 2529 | #define EEPROM_IRQS { EEPROM_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 2530 | |
| AnnaBridge | 163:e59c8e839560 | 2531 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2532 | * @} |
| AnnaBridge | 163:e59c8e839560 | 2533 | */ /* end of group EEPROM_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 2534 | |
| AnnaBridge | 163:e59c8e839560 | 2535 | |
| AnnaBridge | 163:e59c8e839560 | 2536 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 2537 | -- EMC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 2538 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 2539 | |
| AnnaBridge | 163:e59c8e839560 | 2540 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2541 | * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 2542 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 2543 | */ |
| AnnaBridge | 163:e59c8e839560 | 2544 | |
| AnnaBridge | 163:e59c8e839560 | 2545 | /** EMC - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 2546 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 2547 | __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 2548 | __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 2549 | __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 2550 | uint8_t RESERVED_0[20]; |
| AnnaBridge | 163:e59c8e839560 | 2551 | __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 2552 | __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 2553 | __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 2554 | uint8_t RESERVED_1[4]; |
| AnnaBridge | 163:e59c8e839560 | 2555 | __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 2556 | __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */ |
| AnnaBridge | 163:e59c8e839560 | 2557 | __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */ |
| AnnaBridge | 163:e59c8e839560 | 2558 | __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */ |
| AnnaBridge | 163:e59c8e839560 | 2559 | __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2560 | __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */ |
| AnnaBridge | 163:e59c8e839560 | 2561 | __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */ |
| AnnaBridge | 163:e59c8e839560 | 2562 | __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */ |
| AnnaBridge | 163:e59c8e839560 | 2563 | __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */ |
| AnnaBridge | 163:e59c8e839560 | 2564 | __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */ |
| AnnaBridge | 163:e59c8e839560 | 2565 | __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */ |
| AnnaBridge | 163:e59c8e839560 | 2566 | uint8_t RESERVED_2[36]; |
| AnnaBridge | 163:e59c8e839560 | 2567 | __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2568 | uint8_t RESERVED_3[124]; |
| AnnaBridge | 163:e59c8e839560 | 2569 | struct { /* offset: 0x100, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 2570 | __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 2571 | __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 2572 | uint8_t RESERVED_0[24]; |
| AnnaBridge | 163:e59c8e839560 | 2573 | } DYNAMIC[4]; |
| AnnaBridge | 163:e59c8e839560 | 2574 | uint8_t RESERVED_4[128]; |
| AnnaBridge | 163:e59c8e839560 | 2575 | struct { /* offset: 0x200, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 2576 | __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 2577 | __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 2578 | __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 2579 | __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 2580 | __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 2581 | __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 2582 | __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 2583 | uint8_t RESERVED_0[4]; |
| AnnaBridge | 163:e59c8e839560 | 2584 | } STATIC[4]; |
| AnnaBridge | 163:e59c8e839560 | 2585 | } EMC_Type; |
| AnnaBridge | 163:e59c8e839560 | 2586 | |
| AnnaBridge | 163:e59c8e839560 | 2587 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 2588 | -- EMC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 2589 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 2590 | |
| AnnaBridge | 163:e59c8e839560 | 2591 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2592 | * @addtogroup EMC_Register_Masks EMC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 2593 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 2594 | */ |
| AnnaBridge | 163:e59c8e839560 | 2595 | |
| AnnaBridge | 163:e59c8e839560 | 2596 | /*! @name CONTROL - Controls operation of the memory controller */ |
| AnnaBridge | 163:e59c8e839560 | 2597 | #define EMC_CONTROL_E_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2598 | #define EMC_CONTROL_E_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2599 | #define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2600 | #define EMC_CONTROL_M_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 2601 | #define EMC_CONTROL_M_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2602 | #define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2603 | #define EMC_CONTROL_L_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2604 | #define EMC_CONTROL_L_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2605 | #define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2606 | |
| AnnaBridge | 163:e59c8e839560 | 2607 | /*! @name STATUS - Provides EMC status information */ |
| AnnaBridge | 163:e59c8e839560 | 2608 | #define EMC_STATUS_B_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2609 | #define EMC_STATUS_B_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2610 | #define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2611 | #define EMC_STATUS_S_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 2612 | #define EMC_STATUS_S_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2613 | #define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2614 | #define EMC_STATUS_SA_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2615 | #define EMC_STATUS_SA_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2616 | #define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2617 | |
| AnnaBridge | 163:e59c8e839560 | 2618 | /*! @name CONFIG - Configures operation of the memory controller */ |
| AnnaBridge | 163:e59c8e839560 | 2619 | #define EMC_CONFIG_EM_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2620 | #define EMC_CONFIG_EM_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2621 | #define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2622 | #define EMC_CONFIG_CLKR_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 2623 | #define EMC_CONFIG_CLKR_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 2624 | #define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2625 | |
| AnnaBridge | 163:e59c8e839560 | 2626 | /*! @name DYNAMICCONTROL - Controls dynamic memory operation */ |
| AnnaBridge | 163:e59c8e839560 | 2627 | #define EMC_DYNAMICCONTROL_CE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2628 | #define EMC_DYNAMICCONTROL_CE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2629 | #define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2630 | #define EMC_DYNAMICCONTROL_CS_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 2631 | #define EMC_DYNAMICCONTROL_CS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2632 | #define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2633 | #define EMC_DYNAMICCONTROL_SR_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 2634 | #define EMC_DYNAMICCONTROL_SR_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2635 | #define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2636 | #define EMC_DYNAMICCONTROL_MMC_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 2637 | #define EMC_DYNAMICCONTROL_MMC_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 2638 | #define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2639 | #define EMC_DYNAMICCONTROL_I_MASK (0x180U) |
| AnnaBridge | 163:e59c8e839560 | 2640 | #define EMC_DYNAMICCONTROL_I_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 2641 | #define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2642 | |
| AnnaBridge | 163:e59c8e839560 | 2643 | /*! @name DYNAMICREFRESH - Configures dynamic memory refresh */ |
| AnnaBridge | 163:e59c8e839560 | 2644 | #define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU) |
| AnnaBridge | 163:e59c8e839560 | 2645 | #define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2646 | #define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2647 | |
| AnnaBridge | 163:e59c8e839560 | 2648 | /*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */ |
| AnnaBridge | 163:e59c8e839560 | 2649 | #define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 2650 | #define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2651 | #define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2652 | |
| AnnaBridge | 163:e59c8e839560 | 2653 | /*! @name DYNAMICRP - Precharge command period */ |
| AnnaBridge | 163:e59c8e839560 | 2654 | #define EMC_DYNAMICRP_TRP_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2655 | #define EMC_DYNAMICRP_TRP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2656 | #define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2657 | |
| AnnaBridge | 163:e59c8e839560 | 2658 | /*! @name DYNAMICRAS - Active to precharge command period */ |
| AnnaBridge | 163:e59c8e839560 | 2659 | #define EMC_DYNAMICRAS_TRAS_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2660 | #define EMC_DYNAMICRAS_TRAS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2661 | #define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2662 | |
| AnnaBridge | 163:e59c8e839560 | 2663 | /*! @name DYNAMICSREX - Self-refresh exit time */ |
| AnnaBridge | 163:e59c8e839560 | 2664 | #define EMC_DYNAMICSREX_TSREX_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2665 | #define EMC_DYNAMICSREX_TSREX_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2666 | #define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2667 | |
| AnnaBridge | 163:e59c8e839560 | 2668 | /*! @name DYNAMICAPR - Last-data-out to active command time */ |
| AnnaBridge | 163:e59c8e839560 | 2669 | #define EMC_DYNAMICAPR_TAPR_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2670 | #define EMC_DYNAMICAPR_TAPR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2671 | #define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2672 | |
| AnnaBridge | 163:e59c8e839560 | 2673 | /*! @name DYNAMICDAL - Data-in to active command time */ |
| AnnaBridge | 163:e59c8e839560 | 2674 | #define EMC_DYNAMICDAL_TDAL_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2675 | #define EMC_DYNAMICDAL_TDAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2676 | #define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2677 | |
| AnnaBridge | 163:e59c8e839560 | 2678 | /*! @name DYNAMICWR - Write recovery time */ |
| AnnaBridge | 163:e59c8e839560 | 2679 | #define EMC_DYNAMICWR_TWR_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2680 | #define EMC_DYNAMICWR_TWR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2681 | #define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2682 | |
| AnnaBridge | 163:e59c8e839560 | 2683 | /*! @name DYNAMICRC - Selects the active to active command period */ |
| AnnaBridge | 163:e59c8e839560 | 2684 | #define EMC_DYNAMICRC_TRC_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 2685 | #define EMC_DYNAMICRC_TRC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2686 | #define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2687 | |
| AnnaBridge | 163:e59c8e839560 | 2688 | /*! @name DYNAMICRFC - Selects the auto-refresh period */ |
| AnnaBridge | 163:e59c8e839560 | 2689 | #define EMC_DYNAMICRFC_TRFC_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 2690 | #define EMC_DYNAMICRFC_TRFC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2691 | #define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2692 | |
| AnnaBridge | 163:e59c8e839560 | 2693 | /*! @name DYNAMICXSR - Time for exit self-refresh to active command */ |
| AnnaBridge | 163:e59c8e839560 | 2694 | #define EMC_DYNAMICXSR_TXSR_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 2695 | #define EMC_DYNAMICXSR_TXSR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2696 | #define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2697 | |
| AnnaBridge | 163:e59c8e839560 | 2698 | /*! @name DYNAMICRRD - Latency for active bank A to active bank B */ |
| AnnaBridge | 163:e59c8e839560 | 2699 | #define EMC_DYNAMICRRD_TRRD_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2700 | #define EMC_DYNAMICRRD_TRRD_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2701 | #define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2702 | |
| AnnaBridge | 163:e59c8e839560 | 2703 | /*! @name DYNAMICMRD - Time for load mode register to active command */ |
| AnnaBridge | 163:e59c8e839560 | 2704 | #define EMC_DYNAMICMRD_TMRD_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2705 | #define EMC_DYNAMICMRD_TMRD_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2706 | #define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2707 | |
| AnnaBridge | 163:e59c8e839560 | 2708 | /*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */ |
| AnnaBridge | 163:e59c8e839560 | 2709 | #define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU) |
| AnnaBridge | 163:e59c8e839560 | 2710 | #define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2711 | #define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2712 | |
| AnnaBridge | 163:e59c8e839560 | 2713 | /*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */ |
| AnnaBridge | 163:e59c8e839560 | 2714 | #define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U) |
| AnnaBridge | 163:e59c8e839560 | 2715 | #define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 2716 | #define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2717 | #define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U) |
| AnnaBridge | 163:e59c8e839560 | 2718 | #define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 2719 | #define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2720 | #define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 2721 | #define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 2722 | #define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2723 | #define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 2724 | #define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 2725 | #define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2726 | #define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 2727 | #define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 2728 | #define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2729 | |
| AnnaBridge | 163:e59c8e839560 | 2730 | /* The count of EMC_DYNAMIC_DYNAMICCONFIG */ |
| AnnaBridge | 163:e59c8e839560 | 2731 | #define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2732 | |
| AnnaBridge | 163:e59c8e839560 | 2733 | /*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */ |
| AnnaBridge | 163:e59c8e839560 | 2734 | #define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 2735 | #define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2736 | #define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2737 | #define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U) |
| AnnaBridge | 163:e59c8e839560 | 2738 | #define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 2739 | #define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2740 | |
| AnnaBridge | 163:e59c8e839560 | 2741 | /* The count of EMC_DYNAMIC_DYNAMICRASCAS */ |
| AnnaBridge | 163:e59c8e839560 | 2742 | #define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2743 | |
| AnnaBridge | 163:e59c8e839560 | 2744 | /*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */ |
| AnnaBridge | 163:e59c8e839560 | 2745 | #define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 2746 | #define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2747 | #define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2748 | #define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 2749 | #define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 2750 | #define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2751 | #define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 2752 | #define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 2753 | #define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2754 | #define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 2755 | #define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 2756 | #define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2757 | #define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 2758 | #define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 2759 | #define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2760 | #define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 2761 | #define EMC_STATIC_STATICCONFIG_B_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 2762 | #define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2763 | #define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 2764 | #define EMC_STATIC_STATICCONFIG_P_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 2765 | #define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2766 | |
| AnnaBridge | 163:e59c8e839560 | 2767 | /* The count of EMC_STATIC_STATICCONFIG */ |
| AnnaBridge | 163:e59c8e839560 | 2768 | #define EMC_STATIC_STATICCONFIG_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2769 | |
| AnnaBridge | 163:e59c8e839560 | 2770 | /*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */ |
| AnnaBridge | 163:e59c8e839560 | 2771 | #define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2772 | #define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2773 | #define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2774 | |
| AnnaBridge | 163:e59c8e839560 | 2775 | /* The count of EMC_STATIC_STATICWAITWEN */ |
| AnnaBridge | 163:e59c8e839560 | 2776 | #define EMC_STATIC_STATICWAITWEN_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2777 | |
| AnnaBridge | 163:e59c8e839560 | 2778 | /*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */ |
| AnnaBridge | 163:e59c8e839560 | 2779 | #define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2780 | #define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2781 | #define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2782 | |
| AnnaBridge | 163:e59c8e839560 | 2783 | /* The count of EMC_STATIC_STATICWAITOEN */ |
| AnnaBridge | 163:e59c8e839560 | 2784 | #define EMC_STATIC_STATICWAITOEN_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2785 | |
| AnnaBridge | 163:e59c8e839560 | 2786 | /*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */ |
| AnnaBridge | 163:e59c8e839560 | 2787 | #define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 2788 | #define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2789 | #define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2790 | |
| AnnaBridge | 163:e59c8e839560 | 2791 | /* The count of EMC_STATIC_STATICWAITRD */ |
| AnnaBridge | 163:e59c8e839560 | 2792 | #define EMC_STATIC_STATICWAITRD_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2793 | |
| AnnaBridge | 163:e59c8e839560 | 2794 | /*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */ |
| AnnaBridge | 163:e59c8e839560 | 2795 | #define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 2796 | #define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2797 | #define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2798 | |
| AnnaBridge | 163:e59c8e839560 | 2799 | /* The count of EMC_STATIC_STATICWAITPAGE */ |
| AnnaBridge | 163:e59c8e839560 | 2800 | #define EMC_STATIC_STATICWAITPAGE_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2801 | |
| AnnaBridge | 163:e59c8e839560 | 2802 | /*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */ |
| AnnaBridge | 163:e59c8e839560 | 2803 | #define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 2804 | #define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2805 | #define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2806 | |
| AnnaBridge | 163:e59c8e839560 | 2807 | /* The count of EMC_STATIC_STATICWAITWR */ |
| AnnaBridge | 163:e59c8e839560 | 2808 | #define EMC_STATIC_STATICWAITWR_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2809 | |
| AnnaBridge | 163:e59c8e839560 | 2810 | /*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */ |
| AnnaBridge | 163:e59c8e839560 | 2811 | #define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 2812 | #define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2813 | #define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2814 | |
| AnnaBridge | 163:e59c8e839560 | 2815 | /* The count of EMC_STATIC_STATICWAITTURN */ |
| AnnaBridge | 163:e59c8e839560 | 2816 | #define EMC_STATIC_STATICWAITTURN_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2817 | |
| AnnaBridge | 163:e59c8e839560 | 2818 | |
| AnnaBridge | 163:e59c8e839560 | 2819 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2820 | * @} |
| AnnaBridge | 163:e59c8e839560 | 2821 | */ /* end of group EMC_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 2822 | |
| AnnaBridge | 163:e59c8e839560 | 2823 | |
| AnnaBridge | 163:e59c8e839560 | 2824 | /* EMC - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 2825 | /** Peripheral EMC base address */ |
| AnnaBridge | 163:e59c8e839560 | 2826 | #define EMC_BASE (0x40081000u) |
| AnnaBridge | 163:e59c8e839560 | 2827 | /** Peripheral EMC base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 2828 | #define EMC ((EMC_Type *)EMC_BASE) |
| AnnaBridge | 163:e59c8e839560 | 2829 | /** Array initializer of EMC peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 2830 | #define EMC_BASE_ADDRS { EMC_BASE } |
| AnnaBridge | 163:e59c8e839560 | 2831 | /** Array initializer of EMC peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 2832 | #define EMC_BASE_PTRS { EMC } |
| AnnaBridge | 163:e59c8e839560 | 2833 | |
| AnnaBridge | 163:e59c8e839560 | 2834 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2835 | * @} |
| AnnaBridge | 163:e59c8e839560 | 2836 | */ /* end of group EMC_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 2837 | |
| AnnaBridge | 163:e59c8e839560 | 2838 | |
| AnnaBridge | 163:e59c8e839560 | 2839 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 2840 | -- ENET Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 2841 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 2842 | |
| AnnaBridge | 163:e59c8e839560 | 2843 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2844 | * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 2845 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 2846 | */ |
| AnnaBridge | 163:e59c8e839560 | 2847 | |
| AnnaBridge | 163:e59c8e839560 | 2848 | /** ENET - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 2849 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 2850 | __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 2851 | __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 2852 | __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 2853 | __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 2854 | uint8_t RESERVED_0[64]; |
| AnnaBridge | 163:e59c8e839560 | 2855 | __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */ |
| AnnaBridge | 163:e59c8e839560 | 2856 | uint8_t RESERVED_1[28]; |
| AnnaBridge | 163:e59c8e839560 | 2857 | __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 2858 | uint8_t RESERVED_2[24]; |
| AnnaBridge | 163:e59c8e839560 | 2859 | __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */ |
| AnnaBridge | 163:e59c8e839560 | 2860 | uint8_t RESERVED_3[4]; |
| AnnaBridge | 163:e59c8e839560 | 2861 | __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */ |
| AnnaBridge | 163:e59c8e839560 | 2862 | uint8_t RESERVED_4[4]; |
| AnnaBridge | 163:e59c8e839560 | 2863 | __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 2864 | uint8_t RESERVED_5[4]; |
| AnnaBridge | 163:e59c8e839560 | 2865 | __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */ |
| AnnaBridge | 163:e59c8e839560 | 2866 | __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */ |
| AnnaBridge | 163:e59c8e839560 | 2867 | __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */ |
| AnnaBridge | 163:e59c8e839560 | 2868 | uint8_t RESERVED_6[4]; |
| AnnaBridge | 163:e59c8e839560 | 2869 | __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */ |
| AnnaBridge | 163:e59c8e839560 | 2870 | __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */ |
| AnnaBridge | 163:e59c8e839560 | 2871 | uint8_t RESERVED_7[8]; |
| AnnaBridge | 163:e59c8e839560 | 2872 | __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */ |
| AnnaBridge | 163:e59c8e839560 | 2873 | __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */ |
| AnnaBridge | 163:e59c8e839560 | 2874 | __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */ |
| AnnaBridge | 163:e59c8e839560 | 2875 | __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */ |
| AnnaBridge | 163:e59c8e839560 | 2876 | uint8_t RESERVED_8[48]; |
| AnnaBridge | 163:e59c8e839560 | 2877 | __IO uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */ |
| AnnaBridge | 163:e59c8e839560 | 2878 | __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */ |
| AnnaBridge | 163:e59c8e839560 | 2879 | uint8_t RESERVED_9[4]; |
| AnnaBridge | 163:e59c8e839560 | 2880 | __IO uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 2881 | uint8_t RESERVED_10[216]; |
| AnnaBridge | 163:e59c8e839560 | 2882 | __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */ |
| AnnaBridge | 163:e59c8e839560 | 2883 | __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */ |
| AnnaBridge | 163:e59c8e839560 | 2884 | uint8_t RESERVED_11[248]; |
| AnnaBridge | 163:e59c8e839560 | 2885 | __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */ |
| AnnaBridge | 163:e59c8e839560 | 2886 | __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */ |
| AnnaBridge | 163:e59c8e839560 | 2887 | uint8_t RESERVED_12[2040]; |
| AnnaBridge | 163:e59c8e839560 | 2888 | __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */ |
| AnnaBridge | 163:e59c8e839560 | 2889 | __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */ |
| AnnaBridge | 163:e59c8e839560 | 2890 | __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */ |
| AnnaBridge | 163:e59c8e839560 | 2891 | __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */ |
| AnnaBridge | 163:e59c8e839560 | 2892 | __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */ |
| AnnaBridge | 163:e59c8e839560 | 2893 | __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */ |
| AnnaBridge | 163:e59c8e839560 | 2894 | __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */ |
| AnnaBridge | 163:e59c8e839560 | 2895 | __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */ |
| AnnaBridge | 163:e59c8e839560 | 2896 | __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */ |
| AnnaBridge | 163:e59c8e839560 | 2897 | uint8_t RESERVED_13[12]; |
| AnnaBridge | 163:e59c8e839560 | 2898 | __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */ |
| AnnaBridge | 163:e59c8e839560 | 2899 | __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */ |
| AnnaBridge | 163:e59c8e839560 | 2900 | uint8_t RESERVED_14[32]; |
| AnnaBridge | 163:e59c8e839560 | 2901 | __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */ |
| AnnaBridge | 163:e59c8e839560 | 2902 | __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */ |
| AnnaBridge | 163:e59c8e839560 | 2903 | uint8_t RESERVED_15[160]; |
| AnnaBridge | 163:e59c8e839560 | 2904 | __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */ |
| AnnaBridge | 163:e59c8e839560 | 2905 | uint8_t RESERVED_16[28]; |
| AnnaBridge | 163:e59c8e839560 | 2906 | __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */ |
| AnnaBridge | 163:e59c8e839560 | 2907 | uint8_t RESERVED_17[12]; |
| AnnaBridge | 163:e59c8e839560 | 2908 | __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */ |
| AnnaBridge | 163:e59c8e839560 | 2909 | uint8_t RESERVED_18[204]; |
| AnnaBridge | 163:e59c8e839560 | 2910 | struct { /* offset: 0xD00, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2911 | __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2912 | __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2913 | __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2914 | uint8_t RESERVED_0[4]; |
| AnnaBridge | 163:e59c8e839560 | 2915 | __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2916 | __IO uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2917 | __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2918 | __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2919 | __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2920 | __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2921 | uint8_t RESERVED_1[4]; |
| AnnaBridge | 163:e59c8e839560 | 2922 | __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2923 | __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2924 | __IO uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2925 | __IO uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2926 | __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 2927 | } MTL_QUEUE[2]; |
| AnnaBridge | 163:e59c8e839560 | 2928 | uint8_t RESERVED_19[640]; |
| AnnaBridge | 163:e59c8e839560 | 2929 | __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */ |
| AnnaBridge | 163:e59c8e839560 | 2930 | __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */ |
| AnnaBridge | 163:e59c8e839560 | 2931 | __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */ |
| AnnaBridge | 163:e59c8e839560 | 2932 | __IO uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */ |
| AnnaBridge | 163:e59c8e839560 | 2933 | uint8_t RESERVED_20[240]; |
| AnnaBridge | 163:e59c8e839560 | 2934 | struct { /* offset: 0x1100, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2935 | __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2936 | __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2937 | __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2938 | uint8_t RESERVED_0[8]; |
| AnnaBridge | 163:e59c8e839560 | 2939 | __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2940 | uint8_t RESERVED_1[4]; |
| AnnaBridge | 163:e59c8e839560 | 2941 | __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2942 | __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2943 | uint8_t RESERVED_2[4]; |
| AnnaBridge | 163:e59c8e839560 | 2944 | __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2945 | __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2946 | __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2947 | __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2948 | __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2949 | __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2950 | uint8_t RESERVED_3[4]; |
| AnnaBridge | 163:e59c8e839560 | 2951 | __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2952 | uint8_t RESERVED_4[4]; |
| AnnaBridge | 163:e59c8e839560 | 2953 | __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2954 | uint8_t RESERVED_5[4]; |
| AnnaBridge | 163:e59c8e839560 | 2955 | __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2956 | uint8_t RESERVED_6[4]; |
| AnnaBridge | 163:e59c8e839560 | 2957 | __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2958 | __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 2959 | uint8_t RESERVED_7[28]; |
| AnnaBridge | 163:e59c8e839560 | 2960 | } DMA_CH[2]; |
| AnnaBridge | 163:e59c8e839560 | 2961 | } ENET_Type; |
| AnnaBridge | 163:e59c8e839560 | 2962 | |
| AnnaBridge | 163:e59c8e839560 | 2963 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 2964 | -- ENET Register Masks |
| AnnaBridge | 163:e59c8e839560 | 2965 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 2966 | |
| AnnaBridge | 163:e59c8e839560 | 2967 | /*! |
| AnnaBridge | 163:e59c8e839560 | 2968 | * @addtogroup ENET_Register_Masks ENET Register Masks |
| AnnaBridge | 163:e59c8e839560 | 2969 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 2970 | */ |
| AnnaBridge | 163:e59c8e839560 | 2971 | |
| AnnaBridge | 163:e59c8e839560 | 2972 | /*! @name MAC_CONFIG - MAC configuration register */ |
| AnnaBridge | 163:e59c8e839560 | 2973 | #define ENET_MAC_CONFIG_RE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 2974 | #define ENET_MAC_CONFIG_RE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 2975 | #define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2976 | #define ENET_MAC_CONFIG_TE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 2977 | #define ENET_MAC_CONFIG_TE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 2978 | #define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2979 | #define ENET_MAC_CONFIG_PRELEN_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 2980 | #define ENET_MAC_CONFIG_PRELEN_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 2981 | #define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2982 | #define ENET_MAC_CONFIG_DC_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 2983 | #define ENET_MAC_CONFIG_DC_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 2984 | #define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2985 | #define ENET_MAC_CONFIG_BL_MASK (0x60U) |
| AnnaBridge | 163:e59c8e839560 | 2986 | #define ENET_MAC_CONFIG_BL_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 2987 | #define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2988 | #define ENET_MAC_CONFIG_DR_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 2989 | #define ENET_MAC_CONFIG_DR_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 2990 | #define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2991 | #define ENET_MAC_CONFIG_DCRS_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 2992 | #define ENET_MAC_CONFIG_DCRS_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 2993 | #define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2994 | #define ENET_MAC_CONFIG_DO_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 2995 | #define ENET_MAC_CONFIG_DO_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 2996 | #define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 2997 | #define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 2998 | #define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 2999 | #define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3000 | #define ENET_MAC_CONFIG_LM_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 3001 | #define ENET_MAC_CONFIG_LM_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3002 | #define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3003 | #define ENET_MAC_CONFIG_DM_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 3004 | #define ENET_MAC_CONFIG_DM_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 3005 | #define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3006 | #define ENET_MAC_CONFIG_FES_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 3007 | #define ENET_MAC_CONFIG_FES_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 3008 | #define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3009 | #define ENET_MAC_CONFIG_PS_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 3010 | #define ENET_MAC_CONFIG_PS_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 3011 | #define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3012 | #define ENET_MAC_CONFIG_JE_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 3013 | #define ENET_MAC_CONFIG_JE_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3014 | #define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3015 | #define ENET_MAC_CONFIG_JD_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 3016 | #define ENET_MAC_CONFIG_JD_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 3017 | #define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3018 | #define ENET_MAC_CONFIG_BE_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 3019 | #define ENET_MAC_CONFIG_BE_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 3020 | #define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3021 | #define ENET_MAC_CONFIG_WD_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 3022 | #define ENET_MAC_CONFIG_WD_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 3023 | #define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3024 | #define ENET_MAC_CONFIG_ACS_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 3025 | #define ENET_MAC_CONFIG_ACS_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 3026 | #define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3027 | #define ENET_MAC_CONFIG_CST_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 3028 | #define ENET_MAC_CONFIG_CST_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 3029 | #define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3030 | #define ENET_MAC_CONFIG_S2KP_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 3031 | #define ENET_MAC_CONFIG_S2KP_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 3032 | #define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3033 | #define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 3034 | #define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 3035 | #define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3036 | #define ENET_MAC_CONFIG_IPG_MASK (0x7000000U) |
| AnnaBridge | 163:e59c8e839560 | 3037 | #define ENET_MAC_CONFIG_IPG_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 3038 | #define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3039 | #define ENET_MAC_CONFIG_IPC_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 3040 | #define ENET_MAC_CONFIG_IPC_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 3041 | #define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3042 | |
| AnnaBridge | 163:e59c8e839560 | 3043 | /*! @name MAC_EXT_CONFIG - */ |
| AnnaBridge | 163:e59c8e839560 | 3044 | #define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU) |
| AnnaBridge | 163:e59c8e839560 | 3045 | #define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3046 | #define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3047 | #define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 3048 | #define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3049 | #define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3050 | #define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 3051 | #define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 3052 | #define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3053 | #define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 3054 | #define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 3055 | #define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3056 | |
| AnnaBridge | 163:e59c8e839560 | 3057 | /*! @name MAC_FRAME_FILTER - MAC frame filter register */ |
| AnnaBridge | 163:e59c8e839560 | 3058 | #define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3059 | #define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3060 | #define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3061 | #define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 3062 | #define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3063 | #define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3064 | #define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 3065 | #define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3066 | #define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3067 | #define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 3068 | #define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 3069 | #define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3070 | #define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U) |
| AnnaBridge | 163:e59c8e839560 | 3071 | #define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 3072 | #define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3073 | #define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 3074 | #define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3075 | #define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3076 | #define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 3077 | #define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 3078 | #define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3079 | #define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 3080 | #define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 3081 | #define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3082 | |
| AnnaBridge | 163:e59c8e839560 | 3083 | /*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */ |
| AnnaBridge | 163:e59c8e839560 | 3084 | #define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 3085 | #define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3086 | #define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3087 | #define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 3088 | #define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3089 | #define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3090 | |
| AnnaBridge | 163:e59c8e839560 | 3091 | /*! @name MAC_VLAN_TAG - MAC vlan tag register */ |
| AnnaBridge | 163:e59c8e839560 | 3092 | #define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3093 | #define ENET_MAC_VLAN_TAG_VL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3094 | #define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3095 | #define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 3096 | #define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3097 | #define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3098 | #define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 3099 | #define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 3100 | #define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3101 | #define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 3102 | #define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 3103 | #define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3104 | #define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 3105 | #define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 3106 | #define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3107 | #define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 3108 | #define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 3109 | #define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3110 | #define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U) |
| AnnaBridge | 163:e59c8e839560 | 3111 | #define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 3112 | #define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3113 | #define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 3114 | #define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 3115 | #define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3116 | #define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 3117 | #define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 3118 | #define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3119 | #define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 3120 | #define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 3121 | #define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3122 | #define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 3123 | #define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 3124 | #define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3125 | #define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U) |
| AnnaBridge | 163:e59c8e839560 | 3126 | #define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 3127 | #define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3128 | #define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 3129 | #define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 3130 | #define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3131 | |
| AnnaBridge | 163:e59c8e839560 | 3132 | /*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */ |
| AnnaBridge | 163:e59c8e839560 | 3133 | #define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3134 | #define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3135 | #define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3136 | #define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 3137 | #define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3138 | #define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3139 | #define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U) |
| AnnaBridge | 163:e59c8e839560 | 3140 | #define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3141 | #define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3142 | #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 3143 | #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 3144 | #define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3145 | #define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 3146 | #define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3147 | #define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3148 | |
| AnnaBridge | 163:e59c8e839560 | 3149 | /* The count of ENET_MAC_TX_FLOW_CTRL_Q */ |
| AnnaBridge | 163:e59c8e839560 | 3150 | #define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3151 | |
| AnnaBridge | 163:e59c8e839560 | 3152 | /*! @name MAC_RX_FLOW_CTRL - Receive flow control register */ |
| AnnaBridge | 163:e59c8e839560 | 3153 | #define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3154 | #define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3155 | #define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3156 | #define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 3157 | #define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3158 | #define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3159 | |
| AnnaBridge | 163:e59c8e839560 | 3160 | /*! @name MAC_TXQ_PRIO_MAP - */ |
| AnnaBridge | 163:e59c8e839560 | 3161 | #define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 3162 | #define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3163 | #define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3164 | #define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 3165 | #define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3166 | #define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3167 | |
| AnnaBridge | 163:e59c8e839560 | 3168 | /*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3169 | #define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 3170 | #define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3171 | #define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3172 | #define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 3173 | #define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3174 | #define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3175 | #define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 3176 | #define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3177 | #define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3178 | #define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 3179 | #define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3180 | #define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3181 | #define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U) |
| AnnaBridge | 163:e59c8e839560 | 3182 | #define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3183 | #define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3184 | #define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 3185 | #define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3186 | #define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3187 | #define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U) |
| AnnaBridge | 163:e59c8e839560 | 3188 | #define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3189 | #define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3190 | #define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 3191 | #define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3192 | #define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3193 | #define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U) |
| AnnaBridge | 163:e59c8e839560 | 3194 | #define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3195 | #define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3196 | #define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 3197 | #define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 3198 | #define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3199 | #define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U) |
| AnnaBridge | 163:e59c8e839560 | 3200 | #define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 3201 | #define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3202 | |
| AnnaBridge | 163:e59c8e839560 | 3203 | /* The count of ENET_MAC_RXQ_CTRL */ |
| AnnaBridge | 163:e59c8e839560 | 3204 | #define ENET_MAC_RXQ_CTRL_COUNT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3205 | |
| AnnaBridge | 163:e59c8e839560 | 3206 | /*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3207 | #define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 3208 | #define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3209 | #define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3210 | #define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 3211 | #define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3212 | #define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3213 | #define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 3214 | #define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 3215 | #define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3216 | #define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 3217 | #define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3218 | #define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3219 | #define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 3220 | #define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 3221 | #define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3222 | #define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 3223 | #define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 3224 | #define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3225 | |
| AnnaBridge | 163:e59c8e839560 | 3226 | /*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */ |
| AnnaBridge | 163:e59c8e839560 | 3227 | #define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 3228 | #define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3229 | #define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3230 | #define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 3231 | #define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3232 | #define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3233 | #define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 3234 | #define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 3235 | #define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3236 | #define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 3237 | #define ENET_MAC_INTR_EN_TSIE_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3238 | #define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3239 | #define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 3240 | #define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 3241 | #define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3242 | #define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 3243 | #define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 3244 | #define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3245 | |
| AnnaBridge | 163:e59c8e839560 | 3246 | /*! @name MAC_RXTX_STAT - Receive Transmit Status register */ |
| AnnaBridge | 163:e59c8e839560 | 3247 | #define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3248 | #define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3249 | #define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3250 | #define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 3251 | #define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3252 | #define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3253 | #define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 3254 | #define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3255 | #define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3256 | #define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 3257 | #define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3258 | #define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3259 | #define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 3260 | #define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3261 | #define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3262 | #define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 3263 | #define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 3264 | #define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3265 | #define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 3266 | #define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3267 | #define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3268 | |
| AnnaBridge | 163:e59c8e839560 | 3269 | /*! @name MAC_PMT_CRTL_STAT - */ |
| AnnaBridge | 163:e59c8e839560 | 3270 | #define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3271 | #define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3272 | #define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3273 | #define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 3274 | #define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3275 | #define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3276 | #define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 3277 | #define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3278 | #define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3279 | #define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 3280 | #define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 3281 | #define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3282 | #define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 3283 | #define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 3284 | #define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3285 | #define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 3286 | #define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 3287 | #define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3288 | #define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 3289 | #define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 3290 | #define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3291 | #define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U) |
| AnnaBridge | 163:e59c8e839560 | 3292 | #define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 3293 | #define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3294 | #define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 3295 | #define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 3296 | #define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3297 | |
| AnnaBridge | 163:e59c8e839560 | 3298 | /*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */ |
| AnnaBridge | 163:e59c8e839560 | 3299 | #define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3300 | #define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3301 | #define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3302 | |
| AnnaBridge | 163:e59c8e839560 | 3303 | /*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */ |
| AnnaBridge | 163:e59c8e839560 | 3304 | #define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3305 | #define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3306 | #define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3307 | #define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 3308 | #define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3309 | #define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3310 | #define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 3311 | #define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3312 | #define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3313 | #define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 3314 | #define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3315 | #define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3316 | #define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 3317 | #define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3318 | #define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3319 | #define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 3320 | #define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 3321 | #define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3322 | #define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 3323 | #define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3324 | #define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3325 | #define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 3326 | #define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 3327 | #define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3328 | #define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 3329 | #define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 3330 | #define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3331 | #define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 3332 | #define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 3333 | #define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3334 | #define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 3335 | #define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 3336 | #define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3337 | |
| AnnaBridge | 163:e59c8e839560 | 3338 | /*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */ |
| AnnaBridge | 163:e59c8e839560 | 3339 | #define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3340 | #define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3341 | #define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3342 | #define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U) |
| AnnaBridge | 163:e59c8e839560 | 3343 | #define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3344 | #define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3345 | |
| AnnaBridge | 163:e59c8e839560 | 3346 | /*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */ |
| AnnaBridge | 163:e59c8e839560 | 3347 | #define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U) |
| AnnaBridge | 163:e59c8e839560 | 3348 | #define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3349 | #define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3350 | |
| AnnaBridge | 163:e59c8e839560 | 3351 | /*! @name MAC_1US_TIC_COUNTR - */ |
| AnnaBridge | 163:e59c8e839560 | 3352 | #define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3353 | #define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3354 | #define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3355 | |
| AnnaBridge | 163:e59c8e839560 | 3356 | /*! @name MAC_VERSION - MAC version register */ |
| AnnaBridge | 163:e59c8e839560 | 3357 | #define ENET_MAC_VERSION_SNPVER_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 3358 | #define ENET_MAC_VERSION_SNPVER_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3359 | #define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3360 | #define ENET_MAC_VERSION_USERVER_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 3361 | #define ENET_MAC_VERSION_USERVER_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3362 | #define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3363 | |
| AnnaBridge | 163:e59c8e839560 | 3364 | /*! @name MAC_DBG - MAC debug register */ |
| AnnaBridge | 163:e59c8e839560 | 3365 | #define ENET_MAC_DBG_REPESTS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3366 | #define ENET_MAC_DBG_REPESTS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3367 | #define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3368 | #define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U) |
| AnnaBridge | 163:e59c8e839560 | 3369 | #define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3370 | #define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3371 | #define ENET_MAC_DBG_TPESTS_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 3372 | #define ENET_MAC_DBG_TPESTS_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3373 | #define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3374 | #define ENET_MAC_DBG_TFCSTS_MASK (0x60000U) |
| AnnaBridge | 163:e59c8e839560 | 3375 | #define ENET_MAC_DBG_TFCSTS_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 3376 | #define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3377 | |
| AnnaBridge | 163:e59c8e839560 | 3378 | /*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */ |
| AnnaBridge | 163:e59c8e839560 | 3379 | #define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 3380 | #define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3381 | #define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3382 | #define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 3383 | #define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3384 | #define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3385 | #define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3386 | #define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3387 | #define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3388 | #define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 3389 | #define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3390 | #define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3391 | #define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 3392 | #define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3393 | #define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3394 | #define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 3395 | #define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 3396 | #define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3397 | #define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U) |
| AnnaBridge | 163:e59c8e839560 | 3398 | #define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 3399 | #define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3400 | #define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 3401 | #define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 3402 | #define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3403 | #define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U) |
| AnnaBridge | 163:e59c8e839560 | 3404 | #define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 3405 | #define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3406 | #define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 3407 | #define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 3408 | #define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3409 | #define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 3410 | #define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3411 | #define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3412 | #define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 3413 | #define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 3414 | #define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3415 | #define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 3416 | #define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 3417 | #define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3418 | #define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U) |
| AnnaBridge | 163:e59c8e839560 | 3419 | #define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3420 | #define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3421 | #define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 3422 | #define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3423 | #define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3424 | #define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 3425 | #define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3426 | #define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3427 | #define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 3428 | #define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 3429 | #define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3430 | #define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 3431 | #define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 3432 | #define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3433 | #define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U) |
| AnnaBridge | 163:e59c8e839560 | 3434 | #define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 3435 | #define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3436 | #define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 3437 | #define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 3438 | #define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3439 | #define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 3440 | #define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3441 | #define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3442 | #define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 3443 | #define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3444 | #define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3445 | #define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 3446 | #define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 3447 | #define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3448 | #define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U) |
| AnnaBridge | 163:e59c8e839560 | 3449 | #define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 3450 | #define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3451 | #define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 3452 | #define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 3453 | #define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3454 | #define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 3455 | #define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 3456 | #define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3457 | #define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 3458 | #define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 3459 | #define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3460 | #define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 3461 | #define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 3462 | #define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3463 | #define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U) |
| AnnaBridge | 163:e59c8e839560 | 3464 | #define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 3465 | #define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3466 | #define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U) |
| AnnaBridge | 163:e59c8e839560 | 3467 | #define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 3468 | #define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3469 | #define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U) |
| AnnaBridge | 163:e59c8e839560 | 3470 | #define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 3471 | #define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3472 | #define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U) |
| AnnaBridge | 163:e59c8e839560 | 3473 | #define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 3474 | #define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3475 | #define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U) |
| AnnaBridge | 163:e59c8e839560 | 3476 | #define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 3477 | #define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3478 | #define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U) |
| AnnaBridge | 163:e59c8e839560 | 3479 | #define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 3480 | #define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3481 | |
| AnnaBridge | 163:e59c8e839560 | 3482 | /* The count of ENET_MAC_HW_FEAT */ |
| AnnaBridge | 163:e59c8e839560 | 3483 | #define ENET_MAC_HW_FEAT_COUNT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3484 | |
| AnnaBridge | 163:e59c8e839560 | 3485 | /*! @name MAC_MDIO_ADDR - MIDO address Register */ |
| AnnaBridge | 163:e59c8e839560 | 3486 | #define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3487 | #define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3488 | #define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3489 | #define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 3490 | #define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3491 | #define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3492 | #define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U) |
| AnnaBridge | 163:e59c8e839560 | 3493 | #define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3494 | #define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3495 | #define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U) |
| AnnaBridge | 163:e59c8e839560 | 3496 | #define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3497 | #define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3498 | #define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U) |
| AnnaBridge | 163:e59c8e839560 | 3499 | #define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3500 | #define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3501 | #define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U) |
| AnnaBridge | 163:e59c8e839560 | 3502 | #define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 3503 | #define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3504 | #define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 3505 | #define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 3506 | #define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3507 | #define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 3508 | #define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 3509 | #define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3510 | |
| AnnaBridge | 163:e59c8e839560 | 3511 | /*! @name MAC_MDIO_DATA - MDIO Data register */ |
| AnnaBridge | 163:e59c8e839560 | 3512 | #define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3513 | #define ENET_MAC_MDIO_DATA_MD_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3514 | #define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3515 | |
| AnnaBridge | 163:e59c8e839560 | 3516 | /*! @name MAC_ADDR_HIGH - MAC address0 high register */ |
| AnnaBridge | 163:e59c8e839560 | 3517 | #define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3518 | #define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3519 | #define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3520 | #define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 3521 | #define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3522 | #define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3523 | #define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 3524 | #define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 3525 | #define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3526 | |
| AnnaBridge | 163:e59c8e839560 | 3527 | /*! @name MAC_ADDR_LOW - MAC address0 low register */ |
| AnnaBridge | 163:e59c8e839560 | 3528 | #define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3529 | #define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3530 | #define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3531 | |
| AnnaBridge | 163:e59c8e839560 | 3532 | /*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */ |
| AnnaBridge | 163:e59c8e839560 | 3533 | #define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3534 | #define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3535 | #define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3536 | #define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 3537 | #define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3538 | #define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3539 | #define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 3540 | #define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3541 | #define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3542 | #define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 3543 | #define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3544 | #define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3545 | #define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 3546 | #define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3547 | #define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3548 | #define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 3549 | #define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 3550 | #define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3551 | #define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 3552 | #define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3553 | #define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3554 | #define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 3555 | #define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 3556 | #define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3557 | #define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 3558 | #define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 3559 | #define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3560 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 3561 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 3562 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3563 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 3564 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3565 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3566 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 3567 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 3568 | #define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3569 | #define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 3570 | #define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 3571 | #define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3572 | #define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 3573 | #define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 3574 | #define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3575 | #define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U) |
| AnnaBridge | 163:e59c8e839560 | 3576 | #define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3577 | #define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3578 | #define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 3579 | #define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 3580 | #define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3581 | #define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 3582 | #define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 3583 | #define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3584 | #define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 3585 | #define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 3586 | #define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3587 | |
| AnnaBridge | 163:e59c8e839560 | 3588 | /*! @name MAC_SUB_SCND_INCR - Sub-second increment register */ |
| AnnaBridge | 163:e59c8e839560 | 3589 | #define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 3590 | #define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3591 | #define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3592 | |
| AnnaBridge | 163:e59c8e839560 | 3593 | /*! @name MAC_SYS_TIME_SCND - System time seconds register */ |
| AnnaBridge | 163:e59c8e839560 | 3594 | #define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3595 | #define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3596 | #define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3597 | |
| AnnaBridge | 163:e59c8e839560 | 3598 | /*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */ |
| AnnaBridge | 163:e59c8e839560 | 3599 | #define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3600 | #define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3601 | #define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3602 | |
| AnnaBridge | 163:e59c8e839560 | 3603 | /*! @name MAC_SYS_TIME_SCND_UPD - */ |
| AnnaBridge | 163:e59c8e839560 | 3604 | #define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3605 | #define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3606 | #define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3607 | |
| AnnaBridge | 163:e59c8e839560 | 3608 | /*! @name MAC_SYS_TIME_NSCND_UPD - */ |
| AnnaBridge | 163:e59c8e839560 | 3609 | #define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3610 | #define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3611 | #define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3612 | #define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 3613 | #define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 3614 | #define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3615 | |
| AnnaBridge | 163:e59c8e839560 | 3616 | /*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */ |
| AnnaBridge | 163:e59c8e839560 | 3617 | #define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3618 | #define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3619 | #define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3620 | |
| AnnaBridge | 163:e59c8e839560 | 3621 | /*! @name MAC_SYS_TIME_HWORD_SCND - */ |
| AnnaBridge | 163:e59c8e839560 | 3622 | #define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3623 | #define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3624 | #define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3625 | |
| AnnaBridge | 163:e59c8e839560 | 3626 | /*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */ |
| AnnaBridge | 163:e59c8e839560 | 3627 | #define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3628 | #define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3629 | #define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3630 | |
| AnnaBridge | 163:e59c8e839560 | 3631 | /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */ |
| AnnaBridge | 163:e59c8e839560 | 3632 | #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3633 | #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3634 | #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3635 | #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 3636 | #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 3637 | #define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3638 | |
| AnnaBridge | 163:e59c8e839560 | 3639 | /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */ |
| AnnaBridge | 163:e59c8e839560 | 3640 | #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3641 | #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3642 | #define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3643 | |
| AnnaBridge | 163:e59c8e839560 | 3644 | /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */ |
| AnnaBridge | 163:e59c8e839560 | 3645 | #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3646 | #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3647 | #define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3648 | |
| AnnaBridge | 163:e59c8e839560 | 3649 | /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */ |
| AnnaBridge | 163:e59c8e839560 | 3650 | #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3651 | #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3652 | #define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3653 | |
| AnnaBridge | 163:e59c8e839560 | 3654 | /*! @name MTL_OP_MODE - MTL Operation Mode Register */ |
| AnnaBridge | 163:e59c8e839560 | 3655 | #define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 3656 | #define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3657 | #define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3658 | #define ENET_MTL_OP_MODE_RAA_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 3659 | #define ENET_MTL_OP_MODE_RAA_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3660 | #define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3661 | #define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U) |
| AnnaBridge | 163:e59c8e839560 | 3662 | #define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 3663 | #define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3664 | #define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 3665 | #define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3666 | #define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3667 | #define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 3668 | #define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 3669 | #define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3670 | |
| AnnaBridge | 163:e59c8e839560 | 3671 | /*! @name MTL_INTR_STAT - MTL Interrupt Status register */ |
| AnnaBridge | 163:e59c8e839560 | 3672 | #define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3673 | #define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3674 | #define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3675 | #define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 3676 | #define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3677 | #define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3678 | |
| AnnaBridge | 163:e59c8e839560 | 3679 | /*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */ |
| AnnaBridge | 163:e59c8e839560 | 3680 | #define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3681 | #define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3682 | #define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3683 | #define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 3684 | #define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3685 | #define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3686 | #define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 3687 | #define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3688 | #define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3689 | #define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 3690 | #define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3691 | #define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3692 | |
| AnnaBridge | 163:e59c8e839560 | 3693 | /*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */ |
| AnnaBridge | 163:e59c8e839560 | 3694 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3695 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3696 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3697 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 3698 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3699 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3700 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 3701 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3702 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3703 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U) |
| AnnaBridge | 163:e59c8e839560 | 3704 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3705 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3706 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U) |
| AnnaBridge | 163:e59c8e839560 | 3707 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3708 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3709 | |
| AnnaBridge | 163:e59c8e839560 | 3710 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */ |
| AnnaBridge | 163:e59c8e839560 | 3711 | #define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3712 | |
| AnnaBridge | 163:e59c8e839560 | 3713 | /*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */ |
| AnnaBridge | 163:e59c8e839560 | 3714 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU) |
| AnnaBridge | 163:e59c8e839560 | 3715 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3716 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3717 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 3718 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 3719 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3720 | |
| AnnaBridge | 163:e59c8e839560 | 3721 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */ |
| AnnaBridge | 163:e59c8e839560 | 3722 | #define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3723 | |
| AnnaBridge | 163:e59c8e839560 | 3724 | /*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */ |
| AnnaBridge | 163:e59c8e839560 | 3725 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3726 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3727 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3728 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U) |
| AnnaBridge | 163:e59c8e839560 | 3729 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3730 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3731 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 3732 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3733 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3734 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 3735 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3736 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3737 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 3738 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 3739 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3740 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U) |
| AnnaBridge | 163:e59c8e839560 | 3741 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3742 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3743 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U) |
| AnnaBridge | 163:e59c8e839560 | 3744 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 3745 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3746 | |
| AnnaBridge | 163:e59c8e839560 | 3747 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */ |
| AnnaBridge | 163:e59c8e839560 | 3748 | #define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3749 | |
| AnnaBridge | 163:e59c8e839560 | 3750 | /*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */ |
| AnnaBridge | 163:e59c8e839560 | 3751 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 3752 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3753 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3754 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 3755 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3756 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3757 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U) |
| AnnaBridge | 163:e59c8e839560 | 3758 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3759 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3760 | |
| AnnaBridge | 163:e59c8e839560 | 3761 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */ |
| AnnaBridge | 163:e59c8e839560 | 3762 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3763 | |
| AnnaBridge | 163:e59c8e839560 | 3764 | /*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */ |
| AnnaBridge | 163:e59c8e839560 | 3765 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3766 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3767 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3768 | |
| AnnaBridge | 163:e59c8e839560 | 3769 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */ |
| AnnaBridge | 163:e59c8e839560 | 3770 | #define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3771 | |
| AnnaBridge | 163:e59c8e839560 | 3772 | /*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */ |
| AnnaBridge | 163:e59c8e839560 | 3773 | #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3774 | #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3775 | #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3776 | |
| AnnaBridge | 163:e59c8e839560 | 3777 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */ |
| AnnaBridge | 163:e59c8e839560 | 3778 | #define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3779 | |
| AnnaBridge | 163:e59c8e839560 | 3780 | /*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */ |
| AnnaBridge | 163:e59c8e839560 | 3781 | #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU) |
| AnnaBridge | 163:e59c8e839560 | 3782 | #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3783 | #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3784 | |
| AnnaBridge | 163:e59c8e839560 | 3785 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */ |
| AnnaBridge | 163:e59c8e839560 | 3786 | #define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3787 | |
| AnnaBridge | 163:e59c8e839560 | 3788 | /*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */ |
| AnnaBridge | 163:e59c8e839560 | 3789 | #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3790 | #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3791 | #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3792 | |
| AnnaBridge | 163:e59c8e839560 | 3793 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */ |
| AnnaBridge | 163:e59c8e839560 | 3794 | #define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3795 | |
| AnnaBridge | 163:e59c8e839560 | 3796 | /*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */ |
| AnnaBridge | 163:e59c8e839560 | 3797 | #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 3798 | #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3799 | #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3800 | |
| AnnaBridge | 163:e59c8e839560 | 3801 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */ |
| AnnaBridge | 163:e59c8e839560 | 3802 | #define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3803 | |
| AnnaBridge | 163:e59c8e839560 | 3804 | /*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */ |
| AnnaBridge | 163:e59c8e839560 | 3805 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3806 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3807 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3808 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 3809 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3810 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3811 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 3812 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3813 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3814 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 3815 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 3816 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3817 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 3818 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3819 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3820 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 3821 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 3822 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3823 | |
| AnnaBridge | 163:e59c8e839560 | 3824 | /* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */ |
| AnnaBridge | 163:e59c8e839560 | 3825 | #define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3826 | |
| AnnaBridge | 163:e59c8e839560 | 3827 | /*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */ |
| AnnaBridge | 163:e59c8e839560 | 3828 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 3829 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3830 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3831 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 3832 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3833 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3834 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 3835 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3836 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3837 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 3838 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 3839 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3840 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 3841 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 3842 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3843 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U) |
| AnnaBridge | 163:e59c8e839560 | 3844 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 3845 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3846 | |
| AnnaBridge | 163:e59c8e839560 | 3847 | /* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */ |
| AnnaBridge | 163:e59c8e839560 | 3848 | #define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3849 | |
| AnnaBridge | 163:e59c8e839560 | 3850 | /*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */ |
| AnnaBridge | 163:e59c8e839560 | 3851 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU) |
| AnnaBridge | 163:e59c8e839560 | 3852 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3853 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3854 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 3855 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 3856 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3857 | |
| AnnaBridge | 163:e59c8e839560 | 3858 | /* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */ |
| AnnaBridge | 163:e59c8e839560 | 3859 | #define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3860 | |
| AnnaBridge | 163:e59c8e839560 | 3861 | /*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */ |
| AnnaBridge | 163:e59c8e839560 | 3862 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3863 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3864 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3865 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U) |
| AnnaBridge | 163:e59c8e839560 | 3866 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3867 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3868 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 3869 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3870 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3871 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 3872 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3873 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3874 | |
| AnnaBridge | 163:e59c8e839560 | 3875 | /* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */ |
| AnnaBridge | 163:e59c8e839560 | 3876 | #define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3877 | |
| AnnaBridge | 163:e59c8e839560 | 3878 | /*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */ |
| AnnaBridge | 163:e59c8e839560 | 3879 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 3880 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3881 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3882 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 3883 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3884 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3885 | |
| AnnaBridge | 163:e59c8e839560 | 3886 | /* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */ |
| AnnaBridge | 163:e59c8e839560 | 3887 | #define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3888 | |
| AnnaBridge | 163:e59c8e839560 | 3889 | /*! @name DMA_MODE - DMA mode register */ |
| AnnaBridge | 163:e59c8e839560 | 3890 | #define ENET_DMA_MODE_SWR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3891 | #define ENET_DMA_MODE_SWR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3892 | #define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3893 | #define ENET_DMA_MODE_DA_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 3894 | #define ENET_DMA_MODE_DA_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3895 | #define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3896 | #define ENET_DMA_MODE_TAA_MASK (0x1CU) |
| AnnaBridge | 163:e59c8e839560 | 3897 | #define ENET_DMA_MODE_TAA_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3898 | #define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3899 | #define ENET_DMA_MODE_TXPR_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 3900 | #define ENET_DMA_MODE_TXPR_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 3901 | #define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3902 | #define ENET_DMA_MODE_PR_MASK (0x7000U) |
| AnnaBridge | 163:e59c8e839560 | 3903 | #define ENET_DMA_MODE_PR_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3904 | #define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3905 | |
| AnnaBridge | 163:e59c8e839560 | 3906 | /*! @name DMA_SYSBUS_MODE - DMA System Bus mode */ |
| AnnaBridge | 163:e59c8e839560 | 3907 | #define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3908 | #define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3909 | #define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3910 | #define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 3911 | #define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3912 | #define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3913 | #define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 3914 | #define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 3915 | #define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3916 | #define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 3917 | #define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 3918 | #define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3919 | |
| AnnaBridge | 163:e59c8e839560 | 3920 | /*! @name DMA_INTR_STAT - DMA Interrupt status */ |
| AnnaBridge | 163:e59c8e839560 | 3921 | #define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3922 | #define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3923 | #define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3924 | #define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 3925 | #define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3926 | #define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3927 | #define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 3928 | #define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3929 | #define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3930 | #define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 3931 | #define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 3932 | #define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3933 | |
| AnnaBridge | 163:e59c8e839560 | 3934 | /*! @name DMA_DBG_STAT - DMA Debug Status */ |
| AnnaBridge | 163:e59c8e839560 | 3935 | #define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3936 | #define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3937 | #define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3938 | #define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U) |
| AnnaBridge | 163:e59c8e839560 | 3939 | #define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 3940 | #define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3941 | #define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U) |
| AnnaBridge | 163:e59c8e839560 | 3942 | #define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 3943 | #define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3944 | #define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U) |
| AnnaBridge | 163:e59c8e839560 | 3945 | #define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3946 | #define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3947 | #define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U) |
| AnnaBridge | 163:e59c8e839560 | 3948 | #define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 3949 | #define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3950 | |
| AnnaBridge | 163:e59c8e839560 | 3951 | /*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */ |
| AnnaBridge | 163:e59c8e839560 | 3952 | #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 3953 | #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3954 | #define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3955 | #define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U) |
| AnnaBridge | 163:e59c8e839560 | 3956 | #define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 3957 | #define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3958 | |
| AnnaBridge | 163:e59c8e839560 | 3959 | /* The count of ENET_DMA_CH_DMA_CHX_CTRL */ |
| AnnaBridge | 163:e59c8e839560 | 3960 | #define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3961 | |
| AnnaBridge | 163:e59c8e839560 | 3962 | /*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */ |
| AnnaBridge | 163:e59c8e839560 | 3963 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3964 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3965 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3966 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU) |
| AnnaBridge | 163:e59c8e839560 | 3967 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 3968 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3969 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 3970 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 3971 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3972 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U) |
| AnnaBridge | 163:e59c8e839560 | 3973 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3974 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3975 | |
| AnnaBridge | 163:e59c8e839560 | 3976 | /* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */ |
| AnnaBridge | 163:e59c8e839560 | 3977 | #define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3978 | |
| AnnaBridge | 163:e59c8e839560 | 3979 | /*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */ |
| AnnaBridge | 163:e59c8e839560 | 3980 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 3981 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 3982 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3983 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U) |
| AnnaBridge | 163:e59c8e839560 | 3984 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 3985 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3986 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U) |
| AnnaBridge | 163:e59c8e839560 | 3987 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 3988 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3989 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 3990 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 3991 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 3992 | |
| AnnaBridge | 163:e59c8e839560 | 3993 | /* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */ |
| AnnaBridge | 163:e59c8e839560 | 3994 | #define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3995 | |
| AnnaBridge | 163:e59c8e839560 | 3996 | /*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */ |
| AnnaBridge | 163:e59c8e839560 | 3997 | #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU) |
| AnnaBridge | 163:e59c8e839560 | 3998 | #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 3999 | #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4000 | |
| AnnaBridge | 163:e59c8e839560 | 4001 | /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */ |
| AnnaBridge | 163:e59c8e839560 | 4002 | #define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4003 | |
| AnnaBridge | 163:e59c8e839560 | 4004 | /*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */ |
| AnnaBridge | 163:e59c8e839560 | 4005 | #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU) |
| AnnaBridge | 163:e59c8e839560 | 4006 | #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4007 | #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4008 | |
| AnnaBridge | 163:e59c8e839560 | 4009 | /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */ |
| AnnaBridge | 163:e59c8e839560 | 4010 | #define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4011 | |
| AnnaBridge | 163:e59c8e839560 | 4012 | /*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */ |
| AnnaBridge | 163:e59c8e839560 | 4013 | #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU) |
| AnnaBridge | 163:e59c8e839560 | 4014 | #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4015 | #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4016 | |
| AnnaBridge | 163:e59c8e839560 | 4017 | /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */ |
| AnnaBridge | 163:e59c8e839560 | 4018 | #define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4019 | |
| AnnaBridge | 163:e59c8e839560 | 4020 | /*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */ |
| AnnaBridge | 163:e59c8e839560 | 4021 | #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU) |
| AnnaBridge | 163:e59c8e839560 | 4022 | #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4023 | #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4024 | |
| AnnaBridge | 163:e59c8e839560 | 4025 | /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */ |
| AnnaBridge | 163:e59c8e839560 | 4026 | #define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4027 | |
| AnnaBridge | 163:e59c8e839560 | 4028 | /*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */ |
| AnnaBridge | 163:e59c8e839560 | 4029 | #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) |
| AnnaBridge | 163:e59c8e839560 | 4030 | #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4031 | #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4032 | |
| AnnaBridge | 163:e59c8e839560 | 4033 | /* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */ |
| AnnaBridge | 163:e59c8e839560 | 4034 | #define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4035 | |
| AnnaBridge | 163:e59c8e839560 | 4036 | /*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */ |
| AnnaBridge | 163:e59c8e839560 | 4037 | #define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU) |
| AnnaBridge | 163:e59c8e839560 | 4038 | #define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4039 | #define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4040 | |
| AnnaBridge | 163:e59c8e839560 | 4041 | /* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */ |
| AnnaBridge | 163:e59c8e839560 | 4042 | #define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4043 | |
| AnnaBridge | 163:e59c8e839560 | 4044 | /*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */ |
| AnnaBridge | 163:e59c8e839560 | 4045 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4046 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4047 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4048 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 4049 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 4050 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4051 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 4052 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4053 | #define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4054 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 4055 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4056 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4057 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 4058 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 4059 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4060 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 4061 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 4062 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4063 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 4064 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 4065 | #define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4066 | #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 4067 | #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 4068 | #define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4069 | #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 4070 | #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 4071 | #define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4072 | #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 4073 | #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 4074 | #define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4075 | #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 4076 | #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 4077 | #define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4078 | #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 4079 | #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 4080 | #define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4081 | |
| AnnaBridge | 163:e59c8e839560 | 4082 | /* The count of ENET_DMA_CH_DMA_CHX_INT_EN */ |
| AnnaBridge | 163:e59c8e839560 | 4083 | #define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4084 | |
| AnnaBridge | 163:e59c8e839560 | 4085 | /*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */ |
| AnnaBridge | 163:e59c8e839560 | 4086 | #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 4087 | #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4088 | #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4089 | |
| AnnaBridge | 163:e59c8e839560 | 4090 | /* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */ |
| AnnaBridge | 163:e59c8e839560 | 4091 | #define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4092 | |
| AnnaBridge | 163:e59c8e839560 | 4093 | /*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */ |
| AnnaBridge | 163:e59c8e839560 | 4094 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4095 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4096 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4097 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 4098 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 4099 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4100 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U) |
| AnnaBridge | 163:e59c8e839560 | 4101 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 4102 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4103 | |
| AnnaBridge | 163:e59c8e839560 | 4104 | /* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */ |
| AnnaBridge | 163:e59c8e839560 | 4105 | #define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4106 | |
| AnnaBridge | 163:e59c8e839560 | 4107 | /*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */ |
| AnnaBridge | 163:e59c8e839560 | 4108 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4109 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4110 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4111 | |
| AnnaBridge | 163:e59c8e839560 | 4112 | /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */ |
| AnnaBridge | 163:e59c8e839560 | 4113 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4114 | |
| AnnaBridge | 163:e59c8e839560 | 4115 | /*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - */ |
| AnnaBridge | 163:e59c8e839560 | 4116 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4117 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4118 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4119 | |
| AnnaBridge | 163:e59c8e839560 | 4120 | /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */ |
| AnnaBridge | 163:e59c8e839560 | 4121 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4122 | |
| AnnaBridge | 163:e59c8e839560 | 4123 | /*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - */ |
| AnnaBridge | 163:e59c8e839560 | 4124 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4125 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4126 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4127 | |
| AnnaBridge | 163:e59c8e839560 | 4128 | /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */ |
| AnnaBridge | 163:e59c8e839560 | 4129 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4130 | |
| AnnaBridge | 163:e59c8e839560 | 4131 | /*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */ |
| AnnaBridge | 163:e59c8e839560 | 4132 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4133 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4134 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4135 | |
| AnnaBridge | 163:e59c8e839560 | 4136 | /* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */ |
| AnnaBridge | 163:e59c8e839560 | 4137 | #define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4138 | |
| AnnaBridge | 163:e59c8e839560 | 4139 | /*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */ |
| AnnaBridge | 163:e59c8e839560 | 4140 | #define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4141 | #define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4142 | #define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4143 | #define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 4144 | #define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 4145 | #define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4146 | #define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 4147 | #define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4148 | #define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4149 | #define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 4150 | #define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4151 | #define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4152 | #define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 4153 | #define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 4154 | #define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4155 | #define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 4156 | #define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 4157 | #define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4158 | #define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 4159 | #define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 4160 | #define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4161 | #define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 4162 | #define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 4163 | #define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4164 | #define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 4165 | #define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 4166 | #define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4167 | #define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 4168 | #define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 4169 | #define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4170 | #define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 4171 | #define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 4172 | #define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4173 | #define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 4174 | #define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 4175 | #define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4176 | #define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U) |
| AnnaBridge | 163:e59c8e839560 | 4177 | #define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 4178 | #define ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4179 | |
| AnnaBridge | 163:e59c8e839560 | 4180 | /* The count of ENET_DMA_CH_DMA_CHX_STAT */ |
| AnnaBridge | 163:e59c8e839560 | 4181 | #define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4182 | |
| AnnaBridge | 163:e59c8e839560 | 4183 | |
| AnnaBridge | 163:e59c8e839560 | 4184 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4185 | * @} |
| AnnaBridge | 163:e59c8e839560 | 4186 | */ /* end of group ENET_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 4187 | |
| AnnaBridge | 163:e59c8e839560 | 4188 | |
| AnnaBridge | 163:e59c8e839560 | 4189 | /* ENET - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 4190 | /** Peripheral ENET base address */ |
| AnnaBridge | 163:e59c8e839560 | 4191 | #define ENET_BASE (0x40092000u) |
| AnnaBridge | 163:e59c8e839560 | 4192 | /** Peripheral ENET base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4193 | #define ENET ((ENET_Type *)ENET_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4194 | /** Array initializer of ENET peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 4195 | #define ENET_BASE_ADDRS { ENET_BASE } |
| AnnaBridge | 163:e59c8e839560 | 4196 | /** Array initializer of ENET peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 4197 | #define ENET_BASE_PTRS { ENET } |
| AnnaBridge | 163:e59c8e839560 | 4198 | /** Interrupt vectors for the ENET peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 4199 | #define ENET_IRQS { ETHERNET_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 4200 | #define ENET_PMT_IRQS { ETHERNET_PMT_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 4201 | #define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 4202 | |
| AnnaBridge | 163:e59c8e839560 | 4203 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4204 | * @} |
| AnnaBridge | 163:e59c8e839560 | 4205 | */ /* end of group ENET_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 4206 | |
| AnnaBridge | 163:e59c8e839560 | 4207 | |
| AnnaBridge | 163:e59c8e839560 | 4208 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 4209 | -- FLEXCOMM Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 4210 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 4211 | |
| AnnaBridge | 163:e59c8e839560 | 4212 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4213 | * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 4214 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 4215 | */ |
| AnnaBridge | 163:e59c8e839560 | 4216 | |
| AnnaBridge | 163:e59c8e839560 | 4217 | /** FLEXCOMM - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 4218 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 4219 | uint8_t RESERVED_0[4088]; |
| AnnaBridge | 163:e59c8e839560 | 4220 | __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */ |
| AnnaBridge | 163:e59c8e839560 | 4221 | __IO uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */ |
| AnnaBridge | 163:e59c8e839560 | 4222 | } FLEXCOMM_Type; |
| AnnaBridge | 163:e59c8e839560 | 4223 | |
| AnnaBridge | 163:e59c8e839560 | 4224 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 4225 | -- FLEXCOMM Register Masks |
| AnnaBridge | 163:e59c8e839560 | 4226 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 4227 | |
| AnnaBridge | 163:e59c8e839560 | 4228 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4229 | * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks |
| AnnaBridge | 163:e59c8e839560 | 4230 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 4231 | */ |
| AnnaBridge | 163:e59c8e839560 | 4232 | |
| AnnaBridge | 163:e59c8e839560 | 4233 | /*! @name PSELID - Peripheral Select and Flexcomm ID register. */ |
| AnnaBridge | 163:e59c8e839560 | 4234 | #define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 4235 | #define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4236 | #define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4237 | #define FLEXCOMM_PSELID_LOCK_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 4238 | #define FLEXCOMM_PSELID_LOCK_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 4239 | #define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4240 | #define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 4241 | #define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 4242 | #define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4243 | #define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 4244 | #define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 4245 | #define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4246 | #define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 4247 | #define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4248 | #define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4249 | #define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 4250 | #define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 4251 | #define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4252 | #define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) |
| AnnaBridge | 163:e59c8e839560 | 4253 | #define FLEXCOMM_PSELID_ID_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 4254 | #define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4255 | |
| AnnaBridge | 163:e59c8e839560 | 4256 | /*! @name PID - Peripheral identification register. */ |
| AnnaBridge | 163:e59c8e839560 | 4257 | #define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) |
| AnnaBridge | 163:e59c8e839560 | 4258 | #define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 4259 | #define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4260 | #define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) |
| AnnaBridge | 163:e59c8e839560 | 4261 | #define FLEXCOMM_PID_Major_Rev_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 4262 | #define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4263 | #define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 4264 | #define FLEXCOMM_PID_ID_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 4265 | #define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4266 | |
| AnnaBridge | 163:e59c8e839560 | 4267 | |
| AnnaBridge | 163:e59c8e839560 | 4268 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4269 | * @} |
| AnnaBridge | 163:e59c8e839560 | 4270 | */ /* end of group FLEXCOMM_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 4271 | |
| AnnaBridge | 163:e59c8e839560 | 4272 | |
| AnnaBridge | 163:e59c8e839560 | 4273 | /* FLEXCOMM - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 4274 | /** Peripheral FLEXCOMM0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 4275 | #define FLEXCOMM0_BASE (0x40086000u) |
| AnnaBridge | 163:e59c8e839560 | 4276 | /** Peripheral FLEXCOMM0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4277 | #define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4278 | /** Peripheral FLEXCOMM1 base address */ |
| AnnaBridge | 163:e59c8e839560 | 4279 | #define FLEXCOMM1_BASE (0x40087000u) |
| AnnaBridge | 163:e59c8e839560 | 4280 | /** Peripheral FLEXCOMM1 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4281 | #define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4282 | /** Peripheral FLEXCOMM2 base address */ |
| AnnaBridge | 163:e59c8e839560 | 4283 | #define FLEXCOMM2_BASE (0x40088000u) |
| AnnaBridge | 163:e59c8e839560 | 4284 | /** Peripheral FLEXCOMM2 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4285 | #define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4286 | /** Peripheral FLEXCOMM3 base address */ |
| AnnaBridge | 163:e59c8e839560 | 4287 | #define FLEXCOMM3_BASE (0x40089000u) |
| AnnaBridge | 163:e59c8e839560 | 4288 | /** Peripheral FLEXCOMM3 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4289 | #define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4290 | /** Peripheral FLEXCOMM4 base address */ |
| AnnaBridge | 163:e59c8e839560 | 4291 | #define FLEXCOMM4_BASE (0x4008A000u) |
| AnnaBridge | 163:e59c8e839560 | 4292 | /** Peripheral FLEXCOMM4 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4293 | #define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4294 | /** Peripheral FLEXCOMM5 base address */ |
| AnnaBridge | 163:e59c8e839560 | 4295 | #define FLEXCOMM5_BASE (0x40096000u) |
| AnnaBridge | 163:e59c8e839560 | 4296 | /** Peripheral FLEXCOMM5 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4297 | #define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4298 | /** Peripheral FLEXCOMM6 base address */ |
| AnnaBridge | 163:e59c8e839560 | 4299 | #define FLEXCOMM6_BASE (0x40097000u) |
| AnnaBridge | 163:e59c8e839560 | 4300 | /** Peripheral FLEXCOMM6 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4301 | #define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4302 | /** Peripheral FLEXCOMM7 base address */ |
| AnnaBridge | 163:e59c8e839560 | 4303 | #define FLEXCOMM7_BASE (0x40098000u) |
| AnnaBridge | 163:e59c8e839560 | 4304 | /** Peripheral FLEXCOMM7 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4305 | #define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4306 | /** Peripheral FLEXCOMM8 base address */ |
| AnnaBridge | 163:e59c8e839560 | 4307 | #define FLEXCOMM8_BASE (0x40099000u) |
| AnnaBridge | 163:e59c8e839560 | 4308 | /** Peripheral FLEXCOMM8 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4309 | #define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4310 | /** Peripheral FLEXCOMM9 base address */ |
| AnnaBridge | 163:e59c8e839560 | 4311 | #define FLEXCOMM9_BASE (0x4009A000u) |
| AnnaBridge | 163:e59c8e839560 | 4312 | /** Peripheral FLEXCOMM9 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4313 | #define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4314 | /** Array initializer of FLEXCOMM peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 4315 | #define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE } |
| AnnaBridge | 163:e59c8e839560 | 4316 | /** Array initializer of FLEXCOMM peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 4317 | #define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9 } |
| AnnaBridge | 163:e59c8e839560 | 4318 | /** Interrupt vectors for the FLEXCOMM peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 4319 | #define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 4320 | |
| AnnaBridge | 163:e59c8e839560 | 4321 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4322 | * @} |
| AnnaBridge | 163:e59c8e839560 | 4323 | */ /* end of group FLEXCOMM_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 4324 | |
| AnnaBridge | 163:e59c8e839560 | 4325 | |
| AnnaBridge | 163:e59c8e839560 | 4326 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 4327 | -- FMC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 4328 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 4329 | |
| AnnaBridge | 163:e59c8e839560 | 4330 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4331 | * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 4332 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 4333 | */ |
| AnnaBridge | 163:e59c8e839560 | 4334 | |
| AnnaBridge | 163:e59c8e839560 | 4335 | /** FMC - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 4336 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 4337 | __IO uint32_t FCTR; /**< Control register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 4338 | uint8_t RESERVED_0[12]; |
| AnnaBridge | 163:e59c8e839560 | 4339 | __IO uint32_t FBWST; /**< Wait state register, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 4340 | uint8_t RESERVED_1[12]; |
| AnnaBridge | 163:e59c8e839560 | 4341 | __IO uint32_t FMSSTART; /**< Signature start address register, offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 4342 | __IO uint32_t FMSSTOP; /**< Signature stop-address register, offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 4343 | uint8_t RESERVED_2[4]; |
| AnnaBridge | 163:e59c8e839560 | 4344 | __I uint32_t FMSW[4]; /**< Words of 128-bit signature word, array offset: 0x2C, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4345 | uint8_t RESERVED_3[4004]; |
| AnnaBridge | 163:e59c8e839560 | 4346 | __I uint32_t FMSTAT; /**< Signature generation status register, offset: 0xFE0 */ |
| AnnaBridge | 163:e59c8e839560 | 4347 | uint8_t RESERVED_4[4]; |
| AnnaBridge | 163:e59c8e839560 | 4348 | __O uint32_t FMSTATCLR; /**< Signature generation status clear register, offset: 0xFE8 */ |
| AnnaBridge | 163:e59c8e839560 | 4349 | } FMC_Type; |
| AnnaBridge | 163:e59c8e839560 | 4350 | |
| AnnaBridge | 163:e59c8e839560 | 4351 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 4352 | -- FMC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 4353 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 4354 | |
| AnnaBridge | 163:e59c8e839560 | 4355 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4356 | * @addtogroup FMC_Register_Masks FMC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 4357 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 4358 | */ |
| AnnaBridge | 163:e59c8e839560 | 4359 | |
| AnnaBridge | 163:e59c8e839560 | 4360 | /*! @name FCTR - Control register */ |
| AnnaBridge | 163:e59c8e839560 | 4361 | #define FMC_FCTR_FS_RD0_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 4362 | #define FMC_FCTR_FS_RD0_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 4363 | #define FMC_FCTR_FS_RD0(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD0_SHIFT)) & FMC_FCTR_FS_RD0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4364 | #define FMC_FCTR_FS_RD1_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 4365 | #define FMC_FCTR_FS_RD1_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 4366 | #define FMC_FCTR_FS_RD1(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD1_SHIFT)) & FMC_FCTR_FS_RD1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4367 | |
| AnnaBridge | 163:e59c8e839560 | 4368 | /*! @name FBWST - Wait state register */ |
| AnnaBridge | 163:e59c8e839560 | 4369 | #define FMC_FBWST_WAITSTATES_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 4370 | #define FMC_FBWST_WAITSTATES_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4371 | #define FMC_FBWST_WAITSTATES(x) (((uint32_t)(((uint32_t)(x)) << FMC_FBWST_WAITSTATES_SHIFT)) & FMC_FBWST_WAITSTATES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4372 | |
| AnnaBridge | 163:e59c8e839560 | 4373 | /*! @name FMSSTART - Signature start address register */ |
| AnnaBridge | 163:e59c8e839560 | 4374 | #define FMC_FMSSTART_START_MASK (0x1FFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4375 | #define FMC_FMSSTART_START_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4376 | #define FMC_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTART_START_SHIFT)) & FMC_FMSSTART_START_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4377 | |
| AnnaBridge | 163:e59c8e839560 | 4378 | /*! @name FMSSTOP - Signature stop-address register */ |
| AnnaBridge | 163:e59c8e839560 | 4379 | #define FMC_FMSSTOP_STOP_MASK (0x1FFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4380 | #define FMC_FMSSTOP_STOP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4381 | #define FMC_FMSSTOP_STOP(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_STOP_SHIFT)) & FMC_FMSSTOP_STOP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4382 | #define FMC_FMSSTOP_SIG_START_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 4383 | #define FMC_FMSSTOP_SIG_START_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 4384 | #define FMC_FMSSTOP_SIG_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_SIG_START_SHIFT)) & FMC_FMSSTOP_SIG_START_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4385 | |
| AnnaBridge | 163:e59c8e839560 | 4386 | /*! @name FMSW - Words of 128-bit signature word */ |
| AnnaBridge | 163:e59c8e839560 | 4387 | #define FMC_FMSW_SW_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4388 | #define FMC_FMSW_SW_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4389 | #define FMC_FMSW_SW(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSW_SW_SHIFT)) & FMC_FMSW_SW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4390 | |
| AnnaBridge | 163:e59c8e839560 | 4391 | /* The count of FMC_FMSW */ |
| AnnaBridge | 163:e59c8e839560 | 4392 | #define FMC_FMSW_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 4393 | |
| AnnaBridge | 163:e59c8e839560 | 4394 | /*! @name FMSTAT - Signature generation status register */ |
| AnnaBridge | 163:e59c8e839560 | 4395 | #define FMC_FMSTAT_SIG_DONE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 4396 | #define FMC_FMSTAT_SIG_DONE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4397 | #define FMC_FMSTAT_SIG_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTAT_SIG_DONE_SHIFT)) & FMC_FMSTAT_SIG_DONE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4398 | |
| AnnaBridge | 163:e59c8e839560 | 4399 | /*! @name FMSTATCLR - Signature generation status clear register */ |
| AnnaBridge | 163:e59c8e839560 | 4400 | #define FMC_FMSTATCLR_SIG_DONE_CLR_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 4401 | #define FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4402 | #define FMC_FMSTATCLR_SIG_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FMC_FMSTATCLR_SIG_DONE_CLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4403 | |
| AnnaBridge | 163:e59c8e839560 | 4404 | |
| AnnaBridge | 163:e59c8e839560 | 4405 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4406 | * @} |
| AnnaBridge | 163:e59c8e839560 | 4407 | */ /* end of group FMC_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 4408 | |
| AnnaBridge | 163:e59c8e839560 | 4409 | |
| AnnaBridge | 163:e59c8e839560 | 4410 | /* FMC - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 4411 | /** Peripheral FMC base address */ |
| AnnaBridge | 163:e59c8e839560 | 4412 | #define FMC_BASE (0x40034000u) |
| AnnaBridge | 163:e59c8e839560 | 4413 | /** Peripheral FMC base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4414 | #define FMC ((FMC_Type *)FMC_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4415 | /** Array initializer of FMC peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 4416 | #define FMC_BASE_ADDRS { FMC_BASE } |
| AnnaBridge | 163:e59c8e839560 | 4417 | /** Array initializer of FMC peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 4418 | #define FMC_BASE_PTRS { FMC } |
| AnnaBridge | 163:e59c8e839560 | 4419 | |
| AnnaBridge | 163:e59c8e839560 | 4420 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4421 | * @} |
| AnnaBridge | 163:e59c8e839560 | 4422 | */ /* end of group FMC_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 4423 | |
| AnnaBridge | 163:e59c8e839560 | 4424 | |
| AnnaBridge | 163:e59c8e839560 | 4425 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 4426 | -- GINT Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 4427 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 4428 | |
| AnnaBridge | 163:e59c8e839560 | 4429 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4430 | * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 4431 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 4432 | */ |
| AnnaBridge | 163:e59c8e839560 | 4433 | |
| AnnaBridge | 163:e59c8e839560 | 4434 | /** GINT - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 4435 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 4436 | __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 4437 | uint8_t RESERVED_0[28]; |
| AnnaBridge | 163:e59c8e839560 | 4438 | __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4439 | uint8_t RESERVED_1[24]; |
| AnnaBridge | 163:e59c8e839560 | 4440 | __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4441 | } GINT_Type; |
| AnnaBridge | 163:e59c8e839560 | 4442 | |
| AnnaBridge | 163:e59c8e839560 | 4443 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 4444 | -- GINT Register Masks |
| AnnaBridge | 163:e59c8e839560 | 4445 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 4446 | |
| AnnaBridge | 163:e59c8e839560 | 4447 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4448 | * @addtogroup GINT_Register_Masks GINT Register Masks |
| AnnaBridge | 163:e59c8e839560 | 4449 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 4450 | */ |
| AnnaBridge | 163:e59c8e839560 | 4451 | |
| AnnaBridge | 163:e59c8e839560 | 4452 | /*! @name CTRL - GPIO grouped interrupt control register */ |
| AnnaBridge | 163:e59c8e839560 | 4453 | #define GINT_CTRL_INT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4454 | #define GINT_CTRL_INT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4455 | #define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4456 | #define GINT_CTRL_COMB_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 4457 | #define GINT_CTRL_COMB_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 4458 | #define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4459 | #define GINT_CTRL_TRIG_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 4460 | #define GINT_CTRL_TRIG_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4461 | #define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4462 | |
| AnnaBridge | 163:e59c8e839560 | 4463 | /*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ |
| AnnaBridge | 163:e59c8e839560 | 4464 | #define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4465 | #define GINT_PORT_POL_POL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4466 | #define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4467 | |
| AnnaBridge | 163:e59c8e839560 | 4468 | /* The count of GINT_PORT_POL */ |
| AnnaBridge | 163:e59c8e839560 | 4469 | #define GINT_PORT_POL_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4470 | |
| AnnaBridge | 163:e59c8e839560 | 4471 | /*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ |
| AnnaBridge | 163:e59c8e839560 | 4472 | #define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4473 | #define GINT_PORT_ENA_ENA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4474 | #define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4475 | |
| AnnaBridge | 163:e59c8e839560 | 4476 | /* The count of GINT_PORT_ENA */ |
| AnnaBridge | 163:e59c8e839560 | 4477 | #define GINT_PORT_ENA_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4478 | |
| AnnaBridge | 163:e59c8e839560 | 4479 | |
| AnnaBridge | 163:e59c8e839560 | 4480 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4481 | * @} |
| AnnaBridge | 163:e59c8e839560 | 4482 | */ /* end of group GINT_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 4483 | |
| AnnaBridge | 163:e59c8e839560 | 4484 | |
| AnnaBridge | 163:e59c8e839560 | 4485 | /* GINT - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 4486 | /** Peripheral GINT0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 4487 | #define GINT0_BASE (0x40002000u) |
| AnnaBridge | 163:e59c8e839560 | 4488 | /** Peripheral GINT0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4489 | #define GINT0 ((GINT_Type *)GINT0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4490 | /** Peripheral GINT1 base address */ |
| AnnaBridge | 163:e59c8e839560 | 4491 | #define GINT1_BASE (0x40003000u) |
| AnnaBridge | 163:e59c8e839560 | 4492 | /** Peripheral GINT1 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4493 | #define GINT1 ((GINT_Type *)GINT1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4494 | /** Array initializer of GINT peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 4495 | #define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE } |
| AnnaBridge | 163:e59c8e839560 | 4496 | /** Array initializer of GINT peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 4497 | #define GINT_BASE_PTRS { GINT0, GINT1 } |
| AnnaBridge | 163:e59c8e839560 | 4498 | /** Interrupt vectors for the GINT peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 4499 | #define GINT_IRQS { GINT0_IRQn, GINT1_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 4500 | |
| AnnaBridge | 163:e59c8e839560 | 4501 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4502 | * @} |
| AnnaBridge | 163:e59c8e839560 | 4503 | */ /* end of group GINT_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 4504 | |
| AnnaBridge | 163:e59c8e839560 | 4505 | |
| AnnaBridge | 163:e59c8e839560 | 4506 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 4507 | -- GPIO Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 4508 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 4509 | |
| AnnaBridge | 163:e59c8e839560 | 4510 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4511 | * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 4512 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 4513 | */ |
| AnnaBridge | 163:e59c8e839560 | 4514 | |
| AnnaBridge | 163:e59c8e839560 | 4515 | /** GPIO - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 4516 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 4517 | __IO uint8_t B[6][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ |
| AnnaBridge | 163:e59c8e839560 | 4518 | uint8_t RESERVED_0[3904]; |
| AnnaBridge | 163:e59c8e839560 | 4519 | __IO uint32_t W[6][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4520 | uint8_t RESERVED_1[3328]; |
| AnnaBridge | 163:e59c8e839560 | 4521 | __IO uint32_t DIR[6]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4522 | uint8_t RESERVED_2[104]; |
| AnnaBridge | 163:e59c8e839560 | 4523 | __IO uint32_t MASK[6]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4524 | uint8_t RESERVED_3[104]; |
| AnnaBridge | 163:e59c8e839560 | 4525 | __IO uint32_t PIN[6]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4526 | uint8_t RESERVED_4[104]; |
| AnnaBridge | 163:e59c8e839560 | 4527 | __IO uint32_t MPIN[6]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4528 | uint8_t RESERVED_5[104]; |
| AnnaBridge | 163:e59c8e839560 | 4529 | __IO uint32_t SET[6]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4530 | uint8_t RESERVED_6[104]; |
| AnnaBridge | 163:e59c8e839560 | 4531 | __O uint32_t CLR[6]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4532 | uint8_t RESERVED_7[104]; |
| AnnaBridge | 163:e59c8e839560 | 4533 | __O uint32_t NOT[6]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4534 | uint8_t RESERVED_8[104]; |
| AnnaBridge | 163:e59c8e839560 | 4535 | __O uint32_t DIRSET[6]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4536 | uint8_t RESERVED_9[104]; |
| AnnaBridge | 163:e59c8e839560 | 4537 | __O uint32_t DIRCLR[6]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4538 | uint8_t RESERVED_10[104]; |
| AnnaBridge | 163:e59c8e839560 | 4539 | __O uint32_t DIRNOT[6]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4540 | } GPIO_Type; |
| AnnaBridge | 163:e59c8e839560 | 4541 | |
| AnnaBridge | 163:e59c8e839560 | 4542 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 4543 | -- GPIO Register Masks |
| AnnaBridge | 163:e59c8e839560 | 4544 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 4545 | |
| AnnaBridge | 163:e59c8e839560 | 4546 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4547 | * @addtogroup GPIO_Register_Masks GPIO Register Masks |
| AnnaBridge | 163:e59c8e839560 | 4548 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 4549 | */ |
| AnnaBridge | 163:e59c8e839560 | 4550 | |
| AnnaBridge | 163:e59c8e839560 | 4551 | /*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ |
| AnnaBridge | 163:e59c8e839560 | 4552 | #define GPIO_B_PBYTE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4553 | #define GPIO_B_PBYTE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4554 | #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4555 | |
| AnnaBridge | 163:e59c8e839560 | 4556 | /* The count of GPIO_B */ |
| AnnaBridge | 163:e59c8e839560 | 4557 | #define GPIO_B_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4558 | |
| AnnaBridge | 163:e59c8e839560 | 4559 | /* The count of GPIO_B */ |
| AnnaBridge | 163:e59c8e839560 | 4560 | #define GPIO_B_COUNT2 (32U) |
| AnnaBridge | 163:e59c8e839560 | 4561 | |
| AnnaBridge | 163:e59c8e839560 | 4562 | /*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ |
| AnnaBridge | 163:e59c8e839560 | 4563 | #define GPIO_W_PWORD_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4564 | #define GPIO_W_PWORD_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4565 | #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4566 | |
| AnnaBridge | 163:e59c8e839560 | 4567 | /* The count of GPIO_W */ |
| AnnaBridge | 163:e59c8e839560 | 4568 | #define GPIO_W_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4569 | |
| AnnaBridge | 163:e59c8e839560 | 4570 | /* The count of GPIO_W */ |
| AnnaBridge | 163:e59c8e839560 | 4571 | #define GPIO_W_COUNT2 (32U) |
| AnnaBridge | 163:e59c8e839560 | 4572 | |
| AnnaBridge | 163:e59c8e839560 | 4573 | /*! @name DIR - Direction registers */ |
| AnnaBridge | 163:e59c8e839560 | 4574 | #define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4575 | #define GPIO_DIR_DIRP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4576 | #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4577 | |
| AnnaBridge | 163:e59c8e839560 | 4578 | /* The count of GPIO_DIR */ |
| AnnaBridge | 163:e59c8e839560 | 4579 | #define GPIO_DIR_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4580 | |
| AnnaBridge | 163:e59c8e839560 | 4581 | /*! @name MASK - Mask register */ |
| AnnaBridge | 163:e59c8e839560 | 4582 | #define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4583 | #define GPIO_MASK_MASKP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4584 | #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4585 | |
| AnnaBridge | 163:e59c8e839560 | 4586 | /* The count of GPIO_MASK */ |
| AnnaBridge | 163:e59c8e839560 | 4587 | #define GPIO_MASK_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4588 | |
| AnnaBridge | 163:e59c8e839560 | 4589 | /*! @name PIN - Port pin register */ |
| AnnaBridge | 163:e59c8e839560 | 4590 | #define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4591 | #define GPIO_PIN_PORT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4592 | #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4593 | |
| AnnaBridge | 163:e59c8e839560 | 4594 | /* The count of GPIO_PIN */ |
| AnnaBridge | 163:e59c8e839560 | 4595 | #define GPIO_PIN_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4596 | |
| AnnaBridge | 163:e59c8e839560 | 4597 | /*! @name MPIN - Masked port register */ |
| AnnaBridge | 163:e59c8e839560 | 4598 | #define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4599 | #define GPIO_MPIN_MPORTP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4600 | #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4601 | |
| AnnaBridge | 163:e59c8e839560 | 4602 | /* The count of GPIO_MPIN */ |
| AnnaBridge | 163:e59c8e839560 | 4603 | #define GPIO_MPIN_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4604 | |
| AnnaBridge | 163:e59c8e839560 | 4605 | /*! @name SET - Write: Set register for port Read: output bits for port */ |
| AnnaBridge | 163:e59c8e839560 | 4606 | #define GPIO_SET_SETP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4607 | #define GPIO_SET_SETP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4608 | #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4609 | |
| AnnaBridge | 163:e59c8e839560 | 4610 | /* The count of GPIO_SET */ |
| AnnaBridge | 163:e59c8e839560 | 4611 | #define GPIO_SET_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4612 | |
| AnnaBridge | 163:e59c8e839560 | 4613 | /*! @name CLR - Clear port */ |
| AnnaBridge | 163:e59c8e839560 | 4614 | #define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4615 | #define GPIO_CLR_CLRP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4616 | #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4617 | |
| AnnaBridge | 163:e59c8e839560 | 4618 | /* The count of GPIO_CLR */ |
| AnnaBridge | 163:e59c8e839560 | 4619 | #define GPIO_CLR_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4620 | |
| AnnaBridge | 163:e59c8e839560 | 4621 | /*! @name NOT - Toggle port */ |
| AnnaBridge | 163:e59c8e839560 | 4622 | #define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4623 | #define GPIO_NOT_NOTP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4624 | #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4625 | |
| AnnaBridge | 163:e59c8e839560 | 4626 | /* The count of GPIO_NOT */ |
| AnnaBridge | 163:e59c8e839560 | 4627 | #define GPIO_NOT_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4628 | |
| AnnaBridge | 163:e59c8e839560 | 4629 | /*! @name DIRSET - Set pin direction bits for port */ |
| AnnaBridge | 163:e59c8e839560 | 4630 | #define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4631 | #define GPIO_DIRSET_DIRSETP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4632 | #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4633 | |
| AnnaBridge | 163:e59c8e839560 | 4634 | /* The count of GPIO_DIRSET */ |
| AnnaBridge | 163:e59c8e839560 | 4635 | #define GPIO_DIRSET_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4636 | |
| AnnaBridge | 163:e59c8e839560 | 4637 | /*! @name DIRCLR - Clear pin direction bits for port */ |
| AnnaBridge | 163:e59c8e839560 | 4638 | #define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4639 | #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4640 | #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4641 | |
| AnnaBridge | 163:e59c8e839560 | 4642 | /* The count of GPIO_DIRCLR */ |
| AnnaBridge | 163:e59c8e839560 | 4643 | #define GPIO_DIRCLR_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4644 | |
| AnnaBridge | 163:e59c8e839560 | 4645 | /*! @name DIRNOT - Toggle pin direction bits for port */ |
| AnnaBridge | 163:e59c8e839560 | 4646 | #define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4647 | #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4648 | #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4649 | |
| AnnaBridge | 163:e59c8e839560 | 4650 | /* The count of GPIO_DIRNOT */ |
| AnnaBridge | 163:e59c8e839560 | 4651 | #define GPIO_DIRNOT_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4652 | |
| AnnaBridge | 163:e59c8e839560 | 4653 | |
| AnnaBridge | 163:e59c8e839560 | 4654 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4655 | * @} |
| AnnaBridge | 163:e59c8e839560 | 4656 | */ /* end of group GPIO_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 4657 | |
| AnnaBridge | 163:e59c8e839560 | 4658 | |
| AnnaBridge | 163:e59c8e839560 | 4659 | /* GPIO - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 4660 | /** Peripheral GPIO base address */ |
| AnnaBridge | 163:e59c8e839560 | 4661 | #define GPIO_BASE (0x4008C000u) |
| AnnaBridge | 163:e59c8e839560 | 4662 | /** Peripheral GPIO base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 4663 | #define GPIO ((GPIO_Type *)GPIO_BASE) |
| AnnaBridge | 163:e59c8e839560 | 4664 | /** Array initializer of GPIO peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 4665 | #define GPIO_BASE_ADDRS { GPIO_BASE } |
| AnnaBridge | 163:e59c8e839560 | 4666 | /** Array initializer of GPIO peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 4667 | #define GPIO_BASE_PTRS { GPIO } |
| AnnaBridge | 163:e59c8e839560 | 4668 | |
| AnnaBridge | 163:e59c8e839560 | 4669 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4670 | * @} |
| AnnaBridge | 163:e59c8e839560 | 4671 | */ /* end of group GPIO_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 4672 | |
| AnnaBridge | 163:e59c8e839560 | 4673 | |
| AnnaBridge | 163:e59c8e839560 | 4674 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 4675 | -- I2C Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 4676 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 4677 | |
| AnnaBridge | 163:e59c8e839560 | 4678 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4679 | * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 4680 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 4681 | */ |
| AnnaBridge | 163:e59c8e839560 | 4682 | |
| AnnaBridge | 163:e59c8e839560 | 4683 | /** I2C - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 4684 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 4685 | uint8_t RESERVED_0[2048]; |
| AnnaBridge | 163:e59c8e839560 | 4686 | __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */ |
| AnnaBridge | 163:e59c8e839560 | 4687 | __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */ |
| AnnaBridge | 163:e59c8e839560 | 4688 | __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */ |
| AnnaBridge | 163:e59c8e839560 | 4689 | __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */ |
| AnnaBridge | 163:e59c8e839560 | 4690 | __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */ |
| AnnaBridge | 163:e59c8e839560 | 4691 | __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */ |
| AnnaBridge | 163:e59c8e839560 | 4692 | __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */ |
| AnnaBridge | 163:e59c8e839560 | 4693 | uint8_t RESERVED_1[4]; |
| AnnaBridge | 163:e59c8e839560 | 4694 | __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */ |
| AnnaBridge | 163:e59c8e839560 | 4695 | __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */ |
| AnnaBridge | 163:e59c8e839560 | 4696 | __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */ |
| AnnaBridge | 163:e59c8e839560 | 4697 | uint8_t RESERVED_2[20]; |
| AnnaBridge | 163:e59c8e839560 | 4698 | __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */ |
| AnnaBridge | 163:e59c8e839560 | 4699 | __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */ |
| AnnaBridge | 163:e59c8e839560 | 4700 | __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 4701 | __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */ |
| AnnaBridge | 163:e59c8e839560 | 4702 | uint8_t RESERVED_3[36]; |
| AnnaBridge | 163:e59c8e839560 | 4703 | __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */ |
| AnnaBridge | 163:e59c8e839560 | 4704 | uint8_t RESERVED_4[1912]; |
| AnnaBridge | 163:e59c8e839560 | 4705 | __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ |
| AnnaBridge | 163:e59c8e839560 | 4706 | } I2C_Type; |
| AnnaBridge | 163:e59c8e839560 | 4707 | |
| AnnaBridge | 163:e59c8e839560 | 4708 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 4709 | -- I2C Register Masks |
| AnnaBridge | 163:e59c8e839560 | 4710 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 4711 | |
| AnnaBridge | 163:e59c8e839560 | 4712 | /*! |
| AnnaBridge | 163:e59c8e839560 | 4713 | * @addtogroup I2C_Register_Masks I2C Register Masks |
| AnnaBridge | 163:e59c8e839560 | 4714 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 4715 | */ |
| AnnaBridge | 163:e59c8e839560 | 4716 | |
| AnnaBridge | 163:e59c8e839560 | 4717 | /*! @name CFG - Configuration for shared functions. */ |
| AnnaBridge | 163:e59c8e839560 | 4718 | #define I2C_CFG_MSTEN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4719 | #define I2C_CFG_MSTEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4720 | #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4721 | #define I2C_CFG_SLVEN_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 4722 | #define I2C_CFG_SLVEN_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 4723 | #define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4724 | #define I2C_CFG_MONEN_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 4725 | #define I2C_CFG_MONEN_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4726 | #define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4727 | #define I2C_CFG_TIMEOUTEN_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 4728 | #define I2C_CFG_TIMEOUTEN_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 4729 | #define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4730 | #define I2C_CFG_MONCLKSTR_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 4731 | #define I2C_CFG_MONCLKSTR_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 4732 | #define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4733 | #define I2C_CFG_HSCAPABLE_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 4734 | #define I2C_CFG_HSCAPABLE_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 4735 | #define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4736 | |
| AnnaBridge | 163:e59c8e839560 | 4737 | /*! @name STAT - Status register for Master, Slave, and Monitor functions. */ |
| AnnaBridge | 163:e59c8e839560 | 4738 | #define I2C_STAT_MSTPENDING_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4739 | #define I2C_STAT_MSTPENDING_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4740 | #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4741 | #define I2C_STAT_MSTSTATE_MASK (0xEU) |
| AnnaBridge | 163:e59c8e839560 | 4742 | #define I2C_STAT_MSTSTATE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 4743 | #define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4744 | #define I2C_STAT_MSTARBLOSS_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 4745 | #define I2C_STAT_MSTARBLOSS_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 4746 | #define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4747 | #define I2C_STAT_MSTSTSTPERR_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 4748 | #define I2C_STAT_MSTSTSTPERR_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4749 | #define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4750 | #define I2C_STAT_SLVPENDING_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 4751 | #define I2C_STAT_SLVPENDING_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 4752 | #define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4753 | #define I2C_STAT_SLVSTATE_MASK (0x600U) |
| AnnaBridge | 163:e59c8e839560 | 4754 | #define I2C_STAT_SLVSTATE_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 4755 | #define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4756 | #define I2C_STAT_SLVNOTSTR_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 4757 | #define I2C_STAT_SLVNOTSTR_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 4758 | #define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4759 | #define I2C_STAT_SLVIDX_MASK (0x3000U) |
| AnnaBridge | 163:e59c8e839560 | 4760 | #define I2C_STAT_SLVIDX_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 4761 | #define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4762 | #define I2C_STAT_SLVSEL_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 4763 | #define I2C_STAT_SLVSEL_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 4764 | #define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4765 | #define I2C_STAT_SLVDESEL_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 4766 | #define I2C_STAT_SLVDESEL_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 4767 | #define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4768 | #define I2C_STAT_MONRDY_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 4769 | #define I2C_STAT_MONRDY_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 4770 | #define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4771 | #define I2C_STAT_MONOV_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 4772 | #define I2C_STAT_MONOV_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 4773 | #define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4774 | #define I2C_STAT_MONACTIVE_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 4775 | #define I2C_STAT_MONACTIVE_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 4776 | #define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4777 | #define I2C_STAT_MONIDLE_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 4778 | #define I2C_STAT_MONIDLE_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 4779 | #define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4780 | #define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 4781 | #define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 4782 | #define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4783 | #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 4784 | #define I2C_STAT_SCLTIMEOUT_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 4785 | #define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4786 | |
| AnnaBridge | 163:e59c8e839560 | 4787 | /*! @name INTENSET - Interrupt Enable Set and read register. */ |
| AnnaBridge | 163:e59c8e839560 | 4788 | #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4789 | #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4790 | #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4791 | #define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 4792 | #define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 4793 | #define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4794 | #define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 4795 | #define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4796 | #define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4797 | #define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 4798 | #define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 4799 | #define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4800 | #define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 4801 | #define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 4802 | #define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4803 | #define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 4804 | #define I2C_INTENSET_SLVDESELEN_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 4805 | #define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4806 | #define I2C_INTENSET_MONRDYEN_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 4807 | #define I2C_INTENSET_MONRDYEN_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 4808 | #define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4809 | #define I2C_INTENSET_MONOVEN_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 4810 | #define I2C_INTENSET_MONOVEN_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 4811 | #define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4812 | #define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 4813 | #define I2C_INTENSET_MONIDLEEN_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 4814 | #define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4815 | #define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 4816 | #define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 4817 | #define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4818 | #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 4819 | #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 4820 | #define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4821 | |
| AnnaBridge | 163:e59c8e839560 | 4822 | /*! @name INTENCLR - Interrupt Enable Clear register. */ |
| AnnaBridge | 163:e59c8e839560 | 4823 | #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4824 | #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4825 | #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4826 | #define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 4827 | #define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 4828 | #define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4829 | #define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 4830 | #define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4831 | #define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4832 | #define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 4833 | #define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 4834 | #define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4835 | #define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 4836 | #define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 4837 | #define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4838 | #define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 4839 | #define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 4840 | #define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4841 | #define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 4842 | #define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 4843 | #define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4844 | #define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 4845 | #define I2C_INTENCLR_MONOVCLR_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 4846 | #define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4847 | #define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 4848 | #define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 4849 | #define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4850 | #define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 4851 | #define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 4852 | #define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4853 | #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 4854 | #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 4855 | #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4856 | |
| AnnaBridge | 163:e59c8e839560 | 4857 | /*! @name TIMEOUT - Time-out value register. */ |
| AnnaBridge | 163:e59c8e839560 | 4858 | #define I2C_TIMEOUT_TOMIN_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 4859 | #define I2C_TIMEOUT_TOMIN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4860 | #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4861 | #define I2C_TIMEOUT_TO_MASK (0xFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 4862 | #define I2C_TIMEOUT_TO_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 4863 | #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4864 | |
| AnnaBridge | 163:e59c8e839560 | 4865 | /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ |
| AnnaBridge | 163:e59c8e839560 | 4866 | #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 4867 | #define I2C_CLKDIV_DIVVAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4868 | #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4869 | |
| AnnaBridge | 163:e59c8e839560 | 4870 | /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ |
| AnnaBridge | 163:e59c8e839560 | 4871 | #define I2C_INTSTAT_MSTPENDING_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4872 | #define I2C_INTSTAT_MSTPENDING_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4873 | #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4874 | #define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 4875 | #define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 4876 | #define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4877 | #define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 4878 | #define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 4879 | #define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4880 | #define I2C_INTSTAT_SLVPENDING_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 4881 | #define I2C_INTSTAT_SLVPENDING_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 4882 | #define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4883 | #define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 4884 | #define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 4885 | #define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4886 | #define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 4887 | #define I2C_INTSTAT_SLVDESEL_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 4888 | #define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4889 | #define I2C_INTSTAT_MONRDY_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 4890 | #define I2C_INTSTAT_MONRDY_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 4891 | #define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4892 | #define I2C_INTSTAT_MONOV_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 4893 | #define I2C_INTSTAT_MONOV_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 4894 | #define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4895 | #define I2C_INTSTAT_MONIDLE_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 4896 | #define I2C_INTSTAT_MONIDLE_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 4897 | #define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4898 | #define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 4899 | #define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 4900 | #define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4901 | #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 4902 | #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 4903 | #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4904 | |
| AnnaBridge | 163:e59c8e839560 | 4905 | /*! @name MSTCTL - Master control register. */ |
| AnnaBridge | 163:e59c8e839560 | 4906 | #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4907 | #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4908 | #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4909 | #define I2C_MSTCTL_MSTSTART_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 4910 | #define I2C_MSTCTL_MSTSTART_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 4911 | #define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4912 | #define I2C_MSTCTL_MSTSTOP_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 4913 | #define I2C_MSTCTL_MSTSTOP_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 4914 | #define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4915 | #define I2C_MSTCTL_MSTDMA_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 4916 | #define I2C_MSTCTL_MSTDMA_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 4917 | #define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4918 | |
| AnnaBridge | 163:e59c8e839560 | 4919 | /*! @name MSTTIME - Master timing configuration. */ |
| AnnaBridge | 163:e59c8e839560 | 4920 | #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 4921 | #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4922 | #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4923 | #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) |
| AnnaBridge | 163:e59c8e839560 | 4924 | #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 4925 | #define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4926 | |
| AnnaBridge | 163:e59c8e839560 | 4927 | /*! @name MSTDAT - Combined Master receiver and transmitter data register. */ |
| AnnaBridge | 163:e59c8e839560 | 4928 | #define I2C_MSTDAT_DATA_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 4929 | #define I2C_MSTDAT_DATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4930 | #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4931 | |
| AnnaBridge | 163:e59c8e839560 | 4932 | /*! @name SLVCTL - Slave control register. */ |
| AnnaBridge | 163:e59c8e839560 | 4933 | #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4934 | #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4935 | #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4936 | #define I2C_SLVCTL_SLVNACK_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 4937 | #define I2C_SLVCTL_SLVNACK_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 4938 | #define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4939 | #define I2C_SLVCTL_SLVDMA_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 4940 | #define I2C_SLVCTL_SLVDMA_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 4941 | #define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4942 | #define I2C_SLVCTL_AUTOACK_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 4943 | #define I2C_SLVCTL_AUTOACK_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 4944 | #define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4945 | #define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 4946 | #define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 4947 | #define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4948 | |
| AnnaBridge | 163:e59c8e839560 | 4949 | /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ |
| AnnaBridge | 163:e59c8e839560 | 4950 | #define I2C_SLVDAT_DATA_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 4951 | #define I2C_SLVDAT_DATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4952 | #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4953 | |
| AnnaBridge | 163:e59c8e839560 | 4954 | /*! @name SLVADR - Slave address register. */ |
| AnnaBridge | 163:e59c8e839560 | 4955 | #define I2C_SLVADR_SADISABLE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4956 | #define I2C_SLVADR_SADISABLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4957 | #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4958 | #define I2C_SLVADR_SLVADR_MASK (0xFEU) |
| AnnaBridge | 163:e59c8e839560 | 4959 | #define I2C_SLVADR_SLVADR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 4960 | #define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4961 | #define I2C_SLVADR_AUTONACK_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 4962 | #define I2C_SLVADR_AUTONACK_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 4963 | #define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4964 | |
| AnnaBridge | 163:e59c8e839560 | 4965 | /* The count of I2C_SLVADR */ |
| AnnaBridge | 163:e59c8e839560 | 4966 | #define I2C_SLVADR_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 4967 | |
| AnnaBridge | 163:e59c8e839560 | 4968 | /*! @name SLVQUAL0 - Slave Qualification for address 0. */ |
| AnnaBridge | 163:e59c8e839560 | 4969 | #define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 4970 | #define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4971 | #define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4972 | #define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) |
| AnnaBridge | 163:e59c8e839560 | 4973 | #define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 4974 | #define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4975 | |
| AnnaBridge | 163:e59c8e839560 | 4976 | /*! @name MONRXDAT - Monitor receiver data register. */ |
| AnnaBridge | 163:e59c8e839560 | 4977 | #define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 4978 | #define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4979 | #define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4980 | #define I2C_MONRXDAT_MONSTART_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 4981 | #define I2C_MONRXDAT_MONSTART_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 4982 | #define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4983 | #define I2C_MONRXDAT_MONRESTART_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 4984 | #define I2C_MONRXDAT_MONRESTART_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 4985 | #define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4986 | #define I2C_MONRXDAT_MONNACK_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 4987 | #define I2C_MONRXDAT_MONNACK_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 4988 | #define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4989 | |
| AnnaBridge | 163:e59c8e839560 | 4990 | /*! @name ID - Peripheral identification register. */ |
| AnnaBridge | 163:e59c8e839560 | 4991 | #define I2C_ID_APERTURE_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 4992 | #define I2C_ID_APERTURE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 4993 | #define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4994 | #define I2C_ID_MINOR_REV_MASK (0xF00U) |
| AnnaBridge | 163:e59c8e839560 | 4995 | #define I2C_ID_MINOR_REV_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 4996 | #define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 4997 | #define I2C_ID_MAJOR_REV_MASK (0xF000U) |
| AnnaBridge | 163:e59c8e839560 | 4998 | #define I2C_ID_MAJOR_REV_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 4999 | #define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5000 | #define I2C_ID_ID_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 5001 | #define I2C_ID_ID_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5002 | #define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5003 | |
| AnnaBridge | 163:e59c8e839560 | 5004 | |
| AnnaBridge | 163:e59c8e839560 | 5005 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5006 | * @} |
| AnnaBridge | 163:e59c8e839560 | 5007 | */ /* end of group I2C_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 5008 | |
| AnnaBridge | 163:e59c8e839560 | 5009 | |
| AnnaBridge | 163:e59c8e839560 | 5010 | /* I2C - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 5011 | /** Peripheral I2C0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 5012 | #define I2C0_BASE (0x40086000u) |
| AnnaBridge | 163:e59c8e839560 | 5013 | /** Peripheral I2C0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5014 | #define I2C0 ((I2C_Type *)I2C0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5015 | /** Peripheral I2C1 base address */ |
| AnnaBridge | 163:e59c8e839560 | 5016 | #define I2C1_BASE (0x40087000u) |
| AnnaBridge | 163:e59c8e839560 | 5017 | /** Peripheral I2C1 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5018 | #define I2C1 ((I2C_Type *)I2C1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5019 | /** Peripheral I2C2 base address */ |
| AnnaBridge | 163:e59c8e839560 | 5020 | #define I2C2_BASE (0x40088000u) |
| AnnaBridge | 163:e59c8e839560 | 5021 | /** Peripheral I2C2 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5022 | #define I2C2 ((I2C_Type *)I2C2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5023 | /** Peripheral I2C3 base address */ |
| AnnaBridge | 163:e59c8e839560 | 5024 | #define I2C3_BASE (0x40089000u) |
| AnnaBridge | 163:e59c8e839560 | 5025 | /** Peripheral I2C3 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5026 | #define I2C3 ((I2C_Type *)I2C3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5027 | /** Peripheral I2C4 base address */ |
| AnnaBridge | 163:e59c8e839560 | 5028 | #define I2C4_BASE (0x4008A000u) |
| AnnaBridge | 163:e59c8e839560 | 5029 | /** Peripheral I2C4 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5030 | #define I2C4 ((I2C_Type *)I2C4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5031 | /** Peripheral I2C5 base address */ |
| AnnaBridge | 163:e59c8e839560 | 5032 | #define I2C5_BASE (0x40096000u) |
| AnnaBridge | 163:e59c8e839560 | 5033 | /** Peripheral I2C5 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5034 | #define I2C5 ((I2C_Type *)I2C5_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5035 | /** Peripheral I2C6 base address */ |
| AnnaBridge | 163:e59c8e839560 | 5036 | #define I2C6_BASE (0x40097000u) |
| AnnaBridge | 163:e59c8e839560 | 5037 | /** Peripheral I2C6 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5038 | #define I2C6 ((I2C_Type *)I2C6_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5039 | /** Peripheral I2C7 base address */ |
| AnnaBridge | 163:e59c8e839560 | 5040 | #define I2C7_BASE (0x40098000u) |
| AnnaBridge | 163:e59c8e839560 | 5041 | /** Peripheral I2C7 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5042 | #define I2C7 ((I2C_Type *)I2C7_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5043 | /** Peripheral I2C8 base address */ |
| AnnaBridge | 163:e59c8e839560 | 5044 | #define I2C8_BASE (0x40099000u) |
| AnnaBridge | 163:e59c8e839560 | 5045 | /** Peripheral I2C8 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5046 | #define I2C8 ((I2C_Type *)I2C8_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5047 | /** Peripheral I2C9 base address */ |
| AnnaBridge | 163:e59c8e839560 | 5048 | #define I2C9_BASE (0x4009A000u) |
| AnnaBridge | 163:e59c8e839560 | 5049 | /** Peripheral I2C9 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5050 | #define I2C9 ((I2C_Type *)I2C9_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5051 | /** Array initializer of I2C peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 5052 | #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE } |
| AnnaBridge | 163:e59c8e839560 | 5053 | /** Array initializer of I2C peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 5054 | #define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 } |
| AnnaBridge | 163:e59c8e839560 | 5055 | /** Interrupt vectors for the I2C peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 5056 | #define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 5057 | |
| AnnaBridge | 163:e59c8e839560 | 5058 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5059 | * @} |
| AnnaBridge | 163:e59c8e839560 | 5060 | */ /* end of group I2C_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 5061 | |
| AnnaBridge | 163:e59c8e839560 | 5062 | |
| AnnaBridge | 163:e59c8e839560 | 5063 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 5064 | -- I2S Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 5065 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 5066 | |
| AnnaBridge | 163:e59c8e839560 | 5067 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5068 | * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 5069 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 5070 | */ |
| AnnaBridge | 163:e59c8e839560 | 5071 | |
| AnnaBridge | 163:e59c8e839560 | 5072 | /** I2S - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 5073 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 5074 | uint8_t RESERVED_0[32]; |
| AnnaBridge | 163:e59c8e839560 | 5075 | struct { /* offset: 0x20, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 5076 | __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0x20, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 5077 | __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0x24, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 5078 | __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0x28, array step: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 5079 | uint8_t RESERVED_0[20]; |
| AnnaBridge | 163:e59c8e839560 | 5080 | } SECCHANNEL[3]; |
| AnnaBridge | 163:e59c8e839560 | 5081 | uint8_t RESERVED_1[2944]; |
| AnnaBridge | 163:e59c8e839560 | 5082 | __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */ |
| AnnaBridge | 163:e59c8e839560 | 5083 | __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */ |
| AnnaBridge | 163:e59c8e839560 | 5084 | __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ |
| AnnaBridge | 163:e59c8e839560 | 5085 | uint8_t RESERVED_2[16]; |
| AnnaBridge | 163:e59c8e839560 | 5086 | __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ |
| AnnaBridge | 163:e59c8e839560 | 5087 | uint8_t RESERVED_3[480]; |
| AnnaBridge | 163:e59c8e839560 | 5088 | __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ |
| AnnaBridge | 163:e59c8e839560 | 5089 | __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ |
| AnnaBridge | 163:e59c8e839560 | 5090 | __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ |
| AnnaBridge | 163:e59c8e839560 | 5091 | uint8_t RESERVED_4[4]; |
| AnnaBridge | 163:e59c8e839560 | 5092 | __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ |
| AnnaBridge | 163:e59c8e839560 | 5093 | __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ |
| AnnaBridge | 163:e59c8e839560 | 5094 | __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ |
| AnnaBridge | 163:e59c8e839560 | 5095 | uint8_t RESERVED_5[4]; |
| AnnaBridge | 163:e59c8e839560 | 5096 | __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ |
| AnnaBridge | 163:e59c8e839560 | 5097 | __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */ |
| AnnaBridge | 163:e59c8e839560 | 5098 | uint8_t RESERVED_6[8]; |
| AnnaBridge | 163:e59c8e839560 | 5099 | __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ |
| AnnaBridge | 163:e59c8e839560 | 5100 | __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */ |
| AnnaBridge | 163:e59c8e839560 | 5101 | uint8_t RESERVED_7[8]; |
| AnnaBridge | 163:e59c8e839560 | 5102 | __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ |
| AnnaBridge | 163:e59c8e839560 | 5103 | __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ |
| AnnaBridge | 163:e59c8e839560 | 5104 | uint8_t RESERVED_8[4020]; |
| AnnaBridge | 163:e59c8e839560 | 5105 | __I uint32_t ID; /**< I2S Module identification, offset: 0x1DFC */ |
| AnnaBridge | 163:e59c8e839560 | 5106 | } I2S_Type; |
| AnnaBridge | 163:e59c8e839560 | 5107 | |
| AnnaBridge | 163:e59c8e839560 | 5108 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 5109 | -- I2S Register Masks |
| AnnaBridge | 163:e59c8e839560 | 5110 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 5111 | |
| AnnaBridge | 163:e59c8e839560 | 5112 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5113 | * @addtogroup I2S_Register_Masks I2S Register Masks |
| AnnaBridge | 163:e59c8e839560 | 5114 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 5115 | */ |
| AnnaBridge | 163:e59c8e839560 | 5116 | |
| AnnaBridge | 163:e59c8e839560 | 5117 | /*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */ |
| AnnaBridge | 163:e59c8e839560 | 5118 | #define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5119 | #define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5120 | #define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5121 | #define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 5122 | #define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 5123 | #define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5124 | |
| AnnaBridge | 163:e59c8e839560 | 5125 | /* The count of I2S_SECCHANNEL_PCFG1 */ |
| AnnaBridge | 163:e59c8e839560 | 5126 | #define I2S_SECCHANNEL_PCFG1_COUNT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5127 | |
| AnnaBridge | 163:e59c8e839560 | 5128 | /*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */ |
| AnnaBridge | 163:e59c8e839560 | 5129 | #define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) |
| AnnaBridge | 163:e59c8e839560 | 5130 | #define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5131 | #define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5132 | |
| AnnaBridge | 163:e59c8e839560 | 5133 | /* The count of I2S_SECCHANNEL_PCFG2 */ |
| AnnaBridge | 163:e59c8e839560 | 5134 | #define I2S_SECCHANNEL_PCFG2_COUNT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5135 | |
| AnnaBridge | 163:e59c8e839560 | 5136 | /*! @name SECCHANNEL_PSTAT - Status register for channel pair */ |
| AnnaBridge | 163:e59c8e839560 | 5137 | #define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5138 | #define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5139 | #define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5140 | #define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5141 | #define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5142 | #define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5143 | #define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 5144 | #define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 5145 | #define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5146 | #define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 5147 | #define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5148 | #define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5149 | |
| AnnaBridge | 163:e59c8e839560 | 5150 | /* The count of I2S_SECCHANNEL_PSTAT */ |
| AnnaBridge | 163:e59c8e839560 | 5151 | #define I2S_SECCHANNEL_PSTAT_COUNT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5152 | |
| AnnaBridge | 163:e59c8e839560 | 5153 | /*! @name CFG1 - Configuration register 1 for the primary channel pair. */ |
| AnnaBridge | 163:e59c8e839560 | 5154 | #define I2S_CFG1_MAINENABLE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5155 | #define I2S_CFG1_MAINENABLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5156 | #define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5157 | #define I2S_CFG1_DATAPAUSE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5158 | #define I2S_CFG1_DATAPAUSE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5159 | #define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5160 | #define I2S_CFG1_PAIRCOUNT_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 5161 | #define I2S_CFG1_PAIRCOUNT_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 5162 | #define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5163 | #define I2S_CFG1_MSTSLVCFG_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 5164 | #define I2S_CFG1_MSTSLVCFG_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5165 | #define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5166 | #define I2S_CFG1_MODE_MASK (0xC0U) |
| AnnaBridge | 163:e59c8e839560 | 5167 | #define I2S_CFG1_MODE_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 5168 | #define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5169 | #define I2S_CFG1_RIGHTLOW_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 5170 | #define I2S_CFG1_RIGHTLOW_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 5171 | #define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5172 | #define I2S_CFG1_LEFTJUST_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 5173 | #define I2S_CFG1_LEFTJUST_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 5174 | #define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5175 | #define I2S_CFG1_ONECHANNEL_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 5176 | #define I2S_CFG1_ONECHANNEL_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 5177 | #define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5178 | #define I2S_CFG1_PDMDATA_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 5179 | #define I2S_CFG1_PDMDATA_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 5180 | #define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5181 | #define I2S_CFG1_SCK_POL_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 5182 | #define I2S_CFG1_SCK_POL_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 5183 | #define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5184 | #define I2S_CFG1_WS_POL_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 5185 | #define I2S_CFG1_WS_POL_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 5186 | #define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5187 | #define I2S_CFG1_DATALEN_MASK (0x1F0000U) |
| AnnaBridge | 163:e59c8e839560 | 5188 | #define I2S_CFG1_DATALEN_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5189 | #define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5190 | |
| AnnaBridge | 163:e59c8e839560 | 5191 | /*! @name CFG2 - Configuration register 2 for the primary channel pair. */ |
| AnnaBridge | 163:e59c8e839560 | 5192 | #define I2S_CFG2_FRAMELEN_MASK (0x1FFU) |
| AnnaBridge | 163:e59c8e839560 | 5193 | #define I2S_CFG2_FRAMELEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5194 | #define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5195 | #define I2S_CFG2_POSITION_MASK (0x1FF0000U) |
| AnnaBridge | 163:e59c8e839560 | 5196 | #define I2S_CFG2_POSITION_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5197 | #define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5198 | |
| AnnaBridge | 163:e59c8e839560 | 5199 | /*! @name STAT - Status register for the primary channel pair. */ |
| AnnaBridge | 163:e59c8e839560 | 5200 | #define I2S_STAT_BUSY_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5201 | #define I2S_STAT_BUSY_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5202 | #define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5203 | #define I2S_STAT_SLVFRMERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5204 | #define I2S_STAT_SLVFRMERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5205 | #define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5206 | #define I2S_STAT_LR_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 5207 | #define I2S_STAT_LR_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 5208 | #define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5209 | #define I2S_STAT_DATAPAUSED_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 5210 | #define I2S_STAT_DATAPAUSED_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5211 | #define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5212 | |
| AnnaBridge | 163:e59c8e839560 | 5213 | /*! @name DIV - Clock divider, used by all channel pairs. */ |
| AnnaBridge | 163:e59c8e839560 | 5214 | #define I2S_DIV_DIV_MASK (0xFFFU) |
| AnnaBridge | 163:e59c8e839560 | 5215 | #define I2S_DIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5216 | #define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5217 | |
| AnnaBridge | 163:e59c8e839560 | 5218 | /*! @name FIFOCFG - FIFO configuration and enable register. */ |
| AnnaBridge | 163:e59c8e839560 | 5219 | #define I2S_FIFOCFG_ENABLETX_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5220 | #define I2S_FIFOCFG_ENABLETX_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5221 | #define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5222 | #define I2S_FIFOCFG_ENABLERX_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5223 | #define I2S_FIFOCFG_ENABLERX_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5224 | #define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5225 | #define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 5226 | #define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 5227 | #define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5228 | #define I2S_FIFOCFG_PACK48_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 5229 | #define I2S_FIFOCFG_PACK48_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5230 | #define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5231 | #define I2S_FIFOCFG_SIZE_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 5232 | #define I2S_FIFOCFG_SIZE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5233 | #define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5234 | #define I2S_FIFOCFG_DMATX_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 5235 | #define I2S_FIFOCFG_DMATX_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 5236 | #define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5237 | #define I2S_FIFOCFG_DMARX_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 5238 | #define I2S_FIFOCFG_DMARX_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 5239 | #define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5240 | #define I2S_FIFOCFG_WAKETX_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 5241 | #define I2S_FIFOCFG_WAKETX_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 5242 | #define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5243 | #define I2S_FIFOCFG_WAKERX_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 5244 | #define I2S_FIFOCFG_WAKERX_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 5245 | #define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5246 | #define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 5247 | #define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5248 | #define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5249 | #define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 5250 | #define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 5251 | #define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5252 | #define I2S_FIFOCFG_POPDBG_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 5253 | #define I2S_FIFOCFG_POPDBG_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 5254 | #define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5255 | |
| AnnaBridge | 163:e59c8e839560 | 5256 | /*! @name FIFOSTAT - FIFO status register. */ |
| AnnaBridge | 163:e59c8e839560 | 5257 | #define I2S_FIFOSTAT_TXERR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5258 | #define I2S_FIFOSTAT_TXERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5259 | #define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5260 | #define I2S_FIFOSTAT_RXERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5261 | #define I2S_FIFOSTAT_RXERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5262 | #define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5263 | #define I2S_FIFOSTAT_PERINT_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 5264 | #define I2S_FIFOSTAT_PERINT_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5265 | #define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5266 | #define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 5267 | #define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5268 | #define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5269 | #define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 5270 | #define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 5271 | #define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5272 | #define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 5273 | #define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 5274 | #define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5275 | #define I2S_FIFOSTAT_RXFULL_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 5276 | #define I2S_FIFOSTAT_RXFULL_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 5277 | #define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5278 | #define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) |
| AnnaBridge | 163:e59c8e839560 | 5279 | #define I2S_FIFOSTAT_TXLVL_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 5280 | #define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5281 | #define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) |
| AnnaBridge | 163:e59c8e839560 | 5282 | #define I2S_FIFOSTAT_RXLVL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5283 | #define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5284 | |
| AnnaBridge | 163:e59c8e839560 | 5285 | /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ |
| AnnaBridge | 163:e59c8e839560 | 5286 | #define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5287 | #define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5288 | #define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5289 | #define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5290 | #define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5291 | #define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5292 | #define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) |
| AnnaBridge | 163:e59c8e839560 | 5293 | #define I2S_FIFOTRIG_TXLVL_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 5294 | #define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5295 | #define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) |
| AnnaBridge | 163:e59c8e839560 | 5296 | #define I2S_FIFOTRIG_RXLVL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5297 | #define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5298 | |
| AnnaBridge | 163:e59c8e839560 | 5299 | /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ |
| AnnaBridge | 163:e59c8e839560 | 5300 | #define I2S_FIFOINTENSET_TXERR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5301 | #define I2S_FIFOINTENSET_TXERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5302 | #define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5303 | #define I2S_FIFOINTENSET_RXERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5304 | #define I2S_FIFOINTENSET_RXERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5305 | #define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5306 | #define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 5307 | #define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 5308 | #define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5309 | #define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 5310 | #define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5311 | #define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5312 | |
| AnnaBridge | 163:e59c8e839560 | 5313 | /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ |
| AnnaBridge | 163:e59c8e839560 | 5314 | #define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5315 | #define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5316 | #define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5317 | #define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5318 | #define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5319 | #define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5320 | #define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 5321 | #define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 5322 | #define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5323 | #define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 5324 | #define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5325 | #define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5326 | |
| AnnaBridge | 163:e59c8e839560 | 5327 | /*! @name FIFOINTSTAT - FIFO interrupt status register. */ |
| AnnaBridge | 163:e59c8e839560 | 5328 | #define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5329 | #define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5330 | #define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5331 | #define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5332 | #define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5333 | #define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5334 | #define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 5335 | #define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 5336 | #define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5337 | #define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 5338 | #define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5339 | #define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5340 | #define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 5341 | #define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5342 | #define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5343 | |
| AnnaBridge | 163:e59c8e839560 | 5344 | /*! @name FIFOWR - FIFO write data. */ |
| AnnaBridge | 163:e59c8e839560 | 5345 | #define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 5346 | #define I2S_FIFOWR_TXDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5347 | #define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5348 | |
| AnnaBridge | 163:e59c8e839560 | 5349 | /*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ |
| AnnaBridge | 163:e59c8e839560 | 5350 | #define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 5351 | #define I2S_FIFOWR48H_TXDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5352 | #define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5353 | |
| AnnaBridge | 163:e59c8e839560 | 5354 | /*! @name FIFORD - FIFO read data. */ |
| AnnaBridge | 163:e59c8e839560 | 5355 | #define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 5356 | #define I2S_FIFORD_RXDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5357 | #define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5358 | |
| AnnaBridge | 163:e59c8e839560 | 5359 | /*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ |
| AnnaBridge | 163:e59c8e839560 | 5360 | #define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 5361 | #define I2S_FIFORD48H_RXDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5362 | #define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5363 | |
| AnnaBridge | 163:e59c8e839560 | 5364 | /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ |
| AnnaBridge | 163:e59c8e839560 | 5365 | #define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 5366 | #define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5367 | #define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5368 | |
| AnnaBridge | 163:e59c8e839560 | 5369 | /*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ |
| AnnaBridge | 163:e59c8e839560 | 5370 | #define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 5371 | #define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5372 | #define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5373 | |
| AnnaBridge | 163:e59c8e839560 | 5374 | /*! @name ID - I2S Module identification */ |
| AnnaBridge | 163:e59c8e839560 | 5375 | #define I2S_ID_Aperture_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 5376 | #define I2S_ID_Aperture_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5377 | #define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5378 | #define I2S_ID_Minor_Rev_MASK (0xF00U) |
| AnnaBridge | 163:e59c8e839560 | 5379 | #define I2S_ID_Minor_Rev_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 5380 | #define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5381 | #define I2S_ID_Major_Rev_MASK (0xF000U) |
| AnnaBridge | 163:e59c8e839560 | 5382 | #define I2S_ID_Major_Rev_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 5383 | #define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5384 | #define I2S_ID_ID_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 5385 | #define I2S_ID_ID_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5386 | #define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5387 | |
| AnnaBridge | 163:e59c8e839560 | 5388 | |
| AnnaBridge | 163:e59c8e839560 | 5389 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5390 | * @} |
| AnnaBridge | 163:e59c8e839560 | 5391 | */ /* end of group I2S_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 5392 | |
| AnnaBridge | 163:e59c8e839560 | 5393 | |
| AnnaBridge | 163:e59c8e839560 | 5394 | /* I2S - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 5395 | /** Peripheral I2S0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 5396 | #define I2S0_BASE (0x40097000u) |
| AnnaBridge | 163:e59c8e839560 | 5397 | /** Peripheral I2S0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5398 | #define I2S0 ((I2S_Type *)I2S0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5399 | /** Peripheral I2S1 base address */ |
| AnnaBridge | 163:e59c8e839560 | 5400 | #define I2S1_BASE (0x40098000u) |
| AnnaBridge | 163:e59c8e839560 | 5401 | /** Peripheral I2S1 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5402 | #define I2S1 ((I2S_Type *)I2S1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5403 | /** Array initializer of I2S peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 5404 | #define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE } |
| AnnaBridge | 163:e59c8e839560 | 5405 | /** Array initializer of I2S peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 5406 | #define I2S_BASE_PTRS { I2S0, I2S1 } |
| AnnaBridge | 163:e59c8e839560 | 5407 | /** Interrupt vectors for the I2S peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 5408 | #define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 5409 | |
| AnnaBridge | 163:e59c8e839560 | 5410 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5411 | * @} |
| AnnaBridge | 163:e59c8e839560 | 5412 | */ /* end of group I2S_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 5413 | |
| AnnaBridge | 163:e59c8e839560 | 5414 | |
| AnnaBridge | 163:e59c8e839560 | 5415 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 5416 | -- INPUTMUX Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 5417 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 5418 | |
| AnnaBridge | 163:e59c8e839560 | 5419 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5420 | * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 5421 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 5422 | */ |
| AnnaBridge | 163:e59c8e839560 | 5423 | |
| AnnaBridge | 163:e59c8e839560 | 5424 | /** INPUTMUX - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 5425 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 5426 | __IO uint32_t SCT0_INMUX[7]; /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 5427 | uint8_t RESERVED_0[164]; |
| AnnaBridge | 163:e59c8e839560 | 5428 | __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 5429 | __IO uint32_t DMA_ITRIG_INMUX[30]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 5430 | uint8_t RESERVED_1[8]; |
| AnnaBridge | 163:e59c8e839560 | 5431 | __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 5432 | uint8_t RESERVED_2[16]; |
| AnnaBridge | 163:e59c8e839560 | 5433 | __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */ |
| AnnaBridge | 163:e59c8e839560 | 5434 | __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */ |
| AnnaBridge | 163:e59c8e839560 | 5435 | } INPUTMUX_Type; |
| AnnaBridge | 163:e59c8e839560 | 5436 | |
| AnnaBridge | 163:e59c8e839560 | 5437 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 5438 | -- INPUTMUX Register Masks |
| AnnaBridge | 163:e59c8e839560 | 5439 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 5440 | |
| AnnaBridge | 163:e59c8e839560 | 5441 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5442 | * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks |
| AnnaBridge | 163:e59c8e839560 | 5443 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 5444 | */ |
| AnnaBridge | 163:e59c8e839560 | 5445 | |
| AnnaBridge | 163:e59c8e839560 | 5446 | /*! @name SCT0_INMUX - Trigger select register for DMA channel */ |
| AnnaBridge | 163:e59c8e839560 | 5447 | #define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 5448 | #define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5449 | #define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5450 | |
| AnnaBridge | 163:e59c8e839560 | 5451 | /* The count of INPUTMUX_SCT0_INMUX */ |
| AnnaBridge | 163:e59c8e839560 | 5452 | #define INPUTMUX_SCT0_INMUX_COUNT (7U) |
| AnnaBridge | 163:e59c8e839560 | 5453 | |
| AnnaBridge | 163:e59c8e839560 | 5454 | /*! @name PINTSEL - Pin interrupt select register */ |
| AnnaBridge | 163:e59c8e839560 | 5455 | #define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 5456 | #define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5457 | #define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5458 | |
| AnnaBridge | 163:e59c8e839560 | 5459 | /* The count of INPUTMUX_PINTSEL */ |
| AnnaBridge | 163:e59c8e839560 | 5460 | #define INPUTMUX_PINTSEL_COUNT (8U) |
| AnnaBridge | 163:e59c8e839560 | 5461 | |
| AnnaBridge | 163:e59c8e839560 | 5462 | /*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */ |
| AnnaBridge | 163:e59c8e839560 | 5463 | #define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 5464 | #define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5465 | #define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5466 | |
| AnnaBridge | 163:e59c8e839560 | 5467 | /* The count of INPUTMUX_DMA_ITRIG_INMUX */ |
| AnnaBridge | 163:e59c8e839560 | 5468 | #define INPUTMUX_DMA_ITRIG_INMUX_COUNT (30U) |
| AnnaBridge | 163:e59c8e839560 | 5469 | |
| AnnaBridge | 163:e59c8e839560 | 5470 | /*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */ |
| AnnaBridge | 163:e59c8e839560 | 5471 | #define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 5472 | #define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5473 | #define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5474 | |
| AnnaBridge | 163:e59c8e839560 | 5475 | /* The count of INPUTMUX_DMA_OTRIG_INMUX */ |
| AnnaBridge | 163:e59c8e839560 | 5476 | #define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5477 | |
| AnnaBridge | 163:e59c8e839560 | 5478 | /*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ |
| AnnaBridge | 163:e59c8e839560 | 5479 | #define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 5480 | #define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5481 | #define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5482 | |
| AnnaBridge | 163:e59c8e839560 | 5483 | /*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ |
| AnnaBridge | 163:e59c8e839560 | 5484 | #define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 5485 | #define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5486 | #define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5487 | |
| AnnaBridge | 163:e59c8e839560 | 5488 | |
| AnnaBridge | 163:e59c8e839560 | 5489 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5490 | * @} |
| AnnaBridge | 163:e59c8e839560 | 5491 | */ /* end of group INPUTMUX_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 5492 | |
| AnnaBridge | 163:e59c8e839560 | 5493 | |
| AnnaBridge | 163:e59c8e839560 | 5494 | /* INPUTMUX - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 5495 | /** Peripheral INPUTMUX base address */ |
| AnnaBridge | 163:e59c8e839560 | 5496 | #define INPUTMUX_BASE (0x40005000u) |
| AnnaBridge | 163:e59c8e839560 | 5497 | /** Peripheral INPUTMUX base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5498 | #define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5499 | /** Array initializer of INPUTMUX peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 5500 | #define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE } |
| AnnaBridge | 163:e59c8e839560 | 5501 | /** Array initializer of INPUTMUX peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 5502 | #define INPUTMUX_BASE_PTRS { INPUTMUX } |
| AnnaBridge | 163:e59c8e839560 | 5503 | |
| AnnaBridge | 163:e59c8e839560 | 5504 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5505 | * @} |
| AnnaBridge | 163:e59c8e839560 | 5506 | */ /* end of group INPUTMUX_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 5507 | |
| AnnaBridge | 163:e59c8e839560 | 5508 | |
| AnnaBridge | 163:e59c8e839560 | 5509 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 5510 | -- IOCON Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 5511 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 5512 | |
| AnnaBridge | 163:e59c8e839560 | 5513 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5514 | * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 5515 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 5516 | */ |
| AnnaBridge | 163:e59c8e839560 | 5517 | |
| AnnaBridge | 163:e59c8e839560 | 5518 | /** IOCON - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 5519 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 5520 | __IO uint32_t PIO[6][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31, array offset: 0x0, array step: index*0x80, index2*0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 5521 | } IOCON_Type; |
| AnnaBridge | 163:e59c8e839560 | 5522 | |
| AnnaBridge | 163:e59c8e839560 | 5523 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 5524 | -- IOCON Register Masks |
| AnnaBridge | 163:e59c8e839560 | 5525 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 5526 | |
| AnnaBridge | 163:e59c8e839560 | 5527 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5528 | * @addtogroup IOCON_Register_Masks IOCON Register Masks |
| AnnaBridge | 163:e59c8e839560 | 5529 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 5530 | */ |
| AnnaBridge | 163:e59c8e839560 | 5531 | |
| AnnaBridge | 163:e59c8e839560 | 5532 | /*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31 */ |
| AnnaBridge | 163:e59c8e839560 | 5533 | #define IOCON_PIO_FUNC_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 5534 | #define IOCON_PIO_FUNC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5535 | #define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5536 | #define IOCON_PIO_MODE_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 5537 | #define IOCON_PIO_MODE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5538 | #define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5539 | #define IOCON_PIO_I2CSLEW_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 5540 | #define IOCON_PIO_I2CSLEW_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 5541 | #define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5542 | #define IOCON_PIO_INVERT_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 5543 | #define IOCON_PIO_INVERT_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 5544 | #define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5545 | #define IOCON_PIO_DIGIMODE_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 5546 | #define IOCON_PIO_DIGIMODE_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 5547 | #define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5548 | #define IOCON_PIO_FILTEROFF_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 5549 | #define IOCON_PIO_FILTEROFF_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 5550 | #define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5551 | #define IOCON_PIO_I2CDRIVE_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 5552 | #define IOCON_PIO_I2CDRIVE_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 5553 | #define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5554 | #define IOCON_PIO_SLEW_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 5555 | #define IOCON_PIO_SLEW_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 5556 | #define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5557 | #define IOCON_PIO_OD_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 5558 | #define IOCON_PIO_OD_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 5559 | #define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5560 | #define IOCON_PIO_I2CFILTER_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 5561 | #define IOCON_PIO_I2CFILTER_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 5562 | #define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5563 | |
| AnnaBridge | 163:e59c8e839560 | 5564 | /* The count of IOCON_PIO */ |
| AnnaBridge | 163:e59c8e839560 | 5565 | #define IOCON_PIO_COUNT (6U) |
| AnnaBridge | 163:e59c8e839560 | 5566 | |
| AnnaBridge | 163:e59c8e839560 | 5567 | /* The count of IOCON_PIO */ |
| AnnaBridge | 163:e59c8e839560 | 5568 | #define IOCON_PIO_COUNT2 (32U) |
| AnnaBridge | 163:e59c8e839560 | 5569 | |
| AnnaBridge | 163:e59c8e839560 | 5570 | |
| AnnaBridge | 163:e59c8e839560 | 5571 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5572 | * @} |
| AnnaBridge | 163:e59c8e839560 | 5573 | */ /* end of group IOCON_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 5574 | |
| AnnaBridge | 163:e59c8e839560 | 5575 | |
| AnnaBridge | 163:e59c8e839560 | 5576 | /* IOCON - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 5577 | /** Peripheral IOCON base address */ |
| AnnaBridge | 163:e59c8e839560 | 5578 | #define IOCON_BASE (0x40001000u) |
| AnnaBridge | 163:e59c8e839560 | 5579 | /** Peripheral IOCON base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5580 | #define IOCON ((IOCON_Type *)IOCON_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5581 | /** Array initializer of IOCON peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 5582 | #define IOCON_BASE_ADDRS { IOCON_BASE } |
| AnnaBridge | 163:e59c8e839560 | 5583 | /** Array initializer of IOCON peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 5584 | #define IOCON_BASE_PTRS { IOCON } |
| AnnaBridge | 163:e59c8e839560 | 5585 | |
| AnnaBridge | 163:e59c8e839560 | 5586 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5587 | * @} |
| AnnaBridge | 163:e59c8e839560 | 5588 | */ /* end of group IOCON_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 5589 | |
| AnnaBridge | 163:e59c8e839560 | 5590 | |
| AnnaBridge | 163:e59c8e839560 | 5591 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 5592 | -- LCD Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 5593 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 5594 | |
| AnnaBridge | 163:e59c8e839560 | 5595 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5596 | * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 5597 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 5598 | */ |
| AnnaBridge | 163:e59c8e839560 | 5599 | |
| AnnaBridge | 163:e59c8e839560 | 5600 | /** LCD - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 5601 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 5602 | __IO uint32_t TIMH; /**< Horizontal Timing Control register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 5603 | __IO uint32_t TIMV; /**< Vertical Timing Control register, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 5604 | __IO uint32_t POL; /**< Clock and Signal Polarity Control register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 5605 | __IO uint32_t LE; /**< Line End Control register, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 5606 | __IO uint32_t UPBASE; /**< Upper Panel Frame Base Address register, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 5607 | __IO uint32_t LPBASE; /**< Lower Panel Frame Base Address register, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 5608 | __IO uint32_t CTRL; /**< LCD Control register, offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 5609 | __IO uint32_t INTMSK; /**< Interrupt Mask register, offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 5610 | __I uint32_t INTRAW; /**< Raw Interrupt Status register, offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 5611 | __I uint32_t INTSTAT; /**< Masked Interrupt Status register, offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 5612 | __IO uint32_t INTCLR; /**< Interrupt Clear register, offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 5613 | __I uint32_t UPCURR; /**< Upper Panel Current Address Value register, offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 5614 | __I uint32_t LPCURR; /**< Lower Panel Current Address Value register, offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 5615 | uint8_t RESERVED_0[460]; |
| AnnaBridge | 163:e59c8e839560 | 5616 | __IO uint32_t PAL[128]; /**< 256x16-bit Color Palette registers, array offset: 0x200, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 5617 | uint8_t RESERVED_1[1024]; |
| AnnaBridge | 163:e59c8e839560 | 5618 | __IO uint32_t CRSR_IMG[256]; /**< Cursor Image registers, array offset: 0x800, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 5619 | __IO uint32_t CRSR_CTRL; /**< Cursor Control register, offset: 0xC00 */ |
| AnnaBridge | 163:e59c8e839560 | 5620 | __IO uint32_t CRSR_CFG; /**< Cursor Configuration register, offset: 0xC04 */ |
| AnnaBridge | 163:e59c8e839560 | 5621 | __IO uint32_t CRSR_PAL0; /**< Cursor Palette register 0, offset: 0xC08 */ |
| AnnaBridge | 163:e59c8e839560 | 5622 | __IO uint32_t CRSR_PAL1; /**< Cursor Palette register 1, offset: 0xC0C */ |
| AnnaBridge | 163:e59c8e839560 | 5623 | __IO uint32_t CRSR_XY; /**< Cursor XY Position register, offset: 0xC10 */ |
| AnnaBridge | 163:e59c8e839560 | 5624 | __IO uint32_t CRSR_CLIP; /**< Cursor Clip Position register, offset: 0xC14 */ |
| AnnaBridge | 163:e59c8e839560 | 5625 | uint8_t RESERVED_2[8]; |
| AnnaBridge | 163:e59c8e839560 | 5626 | __IO uint32_t CRSR_INTMSK; /**< Cursor Interrupt Mask register, offset: 0xC20 */ |
| AnnaBridge | 163:e59c8e839560 | 5627 | __O uint32_t CRSR_INTCLR; /**< Cursor Interrupt Clear register, offset: 0xC24 */ |
| AnnaBridge | 163:e59c8e839560 | 5628 | __I uint32_t CRSR_INTRAW; /**< Cursor Raw Interrupt Status register, offset: 0xC28 */ |
| AnnaBridge | 163:e59c8e839560 | 5629 | __I uint32_t CRSR_INTSTAT; /**< Cursor Masked Interrupt Status register, offset: 0xC2C */ |
| AnnaBridge | 163:e59c8e839560 | 5630 | } LCD_Type; |
| AnnaBridge | 163:e59c8e839560 | 5631 | |
| AnnaBridge | 163:e59c8e839560 | 5632 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 5633 | -- LCD Register Masks |
| AnnaBridge | 163:e59c8e839560 | 5634 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 5635 | |
| AnnaBridge | 163:e59c8e839560 | 5636 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5637 | * @addtogroup LCD_Register_Masks LCD Register Masks |
| AnnaBridge | 163:e59c8e839560 | 5638 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 5639 | */ |
| AnnaBridge | 163:e59c8e839560 | 5640 | |
| AnnaBridge | 163:e59c8e839560 | 5641 | /*! @name TIMH - Horizontal Timing Control register */ |
| AnnaBridge | 163:e59c8e839560 | 5642 | #define LCD_TIMH_PPL_MASK (0xFCU) |
| AnnaBridge | 163:e59c8e839560 | 5643 | #define LCD_TIMH_PPL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 5644 | #define LCD_TIMH_PPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_PPL_SHIFT)) & LCD_TIMH_PPL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5645 | #define LCD_TIMH_HSW_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 5646 | #define LCD_TIMH_HSW_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 5647 | #define LCD_TIMH_HSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HSW_SHIFT)) & LCD_TIMH_HSW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5648 | #define LCD_TIMH_HFP_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 5649 | #define LCD_TIMH_HFP_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5650 | #define LCD_TIMH_HFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HFP_SHIFT)) & LCD_TIMH_HFP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5651 | #define LCD_TIMH_HBP_MASK (0xFF000000U) |
| AnnaBridge | 163:e59c8e839560 | 5652 | #define LCD_TIMH_HBP_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 5653 | #define LCD_TIMH_HBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HBP_SHIFT)) & LCD_TIMH_HBP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5654 | |
| AnnaBridge | 163:e59c8e839560 | 5655 | /*! @name TIMV - Vertical Timing Control register */ |
| AnnaBridge | 163:e59c8e839560 | 5656 | #define LCD_TIMV_LPP_MASK (0x3FFU) |
| AnnaBridge | 163:e59c8e839560 | 5657 | #define LCD_TIMV_LPP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5658 | #define LCD_TIMV_LPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_LPP_SHIFT)) & LCD_TIMV_LPP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5659 | #define LCD_TIMV_VSW_MASK (0xFC00U) |
| AnnaBridge | 163:e59c8e839560 | 5660 | #define LCD_TIMV_VSW_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 5661 | #define LCD_TIMV_VSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VSW_SHIFT)) & LCD_TIMV_VSW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5662 | #define LCD_TIMV_VFP_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 5663 | #define LCD_TIMV_VFP_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5664 | #define LCD_TIMV_VFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VFP_SHIFT)) & LCD_TIMV_VFP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5665 | #define LCD_TIMV_VBP_MASK (0xFF000000U) |
| AnnaBridge | 163:e59c8e839560 | 5666 | #define LCD_TIMV_VBP_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 5667 | #define LCD_TIMV_VBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VBP_SHIFT)) & LCD_TIMV_VBP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5668 | |
| AnnaBridge | 163:e59c8e839560 | 5669 | /*! @name POL - Clock and Signal Polarity Control register */ |
| AnnaBridge | 163:e59c8e839560 | 5670 | #define LCD_POL_PCD_LO_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 5671 | #define LCD_POL_PCD_LO_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5672 | #define LCD_POL_PCD_LO(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_LO_SHIFT)) & LCD_POL_PCD_LO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5673 | #define LCD_POL_ACB_MASK (0x7C0U) |
| AnnaBridge | 163:e59c8e839560 | 5674 | #define LCD_POL_ACB_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 5675 | #define LCD_POL_ACB(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_ACB_SHIFT)) & LCD_POL_ACB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5676 | #define LCD_POL_IVS_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 5677 | #define LCD_POL_IVS_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 5678 | #define LCD_POL_IVS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IVS_SHIFT)) & LCD_POL_IVS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5679 | #define LCD_POL_IHS_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 5680 | #define LCD_POL_IHS_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 5681 | #define LCD_POL_IHS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IHS_SHIFT)) & LCD_POL_IHS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5682 | #define LCD_POL_IPC_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 5683 | #define LCD_POL_IPC_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 5684 | #define LCD_POL_IPC(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IPC_SHIFT)) & LCD_POL_IPC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5685 | #define LCD_POL_IOE_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 5686 | #define LCD_POL_IOE_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 5687 | #define LCD_POL_IOE(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IOE_SHIFT)) & LCD_POL_IOE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5688 | #define LCD_POL_CPL_MASK (0x3FF0000U) |
| AnnaBridge | 163:e59c8e839560 | 5689 | #define LCD_POL_CPL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5690 | #define LCD_POL_CPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_CPL_SHIFT)) & LCD_POL_CPL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5691 | #define LCD_POL_BCD_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 5692 | #define LCD_POL_BCD_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 5693 | #define LCD_POL_BCD(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_BCD_SHIFT)) & LCD_POL_BCD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5694 | #define LCD_POL_PCD_HI_MASK (0xF8000000U) |
| AnnaBridge | 163:e59c8e839560 | 5695 | #define LCD_POL_PCD_HI_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 5696 | #define LCD_POL_PCD_HI(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_HI_SHIFT)) & LCD_POL_PCD_HI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5697 | |
| AnnaBridge | 163:e59c8e839560 | 5698 | /*! @name LE - Line End Control register */ |
| AnnaBridge | 163:e59c8e839560 | 5699 | #define LCD_LE_LED_MASK (0x7FU) |
| AnnaBridge | 163:e59c8e839560 | 5700 | #define LCD_LE_LED_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5701 | #define LCD_LE_LED(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LED_SHIFT)) & LCD_LE_LED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5702 | #define LCD_LE_LEE_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 5703 | #define LCD_LE_LEE_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5704 | #define LCD_LE_LEE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LEE_SHIFT)) & LCD_LE_LEE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5705 | |
| AnnaBridge | 163:e59c8e839560 | 5706 | /*! @name UPBASE - Upper Panel Frame Base Address register */ |
| AnnaBridge | 163:e59c8e839560 | 5707 | #define LCD_UPBASE_LCDUPBASE_MASK (0xFFFFFFF8U) |
| AnnaBridge | 163:e59c8e839560 | 5708 | #define LCD_UPBASE_LCDUPBASE_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5709 | #define LCD_UPBASE_LCDUPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPBASE_LCDUPBASE_SHIFT)) & LCD_UPBASE_LCDUPBASE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5710 | |
| AnnaBridge | 163:e59c8e839560 | 5711 | /*! @name LPBASE - Lower Panel Frame Base Address register */ |
| AnnaBridge | 163:e59c8e839560 | 5712 | #define LCD_LPBASE_LCDLPBASE_MASK (0xFFFFFFF8U) |
| AnnaBridge | 163:e59c8e839560 | 5713 | #define LCD_LPBASE_LCDLPBASE_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5714 | #define LCD_LPBASE_LCDLPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPBASE_LCDLPBASE_SHIFT)) & LCD_LPBASE_LCDLPBASE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5715 | |
| AnnaBridge | 163:e59c8e839560 | 5716 | /*! @name CTRL - LCD Control register */ |
| AnnaBridge | 163:e59c8e839560 | 5717 | #define LCD_CTRL_LCDEN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5718 | #define LCD_CTRL_LCDEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5719 | #define LCD_CTRL_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDEN_SHIFT)) & LCD_CTRL_LCDEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5720 | #define LCD_CTRL_LCDBPP_MASK (0xEU) |
| AnnaBridge | 163:e59c8e839560 | 5721 | #define LCD_CTRL_LCDBPP_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5722 | #define LCD_CTRL_LCDBPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBPP_SHIFT)) & LCD_CTRL_LCDBPP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5723 | #define LCD_CTRL_LCDBW_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 5724 | #define LCD_CTRL_LCDBW_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5725 | #define LCD_CTRL_LCDBW(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBW_SHIFT)) & LCD_CTRL_LCDBW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5726 | #define LCD_CTRL_LCDTFT_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 5727 | #define LCD_CTRL_LCDTFT_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 5728 | #define LCD_CTRL_LCDTFT(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDTFT_SHIFT)) & LCD_CTRL_LCDTFT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5729 | #define LCD_CTRL_LCDMONO8_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 5730 | #define LCD_CTRL_LCDMONO8_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 5731 | #define LCD_CTRL_LCDMONO8(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDMONO8_SHIFT)) & LCD_CTRL_LCDMONO8_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5732 | #define LCD_CTRL_LCDDUAL_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 5733 | #define LCD_CTRL_LCDDUAL_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 5734 | #define LCD_CTRL_LCDDUAL(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDDUAL_SHIFT)) & LCD_CTRL_LCDDUAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5735 | #define LCD_CTRL_BGR_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 5736 | #define LCD_CTRL_BGR_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 5737 | #define LCD_CTRL_BGR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BGR_SHIFT)) & LCD_CTRL_BGR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5738 | #define LCD_CTRL_BEBO_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 5739 | #define LCD_CTRL_BEBO_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 5740 | #define LCD_CTRL_BEBO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEBO_SHIFT)) & LCD_CTRL_BEBO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5741 | #define LCD_CTRL_BEPO_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 5742 | #define LCD_CTRL_BEPO_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 5743 | #define LCD_CTRL_BEPO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEPO_SHIFT)) & LCD_CTRL_BEPO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5744 | #define LCD_CTRL_LCDPWR_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 5745 | #define LCD_CTRL_LCDPWR_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 5746 | #define LCD_CTRL_LCDPWR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDPWR_SHIFT)) & LCD_CTRL_LCDPWR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5747 | #define LCD_CTRL_LCDVCOMP_MASK (0x3000U) |
| AnnaBridge | 163:e59c8e839560 | 5748 | #define LCD_CTRL_LCDVCOMP_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 5749 | #define LCD_CTRL_LCDVCOMP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDVCOMP_SHIFT)) & LCD_CTRL_LCDVCOMP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5750 | #define LCD_CTRL_WATERMARK_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 5751 | #define LCD_CTRL_WATERMARK_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5752 | #define LCD_CTRL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_WATERMARK_SHIFT)) & LCD_CTRL_WATERMARK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5753 | |
| AnnaBridge | 163:e59c8e839560 | 5754 | /*! @name INTMSK - Interrupt Mask register */ |
| AnnaBridge | 163:e59c8e839560 | 5755 | #define LCD_INTMSK_FUFIM_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5756 | #define LCD_INTMSK_FUFIM_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5757 | #define LCD_INTMSK_FUFIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_FUFIM_SHIFT)) & LCD_INTMSK_FUFIM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5758 | #define LCD_INTMSK_LNBUIM_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 5759 | #define LCD_INTMSK_LNBUIM_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 5760 | #define LCD_INTMSK_LNBUIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_LNBUIM_SHIFT)) & LCD_INTMSK_LNBUIM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5761 | #define LCD_INTMSK_VCOMPIM_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 5762 | #define LCD_INTMSK_VCOMPIM_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5763 | #define LCD_INTMSK_VCOMPIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_VCOMPIM_SHIFT)) & LCD_INTMSK_VCOMPIM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5764 | #define LCD_INTMSK_BERIM_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 5765 | #define LCD_INTMSK_BERIM_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5766 | #define LCD_INTMSK_BERIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_BERIM_SHIFT)) & LCD_INTMSK_BERIM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5767 | |
| AnnaBridge | 163:e59c8e839560 | 5768 | /*! @name INTRAW - Raw Interrupt Status register */ |
| AnnaBridge | 163:e59c8e839560 | 5769 | #define LCD_INTRAW_FUFRIS_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5770 | #define LCD_INTRAW_FUFRIS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5771 | #define LCD_INTRAW_FUFRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_FUFRIS_SHIFT)) & LCD_INTRAW_FUFRIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5772 | #define LCD_INTRAW_LNBURIS_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 5773 | #define LCD_INTRAW_LNBURIS_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 5774 | #define LCD_INTRAW_LNBURIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_LNBURIS_SHIFT)) & LCD_INTRAW_LNBURIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5775 | #define LCD_INTRAW_VCOMPRIS_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 5776 | #define LCD_INTRAW_VCOMPRIS_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5777 | #define LCD_INTRAW_VCOMPRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_VCOMPRIS_SHIFT)) & LCD_INTRAW_VCOMPRIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5778 | #define LCD_INTRAW_BERRAW_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 5779 | #define LCD_INTRAW_BERRAW_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5780 | #define LCD_INTRAW_BERRAW(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_BERRAW_SHIFT)) & LCD_INTRAW_BERRAW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5781 | |
| AnnaBridge | 163:e59c8e839560 | 5782 | /*! @name INTSTAT - Masked Interrupt Status register */ |
| AnnaBridge | 163:e59c8e839560 | 5783 | #define LCD_INTSTAT_FUFMIS_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5784 | #define LCD_INTSTAT_FUFMIS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5785 | #define LCD_INTSTAT_FUFMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_FUFMIS_SHIFT)) & LCD_INTSTAT_FUFMIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5786 | #define LCD_INTSTAT_LNBUMIS_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 5787 | #define LCD_INTSTAT_LNBUMIS_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 5788 | #define LCD_INTSTAT_LNBUMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_LNBUMIS_SHIFT)) & LCD_INTSTAT_LNBUMIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5789 | #define LCD_INTSTAT_VCOMPMIS_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 5790 | #define LCD_INTSTAT_VCOMPMIS_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5791 | #define LCD_INTSTAT_VCOMPMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_VCOMPMIS_SHIFT)) & LCD_INTSTAT_VCOMPMIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5792 | #define LCD_INTSTAT_BERMIS_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 5793 | #define LCD_INTSTAT_BERMIS_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5794 | #define LCD_INTSTAT_BERMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_BERMIS_SHIFT)) & LCD_INTSTAT_BERMIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5795 | |
| AnnaBridge | 163:e59c8e839560 | 5796 | /*! @name INTCLR - Interrupt Clear register */ |
| AnnaBridge | 163:e59c8e839560 | 5797 | #define LCD_INTCLR_FUFIC_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5798 | #define LCD_INTCLR_FUFIC_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5799 | #define LCD_INTCLR_FUFIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_FUFIC_SHIFT)) & LCD_INTCLR_FUFIC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5800 | #define LCD_INTCLR_LNBUIC_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 5801 | #define LCD_INTCLR_LNBUIC_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 5802 | #define LCD_INTCLR_LNBUIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_LNBUIC_SHIFT)) & LCD_INTCLR_LNBUIC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5803 | #define LCD_INTCLR_VCOMPIC_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 5804 | #define LCD_INTCLR_VCOMPIC_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 5805 | #define LCD_INTCLR_VCOMPIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_VCOMPIC_SHIFT)) & LCD_INTCLR_VCOMPIC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5806 | #define LCD_INTCLR_BERIC_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 5807 | #define LCD_INTCLR_BERIC_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5808 | #define LCD_INTCLR_BERIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_BERIC_SHIFT)) & LCD_INTCLR_BERIC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5809 | |
| AnnaBridge | 163:e59c8e839560 | 5810 | /*! @name UPCURR - Upper Panel Current Address Value register */ |
| AnnaBridge | 163:e59c8e839560 | 5811 | #define LCD_UPCURR_LCDUPCURR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 5812 | #define LCD_UPCURR_LCDUPCURR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5813 | #define LCD_UPCURR_LCDUPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPCURR_LCDUPCURR_SHIFT)) & LCD_UPCURR_LCDUPCURR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5814 | |
| AnnaBridge | 163:e59c8e839560 | 5815 | /*! @name LPCURR - Lower Panel Current Address Value register */ |
| AnnaBridge | 163:e59c8e839560 | 5816 | #define LCD_LPCURR_LCDLPCURR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 5817 | #define LCD_LPCURR_LCDLPCURR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5818 | #define LCD_LPCURR_LCDLPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPCURR_LCDLPCURR_SHIFT)) & LCD_LPCURR_LCDLPCURR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5819 | |
| AnnaBridge | 163:e59c8e839560 | 5820 | /*! @name PAL - 256x16-bit Color Palette registers */ |
| AnnaBridge | 163:e59c8e839560 | 5821 | #define LCD_PAL_R04_0_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 5822 | #define LCD_PAL_R04_0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5823 | #define LCD_PAL_R04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R04_0_SHIFT)) & LCD_PAL_R04_0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5824 | #define LCD_PAL_G04_0_MASK (0x3E0U) |
| AnnaBridge | 163:e59c8e839560 | 5825 | #define LCD_PAL_G04_0_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 5826 | #define LCD_PAL_G04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G04_0_SHIFT)) & LCD_PAL_G04_0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5827 | #define LCD_PAL_B04_0_MASK (0x7C00U) |
| AnnaBridge | 163:e59c8e839560 | 5828 | #define LCD_PAL_B04_0_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 5829 | #define LCD_PAL_B04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B04_0_SHIFT)) & LCD_PAL_B04_0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5830 | #define LCD_PAL_I0_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 5831 | #define LCD_PAL_I0_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 5832 | #define LCD_PAL_I0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I0_SHIFT)) & LCD_PAL_I0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5833 | #define LCD_PAL_R14_0_MASK (0x1F0000U) |
| AnnaBridge | 163:e59c8e839560 | 5834 | #define LCD_PAL_R14_0_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5835 | #define LCD_PAL_R14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R14_0_SHIFT)) & LCD_PAL_R14_0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5836 | #define LCD_PAL_G14_0_MASK (0x3E00000U) |
| AnnaBridge | 163:e59c8e839560 | 5837 | #define LCD_PAL_G14_0_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 5838 | #define LCD_PAL_G14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G14_0_SHIFT)) & LCD_PAL_G14_0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5839 | #define LCD_PAL_B14_0_MASK (0x7C000000U) |
| AnnaBridge | 163:e59c8e839560 | 5840 | #define LCD_PAL_B14_0_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 5841 | #define LCD_PAL_B14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B14_0_SHIFT)) & LCD_PAL_B14_0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5842 | #define LCD_PAL_I1_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 5843 | #define LCD_PAL_I1_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 5844 | #define LCD_PAL_I1(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I1_SHIFT)) & LCD_PAL_I1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5845 | |
| AnnaBridge | 163:e59c8e839560 | 5846 | /* The count of LCD_PAL */ |
| AnnaBridge | 163:e59c8e839560 | 5847 | #define LCD_PAL_COUNT (128U) |
| AnnaBridge | 163:e59c8e839560 | 5848 | |
| AnnaBridge | 163:e59c8e839560 | 5849 | /*! @name CRSR_IMG - Cursor Image registers */ |
| AnnaBridge | 163:e59c8e839560 | 5850 | #define LCD_CRSR_IMG_CRSR_IMG_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 5851 | #define LCD_CRSR_IMG_CRSR_IMG_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5852 | #define LCD_CRSR_IMG_CRSR_IMG(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_IMG_CRSR_IMG_SHIFT)) & LCD_CRSR_IMG_CRSR_IMG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5853 | |
| AnnaBridge | 163:e59c8e839560 | 5854 | /* The count of LCD_CRSR_IMG */ |
| AnnaBridge | 163:e59c8e839560 | 5855 | #define LCD_CRSR_IMG_COUNT (256U) |
| AnnaBridge | 163:e59c8e839560 | 5856 | |
| AnnaBridge | 163:e59c8e839560 | 5857 | /*! @name CRSR_CTRL - Cursor Control register */ |
| AnnaBridge | 163:e59c8e839560 | 5858 | #define LCD_CRSR_CTRL_CRSRON_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5859 | #define LCD_CRSR_CTRL_CRSRON_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5860 | #define LCD_CRSR_CTRL_CRSRON(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRON_SHIFT)) & LCD_CRSR_CTRL_CRSRON_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5861 | #define LCD_CRSR_CTRL_CRSRNUM1_0_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 5862 | #define LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5863 | #define LCD_CRSR_CTRL_CRSRNUM1_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)) & LCD_CRSR_CTRL_CRSRNUM1_0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5864 | |
| AnnaBridge | 163:e59c8e839560 | 5865 | /*! @name CRSR_CFG - Cursor Configuration register */ |
| AnnaBridge | 163:e59c8e839560 | 5866 | #define LCD_CRSR_CFG_CRSRSIZE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5867 | #define LCD_CRSR_CFG_CRSRSIZE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5868 | #define LCD_CRSR_CFG_CRSRSIZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_CRSRSIZE_SHIFT)) & LCD_CRSR_CFG_CRSRSIZE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5869 | #define LCD_CRSR_CFG_FRAMESYNC_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 5870 | #define LCD_CRSR_CFG_FRAMESYNC_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 5871 | #define LCD_CRSR_CFG_FRAMESYNC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_FRAMESYNC_SHIFT)) & LCD_CRSR_CFG_FRAMESYNC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5872 | |
| AnnaBridge | 163:e59c8e839560 | 5873 | /*! @name CRSR_PAL0 - Cursor Palette register 0 */ |
| AnnaBridge | 163:e59c8e839560 | 5874 | #define LCD_CRSR_PAL0_RED_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 5875 | #define LCD_CRSR_PAL0_RED_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5876 | #define LCD_CRSR_PAL0_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_RED_SHIFT)) & LCD_CRSR_PAL0_RED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5877 | #define LCD_CRSR_PAL0_GREEN_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 5878 | #define LCD_CRSR_PAL0_GREEN_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 5879 | #define LCD_CRSR_PAL0_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_GREEN_SHIFT)) & LCD_CRSR_PAL0_GREEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5880 | #define LCD_CRSR_PAL0_BLUE_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 5881 | #define LCD_CRSR_PAL0_BLUE_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5882 | #define LCD_CRSR_PAL0_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_BLUE_SHIFT)) & LCD_CRSR_PAL0_BLUE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5883 | |
| AnnaBridge | 163:e59c8e839560 | 5884 | /*! @name CRSR_PAL1 - Cursor Palette register 1 */ |
| AnnaBridge | 163:e59c8e839560 | 5885 | #define LCD_CRSR_PAL1_RED_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 5886 | #define LCD_CRSR_PAL1_RED_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5887 | #define LCD_CRSR_PAL1_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_RED_SHIFT)) & LCD_CRSR_PAL1_RED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5888 | #define LCD_CRSR_PAL1_GREEN_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 5889 | #define LCD_CRSR_PAL1_GREEN_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 5890 | #define LCD_CRSR_PAL1_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_GREEN_SHIFT)) & LCD_CRSR_PAL1_GREEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5891 | #define LCD_CRSR_PAL1_BLUE_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 5892 | #define LCD_CRSR_PAL1_BLUE_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5893 | #define LCD_CRSR_PAL1_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_BLUE_SHIFT)) & LCD_CRSR_PAL1_BLUE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5894 | |
| AnnaBridge | 163:e59c8e839560 | 5895 | /*! @name CRSR_XY - Cursor XY Position register */ |
| AnnaBridge | 163:e59c8e839560 | 5896 | #define LCD_CRSR_XY_CRSRX_MASK (0x3FFU) |
| AnnaBridge | 163:e59c8e839560 | 5897 | #define LCD_CRSR_XY_CRSRX_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5898 | #define LCD_CRSR_XY_CRSRX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRX_SHIFT)) & LCD_CRSR_XY_CRSRX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5899 | #define LCD_CRSR_XY_CRSRY_MASK (0x3FF0000U) |
| AnnaBridge | 163:e59c8e839560 | 5900 | #define LCD_CRSR_XY_CRSRY_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 5901 | #define LCD_CRSR_XY_CRSRY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRY_SHIFT)) & LCD_CRSR_XY_CRSRY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5902 | |
| AnnaBridge | 163:e59c8e839560 | 5903 | /*! @name CRSR_CLIP - Cursor Clip Position register */ |
| AnnaBridge | 163:e59c8e839560 | 5904 | #define LCD_CRSR_CLIP_CRSRCLIPX_MASK (0x3FU) |
| AnnaBridge | 163:e59c8e839560 | 5905 | #define LCD_CRSR_CLIP_CRSRCLIPX_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5906 | #define LCD_CRSR_CLIP_CRSRCLIPX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5907 | #define LCD_CRSR_CLIP_CRSRCLIPY_MASK (0x3F00U) |
| AnnaBridge | 163:e59c8e839560 | 5908 | #define LCD_CRSR_CLIP_CRSRCLIPY_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 5909 | #define LCD_CRSR_CLIP_CRSRCLIPY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPY_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5910 | |
| AnnaBridge | 163:e59c8e839560 | 5911 | /*! @name CRSR_INTMSK - Cursor Interrupt Mask register */ |
| AnnaBridge | 163:e59c8e839560 | 5912 | #define LCD_CRSR_INTMSK_CRSRIM_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5913 | #define LCD_CRSR_INTMSK_CRSRIM_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5914 | #define LCD_CRSR_INTMSK_CRSRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTMSK_CRSRIM_SHIFT)) & LCD_CRSR_INTMSK_CRSRIM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5915 | |
| AnnaBridge | 163:e59c8e839560 | 5916 | /*! @name CRSR_INTCLR - Cursor Interrupt Clear register */ |
| AnnaBridge | 163:e59c8e839560 | 5917 | #define LCD_CRSR_INTCLR_CRSRIC_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5918 | #define LCD_CRSR_INTCLR_CRSRIC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5919 | #define LCD_CRSR_INTCLR_CRSRIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTCLR_CRSRIC_SHIFT)) & LCD_CRSR_INTCLR_CRSRIC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5920 | |
| AnnaBridge | 163:e59c8e839560 | 5921 | /*! @name CRSR_INTRAW - Cursor Raw Interrupt Status register */ |
| AnnaBridge | 163:e59c8e839560 | 5922 | #define LCD_CRSR_INTRAW_CRSRRIS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5923 | #define LCD_CRSR_INTRAW_CRSRRIS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5924 | #define LCD_CRSR_INTRAW_CRSRRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTRAW_CRSRRIS_SHIFT)) & LCD_CRSR_INTRAW_CRSRRIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5925 | |
| AnnaBridge | 163:e59c8e839560 | 5926 | /*! @name CRSR_INTSTAT - Cursor Masked Interrupt Status register */ |
| AnnaBridge | 163:e59c8e839560 | 5927 | #define LCD_CRSR_INTSTAT_CRSRMIS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 5928 | #define LCD_CRSR_INTSTAT_CRSRMIS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5929 | #define LCD_CRSR_INTSTAT_CRSRMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT)) & LCD_CRSR_INTSTAT_CRSRMIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5930 | |
| AnnaBridge | 163:e59c8e839560 | 5931 | |
| AnnaBridge | 163:e59c8e839560 | 5932 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5933 | * @} |
| AnnaBridge | 163:e59c8e839560 | 5934 | */ /* end of group LCD_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 5935 | |
| AnnaBridge | 163:e59c8e839560 | 5936 | |
| AnnaBridge | 163:e59c8e839560 | 5937 | /* LCD - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 5938 | /** Peripheral LCD base address */ |
| AnnaBridge | 163:e59c8e839560 | 5939 | #define LCD_BASE (0x40083000u) |
| AnnaBridge | 163:e59c8e839560 | 5940 | /** Peripheral LCD base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 5941 | #define LCD ((LCD_Type *)LCD_BASE) |
| AnnaBridge | 163:e59c8e839560 | 5942 | /** Array initializer of LCD peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 5943 | #define LCD_BASE_ADDRS { LCD_BASE } |
| AnnaBridge | 163:e59c8e839560 | 5944 | /** Array initializer of LCD peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 5945 | #define LCD_BASE_PTRS { LCD } |
| AnnaBridge | 163:e59c8e839560 | 5946 | /** Interrupt vectors for the LCD peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 5947 | #define LCD_IRQS { LCD_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 5948 | |
| AnnaBridge | 163:e59c8e839560 | 5949 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5950 | * @} |
| AnnaBridge | 163:e59c8e839560 | 5951 | */ /* end of group LCD_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 5952 | |
| AnnaBridge | 163:e59c8e839560 | 5953 | |
| AnnaBridge | 163:e59c8e839560 | 5954 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 5955 | -- MRT Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 5956 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 5957 | |
| AnnaBridge | 163:e59c8e839560 | 5958 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5959 | * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 5960 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 5961 | */ |
| AnnaBridge | 163:e59c8e839560 | 5962 | |
| AnnaBridge | 163:e59c8e839560 | 5963 | /** MRT - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 5964 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 5965 | struct { /* offset: 0x0, array step: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 5966 | __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 5967 | __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 5968 | __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 5969 | __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 5970 | } CHANNEL[4]; |
| AnnaBridge | 163:e59c8e839560 | 5971 | uint8_t RESERVED_0[176]; |
| AnnaBridge | 163:e59c8e839560 | 5972 | __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */ |
| AnnaBridge | 163:e59c8e839560 | 5973 | __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ |
| AnnaBridge | 163:e59c8e839560 | 5974 | __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ |
| AnnaBridge | 163:e59c8e839560 | 5975 | } MRT_Type; |
| AnnaBridge | 163:e59c8e839560 | 5976 | |
| AnnaBridge | 163:e59c8e839560 | 5977 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 5978 | -- MRT Register Masks |
| AnnaBridge | 163:e59c8e839560 | 5979 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 5980 | |
| AnnaBridge | 163:e59c8e839560 | 5981 | /*! |
| AnnaBridge | 163:e59c8e839560 | 5982 | * @addtogroup MRT_Register_Masks MRT Register Masks |
| AnnaBridge | 163:e59c8e839560 | 5983 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 5984 | */ |
| AnnaBridge | 163:e59c8e839560 | 5985 | |
| AnnaBridge | 163:e59c8e839560 | 5986 | /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ |
| AnnaBridge | 163:e59c8e839560 | 5987 | #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 5988 | #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 5989 | #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5990 | #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 5991 | #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 5992 | #define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 5993 | |
| AnnaBridge | 163:e59c8e839560 | 5994 | /* The count of MRT_CHANNEL_INTVAL */ |
| AnnaBridge | 163:e59c8e839560 | 5995 | #define MRT_CHANNEL_INTVAL_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 5996 | |
| AnnaBridge | 163:e59c8e839560 | 5997 | /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ |
| AnnaBridge | 163:e59c8e839560 | 5998 | #define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 5999 | #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6000 | #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6001 | |
| AnnaBridge | 163:e59c8e839560 | 6002 | /* The count of MRT_CHANNEL_TIMER */ |
| AnnaBridge | 163:e59c8e839560 | 6003 | #define MRT_CHANNEL_TIMER_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 6004 | |
| AnnaBridge | 163:e59c8e839560 | 6005 | /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ |
| AnnaBridge | 163:e59c8e839560 | 6006 | #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 6007 | #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6008 | #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6009 | #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) |
| AnnaBridge | 163:e59c8e839560 | 6010 | #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 6011 | #define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6012 | |
| AnnaBridge | 163:e59c8e839560 | 6013 | /* The count of MRT_CHANNEL_CTRL */ |
| AnnaBridge | 163:e59c8e839560 | 6014 | #define MRT_CHANNEL_CTRL_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 6015 | |
| AnnaBridge | 163:e59c8e839560 | 6016 | /*! @name CHANNEL_STAT - MRT Status register. */ |
| AnnaBridge | 163:e59c8e839560 | 6017 | #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 6018 | #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6019 | #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6020 | #define MRT_CHANNEL_STAT_RUN_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 6021 | #define MRT_CHANNEL_STAT_RUN_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 6022 | #define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6023 | #define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 6024 | #define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 6025 | #define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6026 | |
| AnnaBridge | 163:e59c8e839560 | 6027 | /* The count of MRT_CHANNEL_STAT */ |
| AnnaBridge | 163:e59c8e839560 | 6028 | #define MRT_CHANNEL_STAT_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 6029 | |
| AnnaBridge | 163:e59c8e839560 | 6030 | /*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ |
| AnnaBridge | 163:e59c8e839560 | 6031 | #define MRT_MODCFG_NOC_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 6032 | #define MRT_MODCFG_NOC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6033 | #define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6034 | #define MRT_MODCFG_NOB_MASK (0x1F0U) |
| AnnaBridge | 163:e59c8e839560 | 6035 | #define MRT_MODCFG_NOB_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 6036 | #define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6037 | #define MRT_MODCFG_MULTITASK_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 6038 | #define MRT_MODCFG_MULTITASK_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 6039 | #define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6040 | |
| AnnaBridge | 163:e59c8e839560 | 6041 | /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ |
| AnnaBridge | 163:e59c8e839560 | 6042 | #define MRT_IDLE_CH_CHAN_MASK (0xF0U) |
| AnnaBridge | 163:e59c8e839560 | 6043 | #define MRT_IDLE_CH_CHAN_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 6044 | #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6045 | |
| AnnaBridge | 163:e59c8e839560 | 6046 | /*! @name IRQ_FLAG - Global interrupt flag register */ |
| AnnaBridge | 163:e59c8e839560 | 6047 | #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 6048 | #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6049 | #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6050 | #define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 6051 | #define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 6052 | #define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6053 | #define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 6054 | #define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 6055 | #define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6056 | #define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 6057 | #define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 6058 | #define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6059 | |
| AnnaBridge | 163:e59c8e839560 | 6060 | |
| AnnaBridge | 163:e59c8e839560 | 6061 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6062 | * @} |
| AnnaBridge | 163:e59c8e839560 | 6063 | */ /* end of group MRT_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 6064 | |
| AnnaBridge | 163:e59c8e839560 | 6065 | |
| AnnaBridge | 163:e59c8e839560 | 6066 | /* MRT - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 6067 | /** Peripheral MRT0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 6068 | #define MRT0_BASE (0x4000D000u) |
| AnnaBridge | 163:e59c8e839560 | 6069 | /** Peripheral MRT0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 6070 | #define MRT0 ((MRT_Type *)MRT0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 6071 | /** Array initializer of MRT peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 6072 | #define MRT_BASE_ADDRS { MRT0_BASE } |
| AnnaBridge | 163:e59c8e839560 | 6073 | /** Array initializer of MRT peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 6074 | #define MRT_BASE_PTRS { MRT0 } |
| AnnaBridge | 163:e59c8e839560 | 6075 | /** Interrupt vectors for the MRT peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 6076 | #define MRT_IRQS { MRT0_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 6077 | |
| AnnaBridge | 163:e59c8e839560 | 6078 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6079 | * @} |
| AnnaBridge | 163:e59c8e839560 | 6080 | */ /* end of group MRT_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 6081 | |
| AnnaBridge | 163:e59c8e839560 | 6082 | |
| AnnaBridge | 163:e59c8e839560 | 6083 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 6084 | -- OTPC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 6085 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 6086 | |
| AnnaBridge | 163:e59c8e839560 | 6087 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6088 | * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 6089 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 6090 | */ |
| AnnaBridge | 163:e59c8e839560 | 6091 | |
| AnnaBridge | 163:e59c8e839560 | 6092 | /** OTPC - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 6093 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 6094 | uint8_t RESERVED_0[16]; |
| AnnaBridge | 163:e59c8e839560 | 6095 | __I uint32_t AESKEY[8]; /**< Register for reading the AES key., array offset: 0x10, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 6096 | __I uint32_t ECRP; /**< ECRP options., offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 6097 | uint8_t RESERVED_1[4]; |
| AnnaBridge | 163:e59c8e839560 | 6098 | __I uint32_t USER0; /**< User application specific options., offset: 0x38 */ |
| AnnaBridge | 163:e59c8e839560 | 6099 | __I uint32_t USER1; /**< User application specific options., offset: 0x3C */ |
| AnnaBridge | 163:e59c8e839560 | 6100 | } OTPC_Type; |
| AnnaBridge | 163:e59c8e839560 | 6101 | |
| AnnaBridge | 163:e59c8e839560 | 6102 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 6103 | -- OTPC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 6104 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 6105 | |
| AnnaBridge | 163:e59c8e839560 | 6106 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6107 | * @addtogroup OTPC_Register_Masks OTPC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 6108 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 6109 | */ |
| AnnaBridge | 163:e59c8e839560 | 6110 | |
| AnnaBridge | 163:e59c8e839560 | 6111 | /*! @name AESKEY - Register for reading the AES key. */ |
| AnnaBridge | 163:e59c8e839560 | 6112 | #define OTPC_AESKEY_KEY_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6113 | #define OTPC_AESKEY_KEY_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6114 | #define OTPC_AESKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6115 | |
| AnnaBridge | 163:e59c8e839560 | 6116 | /* The count of OTPC_AESKEY */ |
| AnnaBridge | 163:e59c8e839560 | 6117 | #define OTPC_AESKEY_COUNT (8U) |
| AnnaBridge | 163:e59c8e839560 | 6118 | |
| AnnaBridge | 163:e59c8e839560 | 6119 | /*! @name ECRP - ECRP options. */ |
| AnnaBridge | 163:e59c8e839560 | 6120 | #define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 6121 | #define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 6122 | #define OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6123 | #define OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 6124 | #define OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 6125 | #define OTPC_ECRP_IAP_PROTECTION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6126 | #define OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 6127 | #define OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 6128 | #define OTPC_ECRP_CRP_ISP_DISABLE_PIN(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6129 | #define OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 6130 | #define OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 6131 | #define OTPC_ECRP_CRP_ISP_DISABLE_IAP(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6132 | #define OTPC_ECRP_CRP_ALLOW_ZERO_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 6133 | #define OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 6134 | #define OTPC_ECRP_CRP_ALLOW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6135 | #define OTPC_ECRP_JTAG_DISABLE_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 6136 | #define OTPC_ECRP_JTAG_DISABLE_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 6137 | #define OTPC_ECRP_JTAG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6138 | |
| AnnaBridge | 163:e59c8e839560 | 6139 | /*! @name USER0 - User application specific options. */ |
| AnnaBridge | 163:e59c8e839560 | 6140 | #define OTPC_USER0_USER0_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6141 | #define OTPC_USER0_USER0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6142 | #define OTPC_USER0_USER0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6143 | |
| AnnaBridge | 163:e59c8e839560 | 6144 | /*! @name USER1 - User application specific options. */ |
| AnnaBridge | 163:e59c8e839560 | 6145 | #define OTPC_USER1_USER1_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6146 | #define OTPC_USER1_USER1_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6147 | #define OTPC_USER1_USER1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6148 | |
| AnnaBridge | 163:e59c8e839560 | 6149 | |
| AnnaBridge | 163:e59c8e839560 | 6150 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6151 | * @} |
| AnnaBridge | 163:e59c8e839560 | 6152 | */ /* end of group OTPC_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 6153 | |
| AnnaBridge | 163:e59c8e839560 | 6154 | |
| AnnaBridge | 163:e59c8e839560 | 6155 | /* OTPC - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 6156 | /** Peripheral OTPC base address */ |
| AnnaBridge | 163:e59c8e839560 | 6157 | #define OTPC_BASE (0x40015000u) |
| AnnaBridge | 163:e59c8e839560 | 6158 | /** Peripheral OTPC base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 6159 | #define OTPC ((OTPC_Type *)OTPC_BASE) |
| AnnaBridge | 163:e59c8e839560 | 6160 | /** Array initializer of OTPC peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 6161 | #define OTPC_BASE_ADDRS { OTPC_BASE } |
| AnnaBridge | 163:e59c8e839560 | 6162 | /** Array initializer of OTPC peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 6163 | #define OTPC_BASE_PTRS { OTPC } |
| AnnaBridge | 163:e59c8e839560 | 6164 | |
| AnnaBridge | 163:e59c8e839560 | 6165 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6166 | * @} |
| AnnaBridge | 163:e59c8e839560 | 6167 | */ /* end of group OTPC_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 6168 | |
| AnnaBridge | 163:e59c8e839560 | 6169 | |
| AnnaBridge | 163:e59c8e839560 | 6170 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 6171 | -- PINT Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 6172 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 6173 | |
| AnnaBridge | 163:e59c8e839560 | 6174 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6175 | * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 6176 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 6177 | */ |
| AnnaBridge | 163:e59c8e839560 | 6178 | |
| AnnaBridge | 163:e59c8e839560 | 6179 | /** PINT - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 6180 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 6181 | __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 6182 | __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 6183 | __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 6184 | __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 6185 | __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 6186 | __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 6187 | __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 6188 | __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 6189 | __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 6190 | __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 6191 | __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 6192 | __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 6193 | __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 6194 | } PINT_Type; |
| AnnaBridge | 163:e59c8e839560 | 6195 | |
| AnnaBridge | 163:e59c8e839560 | 6196 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 6197 | -- PINT Register Masks |
| AnnaBridge | 163:e59c8e839560 | 6198 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 6199 | |
| AnnaBridge | 163:e59c8e839560 | 6200 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6201 | * @addtogroup PINT_Register_Masks PINT Register Masks |
| AnnaBridge | 163:e59c8e839560 | 6202 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 6203 | */ |
| AnnaBridge | 163:e59c8e839560 | 6204 | |
| AnnaBridge | 163:e59c8e839560 | 6205 | /*! @name ISEL - Pin Interrupt Mode register */ |
| AnnaBridge | 163:e59c8e839560 | 6206 | #define PINT_ISEL_PMODE_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 6207 | #define PINT_ISEL_PMODE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6208 | #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6209 | |
| AnnaBridge | 163:e59c8e839560 | 6210 | /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ |
| AnnaBridge | 163:e59c8e839560 | 6211 | #define PINT_IENR_ENRL_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 6212 | #define PINT_IENR_ENRL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6213 | #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6214 | |
| AnnaBridge | 163:e59c8e839560 | 6215 | /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ |
| AnnaBridge | 163:e59c8e839560 | 6216 | #define PINT_SIENR_SETENRL_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 6217 | #define PINT_SIENR_SETENRL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6218 | #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6219 | |
| AnnaBridge | 163:e59c8e839560 | 6220 | /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ |
| AnnaBridge | 163:e59c8e839560 | 6221 | #define PINT_CIENR_CENRL_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 6222 | #define PINT_CIENR_CENRL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6223 | #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6224 | |
| AnnaBridge | 163:e59c8e839560 | 6225 | /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ |
| AnnaBridge | 163:e59c8e839560 | 6226 | #define PINT_IENF_ENAF_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 6227 | #define PINT_IENF_ENAF_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6228 | #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6229 | |
| AnnaBridge | 163:e59c8e839560 | 6230 | /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ |
| AnnaBridge | 163:e59c8e839560 | 6231 | #define PINT_SIENF_SETENAF_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 6232 | #define PINT_SIENF_SETENAF_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6233 | #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6234 | |
| AnnaBridge | 163:e59c8e839560 | 6235 | /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ |
| AnnaBridge | 163:e59c8e839560 | 6236 | #define PINT_CIENF_CENAF_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 6237 | #define PINT_CIENF_CENAF_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6238 | #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6239 | |
| AnnaBridge | 163:e59c8e839560 | 6240 | /*! @name RISE - Pin interrupt rising edge register */ |
| AnnaBridge | 163:e59c8e839560 | 6241 | #define PINT_RISE_RDET_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 6242 | #define PINT_RISE_RDET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6243 | #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6244 | |
| AnnaBridge | 163:e59c8e839560 | 6245 | /*! @name FALL - Pin interrupt falling edge register */ |
| AnnaBridge | 163:e59c8e839560 | 6246 | #define PINT_FALL_FDET_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 6247 | #define PINT_FALL_FDET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6248 | #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6249 | |
| AnnaBridge | 163:e59c8e839560 | 6250 | /*! @name IST - Pin interrupt status register */ |
| AnnaBridge | 163:e59c8e839560 | 6251 | #define PINT_IST_PSTAT_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 6252 | #define PINT_IST_PSTAT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6253 | #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6254 | |
| AnnaBridge | 163:e59c8e839560 | 6255 | /*! @name PMCTRL - Pattern match interrupt control register */ |
| AnnaBridge | 163:e59c8e839560 | 6256 | #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 6257 | #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6258 | #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6259 | #define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 6260 | #define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 6261 | #define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6262 | #define PINT_PMCTRL_PMAT_MASK (0xFF000000U) |
| AnnaBridge | 163:e59c8e839560 | 6263 | #define PINT_PMCTRL_PMAT_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 6264 | #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6265 | |
| AnnaBridge | 163:e59c8e839560 | 6266 | /*! @name PMSRC - Pattern match interrupt bit-slice source register */ |
| AnnaBridge | 163:e59c8e839560 | 6267 | #define PINT_PMSRC_SRC0_MASK (0x700U) |
| AnnaBridge | 163:e59c8e839560 | 6268 | #define PINT_PMSRC_SRC0_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 6269 | #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6270 | #define PINT_PMSRC_SRC1_MASK (0x3800U) |
| AnnaBridge | 163:e59c8e839560 | 6271 | #define PINT_PMSRC_SRC1_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 6272 | #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6273 | #define PINT_PMSRC_SRC2_MASK (0x1C000U) |
| AnnaBridge | 163:e59c8e839560 | 6274 | #define PINT_PMSRC_SRC2_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 6275 | #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6276 | #define PINT_PMSRC_SRC3_MASK (0xE0000U) |
| AnnaBridge | 163:e59c8e839560 | 6277 | #define PINT_PMSRC_SRC3_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 6278 | #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6279 | #define PINT_PMSRC_SRC4_MASK (0x700000U) |
| AnnaBridge | 163:e59c8e839560 | 6280 | #define PINT_PMSRC_SRC4_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 6281 | #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6282 | #define PINT_PMSRC_SRC5_MASK (0x3800000U) |
| AnnaBridge | 163:e59c8e839560 | 6283 | #define PINT_PMSRC_SRC5_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 6284 | #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6285 | #define PINT_PMSRC_SRC6_MASK (0x1C000000U) |
| AnnaBridge | 163:e59c8e839560 | 6286 | #define PINT_PMSRC_SRC6_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 6287 | #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6288 | #define PINT_PMSRC_SRC7_MASK (0xE0000000U) |
| AnnaBridge | 163:e59c8e839560 | 6289 | #define PINT_PMSRC_SRC7_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 6290 | #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6291 | |
| AnnaBridge | 163:e59c8e839560 | 6292 | /*! @name PMCFG - Pattern match interrupt bit slice configuration register */ |
| AnnaBridge | 163:e59c8e839560 | 6293 | #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 6294 | #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6295 | #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6296 | #define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 6297 | #define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 6298 | #define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6299 | #define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 6300 | #define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 6301 | #define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6302 | #define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 6303 | #define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 6304 | #define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6305 | #define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 6306 | #define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 6307 | #define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6308 | #define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 6309 | #define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 6310 | #define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6311 | #define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 6312 | #define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 6313 | #define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6314 | #define PINT_PMCFG_CFG0_MASK (0x700U) |
| AnnaBridge | 163:e59c8e839560 | 6315 | #define PINT_PMCFG_CFG0_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 6316 | #define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6317 | #define PINT_PMCFG_CFG1_MASK (0x3800U) |
| AnnaBridge | 163:e59c8e839560 | 6318 | #define PINT_PMCFG_CFG1_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 6319 | #define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6320 | #define PINT_PMCFG_CFG2_MASK (0x1C000U) |
| AnnaBridge | 163:e59c8e839560 | 6321 | #define PINT_PMCFG_CFG2_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 6322 | #define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6323 | #define PINT_PMCFG_CFG3_MASK (0xE0000U) |
| AnnaBridge | 163:e59c8e839560 | 6324 | #define PINT_PMCFG_CFG3_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 6325 | #define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6326 | #define PINT_PMCFG_CFG4_MASK (0x700000U) |
| AnnaBridge | 163:e59c8e839560 | 6327 | #define PINT_PMCFG_CFG4_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 6328 | #define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6329 | #define PINT_PMCFG_CFG5_MASK (0x3800000U) |
| AnnaBridge | 163:e59c8e839560 | 6330 | #define PINT_PMCFG_CFG5_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 6331 | #define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6332 | #define PINT_PMCFG_CFG6_MASK (0x1C000000U) |
| AnnaBridge | 163:e59c8e839560 | 6333 | #define PINT_PMCFG_CFG6_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 6334 | #define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6335 | #define PINT_PMCFG_CFG7_MASK (0xE0000000U) |
| AnnaBridge | 163:e59c8e839560 | 6336 | #define PINT_PMCFG_CFG7_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 6337 | #define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6338 | |
| AnnaBridge | 163:e59c8e839560 | 6339 | |
| AnnaBridge | 163:e59c8e839560 | 6340 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6341 | * @} |
| AnnaBridge | 163:e59c8e839560 | 6342 | */ /* end of group PINT_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 6343 | |
| AnnaBridge | 163:e59c8e839560 | 6344 | |
| AnnaBridge | 163:e59c8e839560 | 6345 | /* PINT - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 6346 | /** Peripheral PINT base address */ |
| AnnaBridge | 163:e59c8e839560 | 6347 | #define PINT_BASE (0x40004000u) |
| AnnaBridge | 163:e59c8e839560 | 6348 | /** Peripheral PINT base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 6349 | #define PINT ((PINT_Type *)PINT_BASE) |
| AnnaBridge | 163:e59c8e839560 | 6350 | /** Array initializer of PINT peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 6351 | #define PINT_BASE_ADDRS { PINT_BASE } |
| AnnaBridge | 163:e59c8e839560 | 6352 | /** Array initializer of PINT peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 6353 | #define PINT_BASE_PTRS { PINT } |
| AnnaBridge | 163:e59c8e839560 | 6354 | /** Interrupt vectors for the PINT peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 6355 | #define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 6356 | |
| AnnaBridge | 163:e59c8e839560 | 6357 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6358 | * @} |
| AnnaBridge | 163:e59c8e839560 | 6359 | */ /* end of group PINT_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 6360 | |
| AnnaBridge | 163:e59c8e839560 | 6361 | |
| AnnaBridge | 163:e59c8e839560 | 6362 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 6363 | -- RIT Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 6364 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 6365 | |
| AnnaBridge | 163:e59c8e839560 | 6366 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6367 | * @addtogroup RIT_Peripheral_Access_Layer RIT Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 6368 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 6369 | */ |
| AnnaBridge | 163:e59c8e839560 | 6370 | |
| AnnaBridge | 163:e59c8e839560 | 6371 | /** RIT - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 6372 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 6373 | __IO uint32_t COMPVAL; /**< Compare value LSB register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 6374 | __IO uint32_t MASK; /**< Mask LSB register, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 6375 | __IO uint32_t CTRL; /**< Control register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 6376 | __IO uint32_t COUNTER; /**< Counter LSB register, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 6377 | __IO uint32_t COMPVAL_H; /**< Compare value MSB register, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 6378 | __IO uint32_t MASK_H; /**< Mask MSB register, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 6379 | uint8_t RESERVED_0[4]; |
| AnnaBridge | 163:e59c8e839560 | 6380 | __IO uint32_t COUNTER_H; /**< Counter MSB register, offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 6381 | } RIT_Type; |
| AnnaBridge | 163:e59c8e839560 | 6382 | |
| AnnaBridge | 163:e59c8e839560 | 6383 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 6384 | -- RIT Register Masks |
| AnnaBridge | 163:e59c8e839560 | 6385 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 6386 | |
| AnnaBridge | 163:e59c8e839560 | 6387 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6388 | * @addtogroup RIT_Register_Masks RIT Register Masks |
| AnnaBridge | 163:e59c8e839560 | 6389 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 6390 | */ |
| AnnaBridge | 163:e59c8e839560 | 6391 | |
| AnnaBridge | 163:e59c8e839560 | 6392 | /*! @name COMPVAL - Compare value LSB register */ |
| AnnaBridge | 163:e59c8e839560 | 6393 | #define RIT_COMPVAL_RICOMP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6394 | #define RIT_COMPVAL_RICOMP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6395 | #define RIT_COMPVAL_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6396 | |
| AnnaBridge | 163:e59c8e839560 | 6397 | /*! @name MASK - Mask LSB register */ |
| AnnaBridge | 163:e59c8e839560 | 6398 | #define RIT_MASK_RIMASK_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6399 | #define RIT_MASK_RIMASK_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6400 | #define RIT_MASK_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6401 | |
| AnnaBridge | 163:e59c8e839560 | 6402 | /*! @name CTRL - Control register */ |
| AnnaBridge | 163:e59c8e839560 | 6403 | #define RIT_CTRL_RITINT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 6404 | #define RIT_CTRL_RITINT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6405 | #define RIT_CTRL_RITINT(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6406 | #define RIT_CTRL_RITENCLR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 6407 | #define RIT_CTRL_RITENCLR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 6408 | #define RIT_CTRL_RITENCLR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6409 | #define RIT_CTRL_RITENBR_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 6410 | #define RIT_CTRL_RITENBR_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 6411 | #define RIT_CTRL_RITENBR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6412 | #define RIT_CTRL_RITEN_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 6413 | #define RIT_CTRL_RITEN_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 6414 | #define RIT_CTRL_RITEN(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6415 | |
| AnnaBridge | 163:e59c8e839560 | 6416 | /*! @name COUNTER - Counter LSB register */ |
| AnnaBridge | 163:e59c8e839560 | 6417 | #define RIT_COUNTER_RICOUNTER_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6418 | #define RIT_COUNTER_RICOUNTER_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6419 | #define RIT_COUNTER_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6420 | |
| AnnaBridge | 163:e59c8e839560 | 6421 | /*! @name COMPVAL_H - Compare value MSB register */ |
| AnnaBridge | 163:e59c8e839560 | 6422 | #define RIT_COMPVAL_H_RICOMP_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6423 | #define RIT_COMPVAL_H_RICOMP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6424 | #define RIT_COMPVAL_H_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6425 | |
| AnnaBridge | 163:e59c8e839560 | 6426 | /*! @name MASK_H - Mask MSB register */ |
| AnnaBridge | 163:e59c8e839560 | 6427 | #define RIT_MASK_H_RIMASK_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6428 | #define RIT_MASK_H_RIMASK_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6429 | #define RIT_MASK_H_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6430 | |
| AnnaBridge | 163:e59c8e839560 | 6431 | /*! @name COUNTER_H - Counter MSB register */ |
| AnnaBridge | 163:e59c8e839560 | 6432 | #define RIT_COUNTER_H_RICOUNTER_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6433 | #define RIT_COUNTER_H_RICOUNTER_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6434 | #define RIT_COUNTER_H_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6435 | |
| AnnaBridge | 163:e59c8e839560 | 6436 | |
| AnnaBridge | 163:e59c8e839560 | 6437 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6438 | * @} |
| AnnaBridge | 163:e59c8e839560 | 6439 | */ /* end of group RIT_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 6440 | |
| AnnaBridge | 163:e59c8e839560 | 6441 | |
| AnnaBridge | 163:e59c8e839560 | 6442 | /* RIT - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 6443 | /** Peripheral RIT base address */ |
| AnnaBridge | 163:e59c8e839560 | 6444 | #define RIT_BASE (0x4002D000u) |
| AnnaBridge | 163:e59c8e839560 | 6445 | /** Peripheral RIT base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 6446 | #define RIT ((RIT_Type *)RIT_BASE) |
| AnnaBridge | 163:e59c8e839560 | 6447 | /** Array initializer of RIT peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 6448 | #define RIT_BASE_ADDRS { RIT_BASE } |
| AnnaBridge | 163:e59c8e839560 | 6449 | /** Array initializer of RIT peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 6450 | #define RIT_BASE_PTRS { RIT } |
| AnnaBridge | 163:e59c8e839560 | 6451 | /** Interrupt vectors for the RIT peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 6452 | #define RIT_IRQS { RIT_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 6453 | |
| AnnaBridge | 163:e59c8e839560 | 6454 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6455 | * @} |
| AnnaBridge | 163:e59c8e839560 | 6456 | */ /* end of group RIT_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 6457 | |
| AnnaBridge | 163:e59c8e839560 | 6458 | |
| AnnaBridge | 163:e59c8e839560 | 6459 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 6460 | -- RTC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 6461 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 6462 | |
| AnnaBridge | 163:e59c8e839560 | 6463 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6464 | * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 6465 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 6466 | */ |
| AnnaBridge | 163:e59c8e839560 | 6467 | |
| AnnaBridge | 163:e59c8e839560 | 6468 | /** RTC - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 6469 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 6470 | __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 6471 | __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 6472 | __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 6473 | __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 6474 | uint8_t RESERVED_0[48]; |
| AnnaBridge | 163:e59c8e839560 | 6475 | __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 6476 | } RTC_Type; |
| AnnaBridge | 163:e59c8e839560 | 6477 | |
| AnnaBridge | 163:e59c8e839560 | 6478 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 6479 | -- RTC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 6480 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 6481 | |
| AnnaBridge | 163:e59c8e839560 | 6482 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6483 | * @addtogroup RTC_Register_Masks RTC Register Masks |
| AnnaBridge | 163:e59c8e839560 | 6484 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 6485 | */ |
| AnnaBridge | 163:e59c8e839560 | 6486 | |
| AnnaBridge | 163:e59c8e839560 | 6487 | /*! @name CTRL - RTC control register */ |
| AnnaBridge | 163:e59c8e839560 | 6488 | #define RTC_CTRL_SWRESET_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 6489 | #define RTC_CTRL_SWRESET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6490 | #define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6491 | #define RTC_CTRL_ALARM1HZ_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 6492 | #define RTC_CTRL_ALARM1HZ_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 6493 | #define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6494 | #define RTC_CTRL_WAKE1KHZ_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 6495 | #define RTC_CTRL_WAKE1KHZ_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 6496 | #define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6497 | #define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 6498 | #define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 6499 | #define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6500 | #define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 6501 | #define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 6502 | #define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6503 | #define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 6504 | #define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 6505 | #define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6506 | #define RTC_CTRL_RTC_EN_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 6507 | #define RTC_CTRL_RTC_EN_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 6508 | #define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6509 | #define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 6510 | #define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 6511 | #define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6512 | |
| AnnaBridge | 163:e59c8e839560 | 6513 | /*! @name MATCH - RTC match register */ |
| AnnaBridge | 163:e59c8e839560 | 6514 | #define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6515 | #define RTC_MATCH_MATVAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6516 | #define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6517 | |
| AnnaBridge | 163:e59c8e839560 | 6518 | /*! @name COUNT - RTC counter register */ |
| AnnaBridge | 163:e59c8e839560 | 6519 | #define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6520 | #define RTC_COUNT_VAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6521 | #define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6522 | |
| AnnaBridge | 163:e59c8e839560 | 6523 | /*! @name WAKE - High-resolution/wake-up timer control register */ |
| AnnaBridge | 163:e59c8e839560 | 6524 | #define RTC_WAKE_VAL_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6525 | #define RTC_WAKE_VAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6526 | #define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6527 | |
| AnnaBridge | 163:e59c8e839560 | 6528 | /*! @name GPREG - General Purpose register */ |
| AnnaBridge | 163:e59c8e839560 | 6529 | #define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6530 | #define RTC_GPREG_GPDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6531 | #define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6532 | |
| AnnaBridge | 163:e59c8e839560 | 6533 | /* The count of RTC_GPREG */ |
| AnnaBridge | 163:e59c8e839560 | 6534 | #define RTC_GPREG_COUNT (8U) |
| AnnaBridge | 163:e59c8e839560 | 6535 | |
| AnnaBridge | 163:e59c8e839560 | 6536 | |
| AnnaBridge | 163:e59c8e839560 | 6537 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6538 | * @} |
| AnnaBridge | 163:e59c8e839560 | 6539 | */ /* end of group RTC_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 6540 | |
| AnnaBridge | 163:e59c8e839560 | 6541 | |
| AnnaBridge | 163:e59c8e839560 | 6542 | /* RTC - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 6543 | /** Peripheral RTC base address */ |
| AnnaBridge | 163:e59c8e839560 | 6544 | #define RTC_BASE (0x4002C000u) |
| AnnaBridge | 163:e59c8e839560 | 6545 | /** Peripheral RTC base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 6546 | #define RTC ((RTC_Type *)RTC_BASE) |
| AnnaBridge | 163:e59c8e839560 | 6547 | /** Array initializer of RTC peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 6548 | #define RTC_BASE_ADDRS { RTC_BASE } |
| AnnaBridge | 163:e59c8e839560 | 6549 | /** Array initializer of RTC peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 6550 | #define RTC_BASE_PTRS { RTC } |
| AnnaBridge | 163:e59c8e839560 | 6551 | /** Interrupt vectors for the RTC peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 6552 | #define RTC_IRQS { RTC_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 6553 | |
| AnnaBridge | 163:e59c8e839560 | 6554 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6555 | * @} |
| AnnaBridge | 163:e59c8e839560 | 6556 | */ /* end of group RTC_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 6557 | |
| AnnaBridge | 163:e59c8e839560 | 6558 | |
| AnnaBridge | 163:e59c8e839560 | 6559 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 6560 | -- SCT Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 6561 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 6562 | |
| AnnaBridge | 163:e59c8e839560 | 6563 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6564 | * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 6565 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 6566 | */ |
| AnnaBridge | 163:e59c8e839560 | 6567 | |
| AnnaBridge | 163:e59c8e839560 | 6568 | /** SCT - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 6569 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 6570 | __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 6571 | __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 6572 | __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 6573 | __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 6574 | __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 6575 | __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 6576 | uint8_t RESERVED_0[40]; |
| AnnaBridge | 163:e59c8e839560 | 6577 | __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 6578 | __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ |
| AnnaBridge | 163:e59c8e839560 | 6579 | __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ |
| AnnaBridge | 163:e59c8e839560 | 6580 | __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ |
| AnnaBridge | 163:e59c8e839560 | 6581 | __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ |
| AnnaBridge | 163:e59c8e839560 | 6582 | __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ |
| AnnaBridge | 163:e59c8e839560 | 6583 | __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ |
| AnnaBridge | 163:e59c8e839560 | 6584 | __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 6585 | __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ |
| AnnaBridge | 163:e59c8e839560 | 6586 | uint8_t RESERVED_1[140]; |
| AnnaBridge | 163:e59c8e839560 | 6587 | __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ |
| AnnaBridge | 163:e59c8e839560 | 6588 | __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ |
| AnnaBridge | 163:e59c8e839560 | 6589 | __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ |
| AnnaBridge | 163:e59c8e839560 | 6590 | __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ |
| AnnaBridge | 163:e59c8e839560 | 6591 | union { /* offset: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 6592 | __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 6593 | __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 6594 | }; |
| AnnaBridge | 163:e59c8e839560 | 6595 | uint8_t RESERVED_2[216]; |
| AnnaBridge | 163:e59c8e839560 | 6596 | union { /* offset: 0x200 */ |
| AnnaBridge | 163:e59c8e839560 | 6597 | __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 6598 | __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 6599 | }; |
| AnnaBridge | 163:e59c8e839560 | 6600 | uint8_t RESERVED_3[216]; |
| AnnaBridge | 163:e59c8e839560 | 6601 | struct { /* offset: 0x300, array step: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 6602 | __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 6603 | __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 6604 | } EVENT[10]; |
| AnnaBridge | 163:e59c8e839560 | 6605 | uint8_t RESERVED_4[432]; |
| AnnaBridge | 163:e59c8e839560 | 6606 | struct { /* offset: 0x500, array step: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 6607 | __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 6608 | __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 6609 | } OUT[10]; |
| AnnaBridge | 163:e59c8e839560 | 6610 | } SCT_Type; |
| AnnaBridge | 163:e59c8e839560 | 6611 | |
| AnnaBridge | 163:e59c8e839560 | 6612 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 6613 | -- SCT Register Masks |
| AnnaBridge | 163:e59c8e839560 | 6614 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 6615 | |
| AnnaBridge | 163:e59c8e839560 | 6616 | /*! |
| AnnaBridge | 163:e59c8e839560 | 6617 | * @addtogroup SCT_Register_Masks SCT Register Masks |
| AnnaBridge | 163:e59c8e839560 | 6618 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 6619 | */ |
| AnnaBridge | 163:e59c8e839560 | 6620 | |
| AnnaBridge | 163:e59c8e839560 | 6621 | /*! @name CONFIG - SCT configuration register */ |
| AnnaBridge | 163:e59c8e839560 | 6622 | #define SCT_CONFIG_UNIFY_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 6623 | #define SCT_CONFIG_UNIFY_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6624 | #define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6625 | #define SCT_CONFIG_CLKMODE_MASK (0x6U) |
| AnnaBridge | 163:e59c8e839560 | 6626 | #define SCT_CONFIG_CLKMODE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 6627 | #define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6628 | #define SCT_CONFIG_CKSEL_MASK (0x78U) |
| AnnaBridge | 163:e59c8e839560 | 6629 | #define SCT_CONFIG_CKSEL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 6630 | #define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6631 | #define SCT_CONFIG_NORELAOD_L_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 6632 | #define SCT_CONFIG_NORELAOD_L_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 6633 | #define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6634 | #define SCT_CONFIG_NORELOAD_H_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 6635 | #define SCT_CONFIG_NORELOAD_H_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 6636 | #define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6637 | #define SCT_CONFIG_INSYNC_MASK (0x1E00U) |
| AnnaBridge | 163:e59c8e839560 | 6638 | #define SCT_CONFIG_INSYNC_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 6639 | #define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6640 | #define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 6641 | #define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 6642 | #define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6643 | #define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 6644 | #define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 6645 | #define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6646 | |
| AnnaBridge | 163:e59c8e839560 | 6647 | /*! @name CTRL - SCT control register */ |
| AnnaBridge | 163:e59c8e839560 | 6648 | #define SCT_CTRL_DOWN_L_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 6649 | #define SCT_CTRL_DOWN_L_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6650 | #define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6651 | #define SCT_CTRL_STOP_L_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 6652 | #define SCT_CTRL_STOP_L_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 6653 | #define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6654 | #define SCT_CTRL_HALT_L_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 6655 | #define SCT_CTRL_HALT_L_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 6656 | #define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6657 | #define SCT_CTRL_CLRCTR_L_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 6658 | #define SCT_CTRL_CLRCTR_L_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 6659 | #define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6660 | #define SCT_CTRL_BIDIR_L_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 6661 | #define SCT_CTRL_BIDIR_L_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 6662 | #define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6663 | #define SCT_CTRL_PRE_L_MASK (0x1FE0U) |
| AnnaBridge | 163:e59c8e839560 | 6664 | #define SCT_CTRL_PRE_L_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 6665 | #define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6666 | #define SCT_CTRL_DOWN_H_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 6667 | #define SCT_CTRL_DOWN_H_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 6668 | #define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6669 | #define SCT_CTRL_STOP_H_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 6670 | #define SCT_CTRL_STOP_H_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 6671 | #define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6672 | #define SCT_CTRL_HALT_H_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 6673 | #define SCT_CTRL_HALT_H_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 6674 | #define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6675 | #define SCT_CTRL_CLRCTR_H_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 6676 | #define SCT_CTRL_CLRCTR_H_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 6677 | #define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6678 | #define SCT_CTRL_BIDIR_H_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 6679 | #define SCT_CTRL_BIDIR_H_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 6680 | #define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6681 | #define SCT_CTRL_PRE_H_MASK (0x1FE00000U) |
| AnnaBridge | 163:e59c8e839560 | 6682 | #define SCT_CTRL_PRE_H_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 6683 | #define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6684 | |
| AnnaBridge | 163:e59c8e839560 | 6685 | /*! @name LIMIT - SCT limit event select register */ |
| AnnaBridge | 163:e59c8e839560 | 6686 | #define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6687 | #define SCT_LIMIT_LIMMSK_L_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6688 | #define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6689 | #define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 6690 | #define SCT_LIMIT_LIMMSK_H_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 6691 | #define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6692 | |
| AnnaBridge | 163:e59c8e839560 | 6693 | /*! @name HALT - SCT halt event select register */ |
| AnnaBridge | 163:e59c8e839560 | 6694 | #define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6695 | #define SCT_HALT_HALTMSK_L_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6696 | #define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6697 | #define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 6698 | #define SCT_HALT_HALTMSK_H_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 6699 | #define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6700 | |
| AnnaBridge | 163:e59c8e839560 | 6701 | /*! @name STOP - SCT stop event select register */ |
| AnnaBridge | 163:e59c8e839560 | 6702 | #define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6703 | #define SCT_STOP_STOPMSK_L_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6704 | #define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6705 | #define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 6706 | #define SCT_STOP_STOPMSK_H_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 6707 | #define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6708 | |
| AnnaBridge | 163:e59c8e839560 | 6709 | /*! @name START - SCT start event select register */ |
| AnnaBridge | 163:e59c8e839560 | 6710 | #define SCT_START_STARTMSK_L_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6711 | #define SCT_START_STARTMSK_L_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6712 | #define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6713 | #define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 6714 | #define SCT_START_STARTMSK_H_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 6715 | #define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6716 | |
| AnnaBridge | 163:e59c8e839560 | 6717 | /*! @name COUNT - SCT counter register */ |
| AnnaBridge | 163:e59c8e839560 | 6718 | #define SCT_COUNT_CTR_L_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6719 | #define SCT_COUNT_CTR_L_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6720 | #define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6721 | #define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 6722 | #define SCT_COUNT_CTR_H_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 6723 | #define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6724 | |
| AnnaBridge | 163:e59c8e839560 | 6725 | /*! @name STATE - SCT state register */ |
| AnnaBridge | 163:e59c8e839560 | 6726 | #define SCT_STATE_STATE_L_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 6727 | #define SCT_STATE_STATE_L_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6728 | #define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6729 | #define SCT_STATE_STATE_H_MASK (0x1F0000U) |
| AnnaBridge | 163:e59c8e839560 | 6730 | #define SCT_STATE_STATE_H_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 6731 | #define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6732 | |
| AnnaBridge | 163:e59c8e839560 | 6733 | /*! @name INPUT - SCT input register */ |
| AnnaBridge | 163:e59c8e839560 | 6734 | #define SCT_INPUT_AIN0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 6735 | #define SCT_INPUT_AIN0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6736 | #define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6737 | #define SCT_INPUT_AIN1_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 6738 | #define SCT_INPUT_AIN1_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 6739 | #define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6740 | #define SCT_INPUT_AIN2_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 6741 | #define SCT_INPUT_AIN2_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 6742 | #define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6743 | #define SCT_INPUT_AIN3_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 6744 | #define SCT_INPUT_AIN3_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 6745 | #define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6746 | #define SCT_INPUT_AIN4_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 6747 | #define SCT_INPUT_AIN4_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 6748 | #define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6749 | #define SCT_INPUT_AIN5_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 6750 | #define SCT_INPUT_AIN5_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 6751 | #define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6752 | #define SCT_INPUT_AIN6_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 6753 | #define SCT_INPUT_AIN6_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 6754 | #define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6755 | #define SCT_INPUT_AIN7_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 6756 | #define SCT_INPUT_AIN7_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 6757 | #define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6758 | #define SCT_INPUT_AIN8_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 6759 | #define SCT_INPUT_AIN8_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 6760 | #define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6761 | #define SCT_INPUT_AIN9_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 6762 | #define SCT_INPUT_AIN9_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 6763 | #define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6764 | #define SCT_INPUT_AIN10_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 6765 | #define SCT_INPUT_AIN10_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 6766 | #define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6767 | #define SCT_INPUT_AIN11_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 6768 | #define SCT_INPUT_AIN11_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 6769 | #define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6770 | #define SCT_INPUT_AIN12_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 6771 | #define SCT_INPUT_AIN12_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 6772 | #define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6773 | #define SCT_INPUT_AIN13_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 6774 | #define SCT_INPUT_AIN13_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 6775 | #define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6776 | #define SCT_INPUT_AIN14_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 6777 | #define SCT_INPUT_AIN14_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 6778 | #define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6779 | #define SCT_INPUT_AIN15_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 6780 | #define SCT_INPUT_AIN15_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 6781 | #define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6782 | #define SCT_INPUT_SIN0_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 6783 | #define SCT_INPUT_SIN0_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 6784 | #define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6785 | #define SCT_INPUT_SIN1_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 6786 | #define SCT_INPUT_SIN1_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 6787 | #define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6788 | #define SCT_INPUT_SIN2_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 6789 | #define SCT_INPUT_SIN2_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 6790 | #define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6791 | #define SCT_INPUT_SIN3_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 6792 | #define SCT_INPUT_SIN3_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 6793 | #define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6794 | #define SCT_INPUT_SIN4_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 6795 | #define SCT_INPUT_SIN4_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 6796 | #define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6797 | #define SCT_INPUT_SIN5_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 6798 | #define SCT_INPUT_SIN5_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 6799 | #define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6800 | #define SCT_INPUT_SIN6_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 6801 | #define SCT_INPUT_SIN6_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 6802 | #define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6803 | #define SCT_INPUT_SIN7_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 6804 | #define SCT_INPUT_SIN7_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 6805 | #define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6806 | #define SCT_INPUT_SIN8_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 6807 | #define SCT_INPUT_SIN8_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 6808 | #define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6809 | #define SCT_INPUT_SIN9_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 6810 | #define SCT_INPUT_SIN9_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 6811 | #define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6812 | #define SCT_INPUT_SIN10_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 6813 | #define SCT_INPUT_SIN10_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 6814 | #define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6815 | #define SCT_INPUT_SIN11_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 6816 | #define SCT_INPUT_SIN11_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 6817 | #define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6818 | #define SCT_INPUT_SIN12_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 6819 | #define SCT_INPUT_SIN12_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 6820 | #define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6821 | #define SCT_INPUT_SIN13_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 6822 | #define SCT_INPUT_SIN13_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 6823 | #define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6824 | #define SCT_INPUT_SIN14_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 6825 | #define SCT_INPUT_SIN14_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 6826 | #define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6827 | #define SCT_INPUT_SIN15_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 6828 | #define SCT_INPUT_SIN15_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 6829 | #define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6830 | |
| AnnaBridge | 163:e59c8e839560 | 6831 | /*! @name REGMODE - SCT match/capture mode register */ |
| AnnaBridge | 163:e59c8e839560 | 6832 | #define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6833 | #define SCT_REGMODE_REGMOD_L_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6834 | #define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6835 | #define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 6836 | #define SCT_REGMODE_REGMOD_H_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 6837 | #define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6838 | |
| AnnaBridge | 163:e59c8e839560 | 6839 | /*! @name OUTPUT - SCT output register */ |
| AnnaBridge | 163:e59c8e839560 | 6840 | #define SCT_OUTPUT_OUT_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6841 | #define SCT_OUTPUT_OUT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6842 | #define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6843 | |
| AnnaBridge | 163:e59c8e839560 | 6844 | /*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ |
| AnnaBridge | 163:e59c8e839560 | 6845 | #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 6846 | #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6847 | #define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6848 | #define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 6849 | #define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 6850 | #define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6851 | #define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 6852 | #define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 6853 | #define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6854 | #define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) |
| AnnaBridge | 163:e59c8e839560 | 6855 | #define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 6856 | #define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6857 | #define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) |
| AnnaBridge | 163:e59c8e839560 | 6858 | #define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 6859 | #define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6860 | #define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) |
| AnnaBridge | 163:e59c8e839560 | 6861 | #define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 6862 | #define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6863 | #define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) |
| AnnaBridge | 163:e59c8e839560 | 6864 | #define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 6865 | #define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6866 | #define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) |
| AnnaBridge | 163:e59c8e839560 | 6867 | #define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 6868 | #define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6869 | #define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) |
| AnnaBridge | 163:e59c8e839560 | 6870 | #define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 6871 | #define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6872 | #define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) |
| AnnaBridge | 163:e59c8e839560 | 6873 | #define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 6874 | #define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6875 | #define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) |
| AnnaBridge | 163:e59c8e839560 | 6876 | #define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 6877 | #define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6878 | #define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) |
| AnnaBridge | 163:e59c8e839560 | 6879 | #define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 6880 | #define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6881 | #define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) |
| AnnaBridge | 163:e59c8e839560 | 6882 | #define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 6883 | #define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6884 | #define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) |
| AnnaBridge | 163:e59c8e839560 | 6885 | #define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 6886 | #define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6887 | #define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) |
| AnnaBridge | 163:e59c8e839560 | 6888 | #define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 6889 | #define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6890 | #define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) |
| AnnaBridge | 163:e59c8e839560 | 6891 | #define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 6892 | #define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6893 | |
| AnnaBridge | 163:e59c8e839560 | 6894 | /*! @name RES - SCT conflict resolution register */ |
| AnnaBridge | 163:e59c8e839560 | 6895 | #define SCT_RES_O0RES_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 6896 | #define SCT_RES_O0RES_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6897 | #define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6898 | #define SCT_RES_O1RES_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 6899 | #define SCT_RES_O1RES_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 6900 | #define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6901 | #define SCT_RES_O2RES_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 6902 | #define SCT_RES_O2RES_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 6903 | #define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6904 | #define SCT_RES_O3RES_MASK (0xC0U) |
| AnnaBridge | 163:e59c8e839560 | 6905 | #define SCT_RES_O3RES_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 6906 | #define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6907 | #define SCT_RES_O4RES_MASK (0x300U) |
| AnnaBridge | 163:e59c8e839560 | 6908 | #define SCT_RES_O4RES_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 6909 | #define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6910 | #define SCT_RES_O5RES_MASK (0xC00U) |
| AnnaBridge | 163:e59c8e839560 | 6911 | #define SCT_RES_O5RES_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 6912 | #define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6913 | #define SCT_RES_O6RES_MASK (0x3000U) |
| AnnaBridge | 163:e59c8e839560 | 6914 | #define SCT_RES_O6RES_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 6915 | #define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6916 | #define SCT_RES_O7RES_MASK (0xC000U) |
| AnnaBridge | 163:e59c8e839560 | 6917 | #define SCT_RES_O7RES_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 6918 | #define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6919 | #define SCT_RES_O8RES_MASK (0x30000U) |
| AnnaBridge | 163:e59c8e839560 | 6920 | #define SCT_RES_O8RES_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 6921 | #define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6922 | #define SCT_RES_O9RES_MASK (0xC0000U) |
| AnnaBridge | 163:e59c8e839560 | 6923 | #define SCT_RES_O9RES_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 6924 | #define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6925 | #define SCT_RES_O10RES_MASK (0x300000U) |
| AnnaBridge | 163:e59c8e839560 | 6926 | #define SCT_RES_O10RES_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 6927 | #define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6928 | #define SCT_RES_O11RES_MASK (0xC00000U) |
| AnnaBridge | 163:e59c8e839560 | 6929 | #define SCT_RES_O11RES_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 6930 | #define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6931 | #define SCT_RES_O12RES_MASK (0x3000000U) |
| AnnaBridge | 163:e59c8e839560 | 6932 | #define SCT_RES_O12RES_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 6933 | #define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6934 | #define SCT_RES_O13RES_MASK (0xC000000U) |
| AnnaBridge | 163:e59c8e839560 | 6935 | #define SCT_RES_O13RES_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 6936 | #define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6937 | #define SCT_RES_O14RES_MASK (0x30000000U) |
| AnnaBridge | 163:e59c8e839560 | 6938 | #define SCT_RES_O14RES_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 6939 | #define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6940 | #define SCT_RES_O15RES_MASK (0xC0000000U) |
| AnnaBridge | 163:e59c8e839560 | 6941 | #define SCT_RES_O15RES_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 6942 | #define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6943 | |
| AnnaBridge | 163:e59c8e839560 | 6944 | /*! @name DMA0REQUEST - SCT DMA request 0 register */ |
| AnnaBridge | 163:e59c8e839560 | 6945 | #define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6946 | #define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6947 | #define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6948 | #define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 6949 | #define SCT_DMA0REQUEST_DRL0_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 6950 | #define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6951 | #define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 6952 | #define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 6953 | #define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6954 | |
| AnnaBridge | 163:e59c8e839560 | 6955 | /*! @name DMA1REQUEST - SCT DMA request 1 register */ |
| AnnaBridge | 163:e59c8e839560 | 6956 | #define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6957 | #define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6958 | #define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6959 | #define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 6960 | #define SCT_DMA1REQUEST_DRL1_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 6961 | #define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6962 | #define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 6963 | #define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 6964 | #define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6965 | |
| AnnaBridge | 163:e59c8e839560 | 6966 | /*! @name EVEN - SCT event interrupt enable register */ |
| AnnaBridge | 163:e59c8e839560 | 6967 | #define SCT_EVEN_IEN_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6968 | #define SCT_EVEN_IEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6969 | #define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6970 | |
| AnnaBridge | 163:e59c8e839560 | 6971 | /*! @name EVFLAG - SCT event flag register */ |
| AnnaBridge | 163:e59c8e839560 | 6972 | #define SCT_EVFLAG_FLAG_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6973 | #define SCT_EVFLAG_FLAG_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6974 | #define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6975 | |
| AnnaBridge | 163:e59c8e839560 | 6976 | /*! @name CONEN - SCT conflict interrupt enable register */ |
| AnnaBridge | 163:e59c8e839560 | 6977 | #define SCT_CONEN_NCEN_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6978 | #define SCT_CONEN_NCEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6979 | #define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6980 | |
| AnnaBridge | 163:e59c8e839560 | 6981 | /*! @name CONFLAG - SCT conflict flag register */ |
| AnnaBridge | 163:e59c8e839560 | 6982 | #define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6983 | #define SCT_CONFLAG_NCFLAG_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6984 | #define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6985 | #define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 6986 | #define SCT_CONFLAG_BUSERRL_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 6987 | #define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6988 | #define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 6989 | #define SCT_CONFLAG_BUSERRH_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 6990 | #define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6991 | |
| AnnaBridge | 163:e59c8e839560 | 6992 | /*! @name SCTCAP - SCT capture register of capture channel */ |
| AnnaBridge | 163:e59c8e839560 | 6993 | #define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 6994 | #define SCT_SCTCAP_CAPn_L_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 6995 | #define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6996 | #define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 6997 | #define SCT_SCTCAP_CAPn_H_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 6998 | #define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 6999 | |
| AnnaBridge | 163:e59c8e839560 | 7000 | /* The count of SCT_SCTCAP */ |
| AnnaBridge | 163:e59c8e839560 | 7001 | #define SCT_SCTCAP_COUNT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7002 | |
| AnnaBridge | 163:e59c8e839560 | 7003 | /*! @name SCTMATCH - SCT match value register of match channels */ |
| AnnaBridge | 163:e59c8e839560 | 7004 | #define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7005 | #define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7006 | #define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7007 | #define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 7008 | #define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 7009 | #define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7010 | |
| AnnaBridge | 163:e59c8e839560 | 7011 | /* The count of SCT_SCTMATCH */ |
| AnnaBridge | 163:e59c8e839560 | 7012 | #define SCT_SCTMATCH_COUNT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7013 | |
| AnnaBridge | 163:e59c8e839560 | 7014 | /*! @name SCTCAPCTRL - SCT capture control register */ |
| AnnaBridge | 163:e59c8e839560 | 7015 | #define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7016 | #define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7017 | #define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7018 | #define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 7019 | #define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 7020 | #define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7021 | |
| AnnaBridge | 163:e59c8e839560 | 7022 | /* The count of SCT_SCTCAPCTRL */ |
| AnnaBridge | 163:e59c8e839560 | 7023 | #define SCT_SCTCAPCTRL_COUNT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7024 | |
| AnnaBridge | 163:e59c8e839560 | 7025 | /*! @name SCTMATCHREL - SCT match reload value register */ |
| AnnaBridge | 163:e59c8e839560 | 7026 | #define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7027 | #define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7028 | #define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7029 | #define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 7030 | #define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 7031 | #define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7032 | |
| AnnaBridge | 163:e59c8e839560 | 7033 | /* The count of SCT_SCTMATCHREL */ |
| AnnaBridge | 163:e59c8e839560 | 7034 | #define SCT_SCTMATCHREL_COUNT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7035 | |
| AnnaBridge | 163:e59c8e839560 | 7036 | /*! @name EVENT_STATE - SCT event state register 0 */ |
| AnnaBridge | 163:e59c8e839560 | 7037 | #define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7038 | #define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7039 | #define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7040 | |
| AnnaBridge | 163:e59c8e839560 | 7041 | /* The count of SCT_EVENT_STATE */ |
| AnnaBridge | 163:e59c8e839560 | 7042 | #define SCT_EVENT_STATE_COUNT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7043 | |
| AnnaBridge | 163:e59c8e839560 | 7044 | /*! @name EVENT_CTRL - SCT event control register 0 */ |
| AnnaBridge | 163:e59c8e839560 | 7045 | #define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 7046 | #define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7047 | #define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7048 | #define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 7049 | #define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 7050 | #define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7051 | #define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 7052 | #define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 7053 | #define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7054 | #define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) |
| AnnaBridge | 163:e59c8e839560 | 7055 | #define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 7056 | #define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7057 | #define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) |
| AnnaBridge | 163:e59c8e839560 | 7058 | #define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7059 | #define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7060 | #define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) |
| AnnaBridge | 163:e59c8e839560 | 7061 | #define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 7062 | #define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7063 | #define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 7064 | #define SCT_EVENT_CTRL_STATELD_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 7065 | #define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7066 | #define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) |
| AnnaBridge | 163:e59c8e839560 | 7067 | #define SCT_EVENT_CTRL_STATEV_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 7068 | #define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7069 | #define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 7070 | #define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 7071 | #define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7072 | #define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) |
| AnnaBridge | 163:e59c8e839560 | 7073 | #define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 7074 | #define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7075 | |
| AnnaBridge | 163:e59c8e839560 | 7076 | /* The count of SCT_EVENT_CTRL */ |
| AnnaBridge | 163:e59c8e839560 | 7077 | #define SCT_EVENT_CTRL_COUNT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7078 | |
| AnnaBridge | 163:e59c8e839560 | 7079 | /*! @name OUT_SET - SCT output 0 set register */ |
| AnnaBridge | 163:e59c8e839560 | 7080 | #define SCT_OUT_SET_SET_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7081 | #define SCT_OUT_SET_SET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7082 | #define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7083 | |
| AnnaBridge | 163:e59c8e839560 | 7084 | /* The count of SCT_OUT_SET */ |
| AnnaBridge | 163:e59c8e839560 | 7085 | #define SCT_OUT_SET_COUNT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7086 | |
| AnnaBridge | 163:e59c8e839560 | 7087 | /*! @name OUT_CLR - SCT output 0 clear register */ |
| AnnaBridge | 163:e59c8e839560 | 7088 | #define SCT_OUT_CLR_CLR_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7089 | #define SCT_OUT_CLR_CLR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7090 | #define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7091 | |
| AnnaBridge | 163:e59c8e839560 | 7092 | /* The count of SCT_OUT_CLR */ |
| AnnaBridge | 163:e59c8e839560 | 7093 | #define SCT_OUT_CLR_COUNT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7094 | |
| AnnaBridge | 163:e59c8e839560 | 7095 | |
| AnnaBridge | 163:e59c8e839560 | 7096 | /*! |
| AnnaBridge | 163:e59c8e839560 | 7097 | * @} |
| AnnaBridge | 163:e59c8e839560 | 7098 | */ /* end of group SCT_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 7099 | |
| AnnaBridge | 163:e59c8e839560 | 7100 | |
| AnnaBridge | 163:e59c8e839560 | 7101 | /* SCT - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 7102 | /** Peripheral SCT0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 7103 | #define SCT0_BASE (0x40085000u) |
| AnnaBridge | 163:e59c8e839560 | 7104 | /** Peripheral SCT0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 7105 | #define SCT0 ((SCT_Type *)SCT0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 7106 | /** Array initializer of SCT peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 7107 | #define SCT_BASE_ADDRS { SCT0_BASE } |
| AnnaBridge | 163:e59c8e839560 | 7108 | /** Array initializer of SCT peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 7109 | #define SCT_BASE_PTRS { SCT0 } |
| AnnaBridge | 163:e59c8e839560 | 7110 | /** Interrupt vectors for the SCT peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 7111 | #define SCT_IRQS { SCT0_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 7112 | |
| AnnaBridge | 163:e59c8e839560 | 7113 | /*! |
| AnnaBridge | 163:e59c8e839560 | 7114 | * @} |
| AnnaBridge | 163:e59c8e839560 | 7115 | */ /* end of group SCT_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 7116 | |
| AnnaBridge | 163:e59c8e839560 | 7117 | |
| AnnaBridge | 163:e59c8e839560 | 7118 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 7119 | -- SDIF Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 7120 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 7121 | |
| AnnaBridge | 163:e59c8e839560 | 7122 | /*! |
| AnnaBridge | 163:e59c8e839560 | 7123 | * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 7124 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 7125 | */ |
| AnnaBridge | 163:e59c8e839560 | 7126 | |
| AnnaBridge | 163:e59c8e839560 | 7127 | /** SDIF - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 7128 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 7129 | __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 7130 | __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 7131 | __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 7132 | uint8_t RESERVED_0[4]; |
| AnnaBridge | 163:e59c8e839560 | 7133 | __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 7134 | __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 7135 | __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 7136 | __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 7137 | __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 7138 | __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 7139 | __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 7140 | __IO uint32_t CMD; /**< Command register, offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 7141 | __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 7142 | __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 7143 | __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */ |
| AnnaBridge | 163:e59c8e839560 | 7144 | __IO uint32_t STATUS; /**< Status register, offset: 0x48 */ |
| AnnaBridge | 163:e59c8e839560 | 7145 | __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */ |
| AnnaBridge | 163:e59c8e839560 | 7146 | __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */ |
| AnnaBridge | 163:e59c8e839560 | 7147 | __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */ |
| AnnaBridge | 163:e59c8e839560 | 7148 | uint8_t RESERVED_1[4]; |
| AnnaBridge | 163:e59c8e839560 | 7149 | __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 7150 | __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */ |
| AnnaBridge | 163:e59c8e839560 | 7151 | __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */ |
| AnnaBridge | 163:e59c8e839560 | 7152 | uint8_t RESERVED_2[16]; |
| AnnaBridge | 163:e59c8e839560 | 7153 | __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */ |
| AnnaBridge | 163:e59c8e839560 | 7154 | uint8_t RESERVED_3[4]; |
| AnnaBridge | 163:e59c8e839560 | 7155 | __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */ |
| AnnaBridge | 163:e59c8e839560 | 7156 | __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */ |
| AnnaBridge | 163:e59c8e839560 | 7157 | __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */ |
| AnnaBridge | 163:e59c8e839560 | 7158 | __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */ |
| AnnaBridge | 163:e59c8e839560 | 7159 | __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */ |
| AnnaBridge | 163:e59c8e839560 | 7160 | __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */ |
| AnnaBridge | 163:e59c8e839560 | 7161 | __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */ |
| AnnaBridge | 163:e59c8e839560 | 7162 | uint8_t RESERVED_4[100]; |
| AnnaBridge | 163:e59c8e839560 | 7163 | __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */ |
| AnnaBridge | 163:e59c8e839560 | 7164 | __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */ |
| AnnaBridge | 163:e59c8e839560 | 7165 | uint8_t RESERVED_5[248]; |
| AnnaBridge | 163:e59c8e839560 | 7166 | __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 7167 | } SDIF_Type; |
| AnnaBridge | 163:e59c8e839560 | 7168 | |
| AnnaBridge | 163:e59c8e839560 | 7169 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 7170 | -- SDIF Register Masks |
| AnnaBridge | 163:e59c8e839560 | 7171 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 7172 | |
| AnnaBridge | 163:e59c8e839560 | 7173 | /*! |
| AnnaBridge | 163:e59c8e839560 | 7174 | * @addtogroup SDIF_Register_Masks SDIF Register Masks |
| AnnaBridge | 163:e59c8e839560 | 7175 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 7176 | */ |
| AnnaBridge | 163:e59c8e839560 | 7177 | |
| AnnaBridge | 163:e59c8e839560 | 7178 | /*! @name CTRL - Control register */ |
| AnnaBridge | 163:e59c8e839560 | 7179 | #define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7180 | #define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7181 | #define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7182 | #define SDIF_CTRL_FIFO_RESET_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7183 | #define SDIF_CTRL_FIFO_RESET_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7184 | #define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7185 | #define SDIF_CTRL_DMA_RESET_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7186 | #define SDIF_CTRL_DMA_RESET_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7187 | #define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7188 | #define SDIF_CTRL_INT_ENABLE_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 7189 | #define SDIF_CTRL_INT_ENABLE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 7190 | #define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7191 | #define SDIF_CTRL_READ_WAIT_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 7192 | #define SDIF_CTRL_READ_WAIT_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 7193 | #define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7194 | #define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 7195 | #define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 7196 | #define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7197 | #define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 7198 | #define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 7199 | #define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7200 | #define SDIF_CTRL_SEND_CCSD_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 7201 | #define SDIF_CTRL_SEND_CCSD_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 7202 | #define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7203 | #define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 7204 | #define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7205 | #define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7206 | #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 7207 | #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 7208 | #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7209 | #define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 7210 | #define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 7211 | #define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7212 | #define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 7213 | #define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 7214 | #define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7215 | #define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 7216 | #define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 7217 | #define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7218 | #define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 7219 | #define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 7220 | #define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7221 | |
| AnnaBridge | 163:e59c8e839560 | 7222 | /*! @name PWREN - Power Enable register */ |
| AnnaBridge | 163:e59c8e839560 | 7223 | #define SDIF_PWREN_POWER_ENABLE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7224 | #define SDIF_PWREN_POWER_ENABLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7225 | #define SDIF_PWREN_POWER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7226 | |
| AnnaBridge | 163:e59c8e839560 | 7227 | /*! @name CLKDIV - Clock Divider register */ |
| AnnaBridge | 163:e59c8e839560 | 7228 | #define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 7229 | #define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7230 | #define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7231 | |
| AnnaBridge | 163:e59c8e839560 | 7232 | /*! @name CLKENA - Clock Enable register */ |
| AnnaBridge | 163:e59c8e839560 | 7233 | #define SDIF_CLKENA_CCLK_ENABLE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7234 | #define SDIF_CLKENA_CCLK_ENABLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7235 | #define SDIF_CLKENA_CCLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7236 | #define SDIF_CLKENA_CCLK_LOW_POWER_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 7237 | #define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 7238 | #define SDIF_CLKENA_CCLK_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7239 | |
| AnnaBridge | 163:e59c8e839560 | 7240 | /*! @name TMOUT - Time-out register */ |
| AnnaBridge | 163:e59c8e839560 | 7241 | #define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 7242 | #define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7243 | #define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7244 | #define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) |
| AnnaBridge | 163:e59c8e839560 | 7245 | #define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 7246 | #define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7247 | |
| AnnaBridge | 163:e59c8e839560 | 7248 | /*! @name CTYPE - Card Type register */ |
| AnnaBridge | 163:e59c8e839560 | 7249 | #define SDIF_CTYPE_CARD_WIDTH0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7250 | #define SDIF_CTYPE_CARD_WIDTH0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7251 | #define SDIF_CTYPE_CARD_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7252 | #define SDIF_CTYPE_CARD_WIDTH1_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 7253 | #define SDIF_CTYPE_CARD_WIDTH1_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 7254 | #define SDIF_CTYPE_CARD_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7255 | |
| AnnaBridge | 163:e59c8e839560 | 7256 | /*! @name BLKSIZ - Block Size register */ |
| AnnaBridge | 163:e59c8e839560 | 7257 | #define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7258 | #define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7259 | #define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7260 | |
| AnnaBridge | 163:e59c8e839560 | 7261 | /*! @name BYTCNT - Byte Count register */ |
| AnnaBridge | 163:e59c8e839560 | 7262 | #define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7263 | #define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7264 | #define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7265 | |
| AnnaBridge | 163:e59c8e839560 | 7266 | /*! @name INTMASK - Interrupt Mask register */ |
| AnnaBridge | 163:e59c8e839560 | 7267 | #define SDIF_INTMASK_CDET_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7268 | #define SDIF_INTMASK_CDET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7269 | #define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7270 | #define SDIF_INTMASK_RE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7271 | #define SDIF_INTMASK_RE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7272 | #define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7273 | #define SDIF_INTMASK_CDONE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7274 | #define SDIF_INTMASK_CDONE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7275 | #define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7276 | #define SDIF_INTMASK_DTO_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 7277 | #define SDIF_INTMASK_DTO_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 7278 | #define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7279 | #define SDIF_INTMASK_TXDR_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 7280 | #define SDIF_INTMASK_TXDR_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 7281 | #define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7282 | #define SDIF_INTMASK_RXDR_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 7283 | #define SDIF_INTMASK_RXDR_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 7284 | #define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7285 | #define SDIF_INTMASK_RCRC_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 7286 | #define SDIF_INTMASK_RCRC_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 7287 | #define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7288 | #define SDIF_INTMASK_DCRC_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 7289 | #define SDIF_INTMASK_DCRC_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 7290 | #define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7291 | #define SDIF_INTMASK_RTO_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 7292 | #define SDIF_INTMASK_RTO_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 7293 | #define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7294 | #define SDIF_INTMASK_DRTO_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 7295 | #define SDIF_INTMASK_DRTO_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 7296 | #define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7297 | #define SDIF_INTMASK_HTO_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 7298 | #define SDIF_INTMASK_HTO_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7299 | #define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7300 | #define SDIF_INTMASK_FRUN_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 7301 | #define SDIF_INTMASK_FRUN_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 7302 | #define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7303 | #define SDIF_INTMASK_HLE_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 7304 | #define SDIF_INTMASK_HLE_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 7305 | #define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7306 | #define SDIF_INTMASK_SBE_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 7307 | #define SDIF_INTMASK_SBE_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 7308 | #define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7309 | #define SDIF_INTMASK_ACD_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 7310 | #define SDIF_INTMASK_ACD_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 7311 | #define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7312 | #define SDIF_INTMASK_EBE_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 7313 | #define SDIF_INTMASK_EBE_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 7314 | #define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7315 | #define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 7316 | #define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 7317 | #define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7318 | |
| AnnaBridge | 163:e59c8e839560 | 7319 | /*! @name CMDARG - Command Argument register */ |
| AnnaBridge | 163:e59c8e839560 | 7320 | #define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7321 | #define SDIF_CMDARG_CMD_ARG_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7322 | #define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7323 | |
| AnnaBridge | 163:e59c8e839560 | 7324 | /*! @name CMD - Command register */ |
| AnnaBridge | 163:e59c8e839560 | 7325 | #define SDIF_CMD_CMD_INDEX_MASK (0x3FU) |
| AnnaBridge | 163:e59c8e839560 | 7326 | #define SDIF_CMD_CMD_INDEX_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7327 | #define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7328 | #define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 7329 | #define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 7330 | #define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7331 | #define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 7332 | #define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 7333 | #define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7334 | #define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 7335 | #define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 7336 | #define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7337 | #define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 7338 | #define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 7339 | #define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7340 | #define SDIF_CMD_READ_WRITE_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 7341 | #define SDIF_CMD_READ_WRITE_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7342 | #define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7343 | #define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 7344 | #define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 7345 | #define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7346 | #define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 7347 | #define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 7348 | #define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7349 | #define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 7350 | #define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 7351 | #define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7352 | #define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 7353 | #define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 7354 | #define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7355 | #define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 7356 | #define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 7357 | #define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7358 | #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 7359 | #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 7360 | #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7361 | #define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 7362 | #define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 7363 | #define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7364 | #define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 7365 | #define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 7366 | #define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7367 | #define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 7368 | #define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 7369 | #define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7370 | #define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 7371 | #define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 7372 | #define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7373 | #define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 7374 | #define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 7375 | #define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7376 | #define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 7377 | #define SDIF_CMD_BOOT_MODE_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 7378 | #define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7379 | #define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 7380 | #define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 7381 | #define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7382 | #define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 7383 | #define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 7384 | #define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7385 | #define SDIF_CMD_START_CMD_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 7386 | #define SDIF_CMD_START_CMD_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 7387 | #define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7388 | |
| AnnaBridge | 163:e59c8e839560 | 7389 | /*! @name RESP - Response register */ |
| AnnaBridge | 163:e59c8e839560 | 7390 | #define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7391 | #define SDIF_RESP_RESPONSE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7392 | #define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7393 | |
| AnnaBridge | 163:e59c8e839560 | 7394 | /* The count of SDIF_RESP */ |
| AnnaBridge | 163:e59c8e839560 | 7395 | #define SDIF_RESP_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 7396 | |
| AnnaBridge | 163:e59c8e839560 | 7397 | /*! @name MINTSTS - Masked Interrupt Status register */ |
| AnnaBridge | 163:e59c8e839560 | 7398 | #define SDIF_MINTSTS_CDET_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7399 | #define SDIF_MINTSTS_CDET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7400 | #define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7401 | #define SDIF_MINTSTS_RE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7402 | #define SDIF_MINTSTS_RE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7403 | #define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7404 | #define SDIF_MINTSTS_CDONE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7405 | #define SDIF_MINTSTS_CDONE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7406 | #define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7407 | #define SDIF_MINTSTS_DTO_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 7408 | #define SDIF_MINTSTS_DTO_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 7409 | #define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7410 | #define SDIF_MINTSTS_TXDR_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 7411 | #define SDIF_MINTSTS_TXDR_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 7412 | #define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7413 | #define SDIF_MINTSTS_RXDR_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 7414 | #define SDIF_MINTSTS_RXDR_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 7415 | #define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7416 | #define SDIF_MINTSTS_RCRC_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 7417 | #define SDIF_MINTSTS_RCRC_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 7418 | #define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7419 | #define SDIF_MINTSTS_DCRC_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 7420 | #define SDIF_MINTSTS_DCRC_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 7421 | #define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7422 | #define SDIF_MINTSTS_RTO_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 7423 | #define SDIF_MINTSTS_RTO_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 7424 | #define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7425 | #define SDIF_MINTSTS_DRTO_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 7426 | #define SDIF_MINTSTS_DRTO_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 7427 | #define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7428 | #define SDIF_MINTSTS_HTO_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 7429 | #define SDIF_MINTSTS_HTO_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7430 | #define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7431 | #define SDIF_MINTSTS_FRUN_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 7432 | #define SDIF_MINTSTS_FRUN_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 7433 | #define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7434 | #define SDIF_MINTSTS_HLE_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 7435 | #define SDIF_MINTSTS_HLE_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 7436 | #define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7437 | #define SDIF_MINTSTS_SBE_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 7438 | #define SDIF_MINTSTS_SBE_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 7439 | #define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7440 | #define SDIF_MINTSTS_ACD_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 7441 | #define SDIF_MINTSTS_ACD_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 7442 | #define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7443 | #define SDIF_MINTSTS_EBE_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 7444 | #define SDIF_MINTSTS_EBE_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 7445 | #define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7446 | #define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 7447 | #define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 7448 | #define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7449 | |
| AnnaBridge | 163:e59c8e839560 | 7450 | /*! @name RINTSTS - Raw Interrupt Status register */ |
| AnnaBridge | 163:e59c8e839560 | 7451 | #define SDIF_RINTSTS_CDET_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7452 | #define SDIF_RINTSTS_CDET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7453 | #define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7454 | #define SDIF_RINTSTS_RE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7455 | #define SDIF_RINTSTS_RE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7456 | #define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7457 | #define SDIF_RINTSTS_CDONE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7458 | #define SDIF_RINTSTS_CDONE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7459 | #define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7460 | #define SDIF_RINTSTS_DTO_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 7461 | #define SDIF_RINTSTS_DTO_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 7462 | #define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7463 | #define SDIF_RINTSTS_TXDR_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 7464 | #define SDIF_RINTSTS_TXDR_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 7465 | #define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7466 | #define SDIF_RINTSTS_RXDR_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 7467 | #define SDIF_RINTSTS_RXDR_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 7468 | #define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7469 | #define SDIF_RINTSTS_RCRC_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 7470 | #define SDIF_RINTSTS_RCRC_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 7471 | #define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7472 | #define SDIF_RINTSTS_DCRC_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 7473 | #define SDIF_RINTSTS_DCRC_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 7474 | #define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7475 | #define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 7476 | #define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 7477 | #define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7478 | #define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 7479 | #define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 7480 | #define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7481 | #define SDIF_RINTSTS_HTO_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 7482 | #define SDIF_RINTSTS_HTO_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7483 | #define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7484 | #define SDIF_RINTSTS_FRUN_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 7485 | #define SDIF_RINTSTS_FRUN_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 7486 | #define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7487 | #define SDIF_RINTSTS_HLE_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 7488 | #define SDIF_RINTSTS_HLE_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 7489 | #define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7490 | #define SDIF_RINTSTS_SBE_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 7491 | #define SDIF_RINTSTS_SBE_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 7492 | #define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7493 | #define SDIF_RINTSTS_ACD_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 7494 | #define SDIF_RINTSTS_ACD_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 7495 | #define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7496 | #define SDIF_RINTSTS_EBE_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 7497 | #define SDIF_RINTSTS_EBE_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 7498 | #define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7499 | #define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 7500 | #define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 7501 | #define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7502 | |
| AnnaBridge | 163:e59c8e839560 | 7503 | /*! @name STATUS - Status register */ |
| AnnaBridge | 163:e59c8e839560 | 7504 | #define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7505 | #define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7506 | #define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7507 | #define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7508 | #define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7509 | #define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7510 | #define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7511 | #define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7512 | #define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7513 | #define SDIF_STATUS_FIFO_FULL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 7514 | #define SDIF_STATUS_FIFO_FULL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 7515 | #define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7516 | #define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) |
| AnnaBridge | 163:e59c8e839560 | 7517 | #define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 7518 | #define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7519 | #define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 7520 | #define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 7521 | #define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7522 | #define SDIF_STATUS_DATA_BUSY_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 7523 | #define SDIF_STATUS_DATA_BUSY_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 7524 | #define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7525 | #define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 7526 | #define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7527 | #define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7528 | #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) |
| AnnaBridge | 163:e59c8e839560 | 7529 | #define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 7530 | #define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7531 | #define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) |
| AnnaBridge | 163:e59c8e839560 | 7532 | #define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 7533 | #define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7534 | #define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 7535 | #define SDIF_STATUS_DMA_ACK_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 7536 | #define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7537 | #define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 7538 | #define SDIF_STATUS_DMA_REQ_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 7539 | #define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7540 | |
| AnnaBridge | 163:e59c8e839560 | 7541 | /*! @name FIFOTH - FIFO Threshold Watermark register */ |
| AnnaBridge | 163:e59c8e839560 | 7542 | #define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7543 | #define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7544 | #define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7545 | #define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 7546 | #define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 7547 | #define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7548 | #define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) |
| AnnaBridge | 163:e59c8e839560 | 7549 | #define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 7550 | #define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7551 | |
| AnnaBridge | 163:e59c8e839560 | 7552 | /*! @name CDETECT - Card Detect register */ |
| AnnaBridge | 163:e59c8e839560 | 7553 | #define SDIF_CDETECT_CARD_DETECT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7554 | #define SDIF_CDETECT_CARD_DETECT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7555 | #define SDIF_CDETECT_CARD_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7556 | |
| AnnaBridge | 163:e59c8e839560 | 7557 | /*! @name WRTPRT - Write Protect register */ |
| AnnaBridge | 163:e59c8e839560 | 7558 | #define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7559 | #define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7560 | #define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7561 | |
| AnnaBridge | 163:e59c8e839560 | 7562 | /*! @name TCBCNT - Transferred CIU Card Byte Count register */ |
| AnnaBridge | 163:e59c8e839560 | 7563 | #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7564 | #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7565 | #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7566 | |
| AnnaBridge | 163:e59c8e839560 | 7567 | /*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ |
| AnnaBridge | 163:e59c8e839560 | 7568 | #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7569 | #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7570 | #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7571 | |
| AnnaBridge | 163:e59c8e839560 | 7572 | /*! @name DEBNCE - Debounce Count register */ |
| AnnaBridge | 163:e59c8e839560 | 7573 | #define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7574 | #define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7575 | #define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7576 | |
| AnnaBridge | 163:e59c8e839560 | 7577 | /*! @name RST_N - Hardware Reset */ |
| AnnaBridge | 163:e59c8e839560 | 7578 | #define SDIF_RST_N_CARD_RESET_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7579 | #define SDIF_RST_N_CARD_RESET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7580 | #define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7581 | |
| AnnaBridge | 163:e59c8e839560 | 7582 | /*! @name BMOD - Bus Mode register */ |
| AnnaBridge | 163:e59c8e839560 | 7583 | #define SDIF_BMOD_SWR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7584 | #define SDIF_BMOD_SWR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7585 | #define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7586 | #define SDIF_BMOD_FB_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7587 | #define SDIF_BMOD_FB_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7588 | #define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7589 | #define SDIF_BMOD_DSL_MASK (0x7CU) |
| AnnaBridge | 163:e59c8e839560 | 7590 | #define SDIF_BMOD_DSL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7591 | #define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7592 | #define SDIF_BMOD_DE_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 7593 | #define SDIF_BMOD_DE_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 7594 | #define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7595 | #define SDIF_BMOD_PBL_MASK (0x700U) |
| AnnaBridge | 163:e59c8e839560 | 7596 | #define SDIF_BMOD_PBL_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 7597 | #define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7598 | |
| AnnaBridge | 163:e59c8e839560 | 7599 | /*! @name PLDMND - Poll Demand register */ |
| AnnaBridge | 163:e59c8e839560 | 7600 | #define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7601 | #define SDIF_PLDMND_PD_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7602 | #define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7603 | |
| AnnaBridge | 163:e59c8e839560 | 7604 | /*! @name DBADDR - Descriptor List Base Address register */ |
| AnnaBridge | 163:e59c8e839560 | 7605 | #define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7606 | #define SDIF_DBADDR_SDL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7607 | #define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7608 | |
| AnnaBridge | 163:e59c8e839560 | 7609 | /*! @name IDSTS - Internal DMAC Status register */ |
| AnnaBridge | 163:e59c8e839560 | 7610 | #define SDIF_IDSTS_TI_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7611 | #define SDIF_IDSTS_TI_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7612 | #define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7613 | #define SDIF_IDSTS_RI_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7614 | #define SDIF_IDSTS_RI_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7615 | #define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7616 | #define SDIF_IDSTS_FBE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7617 | #define SDIF_IDSTS_FBE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7618 | #define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7619 | #define SDIF_IDSTS_DU_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 7620 | #define SDIF_IDSTS_DU_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 7621 | #define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7622 | #define SDIF_IDSTS_CES_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 7623 | #define SDIF_IDSTS_CES_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 7624 | #define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7625 | #define SDIF_IDSTS_NIS_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 7626 | #define SDIF_IDSTS_NIS_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 7627 | #define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7628 | #define SDIF_IDSTS_AIS_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 7629 | #define SDIF_IDSTS_AIS_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 7630 | #define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7631 | #define SDIF_IDSTS_EB_MASK (0x1C00U) |
| AnnaBridge | 163:e59c8e839560 | 7632 | #define SDIF_IDSTS_EB_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 7633 | #define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7634 | #define SDIF_IDSTS_FSM_MASK (0x1E000U) |
| AnnaBridge | 163:e59c8e839560 | 7635 | #define SDIF_IDSTS_FSM_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 7636 | #define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7637 | |
| AnnaBridge | 163:e59c8e839560 | 7638 | /*! @name IDINTEN - Internal DMAC Interrupt Enable register */ |
| AnnaBridge | 163:e59c8e839560 | 7639 | #define SDIF_IDINTEN_TI_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7640 | #define SDIF_IDINTEN_TI_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7641 | #define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7642 | #define SDIF_IDINTEN_RI_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7643 | #define SDIF_IDINTEN_RI_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7644 | #define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7645 | #define SDIF_IDINTEN_FBE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7646 | #define SDIF_IDINTEN_FBE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7647 | #define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7648 | #define SDIF_IDINTEN_DU_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 7649 | #define SDIF_IDINTEN_DU_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 7650 | #define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7651 | #define SDIF_IDINTEN_CES_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 7652 | #define SDIF_IDINTEN_CES_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 7653 | #define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7654 | #define SDIF_IDINTEN_NIS_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 7655 | #define SDIF_IDINTEN_NIS_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 7656 | #define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7657 | #define SDIF_IDINTEN_AIS_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 7658 | #define SDIF_IDINTEN_AIS_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 7659 | #define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7660 | |
| AnnaBridge | 163:e59c8e839560 | 7661 | /*! @name DSCADDR - Current Host Descriptor Address register */ |
| AnnaBridge | 163:e59c8e839560 | 7662 | #define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7663 | #define SDIF_DSCADDR_HDA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7664 | #define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7665 | |
| AnnaBridge | 163:e59c8e839560 | 7666 | /*! @name BUFADDR - Current Buffer Descriptor Address register */ |
| AnnaBridge | 163:e59c8e839560 | 7667 | #define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7668 | #define SDIF_BUFADDR_HBA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7669 | #define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7670 | |
| AnnaBridge | 163:e59c8e839560 | 7671 | /*! @name CARDTHRCTL - Card Threshold Control */ |
| AnnaBridge | 163:e59c8e839560 | 7672 | #define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7673 | #define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7674 | #define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7675 | #define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7676 | #define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7677 | #define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7678 | #define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 7679 | #define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 7680 | #define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7681 | |
| AnnaBridge | 163:e59c8e839560 | 7682 | /*! @name BACKENDPWR - Power control */ |
| AnnaBridge | 163:e59c8e839560 | 7683 | #define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7684 | #define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7685 | #define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7686 | |
| AnnaBridge | 163:e59c8e839560 | 7687 | /*! @name FIFO - SDIF FIFO */ |
| AnnaBridge | 163:e59c8e839560 | 7688 | #define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7689 | #define SDIF_FIFO_DATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7690 | #define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7691 | |
| AnnaBridge | 163:e59c8e839560 | 7692 | /* The count of SDIF_FIFO */ |
| AnnaBridge | 163:e59c8e839560 | 7693 | #define SDIF_FIFO_COUNT (64U) |
| AnnaBridge | 163:e59c8e839560 | 7694 | |
| AnnaBridge | 163:e59c8e839560 | 7695 | |
| AnnaBridge | 163:e59c8e839560 | 7696 | /*! |
| AnnaBridge | 163:e59c8e839560 | 7697 | * @} |
| AnnaBridge | 163:e59c8e839560 | 7698 | */ /* end of group SDIF_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 7699 | |
| AnnaBridge | 163:e59c8e839560 | 7700 | |
| AnnaBridge | 163:e59c8e839560 | 7701 | /* SDIF - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 7702 | /** Peripheral SDIF base address */ |
| AnnaBridge | 163:e59c8e839560 | 7703 | #define SDIF_BASE (0x4009B000u) |
| AnnaBridge | 163:e59c8e839560 | 7704 | /** Peripheral SDIF base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 7705 | #define SDIF ((SDIF_Type *)SDIF_BASE) |
| AnnaBridge | 163:e59c8e839560 | 7706 | /** Array initializer of SDIF peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 7707 | #define SDIF_BASE_ADDRS { SDIF_BASE } |
| AnnaBridge | 163:e59c8e839560 | 7708 | /** Array initializer of SDIF peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 7709 | #define SDIF_BASE_PTRS { SDIF } |
| AnnaBridge | 163:e59c8e839560 | 7710 | /** Interrupt vectors for the SDIF peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 7711 | #define SDIF_IRQS { SDIO_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 7712 | |
| AnnaBridge | 163:e59c8e839560 | 7713 | /*! |
| AnnaBridge | 163:e59c8e839560 | 7714 | * @} |
| AnnaBridge | 163:e59c8e839560 | 7715 | */ /* end of group SDIF_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 7716 | |
| AnnaBridge | 163:e59c8e839560 | 7717 | |
| AnnaBridge | 163:e59c8e839560 | 7718 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 7719 | -- SHA Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 7720 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 7721 | |
| AnnaBridge | 163:e59c8e839560 | 7722 | /*! |
| AnnaBridge | 163:e59c8e839560 | 7723 | * @addtogroup SHA_Peripheral_Access_Layer SHA Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 7724 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 7725 | */ |
| AnnaBridge | 163:e59c8e839560 | 7726 | |
| AnnaBridge | 163:e59c8e839560 | 7727 | /** SHA - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 7728 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 7729 | __IO uint32_t CTRL; /**< Control register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 7730 | __IO uint32_t STATUS; /**< Status register, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 7731 | __IO uint32_t INTENSET; /**< Interrupt Enable register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 7732 | __IO uint32_t INTENCLR; /**< Interrupt Clear register, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 7733 | __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 7734 | __IO uint32_t MEMADDR; /**< Memory Address register, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 7735 | uint8_t RESERVED_0[8]; |
| AnnaBridge | 163:e59c8e839560 | 7736 | __IO uint32_t INDATA; /**< Input Data register, offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 7737 | __IO uint32_t ALIAS[7]; /**< Alias register, array offset: 0x24, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 7738 | __I uint32_t DIGEST[8]; /**< Digest register, array offset: 0x40, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 7739 | } SHA_Type; |
| AnnaBridge | 163:e59c8e839560 | 7740 | |
| AnnaBridge | 163:e59c8e839560 | 7741 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 7742 | -- SHA Register Masks |
| AnnaBridge | 163:e59c8e839560 | 7743 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 7744 | |
| AnnaBridge | 163:e59c8e839560 | 7745 | /*! |
| AnnaBridge | 163:e59c8e839560 | 7746 | * @addtogroup SHA_Register_Masks SHA Register Masks |
| AnnaBridge | 163:e59c8e839560 | 7747 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 7748 | */ |
| AnnaBridge | 163:e59c8e839560 | 7749 | |
| AnnaBridge | 163:e59c8e839560 | 7750 | /*! @name CTRL - Control register */ |
| AnnaBridge | 163:e59c8e839560 | 7751 | #define SHA_CTRL_MODE_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 7752 | #define SHA_CTRL_MODE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7753 | #define SHA_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_MODE_SHIFT)) & SHA_CTRL_MODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7754 | #define SHA_CTRL_NEW_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 7755 | #define SHA_CTRL_NEW_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 7756 | #define SHA_CTRL_NEW(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_NEW_SHIFT)) & SHA_CTRL_NEW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7757 | #define SHA_CTRL_DMA_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 7758 | #define SHA_CTRL_DMA_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 7759 | #define SHA_CTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_DMA_SHIFT)) & SHA_CTRL_DMA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7760 | |
| AnnaBridge | 163:e59c8e839560 | 7761 | /*! @name STATUS - Status register */ |
| AnnaBridge | 163:e59c8e839560 | 7762 | #define SHA_STATUS_WAITING_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7763 | #define SHA_STATUS_WAITING_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7764 | #define SHA_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_WAITING_SHIFT)) & SHA_STATUS_WAITING_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7765 | #define SHA_STATUS_DIGEST_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7766 | #define SHA_STATUS_DIGEST_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7767 | #define SHA_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_DIGEST_SHIFT)) & SHA_STATUS_DIGEST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7768 | #define SHA_STATUS_ERROR_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7769 | #define SHA_STATUS_ERROR_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7770 | #define SHA_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_ERROR_SHIFT)) & SHA_STATUS_ERROR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7771 | |
| AnnaBridge | 163:e59c8e839560 | 7772 | /*! @name INTENSET - Interrupt Enable register */ |
| AnnaBridge | 163:e59c8e839560 | 7773 | #define SHA_INTENSET_WAITING_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7774 | #define SHA_INTENSET_WAITING_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7775 | #define SHA_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_WAITING_SHIFT)) & SHA_INTENSET_WAITING_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7776 | #define SHA_INTENSET_DIGEST_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7777 | #define SHA_INTENSET_DIGEST_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7778 | #define SHA_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_DIGEST_SHIFT)) & SHA_INTENSET_DIGEST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7779 | #define SHA_INTENSET_ERROR_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7780 | #define SHA_INTENSET_ERROR_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7781 | #define SHA_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_ERROR_SHIFT)) & SHA_INTENSET_ERROR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7782 | |
| AnnaBridge | 163:e59c8e839560 | 7783 | /*! @name INTENCLR - Interrupt Clear register */ |
| AnnaBridge | 163:e59c8e839560 | 7784 | #define SHA_INTENCLR_WAITING_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7785 | #define SHA_INTENCLR_WAITING_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7786 | #define SHA_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_WAITING_SHIFT)) & SHA_INTENCLR_WAITING_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7787 | #define SHA_INTENCLR_DIGEST_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7788 | #define SHA_INTENCLR_DIGEST_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7789 | #define SHA_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_DIGEST_SHIFT)) & SHA_INTENCLR_DIGEST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7790 | #define SHA_INTENCLR_ERROR_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7791 | #define SHA_INTENCLR_ERROR_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7792 | #define SHA_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_ERROR_SHIFT)) & SHA_INTENCLR_ERROR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7793 | |
| AnnaBridge | 163:e59c8e839560 | 7794 | /*! @name MEMCTRL - Memory Control register */ |
| AnnaBridge | 163:e59c8e839560 | 7795 | #define SHA_MEMCTRL_MASTER_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7796 | #define SHA_MEMCTRL_MASTER_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7797 | #define SHA_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_MASTER_SHIFT)) & SHA_MEMCTRL_MASTER_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7798 | #define SHA_MEMCTRL_COUNT_MASK (0x7FF0000U) |
| AnnaBridge | 163:e59c8e839560 | 7799 | #define SHA_MEMCTRL_COUNT_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 7800 | #define SHA_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_COUNT_SHIFT)) & SHA_MEMCTRL_COUNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7801 | |
| AnnaBridge | 163:e59c8e839560 | 7802 | /*! @name MEMADDR - Memory Address register */ |
| AnnaBridge | 163:e59c8e839560 | 7803 | #define SHA_MEMADDR_BASEADDR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7804 | #define SHA_MEMADDR_BASEADDR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7805 | #define SHA_MEMADDR_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMADDR_BASEADDR_SHIFT)) & SHA_MEMADDR_BASEADDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7806 | |
| AnnaBridge | 163:e59c8e839560 | 7807 | /*! @name INDATA - Input Data register */ |
| AnnaBridge | 163:e59c8e839560 | 7808 | #define SHA_INDATA_DATA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7809 | #define SHA_INDATA_DATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7810 | #define SHA_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SHA_INDATA_DATA_SHIFT)) & SHA_INDATA_DATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7811 | |
| AnnaBridge | 163:e59c8e839560 | 7812 | /*! @name ALIAS - Alias register */ |
| AnnaBridge | 163:e59c8e839560 | 7813 | #define SHA_ALIAS_DATA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7814 | #define SHA_ALIAS_DATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7815 | #define SHA_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << SHA_ALIAS_DATA_SHIFT)) & SHA_ALIAS_DATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7816 | |
| AnnaBridge | 163:e59c8e839560 | 7817 | /* The count of SHA_ALIAS */ |
| AnnaBridge | 163:e59c8e839560 | 7818 | #define SHA_ALIAS_COUNT (7U) |
| AnnaBridge | 163:e59c8e839560 | 7819 | |
| AnnaBridge | 163:e59c8e839560 | 7820 | /*! @name DIGEST - Digest register */ |
| AnnaBridge | 163:e59c8e839560 | 7821 | #define SHA_DIGEST_DIGEST_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 7822 | #define SHA_DIGEST_DIGEST_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7823 | #define SHA_DIGEST_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_DIGEST_DIGEST_SHIFT)) & SHA_DIGEST_DIGEST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7824 | |
| AnnaBridge | 163:e59c8e839560 | 7825 | /* The count of SHA_DIGEST */ |
| AnnaBridge | 163:e59c8e839560 | 7826 | #define SHA_DIGEST_COUNT (8U) |
| AnnaBridge | 163:e59c8e839560 | 7827 | |
| AnnaBridge | 163:e59c8e839560 | 7828 | |
| AnnaBridge | 163:e59c8e839560 | 7829 | /*! |
| AnnaBridge | 163:e59c8e839560 | 7830 | * @} |
| AnnaBridge | 163:e59c8e839560 | 7831 | */ /* end of group SHA_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 7832 | |
| AnnaBridge | 163:e59c8e839560 | 7833 | |
| AnnaBridge | 163:e59c8e839560 | 7834 | /* SHA - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 7835 | /** Peripheral SHA0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 7836 | #define SHA0_BASE (0x400A4000u) |
| AnnaBridge | 163:e59c8e839560 | 7837 | /** Peripheral SHA0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 7838 | #define SHA0 ((SHA_Type *)SHA0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 7839 | /** Array initializer of SHA peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 7840 | #define SHA_BASE_ADDRS { SHA0_BASE } |
| AnnaBridge | 163:e59c8e839560 | 7841 | /** Array initializer of SHA peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 7842 | #define SHA_BASE_PTRS { SHA0 } |
| AnnaBridge | 163:e59c8e839560 | 7843 | |
| AnnaBridge | 163:e59c8e839560 | 7844 | /*! |
| AnnaBridge | 163:e59c8e839560 | 7845 | * @} |
| AnnaBridge | 163:e59c8e839560 | 7846 | */ /* end of group SHA_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 7847 | |
| AnnaBridge | 163:e59c8e839560 | 7848 | |
| AnnaBridge | 163:e59c8e839560 | 7849 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 7850 | -- SMARTCARD Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 7851 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 7852 | |
| AnnaBridge | 163:e59c8e839560 | 7853 | /*! |
| AnnaBridge | 163:e59c8e839560 | 7854 | * @addtogroup SMARTCARD_Peripheral_Access_Layer SMARTCARD Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 7855 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 7856 | */ |
| AnnaBridge | 163:e59c8e839560 | 7857 | |
| AnnaBridge | 163:e59c8e839560 | 7858 | /** SMARTCARD - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 7859 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 7860 | union { /* offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 7861 | __IO uint32_t DLL; /**< Divisor Latch LSB, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 7862 | __I uint32_t RBR; /**< Receiver Buffer Register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 7863 | __O uint32_t THR; /**< Transmit Holding Register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 7864 | }; |
| AnnaBridge | 163:e59c8e839560 | 7865 | union { /* offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 7866 | __IO uint32_t DLM; /**< Divisor Latch MSB, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 7867 | __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 7868 | }; |
| AnnaBridge | 163:e59c8e839560 | 7869 | union { /* offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 7870 | __O uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 7871 | __I uint32_t IIR; /**< Interrupt ID Register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 7872 | }; |
| AnnaBridge | 163:e59c8e839560 | 7873 | __IO uint32_t LCR; /**< Line Control Register, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 7874 | uint8_t RESERVED_0[4]; |
| AnnaBridge | 163:e59c8e839560 | 7875 | __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 7876 | uint8_t RESERVED_1[4]; |
| AnnaBridge | 163:e59c8e839560 | 7877 | __IO uint32_t SCR; /**< Scratch Pad Register, offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 7878 | uint8_t RESERVED_2[12]; |
| AnnaBridge | 163:e59c8e839560 | 7879 | __IO uint32_t OSR; /**< Oversampling register, offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 7880 | uint8_t RESERVED_3[24]; |
| AnnaBridge | 163:e59c8e839560 | 7881 | __IO uint32_t SCICTRL; /**< Smart Card Interface control register, offset: 0x48 */ |
| AnnaBridge | 163:e59c8e839560 | 7882 | } SMARTCARD_Type; |
| AnnaBridge | 163:e59c8e839560 | 7883 | |
| AnnaBridge | 163:e59c8e839560 | 7884 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 7885 | -- SMARTCARD Register Masks |
| AnnaBridge | 163:e59c8e839560 | 7886 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 7887 | |
| AnnaBridge | 163:e59c8e839560 | 7888 | /*! |
| AnnaBridge | 163:e59c8e839560 | 7889 | * @addtogroup SMARTCARD_Register_Masks SMARTCARD Register Masks |
| AnnaBridge | 163:e59c8e839560 | 7890 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 7891 | */ |
| AnnaBridge | 163:e59c8e839560 | 7892 | |
| AnnaBridge | 163:e59c8e839560 | 7893 | /*! @name DLL - Divisor Latch LSB */ |
| AnnaBridge | 163:e59c8e839560 | 7894 | #define SMARTCARD_DLL_DLLSB_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 7895 | #define SMARTCARD_DLL_DLLSB_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7896 | #define SMARTCARD_DLL_DLLSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLL_DLLSB_SHIFT)) & SMARTCARD_DLL_DLLSB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7897 | |
| AnnaBridge | 163:e59c8e839560 | 7898 | /*! @name RBR - Receiver Buffer Register */ |
| AnnaBridge | 163:e59c8e839560 | 7899 | #define SMARTCARD_RBR_RBR_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 7900 | #define SMARTCARD_RBR_RBR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7901 | #define SMARTCARD_RBR_RBR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_RBR_RBR_SHIFT)) & SMARTCARD_RBR_RBR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7902 | |
| AnnaBridge | 163:e59c8e839560 | 7903 | /*! @name THR - Transmit Holding Register */ |
| AnnaBridge | 163:e59c8e839560 | 7904 | #define SMARTCARD_THR_THR_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 7905 | #define SMARTCARD_THR_THR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7906 | #define SMARTCARD_THR_THR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_THR_THR_SHIFT)) & SMARTCARD_THR_THR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7907 | |
| AnnaBridge | 163:e59c8e839560 | 7908 | /*! @name DLM - Divisor Latch MSB */ |
| AnnaBridge | 163:e59c8e839560 | 7909 | #define SMARTCARD_DLM_DLMSB_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 7910 | #define SMARTCARD_DLM_DLMSB_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7911 | #define SMARTCARD_DLM_DLMSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLM_DLMSB_SHIFT)) & SMARTCARD_DLM_DLMSB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7912 | |
| AnnaBridge | 163:e59c8e839560 | 7913 | /*! @name IER - Interrupt Enable Register */ |
| AnnaBridge | 163:e59c8e839560 | 7914 | #define SMARTCARD_IER_RBRIE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7915 | #define SMARTCARD_IER_RBRIE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7916 | #define SMARTCARD_IER_RBRIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RBRIE_SHIFT)) & SMARTCARD_IER_RBRIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7917 | #define SMARTCARD_IER_THREIE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7918 | #define SMARTCARD_IER_THREIE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7919 | #define SMARTCARD_IER_THREIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_THREIE_SHIFT)) & SMARTCARD_IER_THREIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7920 | #define SMARTCARD_IER_RXIE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7921 | #define SMARTCARD_IER_RXIE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7922 | #define SMARTCARD_IER_RXIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RXIE_SHIFT)) & SMARTCARD_IER_RXIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7923 | |
| AnnaBridge | 163:e59c8e839560 | 7924 | /*! @name FCR - FIFO Control Register */ |
| AnnaBridge | 163:e59c8e839560 | 7925 | #define SMARTCARD_FCR_FIFOEN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7926 | #define SMARTCARD_FCR_FIFOEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7927 | #define SMARTCARD_FCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_FIFOEN_SHIFT)) & SMARTCARD_FCR_FIFOEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7928 | #define SMARTCARD_FCR_RXFIFORES_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7929 | #define SMARTCARD_FCR_RXFIFORES_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7930 | #define SMARTCARD_FCR_RXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXFIFORES_SHIFT)) & SMARTCARD_FCR_RXFIFORES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7931 | #define SMARTCARD_FCR_TXFIFORES_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7932 | #define SMARTCARD_FCR_TXFIFORES_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7933 | #define SMARTCARD_FCR_TXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_TXFIFORES_SHIFT)) & SMARTCARD_FCR_TXFIFORES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7934 | #define SMARTCARD_FCR_DMAMODE_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 7935 | #define SMARTCARD_FCR_DMAMODE_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 7936 | #define SMARTCARD_FCR_DMAMODE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_DMAMODE_SHIFT)) & SMARTCARD_FCR_DMAMODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7937 | #define SMARTCARD_FCR_RXTRIGLVL_MASK (0xC0U) |
| AnnaBridge | 163:e59c8e839560 | 7938 | #define SMARTCARD_FCR_RXTRIGLVL_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 7939 | #define SMARTCARD_FCR_RXTRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXTRIGLVL_SHIFT)) & SMARTCARD_FCR_RXTRIGLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7940 | |
| AnnaBridge | 163:e59c8e839560 | 7941 | /*! @name IIR - Interrupt ID Register */ |
| AnnaBridge | 163:e59c8e839560 | 7942 | #define SMARTCARD_IIR_INTSTATUS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7943 | #define SMARTCARD_IIR_INTSTATUS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7944 | #define SMARTCARD_IIR_INTSTATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTSTATUS_SHIFT)) & SMARTCARD_IIR_INTSTATUS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7945 | #define SMARTCARD_IIR_INTID_MASK (0xEU) |
| AnnaBridge | 163:e59c8e839560 | 7946 | #define SMARTCARD_IIR_INTID_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7947 | #define SMARTCARD_IIR_INTID(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTID_SHIFT)) & SMARTCARD_IIR_INTID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7948 | #define SMARTCARD_IIR_FIFOENABLE_MASK (0xC0U) |
| AnnaBridge | 163:e59c8e839560 | 7949 | #define SMARTCARD_IIR_FIFOENABLE_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 7950 | #define SMARTCARD_IIR_FIFOENABLE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_FIFOENABLE_SHIFT)) & SMARTCARD_IIR_FIFOENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7951 | |
| AnnaBridge | 163:e59c8e839560 | 7952 | /*! @name LCR - Line Control Register */ |
| AnnaBridge | 163:e59c8e839560 | 7953 | #define SMARTCARD_LCR_WLS_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 7954 | #define SMARTCARD_LCR_WLS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7955 | #define SMARTCARD_LCR_WLS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_WLS_SHIFT)) & SMARTCARD_LCR_WLS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7956 | #define SMARTCARD_LCR_SBS_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7957 | #define SMARTCARD_LCR_SBS_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7958 | #define SMARTCARD_LCR_SBS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_SBS_SHIFT)) & SMARTCARD_LCR_SBS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7959 | #define SMARTCARD_LCR_PE_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 7960 | #define SMARTCARD_LCR_PE_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 7961 | #define SMARTCARD_LCR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PE_SHIFT)) & SMARTCARD_LCR_PE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7962 | #define SMARTCARD_LCR_PS_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 7963 | #define SMARTCARD_LCR_PS_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 7964 | #define SMARTCARD_LCR_PS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PS_SHIFT)) & SMARTCARD_LCR_PS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7965 | #define SMARTCARD_LCR_DLAB_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 7966 | #define SMARTCARD_LCR_DLAB_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 7967 | #define SMARTCARD_LCR_DLAB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_DLAB_SHIFT)) & SMARTCARD_LCR_DLAB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7968 | |
| AnnaBridge | 163:e59c8e839560 | 7969 | /*! @name LSR - Line Status Register */ |
| AnnaBridge | 163:e59c8e839560 | 7970 | #define SMARTCARD_LSR_RDR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 7971 | #define SMARTCARD_LSR_RDR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7972 | #define SMARTCARD_LSR_RDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RDR_SHIFT)) & SMARTCARD_LSR_RDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7973 | #define SMARTCARD_LSR_OE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 7974 | #define SMARTCARD_LSR_OE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 7975 | #define SMARTCARD_LSR_OE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_OE_SHIFT)) & SMARTCARD_LSR_OE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7976 | #define SMARTCARD_LSR_PE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 7977 | #define SMARTCARD_LSR_PE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 7978 | #define SMARTCARD_LSR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_PE_SHIFT)) & SMARTCARD_LSR_PE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7979 | #define SMARTCARD_LSR_FE_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 7980 | #define SMARTCARD_LSR_FE_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 7981 | #define SMARTCARD_LSR_FE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_FE_SHIFT)) & SMARTCARD_LSR_FE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7982 | #define SMARTCARD_LSR_THRE_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 7983 | #define SMARTCARD_LSR_THRE_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 7984 | #define SMARTCARD_LSR_THRE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_THRE_SHIFT)) & SMARTCARD_LSR_THRE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7985 | #define SMARTCARD_LSR_TEMT_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 7986 | #define SMARTCARD_LSR_TEMT_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 7987 | #define SMARTCARD_LSR_TEMT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_TEMT_SHIFT)) & SMARTCARD_LSR_TEMT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7988 | #define SMARTCARD_LSR_RXFE_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 7989 | #define SMARTCARD_LSR_RXFE_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 7990 | #define SMARTCARD_LSR_RXFE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RXFE_SHIFT)) & SMARTCARD_LSR_RXFE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7991 | |
| AnnaBridge | 163:e59c8e839560 | 7992 | /*! @name SCR - Scratch Pad Register */ |
| AnnaBridge | 163:e59c8e839560 | 7993 | #define SMARTCARD_SCR_PAD_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 7994 | #define SMARTCARD_SCR_PAD_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 7995 | #define SMARTCARD_SCR_PAD(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCR_PAD_SHIFT)) & SMARTCARD_SCR_PAD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 7996 | |
| AnnaBridge | 163:e59c8e839560 | 7997 | /*! @name OSR - Oversampling register */ |
| AnnaBridge | 163:e59c8e839560 | 7998 | #define SMARTCARD_OSR_OSFRAC_MASK (0xEU) |
| AnnaBridge | 163:e59c8e839560 | 7999 | #define SMARTCARD_OSR_OSFRAC_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 8000 | #define SMARTCARD_OSR_OSFRAC(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSFRAC_SHIFT)) & SMARTCARD_OSR_OSFRAC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8001 | #define SMARTCARD_OSR_OSINT_MASK (0xF0U) |
| AnnaBridge | 163:e59c8e839560 | 8002 | #define SMARTCARD_OSR_OSINT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8003 | #define SMARTCARD_OSR_OSINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSINT_SHIFT)) & SMARTCARD_OSR_OSINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8004 | #define SMARTCARD_OSR_FDINT_MASK (0x7F00U) |
| AnnaBridge | 163:e59c8e839560 | 8005 | #define SMARTCARD_OSR_FDINT_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8006 | #define SMARTCARD_OSR_FDINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_FDINT_SHIFT)) & SMARTCARD_OSR_FDINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8007 | |
| AnnaBridge | 163:e59c8e839560 | 8008 | /*! @name SCICTRL - Smart Card Interface control register */ |
| AnnaBridge | 163:e59c8e839560 | 8009 | #define SMARTCARD_SCICTRL_SCIEN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 8010 | #define SMARTCARD_SCICTRL_SCIEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8011 | #define SMARTCARD_SCICTRL_SCIEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_SCIEN_SHIFT)) & SMARTCARD_SCICTRL_SCIEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8012 | #define SMARTCARD_SCICTRL_NACKDIS_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 8013 | #define SMARTCARD_SCICTRL_NACKDIS_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 8014 | #define SMARTCARD_SCICTRL_NACKDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_NACKDIS_SHIFT)) & SMARTCARD_SCICTRL_NACKDIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8015 | #define SMARTCARD_SCICTRL_PROTSEL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 8016 | #define SMARTCARD_SCICTRL_PROTSEL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 8017 | #define SMARTCARD_SCICTRL_PROTSEL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_PROTSEL_SHIFT)) & SMARTCARD_SCICTRL_PROTSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8018 | #define SMARTCARD_SCICTRL_TXRETRY_MASK (0xE0U) |
| AnnaBridge | 163:e59c8e839560 | 8019 | #define SMARTCARD_SCICTRL_TXRETRY_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 8020 | #define SMARTCARD_SCICTRL_TXRETRY(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_TXRETRY_SHIFT)) & SMARTCARD_SCICTRL_TXRETRY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8021 | #define SMARTCARD_SCICTRL_GUARDTIME_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 8022 | #define SMARTCARD_SCICTRL_GUARDTIME_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8023 | #define SMARTCARD_SCICTRL_GUARDTIME(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_GUARDTIME_SHIFT)) & SMARTCARD_SCICTRL_GUARDTIME_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8024 | |
| AnnaBridge | 163:e59c8e839560 | 8025 | |
| AnnaBridge | 163:e59c8e839560 | 8026 | /*! |
| AnnaBridge | 163:e59c8e839560 | 8027 | * @} |
| AnnaBridge | 163:e59c8e839560 | 8028 | */ /* end of group SMARTCARD_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 8029 | |
| AnnaBridge | 163:e59c8e839560 | 8030 | |
| AnnaBridge | 163:e59c8e839560 | 8031 | /* SMARTCARD - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 8032 | /** Peripheral SMARTCARD0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8033 | #define SMARTCARD0_BASE (0x40036000u) |
| AnnaBridge | 163:e59c8e839560 | 8034 | /** Peripheral SMARTCARD0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8035 | #define SMARTCARD0 ((SMARTCARD_Type *)SMARTCARD0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8036 | /** Peripheral SMARTCARD1 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8037 | #define SMARTCARD1_BASE (0x40037000u) |
| AnnaBridge | 163:e59c8e839560 | 8038 | /** Peripheral SMARTCARD1 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8039 | #define SMARTCARD1 ((SMARTCARD_Type *)SMARTCARD1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8040 | /** Array initializer of SMARTCARD peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 8041 | #define SMARTCARD_BASE_ADDRS { SMARTCARD0_BASE, SMARTCARD1_BASE } |
| AnnaBridge | 163:e59c8e839560 | 8042 | /** Array initializer of SMARTCARD peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 8043 | #define SMARTCARD_BASE_PTRS { SMARTCARD0, SMARTCARD1 } |
| AnnaBridge | 163:e59c8e839560 | 8044 | /** Interrupt vectors for the SMARTCARD peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 8045 | #define SMARTCARD_IRQS { SMARTCARD0_IRQn, SMARTCARD1_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 8046 | |
| AnnaBridge | 163:e59c8e839560 | 8047 | /*! |
| AnnaBridge | 163:e59c8e839560 | 8048 | * @} |
| AnnaBridge | 163:e59c8e839560 | 8049 | */ /* end of group SMARTCARD_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 8050 | |
| AnnaBridge | 163:e59c8e839560 | 8051 | |
| AnnaBridge | 163:e59c8e839560 | 8052 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 8053 | -- SPI Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 8054 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 8055 | |
| AnnaBridge | 163:e59c8e839560 | 8056 | /*! |
| AnnaBridge | 163:e59c8e839560 | 8057 | * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 8058 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 8059 | */ |
| AnnaBridge | 163:e59c8e839560 | 8060 | |
| AnnaBridge | 163:e59c8e839560 | 8061 | /** SPI - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 8062 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 8063 | uint8_t RESERVED_0[1024]; |
| AnnaBridge | 163:e59c8e839560 | 8064 | __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */ |
| AnnaBridge | 163:e59c8e839560 | 8065 | __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */ |
| AnnaBridge | 163:e59c8e839560 | 8066 | __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */ |
| AnnaBridge | 163:e59c8e839560 | 8067 | __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */ |
| AnnaBridge | 163:e59c8e839560 | 8068 | __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */ |
| AnnaBridge | 163:e59c8e839560 | 8069 | uint8_t RESERVED_1[16]; |
| AnnaBridge | 163:e59c8e839560 | 8070 | __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */ |
| AnnaBridge | 163:e59c8e839560 | 8071 | __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */ |
| AnnaBridge | 163:e59c8e839560 | 8072 | uint8_t RESERVED_2[2516]; |
| AnnaBridge | 163:e59c8e839560 | 8073 | __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ |
| AnnaBridge | 163:e59c8e839560 | 8074 | __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ |
| AnnaBridge | 163:e59c8e839560 | 8075 | __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ |
| AnnaBridge | 163:e59c8e839560 | 8076 | uint8_t RESERVED_3[4]; |
| AnnaBridge | 163:e59c8e839560 | 8077 | __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ |
| AnnaBridge | 163:e59c8e839560 | 8078 | __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ |
| AnnaBridge | 163:e59c8e839560 | 8079 | __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ |
| AnnaBridge | 163:e59c8e839560 | 8080 | uint8_t RESERVED_4[4]; |
| AnnaBridge | 163:e59c8e839560 | 8081 | __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ |
| AnnaBridge | 163:e59c8e839560 | 8082 | uint8_t RESERVED_5[12]; |
| AnnaBridge | 163:e59c8e839560 | 8083 | __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ |
| AnnaBridge | 163:e59c8e839560 | 8084 | uint8_t RESERVED_6[12]; |
| AnnaBridge | 163:e59c8e839560 | 8085 | __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ |
| AnnaBridge | 163:e59c8e839560 | 8086 | uint8_t RESERVED_7[440]; |
| AnnaBridge | 163:e59c8e839560 | 8087 | __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ |
| AnnaBridge | 163:e59c8e839560 | 8088 | } SPI_Type; |
| AnnaBridge | 163:e59c8e839560 | 8089 | |
| AnnaBridge | 163:e59c8e839560 | 8090 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 8091 | -- SPI Register Masks |
| AnnaBridge | 163:e59c8e839560 | 8092 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 8093 | |
| AnnaBridge | 163:e59c8e839560 | 8094 | /*! |
| AnnaBridge | 163:e59c8e839560 | 8095 | * @addtogroup SPI_Register_Masks SPI Register Masks |
| AnnaBridge | 163:e59c8e839560 | 8096 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 8097 | */ |
| AnnaBridge | 163:e59c8e839560 | 8098 | |
| AnnaBridge | 163:e59c8e839560 | 8099 | /*! @name CFG - SPI Configuration register */ |
| AnnaBridge | 163:e59c8e839560 | 8100 | #define SPI_CFG_ENABLE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 8101 | #define SPI_CFG_ENABLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8102 | #define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8103 | #define SPI_CFG_MASTER_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 8104 | #define SPI_CFG_MASTER_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 8105 | #define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8106 | #define SPI_CFG_LSBF_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 8107 | #define SPI_CFG_LSBF_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 8108 | #define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8109 | #define SPI_CFG_CPHA_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 8110 | #define SPI_CFG_CPHA_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8111 | #define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8112 | #define SPI_CFG_CPOL_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 8113 | #define SPI_CFG_CPOL_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 8114 | #define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8115 | #define SPI_CFG_LOOP_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 8116 | #define SPI_CFG_LOOP_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 8117 | #define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8118 | #define SPI_CFG_SPOL0_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 8119 | #define SPI_CFG_SPOL0_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8120 | #define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8121 | #define SPI_CFG_SPOL1_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 8122 | #define SPI_CFG_SPOL1_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 8123 | #define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8124 | #define SPI_CFG_SPOL2_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 8125 | #define SPI_CFG_SPOL2_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 8126 | #define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8127 | #define SPI_CFG_SPOL3_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 8128 | #define SPI_CFG_SPOL3_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 8129 | #define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8130 | |
| AnnaBridge | 163:e59c8e839560 | 8131 | /*! @name DLY - SPI Delay register */ |
| AnnaBridge | 163:e59c8e839560 | 8132 | #define SPI_DLY_PRE_DELAY_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 8133 | #define SPI_DLY_PRE_DELAY_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8134 | #define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8135 | #define SPI_DLY_POST_DELAY_MASK (0xF0U) |
| AnnaBridge | 163:e59c8e839560 | 8136 | #define SPI_DLY_POST_DELAY_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8137 | #define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8138 | #define SPI_DLY_FRAME_DELAY_MASK (0xF00U) |
| AnnaBridge | 163:e59c8e839560 | 8139 | #define SPI_DLY_FRAME_DELAY_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8140 | #define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8141 | #define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) |
| AnnaBridge | 163:e59c8e839560 | 8142 | #define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 8143 | #define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8144 | |
| AnnaBridge | 163:e59c8e839560 | 8145 | /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ |
| AnnaBridge | 163:e59c8e839560 | 8146 | #define SPI_STAT_SSA_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 8147 | #define SPI_STAT_SSA_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8148 | #define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8149 | #define SPI_STAT_SSD_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 8150 | #define SPI_STAT_SSD_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 8151 | #define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8152 | #define SPI_STAT_STALLED_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 8153 | #define SPI_STAT_STALLED_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 8154 | #define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8155 | #define SPI_STAT_ENDTRANSFER_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 8156 | #define SPI_STAT_ENDTRANSFER_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 8157 | #define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8158 | #define SPI_STAT_MSTIDLE_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 8159 | #define SPI_STAT_MSTIDLE_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8160 | #define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8161 | |
| AnnaBridge | 163:e59c8e839560 | 8162 | /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ |
| AnnaBridge | 163:e59c8e839560 | 8163 | #define SPI_INTENSET_SSAEN_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 8164 | #define SPI_INTENSET_SSAEN_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8165 | #define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8166 | #define SPI_INTENSET_SSDEN_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 8167 | #define SPI_INTENSET_SSDEN_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 8168 | #define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8169 | #define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 8170 | #define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8171 | #define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8172 | |
| AnnaBridge | 163:e59c8e839560 | 8173 | /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ |
| AnnaBridge | 163:e59c8e839560 | 8174 | #define SPI_INTENCLR_SSAEN_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 8175 | #define SPI_INTENCLR_SSAEN_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8176 | #define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8177 | #define SPI_INTENCLR_SSDEN_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 8178 | #define SPI_INTENCLR_SSDEN_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 8179 | #define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8180 | #define SPI_INTENCLR_MSTIDLE_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 8181 | #define SPI_INTENCLR_MSTIDLE_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8182 | #define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8183 | |
| AnnaBridge | 163:e59c8e839560 | 8184 | /*! @name DIV - SPI clock Divider */ |
| AnnaBridge | 163:e59c8e839560 | 8185 | #define SPI_DIV_DIVVAL_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 8186 | #define SPI_DIV_DIVVAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8187 | #define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8188 | |
| AnnaBridge | 163:e59c8e839560 | 8189 | /*! @name INTSTAT - SPI Interrupt Status */ |
| AnnaBridge | 163:e59c8e839560 | 8190 | #define SPI_INTSTAT_SSA_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 8191 | #define SPI_INTSTAT_SSA_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8192 | #define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8193 | #define SPI_INTSTAT_SSD_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 8194 | #define SPI_INTSTAT_SSD_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 8195 | #define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8196 | #define SPI_INTSTAT_MSTIDLE_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 8197 | #define SPI_INTSTAT_MSTIDLE_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8198 | #define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8199 | |
| AnnaBridge | 163:e59c8e839560 | 8200 | /*! @name FIFOCFG - FIFO configuration and enable register. */ |
| AnnaBridge | 163:e59c8e839560 | 8201 | #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 8202 | #define SPI_FIFOCFG_ENABLETX_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8203 | #define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8204 | #define SPI_FIFOCFG_ENABLERX_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 8205 | #define SPI_FIFOCFG_ENABLERX_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 8206 | #define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8207 | #define SPI_FIFOCFG_SIZE_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 8208 | #define SPI_FIFOCFG_SIZE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8209 | #define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8210 | #define SPI_FIFOCFG_DMATX_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 8211 | #define SPI_FIFOCFG_DMATX_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 8212 | #define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8213 | #define SPI_FIFOCFG_DMARX_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 8214 | #define SPI_FIFOCFG_DMARX_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 8215 | #define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8216 | #define SPI_FIFOCFG_WAKETX_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 8217 | #define SPI_FIFOCFG_WAKETX_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 8218 | #define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8219 | #define SPI_FIFOCFG_WAKERX_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 8220 | #define SPI_FIFOCFG_WAKERX_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 8221 | #define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8222 | #define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 8223 | #define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8224 | #define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8225 | #define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 8226 | #define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 8227 | #define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8228 | #define SPI_FIFOCFG_POPDBG_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 8229 | #define SPI_FIFOCFG_POPDBG_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 8230 | #define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8231 | |
| AnnaBridge | 163:e59c8e839560 | 8232 | /*! @name FIFOSTAT - FIFO status register. */ |
| AnnaBridge | 163:e59c8e839560 | 8233 | #define SPI_FIFOSTAT_TXERR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 8234 | #define SPI_FIFOSTAT_TXERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8235 | #define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8236 | #define SPI_FIFOSTAT_RXERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 8237 | #define SPI_FIFOSTAT_RXERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 8238 | #define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8239 | #define SPI_FIFOSTAT_PERINT_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 8240 | #define SPI_FIFOSTAT_PERINT_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 8241 | #define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8242 | #define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 8243 | #define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8244 | #define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8245 | #define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 8246 | #define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 8247 | #define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8248 | #define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 8249 | #define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 8250 | #define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8251 | #define SPI_FIFOSTAT_RXFULL_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 8252 | #define SPI_FIFOSTAT_RXFULL_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 8253 | #define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8254 | #define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) |
| AnnaBridge | 163:e59c8e839560 | 8255 | #define SPI_FIFOSTAT_TXLVL_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8256 | #define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8257 | #define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) |
| AnnaBridge | 163:e59c8e839560 | 8258 | #define SPI_FIFOSTAT_RXLVL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8259 | #define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8260 | |
| AnnaBridge | 163:e59c8e839560 | 8261 | /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ |
| AnnaBridge | 163:e59c8e839560 | 8262 | #define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 8263 | #define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8264 | #define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8265 | #define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 8266 | #define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 8267 | #define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8268 | #define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) |
| AnnaBridge | 163:e59c8e839560 | 8269 | #define SPI_FIFOTRIG_TXLVL_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8270 | #define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8271 | #define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) |
| AnnaBridge | 163:e59c8e839560 | 8272 | #define SPI_FIFOTRIG_RXLVL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8273 | #define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8274 | |
| AnnaBridge | 163:e59c8e839560 | 8275 | /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ |
| AnnaBridge | 163:e59c8e839560 | 8276 | #define SPI_FIFOINTENSET_TXERR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 8277 | #define SPI_FIFOINTENSET_TXERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8278 | #define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8279 | #define SPI_FIFOINTENSET_RXERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 8280 | #define SPI_FIFOINTENSET_RXERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 8281 | #define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8282 | #define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 8283 | #define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 8284 | #define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8285 | #define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 8286 | #define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 8287 | #define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8288 | |
| AnnaBridge | 163:e59c8e839560 | 8289 | /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ |
| AnnaBridge | 163:e59c8e839560 | 8290 | #define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 8291 | #define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8292 | #define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8293 | #define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 8294 | #define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 8295 | #define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8296 | #define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 8297 | #define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 8298 | #define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8299 | #define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 8300 | #define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 8301 | #define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8302 | |
| AnnaBridge | 163:e59c8e839560 | 8303 | /*! @name FIFOINTSTAT - FIFO interrupt status register. */ |
| AnnaBridge | 163:e59c8e839560 | 8304 | #define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 8305 | #define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8306 | #define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8307 | #define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 8308 | #define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 8309 | #define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8310 | #define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 8311 | #define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 8312 | #define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8313 | #define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 8314 | #define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 8315 | #define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8316 | #define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 8317 | #define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8318 | #define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8319 | |
| AnnaBridge | 163:e59c8e839560 | 8320 | /*! @name FIFOWR - FIFO write data. */ |
| AnnaBridge | 163:e59c8e839560 | 8321 | #define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 8322 | #define SPI_FIFOWR_TXDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8323 | #define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8324 | #define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 8325 | #define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8326 | #define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8327 | #define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 8328 | #define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 8329 | #define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8330 | #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 8331 | #define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 8332 | #define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8333 | #define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 8334 | #define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 8335 | #define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8336 | #define SPI_FIFOWR_EOT_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 8337 | #define SPI_FIFOWR_EOT_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 8338 | #define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8339 | #define SPI_FIFOWR_EOF_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 8340 | #define SPI_FIFOWR_EOF_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 8341 | #define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8342 | #define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 8343 | #define SPI_FIFOWR_RXIGNORE_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 8344 | #define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8345 | #define SPI_FIFOWR_LEN_MASK (0xF000000U) |
| AnnaBridge | 163:e59c8e839560 | 8346 | #define SPI_FIFOWR_LEN_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 8347 | #define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8348 | |
| AnnaBridge | 163:e59c8e839560 | 8349 | /*! @name FIFORD - FIFO read data. */ |
| AnnaBridge | 163:e59c8e839560 | 8350 | #define SPI_FIFORD_RXDATA_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 8351 | #define SPI_FIFORD_RXDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8352 | #define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8353 | #define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 8354 | #define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8355 | #define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8356 | #define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 8357 | #define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 8358 | #define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8359 | #define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 8360 | #define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 8361 | #define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8362 | #define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 8363 | #define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 8364 | #define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8365 | #define SPI_FIFORD_SOT_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 8366 | #define SPI_FIFORD_SOT_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 8367 | #define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8368 | |
| AnnaBridge | 163:e59c8e839560 | 8369 | /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ |
| AnnaBridge | 163:e59c8e839560 | 8370 | #define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 8371 | #define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8372 | #define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8373 | #define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 8374 | #define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8375 | #define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8376 | #define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 8377 | #define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 8378 | #define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8379 | #define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 8380 | #define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 8381 | #define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8382 | #define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 8383 | #define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 8384 | #define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8385 | #define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 8386 | #define SPI_FIFORDNOPOP_SOT_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 8387 | #define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8388 | |
| AnnaBridge | 163:e59c8e839560 | 8389 | /*! @name ID - Peripheral identification register. */ |
| AnnaBridge | 163:e59c8e839560 | 8390 | #define SPI_ID_APERTURE_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 8391 | #define SPI_ID_APERTURE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8392 | #define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8393 | #define SPI_ID_MINOR_REV_MASK (0xF00U) |
| AnnaBridge | 163:e59c8e839560 | 8394 | #define SPI_ID_MINOR_REV_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8395 | #define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8396 | #define SPI_ID_MAJOR_REV_MASK (0xF000U) |
| AnnaBridge | 163:e59c8e839560 | 8397 | #define SPI_ID_MAJOR_REV_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 8398 | #define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8399 | #define SPI_ID_ID_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 8400 | #define SPI_ID_ID_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8401 | #define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8402 | |
| AnnaBridge | 163:e59c8e839560 | 8403 | |
| AnnaBridge | 163:e59c8e839560 | 8404 | /*! |
| AnnaBridge | 163:e59c8e839560 | 8405 | * @} |
| AnnaBridge | 163:e59c8e839560 | 8406 | */ /* end of group SPI_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 8407 | |
| AnnaBridge | 163:e59c8e839560 | 8408 | |
| AnnaBridge | 163:e59c8e839560 | 8409 | /* SPI - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 8410 | /** Peripheral SPI0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8411 | #define SPI0_BASE (0x40086000u) |
| AnnaBridge | 163:e59c8e839560 | 8412 | /** Peripheral SPI0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8413 | #define SPI0 ((SPI_Type *)SPI0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8414 | /** Peripheral SPI1 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8415 | #define SPI1_BASE (0x40087000u) |
| AnnaBridge | 163:e59c8e839560 | 8416 | /** Peripheral SPI1 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8417 | #define SPI1 ((SPI_Type *)SPI1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8418 | /** Peripheral SPI2 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8419 | #define SPI2_BASE (0x40088000u) |
| AnnaBridge | 163:e59c8e839560 | 8420 | /** Peripheral SPI2 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8421 | #define SPI2 ((SPI_Type *)SPI2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8422 | /** Peripheral SPI3 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8423 | #define SPI3_BASE (0x40089000u) |
| AnnaBridge | 163:e59c8e839560 | 8424 | /** Peripheral SPI3 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8425 | #define SPI3 ((SPI_Type *)SPI3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8426 | /** Peripheral SPI4 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8427 | #define SPI4_BASE (0x4008A000u) |
| AnnaBridge | 163:e59c8e839560 | 8428 | /** Peripheral SPI4 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8429 | #define SPI4 ((SPI_Type *)SPI4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8430 | /** Peripheral SPI5 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8431 | #define SPI5_BASE (0x40096000u) |
| AnnaBridge | 163:e59c8e839560 | 8432 | /** Peripheral SPI5 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8433 | #define SPI5 ((SPI_Type *)SPI5_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8434 | /** Peripheral SPI6 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8435 | #define SPI6_BASE (0x40097000u) |
| AnnaBridge | 163:e59c8e839560 | 8436 | /** Peripheral SPI6 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8437 | #define SPI6 ((SPI_Type *)SPI6_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8438 | /** Peripheral SPI7 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8439 | #define SPI7_BASE (0x40098000u) |
| AnnaBridge | 163:e59c8e839560 | 8440 | /** Peripheral SPI7 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8441 | #define SPI7 ((SPI_Type *)SPI7_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8442 | /** Peripheral SPI8 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8443 | #define SPI8_BASE (0x40099000u) |
| AnnaBridge | 163:e59c8e839560 | 8444 | /** Peripheral SPI8 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8445 | #define SPI8 ((SPI_Type *)SPI8_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8446 | /** Peripheral SPI9 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8447 | #define SPI9_BASE (0x4009A000u) |
| AnnaBridge | 163:e59c8e839560 | 8448 | /** Peripheral SPI9 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8449 | #define SPI9 ((SPI_Type *)SPI9_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8450 | /** Array initializer of SPI peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 8451 | #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE } |
| AnnaBridge | 163:e59c8e839560 | 8452 | /** Array initializer of SPI peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 8453 | #define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9 } |
| AnnaBridge | 163:e59c8e839560 | 8454 | /** Interrupt vectors for the SPI peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 8455 | #define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 8456 | |
| AnnaBridge | 163:e59c8e839560 | 8457 | /*! |
| AnnaBridge | 163:e59c8e839560 | 8458 | * @} |
| AnnaBridge | 163:e59c8e839560 | 8459 | */ /* end of group SPI_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 8460 | |
| AnnaBridge | 163:e59c8e839560 | 8461 | |
| AnnaBridge | 163:e59c8e839560 | 8462 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 8463 | -- SPIFI Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 8464 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 8465 | |
| AnnaBridge | 163:e59c8e839560 | 8466 | /*! |
| AnnaBridge | 163:e59c8e839560 | 8467 | * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 8468 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 8469 | */ |
| AnnaBridge | 163:e59c8e839560 | 8470 | |
| AnnaBridge | 163:e59c8e839560 | 8471 | /** SPIFI - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 8472 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 8473 | __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 8474 | __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8475 | __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 8476 | __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 8477 | __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 8478 | __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 8479 | __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 8480 | __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 8481 | } SPIFI_Type; |
| AnnaBridge | 163:e59c8e839560 | 8482 | |
| AnnaBridge | 163:e59c8e839560 | 8483 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 8484 | -- SPIFI Register Masks |
| AnnaBridge | 163:e59c8e839560 | 8485 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 8486 | |
| AnnaBridge | 163:e59c8e839560 | 8487 | /*! |
| AnnaBridge | 163:e59c8e839560 | 8488 | * @addtogroup SPIFI_Register_Masks SPIFI Register Masks |
| AnnaBridge | 163:e59c8e839560 | 8489 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 8490 | */ |
| AnnaBridge | 163:e59c8e839560 | 8491 | |
| AnnaBridge | 163:e59c8e839560 | 8492 | /*! @name CTRL - SPIFI control register */ |
| AnnaBridge | 163:e59c8e839560 | 8493 | #define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 8494 | #define SPIFI_CTRL_TIMEOUT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8495 | #define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8496 | #define SPIFI_CTRL_CSHIGH_MASK (0xF0000U) |
| AnnaBridge | 163:e59c8e839560 | 8497 | #define SPIFI_CTRL_CSHIGH_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8498 | #define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8499 | #define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 8500 | #define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 8501 | #define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8502 | #define SPIFI_CTRL_INTEN_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 8503 | #define SPIFI_CTRL_INTEN_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 8504 | #define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8505 | #define SPIFI_CTRL_MODE3_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 8506 | #define SPIFI_CTRL_MODE3_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 8507 | #define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8508 | #define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 8509 | #define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 8510 | #define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8511 | #define SPIFI_CTRL_DUAL_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 8512 | #define SPIFI_CTRL_DUAL_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 8513 | #define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8514 | #define SPIFI_CTRL_RFCLK_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 8515 | #define SPIFI_CTRL_RFCLK_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 8516 | #define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8517 | #define SPIFI_CTRL_FBCLK_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 8518 | #define SPIFI_CTRL_FBCLK_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 8519 | #define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8520 | #define SPIFI_CTRL_DMAEN_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 8521 | #define SPIFI_CTRL_DMAEN_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 8522 | #define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8523 | |
| AnnaBridge | 163:e59c8e839560 | 8524 | /*! @name CMD - SPIFI command register */ |
| AnnaBridge | 163:e59c8e839560 | 8525 | #define SPIFI_CMD_DATALEN_MASK (0x3FFFU) |
| AnnaBridge | 163:e59c8e839560 | 8526 | #define SPIFI_CMD_DATALEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8527 | #define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8528 | #define SPIFI_CMD_POLL_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 8529 | #define SPIFI_CMD_POLL_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 8530 | #define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8531 | #define SPIFI_CMD_DOUT_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 8532 | #define SPIFI_CMD_DOUT_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 8533 | #define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8534 | #define SPIFI_CMD_INTLEN_MASK (0x70000U) |
| AnnaBridge | 163:e59c8e839560 | 8535 | #define SPIFI_CMD_INTLEN_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8536 | #define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8537 | #define SPIFI_CMD_FIELDFORM_MASK (0x180000U) |
| AnnaBridge | 163:e59c8e839560 | 8538 | #define SPIFI_CMD_FIELDFORM_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 8539 | #define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8540 | #define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U) |
| AnnaBridge | 163:e59c8e839560 | 8541 | #define SPIFI_CMD_FRAMEFORM_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 8542 | #define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8543 | #define SPIFI_CMD_OPCODE_MASK (0xFF000000U) |
| AnnaBridge | 163:e59c8e839560 | 8544 | #define SPIFI_CMD_OPCODE_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 8545 | #define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8546 | |
| AnnaBridge | 163:e59c8e839560 | 8547 | /*! @name ADDR - SPIFI address register */ |
| AnnaBridge | 163:e59c8e839560 | 8548 | #define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 8549 | #define SPIFI_ADDR_ADDRESS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8550 | #define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8551 | |
| AnnaBridge | 163:e59c8e839560 | 8552 | /*! @name IDATA - SPIFI intermediate data register */ |
| AnnaBridge | 163:e59c8e839560 | 8553 | #define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 8554 | #define SPIFI_IDATA_IDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8555 | #define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8556 | |
| AnnaBridge | 163:e59c8e839560 | 8557 | /*! @name CLIMIT - SPIFI limit register */ |
| AnnaBridge | 163:e59c8e839560 | 8558 | #define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 8559 | #define SPIFI_CLIMIT_CLIMIT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8560 | #define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8561 | |
| AnnaBridge | 163:e59c8e839560 | 8562 | /*! @name DATA - SPIFI data register */ |
| AnnaBridge | 163:e59c8e839560 | 8563 | #define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 8564 | #define SPIFI_DATA_DATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8565 | #define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8566 | |
| AnnaBridge | 163:e59c8e839560 | 8567 | /*! @name MCMD - SPIFI memory command register */ |
| AnnaBridge | 163:e59c8e839560 | 8568 | #define SPIFI_MCMD_POLL_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 8569 | #define SPIFI_MCMD_POLL_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 8570 | #define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8571 | #define SPIFI_MCMD_DOUT_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 8572 | #define SPIFI_MCMD_DOUT_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 8573 | #define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8574 | #define SPIFI_MCMD_INTLEN_MASK (0x70000U) |
| AnnaBridge | 163:e59c8e839560 | 8575 | #define SPIFI_MCMD_INTLEN_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8576 | #define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8577 | #define SPIFI_MCMD_FIELDFORM_MASK (0x180000U) |
| AnnaBridge | 163:e59c8e839560 | 8578 | #define SPIFI_MCMD_FIELDFORM_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 8579 | #define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8580 | #define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U) |
| AnnaBridge | 163:e59c8e839560 | 8581 | #define SPIFI_MCMD_FRAMEFORM_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 8582 | #define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8583 | #define SPIFI_MCMD_OPCODE_MASK (0xFF000000U) |
| AnnaBridge | 163:e59c8e839560 | 8584 | #define SPIFI_MCMD_OPCODE_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 8585 | #define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8586 | |
| AnnaBridge | 163:e59c8e839560 | 8587 | /*! @name STAT - SPIFI status register */ |
| AnnaBridge | 163:e59c8e839560 | 8588 | #define SPIFI_STAT_MCINIT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 8589 | #define SPIFI_STAT_MCINIT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8590 | #define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8591 | #define SPIFI_STAT_CMD_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 8592 | #define SPIFI_STAT_CMD_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 8593 | #define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8594 | #define SPIFI_STAT_RESET_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 8595 | #define SPIFI_STAT_RESET_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8596 | #define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8597 | #define SPIFI_STAT_INTRQ_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 8598 | #define SPIFI_STAT_INTRQ_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 8599 | #define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8600 | |
| AnnaBridge | 163:e59c8e839560 | 8601 | |
| AnnaBridge | 163:e59c8e839560 | 8602 | /*! |
| AnnaBridge | 163:e59c8e839560 | 8603 | * @} |
| AnnaBridge | 163:e59c8e839560 | 8604 | */ /* end of group SPIFI_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 8605 | |
| AnnaBridge | 163:e59c8e839560 | 8606 | |
| AnnaBridge | 163:e59c8e839560 | 8607 | /* SPIFI - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 8608 | /** Peripheral SPIFI0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 8609 | #define SPIFI0_BASE (0x40080000u) |
| AnnaBridge | 163:e59c8e839560 | 8610 | /** Peripheral SPIFI0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 8611 | #define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 8612 | /** Array initializer of SPIFI peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 8613 | #define SPIFI_BASE_ADDRS { SPIFI0_BASE } |
| AnnaBridge | 163:e59c8e839560 | 8614 | /** Array initializer of SPIFI peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 8615 | #define SPIFI_BASE_PTRS { SPIFI0 } |
| AnnaBridge | 163:e59c8e839560 | 8616 | /** Interrupt vectors for the SPIFI peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 8617 | #define SPIFI_IRQS { SPIFI0_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 8618 | |
| AnnaBridge | 163:e59c8e839560 | 8619 | /*! |
| AnnaBridge | 163:e59c8e839560 | 8620 | * @} |
| AnnaBridge | 163:e59c8e839560 | 8621 | */ /* end of group SPIFI_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 8622 | |
| AnnaBridge | 163:e59c8e839560 | 8623 | |
| AnnaBridge | 163:e59c8e839560 | 8624 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 8625 | -- SYSCON Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 8626 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 8627 | |
| AnnaBridge | 163:e59c8e839560 | 8628 | /*! |
| AnnaBridge | 163:e59c8e839560 | 8629 | * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 8630 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 8631 | */ |
| AnnaBridge | 163:e59c8e839560 | 8632 | |
| AnnaBridge | 163:e59c8e839560 | 8633 | /** SYSCON - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 8634 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 8635 | uint8_t RESERVED_0[16]; |
| AnnaBridge | 163:e59c8e839560 | 8636 | __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 8637 | uint8_t RESERVED_1[44]; |
| AnnaBridge | 163:e59c8e839560 | 8638 | __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 8639 | uint8_t RESERVED_2[4]; |
| AnnaBridge | 163:e59c8e839560 | 8640 | __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ |
| AnnaBridge | 163:e59c8e839560 | 8641 | __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */ |
| AnnaBridge | 163:e59c8e839560 | 8642 | uint8_t RESERVED_3[112]; |
| AnnaBridge | 163:e59c8e839560 | 8643 | __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8644 | uint8_t RESERVED_4[8]; |
| AnnaBridge | 163:e59c8e839560 | 8645 | __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8646 | uint8_t RESERVED_5[40]; |
| AnnaBridge | 163:e59c8e839560 | 8647 | __IO uint32_t PRESETCTRL[3]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8648 | uint8_t RESERVED_6[20]; |
| AnnaBridge | 163:e59c8e839560 | 8649 | __O uint32_t PRESETCTRLSET[3]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8650 | uint8_t RESERVED_7[20]; |
| AnnaBridge | 163:e59c8e839560 | 8651 | __O uint32_t PRESETCTRLCLR[3]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8652 | uint8_t RESERVED_8[164]; |
| AnnaBridge | 163:e59c8e839560 | 8653 | __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */ |
| AnnaBridge | 163:e59c8e839560 | 8654 | uint8_t RESERVED_9[12]; |
| AnnaBridge | 163:e59c8e839560 | 8655 | __IO uint32_t AHBCLKCTRL[3]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8656 | uint8_t RESERVED_10[20]; |
| AnnaBridge | 163:e59c8e839560 | 8657 | __O uint32_t AHBCLKCTRLSET[3]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8658 | uint8_t RESERVED_11[20]; |
| AnnaBridge | 163:e59c8e839560 | 8659 | __O uint32_t AHBCLKCTRLCLR[3]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8660 | uint8_t RESERVED_12[52]; |
| AnnaBridge | 163:e59c8e839560 | 8661 | __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */ |
| AnnaBridge | 163:e59c8e839560 | 8662 | __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */ |
| AnnaBridge | 163:e59c8e839560 | 8663 | __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */ |
| AnnaBridge | 163:e59c8e839560 | 8664 | uint8_t RESERVED_13[4]; |
| AnnaBridge | 163:e59c8e839560 | 8665 | __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */ |
| AnnaBridge | 163:e59c8e839560 | 8666 | uint8_t RESERVED_14[4]; |
| AnnaBridge | 163:e59c8e839560 | 8667 | __IO uint32_t AUDPLLCLKSEL; /**< Audio PLL clock source select, offset: 0x298 */ |
| AnnaBridge | 163:e59c8e839560 | 8668 | uint8_t RESERVED_15[4]; |
| AnnaBridge | 163:e59c8e839560 | 8669 | __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */ |
| AnnaBridge | 163:e59c8e839560 | 8670 | __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ |
| AnnaBridge | 163:e59c8e839560 | 8671 | __IO uint32_t USB0CLKSEL; /**< USB0 clock source select, offset: 0x2A8 */ |
| AnnaBridge | 163:e59c8e839560 | 8672 | __IO uint32_t USB1CLKSEL; /**< USB1 clock source select, offset: 0x2AC */ |
| AnnaBridge | 163:e59c8e839560 | 8673 | __IO uint32_t FCLKSEL[10]; /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8674 | uint8_t RESERVED_16[8]; |
| AnnaBridge | 163:e59c8e839560 | 8675 | __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ |
| AnnaBridge | 163:e59c8e839560 | 8676 | uint8_t RESERVED_17[4]; |
| AnnaBridge | 163:e59c8e839560 | 8677 | __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */ |
| AnnaBridge | 163:e59c8e839560 | 8678 | __IO uint32_t DMICCLKSEL; /**< Digital microphone (DMIC) subsystem clock select, offset: 0x2EC */ |
| AnnaBridge | 163:e59c8e839560 | 8679 | __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ |
| AnnaBridge | 163:e59c8e839560 | 8680 | __IO uint32_t LCDCLKSEL; /**< LCD clock source select, offset: 0x2F4 */ |
| AnnaBridge | 163:e59c8e839560 | 8681 | __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ |
| AnnaBridge | 163:e59c8e839560 | 8682 | uint8_t RESERVED_18[4]; |
| AnnaBridge | 163:e59c8e839560 | 8683 | __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */ |
| AnnaBridge | 163:e59c8e839560 | 8684 | __IO uint32_t ARMTRACECLKDIV; /**< ARM Trace clock divider, offset: 0x304 */ |
| AnnaBridge | 163:e59c8e839560 | 8685 | __IO uint32_t CAN0CLKDIV; /**< MCAN0 clock divider, offset: 0x308 */ |
| AnnaBridge | 163:e59c8e839560 | 8686 | __IO uint32_t CAN1CLKDIV; /**< MCAN1 clock divider, offset: 0x30C */ |
| AnnaBridge | 163:e59c8e839560 | 8687 | __IO uint32_t SC0CLKDIV; /**< Smartcard0 clock divider, offset: 0x310 */ |
| AnnaBridge | 163:e59c8e839560 | 8688 | __IO uint32_t SC1CLKDIV; /**< Smartcard1 clock divider, offset: 0x314 */ |
| AnnaBridge | 163:e59c8e839560 | 8689 | uint8_t RESERVED_19[104]; |
| AnnaBridge | 163:e59c8e839560 | 8690 | __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */ |
| AnnaBridge | 163:e59c8e839560 | 8691 | __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ |
| AnnaBridge | 163:e59c8e839560 | 8692 | __IO uint32_t FROHFCLKDIV; /**< FROHF clock divider, offset: 0x388 */ |
| AnnaBridge | 163:e59c8e839560 | 8693 | uint8_t RESERVED_20[4]; |
| AnnaBridge | 163:e59c8e839560 | 8694 | __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */ |
| AnnaBridge | 163:e59c8e839560 | 8695 | __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ |
| AnnaBridge | 163:e59c8e839560 | 8696 | __IO uint32_t USB0CLKDIV; /**< USB0 clock divider, offset: 0x398 */ |
| AnnaBridge | 163:e59c8e839560 | 8697 | __IO uint32_t USB1CLKDIV; /**< USB1 clock divider, offset: 0x39C */ |
| AnnaBridge | 163:e59c8e839560 | 8698 | __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */ |
| AnnaBridge | 163:e59c8e839560 | 8699 | uint8_t RESERVED_21[4]; |
| AnnaBridge | 163:e59c8e839560 | 8700 | __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */ |
| AnnaBridge | 163:e59c8e839560 | 8701 | __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ |
| AnnaBridge | 163:e59c8e839560 | 8702 | __IO uint32_t LCDCLKDIV; /**< LCD clock divider, offset: 0x3B0 */ |
| AnnaBridge | 163:e59c8e839560 | 8703 | __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ |
| AnnaBridge | 163:e59c8e839560 | 8704 | __IO uint32_t EMCCLKDIV; /**< EMC clock divider, offset: 0x3B8 */ |
| AnnaBridge | 163:e59c8e839560 | 8705 | __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ |
| AnnaBridge | 163:e59c8e839560 | 8706 | uint8_t RESERVED_22[64]; |
| AnnaBridge | 163:e59c8e839560 | 8707 | __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */ |
| AnnaBridge | 163:e59c8e839560 | 8708 | uint8_t RESERVED_23[8]; |
| AnnaBridge | 163:e59c8e839560 | 8709 | __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */ |
| AnnaBridge | 163:e59c8e839560 | 8710 | __IO uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */ |
| AnnaBridge | 163:e59c8e839560 | 8711 | uint8_t RESERVED_24[4]; |
| AnnaBridge | 163:e59c8e839560 | 8712 | __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */ |
| AnnaBridge | 163:e59c8e839560 | 8713 | uint8_t RESERVED_25[4]; |
| AnnaBridge | 163:e59c8e839560 | 8714 | __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */ |
| AnnaBridge | 163:e59c8e839560 | 8715 | __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */ |
| AnnaBridge | 163:e59c8e839560 | 8716 | __IO uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */ |
| AnnaBridge | 163:e59c8e839560 | 8717 | uint8_t RESERVED_26[24]; |
| AnnaBridge | 163:e59c8e839560 | 8718 | __IO uint32_t EMCSYSCTRL; /**< EMC system control, offset: 0x444 */ |
| AnnaBridge | 163:e59c8e839560 | 8719 | __IO uint32_t EMCDLYCTRL; /**< EMC clock delay control, offset: 0x448 */ |
| AnnaBridge | 163:e59c8e839560 | 8720 | __IO uint32_t EMCDLYCAL; /**< EMC delay chain calibration control, offset: 0x44C */ |
| AnnaBridge | 163:e59c8e839560 | 8721 | __IO uint32_t ETHPHYSEL; /**< Ethernet PHY Selection, offset: 0x450 */ |
| AnnaBridge | 163:e59c8e839560 | 8722 | __IO uint32_t ETHSBDCTRL; /**< Ethernet SBD flow control, offset: 0x454 */ |
| AnnaBridge | 163:e59c8e839560 | 8723 | uint8_t RESERVED_27[8]; |
| AnnaBridge | 163:e59c8e839560 | 8724 | __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ |
| AnnaBridge | 163:e59c8e839560 | 8725 | uint8_t RESERVED_28[156]; |
| AnnaBridge | 163:e59c8e839560 | 8726 | __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */ |
| AnnaBridge | 163:e59c8e839560 | 8727 | __IO uint32_t SYSOSCCTRL; /**< System oscillator control, offset: 0x504 */ |
| AnnaBridge | 163:e59c8e839560 | 8728 | __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */ |
| AnnaBridge | 163:e59c8e839560 | 8729 | __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */ |
| AnnaBridge | 163:e59c8e839560 | 8730 | uint8_t RESERVED_29[12]; |
| AnnaBridge | 163:e59c8e839560 | 8731 | __IO uint32_t USBPLLCTRL; /**< USB PLL control, offset: 0x51C */ |
| AnnaBridge | 163:e59c8e839560 | 8732 | __IO uint32_t USBPLLSTAT; /**< USB PLL status, offset: 0x520 */ |
| AnnaBridge | 163:e59c8e839560 | 8733 | uint8_t RESERVED_30[92]; |
| AnnaBridge | 163:e59c8e839560 | 8734 | __IO uint32_t SYSPLLCTRL; /**< System PLL control, offset: 0x580 */ |
| AnnaBridge | 163:e59c8e839560 | 8735 | __IO uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */ |
| AnnaBridge | 163:e59c8e839560 | 8736 | __IO uint32_t SYSPLLNDEC; /**< PLL N divider, offset: 0x588 */ |
| AnnaBridge | 163:e59c8e839560 | 8737 | __IO uint32_t SYSPLLPDEC; /**< PLL P divider, offset: 0x58C */ |
| AnnaBridge | 163:e59c8e839560 | 8738 | __IO uint32_t SYSPLLMDEC; /**< System PLL M divider, offset: 0x590 */ |
| AnnaBridge | 163:e59c8e839560 | 8739 | uint8_t RESERVED_31[12]; |
| AnnaBridge | 163:e59c8e839560 | 8740 | __IO uint32_t AUDPLLCTRL; /**< Audio PLL control, offset: 0x5A0 */ |
| AnnaBridge | 163:e59c8e839560 | 8741 | __IO uint32_t AUDPLLSTAT; /**< Audio PLL status, offset: 0x5A4 */ |
| AnnaBridge | 163:e59c8e839560 | 8742 | __IO uint32_t AUDPLLNDEC; /**< Audio PLL N divider, offset: 0x5A8 */ |
| AnnaBridge | 163:e59c8e839560 | 8743 | __IO uint32_t AUDPLLPDEC; /**< Audio PLL P divider, offset: 0x5AC */ |
| AnnaBridge | 163:e59c8e839560 | 8744 | __IO uint32_t AUDPLLMDEC; /**< Audio PLL M divider, offset: 0x5B0 */ |
| AnnaBridge | 163:e59c8e839560 | 8745 | __IO uint32_t AUDPLLFRAC; /**< Audio PLL fractional divider control, offset: 0x5B4 */ |
| AnnaBridge | 163:e59c8e839560 | 8746 | uint8_t RESERVED_32[72]; |
| AnnaBridge | 163:e59c8e839560 | 8747 | __IO uint32_t PDSLEEPCFG[2]; /**< Power configuration register 0, array offset: 0x600, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8748 | uint8_t RESERVED_33[8]; |
| AnnaBridge | 163:e59c8e839560 | 8749 | __IO uint32_t PDRUNCFG[2]; /**< Power configuration register 0, array offset: 0x610, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8750 | uint8_t RESERVED_34[8]; |
| AnnaBridge | 163:e59c8e839560 | 8751 | __IO uint32_t PDRUNCFGSET[2]; /**< Set bits in PDRUNCFG0, array offset: 0x620, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8752 | uint8_t RESERVED_35[8]; |
| AnnaBridge | 163:e59c8e839560 | 8753 | __IO uint32_t PDRUNCFGCLR[2]; /**< Clear bits in PDRUNCFG0, array offset: 0x630, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8754 | uint8_t RESERVED_36[72]; |
| AnnaBridge | 163:e59c8e839560 | 8755 | __IO uint32_t STARTER[2]; /**< Start logic 0 wake-up enable register, array offset: 0x680, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8756 | uint8_t RESERVED_37[24]; |
| AnnaBridge | 163:e59c8e839560 | 8757 | __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8758 | uint8_t RESERVED_38[24]; |
| AnnaBridge | 163:e59c8e839560 | 8759 | __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER0, array offset: 0x6C0, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 8760 | uint8_t RESERVED_39[184]; |
| AnnaBridge | 163:e59c8e839560 | 8761 | __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */ |
| AnnaBridge | 163:e59c8e839560 | 8762 | uint8_t RESERVED_40[1664]; |
| AnnaBridge | 163:e59c8e839560 | 8763 | __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */ |
| AnnaBridge | 163:e59c8e839560 | 8764 | uint8_t RESERVED_41[492]; |
| AnnaBridge | 163:e59c8e839560 | 8765 | __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */ |
| AnnaBridge | 163:e59c8e839560 | 8766 | __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */ |
| AnnaBridge | 163:e59c8e839560 | 8767 | __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */ |
| AnnaBridge | 163:e59c8e839560 | 8768 | uint8_t RESERVED_42[127044]; |
| AnnaBridge | 163:e59c8e839560 | 8769 | __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */ |
| AnnaBridge | 163:e59c8e839560 | 8770 | } SYSCON_Type; |
| AnnaBridge | 163:e59c8e839560 | 8771 | |
| AnnaBridge | 163:e59c8e839560 | 8772 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 8773 | -- SYSCON Register Masks |
| AnnaBridge | 163:e59c8e839560 | 8774 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 8775 | |
| AnnaBridge | 163:e59c8e839560 | 8776 | /*! |
| AnnaBridge | 163:e59c8e839560 | 8777 | * @addtogroup SYSCON_Register_Masks SYSCON Register Masks |
| AnnaBridge | 163:e59c8e839560 | 8778 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 8779 | */ |
| AnnaBridge | 163:e59c8e839560 | 8780 | |
| AnnaBridge | 163:e59c8e839560 | 8781 | /*! @name AHBMATPRIO - AHB multilayer matrix priority control */ |
| AnnaBridge | 163:e59c8e839560 | 8782 | #define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 8783 | #define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8784 | #define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8785 | #define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 8786 | #define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 8787 | #define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8788 | #define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 8789 | #define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8790 | #define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8791 | #define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0x3C0U) |
| AnnaBridge | 163:e59c8e839560 | 8792 | #define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 8793 | #define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8794 | #define SYSCON_AHBMATPRIO_PRI_ETH_MASK (0xC00U) |
| AnnaBridge | 163:e59c8e839560 | 8795 | #define SYSCON_AHBMATPRIO_PRI_ETH_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 8796 | #define SYSCON_AHBMATPRIO_PRI_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8797 | #define SYSCON_AHBMATPRIO_PRI_LCD_MASK (0x3000U) |
| AnnaBridge | 163:e59c8e839560 | 8798 | #define SYSCON_AHBMATPRIO_PRI_LCD_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 8799 | #define SYSCON_AHBMATPRIO_PRI_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8800 | #define SYSCON_AHBMATPRIO_PRI_USB0_MASK (0xC000U) |
| AnnaBridge | 163:e59c8e839560 | 8801 | #define SYSCON_AHBMATPRIO_PRI_USB0_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 8802 | #define SYSCON_AHBMATPRIO_PRI_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8803 | #define SYSCON_AHBMATPRIO_PRI_USB1_MASK (0x30000U) |
| AnnaBridge | 163:e59c8e839560 | 8804 | #define SYSCON_AHBMATPRIO_PRI_USB1_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8805 | #define SYSCON_AHBMATPRIO_PRI_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8806 | #define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0xC0000U) |
| AnnaBridge | 163:e59c8e839560 | 8807 | #define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 8808 | #define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8809 | #define SYSCON_AHBMATPRIO_PRI_MCAN1_MASK (0x300000U) |
| AnnaBridge | 163:e59c8e839560 | 8810 | #define SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 8811 | #define SYSCON_AHBMATPRIO_PRI_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8812 | #define SYSCON_AHBMATPRIO_PRI_MCAN2_MASK (0xC00000U) |
| AnnaBridge | 163:e59c8e839560 | 8813 | #define SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 8814 | #define SYSCON_AHBMATPRIO_PRI_MCAN2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8815 | #define SYSCON_AHBMATPRIO_PRI_SHA_MASK (0x3000000U) |
| AnnaBridge | 163:e59c8e839560 | 8816 | #define SYSCON_AHBMATPRIO_PRI_SHA_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 8817 | #define SYSCON_AHBMATPRIO_PRI_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8818 | |
| AnnaBridge | 163:e59c8e839560 | 8819 | /*! @name SYSTCKCAL - System tick counter calibration */ |
| AnnaBridge | 163:e59c8e839560 | 8820 | #define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 8821 | #define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8822 | #define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8823 | #define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 8824 | #define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 8825 | #define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8826 | #define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 8827 | #define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 8828 | #define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8829 | |
| AnnaBridge | 163:e59c8e839560 | 8830 | /*! @name NMISRC - NMI Source Select */ |
| AnnaBridge | 163:e59c8e839560 | 8831 | #define SYSCON_NMISRC_IRQM4_MASK (0x3FU) |
| AnnaBridge | 163:e59c8e839560 | 8832 | #define SYSCON_NMISRC_IRQM4_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8833 | #define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8834 | #define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 8835 | #define SYSCON_NMISRC_NMIENM4_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 8836 | #define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8837 | |
| AnnaBridge | 163:e59c8e839560 | 8838 | /*! @name ASYNCAPBCTRL - Asynchronous APB Control */ |
| AnnaBridge | 163:e59c8e839560 | 8839 | #define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 8840 | #define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8841 | #define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8842 | |
| AnnaBridge | 163:e59c8e839560 | 8843 | /*! @name PIOPORCAP - POR captured value of port n */ |
| AnnaBridge | 163:e59c8e839560 | 8844 | #define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 8845 | #define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8846 | #define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8847 | |
| AnnaBridge | 163:e59c8e839560 | 8848 | /* The count of SYSCON_PIOPORCAP */ |
| AnnaBridge | 163:e59c8e839560 | 8849 | #define SYSCON_PIOPORCAP_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 8850 | |
| AnnaBridge | 163:e59c8e839560 | 8851 | /*! @name PIORESCAP - Reset captured value of port n */ |
| AnnaBridge | 163:e59c8e839560 | 8852 | #define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 8853 | #define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8854 | #define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8855 | |
| AnnaBridge | 163:e59c8e839560 | 8856 | /* The count of SYSCON_PIORESCAP */ |
| AnnaBridge | 163:e59c8e839560 | 8857 | #define SYSCON_PIORESCAP_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 8858 | |
| AnnaBridge | 163:e59c8e839560 | 8859 | /*! @name PRESETCTRL - Peripheral reset control n */ |
| AnnaBridge | 163:e59c8e839560 | 8860 | #define SYSCON_PRESETCTRL_MRT_RST_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 8861 | #define SYSCON_PRESETCTRL_MRT_RST_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 8862 | #define SYSCON_PRESETCTRL_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8863 | #define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 8864 | #define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 8865 | #define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8866 | #define SYSCON_PRESETCTRL_LCD_RST_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 8867 | #define SYSCON_PRESETCTRL_LCD_RST_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 8868 | #define SYSCON_PRESETCTRL_LCD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8869 | #define SYSCON_PRESETCTRL_SDIO_RST_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 8870 | #define SYSCON_PRESETCTRL_SDIO_RST_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 8871 | #define SYSCON_PRESETCTRL_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8872 | #define SYSCON_PRESETCTRL_USB1H_RST_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 8873 | #define SYSCON_PRESETCTRL_USB1H_RST_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 8874 | #define SYSCON_PRESETCTRL_USB1H_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8875 | #define SYSCON_PRESETCTRL_USB1D_RST_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 8876 | #define SYSCON_PRESETCTRL_USB1D_RST_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 8877 | #define SYSCON_PRESETCTRL_USB1D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8878 | #define SYSCON_PRESETCTRL_USB1RAM_RST_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 8879 | #define SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 8880 | #define SYSCON_PRESETCTRL_USB1RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8881 | #define SYSCON_PRESETCTRL_EMC_RESET_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 8882 | #define SYSCON_PRESETCTRL_EMC_RESET_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 8883 | #define SYSCON_PRESETCTRL_EMC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8884 | #define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 8885 | #define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 8886 | #define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8887 | #define SYSCON_PRESETCTRL_MCAN0_RST_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 8888 | #define SYSCON_PRESETCTRL_MCAN0_RST_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 8889 | #define SYSCON_PRESETCTRL_MCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8890 | #define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 8891 | #define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8892 | #define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8893 | #define SYSCON_PRESETCTRL_ETH_RST_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 8894 | #define SYSCON_PRESETCTRL_ETH_RST_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8895 | #define SYSCON_PRESETCTRL_ETH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8896 | #define SYSCON_PRESETCTRL_MCAN1_RST_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 8897 | #define SYSCON_PRESETCTRL_MCAN1_RST_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 8898 | #define SYSCON_PRESETCTRL_MCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8899 | #define SYSCON_PRESETCTRL_GPIO4_RST_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 8900 | #define SYSCON_PRESETCTRL_GPIO4_RST_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 8901 | #define SYSCON_PRESETCTRL_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8902 | #define SYSCON_PRESETCTRL_EEPROM_RST_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 8903 | #define SYSCON_PRESETCTRL_EEPROM_RST_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 8904 | #define SYSCON_PRESETCTRL_EEPROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EEPROM_RST_SHIFT)) & SYSCON_PRESETCTRL_EEPROM_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8905 | #define SYSCON_PRESETCTRL_GPIO5_RST_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 8906 | #define SYSCON_PRESETCTRL_GPIO5_RST_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 8907 | #define SYSCON_PRESETCTRL_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8908 | #define SYSCON_PRESETCTRL_UTICK_RST_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 8909 | #define SYSCON_PRESETCTRL_UTICK_RST_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 8910 | #define SYSCON_PRESETCTRL_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8911 | #define SYSCON_PRESETCTRL_SPIFI_RST_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 8912 | #define SYSCON_PRESETCTRL_SPIFI_RST_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 8913 | #define SYSCON_PRESETCTRL_SPIFI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8914 | #define SYSCON_PRESETCTRL_AES_RST_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 8915 | #define SYSCON_PRESETCTRL_AES_RST_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 8916 | #define SYSCON_PRESETCTRL_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_AES_RST_SHIFT)) & SYSCON_PRESETCTRL_AES_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8917 | #define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 8918 | #define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 8919 | #define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8920 | #define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 8921 | #define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 8922 | #define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8923 | #define SYSCON_PRESETCTRL_OTP_RST_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 8924 | #define SYSCON_PRESETCTRL_OTP_RST_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 8925 | #define SYSCON_PRESETCTRL_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8926 | #define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 8927 | #define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 8928 | #define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8929 | #define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 8930 | #define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 8931 | #define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8932 | #define SYSCON_PRESETCTRL_RNG_RST_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 8933 | #define SYSCON_PRESETCTRL_RNG_RST_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 8934 | #define SYSCON_PRESETCTRL_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8935 | #define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 8936 | #define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 8937 | #define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8938 | #define SYSCON_PRESETCTRL_FC8_RST_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 8939 | #define SYSCON_PRESETCTRL_FC8_RST_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 8940 | #define SYSCON_PRESETCTRL_FC8_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8941 | #define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 8942 | #define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 8943 | #define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8944 | #define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 8945 | #define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 8946 | #define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8947 | #define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 8948 | #define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 8949 | #define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8950 | #define SYSCON_PRESETCTRL_FC9_RST_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 8951 | #define SYSCON_PRESETCTRL_FC9_RST_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 8952 | #define SYSCON_PRESETCTRL_FC9_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8953 | #define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 8954 | #define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 8955 | #define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8956 | #define SYSCON_PRESETCTRL_USB0HMR_RST_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 8957 | #define SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8958 | #define SYSCON_PRESETCTRL_USB0HMR_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8959 | #define SYSCON_PRESETCTRL_GPIO2_RST_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 8960 | #define SYSCON_PRESETCTRL_GPIO2_RST_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8961 | #define SYSCON_PRESETCTRL_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8962 | #define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 8963 | #define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 8964 | #define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8965 | #define SYSCON_PRESETCTRL_GPIO3_RST_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 8966 | #define SYSCON_PRESETCTRL_GPIO3_RST_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 8967 | #define SYSCON_PRESETCTRL_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8968 | #define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 8969 | #define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 8970 | #define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8971 | #define SYSCON_PRESETCTRL_USB0HSL_RST_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 8972 | #define SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 8973 | #define SYSCON_PRESETCTRL_USB0HSL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8974 | #define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 8975 | #define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 8976 | #define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8977 | #define SYSCON_PRESETCTRL_SHA_RST_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 8978 | #define SYSCON_PRESETCTRL_SHA_RST_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 8979 | #define SYSCON_PRESETCTRL_SHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8980 | #define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 8981 | #define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 8982 | #define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8983 | #define SYSCON_PRESETCTRL_DMIC_RST_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 8984 | #define SYSCON_PRESETCTRL_DMIC_RST_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 8985 | #define SYSCON_PRESETCTRL_DMIC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8986 | #define SYSCON_PRESETCTRL_SC0_RST_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 8987 | #define SYSCON_PRESETCTRL_SC0_RST_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 8988 | #define SYSCON_PRESETCTRL_SC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8989 | #define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 8990 | #define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 8991 | #define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8992 | #define SYSCON_PRESETCTRL_SC1_RST_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 8993 | #define SYSCON_PRESETCTRL_SC1_RST_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 8994 | #define SYSCON_PRESETCTRL_SC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8995 | #define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 8996 | #define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 8997 | #define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 8998 | #define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 8999 | #define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 9000 | #define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9001 | #define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 9002 | #define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 9003 | #define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9004 | #define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 9005 | #define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 9006 | #define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9007 | #define SYSCON_PRESETCTRL_USB0D_RST_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 9008 | #define SYSCON_PRESETCTRL_USB0D_RST_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 9009 | #define SYSCON_PRESETCTRL_USB0D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9010 | #define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 9011 | #define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 9012 | #define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9013 | #define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 9014 | #define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 9015 | #define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9016 | #define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 9017 | #define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 9018 | #define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9019 | |
| AnnaBridge | 163:e59c8e839560 | 9020 | /* The count of SYSCON_PRESETCTRL */ |
| AnnaBridge | 163:e59c8e839560 | 9021 | #define SYSCON_PRESETCTRL_COUNT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9022 | |
| AnnaBridge | 163:e59c8e839560 | 9023 | /*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */ |
| AnnaBridge | 163:e59c8e839560 | 9024 | #define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 9025 | #define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9026 | #define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9027 | |
| AnnaBridge | 163:e59c8e839560 | 9028 | /* The count of SYSCON_PRESETCTRLSET */ |
| AnnaBridge | 163:e59c8e839560 | 9029 | #define SYSCON_PRESETCTRLSET_COUNT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9030 | |
| AnnaBridge | 163:e59c8e839560 | 9031 | /*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */ |
| AnnaBridge | 163:e59c8e839560 | 9032 | #define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 9033 | #define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9034 | #define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9035 | |
| AnnaBridge | 163:e59c8e839560 | 9036 | /* The count of SYSCON_PRESETCTRLCLR */ |
| AnnaBridge | 163:e59c8e839560 | 9037 | #define SYSCON_PRESETCTRLCLR_COUNT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9038 | |
| AnnaBridge | 163:e59c8e839560 | 9039 | /*! @name SYSRSTSTAT - System reset status register */ |
| AnnaBridge | 163:e59c8e839560 | 9040 | #define SYSCON_SYSRSTSTAT_POR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9041 | #define SYSCON_SYSRSTSTAT_POR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9042 | #define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9043 | #define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 9044 | #define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 9045 | #define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9046 | #define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 9047 | #define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 9048 | #define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9049 | #define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 9050 | #define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9051 | #define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9052 | #define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 9053 | #define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 9054 | #define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9055 | |
| AnnaBridge | 163:e59c8e839560 | 9056 | /*! @name AHBCLKCTRL - AHB Clock control n */ |
| AnnaBridge | 163:e59c8e839560 | 9057 | #define SYSCON_AHBCLKCTRL_MRT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9058 | #define SYSCON_AHBCLKCTRL_MRT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9059 | #define SYSCON_AHBCLKCTRL_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9060 | #define SYSCON_AHBCLKCTRL_RIT_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 9061 | #define SYSCON_AHBCLKCTRL_RIT_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 9062 | #define SYSCON_AHBCLKCTRL_RIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9063 | #define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 9064 | #define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 9065 | #define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9066 | #define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 9067 | #define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 9068 | #define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9069 | #define SYSCON_AHBCLKCTRL_LCD_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 9070 | #define SYSCON_AHBCLKCTRL_LCD_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 9071 | #define SYSCON_AHBCLKCTRL_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9072 | #define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 9073 | #define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9074 | #define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9075 | #define SYSCON_AHBCLKCTRL_SDIO_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 9076 | #define SYSCON_AHBCLKCTRL_SDIO_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9077 | #define SYSCON_AHBCLKCTRL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9078 | #define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 9079 | #define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 9080 | #define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9081 | #define SYSCON_AHBCLKCTRL_USB1H_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 9082 | #define SYSCON_AHBCLKCTRL_USB1H_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 9083 | #define SYSCON_AHBCLKCTRL_USB1H(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9084 | #define SYSCON_AHBCLKCTRL_SRAM3_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 9085 | #define SYSCON_AHBCLKCTRL_SRAM3_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 9086 | #define SYSCON_AHBCLKCTRL_SRAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9087 | #define SYSCON_AHBCLKCTRL_USB1D_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 9088 | #define SYSCON_AHBCLKCTRL_USB1D_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 9089 | #define SYSCON_AHBCLKCTRL_USB1D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9090 | #define SYSCON_AHBCLKCTRL_USB1RAM_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 9091 | #define SYSCON_AHBCLKCTRL_USB1RAM_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 9092 | #define SYSCON_AHBCLKCTRL_USB1RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9093 | #define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 9094 | #define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 9095 | #define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9096 | #define SYSCON_AHBCLKCTRL_EMC_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 9097 | #define SYSCON_AHBCLKCTRL_EMC_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 9098 | #define SYSCON_AHBCLKCTRL_EMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9099 | #define SYSCON_AHBCLKCTRL_MCAN0_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 9100 | #define SYSCON_AHBCLKCTRL_MCAN0_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 9101 | #define SYSCON_AHBCLKCTRL_MCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9102 | #define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 9103 | #define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 9104 | #define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9105 | #define SYSCON_AHBCLKCTRL_ETH_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 9106 | #define SYSCON_AHBCLKCTRL_ETH_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 9107 | #define SYSCON_AHBCLKCTRL_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9108 | #define SYSCON_AHBCLKCTRL_MCAN1_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 9109 | #define SYSCON_AHBCLKCTRL_MCAN1_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 9110 | #define SYSCON_AHBCLKCTRL_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9111 | #define SYSCON_AHBCLKCTRL_EEPROM_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 9112 | #define SYSCON_AHBCLKCTRL_EEPROM_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 9113 | #define SYSCON_AHBCLKCTRL_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EEPROM_SHIFT)) & SYSCON_AHBCLKCTRL_EEPROM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9114 | #define SYSCON_AHBCLKCTRL_GPIO4_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 9115 | #define SYSCON_AHBCLKCTRL_GPIO4_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 9116 | #define SYSCON_AHBCLKCTRL_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9117 | #define SYSCON_AHBCLKCTRL_GPIO5_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 9118 | #define SYSCON_AHBCLKCTRL_GPIO5_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 9119 | #define SYSCON_AHBCLKCTRL_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9120 | #define SYSCON_AHBCLKCTRL_UTICK_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 9121 | #define SYSCON_AHBCLKCTRL_UTICK_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 9122 | #define SYSCON_AHBCLKCTRL_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9123 | #define SYSCON_AHBCLKCTRL_SPIFI_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 9124 | #define SYSCON_AHBCLKCTRL_SPIFI_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 9125 | #define SYSCON_AHBCLKCTRL_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9126 | #define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 9127 | #define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 9128 | #define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9129 | #define SYSCON_AHBCLKCTRL_AES_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 9130 | #define SYSCON_AHBCLKCTRL_AES_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 9131 | #define SYSCON_AHBCLKCTRL_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_AES_SHIFT)) & SYSCON_AHBCLKCTRL_AES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9132 | #define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 9133 | #define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 9134 | #define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9135 | #define SYSCON_AHBCLKCTRL_OTP_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 9136 | #define SYSCON_AHBCLKCTRL_OTP_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 9137 | #define SYSCON_AHBCLKCTRL_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9138 | #define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 9139 | #define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 9140 | #define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9141 | #define SYSCON_AHBCLKCTRL_RNG_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 9142 | #define SYSCON_AHBCLKCTRL_RNG_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 9143 | #define SYSCON_AHBCLKCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9144 | #define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 9145 | #define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 9146 | #define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9147 | #define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 9148 | #define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 9149 | #define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9150 | #define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 9151 | #define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 9152 | #define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9153 | #define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 9154 | #define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 9155 | #define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9156 | #define SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 9157 | #define SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 9158 | #define SYSCON_AHBCLKCTRL_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9159 | #define SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 9160 | #define SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 9161 | #define SYSCON_AHBCLKCTRL_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9162 | #define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 9163 | #define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 9164 | #define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9165 | #define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 9166 | #define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 9167 | #define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9168 | #define SYSCON_AHBCLKCTRL_GPIO2_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 9169 | #define SYSCON_AHBCLKCTRL_GPIO2_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 9170 | #define SYSCON_AHBCLKCTRL_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9171 | #define SYSCON_AHBCLKCTRL_USB0HMR_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 9172 | #define SYSCON_AHBCLKCTRL_USB0HMR_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 9173 | #define SYSCON_AHBCLKCTRL_USB0HMR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9174 | #define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 9175 | #define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 9176 | #define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9177 | #define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 9178 | #define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 9179 | #define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9180 | #define SYSCON_AHBCLKCTRL_GPIO3_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 9181 | #define SYSCON_AHBCLKCTRL_GPIO3_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 9182 | #define SYSCON_AHBCLKCTRL_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9183 | #define SYSCON_AHBCLKCTRL_USB0HSL_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 9184 | #define SYSCON_AHBCLKCTRL_USB0HSL_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 9185 | #define SYSCON_AHBCLKCTRL_USB0HSL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9186 | #define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 9187 | #define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 9188 | #define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9189 | #define SYSCON_AHBCLKCTRL_SHA0_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 9190 | #define SYSCON_AHBCLKCTRL_SHA0_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 9191 | #define SYSCON_AHBCLKCTRL_SHA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA0_SHIFT)) & SYSCON_AHBCLKCTRL_SHA0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9192 | #define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 9193 | #define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 9194 | #define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9195 | #define SYSCON_AHBCLKCTRL_DMIC_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 9196 | #define SYSCON_AHBCLKCTRL_DMIC_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 9197 | #define SYSCON_AHBCLKCTRL_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9198 | #define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 9199 | #define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 9200 | #define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9201 | #define SYSCON_AHBCLKCTRL_SC0_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 9202 | #define SYSCON_AHBCLKCTRL_SC0_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 9203 | #define SYSCON_AHBCLKCTRL_SC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9204 | #define SYSCON_AHBCLKCTRL_SC1_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 9205 | #define SYSCON_AHBCLKCTRL_SC1_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 9206 | #define SYSCON_AHBCLKCTRL_SC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9207 | #define SYSCON_AHBCLKCTRL_DMA_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 9208 | #define SYSCON_AHBCLKCTRL_DMA_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 9209 | #define SYSCON_AHBCLKCTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9210 | #define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 9211 | #define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 9212 | #define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9213 | #define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 9214 | #define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 9215 | #define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9216 | #define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 9217 | #define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 9218 | #define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9219 | #define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 9220 | #define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 9221 | #define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9222 | #define SYSCON_AHBCLKCTRL_USB0D_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 9223 | #define SYSCON_AHBCLKCTRL_USB0D_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 9224 | #define SYSCON_AHBCLKCTRL_USB0D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9225 | #define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 9226 | #define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 9227 | #define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9228 | #define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 9229 | #define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 9230 | #define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9231 | #define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 9232 | #define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 9233 | #define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9234 | |
| AnnaBridge | 163:e59c8e839560 | 9235 | /* The count of SYSCON_AHBCLKCTRL */ |
| AnnaBridge | 163:e59c8e839560 | 9236 | #define SYSCON_AHBCLKCTRL_COUNT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9237 | |
| AnnaBridge | 163:e59c8e839560 | 9238 | /*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */ |
| AnnaBridge | 163:e59c8e839560 | 9239 | #define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 9240 | #define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9241 | #define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9242 | |
| AnnaBridge | 163:e59c8e839560 | 9243 | /* The count of SYSCON_AHBCLKCTRLSET */ |
| AnnaBridge | 163:e59c8e839560 | 9244 | #define SYSCON_AHBCLKCTRLSET_COUNT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9245 | |
| AnnaBridge | 163:e59c8e839560 | 9246 | /*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */ |
| AnnaBridge | 163:e59c8e839560 | 9247 | #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 9248 | #define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9249 | #define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9250 | |
| AnnaBridge | 163:e59c8e839560 | 9251 | /* The count of SYSCON_AHBCLKCTRLCLR */ |
| AnnaBridge | 163:e59c8e839560 | 9252 | #define SYSCON_AHBCLKCTRLCLR_COUNT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9253 | |
| AnnaBridge | 163:e59c8e839560 | 9254 | /*! @name MAINCLKSELA - Main clock source select A */ |
| AnnaBridge | 163:e59c8e839560 | 9255 | #define SYSCON_MAINCLKSELA_SEL_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 9256 | #define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9257 | #define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9258 | |
| AnnaBridge | 163:e59c8e839560 | 9259 | /*! @name MAINCLKSELB - Main clock source select B */ |
| AnnaBridge | 163:e59c8e839560 | 9260 | #define SYSCON_MAINCLKSELB_SEL_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 9261 | #define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9262 | #define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9263 | |
| AnnaBridge | 163:e59c8e839560 | 9264 | /*! @name CLKOUTSELA - CLKOUT clock source select A */ |
| AnnaBridge | 163:e59c8e839560 | 9265 | #define SYSCON_CLKOUTSELA_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9266 | #define SYSCON_CLKOUTSELA_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9267 | #define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9268 | |
| AnnaBridge | 163:e59c8e839560 | 9269 | /*! @name SYSPLLCLKSEL - PLL clock source select */ |
| AnnaBridge | 163:e59c8e839560 | 9270 | #define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9271 | #define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9272 | #define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9273 | |
| AnnaBridge | 163:e59c8e839560 | 9274 | /*! @name AUDPLLCLKSEL - Audio PLL clock source select */ |
| AnnaBridge | 163:e59c8e839560 | 9275 | #define SYSCON_AUDPLLCLKSEL_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9276 | #define SYSCON_AUDPLLCLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9277 | #define SYSCON_AUDPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9278 | |
| AnnaBridge | 163:e59c8e839560 | 9279 | /*! @name SPIFICLKSEL - SPIFI clock source select */ |
| AnnaBridge | 163:e59c8e839560 | 9280 | #define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9281 | #define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9282 | #define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9283 | |
| AnnaBridge | 163:e59c8e839560 | 9284 | /*! @name ADCCLKSEL - ADC clock source select */ |
| AnnaBridge | 163:e59c8e839560 | 9285 | #define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9286 | #define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9287 | #define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9288 | |
| AnnaBridge | 163:e59c8e839560 | 9289 | /*! @name USB0CLKSEL - USB0 clock source select */ |
| AnnaBridge | 163:e59c8e839560 | 9290 | #define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9291 | #define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9292 | #define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9293 | |
| AnnaBridge | 163:e59c8e839560 | 9294 | /*! @name USB1CLKSEL - USB1 clock source select */ |
| AnnaBridge | 163:e59c8e839560 | 9295 | #define SYSCON_USB1CLKSEL_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9296 | #define SYSCON_USB1CLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9297 | #define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9298 | |
| AnnaBridge | 163:e59c8e839560 | 9299 | /*! @name FCLKSEL - Flexcomm 0 clock source select */ |
| AnnaBridge | 163:e59c8e839560 | 9300 | #define SYSCON_FCLKSEL_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9301 | #define SYSCON_FCLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9302 | #define SYSCON_FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9303 | |
| AnnaBridge | 163:e59c8e839560 | 9304 | /* The count of SYSCON_FCLKSEL */ |
| AnnaBridge | 163:e59c8e839560 | 9305 | #define SYSCON_FCLKSEL_COUNT (10U) |
| AnnaBridge | 163:e59c8e839560 | 9306 | |
| AnnaBridge | 163:e59c8e839560 | 9307 | /*! @name MCLKCLKSEL - MCLK clock source select */ |
| AnnaBridge | 163:e59c8e839560 | 9308 | #define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9309 | #define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9310 | #define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9311 | |
| AnnaBridge | 163:e59c8e839560 | 9312 | /*! @name FRGCLKSEL - Fractional Rate Generator clock source select */ |
| AnnaBridge | 163:e59c8e839560 | 9313 | #define SYSCON_FRGCLKSEL_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9314 | #define SYSCON_FRGCLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9315 | #define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9316 | |
| AnnaBridge | 163:e59c8e839560 | 9317 | /*! @name DMICCLKSEL - Digital microphone (DMIC) subsystem clock select */ |
| AnnaBridge | 163:e59c8e839560 | 9318 | #define SYSCON_DMICCLKSEL_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9319 | #define SYSCON_DMICCLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9320 | #define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9321 | |
| AnnaBridge | 163:e59c8e839560 | 9322 | /*! @name SCTCLKSEL - SCTimer/PWM clock source select */ |
| AnnaBridge | 163:e59c8e839560 | 9323 | #define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9324 | #define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9325 | #define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9326 | |
| AnnaBridge | 163:e59c8e839560 | 9327 | /*! @name LCDCLKSEL - LCD clock source select */ |
| AnnaBridge | 163:e59c8e839560 | 9328 | #define SYSCON_LCDCLKSEL_SEL_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 9329 | #define SYSCON_LCDCLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9330 | #define SYSCON_LCDCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9331 | |
| AnnaBridge | 163:e59c8e839560 | 9332 | /*! @name SDIOCLKSEL - SDIO clock source select */ |
| AnnaBridge | 163:e59c8e839560 | 9333 | #define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) |
| AnnaBridge | 163:e59c8e839560 | 9334 | #define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9335 | #define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9336 | |
| AnnaBridge | 163:e59c8e839560 | 9337 | /*! @name SYSTICKCLKDIV - SYSTICK clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9338 | #define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9339 | #define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9340 | #define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9341 | #define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9342 | #define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9343 | #define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9344 | #define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9345 | #define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9346 | #define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9347 | #define SYSCON_SYSTICKCLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9348 | #define SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9349 | #define SYSCON_SYSTICKCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9350 | |
| AnnaBridge | 163:e59c8e839560 | 9351 | /*! @name ARMTRACECLKDIV - ARM Trace clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9352 | #define SYSCON_ARMTRACECLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9353 | #define SYSCON_ARMTRACECLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9354 | #define SYSCON_ARMTRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9355 | #define SYSCON_ARMTRACECLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9356 | #define SYSCON_ARMTRACECLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9357 | #define SYSCON_ARMTRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9358 | #define SYSCON_ARMTRACECLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9359 | #define SYSCON_ARMTRACECLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9360 | #define SYSCON_ARMTRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9361 | #define SYSCON_ARMTRACECLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9362 | #define SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9363 | #define SYSCON_ARMTRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9364 | |
| AnnaBridge | 163:e59c8e839560 | 9365 | /*! @name CAN0CLKDIV - MCAN0 clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9366 | #define SYSCON_CAN0CLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9367 | #define SYSCON_CAN0CLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9368 | #define SYSCON_CAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9369 | #define SYSCON_CAN0CLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9370 | #define SYSCON_CAN0CLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9371 | #define SYSCON_CAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9372 | #define SYSCON_CAN0CLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9373 | #define SYSCON_CAN0CLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9374 | #define SYSCON_CAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9375 | #define SYSCON_CAN0CLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9376 | #define SYSCON_CAN0CLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9377 | #define SYSCON_CAN0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9378 | |
| AnnaBridge | 163:e59c8e839560 | 9379 | /*! @name CAN1CLKDIV - MCAN1 clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9380 | #define SYSCON_CAN1CLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9381 | #define SYSCON_CAN1CLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9382 | #define SYSCON_CAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9383 | #define SYSCON_CAN1CLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9384 | #define SYSCON_CAN1CLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9385 | #define SYSCON_CAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9386 | #define SYSCON_CAN1CLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9387 | #define SYSCON_CAN1CLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9388 | #define SYSCON_CAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9389 | #define SYSCON_CAN1CLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9390 | #define SYSCON_CAN1CLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9391 | #define SYSCON_CAN1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9392 | |
| AnnaBridge | 163:e59c8e839560 | 9393 | /*! @name SC0CLKDIV - Smartcard0 clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9394 | #define SYSCON_SC0CLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9395 | #define SYSCON_SC0CLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9396 | #define SYSCON_SC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9397 | #define SYSCON_SC0CLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9398 | #define SYSCON_SC0CLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9399 | #define SYSCON_SC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9400 | #define SYSCON_SC0CLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9401 | #define SYSCON_SC0CLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9402 | #define SYSCON_SC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9403 | #define SYSCON_SC0CLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9404 | #define SYSCON_SC0CLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9405 | #define SYSCON_SC0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9406 | |
| AnnaBridge | 163:e59c8e839560 | 9407 | /*! @name SC1CLKDIV - Smartcard1 clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9408 | #define SYSCON_SC1CLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9409 | #define SYSCON_SC1CLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9410 | #define SYSCON_SC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9411 | #define SYSCON_SC1CLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9412 | #define SYSCON_SC1CLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9413 | #define SYSCON_SC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9414 | #define SYSCON_SC1CLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9415 | #define SYSCON_SC1CLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9416 | #define SYSCON_SC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9417 | #define SYSCON_SC1CLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9418 | #define SYSCON_SC1CLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9419 | #define SYSCON_SC1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9420 | |
| AnnaBridge | 163:e59c8e839560 | 9421 | /*! @name AHBCLKDIV - AHB clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9422 | #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9423 | #define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9424 | #define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9425 | #define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9426 | #define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9427 | #define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9428 | |
| AnnaBridge | 163:e59c8e839560 | 9429 | /*! @name CLKOUTDIV - CLKOUT clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9430 | #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9431 | #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9432 | #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9433 | #define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9434 | #define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9435 | #define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9436 | #define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9437 | #define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9438 | #define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9439 | #define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9440 | #define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9441 | #define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9442 | |
| AnnaBridge | 163:e59c8e839560 | 9443 | /*! @name FROHFCLKDIV - FROHF clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9444 | #define SYSCON_FROHFCLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9445 | #define SYSCON_FROHFCLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9446 | #define SYSCON_FROHFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_DIV_SHIFT)) & SYSCON_FROHFCLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9447 | #define SYSCON_FROHFCLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9448 | #define SYSCON_FROHFCLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9449 | #define SYSCON_FROHFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_RESET_SHIFT)) & SYSCON_FROHFCLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9450 | #define SYSCON_FROHFCLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9451 | #define SYSCON_FROHFCLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9452 | #define SYSCON_FROHFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_HALT_SHIFT)) & SYSCON_FROHFCLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9453 | #define SYSCON_FROHFCLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9454 | #define SYSCON_FROHFCLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9455 | #define SYSCON_FROHFCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_REQFLAG_SHIFT)) & SYSCON_FROHFCLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9456 | |
| AnnaBridge | 163:e59c8e839560 | 9457 | /*! @name SPIFICLKDIV - SPIFI clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9458 | #define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9459 | #define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9460 | #define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9461 | #define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9462 | #define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9463 | #define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9464 | #define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9465 | #define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9466 | #define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9467 | #define SYSCON_SPIFICLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9468 | #define SYSCON_SPIFICLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9469 | #define SYSCON_SPIFICLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9470 | |
| AnnaBridge | 163:e59c8e839560 | 9471 | /*! @name ADCCLKDIV - ADC clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9472 | #define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9473 | #define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9474 | #define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9475 | #define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9476 | #define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9477 | #define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9478 | #define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9479 | #define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9480 | #define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9481 | #define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9482 | #define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9483 | #define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9484 | |
| AnnaBridge | 163:e59c8e839560 | 9485 | /*! @name USB0CLKDIV - USB0 clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9486 | #define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9487 | #define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9488 | #define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9489 | #define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9490 | #define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9491 | #define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9492 | #define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9493 | #define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9494 | #define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9495 | #define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9496 | #define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9497 | #define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9498 | |
| AnnaBridge | 163:e59c8e839560 | 9499 | /*! @name USB1CLKDIV - USB1 clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9500 | #define SYSCON_USB1CLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9501 | #define SYSCON_USB1CLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9502 | #define SYSCON_USB1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9503 | #define SYSCON_USB1CLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9504 | #define SYSCON_USB1CLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9505 | #define SYSCON_USB1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9506 | #define SYSCON_USB1CLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9507 | #define SYSCON_USB1CLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9508 | #define SYSCON_USB1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9509 | #define SYSCON_USB1CLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9510 | #define SYSCON_USB1CLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9511 | #define SYSCON_USB1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9512 | |
| AnnaBridge | 163:e59c8e839560 | 9513 | /*! @name FRGCTRL - Fractional rate divider */ |
| AnnaBridge | 163:e59c8e839560 | 9514 | #define SYSCON_FRGCTRL_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9515 | #define SYSCON_FRGCTRL_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9516 | #define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9517 | #define SYSCON_FRGCTRL_MULT_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 9518 | #define SYSCON_FRGCTRL_MULT_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 9519 | #define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9520 | |
| AnnaBridge | 163:e59c8e839560 | 9521 | /*! @name DMICCLKDIV - DMIC clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9522 | #define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9523 | #define SYSCON_DMICCLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9524 | #define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9525 | #define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9526 | #define SYSCON_DMICCLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9527 | #define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9528 | #define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9529 | #define SYSCON_DMICCLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9530 | #define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9531 | #define SYSCON_DMICCLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9532 | #define SYSCON_DMICCLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9533 | #define SYSCON_DMICCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9534 | |
| AnnaBridge | 163:e59c8e839560 | 9535 | /*! @name MCLKDIV - I2S MCLK clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9536 | #define SYSCON_MCLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9537 | #define SYSCON_MCLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9538 | #define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9539 | #define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9540 | #define SYSCON_MCLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9541 | #define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9542 | #define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9543 | #define SYSCON_MCLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9544 | #define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9545 | #define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9546 | #define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9547 | #define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9548 | |
| AnnaBridge | 163:e59c8e839560 | 9549 | /*! @name LCDCLKDIV - LCD clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9550 | #define SYSCON_LCDCLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9551 | #define SYSCON_LCDCLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9552 | #define SYSCON_LCDCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9553 | #define SYSCON_LCDCLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9554 | #define SYSCON_LCDCLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9555 | #define SYSCON_LCDCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9556 | #define SYSCON_LCDCLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9557 | #define SYSCON_LCDCLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9558 | #define SYSCON_LCDCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9559 | #define SYSCON_LCDCLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9560 | #define SYSCON_LCDCLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9561 | #define SYSCON_LCDCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9562 | |
| AnnaBridge | 163:e59c8e839560 | 9563 | /*! @name SCTCLKDIV - SCT/PWM clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9564 | #define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9565 | #define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9566 | #define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9567 | #define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9568 | #define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9569 | #define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9570 | #define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9571 | #define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9572 | #define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9573 | #define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9574 | #define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9575 | #define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9576 | |
| AnnaBridge | 163:e59c8e839560 | 9577 | /*! @name EMCCLKDIV - EMC clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9578 | #define SYSCON_EMCCLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9579 | #define SYSCON_EMCCLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9580 | #define SYSCON_EMCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9581 | #define SYSCON_EMCCLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9582 | #define SYSCON_EMCCLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9583 | #define SYSCON_EMCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9584 | #define SYSCON_EMCCLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9585 | #define SYSCON_EMCCLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9586 | #define SYSCON_EMCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9587 | #define SYSCON_EMCCLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9588 | #define SYSCON_EMCCLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9589 | #define SYSCON_EMCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9590 | |
| AnnaBridge | 163:e59c8e839560 | 9591 | /*! @name SDIOCLKDIV - SDIO clock divider */ |
| AnnaBridge | 163:e59c8e839560 | 9592 | #define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9593 | #define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9594 | #define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9595 | #define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 9596 | #define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 9597 | #define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9598 | #define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9599 | #define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9600 | #define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9601 | #define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9602 | #define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9603 | #define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9604 | |
| AnnaBridge | 163:e59c8e839560 | 9605 | /*! @name FLASHCFG - Flash wait states configuration */ |
| AnnaBridge | 163:e59c8e839560 | 9606 | #define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 9607 | #define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9608 | #define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9609 | #define SYSCON_FLASHCFG_DATACFG_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 9610 | #define SYSCON_FLASHCFG_DATACFG_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 9611 | #define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9612 | #define SYSCON_FLASHCFG_ACCEL_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 9613 | #define SYSCON_FLASHCFG_ACCEL_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 9614 | #define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9615 | #define SYSCON_FLASHCFG_PREFEN_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 9616 | #define SYSCON_FLASHCFG_PREFEN_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 9617 | #define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9618 | #define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 9619 | #define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 9620 | #define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9621 | #define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U) |
| AnnaBridge | 163:e59c8e839560 | 9622 | #define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 9623 | #define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9624 | |
| AnnaBridge | 163:e59c8e839560 | 9625 | /*! @name USB0CLKCTRL - USB0 clock control */ |
| AnnaBridge | 163:e59c8e839560 | 9626 | #define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9627 | #define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9628 | #define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9629 | #define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 9630 | #define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 9631 | #define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9632 | #define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 9633 | #define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 9634 | #define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9635 | #define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 9636 | #define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9637 | #define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9638 | #define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 9639 | #define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 9640 | #define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9641 | |
| AnnaBridge | 163:e59c8e839560 | 9642 | /*! @name USB0CLKSTAT - USB0 clock status */ |
| AnnaBridge | 163:e59c8e839560 | 9643 | #define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9644 | #define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9645 | #define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9646 | #define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 9647 | #define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 9648 | #define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9649 | |
| AnnaBridge | 163:e59c8e839560 | 9650 | /*! @name FREQMECTRL - Frequency measure register */ |
| AnnaBridge | 163:e59c8e839560 | 9651 | #define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU) |
| AnnaBridge | 163:e59c8e839560 | 9652 | #define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9653 | #define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9654 | #define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9655 | #define SYSCON_FREQMECTRL_PROG_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9656 | #define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9657 | |
| AnnaBridge | 163:e59c8e839560 | 9658 | /*! @name MCLKIO - MCLK input/output control */ |
| AnnaBridge | 163:e59c8e839560 | 9659 | #define SYSCON_MCLKIO_DIR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9660 | #define SYSCON_MCLKIO_DIR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9661 | #define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9662 | |
| AnnaBridge | 163:e59c8e839560 | 9663 | /*! @name USB1CLKCTRL - USB1 clock control */ |
| AnnaBridge | 163:e59c8e839560 | 9664 | #define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9665 | #define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9666 | #define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9667 | #define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 9668 | #define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 9669 | #define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9670 | #define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 9671 | #define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 9672 | #define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9673 | #define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 9674 | #define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9675 | #define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9676 | #define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 9677 | #define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 9678 | #define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9679 | |
| AnnaBridge | 163:e59c8e839560 | 9680 | /*! @name USB1CLKSTAT - USB1 clock status */ |
| AnnaBridge | 163:e59c8e839560 | 9681 | #define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9682 | #define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9683 | #define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9684 | #define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 9685 | #define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 9686 | #define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9687 | |
| AnnaBridge | 163:e59c8e839560 | 9688 | /*! @name EMCSYSCTRL - EMC system control */ |
| AnnaBridge | 163:e59c8e839560 | 9689 | #define SYSCON_EMCSYSCTRL_EMCSC_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9690 | #define SYSCON_EMCSYSCTRL_EMCSC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9691 | #define SYSCON_EMCSYSCTRL_EMCSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9692 | #define SYSCON_EMCSYSCTRL_EMCRD_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 9693 | #define SYSCON_EMCSYSCTRL_EMCRD_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 9694 | #define SYSCON_EMCSYSCTRL_EMCRD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9695 | #define SYSCON_EMCSYSCTRL_EMCBC_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 9696 | #define SYSCON_EMCSYSCTRL_EMCBC_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 9697 | #define SYSCON_EMCSYSCTRL_EMCBC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9698 | #define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 9699 | #define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9700 | #define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9701 | |
| AnnaBridge | 163:e59c8e839560 | 9702 | /*! @name EMCDLYCTRL - EMC clock delay control */ |
| AnnaBridge | 163:e59c8e839560 | 9703 | #define SYSCON_EMCDLYCTRL_CMD_DELAY_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 9704 | #define SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9705 | #define SYSCON_EMCDLYCTRL_CMD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_CMD_DELAY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9706 | #define SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK (0x1F00U) |
| AnnaBridge | 163:e59c8e839560 | 9707 | #define SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 9708 | #define SYSCON_EMCDLYCTRL_FBCLK_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9709 | |
| AnnaBridge | 163:e59c8e839560 | 9710 | /*! @name EMCDLYCAL - EMC delay chain calibration control */ |
| AnnaBridge | 163:e59c8e839560 | 9711 | #define SYSCON_EMCDLYCAL_CALVALUE_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9712 | #define SYSCON_EMCDLYCAL_CALVALUE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9713 | #define SYSCON_EMCDLYCAL_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_CALVALUE_SHIFT)) & SYSCON_EMCDLYCAL_CALVALUE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9714 | #define SYSCON_EMCDLYCAL_START_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 9715 | #define SYSCON_EMCDLYCAL_START_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 9716 | #define SYSCON_EMCDLYCAL_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_START_SHIFT)) & SYSCON_EMCDLYCAL_START_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9717 | #define SYSCON_EMCDLYCAL_DONE_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 9718 | #define SYSCON_EMCDLYCAL_DONE_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 9719 | #define SYSCON_EMCDLYCAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_DONE_SHIFT)) & SYSCON_EMCDLYCAL_DONE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9720 | |
| AnnaBridge | 163:e59c8e839560 | 9721 | /*! @name ETHPHYSEL - Ethernet PHY Selection */ |
| AnnaBridge | 163:e59c8e839560 | 9722 | #define SYSCON_ETHPHYSEL_PHY_SEL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 9723 | #define SYSCON_ETHPHYSEL_PHY_SEL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 9724 | #define SYSCON_ETHPHYSEL_PHY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9725 | |
| AnnaBridge | 163:e59c8e839560 | 9726 | /*! @name ETHSBDCTRL - Ethernet SBD flow control */ |
| AnnaBridge | 163:e59c8e839560 | 9727 | #define SYSCON_ETHSBDCTRL_SBD_CTRL_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 9728 | #define SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9729 | #define SYSCON_ETHSBDCTRL_SBD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9730 | |
| AnnaBridge | 163:e59c8e839560 | 9731 | /*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ |
| AnnaBridge | 163:e59c8e839560 | 9732 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 9733 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9734 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9735 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 9736 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 9737 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9738 | #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 9739 | #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 9740 | #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9741 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) |
| AnnaBridge | 163:e59c8e839560 | 9742 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 9743 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9744 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 9745 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 9746 | #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9747 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) |
| AnnaBridge | 163:e59c8e839560 | 9748 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 9749 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9750 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9751 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9752 | #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9753 | |
| AnnaBridge | 163:e59c8e839560 | 9754 | /*! @name FROCTRL - FRO oscillator control */ |
| AnnaBridge | 163:e59c8e839560 | 9755 | #define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU) |
| AnnaBridge | 163:e59c8e839560 | 9756 | #define SYSCON_FROCTRL_TRIM_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9757 | #define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9758 | #define SYSCON_FROCTRL_SEL_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 9759 | #define SYSCON_FROCTRL_SEL_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 9760 | #define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9761 | #define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 9762 | #define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 9763 | #define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9764 | #define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 9765 | #define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 9766 | #define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9767 | #define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 9768 | #define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 9769 | #define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9770 | #define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 9771 | #define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 9772 | #define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9773 | #define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 9774 | #define SYSCON_FROCTRL_WRTRIM_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 9775 | #define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9776 | |
| AnnaBridge | 163:e59c8e839560 | 9777 | /*! @name SYSOSCCTRL - System oscillator control */ |
| AnnaBridge | 163:e59c8e839560 | 9778 | #define SYSCON_SYSOSCCTRL_BYPASS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9779 | #define SYSCON_SYSOSCCTRL_BYPASS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9780 | #define SYSCON_SYSOSCCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_BYPASS_SHIFT)) & SYSCON_SYSOSCCTRL_BYPASS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9781 | #define SYSCON_SYSOSCCTRL_FREQRANGE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 9782 | #define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 9783 | #define SYSCON_SYSOSCCTRL_FREQRANGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9784 | |
| AnnaBridge | 163:e59c8e839560 | 9785 | /*! @name WDTOSCCTRL - Watchdog oscillator control */ |
| AnnaBridge | 163:e59c8e839560 | 9786 | #define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 9787 | #define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9788 | #define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9789 | #define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U) |
| AnnaBridge | 163:e59c8e839560 | 9790 | #define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 9791 | #define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9792 | |
| AnnaBridge | 163:e59c8e839560 | 9793 | /*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */ |
| AnnaBridge | 163:e59c8e839560 | 9794 | #define SYSCON_RTCOSCCTRL_EN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9795 | #define SYSCON_RTCOSCCTRL_EN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9796 | #define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9797 | |
| AnnaBridge | 163:e59c8e839560 | 9798 | /*! @name USBPLLCTRL - USB PLL control */ |
| AnnaBridge | 163:e59c8e839560 | 9799 | #define SYSCON_USBPLLCTRL_MSEL_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 9800 | #define SYSCON_USBPLLCTRL_MSEL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9801 | #define SYSCON_USBPLLCTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9802 | #define SYSCON_USBPLLCTRL_PSEL_MASK (0x300U) |
| AnnaBridge | 163:e59c8e839560 | 9803 | #define SYSCON_USBPLLCTRL_PSEL_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 9804 | #define SYSCON_USBPLLCTRL_PSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9805 | #define SYSCON_USBPLLCTRL_NSEL_MASK (0xC00U) |
| AnnaBridge | 163:e59c8e839560 | 9806 | #define SYSCON_USBPLLCTRL_NSEL_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 9807 | #define SYSCON_USBPLLCTRL_NSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9808 | #define SYSCON_USBPLLCTRL_DIRECT_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 9809 | #define SYSCON_USBPLLCTRL_DIRECT_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 9810 | #define SYSCON_USBPLLCTRL_DIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9811 | #define SYSCON_USBPLLCTRL_BYPASS_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 9812 | #define SYSCON_USBPLLCTRL_BYPASS_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 9813 | #define SYSCON_USBPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9814 | #define SYSCON_USBPLLCTRL_FBSEL_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 9815 | #define SYSCON_USBPLLCTRL_FBSEL_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 9816 | #define SYSCON_USBPLLCTRL_FBSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9817 | |
| AnnaBridge | 163:e59c8e839560 | 9818 | /*! @name USBPLLSTAT - USB PLL status */ |
| AnnaBridge | 163:e59c8e839560 | 9819 | #define SYSCON_USBPLLSTAT_LOCK_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9820 | #define SYSCON_USBPLLSTAT_LOCK_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9821 | #define SYSCON_USBPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9822 | |
| AnnaBridge | 163:e59c8e839560 | 9823 | /*! @name SYSPLLCTRL - System PLL control */ |
| AnnaBridge | 163:e59c8e839560 | 9824 | #define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 9825 | #define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9826 | #define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9827 | #define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U) |
| AnnaBridge | 163:e59c8e839560 | 9828 | #define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 9829 | #define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9830 | #define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U) |
| AnnaBridge | 163:e59c8e839560 | 9831 | #define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 9832 | #define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9833 | #define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 9834 | #define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 9835 | #define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9836 | #define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 9837 | #define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 9838 | #define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9839 | #define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 9840 | #define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 9841 | #define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9842 | #define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 9843 | #define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 9844 | #define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9845 | |
| AnnaBridge | 163:e59c8e839560 | 9846 | /*! @name SYSPLLSTAT - PLL status */ |
| AnnaBridge | 163:e59c8e839560 | 9847 | #define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9848 | #define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9849 | #define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9850 | |
| AnnaBridge | 163:e59c8e839560 | 9851 | /*! @name SYSPLLNDEC - PLL N divider */ |
| AnnaBridge | 163:e59c8e839560 | 9852 | #define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU) |
| AnnaBridge | 163:e59c8e839560 | 9853 | #define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9854 | #define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9855 | #define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 9856 | #define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 9857 | #define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9858 | |
| AnnaBridge | 163:e59c8e839560 | 9859 | /*! @name SYSPLLPDEC - PLL P divider */ |
| AnnaBridge | 163:e59c8e839560 | 9860 | #define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU) |
| AnnaBridge | 163:e59c8e839560 | 9861 | #define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9862 | #define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9863 | #define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 9864 | #define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 9865 | #define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9866 | |
| AnnaBridge | 163:e59c8e839560 | 9867 | /*! @name SYSPLLMDEC - System PLL M divider */ |
| AnnaBridge | 163:e59c8e839560 | 9868 | #define SYSCON_SYSPLLMDEC_MDEC_MASK (0x1FFFFU) |
| AnnaBridge | 163:e59c8e839560 | 9869 | #define SYSCON_SYSPLLMDEC_MDEC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9870 | #define SYSCON_SYSPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9871 | #define SYSCON_SYSPLLMDEC_MREQ_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 9872 | #define SYSCON_SYSPLLMDEC_MREQ_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 9873 | #define SYSCON_SYSPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9874 | |
| AnnaBridge | 163:e59c8e839560 | 9875 | /*! @name AUDPLLCTRL - Audio PLL control */ |
| AnnaBridge | 163:e59c8e839560 | 9876 | #define SYSCON_AUDPLLCTRL_SELR_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 9877 | #define SYSCON_AUDPLLCTRL_SELR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9878 | #define SYSCON_AUDPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9879 | #define SYSCON_AUDPLLCTRL_SELI_MASK (0x3F0U) |
| AnnaBridge | 163:e59c8e839560 | 9880 | #define SYSCON_AUDPLLCTRL_SELI_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 9881 | #define SYSCON_AUDPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9882 | #define SYSCON_AUDPLLCTRL_SELP_MASK (0x7C00U) |
| AnnaBridge | 163:e59c8e839560 | 9883 | #define SYSCON_AUDPLLCTRL_SELP_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 9884 | #define SYSCON_AUDPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9885 | #define SYSCON_AUDPLLCTRL_BYPASS_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 9886 | #define SYSCON_AUDPLLCTRL_BYPASS_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 9887 | #define SYSCON_AUDPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9888 | #define SYSCON_AUDPLLCTRL_UPLIMOFF_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 9889 | #define SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 9890 | #define SYSCON_AUDPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9891 | #define SYSCON_AUDPLLCTRL_DIRECTI_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 9892 | #define SYSCON_AUDPLLCTRL_DIRECTI_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 9893 | #define SYSCON_AUDPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9894 | #define SYSCON_AUDPLLCTRL_DIRECTO_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 9895 | #define SYSCON_AUDPLLCTRL_DIRECTO_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 9896 | #define SYSCON_AUDPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9897 | |
| AnnaBridge | 163:e59c8e839560 | 9898 | /*! @name AUDPLLSTAT - Audio PLL status */ |
| AnnaBridge | 163:e59c8e839560 | 9899 | #define SYSCON_AUDPLLSTAT_LOCK_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9900 | #define SYSCON_AUDPLLSTAT_LOCK_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9901 | #define SYSCON_AUDPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9902 | |
| AnnaBridge | 163:e59c8e839560 | 9903 | /*! @name AUDPLLNDEC - Audio PLL N divider */ |
| AnnaBridge | 163:e59c8e839560 | 9904 | #define SYSCON_AUDPLLNDEC_NDEC_MASK (0x3FFU) |
| AnnaBridge | 163:e59c8e839560 | 9905 | #define SYSCON_AUDPLLNDEC_NDEC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9906 | #define SYSCON_AUDPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9907 | #define SYSCON_AUDPLLNDEC_NREQ_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 9908 | #define SYSCON_AUDPLLNDEC_NREQ_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 9909 | #define SYSCON_AUDPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9910 | |
| AnnaBridge | 163:e59c8e839560 | 9911 | /*! @name AUDPLLPDEC - Audio PLL P divider */ |
| AnnaBridge | 163:e59c8e839560 | 9912 | #define SYSCON_AUDPLLPDEC_PDEC_MASK (0x7FU) |
| AnnaBridge | 163:e59c8e839560 | 9913 | #define SYSCON_AUDPLLPDEC_PDEC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9914 | #define SYSCON_AUDPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9915 | #define SYSCON_AUDPLLPDEC_PREQ_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 9916 | #define SYSCON_AUDPLLPDEC_PREQ_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 9917 | #define SYSCON_AUDPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9918 | |
| AnnaBridge | 163:e59c8e839560 | 9919 | /*! @name AUDPLLMDEC - Audio PLL M divider */ |
| AnnaBridge | 163:e59c8e839560 | 9920 | #define SYSCON_AUDPLLMDEC_MDEC_MASK (0x1FFFFU) |
| AnnaBridge | 163:e59c8e839560 | 9921 | #define SYSCON_AUDPLLMDEC_MDEC_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9922 | #define SYSCON_AUDPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9923 | #define SYSCON_AUDPLLMDEC_MREQ_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 9924 | #define SYSCON_AUDPLLMDEC_MREQ_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 9925 | #define SYSCON_AUDPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9926 | |
| AnnaBridge | 163:e59c8e839560 | 9927 | /*! @name AUDPLLFRAC - Audio PLL fractional divider control */ |
| AnnaBridge | 163:e59c8e839560 | 9928 | #define SYSCON_AUDPLLFRAC_CTRL_MASK (0x3FFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 9929 | #define SYSCON_AUDPLLFRAC_CTRL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9930 | #define SYSCON_AUDPLLFRAC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9931 | #define SYSCON_AUDPLLFRAC_REQ_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 9932 | #define SYSCON_AUDPLLFRAC_REQ_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 9933 | #define SYSCON_AUDPLLFRAC_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9934 | #define SYSCON_AUDPLLFRAC_SEL_EXT_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 9935 | #define SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 9936 | #define SYSCON_AUDPLLFRAC_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9937 | |
| AnnaBridge | 163:e59c8e839560 | 9938 | /*! @name PDSLEEPCFG - Power configuration register 0 */ |
| AnnaBridge | 163:e59c8e839560 | 9939 | #define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 9940 | #define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 9941 | #define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9942 | #define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 9943 | #define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 9944 | #define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9945 | #define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 9946 | #define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 9947 | #define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9948 | #define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 9949 | #define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 9950 | #define SYSCON_PDSLEEPCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9951 | #define SYSCON_PDSLEEPCFG_PDEN_FRO_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 9952 | #define SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 9953 | #define SYSCON_PDSLEEPCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9954 | #define SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 9955 | #define SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 9956 | #define SYSCON_PDSLEEPCFG_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9957 | #define SYSCON_PDSLEEPCFG_PDEN_TS_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 9958 | #define SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 9959 | #define SYSCON_PDSLEEPCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9960 | #define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 9961 | #define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 9962 | #define SYSCON_PDSLEEPCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9963 | #define SYSCON_PDSLEEPCFG_PDEN_RNG_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 9964 | #define SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 9965 | #define SYSCON_PDSLEEPCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9966 | #define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 9967 | #define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 9968 | #define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9969 | #define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 9970 | #define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 9971 | #define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9972 | #define SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 9973 | #define SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 9974 | #define SYSCON_PDSLEEPCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9975 | #define SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 9976 | #define SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 9977 | #define SYSCON_PDSLEEPCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9978 | #define SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 9979 | #define SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 9980 | #define SYSCON_PDSLEEPCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9981 | #define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 9982 | #define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 9983 | #define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9984 | #define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 9985 | #define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 9986 | #define SYSCON_PDSLEEPCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9987 | #define SYSCON_PDSLEEPCFG_PDEN_ROM_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 9988 | #define SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 9989 | #define SYSCON_PDSLEEPCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9990 | #define SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 9991 | #define SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 9992 | #define SYSCON_PDSLEEPCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9993 | #define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 9994 | #define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 9995 | #define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9996 | #define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 9997 | #define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 9998 | #define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 9999 | #define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 10000 | #define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 10001 | #define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10002 | #define SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 10003 | #define SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 10004 | #define SYSCON_PDSLEEPCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10005 | #define SYSCON_PDSLEEPCFG_PDEN_VD3_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 10006 | #define SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 10007 | #define SYSCON_PDSLEEPCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10008 | #define SYSCON_PDSLEEPCFG_PDEN_VD4_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 10009 | #define SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 10010 | #define SYSCON_PDSLEEPCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10011 | #define SYSCON_PDSLEEPCFG_PDEN_VD5_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 10012 | #define SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 10013 | #define SYSCON_PDSLEEPCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10014 | #define SYSCON_PDSLEEPCFG_PDEN_VD6_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 10015 | #define SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 10016 | #define SYSCON_PDSLEEPCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10017 | |
| AnnaBridge | 163:e59c8e839560 | 10018 | /* The count of SYSCON_PDSLEEPCFG */ |
| AnnaBridge | 163:e59c8e839560 | 10019 | #define SYSCON_PDSLEEPCFG_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10020 | |
| AnnaBridge | 163:e59c8e839560 | 10021 | /*! @name PDRUNCFG - Power configuration register 0 */ |
| AnnaBridge | 163:e59c8e839560 | 10022 | #define SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10023 | #define SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10024 | #define SYSCON_PDRUNCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10025 | #define SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10026 | #define SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10027 | #define SYSCON_PDRUNCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10028 | #define SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 10029 | #define SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10030 | #define SYSCON_PDRUNCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10031 | #define SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10032 | #define SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10033 | #define SYSCON_PDRUNCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10034 | #define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 10035 | #define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 10036 | #define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10037 | #define SYSCON_PDRUNCFG_PDEN_EEPROM_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 10038 | #define SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 10039 | #define SYSCON_PDRUNCFG_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_EEPROM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10040 | #define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 10041 | #define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 10042 | #define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10043 | #define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 10044 | #define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 10045 | #define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10046 | #define SYSCON_PDRUNCFG_PDEN_RNG_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 10047 | #define SYSCON_PDRUNCFG_PDEN_RNG_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 10048 | #define SYSCON_PDRUNCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10049 | #define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 10050 | #define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 10051 | #define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10052 | #define SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 10053 | #define SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 10054 | #define SYSCON_PDRUNCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10055 | #define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 10056 | #define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 10057 | #define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10058 | #define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 10059 | #define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 10060 | #define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10061 | #define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 10062 | #define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 10063 | #define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10064 | #define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10065 | #define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10066 | #define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10067 | #define SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 10068 | #define SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10069 | #define SYSCON_PDRUNCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10070 | #define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 10071 | #define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 10072 | #define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10073 | #define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 10074 | #define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 10075 | #define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10076 | #define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 10077 | #define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 10078 | #define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10079 | #define SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 10080 | #define SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 10081 | #define SYSCON_PDRUNCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10082 | #define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 10083 | #define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 10084 | #define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10085 | #define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 10086 | #define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 10087 | #define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10088 | #define SYSCON_PDRUNCFG_PDEN_VD3_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 10089 | #define SYSCON_PDRUNCFG_PDEN_VD3_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 10090 | #define SYSCON_PDRUNCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10091 | #define SYSCON_PDRUNCFG_PDEN_VD4_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 10092 | #define SYSCON_PDRUNCFG_PDEN_VD4_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 10093 | #define SYSCON_PDRUNCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10094 | #define SYSCON_PDRUNCFG_PDEN_VD5_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 10095 | #define SYSCON_PDRUNCFG_PDEN_VD5_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 10096 | #define SYSCON_PDRUNCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10097 | #define SYSCON_PDRUNCFG_PDEN_VD6_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 10098 | #define SYSCON_PDRUNCFG_PDEN_VD6_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 10099 | #define SYSCON_PDRUNCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10100 | |
| AnnaBridge | 163:e59c8e839560 | 10101 | /* The count of SYSCON_PDRUNCFG */ |
| AnnaBridge | 163:e59c8e839560 | 10102 | #define SYSCON_PDRUNCFG_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10103 | |
| AnnaBridge | 163:e59c8e839560 | 10104 | /*! @name PDRUNCFGSET - Set bits in PDRUNCFG0 */ |
| AnnaBridge | 163:e59c8e839560 | 10105 | #define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10106 | #define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10107 | #define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10108 | #define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10109 | #define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10110 | #define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10111 | #define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 10112 | #define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10113 | #define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10114 | #define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10115 | #define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10116 | #define SYSCON_PDRUNCFGSET_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10117 | #define SYSCON_PDRUNCFGSET_PDEN_FRO_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 10118 | #define SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 10119 | #define SYSCON_PDRUNCFGSET_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10120 | #define SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 10121 | #define SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 10122 | #define SYSCON_PDRUNCFGSET_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10123 | #define SYSCON_PDRUNCFGSET_PDEN_TS_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 10124 | #define SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 10125 | #define SYSCON_PDRUNCFGSET_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10126 | #define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 10127 | #define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 10128 | #define SYSCON_PDRUNCFGSET_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10129 | #define SYSCON_PDRUNCFGSET_PDEN_RNG_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 10130 | #define SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 10131 | #define SYSCON_PDRUNCFGSET_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10132 | #define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 10133 | #define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 10134 | #define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10135 | #define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 10136 | #define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 10137 | #define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10138 | #define SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 10139 | #define SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 10140 | #define SYSCON_PDRUNCFGSET_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10141 | #define SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 10142 | #define SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 10143 | #define SYSCON_PDRUNCFGSET_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10144 | #define SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 10145 | #define SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 10146 | #define SYSCON_PDRUNCFGSET_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10147 | #define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10148 | #define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10149 | #define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10150 | #define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 10151 | #define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10152 | #define SYSCON_PDRUNCFGSET_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10153 | #define SYSCON_PDRUNCFGSET_PDEN_ROM_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 10154 | #define SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 10155 | #define SYSCON_PDRUNCFGSET_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10156 | #define SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 10157 | #define SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 10158 | #define SYSCON_PDRUNCFGSET_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10159 | #define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 10160 | #define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 10161 | #define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10162 | #define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 10163 | #define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 10164 | #define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10165 | #define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 10166 | #define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 10167 | #define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10168 | #define SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 10169 | #define SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 10170 | #define SYSCON_PDRUNCFGSET_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10171 | #define SYSCON_PDRUNCFGSET_PDEN_VD3_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 10172 | #define SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 10173 | #define SYSCON_PDRUNCFGSET_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10174 | #define SYSCON_PDRUNCFGSET_PDEN_VD4_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 10175 | #define SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 10176 | #define SYSCON_PDRUNCFGSET_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10177 | #define SYSCON_PDRUNCFGSET_PDEN_VD5_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 10178 | #define SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 10179 | #define SYSCON_PDRUNCFGSET_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10180 | #define SYSCON_PDRUNCFGSET_PDEN_VD6_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 10181 | #define SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 10182 | #define SYSCON_PDRUNCFGSET_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10183 | |
| AnnaBridge | 163:e59c8e839560 | 10184 | /* The count of SYSCON_PDRUNCFGSET */ |
| AnnaBridge | 163:e59c8e839560 | 10185 | #define SYSCON_PDRUNCFGSET_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10186 | |
| AnnaBridge | 163:e59c8e839560 | 10187 | /*! @name PDRUNCFGCLR - Clear bits in PDRUNCFG0 */ |
| AnnaBridge | 163:e59c8e839560 | 10188 | #define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10189 | #define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10190 | #define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10191 | #define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10192 | #define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10193 | #define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10194 | #define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 10195 | #define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10196 | #define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10197 | #define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10198 | #define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10199 | #define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10200 | #define SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 10201 | #define SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 10202 | #define SYSCON_PDRUNCFGCLR_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10203 | #define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 10204 | #define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 10205 | #define SYSCON_PDRUNCFGCLR_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10206 | #define SYSCON_PDRUNCFGCLR_PDEN_TS_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 10207 | #define SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 10208 | #define SYSCON_PDRUNCFGCLR_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10209 | #define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 10210 | #define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 10211 | #define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10212 | #define SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 10213 | #define SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 10214 | #define SYSCON_PDRUNCFGCLR_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10215 | #define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 10216 | #define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 10217 | #define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10218 | #define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 10219 | #define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 10220 | #define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10221 | #define SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 10222 | #define SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 10223 | #define SYSCON_PDRUNCFGCLR_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10224 | #define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 10225 | #define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 10226 | #define SYSCON_PDRUNCFGCLR_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10227 | #define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 10228 | #define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 10229 | #define SYSCON_PDRUNCFGCLR_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10230 | #define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10231 | #define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10232 | #define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10233 | #define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 10234 | #define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10235 | #define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10236 | #define SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 10237 | #define SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 10238 | #define SYSCON_PDRUNCFGCLR_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10239 | #define SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 10240 | #define SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 10241 | #define SYSCON_PDRUNCFGCLR_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10242 | #define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 10243 | #define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 10244 | #define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10245 | #define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 10246 | #define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 10247 | #define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10248 | #define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 10249 | #define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 10250 | #define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10251 | #define SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 10252 | #define SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 10253 | #define SYSCON_PDRUNCFGCLR_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10254 | #define SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 10255 | #define SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 10256 | #define SYSCON_PDRUNCFGCLR_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10257 | #define SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 10258 | #define SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 10259 | #define SYSCON_PDRUNCFGCLR_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10260 | #define SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 10261 | #define SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 10262 | #define SYSCON_PDRUNCFGCLR_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10263 | #define SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 10264 | #define SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 10265 | #define SYSCON_PDRUNCFGCLR_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10266 | |
| AnnaBridge | 163:e59c8e839560 | 10267 | /* The count of SYSCON_PDRUNCFGCLR */ |
| AnnaBridge | 163:e59c8e839560 | 10268 | #define SYSCON_PDRUNCFGCLR_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10269 | |
| AnnaBridge | 163:e59c8e839560 | 10270 | /*! @name STARTER - Start logic 0 wake-up enable register */ |
| AnnaBridge | 163:e59c8e839560 | 10271 | #define SYSCON_STARTER_WDT_BOD_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10272 | #define SYSCON_STARTER_WDT_BOD_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10273 | #define SYSCON_STARTER_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10274 | #define SYSCON_STARTER_PINT4_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10275 | #define SYSCON_STARTER_PINT4_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10276 | #define SYSCON_STARTER_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10277 | #define SYSCON_STARTER_PINT5_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10278 | #define SYSCON_STARTER_PINT5_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10279 | #define SYSCON_STARTER_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10280 | #define SYSCON_STARTER_DMA_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10281 | #define SYSCON_STARTER_DMA_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10282 | #define SYSCON_STARTER_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10283 | #define SYSCON_STARTER_GINT0_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 10284 | #define SYSCON_STARTER_GINT0_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10285 | #define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10286 | #define SYSCON_STARTER_PINT6_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 10287 | #define SYSCON_STARTER_PINT6_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10288 | #define SYSCON_STARTER_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10289 | #define SYSCON_STARTER_GINT1_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10290 | #define SYSCON_STARTER_GINT1_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10291 | #define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10292 | #define SYSCON_STARTER_PINT7_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10293 | #define SYSCON_STARTER_PINT7_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10294 | #define SYSCON_STARTER_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10295 | #define SYSCON_STARTER_CTIMER2_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 10296 | #define SYSCON_STARTER_CTIMER2_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 10297 | #define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10298 | #define SYSCON_STARTER_PIN_INT0_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 10299 | #define SYSCON_STARTER_PIN_INT0_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 10300 | #define SYSCON_STARTER_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10301 | #define SYSCON_STARTER_CTIMER4_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 10302 | #define SYSCON_STARTER_CTIMER4_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 10303 | #define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10304 | #define SYSCON_STARTER_PIN_INT1_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 10305 | #define SYSCON_STARTER_PIN_INT1_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 10306 | #define SYSCON_STARTER_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10307 | #define SYSCON_STARTER_PIN_INT2_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 10308 | #define SYSCON_STARTER_PIN_INT2_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 10309 | #define SYSCON_STARTER_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10310 | #define SYSCON_STARTER_PIN_INT3_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 10311 | #define SYSCON_STARTER_PIN_INT3_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 10312 | #define SYSCON_STARTER_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10313 | #define SYSCON_STARTER_SPIFI_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 10314 | #define SYSCON_STARTER_SPIFI_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 10315 | #define SYSCON_STARTER_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPIFI_SHIFT)) & SYSCON_STARTER_SPIFI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10316 | #define SYSCON_STARTER_FLEXCOMM8_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 10317 | #define SYSCON_STARTER_FLEXCOMM8_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 10318 | #define SYSCON_STARTER_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10319 | #define SYSCON_STARTER_UTICK_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 10320 | #define SYSCON_STARTER_UTICK_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 10321 | #define SYSCON_STARTER_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10322 | #define SYSCON_STARTER_MRT_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 10323 | #define SYSCON_STARTER_MRT_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 10324 | #define SYSCON_STARTER_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT_SHIFT)) & SYSCON_STARTER_MRT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10325 | #define SYSCON_STARTER_FLEXCOMM9_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 10326 | #define SYSCON_STARTER_FLEXCOMM9_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 10327 | #define SYSCON_STARTER_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10328 | #define SYSCON_STARTER_CTIMER0_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 10329 | #define SYSCON_STARTER_CTIMER0_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 10330 | #define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10331 | #define SYSCON_STARTER_CTIMER1_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 10332 | #define SYSCON_STARTER_CTIMER1_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 10333 | #define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10334 | #define SYSCON_STARTER_SCT0_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 10335 | #define SYSCON_STARTER_SCT0_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 10336 | #define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10337 | #define SYSCON_STARTER_CTIMER3_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 10338 | #define SYSCON_STARTER_CTIMER3_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 10339 | #define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10340 | #define SYSCON_STARTER_FLEXCOMM0_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 10341 | #define SYSCON_STARTER_FLEXCOMM0_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 10342 | #define SYSCON_STARTER_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10343 | #define SYSCON_STARTER_FLEXCOMM1_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10344 | #define SYSCON_STARTER_FLEXCOMM1_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10345 | #define SYSCON_STARTER_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10346 | #define SYSCON_STARTER_USB1_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10347 | #define SYSCON_STARTER_USB1_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10348 | #define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10349 | #define SYSCON_STARTER_FLEXCOMM2_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 10350 | #define SYSCON_STARTER_FLEXCOMM2_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10351 | #define SYSCON_STARTER_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10352 | #define SYSCON_STARTER_USB1_ACT_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 10353 | #define SYSCON_STARTER_USB1_ACT_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10354 | #define SYSCON_STARTER_USB1_ACT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10355 | #define SYSCON_STARTER_ENET_INT1_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 10356 | #define SYSCON_STARTER_ENET_INT1_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 10357 | #define SYSCON_STARTER_ENET_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT1_SHIFT)) & SYSCON_STARTER_ENET_INT1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10358 | #define SYSCON_STARTER_FLEXCOMM3_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 10359 | #define SYSCON_STARTER_FLEXCOMM3_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 10360 | #define SYSCON_STARTER_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10361 | #define SYSCON_STARTER_ENET_INT2_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 10362 | #define SYSCON_STARTER_ENET_INT2_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 10363 | #define SYSCON_STARTER_ENET_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT2_SHIFT)) & SYSCON_STARTER_ENET_INT2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10364 | #define SYSCON_STARTER_FLEXCOMM4_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 10365 | #define SYSCON_STARTER_FLEXCOMM4_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 10366 | #define SYSCON_STARTER_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10367 | #define SYSCON_STARTER_ENET_INT0_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 10368 | #define SYSCON_STARTER_ENET_INT0_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 10369 | #define SYSCON_STARTER_ENET_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT0_SHIFT)) & SYSCON_STARTER_ENET_INT0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10370 | #define SYSCON_STARTER_FLEXCOMM5_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 10371 | #define SYSCON_STARTER_FLEXCOMM5_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 10372 | #define SYSCON_STARTER_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10373 | #define SYSCON_STARTER_FLEXCOMM6_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 10374 | #define SYSCON_STARTER_FLEXCOMM6_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 10375 | #define SYSCON_STARTER_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10376 | #define SYSCON_STARTER_FLEXCOMM7_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 10377 | #define SYSCON_STARTER_FLEXCOMM7_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 10378 | #define SYSCON_STARTER_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10379 | #define SYSCON_STARTER_ADC0_SEQA_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 10380 | #define SYSCON_STARTER_ADC0_SEQA_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 10381 | #define SYSCON_STARTER_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQA_SHIFT)) & SYSCON_STARTER_ADC0_SEQA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10382 | #define SYSCON_STARTER_SMARTCARD0_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 10383 | #define SYSCON_STARTER_SMARTCARD0_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 10384 | #define SYSCON_STARTER_SMARTCARD0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD0_SHIFT)) & SYSCON_STARTER_SMARTCARD0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10385 | #define SYSCON_STARTER_ADC0_SEQB_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 10386 | #define SYSCON_STARTER_ADC0_SEQB_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 10387 | #define SYSCON_STARTER_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQB_SHIFT)) & SYSCON_STARTER_ADC0_SEQB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10388 | #define SYSCON_STARTER_ADC0_THCMP_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 10389 | #define SYSCON_STARTER_ADC0_THCMP_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 10390 | #define SYSCON_STARTER_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10391 | #define SYSCON_STARTER_SMARTCARD1_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 10392 | #define SYSCON_STARTER_SMARTCARD1_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 10393 | #define SYSCON_STARTER_SMARTCARD1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD1_SHIFT)) & SYSCON_STARTER_SMARTCARD1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10394 | #define SYSCON_STARTER_DMIC_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 10395 | #define SYSCON_STARTER_DMIC_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 10396 | #define SYSCON_STARTER_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10397 | #define SYSCON_STARTER_HWVAD_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 10398 | #define SYSCON_STARTER_HWVAD_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 10399 | #define SYSCON_STARTER_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10400 | #define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) |
| AnnaBridge | 163:e59c8e839560 | 10401 | #define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) |
| AnnaBridge | 163:e59c8e839560 | 10402 | #define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10403 | #define SYSCON_STARTER_USB0_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 10404 | #define SYSCON_STARTER_USB0_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 10405 | #define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10406 | #define SYSCON_STARTER_RTC_MASK (0x20000000U) |
| AnnaBridge | 163:e59c8e839560 | 10407 | #define SYSCON_STARTER_RTC_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 10408 | #define SYSCON_STARTER_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10409 | |
| AnnaBridge | 163:e59c8e839560 | 10410 | /* The count of SYSCON_STARTER */ |
| AnnaBridge | 163:e59c8e839560 | 10411 | #define SYSCON_STARTER_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10412 | |
| AnnaBridge | 163:e59c8e839560 | 10413 | /*! @name STARTERSET - Set bits in STARTER */ |
| AnnaBridge | 163:e59c8e839560 | 10414 | #define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 10415 | #define SYSCON_STARTERSET_START_SET_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10416 | #define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10417 | |
| AnnaBridge | 163:e59c8e839560 | 10418 | /* The count of SYSCON_STARTERSET */ |
| AnnaBridge | 163:e59c8e839560 | 10419 | #define SYSCON_STARTERSET_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10420 | |
| AnnaBridge | 163:e59c8e839560 | 10421 | /*! @name STARTERCLR - Clear bits in STARTER0 */ |
| AnnaBridge | 163:e59c8e839560 | 10422 | #define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 10423 | #define SYSCON_STARTERCLR_START_CLR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10424 | #define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10425 | |
| AnnaBridge | 163:e59c8e839560 | 10426 | /* The count of SYSCON_STARTERCLR */ |
| AnnaBridge | 163:e59c8e839560 | 10427 | #define SYSCON_STARTERCLR_COUNT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10428 | |
| AnnaBridge | 163:e59c8e839560 | 10429 | /*! @name HWWAKE - Configures special cases of hardware wake-up */ |
| AnnaBridge | 163:e59c8e839560 | 10430 | #define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10431 | #define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10432 | #define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10433 | #define SYSCON_HWWAKE_FCWAKE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10434 | #define SYSCON_HWWAKE_FCWAKE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10435 | #define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10436 | #define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 10437 | #define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10438 | #define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10439 | #define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10440 | #define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10441 | #define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10442 | |
| AnnaBridge | 163:e59c8e839560 | 10443 | /*! @name AUTOCGOR - Auto Clock-Gate Override Register */ |
| AnnaBridge | 163:e59c8e839560 | 10444 | #define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10445 | #define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10446 | #define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10447 | #define SYSCON_AUTOCGOR_RAM1_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 10448 | #define SYSCON_AUTOCGOR_RAM1_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10449 | #define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10450 | #define SYSCON_AUTOCGOR_RAM2_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10451 | #define SYSCON_AUTOCGOR_RAM2_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10452 | #define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10453 | #define SYSCON_AUTOCGOR_RAM3_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 10454 | #define SYSCON_AUTOCGOR_RAM3_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 10455 | #define SYSCON_AUTOCGOR_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10456 | |
| AnnaBridge | 163:e59c8e839560 | 10457 | /*! @name JTAGIDCODE - JTAG ID code register */ |
| AnnaBridge | 163:e59c8e839560 | 10458 | #define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 10459 | #define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10460 | #define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10461 | |
| AnnaBridge | 163:e59c8e839560 | 10462 | /*! @name DEVICE_ID0 - Part ID register */ |
| AnnaBridge | 163:e59c8e839560 | 10463 | #define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 10464 | #define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10465 | #define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10466 | |
| AnnaBridge | 163:e59c8e839560 | 10467 | /*! @name DEVICE_ID1 - Boot ROM and die revision register */ |
| AnnaBridge | 163:e59c8e839560 | 10468 | #define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 10469 | #define SYSCON_DEVICE_ID1_REVID_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10470 | #define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10471 | |
| AnnaBridge | 163:e59c8e839560 | 10472 | /*! @name BODCTRL - Brown-Out Detect control */ |
| AnnaBridge | 163:e59c8e839560 | 10473 | #define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 10474 | #define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10475 | #define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10476 | #define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 10477 | #define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10478 | #define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10479 | #define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U) |
| AnnaBridge | 163:e59c8e839560 | 10480 | #define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10481 | #define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10482 | #define SYSCON_BODCTRL_BODINTENA_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 10483 | #define SYSCON_BODCTRL_BODINTENA_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 10484 | #define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10485 | #define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 10486 | #define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 10487 | #define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10488 | #define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 10489 | #define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 10490 | #define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10491 | |
| AnnaBridge | 163:e59c8e839560 | 10492 | |
| AnnaBridge | 163:e59c8e839560 | 10493 | /*! |
| AnnaBridge | 163:e59c8e839560 | 10494 | * @} |
| AnnaBridge | 163:e59c8e839560 | 10495 | */ /* end of group SYSCON_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 10496 | |
| AnnaBridge | 163:e59c8e839560 | 10497 | |
| AnnaBridge | 163:e59c8e839560 | 10498 | /* SYSCON - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 10499 | /** Peripheral SYSCON base address */ |
| AnnaBridge | 163:e59c8e839560 | 10500 | #define SYSCON_BASE (0x40000000u) |
| AnnaBridge | 163:e59c8e839560 | 10501 | /** Peripheral SYSCON base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 10502 | #define SYSCON ((SYSCON_Type *)SYSCON_BASE) |
| AnnaBridge | 163:e59c8e839560 | 10503 | /** Array initializer of SYSCON peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 10504 | #define SYSCON_BASE_ADDRS { SYSCON_BASE } |
| AnnaBridge | 163:e59c8e839560 | 10505 | /** Array initializer of SYSCON peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 10506 | #define SYSCON_BASE_PTRS { SYSCON } |
| AnnaBridge | 163:e59c8e839560 | 10507 | |
| AnnaBridge | 163:e59c8e839560 | 10508 | /*! |
| AnnaBridge | 163:e59c8e839560 | 10509 | * @} |
| AnnaBridge | 163:e59c8e839560 | 10510 | */ /* end of group SYSCON_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 10511 | |
| AnnaBridge | 163:e59c8e839560 | 10512 | |
| AnnaBridge | 163:e59c8e839560 | 10513 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 10514 | -- USART Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 10515 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 10516 | |
| AnnaBridge | 163:e59c8e839560 | 10517 | /*! |
| AnnaBridge | 163:e59c8e839560 | 10518 | * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 10519 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 10520 | */ |
| AnnaBridge | 163:e59c8e839560 | 10521 | |
| AnnaBridge | 163:e59c8e839560 | 10522 | /** USART - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 10523 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 10524 | __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 10525 | __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 10526 | __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 10527 | __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 10528 | __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 10529 | uint8_t RESERVED_0[12]; |
| AnnaBridge | 163:e59c8e839560 | 10530 | __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 10531 | __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 10532 | __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 10533 | __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 10534 | uint8_t RESERVED_1[3536]; |
| AnnaBridge | 163:e59c8e839560 | 10535 | __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ |
| AnnaBridge | 163:e59c8e839560 | 10536 | __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ |
| AnnaBridge | 163:e59c8e839560 | 10537 | __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ |
| AnnaBridge | 163:e59c8e839560 | 10538 | uint8_t RESERVED_2[4]; |
| AnnaBridge | 163:e59c8e839560 | 10539 | __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */ |
| AnnaBridge | 163:e59c8e839560 | 10540 | __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */ |
| AnnaBridge | 163:e59c8e839560 | 10541 | __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */ |
| AnnaBridge | 163:e59c8e839560 | 10542 | uint8_t RESERVED_3[4]; |
| AnnaBridge | 163:e59c8e839560 | 10543 | __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */ |
| AnnaBridge | 163:e59c8e839560 | 10544 | uint8_t RESERVED_4[12]; |
| AnnaBridge | 163:e59c8e839560 | 10545 | __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ |
| AnnaBridge | 163:e59c8e839560 | 10546 | uint8_t RESERVED_5[12]; |
| AnnaBridge | 163:e59c8e839560 | 10547 | __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ |
| AnnaBridge | 163:e59c8e839560 | 10548 | uint8_t RESERVED_6[440]; |
| AnnaBridge | 163:e59c8e839560 | 10549 | __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ |
| AnnaBridge | 163:e59c8e839560 | 10550 | } USART_Type; |
| AnnaBridge | 163:e59c8e839560 | 10551 | |
| AnnaBridge | 163:e59c8e839560 | 10552 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 10553 | -- USART Register Masks |
| AnnaBridge | 163:e59c8e839560 | 10554 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 10555 | |
| AnnaBridge | 163:e59c8e839560 | 10556 | /*! |
| AnnaBridge | 163:e59c8e839560 | 10557 | * @addtogroup USART_Register_Masks USART Register Masks |
| AnnaBridge | 163:e59c8e839560 | 10558 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 10559 | */ |
| AnnaBridge | 163:e59c8e839560 | 10560 | |
| AnnaBridge | 163:e59c8e839560 | 10561 | /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ |
| AnnaBridge | 163:e59c8e839560 | 10562 | #define USART_CFG_ENABLE_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10563 | #define USART_CFG_ENABLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10564 | #define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10565 | #define USART_CFG_DATALEN_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 10566 | #define USART_CFG_DATALEN_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10567 | #define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10568 | #define USART_CFG_PARITYSEL_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 10569 | #define USART_CFG_PARITYSEL_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 10570 | #define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10571 | #define USART_CFG_STOPLEN_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 10572 | #define USART_CFG_STOPLEN_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 10573 | #define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10574 | #define USART_CFG_MODE32K_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 10575 | #define USART_CFG_MODE32K_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 10576 | #define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10577 | #define USART_CFG_LINMODE_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 10578 | #define USART_CFG_LINMODE_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 10579 | #define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10580 | #define USART_CFG_CTSEN_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 10581 | #define USART_CFG_CTSEN_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 10582 | #define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10583 | #define USART_CFG_SYNCEN_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 10584 | #define USART_CFG_SYNCEN_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 10585 | #define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10586 | #define USART_CFG_CLKPOL_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 10587 | #define USART_CFG_CLKPOL_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 10588 | #define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10589 | #define USART_CFG_SYNCMST_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 10590 | #define USART_CFG_SYNCMST_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 10591 | #define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10592 | #define USART_CFG_LOOP_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10593 | #define USART_CFG_LOOP_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10594 | #define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10595 | #define USART_CFG_OETA_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 10596 | #define USART_CFG_OETA_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 10597 | #define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10598 | #define USART_CFG_AUTOADDR_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 10599 | #define USART_CFG_AUTOADDR_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 10600 | #define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10601 | #define USART_CFG_OESEL_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 10602 | #define USART_CFG_OESEL_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 10603 | #define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10604 | #define USART_CFG_OEPOL_MASK (0x200000U) |
| AnnaBridge | 163:e59c8e839560 | 10605 | #define USART_CFG_OEPOL_SHIFT (21U) |
| AnnaBridge | 163:e59c8e839560 | 10606 | #define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10607 | #define USART_CFG_RXPOL_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 10608 | #define USART_CFG_RXPOL_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 10609 | #define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10610 | #define USART_CFG_TXPOL_MASK (0x800000U) |
| AnnaBridge | 163:e59c8e839560 | 10611 | #define USART_CFG_TXPOL_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 10612 | #define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10613 | |
| AnnaBridge | 163:e59c8e839560 | 10614 | /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ |
| AnnaBridge | 163:e59c8e839560 | 10615 | #define USART_CTL_TXBRKEN_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10616 | #define USART_CTL_TXBRKEN_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10617 | #define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10618 | #define USART_CTL_ADDRDET_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 10619 | #define USART_CTL_ADDRDET_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10620 | #define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10621 | #define USART_CTL_TXDIS_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 10622 | #define USART_CTL_TXDIS_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 10623 | #define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10624 | #define USART_CTL_CC_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 10625 | #define USART_CTL_CC_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 10626 | #define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10627 | #define USART_CTL_CLRCCONRX_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 10628 | #define USART_CTL_CLRCCONRX_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 10629 | #define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10630 | #define USART_CTL_AUTOBAUD_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 10631 | #define USART_CTL_AUTOBAUD_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10632 | #define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10633 | |
| AnnaBridge | 163:e59c8e839560 | 10634 | /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ |
| AnnaBridge | 163:e59c8e839560 | 10635 | #define USART_STAT_RXIDLE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10636 | #define USART_STAT_RXIDLE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10637 | #define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10638 | #define USART_STAT_TXIDLE_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10639 | #define USART_STAT_TXIDLE_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10640 | #define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10641 | #define USART_STAT_CTS_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 10642 | #define USART_STAT_CTS_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 10643 | #define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10644 | #define USART_STAT_DELTACTS_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 10645 | #define USART_STAT_DELTACTS_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 10646 | #define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10647 | #define USART_STAT_TXDISSTAT_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 10648 | #define USART_STAT_TXDISSTAT_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 10649 | #define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10650 | #define USART_STAT_RXBRK_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 10651 | #define USART_STAT_RXBRK_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 10652 | #define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10653 | #define USART_STAT_DELTARXBRK_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 10654 | #define USART_STAT_DELTARXBRK_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 10655 | #define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10656 | #define USART_STAT_START_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 10657 | #define USART_STAT_START_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 10658 | #define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10659 | #define USART_STAT_FRAMERRINT_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 10660 | #define USART_STAT_FRAMERRINT_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 10661 | #define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10662 | #define USART_STAT_PARITYERRINT_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 10663 | #define USART_STAT_PARITYERRINT_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 10664 | #define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10665 | #define USART_STAT_RXNOISEINT_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10666 | #define USART_STAT_RXNOISEINT_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10667 | #define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10668 | #define USART_STAT_ABERR_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 10669 | #define USART_STAT_ABERR_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10670 | #define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10671 | |
| AnnaBridge | 163:e59c8e839560 | 10672 | /*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ |
| AnnaBridge | 163:e59c8e839560 | 10673 | #define USART_INTENSET_TXIDLEEN_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10674 | #define USART_INTENSET_TXIDLEEN_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10675 | #define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10676 | #define USART_INTENSET_DELTACTSEN_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 10677 | #define USART_INTENSET_DELTACTSEN_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 10678 | #define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10679 | #define USART_INTENSET_TXDISEN_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 10680 | #define USART_INTENSET_TXDISEN_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 10681 | #define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10682 | #define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 10683 | #define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 10684 | #define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10685 | #define USART_INTENSET_STARTEN_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 10686 | #define USART_INTENSET_STARTEN_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 10687 | #define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10688 | #define USART_INTENSET_FRAMERREN_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 10689 | #define USART_INTENSET_FRAMERREN_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 10690 | #define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10691 | #define USART_INTENSET_PARITYERREN_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 10692 | #define USART_INTENSET_PARITYERREN_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 10693 | #define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10694 | #define USART_INTENSET_RXNOISEEN_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10695 | #define USART_INTENSET_RXNOISEEN_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10696 | #define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10697 | #define USART_INTENSET_ABERREN_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 10698 | #define USART_INTENSET_ABERREN_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10699 | #define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10700 | |
| AnnaBridge | 163:e59c8e839560 | 10701 | /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ |
| AnnaBridge | 163:e59c8e839560 | 10702 | #define USART_INTENCLR_TXIDLECLR_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10703 | #define USART_INTENCLR_TXIDLECLR_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10704 | #define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10705 | #define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 10706 | #define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 10707 | #define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10708 | #define USART_INTENCLR_TXDISCLR_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 10709 | #define USART_INTENCLR_TXDISCLR_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 10710 | #define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10711 | #define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 10712 | #define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 10713 | #define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10714 | #define USART_INTENCLR_STARTCLR_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 10715 | #define USART_INTENCLR_STARTCLR_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 10716 | #define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10717 | #define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 10718 | #define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 10719 | #define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10720 | #define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 10721 | #define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 10722 | #define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10723 | #define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10724 | #define USART_INTENCLR_RXNOISECLR_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10725 | #define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10726 | #define USART_INTENCLR_ABERRCLR_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 10727 | #define USART_INTENCLR_ABERRCLR_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10728 | #define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10729 | |
| AnnaBridge | 163:e59c8e839560 | 10730 | /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ |
| AnnaBridge | 163:e59c8e839560 | 10731 | #define USART_BRG_BRGVAL_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 10732 | #define USART_BRG_BRGVAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10733 | #define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10734 | |
| AnnaBridge | 163:e59c8e839560 | 10735 | /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ |
| AnnaBridge | 163:e59c8e839560 | 10736 | #define USART_INTSTAT_TXIDLE_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10737 | #define USART_INTSTAT_TXIDLE_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10738 | #define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10739 | #define USART_INTSTAT_DELTACTS_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 10740 | #define USART_INTSTAT_DELTACTS_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 10741 | #define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10742 | #define USART_INTSTAT_TXDISINT_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 10743 | #define USART_INTSTAT_TXDISINT_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 10744 | #define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10745 | #define USART_INTSTAT_DELTARXBRK_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 10746 | #define USART_INTSTAT_DELTARXBRK_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 10747 | #define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10748 | #define USART_INTSTAT_START_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 10749 | #define USART_INTSTAT_START_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 10750 | #define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10751 | #define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 10752 | #define USART_INTSTAT_FRAMERRINT_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 10753 | #define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10754 | #define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 10755 | #define USART_INTSTAT_PARITYERRINT_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 10756 | #define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10757 | #define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10758 | #define USART_INTSTAT_RXNOISEINT_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10759 | #define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10760 | #define USART_INTSTAT_ABERRINT_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 10761 | #define USART_INTSTAT_ABERRINT_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10762 | #define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10763 | |
| AnnaBridge | 163:e59c8e839560 | 10764 | /*! @name OSR - Oversample selection register for asynchronous communication. */ |
| AnnaBridge | 163:e59c8e839560 | 10765 | #define USART_OSR_OSRVAL_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 10766 | #define USART_OSR_OSRVAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10767 | #define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10768 | |
| AnnaBridge | 163:e59c8e839560 | 10769 | /*! @name ADDR - Address register for automatic address matching. */ |
| AnnaBridge | 163:e59c8e839560 | 10770 | #define USART_ADDR_ADDRESS_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 10771 | #define USART_ADDR_ADDRESS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10772 | #define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10773 | |
| AnnaBridge | 163:e59c8e839560 | 10774 | /*! @name FIFOCFG - FIFO configuration and enable register. */ |
| AnnaBridge | 163:e59c8e839560 | 10775 | #define USART_FIFOCFG_ENABLETX_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10776 | #define USART_FIFOCFG_ENABLETX_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10777 | #define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10778 | #define USART_FIFOCFG_ENABLERX_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10779 | #define USART_FIFOCFG_ENABLERX_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10780 | #define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10781 | #define USART_FIFOCFG_SIZE_MASK (0x30U) |
| AnnaBridge | 163:e59c8e839560 | 10782 | #define USART_FIFOCFG_SIZE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 10783 | #define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10784 | #define USART_FIFOCFG_DMATX_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 10785 | #define USART_FIFOCFG_DMATX_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 10786 | #define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10787 | #define USART_FIFOCFG_DMARX_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 10788 | #define USART_FIFOCFG_DMARX_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 10789 | #define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10790 | #define USART_FIFOCFG_WAKETX_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 10791 | #define USART_FIFOCFG_WAKETX_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 10792 | #define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10793 | #define USART_FIFOCFG_WAKERX_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10794 | #define USART_FIFOCFG_WAKERX_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10795 | #define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10796 | #define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 10797 | #define USART_FIFOCFG_EMPTYTX_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10798 | #define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10799 | #define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 10800 | #define USART_FIFOCFG_EMPTYRX_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 10801 | #define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10802 | #define USART_FIFOCFG_POPDBG_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 10803 | #define USART_FIFOCFG_POPDBG_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 10804 | #define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10805 | |
| AnnaBridge | 163:e59c8e839560 | 10806 | /*! @name FIFOSTAT - FIFO status register. */ |
| AnnaBridge | 163:e59c8e839560 | 10807 | #define USART_FIFOSTAT_TXERR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10808 | #define USART_FIFOSTAT_TXERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10809 | #define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10810 | #define USART_FIFOSTAT_RXERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10811 | #define USART_FIFOSTAT_RXERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10812 | #define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10813 | #define USART_FIFOSTAT_PERINT_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10814 | #define USART_FIFOSTAT_PERINT_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10815 | #define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10816 | #define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 10817 | #define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 10818 | #define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10819 | #define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 10820 | #define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 10821 | #define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10822 | #define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 10823 | #define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 10824 | #define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10825 | #define USART_FIFOSTAT_RXFULL_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 10826 | #define USART_FIFOSTAT_RXFULL_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 10827 | #define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10828 | #define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) |
| AnnaBridge | 163:e59c8e839560 | 10829 | #define USART_FIFOSTAT_TXLVL_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 10830 | #define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10831 | #define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) |
| AnnaBridge | 163:e59c8e839560 | 10832 | #define USART_FIFOSTAT_RXLVL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10833 | #define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10834 | |
| AnnaBridge | 163:e59c8e839560 | 10835 | /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ |
| AnnaBridge | 163:e59c8e839560 | 10836 | #define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10837 | #define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10838 | #define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10839 | #define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10840 | #define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10841 | #define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10842 | #define USART_FIFOTRIG_TXLVL_MASK (0xF00U) |
| AnnaBridge | 163:e59c8e839560 | 10843 | #define USART_FIFOTRIG_TXLVL_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 10844 | #define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10845 | #define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) |
| AnnaBridge | 163:e59c8e839560 | 10846 | #define USART_FIFOTRIG_RXLVL_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10847 | #define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10848 | |
| AnnaBridge | 163:e59c8e839560 | 10849 | /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ |
| AnnaBridge | 163:e59c8e839560 | 10850 | #define USART_FIFOINTENSET_TXERR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10851 | #define USART_FIFOINTENSET_TXERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10852 | #define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10853 | #define USART_FIFOINTENSET_RXERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10854 | #define USART_FIFOINTENSET_RXERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10855 | #define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10856 | #define USART_FIFOINTENSET_TXLVL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 10857 | #define USART_FIFOINTENSET_TXLVL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10858 | #define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10859 | #define USART_FIFOINTENSET_RXLVL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10860 | #define USART_FIFOINTENSET_RXLVL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10861 | #define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10862 | |
| AnnaBridge | 163:e59c8e839560 | 10863 | /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ |
| AnnaBridge | 163:e59c8e839560 | 10864 | #define USART_FIFOINTENCLR_TXERR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10865 | #define USART_FIFOINTENCLR_TXERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10866 | #define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10867 | #define USART_FIFOINTENCLR_RXERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10868 | #define USART_FIFOINTENCLR_RXERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10869 | #define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10870 | #define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 10871 | #define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10872 | #define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10873 | #define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10874 | #define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10875 | #define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10876 | |
| AnnaBridge | 163:e59c8e839560 | 10877 | /*! @name FIFOINTSTAT - FIFO interrupt status register. */ |
| AnnaBridge | 163:e59c8e839560 | 10878 | #define USART_FIFOINTSTAT_TXERR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 10879 | #define USART_FIFOINTSTAT_TXERR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10880 | #define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10881 | #define USART_FIFOINTSTAT_RXERR_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 10882 | #define USART_FIFOINTSTAT_RXERR_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 10883 | #define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10884 | #define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 10885 | #define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 10886 | #define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10887 | #define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 10888 | #define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 10889 | #define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10890 | #define USART_FIFOINTSTAT_PERINT_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 10891 | #define USART_FIFOINTSTAT_PERINT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 10892 | #define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10893 | |
| AnnaBridge | 163:e59c8e839560 | 10894 | /*! @name FIFOWR - FIFO write data. */ |
| AnnaBridge | 163:e59c8e839560 | 10895 | #define USART_FIFOWR_TXDATA_MASK (0x1FFU) |
| AnnaBridge | 163:e59c8e839560 | 10896 | #define USART_FIFOWR_TXDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10897 | #define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10898 | |
| AnnaBridge | 163:e59c8e839560 | 10899 | /*! @name FIFORD - FIFO read data. */ |
| AnnaBridge | 163:e59c8e839560 | 10900 | #define USART_FIFORD_RXDATA_MASK (0x1FFU) |
| AnnaBridge | 163:e59c8e839560 | 10901 | #define USART_FIFORD_RXDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10902 | #define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10903 | #define USART_FIFORD_FRAMERR_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 10904 | #define USART_FIFORD_FRAMERR_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 10905 | #define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10906 | #define USART_FIFORD_PARITYERR_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 10907 | #define USART_FIFORD_PARITYERR_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 10908 | #define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10909 | #define USART_FIFORD_RXNOISE_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10910 | #define USART_FIFORD_RXNOISE_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10911 | #define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10912 | |
| AnnaBridge | 163:e59c8e839560 | 10913 | /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ |
| AnnaBridge | 163:e59c8e839560 | 10914 | #define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) |
| AnnaBridge | 163:e59c8e839560 | 10915 | #define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10916 | #define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10917 | #define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 10918 | #define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 10919 | #define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10920 | #define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 10921 | #define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 10922 | #define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10923 | #define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 10924 | #define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 10925 | #define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10926 | |
| AnnaBridge | 163:e59c8e839560 | 10927 | /*! @name ID - Peripheral identification register. */ |
| AnnaBridge | 163:e59c8e839560 | 10928 | #define USART_ID_APERTURE_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 10929 | #define USART_ID_APERTURE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 10930 | #define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10931 | #define USART_ID_MINOR_REV_MASK (0xF00U) |
| AnnaBridge | 163:e59c8e839560 | 10932 | #define USART_ID_MINOR_REV_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 10933 | #define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10934 | #define USART_ID_MAJOR_REV_MASK (0xF000U) |
| AnnaBridge | 163:e59c8e839560 | 10935 | #define USART_ID_MAJOR_REV_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 10936 | #define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10937 | #define USART_ID_ID_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 10938 | #define USART_ID_ID_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 10939 | #define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 10940 | |
| AnnaBridge | 163:e59c8e839560 | 10941 | |
| AnnaBridge | 163:e59c8e839560 | 10942 | /*! |
| AnnaBridge | 163:e59c8e839560 | 10943 | * @} |
| AnnaBridge | 163:e59c8e839560 | 10944 | */ /* end of group USART_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 10945 | |
| AnnaBridge | 163:e59c8e839560 | 10946 | |
| AnnaBridge | 163:e59c8e839560 | 10947 | /* USART - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 10948 | /** Peripheral USART0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 10949 | #define USART0_BASE (0x40086000u) |
| AnnaBridge | 163:e59c8e839560 | 10950 | /** Peripheral USART0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 10951 | #define USART0 ((USART_Type *)USART0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 10952 | /** Peripheral USART1 base address */ |
| AnnaBridge | 163:e59c8e839560 | 10953 | #define USART1_BASE (0x40087000u) |
| AnnaBridge | 163:e59c8e839560 | 10954 | /** Peripheral USART1 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 10955 | #define USART1 ((USART_Type *)USART1_BASE) |
| AnnaBridge | 163:e59c8e839560 | 10956 | /** Peripheral USART2 base address */ |
| AnnaBridge | 163:e59c8e839560 | 10957 | #define USART2_BASE (0x40088000u) |
| AnnaBridge | 163:e59c8e839560 | 10958 | /** Peripheral USART2 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 10959 | #define USART2 ((USART_Type *)USART2_BASE) |
| AnnaBridge | 163:e59c8e839560 | 10960 | /** Peripheral USART3 base address */ |
| AnnaBridge | 163:e59c8e839560 | 10961 | #define USART3_BASE (0x40089000u) |
| AnnaBridge | 163:e59c8e839560 | 10962 | /** Peripheral USART3 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 10963 | #define USART3 ((USART_Type *)USART3_BASE) |
| AnnaBridge | 163:e59c8e839560 | 10964 | /** Peripheral USART4 base address */ |
| AnnaBridge | 163:e59c8e839560 | 10965 | #define USART4_BASE (0x4008A000u) |
| AnnaBridge | 163:e59c8e839560 | 10966 | /** Peripheral USART4 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 10967 | #define USART4 ((USART_Type *)USART4_BASE) |
| AnnaBridge | 163:e59c8e839560 | 10968 | /** Peripheral USART5 base address */ |
| AnnaBridge | 163:e59c8e839560 | 10969 | #define USART5_BASE (0x40096000u) |
| AnnaBridge | 163:e59c8e839560 | 10970 | /** Peripheral USART5 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 10971 | #define USART5 ((USART_Type *)USART5_BASE) |
| AnnaBridge | 163:e59c8e839560 | 10972 | /** Peripheral USART6 base address */ |
| AnnaBridge | 163:e59c8e839560 | 10973 | #define USART6_BASE (0x40097000u) |
| AnnaBridge | 163:e59c8e839560 | 10974 | /** Peripheral USART6 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 10975 | #define USART6 ((USART_Type *)USART6_BASE) |
| AnnaBridge | 163:e59c8e839560 | 10976 | /** Peripheral USART7 base address */ |
| AnnaBridge | 163:e59c8e839560 | 10977 | #define USART7_BASE (0x40098000u) |
| AnnaBridge | 163:e59c8e839560 | 10978 | /** Peripheral USART7 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 10979 | #define USART7 ((USART_Type *)USART7_BASE) |
| AnnaBridge | 163:e59c8e839560 | 10980 | /** Peripheral USART8 base address */ |
| AnnaBridge | 163:e59c8e839560 | 10981 | #define USART8_BASE (0x40099000u) |
| AnnaBridge | 163:e59c8e839560 | 10982 | /** Peripheral USART8 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 10983 | #define USART8 ((USART_Type *)USART8_BASE) |
| AnnaBridge | 163:e59c8e839560 | 10984 | /** Peripheral USART9 base address */ |
| AnnaBridge | 163:e59c8e839560 | 10985 | #define USART9_BASE (0x4009A000u) |
| AnnaBridge | 163:e59c8e839560 | 10986 | /** Peripheral USART9 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 10987 | #define USART9 ((USART_Type *)USART9_BASE) |
| AnnaBridge | 163:e59c8e839560 | 10988 | /** Array initializer of USART peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 10989 | #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE } |
| AnnaBridge | 163:e59c8e839560 | 10990 | /** Array initializer of USART peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 10991 | #define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 } |
| AnnaBridge | 163:e59c8e839560 | 10992 | /** Interrupt vectors for the USART peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 10993 | #define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 10994 | |
| AnnaBridge | 163:e59c8e839560 | 10995 | /*! |
| AnnaBridge | 163:e59c8e839560 | 10996 | * @} |
| AnnaBridge | 163:e59c8e839560 | 10997 | */ /* end of group USART_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 10998 | |
| AnnaBridge | 163:e59c8e839560 | 10999 | |
| AnnaBridge | 163:e59c8e839560 | 11000 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 11001 | -- USB Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 11002 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 11003 | |
| AnnaBridge | 163:e59c8e839560 | 11004 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11005 | * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 11006 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 11007 | */ |
| AnnaBridge | 163:e59c8e839560 | 11008 | |
| AnnaBridge | 163:e59c8e839560 | 11009 | /** USB - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 11010 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 11011 | __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 11012 | __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 11013 | __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 11014 | __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 11015 | __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 11016 | __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 11017 | __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 11018 | __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 11019 | __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 11020 | __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 11021 | __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 11022 | uint8_t RESERVED_0[8]; |
| AnnaBridge | 163:e59c8e839560 | 11023 | __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ |
| AnnaBridge | 163:e59c8e839560 | 11024 | } USB_Type; |
| AnnaBridge | 163:e59c8e839560 | 11025 | |
| AnnaBridge | 163:e59c8e839560 | 11026 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 11027 | -- USB Register Masks |
| AnnaBridge | 163:e59c8e839560 | 11028 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 11029 | |
| AnnaBridge | 163:e59c8e839560 | 11030 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11031 | * @addtogroup USB_Register_Masks USB Register Masks |
| AnnaBridge | 163:e59c8e839560 | 11032 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 11033 | */ |
| AnnaBridge | 163:e59c8e839560 | 11034 | |
| AnnaBridge | 163:e59c8e839560 | 11035 | /*! @name DEVCMDSTAT - USB Device Command/Status register */ |
| AnnaBridge | 163:e59c8e839560 | 11036 | #define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) |
| AnnaBridge | 163:e59c8e839560 | 11037 | #define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11038 | #define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11039 | #define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 11040 | #define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 11041 | #define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11042 | #define USB_DEVCMDSTAT_SETUP_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 11043 | #define USB_DEVCMDSTAT_SETUP_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11044 | #define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11045 | #define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 11046 | #define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 11047 | #define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11048 | #define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 11049 | #define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 11050 | #define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11051 | #define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 11052 | #define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 11053 | #define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11054 | #define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 11055 | #define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 11056 | #define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11057 | #define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 11058 | #define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 11059 | #define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11060 | #define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 11061 | #define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 11062 | #define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11063 | #define USB_DEVCMDSTAT_DCON_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 11064 | #define USB_DEVCMDSTAT_DCON_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11065 | #define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11066 | #define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 11067 | #define USB_DEVCMDSTAT_DSUS_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 11068 | #define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11069 | #define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 11070 | #define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 11071 | #define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11072 | #define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 11073 | #define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 11074 | #define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11075 | #define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 11076 | #define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 11077 | #define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11078 | #define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 11079 | #define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 11080 | #define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11081 | #define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 11082 | #define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 11083 | #define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11084 | #define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 11085 | #define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 11086 | #define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11087 | |
| AnnaBridge | 163:e59c8e839560 | 11088 | /*! @name INFO - USB Info register */ |
| AnnaBridge | 163:e59c8e839560 | 11089 | #define USB_INFO_FRAME_NR_MASK (0x7FFU) |
| AnnaBridge | 163:e59c8e839560 | 11090 | #define USB_INFO_FRAME_NR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11091 | #define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11092 | #define USB_INFO_ERR_CODE_MASK (0x7800U) |
| AnnaBridge | 163:e59c8e839560 | 11093 | #define USB_INFO_ERR_CODE_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 11094 | #define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11095 | #define USB_INFO_MINREV_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 11096 | #define USB_INFO_MINREV_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11097 | #define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11098 | #define USB_INFO_MAJREV_MASK (0xFF000000U) |
| AnnaBridge | 163:e59c8e839560 | 11099 | #define USB_INFO_MAJREV_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 11100 | #define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11101 | |
| AnnaBridge | 163:e59c8e839560 | 11102 | /*! @name EPLISTSTART - USB EP Command/Status List start address */ |
| AnnaBridge | 163:e59c8e839560 | 11103 | #define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) |
| AnnaBridge | 163:e59c8e839560 | 11104 | #define USB_EPLISTSTART_EP_LIST_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11105 | #define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11106 | |
| AnnaBridge | 163:e59c8e839560 | 11107 | /*! @name DATABUFSTART - USB Data buffer start address */ |
| AnnaBridge | 163:e59c8e839560 | 11108 | #define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) |
| AnnaBridge | 163:e59c8e839560 | 11109 | #define USB_DATABUFSTART_DA_BUF_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 11110 | #define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11111 | |
| AnnaBridge | 163:e59c8e839560 | 11112 | /*! @name LPM - USB Link Power Management register */ |
| AnnaBridge | 163:e59c8e839560 | 11113 | #define USB_LPM_HIRD_HW_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 11114 | #define USB_LPM_HIRD_HW_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11115 | #define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11116 | #define USB_LPM_HIRD_SW_MASK (0xF0U) |
| AnnaBridge | 163:e59c8e839560 | 11117 | #define USB_LPM_HIRD_SW_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11118 | #define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11119 | #define USB_LPM_DATA_PENDING_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 11120 | #define USB_LPM_DATA_PENDING_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11121 | #define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11122 | |
| AnnaBridge | 163:e59c8e839560 | 11123 | /*! @name EPSKIP - USB Endpoint skip */ |
| AnnaBridge | 163:e59c8e839560 | 11124 | #define USB_EPSKIP_SKIP_MASK (0x3FFU) |
| AnnaBridge | 163:e59c8e839560 | 11125 | #define USB_EPSKIP_SKIP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11126 | #define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11127 | |
| AnnaBridge | 163:e59c8e839560 | 11128 | /*! @name EPINUSE - USB Endpoint Buffer in use */ |
| AnnaBridge | 163:e59c8e839560 | 11129 | #define USB_EPINUSE_BUF_MASK (0x3FCU) |
| AnnaBridge | 163:e59c8e839560 | 11130 | #define USB_EPINUSE_BUF_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11131 | #define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11132 | |
| AnnaBridge | 163:e59c8e839560 | 11133 | /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ |
| AnnaBridge | 163:e59c8e839560 | 11134 | #define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) |
| AnnaBridge | 163:e59c8e839560 | 11135 | #define USB_EPBUFCFG_BUF_SB_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11136 | #define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11137 | |
| AnnaBridge | 163:e59c8e839560 | 11138 | /*! @name INTSTAT - USB interrupt status register */ |
| AnnaBridge | 163:e59c8e839560 | 11139 | #define USB_INTSTAT_EP0OUT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 11140 | #define USB_INTSTAT_EP0OUT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11141 | #define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11142 | #define USB_INTSTAT_EP0IN_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 11143 | #define USB_INTSTAT_EP0IN_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 11144 | #define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11145 | #define USB_INTSTAT_EP1OUT_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 11146 | #define USB_INTSTAT_EP1OUT_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11147 | #define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11148 | #define USB_INTSTAT_EP1IN_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 11149 | #define USB_INTSTAT_EP1IN_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 11150 | #define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11151 | #define USB_INTSTAT_EP2OUT_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 11152 | #define USB_INTSTAT_EP2OUT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11153 | #define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11154 | #define USB_INTSTAT_EP2IN_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 11155 | #define USB_INTSTAT_EP2IN_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 11156 | #define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11157 | #define USB_INTSTAT_EP3OUT_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 11158 | #define USB_INTSTAT_EP3OUT_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 11159 | #define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11160 | #define USB_INTSTAT_EP3IN_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 11161 | #define USB_INTSTAT_EP3IN_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 11162 | #define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11163 | #define USB_INTSTAT_EP4OUT_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 11164 | #define USB_INTSTAT_EP4OUT_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11165 | #define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11166 | #define USB_INTSTAT_EP4IN_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 11167 | #define USB_INTSTAT_EP4IN_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 11168 | #define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11169 | #define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 11170 | #define USB_INTSTAT_FRAME_INT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 11171 | #define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11172 | #define USB_INTSTAT_DEV_INT_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 11173 | #define USB_INTSTAT_DEV_INT_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 11174 | #define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11175 | |
| AnnaBridge | 163:e59c8e839560 | 11176 | /*! @name INTEN - USB interrupt enable register */ |
| AnnaBridge | 163:e59c8e839560 | 11177 | #define USB_INTEN_EP_INT_EN_MASK (0x3FFU) |
| AnnaBridge | 163:e59c8e839560 | 11178 | #define USB_INTEN_EP_INT_EN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11179 | #define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11180 | #define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 11181 | #define USB_INTEN_FRAME_INT_EN_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 11182 | #define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11183 | #define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 11184 | #define USB_INTEN_DEV_INT_EN_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 11185 | #define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11186 | |
| AnnaBridge | 163:e59c8e839560 | 11187 | /*! @name INTSETSTAT - USB set interrupt status register */ |
| AnnaBridge | 163:e59c8e839560 | 11188 | #define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) |
| AnnaBridge | 163:e59c8e839560 | 11189 | #define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11190 | #define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11191 | #define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 11192 | #define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 11193 | #define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11194 | #define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 11195 | #define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 11196 | #define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11197 | |
| AnnaBridge | 163:e59c8e839560 | 11198 | /*! @name EPTOGGLE - USB Endpoint toggle register */ |
| AnnaBridge | 163:e59c8e839560 | 11199 | #define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) |
| AnnaBridge | 163:e59c8e839560 | 11200 | #define USB_EPTOGGLE_TOGGLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11201 | #define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11202 | |
| AnnaBridge | 163:e59c8e839560 | 11203 | |
| AnnaBridge | 163:e59c8e839560 | 11204 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11205 | * @} |
| AnnaBridge | 163:e59c8e839560 | 11206 | */ /* end of group USB_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 11207 | |
| AnnaBridge | 163:e59c8e839560 | 11208 | |
| AnnaBridge | 163:e59c8e839560 | 11209 | /* USB - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 11210 | /** Peripheral USB0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 11211 | #define USB0_BASE (0x40084000u) |
| AnnaBridge | 163:e59c8e839560 | 11212 | /** Peripheral USB0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 11213 | #define USB0 ((USB_Type *)USB0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 11214 | /** Array initializer of USB peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 11215 | #define USB_BASE_ADDRS { USB0_BASE } |
| AnnaBridge | 163:e59c8e839560 | 11216 | /** Array initializer of USB peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 11217 | #define USB_BASE_PTRS { USB0 } |
| AnnaBridge | 163:e59c8e839560 | 11218 | /** Interrupt vectors for the USB peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 11219 | #define USB_IRQS { USB0_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 11220 | #define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 11221 | |
| AnnaBridge | 163:e59c8e839560 | 11222 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11223 | * @} |
| AnnaBridge | 163:e59c8e839560 | 11224 | */ /* end of group USB_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 11225 | |
| AnnaBridge | 163:e59c8e839560 | 11226 | |
| AnnaBridge | 163:e59c8e839560 | 11227 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 11228 | -- USBFSH Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 11229 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 11230 | |
| AnnaBridge | 163:e59c8e839560 | 11231 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11232 | * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 11233 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 11234 | */ |
| AnnaBridge | 163:e59c8e839560 | 11235 | |
| AnnaBridge | 163:e59c8e839560 | 11236 | /** USBFSH - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 11237 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 11238 | __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 11239 | __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 11240 | __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 11241 | __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 11242 | __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 11243 | __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 11244 | __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 11245 | __IO uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 11246 | __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 11247 | __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 11248 | __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 11249 | __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 11250 | __IO uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 11251 | __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ |
| AnnaBridge | 163:e59c8e839560 | 11252 | __IO uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ |
| AnnaBridge | 163:e59c8e839560 | 11253 | __IO uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ |
| AnnaBridge | 163:e59c8e839560 | 11254 | __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 11255 | __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ |
| AnnaBridge | 163:e59c8e839560 | 11256 | __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ |
| AnnaBridge | 163:e59c8e839560 | 11257 | __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */ |
| AnnaBridge | 163:e59c8e839560 | 11258 | __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */ |
| AnnaBridge | 163:e59c8e839560 | 11259 | __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */ |
| AnnaBridge | 163:e59c8e839560 | 11260 | uint8_t RESERVED_0[4]; |
| AnnaBridge | 163:e59c8e839560 | 11261 | __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */ |
| AnnaBridge | 163:e59c8e839560 | 11262 | } USBFSH_Type; |
| AnnaBridge | 163:e59c8e839560 | 11263 | |
| AnnaBridge | 163:e59c8e839560 | 11264 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 11265 | -- USBFSH Register Masks |
| AnnaBridge | 163:e59c8e839560 | 11266 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 11267 | |
| AnnaBridge | 163:e59c8e839560 | 11268 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11269 | * @addtogroup USBFSH_Register_Masks USBFSH Register Masks |
| AnnaBridge | 163:e59c8e839560 | 11270 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 11271 | */ |
| AnnaBridge | 163:e59c8e839560 | 11272 | |
| AnnaBridge | 163:e59c8e839560 | 11273 | /*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ |
| AnnaBridge | 163:e59c8e839560 | 11274 | #define USBFSH_HCREVISION_REV_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 11275 | #define USBFSH_HCREVISION_REV_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11276 | #define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11277 | |
| AnnaBridge | 163:e59c8e839560 | 11278 | /*! @name HCCONTROL - Defines the operating modes of the HC */ |
| AnnaBridge | 163:e59c8e839560 | 11279 | #define USBFSH_HCCONTROL_CBSR_MASK (0x3U) |
| AnnaBridge | 163:e59c8e839560 | 11280 | #define USBFSH_HCCONTROL_CBSR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11281 | #define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11282 | #define USBFSH_HCCONTROL_PLE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 11283 | #define USBFSH_HCCONTROL_PLE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11284 | #define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11285 | #define USBFSH_HCCONTROL_IE_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 11286 | #define USBFSH_HCCONTROL_IE_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 11287 | #define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11288 | #define USBFSH_HCCONTROL_CLE_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 11289 | #define USBFSH_HCCONTROL_CLE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11290 | #define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11291 | #define USBFSH_HCCONTROL_BLE_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 11292 | #define USBFSH_HCCONTROL_BLE_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 11293 | #define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11294 | #define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) |
| AnnaBridge | 163:e59c8e839560 | 11295 | #define USBFSH_HCCONTROL_HCFS_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 11296 | #define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11297 | #define USBFSH_HCCONTROL_IR_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 11298 | #define USBFSH_HCCONTROL_IR_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11299 | #define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11300 | #define USBFSH_HCCONTROL_RWC_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 11301 | #define USBFSH_HCCONTROL_RWC_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 11302 | #define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11303 | #define USBFSH_HCCONTROL_RWE_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 11304 | #define USBFSH_HCCONTROL_RWE_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 11305 | #define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11306 | |
| AnnaBridge | 163:e59c8e839560 | 11307 | /*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ |
| AnnaBridge | 163:e59c8e839560 | 11308 | #define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 11309 | #define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11310 | #define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11311 | #define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 11312 | #define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 11313 | #define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11314 | #define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 11315 | #define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11316 | #define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11317 | #define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 11318 | #define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 11319 | #define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11320 | #define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) |
| AnnaBridge | 163:e59c8e839560 | 11321 | #define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 11322 | #define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11323 | |
| AnnaBridge | 163:e59c8e839560 | 11324 | /*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ |
| AnnaBridge | 163:e59c8e839560 | 11325 | #define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 11326 | #define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11327 | #define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11328 | #define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 11329 | #define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 11330 | #define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11331 | #define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 11332 | #define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11333 | #define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11334 | #define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 11335 | #define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 11336 | #define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11337 | #define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 11338 | #define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11339 | #define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11340 | #define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 11341 | #define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 11342 | #define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11343 | #define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 11344 | #define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 11345 | #define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11346 | #define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) |
| AnnaBridge | 163:e59c8e839560 | 11347 | #define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 11348 | #define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11349 | |
| AnnaBridge | 163:e59c8e839560 | 11350 | /*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 11351 | #define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 11352 | #define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11353 | #define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11354 | #define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 11355 | #define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 11356 | #define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11357 | #define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 11358 | #define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11359 | #define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11360 | #define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 11361 | #define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 11362 | #define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11363 | #define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 11364 | #define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11365 | #define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11366 | #define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 11367 | #define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 11368 | #define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11369 | #define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 11370 | #define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 11371 | #define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11372 | #define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 11373 | #define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 11374 | #define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11375 | #define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 11376 | #define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 11377 | #define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11378 | |
| AnnaBridge | 163:e59c8e839560 | 11379 | /*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ |
| AnnaBridge | 163:e59c8e839560 | 11380 | #define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 11381 | #define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11382 | #define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11383 | #define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 11384 | #define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 11385 | #define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11386 | #define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 11387 | #define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11388 | #define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11389 | #define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 11390 | #define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 11391 | #define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11392 | #define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 11393 | #define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11394 | #define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11395 | #define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 11396 | #define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 11397 | #define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11398 | #define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 11399 | #define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 11400 | #define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11401 | #define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 11402 | #define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 11403 | #define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11404 | #define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 11405 | #define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 11406 | #define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11407 | |
| AnnaBridge | 163:e59c8e839560 | 11408 | /*! @name HCHCCA - Contains the physical address of the host controller communication area */ |
| AnnaBridge | 163:e59c8e839560 | 11409 | #define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) |
| AnnaBridge | 163:e59c8e839560 | 11410 | #define USBFSH_HCHCCA_HCCA_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11411 | #define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11412 | |
| AnnaBridge | 163:e59c8e839560 | 11413 | /*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ |
| AnnaBridge | 163:e59c8e839560 | 11414 | #define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 11415 | #define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11416 | #define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11417 | |
| AnnaBridge | 163:e59c8e839560 | 11418 | /*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ |
| AnnaBridge | 163:e59c8e839560 | 11419 | #define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 11420 | #define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11421 | #define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11422 | |
| AnnaBridge | 163:e59c8e839560 | 11423 | /*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ |
| AnnaBridge | 163:e59c8e839560 | 11424 | #define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 11425 | #define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11426 | #define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11427 | |
| AnnaBridge | 163:e59c8e839560 | 11428 | /*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ |
| AnnaBridge | 163:e59c8e839560 | 11429 | #define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 11430 | #define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11431 | #define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11432 | |
| AnnaBridge | 163:e59c8e839560 | 11433 | /*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ |
| AnnaBridge | 163:e59c8e839560 | 11434 | #define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 11435 | #define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11436 | #define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11437 | |
| AnnaBridge | 163:e59c8e839560 | 11438 | /*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ |
| AnnaBridge | 163:e59c8e839560 | 11439 | #define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) |
| AnnaBridge | 163:e59c8e839560 | 11440 | #define USBFSH_HCDONEHEAD_DH_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11441 | #define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11442 | |
| AnnaBridge | 163:e59c8e839560 | 11443 | /*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ |
| AnnaBridge | 163:e59c8e839560 | 11444 | #define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) |
| AnnaBridge | 163:e59c8e839560 | 11445 | #define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11446 | #define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11447 | #define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 11448 | #define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11449 | #define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11450 | #define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 11451 | #define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 11452 | #define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11453 | |
| AnnaBridge | 163:e59c8e839560 | 11454 | /*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ |
| AnnaBridge | 163:e59c8e839560 | 11455 | #define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) |
| AnnaBridge | 163:e59c8e839560 | 11456 | #define USBFSH_HCFMREMAINING_FR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11457 | #define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11458 | #define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 11459 | #define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 11460 | #define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11461 | |
| AnnaBridge | 163:e59c8e839560 | 11462 | /*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ |
| AnnaBridge | 163:e59c8e839560 | 11463 | #define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 11464 | #define USBFSH_HCFMNUMBER_FN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11465 | #define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11466 | |
| AnnaBridge | 163:e59c8e839560 | 11467 | /*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ |
| AnnaBridge | 163:e59c8e839560 | 11468 | #define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) |
| AnnaBridge | 163:e59c8e839560 | 11469 | #define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11470 | #define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11471 | |
| AnnaBridge | 163:e59c8e839560 | 11472 | /*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ |
| AnnaBridge | 163:e59c8e839560 | 11473 | #define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) |
| AnnaBridge | 163:e59c8e839560 | 11474 | #define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11475 | #define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11476 | |
| AnnaBridge | 163:e59c8e839560 | 11477 | /*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ |
| AnnaBridge | 163:e59c8e839560 | 11478 | #define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 11479 | #define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11480 | #define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11481 | #define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 11482 | #define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11483 | #define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11484 | #define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 11485 | #define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 11486 | #define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11487 | #define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 11488 | #define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 11489 | #define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11490 | #define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 11491 | #define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 11492 | #define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11493 | #define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 11494 | #define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 11495 | #define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11496 | #define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) |
| AnnaBridge | 163:e59c8e839560 | 11497 | #define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 11498 | #define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11499 | |
| AnnaBridge | 163:e59c8e839560 | 11500 | /*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ |
| AnnaBridge | 163:e59c8e839560 | 11501 | #define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 11502 | #define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11503 | #define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11504 | #define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 11505 | #define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11506 | #define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11507 | |
| AnnaBridge | 163:e59c8e839560 | 11508 | /*! @name HCRHSTATUS - This register is divided into two parts */ |
| AnnaBridge | 163:e59c8e839560 | 11509 | #define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 11510 | #define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11511 | #define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11512 | #define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 11513 | #define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 11514 | #define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11515 | #define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 11516 | #define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 11517 | #define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11518 | #define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 11519 | #define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11520 | #define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11521 | #define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 11522 | #define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 11523 | #define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11524 | #define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 11525 | #define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 11526 | #define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11527 | |
| AnnaBridge | 163:e59c8e839560 | 11528 | /*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ |
| AnnaBridge | 163:e59c8e839560 | 11529 | #define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 11530 | #define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11531 | #define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11532 | #define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 11533 | #define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 11534 | #define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11535 | #define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 11536 | #define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11537 | #define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11538 | #define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 11539 | #define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 11540 | #define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11541 | #define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 11542 | #define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11543 | #define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11544 | #define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 11545 | #define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11546 | #define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11547 | #define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 11548 | #define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 11549 | #define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11550 | #define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 11551 | #define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11552 | #define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11553 | #define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 11554 | #define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 11555 | #define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11556 | #define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 11557 | #define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 11558 | #define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11559 | #define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 11560 | #define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 11561 | #define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11562 | #define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 11563 | #define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 11564 | #define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11565 | |
| AnnaBridge | 163:e59c8e839560 | 11566 | /*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ |
| AnnaBridge | 163:e59c8e839560 | 11567 | #define USBFSH_PORTMODE_ID_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 11568 | #define USBFSH_PORTMODE_ID_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11569 | #define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11570 | #define USBFSH_PORTMODE_ID_EN_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 11571 | #define USBFSH_PORTMODE_ID_EN_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11572 | #define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11573 | #define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 11574 | #define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11575 | #define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11576 | |
| AnnaBridge | 163:e59c8e839560 | 11577 | |
| AnnaBridge | 163:e59c8e839560 | 11578 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11579 | * @} |
| AnnaBridge | 163:e59c8e839560 | 11580 | */ /* end of group USBFSH_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 11581 | |
| AnnaBridge | 163:e59c8e839560 | 11582 | |
| AnnaBridge | 163:e59c8e839560 | 11583 | /* USBFSH - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 11584 | /** Peripheral USBFSH base address */ |
| AnnaBridge | 163:e59c8e839560 | 11585 | #define USBFSH_BASE (0x400A2000u) |
| AnnaBridge | 163:e59c8e839560 | 11586 | /** Peripheral USBFSH base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 11587 | #define USBFSH ((USBFSH_Type *)USBFSH_BASE) |
| AnnaBridge | 163:e59c8e839560 | 11588 | /** Array initializer of USBFSH peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 11589 | #define USBFSH_BASE_ADDRS { USBFSH_BASE } |
| AnnaBridge | 163:e59c8e839560 | 11590 | /** Array initializer of USBFSH peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 11591 | #define USBFSH_BASE_PTRS { USBFSH } |
| AnnaBridge | 163:e59c8e839560 | 11592 | /** Interrupt vectors for the USBFSH peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 11593 | #define USBFSH_IRQS { USB0_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 11594 | #define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 11595 | |
| AnnaBridge | 163:e59c8e839560 | 11596 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11597 | * @} |
| AnnaBridge | 163:e59c8e839560 | 11598 | */ /* end of group USBFSH_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 11599 | |
| AnnaBridge | 163:e59c8e839560 | 11600 | |
| AnnaBridge | 163:e59c8e839560 | 11601 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 11602 | -- USBHSD Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 11603 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 11604 | |
| AnnaBridge | 163:e59c8e839560 | 11605 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11606 | * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 11607 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 11608 | */ |
| AnnaBridge | 163:e59c8e839560 | 11609 | |
| AnnaBridge | 163:e59c8e839560 | 11610 | /** USBHSD - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 11611 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 11612 | __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 11613 | __I uint32_t INFO; /**< USB Info register, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 11614 | __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 11615 | __I uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 11616 | __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 11617 | __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 11618 | __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 11619 | __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 11620 | __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 11621 | __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 11622 | __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 11623 | uint8_t RESERVED_0[8]; |
| AnnaBridge | 163:e59c8e839560 | 11624 | __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ |
| AnnaBridge | 163:e59c8e839560 | 11625 | uint8_t RESERVED_1[4]; |
| AnnaBridge | 163:e59c8e839560 | 11626 | __IO uint32_t ULPIDEBUG; /**< UTMI/ULPI debug register, offset: 0x3C */ |
| AnnaBridge | 163:e59c8e839560 | 11627 | } USBHSD_Type; |
| AnnaBridge | 163:e59c8e839560 | 11628 | |
| AnnaBridge | 163:e59c8e839560 | 11629 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 11630 | -- USBHSD Register Masks |
| AnnaBridge | 163:e59c8e839560 | 11631 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 11632 | |
| AnnaBridge | 163:e59c8e839560 | 11633 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11634 | * @addtogroup USBHSD_Register_Masks USBHSD Register Masks |
| AnnaBridge | 163:e59c8e839560 | 11635 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 11636 | */ |
| AnnaBridge | 163:e59c8e839560 | 11637 | |
| AnnaBridge | 163:e59c8e839560 | 11638 | /*! @name DEVCMDSTAT - USB Device Command/Status register */ |
| AnnaBridge | 163:e59c8e839560 | 11639 | #define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) |
| AnnaBridge | 163:e59c8e839560 | 11640 | #define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11641 | #define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11642 | #define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 11643 | #define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 11644 | #define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11645 | #define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 11646 | #define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11647 | #define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11648 | #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 11649 | #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 11650 | #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11651 | #define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 11652 | #define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 11653 | #define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11654 | #define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 11655 | #define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 11656 | #define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11657 | #define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 11658 | #define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 11659 | #define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11660 | #define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) |
| AnnaBridge | 163:e59c8e839560 | 11661 | #define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) |
| AnnaBridge | 163:e59c8e839560 | 11662 | #define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11663 | #define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) |
| AnnaBridge | 163:e59c8e839560 | 11664 | #define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 11665 | #define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11666 | #define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) |
| AnnaBridge | 163:e59c8e839560 | 11667 | #define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) |
| AnnaBridge | 163:e59c8e839560 | 11668 | #define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11669 | #define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 11670 | #define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11671 | #define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11672 | #define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 11673 | #define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 11674 | #define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11675 | #define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 11676 | #define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 11677 | #define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11678 | #define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) |
| AnnaBridge | 163:e59c8e839560 | 11679 | #define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 11680 | #define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11681 | #define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) |
| AnnaBridge | 163:e59c8e839560 | 11682 | #define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 11683 | #define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11684 | #define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 11685 | #define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 11686 | #define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11687 | #define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 11688 | #define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 11689 | #define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11690 | #define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) |
| AnnaBridge | 163:e59c8e839560 | 11691 | #define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) |
| AnnaBridge | 163:e59c8e839560 | 11692 | #define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11693 | #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 11694 | #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 11695 | #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11696 | #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) |
| AnnaBridge | 163:e59c8e839560 | 11697 | #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) |
| AnnaBridge | 163:e59c8e839560 | 11698 | #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11699 | |
| AnnaBridge | 163:e59c8e839560 | 11700 | /*! @name INFO - USB Info register */ |
| AnnaBridge | 163:e59c8e839560 | 11701 | #define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) |
| AnnaBridge | 163:e59c8e839560 | 11702 | #define USBHSD_INFO_FRAME_NR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11703 | #define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11704 | #define USBHSD_INFO_ERR_CODE_MASK (0x7800U) |
| AnnaBridge | 163:e59c8e839560 | 11705 | #define USBHSD_INFO_ERR_CODE_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 11706 | #define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11707 | #define USBHSD_INFO_Minrev_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 11708 | #define USBHSD_INFO_Minrev_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11709 | #define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11710 | #define USBHSD_INFO_Majrev_MASK (0xFF000000U) |
| AnnaBridge | 163:e59c8e839560 | 11711 | #define USBHSD_INFO_Majrev_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 11712 | #define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11713 | |
| AnnaBridge | 163:e59c8e839560 | 11714 | /*! @name EPLISTSTART - USB EP Command/Status List start address */ |
| AnnaBridge | 163:e59c8e839560 | 11715 | #define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) |
| AnnaBridge | 163:e59c8e839560 | 11716 | #define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11717 | #define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11718 | #define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) |
| AnnaBridge | 163:e59c8e839560 | 11719 | #define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 11720 | #define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11721 | |
| AnnaBridge | 163:e59c8e839560 | 11722 | /*! @name DATABUFSTART - USB Data buffer start address */ |
| AnnaBridge | 163:e59c8e839560 | 11723 | #define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 11724 | #define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11725 | #define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11726 | |
| AnnaBridge | 163:e59c8e839560 | 11727 | /*! @name LPM - USB Link Power Management register */ |
| AnnaBridge | 163:e59c8e839560 | 11728 | #define USBHSD_LPM_HIRD_HW_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 11729 | #define USBHSD_LPM_HIRD_HW_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11730 | #define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11731 | #define USBHSD_LPM_HIRD_SW_MASK (0xF0U) |
| AnnaBridge | 163:e59c8e839560 | 11732 | #define USBHSD_LPM_HIRD_SW_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11733 | #define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11734 | #define USBHSD_LPM_DATA_PENDING_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 11735 | #define USBHSD_LPM_DATA_PENDING_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11736 | #define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11737 | |
| AnnaBridge | 163:e59c8e839560 | 11738 | /*! @name EPSKIP - USB Endpoint skip */ |
| AnnaBridge | 163:e59c8e839560 | 11739 | #define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) |
| AnnaBridge | 163:e59c8e839560 | 11740 | #define USBHSD_EPSKIP_SKIP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11741 | #define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11742 | |
| AnnaBridge | 163:e59c8e839560 | 11743 | /*! @name EPINUSE - USB Endpoint Buffer in use */ |
| AnnaBridge | 163:e59c8e839560 | 11744 | #define USBHSD_EPINUSE_BUF_MASK (0xFFCU) |
| AnnaBridge | 163:e59c8e839560 | 11745 | #define USBHSD_EPINUSE_BUF_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11746 | #define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11747 | |
| AnnaBridge | 163:e59c8e839560 | 11748 | /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ |
| AnnaBridge | 163:e59c8e839560 | 11749 | #define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) |
| AnnaBridge | 163:e59c8e839560 | 11750 | #define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11751 | #define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11752 | |
| AnnaBridge | 163:e59c8e839560 | 11753 | /*! @name INTSTAT - USB interrupt status register */ |
| AnnaBridge | 163:e59c8e839560 | 11754 | #define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 11755 | #define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11756 | #define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11757 | #define USBHSD_INTSTAT_EP0IN_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 11758 | #define USBHSD_INTSTAT_EP0IN_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 11759 | #define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11760 | #define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 11761 | #define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11762 | #define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11763 | #define USBHSD_INTSTAT_EP1IN_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 11764 | #define USBHSD_INTSTAT_EP1IN_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 11765 | #define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11766 | #define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 11767 | #define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11768 | #define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11769 | #define USBHSD_INTSTAT_EP2IN_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 11770 | #define USBHSD_INTSTAT_EP2IN_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 11771 | #define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11772 | #define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 11773 | #define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 11774 | #define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11775 | #define USBHSD_INTSTAT_EP3IN_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 11776 | #define USBHSD_INTSTAT_EP3IN_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 11777 | #define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11778 | #define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 11779 | #define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11780 | #define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11781 | #define USBHSD_INTSTAT_EP4IN_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 11782 | #define USBHSD_INTSTAT_EP4IN_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 11783 | #define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11784 | #define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 11785 | #define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 11786 | #define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11787 | #define USBHSD_INTSTAT_EP5IN_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 11788 | #define USBHSD_INTSTAT_EP5IN_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 11789 | #define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11790 | #define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 11791 | #define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 11792 | #define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11793 | #define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 11794 | #define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 11795 | #define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11796 | |
| AnnaBridge | 163:e59c8e839560 | 11797 | /*! @name INTEN - USB interrupt enable register */ |
| AnnaBridge | 163:e59c8e839560 | 11798 | #define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) |
| AnnaBridge | 163:e59c8e839560 | 11799 | #define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11800 | #define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11801 | #define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 11802 | #define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 11803 | #define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11804 | #define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 11805 | #define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 11806 | #define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11807 | |
| AnnaBridge | 163:e59c8e839560 | 11808 | /*! @name INTSETSTAT - USB set interrupt status register */ |
| AnnaBridge | 163:e59c8e839560 | 11809 | #define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) |
| AnnaBridge | 163:e59c8e839560 | 11810 | #define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11811 | #define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11812 | #define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) |
| AnnaBridge | 163:e59c8e839560 | 11813 | #define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) |
| AnnaBridge | 163:e59c8e839560 | 11814 | #define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11815 | #define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 11816 | #define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 11817 | #define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11818 | |
| AnnaBridge | 163:e59c8e839560 | 11819 | /*! @name EPTOGGLE - USB Endpoint toggle register */ |
| AnnaBridge | 163:e59c8e839560 | 11820 | #define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 11821 | #define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11822 | #define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11823 | |
| AnnaBridge | 163:e59c8e839560 | 11824 | /*! @name ULPIDEBUG - UTMI/ULPI debug register */ |
| AnnaBridge | 163:e59c8e839560 | 11825 | #define USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 11826 | #define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11827 | #define USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11828 | #define USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 11829 | #define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11830 | #define USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11831 | #define USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 11832 | #define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11833 | #define USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11834 | #define USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 11835 | #define USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 11836 | #define USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11837 | #define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 11838 | #define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 11839 | #define USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11840 | #define USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 11841 | #define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 11842 | #define USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11843 | |
| AnnaBridge | 163:e59c8e839560 | 11844 | |
| AnnaBridge | 163:e59c8e839560 | 11845 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11846 | * @} |
| AnnaBridge | 163:e59c8e839560 | 11847 | */ /* end of group USBHSD_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 11848 | |
| AnnaBridge | 163:e59c8e839560 | 11849 | |
| AnnaBridge | 163:e59c8e839560 | 11850 | /* USBHSD - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 11851 | /** Peripheral USBHSD base address */ |
| AnnaBridge | 163:e59c8e839560 | 11852 | #define USBHSD_BASE (0x40094000u) |
| AnnaBridge | 163:e59c8e839560 | 11853 | /** Peripheral USBHSD base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 11854 | #define USBHSD ((USBHSD_Type *)USBHSD_BASE) |
| AnnaBridge | 163:e59c8e839560 | 11855 | /** Array initializer of USBHSD peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 11856 | #define USBHSD_BASE_ADDRS { USBHSD_BASE } |
| AnnaBridge | 163:e59c8e839560 | 11857 | /** Array initializer of USBHSD peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 11858 | #define USBHSD_BASE_PTRS { USBHSD } |
| AnnaBridge | 163:e59c8e839560 | 11859 | /** Interrupt vectors for the USBHSD peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 11860 | #define USBHSD_IRQS { USB1_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 11861 | #define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 11862 | |
| AnnaBridge | 163:e59c8e839560 | 11863 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11864 | * @} |
| AnnaBridge | 163:e59c8e839560 | 11865 | */ /* end of group USBHSD_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 11866 | |
| AnnaBridge | 163:e59c8e839560 | 11867 | |
| AnnaBridge | 163:e59c8e839560 | 11868 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 11869 | -- USBHSH Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 11870 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 11871 | |
| AnnaBridge | 163:e59c8e839560 | 11872 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11873 | * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 11874 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 11875 | */ |
| AnnaBridge | 163:e59c8e839560 | 11876 | |
| AnnaBridge | 163:e59c8e839560 | 11877 | /** USBHSH - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 11878 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 11879 | __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 11880 | __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 11881 | __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 11882 | __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 11883 | __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ |
| AnnaBridge | 163:e59c8e839560 | 11884 | __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 11885 | __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 11886 | __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ |
| AnnaBridge | 163:e59c8e839560 | 11887 | __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ |
| AnnaBridge | 163:e59c8e839560 | 11888 | __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ |
| AnnaBridge | 163:e59c8e839560 | 11889 | __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ |
| AnnaBridge | 163:e59c8e839560 | 11890 | __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ |
| AnnaBridge | 163:e59c8e839560 | 11891 | __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */ |
| AnnaBridge | 163:e59c8e839560 | 11892 | __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */ |
| AnnaBridge | 163:e59c8e839560 | 11893 | __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */ |
| AnnaBridge | 163:e59c8e839560 | 11894 | __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */ |
| AnnaBridge | 163:e59c8e839560 | 11895 | __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */ |
| AnnaBridge | 163:e59c8e839560 | 11896 | __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */ |
| AnnaBridge | 163:e59c8e839560 | 11897 | __IO uint32_t LAST_PTD_INUSE; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ |
| AnnaBridge | 163:e59c8e839560 | 11898 | __IO uint32_t UTMIPLUS_ULPI_DEBUG; /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */ |
| AnnaBridge | 163:e59c8e839560 | 11899 | __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ |
| AnnaBridge | 163:e59c8e839560 | 11900 | } USBHSH_Type; |
| AnnaBridge | 163:e59c8e839560 | 11901 | |
| AnnaBridge | 163:e59c8e839560 | 11902 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 11903 | -- USBHSH Register Masks |
| AnnaBridge | 163:e59c8e839560 | 11904 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 11905 | |
| AnnaBridge | 163:e59c8e839560 | 11906 | /*! |
| AnnaBridge | 163:e59c8e839560 | 11907 | * @addtogroup USBHSH_Register_Masks USBHSH Register Masks |
| AnnaBridge | 163:e59c8e839560 | 11908 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 11909 | */ |
| AnnaBridge | 163:e59c8e839560 | 11910 | |
| AnnaBridge | 163:e59c8e839560 | 11911 | /*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ |
| AnnaBridge | 163:e59c8e839560 | 11912 | #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 11913 | #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11914 | #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11915 | #define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 11916 | #define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11917 | #define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11918 | |
| AnnaBridge | 163:e59c8e839560 | 11919 | /*! @name HCSPARAMS - Host Controller Structural Parameters */ |
| AnnaBridge | 163:e59c8e839560 | 11920 | #define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) |
| AnnaBridge | 163:e59c8e839560 | 11921 | #define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11922 | #define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11923 | #define USBHSH_HCSPARAMS_PPC_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 11924 | #define USBHSH_HCSPARAMS_PPC_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11925 | #define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11926 | #define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 11927 | #define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11928 | #define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11929 | |
| AnnaBridge | 163:e59c8e839560 | 11930 | /*! @name HCCPARAMS - Host Controller Capability Parameters */ |
| AnnaBridge | 163:e59c8e839560 | 11931 | #define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 11932 | #define USBHSH_HCCPARAMS_LPMC_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 11933 | #define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11934 | |
| AnnaBridge | 163:e59c8e839560 | 11935 | /*! @name FLADJ_FRINDEX - Frame Length Adjustment */ |
| AnnaBridge | 163:e59c8e839560 | 11936 | #define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) |
| AnnaBridge | 163:e59c8e839560 | 11937 | #define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11938 | #define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11939 | #define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 11940 | #define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11941 | #define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11942 | |
| AnnaBridge | 163:e59c8e839560 | 11943 | /*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */ |
| AnnaBridge | 163:e59c8e839560 | 11944 | #define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U) |
| AnnaBridge | 163:e59c8e839560 | 11945 | #define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 11946 | #define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11947 | #define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U) |
| AnnaBridge | 163:e59c8e839560 | 11948 | #define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 11949 | #define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11950 | |
| AnnaBridge | 163:e59c8e839560 | 11951 | /*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */ |
| AnnaBridge | 163:e59c8e839560 | 11952 | #define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U) |
| AnnaBridge | 163:e59c8e839560 | 11953 | #define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 11954 | #define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11955 | #define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U) |
| AnnaBridge | 163:e59c8e839560 | 11956 | #define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 11957 | #define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11958 | |
| AnnaBridge | 163:e59c8e839560 | 11959 | /*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */ |
| AnnaBridge | 163:e59c8e839560 | 11960 | #define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U) |
| AnnaBridge | 163:e59c8e839560 | 11961 | #define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 11962 | #define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11963 | #define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U) |
| AnnaBridge | 163:e59c8e839560 | 11964 | #define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 11965 | #define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11966 | |
| AnnaBridge | 163:e59c8e839560 | 11967 | /*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */ |
| AnnaBridge | 163:e59c8e839560 | 11968 | #define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 11969 | #define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 11970 | #define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11971 | |
| AnnaBridge | 163:e59c8e839560 | 11972 | /*! @name USBCMD - USB Command register */ |
| AnnaBridge | 163:e59c8e839560 | 11973 | #define USBHSH_USBCMD_RS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 11974 | #define USBHSH_USBCMD_RS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 11975 | #define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11976 | #define USBHSH_USBCMD_HCRESET_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 11977 | #define USBHSH_USBCMD_HCRESET_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 11978 | #define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11979 | #define USBHSH_USBCMD_FLS_MASK (0xCU) |
| AnnaBridge | 163:e59c8e839560 | 11980 | #define USBHSH_USBCMD_FLS_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 11981 | #define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11982 | #define USBHSH_USBCMD_LHCR_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 11983 | #define USBHSH_USBCMD_LHCR_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 11984 | #define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11985 | #define USBHSH_USBCMD_ATL_EN_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 11986 | #define USBHSH_USBCMD_ATL_EN_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 11987 | #define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11988 | #define USBHSH_USBCMD_ISO_EN_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 11989 | #define USBHSH_USBCMD_ISO_EN_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 11990 | #define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11991 | #define USBHSH_USBCMD_INT_EN_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 11992 | #define USBHSH_USBCMD_INT_EN_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 11993 | #define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11994 | #define USBHSH_USBCMD_HIRD_MASK (0xF000000U) |
| AnnaBridge | 163:e59c8e839560 | 11995 | #define USBHSH_USBCMD_HIRD_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 11996 | #define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 11997 | #define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U) |
| AnnaBridge | 163:e59c8e839560 | 11998 | #define USBHSH_USBCMD_LPM_RWU_SHIFT (28U) |
| AnnaBridge | 163:e59c8e839560 | 11999 | #define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12000 | |
| AnnaBridge | 163:e59c8e839560 | 12001 | /*! @name USBSTS - USB Interrupt Status register */ |
| AnnaBridge | 163:e59c8e839560 | 12002 | #define USBHSH_USBSTS_PCD_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 12003 | #define USBHSH_USBSTS_PCD_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 12004 | #define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12005 | #define USBHSH_USBSTS_FLR_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 12006 | #define USBHSH_USBSTS_FLR_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 12007 | #define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12008 | #define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 12009 | #define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 12010 | #define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12011 | #define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 12012 | #define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 12013 | #define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12014 | #define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 12015 | #define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 12016 | #define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12017 | #define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 12018 | #define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 12019 | #define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12020 | |
| AnnaBridge | 163:e59c8e839560 | 12021 | /*! @name USBINTR - USB Interrupt Enable register */ |
| AnnaBridge | 163:e59c8e839560 | 12022 | #define USBHSH_USBINTR_PCDE_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 12023 | #define USBHSH_USBINTR_PCDE_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 12024 | #define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12025 | #define USBHSH_USBINTR_FLRE_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 12026 | #define USBHSH_USBINTR_FLRE_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 12027 | #define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12028 | #define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 12029 | #define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 12030 | #define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12031 | #define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) |
| AnnaBridge | 163:e59c8e839560 | 12032 | #define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) |
| AnnaBridge | 163:e59c8e839560 | 12033 | #define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12034 | #define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 12035 | #define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 12036 | #define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12037 | #define USBHSH_USBINTR_SOF_E_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 12038 | #define USBHSH_USBINTR_SOF_E_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 12039 | #define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12040 | |
| AnnaBridge | 163:e59c8e839560 | 12041 | /*! @name PORTSC1 - Port Status and Control register */ |
| AnnaBridge | 163:e59c8e839560 | 12042 | #define USBHSH_PORTSC1_CCS_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 12043 | #define USBHSH_PORTSC1_CCS_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12044 | #define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12045 | #define USBHSH_PORTSC1_CSC_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 12046 | #define USBHSH_PORTSC1_CSC_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 12047 | #define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12048 | #define USBHSH_PORTSC1_PED_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 12049 | #define USBHSH_PORTSC1_PED_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 12050 | #define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12051 | #define USBHSH_PORTSC1_PEDC_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 12052 | #define USBHSH_PORTSC1_PEDC_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 12053 | #define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12054 | #define USBHSH_PORTSC1_OCA_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 12055 | #define USBHSH_PORTSC1_OCA_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 12056 | #define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12057 | #define USBHSH_PORTSC1_OCC_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 12058 | #define USBHSH_PORTSC1_OCC_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 12059 | #define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12060 | #define USBHSH_PORTSC1_FPR_MASK (0x40U) |
| AnnaBridge | 163:e59c8e839560 | 12061 | #define USBHSH_PORTSC1_FPR_SHIFT (6U) |
| AnnaBridge | 163:e59c8e839560 | 12062 | #define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12063 | #define USBHSH_PORTSC1_SUSP_MASK (0x80U) |
| AnnaBridge | 163:e59c8e839560 | 12064 | #define USBHSH_PORTSC1_SUSP_SHIFT (7U) |
| AnnaBridge | 163:e59c8e839560 | 12065 | #define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12066 | #define USBHSH_PORTSC1_PR_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 12067 | #define USBHSH_PORTSC1_PR_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 12068 | #define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12069 | #define USBHSH_PORTSC1_SUS_L1_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 12070 | #define USBHSH_PORTSC1_SUS_L1_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 12071 | #define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12072 | #define USBHSH_PORTSC1_LS_MASK (0xC00U) |
| AnnaBridge | 163:e59c8e839560 | 12073 | #define USBHSH_PORTSC1_LS_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 12074 | #define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12075 | #define USBHSH_PORTSC1_PP_MASK (0x1000U) |
| AnnaBridge | 163:e59c8e839560 | 12076 | #define USBHSH_PORTSC1_PP_SHIFT (12U) |
| AnnaBridge | 163:e59c8e839560 | 12077 | #define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12078 | #define USBHSH_PORTSC1_PIC_MASK (0xC000U) |
| AnnaBridge | 163:e59c8e839560 | 12079 | #define USBHSH_PORTSC1_PIC_SHIFT (14U) |
| AnnaBridge | 163:e59c8e839560 | 12080 | #define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12081 | #define USBHSH_PORTSC1_PTC_MASK (0xF0000U) |
| AnnaBridge | 163:e59c8e839560 | 12082 | #define USBHSH_PORTSC1_PTC_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 12083 | #define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12084 | #define USBHSH_PORTSC1_PSPD_MASK (0x300000U) |
| AnnaBridge | 163:e59c8e839560 | 12085 | #define USBHSH_PORTSC1_PSPD_SHIFT (20U) |
| AnnaBridge | 163:e59c8e839560 | 12086 | #define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12087 | #define USBHSH_PORTSC1_WOO_MASK (0x400000U) |
| AnnaBridge | 163:e59c8e839560 | 12088 | #define USBHSH_PORTSC1_WOO_SHIFT (22U) |
| AnnaBridge | 163:e59c8e839560 | 12089 | #define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12090 | #define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U) |
| AnnaBridge | 163:e59c8e839560 | 12091 | #define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U) |
| AnnaBridge | 163:e59c8e839560 | 12092 | #define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12093 | #define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U) |
| AnnaBridge | 163:e59c8e839560 | 12094 | #define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 12095 | #define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12096 | |
| AnnaBridge | 163:e59c8e839560 | 12097 | /*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */ |
| AnnaBridge | 163:e59c8e839560 | 12098 | #define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 12099 | #define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12100 | #define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12101 | |
| AnnaBridge | 163:e59c8e839560 | 12102 | /*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */ |
| AnnaBridge | 163:e59c8e839560 | 12103 | #define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 12104 | #define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12105 | #define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12106 | |
| AnnaBridge | 163:e59c8e839560 | 12107 | /*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */ |
| AnnaBridge | 163:e59c8e839560 | 12108 | #define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 12109 | #define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12110 | #define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12111 | |
| AnnaBridge | 163:e59c8e839560 | 12112 | /*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */ |
| AnnaBridge | 163:e59c8e839560 | 12113 | #define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 12114 | #define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12115 | #define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12116 | |
| AnnaBridge | 163:e59c8e839560 | 12117 | /*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */ |
| AnnaBridge | 163:e59c8e839560 | 12118 | #define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 12119 | #define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12120 | #define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12121 | |
| AnnaBridge | 163:e59c8e839560 | 12122 | /*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */ |
| AnnaBridge | 163:e59c8e839560 | 12123 | #define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 12124 | #define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12125 | #define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12126 | |
| AnnaBridge | 163:e59c8e839560 | 12127 | /*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */ |
| AnnaBridge | 163:e59c8e839560 | 12128 | #define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU) |
| AnnaBridge | 163:e59c8e839560 | 12129 | #define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12130 | #define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12131 | #define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U) |
| AnnaBridge | 163:e59c8e839560 | 12132 | #define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 12133 | #define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12134 | #define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U) |
| AnnaBridge | 163:e59c8e839560 | 12135 | #define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 12136 | #define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12137 | |
| AnnaBridge | 163:e59c8e839560 | 12138 | /*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */ |
| AnnaBridge | 163:e59c8e839560 | 12139 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 12140 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12141 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12142 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U) |
| AnnaBridge | 163:e59c8e839560 | 12143 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 12144 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12145 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U) |
| AnnaBridge | 163:e59c8e839560 | 12146 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 12147 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12148 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U) |
| AnnaBridge | 163:e59c8e839560 | 12149 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U) |
| AnnaBridge | 163:e59c8e839560 | 12150 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12151 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U) |
| AnnaBridge | 163:e59c8e839560 | 12152 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U) |
| AnnaBridge | 163:e59c8e839560 | 12153 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12154 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 12155 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 12156 | #define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12157 | |
| AnnaBridge | 163:e59c8e839560 | 12158 | /*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ |
| AnnaBridge | 163:e59c8e839560 | 12159 | #define USBHSH_PORTMODE_ID0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 12160 | #define USBHSH_PORTMODE_ID0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12161 | #define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12162 | #define USBHSH_PORTMODE_ID0_EN_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 12163 | #define USBHSH_PORTMODE_ID0_EN_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 12164 | #define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12165 | #define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) |
| AnnaBridge | 163:e59c8e839560 | 12166 | #define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) |
| AnnaBridge | 163:e59c8e839560 | 12167 | #define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12168 | #define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) |
| AnnaBridge | 163:e59c8e839560 | 12169 | #define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) |
| AnnaBridge | 163:e59c8e839560 | 12170 | #define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12171 | #define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) |
| AnnaBridge | 163:e59c8e839560 | 12172 | #define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) |
| AnnaBridge | 163:e59c8e839560 | 12173 | #define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12174 | |
| AnnaBridge | 163:e59c8e839560 | 12175 | |
| AnnaBridge | 163:e59c8e839560 | 12176 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12177 | * @} |
| AnnaBridge | 163:e59c8e839560 | 12178 | */ /* end of group USBHSH_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 12179 | |
| AnnaBridge | 163:e59c8e839560 | 12180 | |
| AnnaBridge | 163:e59c8e839560 | 12181 | /* USBHSH - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 12182 | /** Peripheral USBHSH base address */ |
| AnnaBridge | 163:e59c8e839560 | 12183 | #define USBHSH_BASE (0x400A3000u) |
| AnnaBridge | 163:e59c8e839560 | 12184 | /** Peripheral USBHSH base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 12185 | #define USBHSH ((USBHSH_Type *)USBHSH_BASE) |
| AnnaBridge | 163:e59c8e839560 | 12186 | /** Array initializer of USBHSH peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 12187 | #define USBHSH_BASE_ADDRS { USBHSH_BASE } |
| AnnaBridge | 163:e59c8e839560 | 12188 | /** Array initializer of USBHSH peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 12189 | #define USBHSH_BASE_PTRS { USBHSH } |
| AnnaBridge | 163:e59c8e839560 | 12190 | /** Interrupt vectors for the USBHSH peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 12191 | #define USBHSH_IRQS { USB1_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 12192 | #define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 12193 | |
| AnnaBridge | 163:e59c8e839560 | 12194 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12195 | * @} |
| AnnaBridge | 163:e59c8e839560 | 12196 | */ /* end of group USBHSH_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 12197 | |
| AnnaBridge | 163:e59c8e839560 | 12198 | |
| AnnaBridge | 163:e59c8e839560 | 12199 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 12200 | -- UTICK Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 12201 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 12202 | |
| AnnaBridge | 163:e59c8e839560 | 12203 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12204 | * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 12205 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 12206 | */ |
| AnnaBridge | 163:e59c8e839560 | 12207 | |
| AnnaBridge | 163:e59c8e839560 | 12208 | /** UTICK - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 12209 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 12210 | __IO uint32_t CTRL; /**< Control register., offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 12211 | __IO uint32_t STAT; /**< Status register., offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 12212 | __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 12213 | __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 12214 | __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 12215 | } UTICK_Type; |
| AnnaBridge | 163:e59c8e839560 | 12216 | |
| AnnaBridge | 163:e59c8e839560 | 12217 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 12218 | -- UTICK Register Masks |
| AnnaBridge | 163:e59c8e839560 | 12219 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 12220 | |
| AnnaBridge | 163:e59c8e839560 | 12221 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12222 | * @addtogroup UTICK_Register_Masks UTICK Register Masks |
| AnnaBridge | 163:e59c8e839560 | 12223 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 12224 | */ |
| AnnaBridge | 163:e59c8e839560 | 12225 | |
| AnnaBridge | 163:e59c8e839560 | 12226 | /*! @name CTRL - Control register. */ |
| AnnaBridge | 163:e59c8e839560 | 12227 | #define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 12228 | #define UTICK_CTRL_DELAYVAL_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12229 | #define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12230 | #define UTICK_CTRL_REPEAT_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 12231 | #define UTICK_CTRL_REPEAT_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 12232 | #define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12233 | |
| AnnaBridge | 163:e59c8e839560 | 12234 | /*! @name STAT - Status register. */ |
| AnnaBridge | 163:e59c8e839560 | 12235 | #define UTICK_STAT_INTR_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 12236 | #define UTICK_STAT_INTR_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12237 | #define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12238 | #define UTICK_STAT_ACTIVE_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 12239 | #define UTICK_STAT_ACTIVE_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 12240 | #define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12241 | |
| AnnaBridge | 163:e59c8e839560 | 12242 | /*! @name CFG - Capture configuration register. */ |
| AnnaBridge | 163:e59c8e839560 | 12243 | #define UTICK_CFG_CAPEN0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 12244 | #define UTICK_CFG_CAPEN0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12245 | #define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12246 | #define UTICK_CFG_CAPEN1_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 12247 | #define UTICK_CFG_CAPEN1_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 12248 | #define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12249 | #define UTICK_CFG_CAPEN2_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 12250 | #define UTICK_CFG_CAPEN2_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 12251 | #define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12252 | #define UTICK_CFG_CAPEN3_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 12253 | #define UTICK_CFG_CAPEN3_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 12254 | #define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12255 | #define UTICK_CFG_CAPPOL0_MASK (0x100U) |
| AnnaBridge | 163:e59c8e839560 | 12256 | #define UTICK_CFG_CAPPOL0_SHIFT (8U) |
| AnnaBridge | 163:e59c8e839560 | 12257 | #define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12258 | #define UTICK_CFG_CAPPOL1_MASK (0x200U) |
| AnnaBridge | 163:e59c8e839560 | 12259 | #define UTICK_CFG_CAPPOL1_SHIFT (9U) |
| AnnaBridge | 163:e59c8e839560 | 12260 | #define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12261 | #define UTICK_CFG_CAPPOL2_MASK (0x400U) |
| AnnaBridge | 163:e59c8e839560 | 12262 | #define UTICK_CFG_CAPPOL2_SHIFT (10U) |
| AnnaBridge | 163:e59c8e839560 | 12263 | #define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12264 | #define UTICK_CFG_CAPPOL3_MASK (0x800U) |
| AnnaBridge | 163:e59c8e839560 | 12265 | #define UTICK_CFG_CAPPOL3_SHIFT (11U) |
| AnnaBridge | 163:e59c8e839560 | 12266 | #define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12267 | |
| AnnaBridge | 163:e59c8e839560 | 12268 | /*! @name CAPCLR - Capture clear register. */ |
| AnnaBridge | 163:e59c8e839560 | 12269 | #define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 12270 | #define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12271 | #define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12272 | #define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 12273 | #define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 12274 | #define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12275 | #define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 12276 | #define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 12277 | #define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12278 | #define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 12279 | #define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 12280 | #define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12281 | |
| AnnaBridge | 163:e59c8e839560 | 12282 | /*! @name CAP - Capture register . */ |
| AnnaBridge | 163:e59c8e839560 | 12283 | #define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 12284 | #define UTICK_CAP_CAP_VALUE_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12285 | #define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12286 | #define UTICK_CAP_VALID_MASK (0x80000000U) |
| AnnaBridge | 163:e59c8e839560 | 12287 | #define UTICK_CAP_VALID_SHIFT (31U) |
| AnnaBridge | 163:e59c8e839560 | 12288 | #define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12289 | |
| AnnaBridge | 163:e59c8e839560 | 12290 | /* The count of UTICK_CAP */ |
| AnnaBridge | 163:e59c8e839560 | 12291 | #define UTICK_CAP_COUNT (4U) |
| AnnaBridge | 163:e59c8e839560 | 12292 | |
| AnnaBridge | 163:e59c8e839560 | 12293 | |
| AnnaBridge | 163:e59c8e839560 | 12294 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12295 | * @} |
| AnnaBridge | 163:e59c8e839560 | 12296 | */ /* end of group UTICK_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 12297 | |
| AnnaBridge | 163:e59c8e839560 | 12298 | |
| AnnaBridge | 163:e59c8e839560 | 12299 | /* UTICK - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 12300 | /** Peripheral UTICK0 base address */ |
| AnnaBridge | 163:e59c8e839560 | 12301 | #define UTICK0_BASE (0x4000E000u) |
| AnnaBridge | 163:e59c8e839560 | 12302 | /** Peripheral UTICK0 base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 12303 | #define UTICK0 ((UTICK_Type *)UTICK0_BASE) |
| AnnaBridge | 163:e59c8e839560 | 12304 | /** Array initializer of UTICK peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 12305 | #define UTICK_BASE_ADDRS { UTICK0_BASE } |
| AnnaBridge | 163:e59c8e839560 | 12306 | /** Array initializer of UTICK peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 12307 | #define UTICK_BASE_PTRS { UTICK0 } |
| AnnaBridge | 163:e59c8e839560 | 12308 | /** Interrupt vectors for the UTICK peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 12309 | #define UTICK_IRQS { UTICK0_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 12310 | |
| AnnaBridge | 163:e59c8e839560 | 12311 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12312 | * @} |
| AnnaBridge | 163:e59c8e839560 | 12313 | */ /* end of group UTICK_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 12314 | |
| AnnaBridge | 163:e59c8e839560 | 12315 | |
| AnnaBridge | 163:e59c8e839560 | 12316 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 12317 | -- WWDT Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 12318 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 12319 | |
| AnnaBridge | 163:e59c8e839560 | 12320 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12321 | * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer |
| AnnaBridge | 163:e59c8e839560 | 12322 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 12323 | */ |
| AnnaBridge | 163:e59c8e839560 | 12324 | |
| AnnaBridge | 163:e59c8e839560 | 12325 | /** WWDT - Register Layout Typedef */ |
| AnnaBridge | 163:e59c8e839560 | 12326 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 12327 | __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ |
| AnnaBridge | 163:e59c8e839560 | 12328 | __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ |
| AnnaBridge | 163:e59c8e839560 | 12329 | __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ |
| AnnaBridge | 163:e59c8e839560 | 12330 | __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ |
| AnnaBridge | 163:e59c8e839560 | 12331 | uint8_t RESERVED_0[4]; |
| AnnaBridge | 163:e59c8e839560 | 12332 | __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ |
| AnnaBridge | 163:e59c8e839560 | 12333 | __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ |
| AnnaBridge | 163:e59c8e839560 | 12334 | } WWDT_Type; |
| AnnaBridge | 163:e59c8e839560 | 12335 | |
| AnnaBridge | 163:e59c8e839560 | 12336 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 12337 | -- WWDT Register Masks |
| AnnaBridge | 163:e59c8e839560 | 12338 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 12339 | |
| AnnaBridge | 163:e59c8e839560 | 12340 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12341 | * @addtogroup WWDT_Register_Masks WWDT Register Masks |
| AnnaBridge | 163:e59c8e839560 | 12342 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 12343 | */ |
| AnnaBridge | 163:e59c8e839560 | 12344 | |
| AnnaBridge | 163:e59c8e839560 | 12345 | /*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ |
| AnnaBridge | 163:e59c8e839560 | 12346 | #define WWDT_MOD_WDEN_MASK (0x1U) |
| AnnaBridge | 163:e59c8e839560 | 12347 | #define WWDT_MOD_WDEN_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12348 | #define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12349 | #define WWDT_MOD_WDRESET_MASK (0x2U) |
| AnnaBridge | 163:e59c8e839560 | 12350 | #define WWDT_MOD_WDRESET_SHIFT (1U) |
| AnnaBridge | 163:e59c8e839560 | 12351 | #define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12352 | #define WWDT_MOD_WDTOF_MASK (0x4U) |
| AnnaBridge | 163:e59c8e839560 | 12353 | #define WWDT_MOD_WDTOF_SHIFT (2U) |
| AnnaBridge | 163:e59c8e839560 | 12354 | #define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12355 | #define WWDT_MOD_WDINT_MASK (0x8U) |
| AnnaBridge | 163:e59c8e839560 | 12356 | #define WWDT_MOD_WDINT_SHIFT (3U) |
| AnnaBridge | 163:e59c8e839560 | 12357 | #define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12358 | #define WWDT_MOD_WDPROTECT_MASK (0x10U) |
| AnnaBridge | 163:e59c8e839560 | 12359 | #define WWDT_MOD_WDPROTECT_SHIFT (4U) |
| AnnaBridge | 163:e59c8e839560 | 12360 | #define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12361 | #define WWDT_MOD_LOCK_MASK (0x20U) |
| AnnaBridge | 163:e59c8e839560 | 12362 | #define WWDT_MOD_LOCK_SHIFT (5U) |
| AnnaBridge | 163:e59c8e839560 | 12363 | #define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12364 | |
| AnnaBridge | 163:e59c8e839560 | 12365 | /*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ |
| AnnaBridge | 163:e59c8e839560 | 12366 | #define WWDT_TC_COUNT_MASK (0xFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 12367 | #define WWDT_TC_COUNT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12368 | #define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12369 | |
| AnnaBridge | 163:e59c8e839560 | 12370 | /*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ |
| AnnaBridge | 163:e59c8e839560 | 12371 | #define WWDT_FEED_FEED_MASK (0xFFU) |
| AnnaBridge | 163:e59c8e839560 | 12372 | #define WWDT_FEED_FEED_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12373 | #define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12374 | |
| AnnaBridge | 163:e59c8e839560 | 12375 | /*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ |
| AnnaBridge | 163:e59c8e839560 | 12376 | #define WWDT_TV_COUNT_MASK (0xFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 12377 | #define WWDT_TV_COUNT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12378 | #define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12379 | |
| AnnaBridge | 163:e59c8e839560 | 12380 | /*! @name WARNINT - Watchdog Warning Interrupt compare value. */ |
| AnnaBridge | 163:e59c8e839560 | 12381 | #define WWDT_WARNINT_WARNINT_MASK (0x3FFU) |
| AnnaBridge | 163:e59c8e839560 | 12382 | #define WWDT_WARNINT_WARNINT_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12383 | #define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12384 | |
| AnnaBridge | 163:e59c8e839560 | 12385 | /*! @name WINDOW - Watchdog Window compare value. */ |
| AnnaBridge | 163:e59c8e839560 | 12386 | #define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) |
| AnnaBridge | 163:e59c8e839560 | 12387 | #define WWDT_WINDOW_WINDOW_SHIFT (0U) |
| AnnaBridge | 163:e59c8e839560 | 12388 | #define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) |
| AnnaBridge | 163:e59c8e839560 | 12389 | |
| AnnaBridge | 163:e59c8e839560 | 12390 | |
| AnnaBridge | 163:e59c8e839560 | 12391 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12392 | * @} |
| AnnaBridge | 163:e59c8e839560 | 12393 | */ /* end of group WWDT_Register_Masks */ |
| AnnaBridge | 163:e59c8e839560 | 12394 | |
| AnnaBridge | 163:e59c8e839560 | 12395 | |
| AnnaBridge | 163:e59c8e839560 | 12396 | /* WWDT - Peripheral instance base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 12397 | /** Peripheral WWDT base address */ |
| AnnaBridge | 163:e59c8e839560 | 12398 | #define WWDT_BASE (0x4000C000u) |
| AnnaBridge | 163:e59c8e839560 | 12399 | /** Peripheral WWDT base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 12400 | #define WWDT ((WWDT_Type *)WWDT_BASE) |
| AnnaBridge | 163:e59c8e839560 | 12401 | /** Array initializer of WWDT peripheral base addresses */ |
| AnnaBridge | 163:e59c8e839560 | 12402 | #define WWDT_BASE_ADDRS { WWDT_BASE } |
| AnnaBridge | 163:e59c8e839560 | 12403 | /** Array initializer of WWDT peripheral base pointers */ |
| AnnaBridge | 163:e59c8e839560 | 12404 | #define WWDT_BASE_PTRS { WWDT } |
| AnnaBridge | 163:e59c8e839560 | 12405 | /** Interrupt vectors for the WWDT peripheral type */ |
| AnnaBridge | 163:e59c8e839560 | 12406 | #define WWDT_IRQS { WDT_BOD_IRQn } |
| AnnaBridge | 163:e59c8e839560 | 12407 | |
| AnnaBridge | 163:e59c8e839560 | 12408 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12409 | * @} |
| AnnaBridge | 163:e59c8e839560 | 12410 | */ /* end of group WWDT_Peripheral_Access_Layer */ |
| AnnaBridge | 163:e59c8e839560 | 12411 | |
| AnnaBridge | 163:e59c8e839560 | 12412 | |
| AnnaBridge | 163:e59c8e839560 | 12413 | /* |
| AnnaBridge | 163:e59c8e839560 | 12414 | ** End of section using anonymous unions |
| AnnaBridge | 163:e59c8e839560 | 12415 | */ |
| AnnaBridge | 163:e59c8e839560 | 12416 | |
| AnnaBridge | 163:e59c8e839560 | 12417 | #if defined(__ARMCC_VERSION) |
| AnnaBridge | 163:e59c8e839560 | 12418 | #pragma pop |
| AnnaBridge | 163:e59c8e839560 | 12419 | #elif defined(__GNUC__) |
| AnnaBridge | 163:e59c8e839560 | 12420 | /* leave anonymous unions enabled */ |
| AnnaBridge | 163:e59c8e839560 | 12421 | #elif defined(__IAR_SYSTEMS_ICC__) |
| AnnaBridge | 163:e59c8e839560 | 12422 | #pragma language=default |
| AnnaBridge | 163:e59c8e839560 | 12423 | #else |
| AnnaBridge | 163:e59c8e839560 | 12424 | #error Not supported compiler type |
| AnnaBridge | 163:e59c8e839560 | 12425 | #endif |
| AnnaBridge | 163:e59c8e839560 | 12426 | |
| AnnaBridge | 163:e59c8e839560 | 12427 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12428 | * @} |
| AnnaBridge | 163:e59c8e839560 | 12429 | */ /* end of group Peripheral_access_layer */ |
| AnnaBridge | 163:e59c8e839560 | 12430 | |
| AnnaBridge | 163:e59c8e839560 | 12431 | |
| AnnaBridge | 163:e59c8e839560 | 12432 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 12433 | -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). |
| AnnaBridge | 163:e59c8e839560 | 12434 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 12435 | |
| AnnaBridge | 163:e59c8e839560 | 12436 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12437 | * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). |
| AnnaBridge | 163:e59c8e839560 | 12438 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 12439 | */ |
| AnnaBridge | 163:e59c8e839560 | 12440 | |
| AnnaBridge | 163:e59c8e839560 | 12441 | #if defined(__ARMCC_VERSION) |
| AnnaBridge | 163:e59c8e839560 | 12442 | #if (__ARMCC_VERSION >= 6010050) |
| AnnaBridge | 163:e59c8e839560 | 12443 | #pragma clang system_header |
| AnnaBridge | 163:e59c8e839560 | 12444 | #endif |
| AnnaBridge | 163:e59c8e839560 | 12445 | #elif defined(__IAR_SYSTEMS_ICC__) |
| AnnaBridge | 163:e59c8e839560 | 12446 | #pragma system_include |
| AnnaBridge | 163:e59c8e839560 | 12447 | #endif |
| AnnaBridge | 163:e59c8e839560 | 12448 | |
| AnnaBridge | 163:e59c8e839560 | 12449 | /** |
| AnnaBridge | 163:e59c8e839560 | 12450 | * @brief Mask and left-shift a bit field value for use in a register bit range. |
| AnnaBridge | 163:e59c8e839560 | 12451 | * @param field Name of the register bit field. |
| AnnaBridge | 163:e59c8e839560 | 12452 | * @param value Value of the bit field. |
| AnnaBridge | 163:e59c8e839560 | 12453 | * @return Masked and shifted value. |
| AnnaBridge | 163:e59c8e839560 | 12454 | */ |
| AnnaBridge | 163:e59c8e839560 | 12455 | #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) |
| AnnaBridge | 163:e59c8e839560 | 12456 | /** |
| AnnaBridge | 163:e59c8e839560 | 12457 | * @brief Mask and right-shift a register value to extract a bit field value. |
| AnnaBridge | 163:e59c8e839560 | 12458 | * @param field Name of the register bit field. |
| AnnaBridge | 163:e59c8e839560 | 12459 | * @param value Value of the register. |
| AnnaBridge | 163:e59c8e839560 | 12460 | * @return Masked and shifted bit field value. |
| AnnaBridge | 163:e59c8e839560 | 12461 | */ |
| AnnaBridge | 163:e59c8e839560 | 12462 | #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) |
| AnnaBridge | 163:e59c8e839560 | 12463 | |
| AnnaBridge | 163:e59c8e839560 | 12464 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12465 | * @} |
| AnnaBridge | 163:e59c8e839560 | 12466 | */ /* end of group Bit_Field_Generic_Macros */ |
| AnnaBridge | 163:e59c8e839560 | 12467 | |
| AnnaBridge | 163:e59c8e839560 | 12468 | |
| AnnaBridge | 163:e59c8e839560 | 12469 | /* ---------------------------------------------------------------------------- |
| AnnaBridge | 163:e59c8e839560 | 12470 | -- SDK Compatibility |
| AnnaBridge | 163:e59c8e839560 | 12471 | ---------------------------------------------------------------------------- */ |
| AnnaBridge | 163:e59c8e839560 | 12472 | |
| AnnaBridge | 163:e59c8e839560 | 12473 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12474 | * @addtogroup SDK_Compatibility_Symbols SDK Compatibility |
| AnnaBridge | 163:e59c8e839560 | 12475 | * @{ |
| AnnaBridge | 163:e59c8e839560 | 12476 | */ |
| AnnaBridge | 163:e59c8e839560 | 12477 | |
| AnnaBridge | 163:e59c8e839560 | 12478 | /** EMC CS base address */ |
| AnnaBridge | 163:e59c8e839560 | 12479 | #define EMC_CS0_BASE (0x80000000u) |
| AnnaBridge | 163:e59c8e839560 | 12480 | #define EMC_CS1_BASE (0x90000000u) |
| AnnaBridge | 163:e59c8e839560 | 12481 | #define EMC_CS2_BASE (0x98000000u) |
| AnnaBridge | 163:e59c8e839560 | 12482 | #define EMC_CS3_BASE (0x9C000000u) |
| AnnaBridge | 163:e59c8e839560 | 12483 | #define EMC_DYCS0_BASE (0xA0000000u) |
| AnnaBridge | 163:e59c8e839560 | 12484 | #define EMC_DYCS1_BASE (0xB0000000u) |
| AnnaBridge | 163:e59c8e839560 | 12485 | #define EMC_DYCS2_BASE (0xC0000000u) |
| AnnaBridge | 163:e59c8e839560 | 12486 | #define EMC_DYCS3_BASE (0xD0000000u) |
| AnnaBridge | 163:e59c8e839560 | 12487 | #define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE} |
| AnnaBridge | 163:e59c8e839560 | 12488 | #define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE} |
| AnnaBridge | 163:e59c8e839560 | 12489 | |
| AnnaBridge | 163:e59c8e839560 | 12490 | /** OTP API */ |
| AnnaBridge | 163:e59c8e839560 | 12491 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 12492 | uint32_t (*otpInit)(void); /** Initializes OTP controller */ |
| AnnaBridge | 163:e59c8e839560 | 12493 | uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */ |
| AnnaBridge | 163:e59c8e839560 | 12494 | uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */ |
| AnnaBridge | 163:e59c8e839560 | 12495 | uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, |
| AnnaBridge | 163:e59c8e839560 | 12496 | uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */ |
| AnnaBridge | 163:e59c8e839560 | 12497 | uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, |
| AnnaBridge | 163:e59c8e839560 | 12498 | uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */ |
| AnnaBridge | 163:e59c8e839560 | 12499 | uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */ |
| AnnaBridge | 163:e59c8e839560 | 12500 | uint32_t RESERVED_0[5]; |
| AnnaBridge | 163:e59c8e839560 | 12501 | uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */ |
| AnnaBridge | 163:e59c8e839560 | 12502 | uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */ |
| AnnaBridge | 163:e59c8e839560 | 12503 | } OTP_API_Type; |
| AnnaBridge | 163:e59c8e839560 | 12504 | |
| AnnaBridge | 163:e59c8e839560 | 12505 | /** ROM API */ |
| AnnaBridge | 163:e59c8e839560 | 12506 | typedef struct { |
| AnnaBridge | 163:e59c8e839560 | 12507 | __I uint32_t usbdApiBase; /** USB API Base */ |
| AnnaBridge | 163:e59c8e839560 | 12508 | uint32_t RESERVED_0[13]; |
| AnnaBridge | 163:e59c8e839560 | 12509 | __I OTP_API_Type *otpApiBase; /** OTP API Base */ |
| AnnaBridge | 163:e59c8e839560 | 12510 | __I uint32_t aesApiBase; /** AES API Base */ |
| AnnaBridge | 163:e59c8e839560 | 12511 | __I uint32_t secureApiBase; /** Secure API Base */ |
| AnnaBridge | 163:e59c8e839560 | 12512 | } ROM_API_Type; |
| AnnaBridge | 163:e59c8e839560 | 12513 | |
| AnnaBridge | 163:e59c8e839560 | 12514 | /** ROM API base address */ |
| AnnaBridge | 163:e59c8e839560 | 12515 | #define ROM_API_BASE (0x03000200u) |
| AnnaBridge | 163:e59c8e839560 | 12516 | /** ROM API base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 12517 | #define ROM_API (*(ROM_API_Type**) ROM_API_BASE) |
| AnnaBridge | 163:e59c8e839560 | 12518 | /** OTP API base pointer */ |
| AnnaBridge | 163:e59c8e839560 | 12519 | #define OTP_API (ROM_API->otpApiBase) |
| AnnaBridge | 163:e59c8e839560 | 12520 | |
| AnnaBridge | 163:e59c8e839560 | 12521 | /*! |
| AnnaBridge | 163:e59c8e839560 | 12522 | * @} |
| AnnaBridge | 163:e59c8e839560 | 12523 | */ /* end of group SDK_Compatibility_Symbols */ |
| AnnaBridge | 163:e59c8e839560 | 12524 | |
| AnnaBridge | 163:e59c8e839560 | 12525 | |
| AnnaBridge | 163:e59c8e839560 | 12526 | #endif /* _LPC54628_H_ */ |
| AnnaBridge | 163:e59c8e839560 | 12527 |
