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TARGET_LPC54114/TOOLCHAIN_IAR/fsl_dma.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 148:fd96258d940d 1 /*
Kojto 148:fd96258d940d 2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
Kojto 148:fd96258d940d 3 * All rights reserved.
Kojto 148:fd96258d940d 4 *
Kojto 148:fd96258d940d 5 * Redistribution and use in source and binary forms, with or without modification,
Kojto 148:fd96258d940d 6 * are permitted provided that the following conditions are met:
Kojto 148:fd96258d940d 7 *
Kojto 148:fd96258d940d 8 * o Redistributions of source code must retain the above copyright notice, this list
Kojto 148:fd96258d940d 9 * of conditions and the following disclaimer.
Kojto 148:fd96258d940d 10 *
Kojto 148:fd96258d940d 11 * o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 148:fd96258d940d 12 * list of conditions and the following disclaimer in the documentation and/or
Kojto 148:fd96258d940d 13 * other materials provided with the distribution.
Kojto 148:fd96258d940d 14 *
Kojto 148:fd96258d940d 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 148:fd96258d940d 16 * contributors may be used to endorse or promote products derived from this
Kojto 148:fd96258d940d 17 * software without specific prior written permission.
Kojto 148:fd96258d940d 18 *
Kojto 148:fd96258d940d 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 148:fd96258d940d 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 148:fd96258d940d 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 148:fd96258d940d 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 148:fd96258d940d 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 148:fd96258d940d 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 148:fd96258d940d 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 148:fd96258d940d 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 148:fd96258d940d 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 148:fd96258d940d 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 148:fd96258d940d 29 */
Kojto 148:fd96258d940d 30
Kojto 148:fd96258d940d 31 #ifndef _FSL_DMA_H_
Kojto 148:fd96258d940d 32 #define _FSL_DMA_H_
Kojto 148:fd96258d940d 33
Kojto 148:fd96258d940d 34 #include "fsl_common.h"
Kojto 148:fd96258d940d 35
Kojto 148:fd96258d940d 36 /*!
Kojto 148:fd96258d940d 37 * @addtogroup dma
Kojto 148:fd96258d940d 38 * @{
Kojto 148:fd96258d940d 39 */
Kojto 148:fd96258d940d 40
Kojto 148:fd96258d940d 41 /*! @file */
Kojto 148:fd96258d940d 42 /*******************************************************************************
Kojto 148:fd96258d940d 43 * Definitions
Kojto 148:fd96258d940d 44 ******************************************************************************/
Kojto 148:fd96258d940d 45
Kojto 148:fd96258d940d 46 /*! @name Driver version */
Kojto 148:fd96258d940d 47 /*@{*/
Kojto 148:fd96258d940d 48 /*! @brief DMA driver version */
Kojto 148:fd96258d940d 49 #define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
Kojto 148:fd96258d940d 50 /*@}*/
Kojto 148:fd96258d940d 51
Kojto 148:fd96258d940d 52 #define DMA_MAX_TRANSFER_COUNT 0x400
Kojto 148:fd96258d940d 53
Kojto 148:fd96258d940d 54 /* Channel group consists of 32 channels. channel_group = (channel / 32) */
Kojto 148:fd96258d940d 55 #define DMA_CHANNEL_GROUP(channel) (((uint8_t)channel) >> 5U)
Kojto 148:fd96258d940d 56 /* Channel index in channel group. channel_index = (channel % 32) */
Kojto 148:fd96258d940d 57 #define DMA_CHANNEL_INDEX(channel) (((uint8_t)channel) & 0x1F)
Kojto 148:fd96258d940d 58
Kojto 148:fd96258d940d 59
Kojto 148:fd96258d940d 60 /*! @brief DMA descriptor structure */
Kojto 148:fd96258d940d 61 typedef struct _dma_descriptor {
Kojto 148:fd96258d940d 62 uint32_t xfercfg; /*!< Transfer configuration */
Kojto 148:fd96258d940d 63 void *srcEndAddr; /*!< Last source address of DMA transfer */
Kojto 148:fd96258d940d 64 void *dstEndAddr; /*!< Last destination address of DMA transfer */
Kojto 148:fd96258d940d 65 void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */
Kojto 148:fd96258d940d 66 } dma_descriptor_t;
Kojto 148:fd96258d940d 67
Kojto 148:fd96258d940d 68 /*! @brief DMA transfer configuration */
Kojto 148:fd96258d940d 69 typedef struct _dma_xfercfg {
Kojto 148:fd96258d940d 70 bool valid; /*!< Descriptor is ready to transfer */
Kojto 148:fd96258d940d 71 bool reload; /*!< Reload channel configuration register after
Kojto 148:fd96258d940d 72 current descriptor is exhausted */
Kojto 148:fd96258d940d 73 bool swtrig; /*!< Perform software trigger. Transfer if fired
Kojto 148:fd96258d940d 74 when 'valid' is set */
Kojto 148:fd96258d940d 75 bool clrtrig; /*!< Clear trigger */
Kojto 148:fd96258d940d 76 bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */
Kojto 148:fd96258d940d 77 bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */
Kojto 148:fd96258d940d 78 uint8_t byteWidth; /*!< Byte width of data to transfer */
Kojto 148:fd96258d940d 79 uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */
Kojto 148:fd96258d940d 80 uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */
Kojto 148:fd96258d940d 81 uint16_t transferCount; /*!< Number of transfers */
Kojto 148:fd96258d940d 82 } dma_xfercfg_t;
Kojto 148:fd96258d940d 83
Kojto 148:fd96258d940d 84 /*! @brief DMA channel priority */
Kojto 148:fd96258d940d 85 typedef enum _dma_priority {
Kojto 148:fd96258d940d 86 kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */
Kojto 148:fd96258d940d 87 kDMA_ChannelPriority1, /*!< Channel priority 1 */
Kojto 148:fd96258d940d 88 kDMA_ChannelPriority2, /*!< Channel priority 2 */
Kojto 148:fd96258d940d 89 kDMA_ChannelPriority3, /*!< Channel priority 3 */
Kojto 148:fd96258d940d 90 kDMA_ChannelPriority4, /*!< Channel priority 4 */
Kojto 148:fd96258d940d 91 kDMA_ChannelPriority5, /*!< Channel priority 5 */
Kojto 148:fd96258d940d 92 kDMA_ChannelPriority6, /*!< Channel priority 6 */
Kojto 148:fd96258d940d 93 kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */
Kojto 148:fd96258d940d 94 } dma_priority_t;
Kojto 148:fd96258d940d 95
Kojto 148:fd96258d940d 96 /*! @brief DMA interrupt flags */
Kojto 148:fd96258d940d 97 typedef enum _dma_int {
Kojto 148:fd96258d940d 98 kDMA_IntA, /*!< DMA interrupt flag A */
Kojto 148:fd96258d940d 99 kDMA_IntB, /*!< DMA interrupt flag B */
Kojto 148:fd96258d940d 100 } dma_irq_t;
Kojto 148:fd96258d940d 101
Kojto 148:fd96258d940d 102 /*! @brief DMA trigger type*/
Kojto 148:fd96258d940d 103 typedef enum _dma_trigger_type {
Kojto 148:fd96258d940d 104 kDMA_NoTrigger = 0, /*!< Trigger is disabled */
Kojto 148:fd96258d940d 105 kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */
Kojto 148:fd96258d940d 106 kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */
Kojto 148:fd96258d940d 107 kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */
Kojto 148:fd96258d940d 108 kDMA_RisingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */
Kojto 148:fd96258d940d 109 } dma_trigger_type_t;
Kojto 148:fd96258d940d 110
Kojto 148:fd96258d940d 111 /*! @brief DMA trigger burst */
Kojto 148:fd96258d940d 112 typedef enum _dma_trigger_burst {
Kojto 148:fd96258d940d 113 kDMA_SingleTransfer = 0, /*!< Single transfer */
Kojto 148:fd96258d940d 114 kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */
Kojto 148:fd96258d940d 115 kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */
Kojto 148:fd96258d940d 116 kDMA_EdgeBurstTransfer2 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */
Kojto 148:fd96258d940d 117 kDMA_EdgeBurstTransfer4 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */
Kojto 148:fd96258d940d 118 kDMA_EdgeBurstTransfer8 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */
Kojto 148:fd96258d940d 119 kDMA_EdgeBurstTransfer16 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */
Kojto 148:fd96258d940d 120 kDMA_EdgeBurstTransfer32 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */
Kojto 148:fd96258d940d 121 kDMA_EdgeBurstTransfer64 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */
Kojto 148:fd96258d940d 122 kDMA_EdgeBurstTransfer128 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */
Kojto 148:fd96258d940d 123 kDMA_EdgeBurstTransfer256 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */
Kojto 148:fd96258d940d 124 kDMA_EdgeBurstTransfer512 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */
Kojto 148:fd96258d940d 125 kDMA_EdgeBurstTransfer1024 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */
Kojto 148:fd96258d940d 126 } dma_trigger_burst_t;
Kojto 148:fd96258d940d 127
Kojto 148:fd96258d940d 128 /*! @brief DMA burst wrapping */
Kojto 148:fd96258d940d 129 typedef enum _dma_burst_wrap {
Kojto 148:fd96258d940d 130 kDMA_NoWrap = 0, /*!< Wrapping is disabled */
Kojto 148:fd96258d940d 131 kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */
Kojto 148:fd96258d940d 132 kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */
Kojto 148:fd96258d940d 133 kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */
Kojto 148:fd96258d940d 134 } dma_burst_wrap_t;
Kojto 148:fd96258d940d 135
Kojto 148:fd96258d940d 136 /*! @brief DMA transfer type */
Kojto 148:fd96258d940d 137 typedef enum _dma_transfer_type
Kojto 148:fd96258d940d 138 {
Kojto 148:fd96258d940d 139 kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */
Kojto 148:fd96258d940d 140 kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */
Kojto 148:fd96258d940d 141 kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/
Kojto 148:fd96258d940d 142 kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */
Kojto 148:fd96258d940d 143 } dma_transfer_type_t;
Kojto 148:fd96258d940d 144
Kojto 148:fd96258d940d 145 /*! @brief DMA channel trigger */
Kojto 148:fd96258d940d 146 typedef struct _dma_channel_trigger {
Kojto 148:fd96258d940d 147 dma_trigger_type_t type;
Kojto 148:fd96258d940d 148 dma_trigger_burst_t burst;
Kojto 148:fd96258d940d 149 dma_burst_wrap_t wrap;
Kojto 148:fd96258d940d 150 } dma_channel_trigger_t;
Kojto 148:fd96258d940d 151
Kojto 148:fd96258d940d 152 /*! @brief DMA transfer status */
Kojto 148:fd96258d940d 153 enum _dma_transfer_status
Kojto 148:fd96258d940d 154 {
Kojto 148:fd96258d940d 155 kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the
Kojto 148:fd96258d940d 156 transfer request. */
Kojto 148:fd96258d940d 157 };
Kojto 148:fd96258d940d 158
Kojto 148:fd96258d940d 159 /*! @brief DMA transfer configuration */
Kojto 148:fd96258d940d 160 typedef struct _dma_transfer_config
Kojto 148:fd96258d940d 161 {
Kojto 148:fd96258d940d 162 uint8_t *srcAddr; /*!< Source data address */
Kojto 148:fd96258d940d 163 uint8_t *dstAddr; /*!< Destination data address */
Kojto 148:fd96258d940d 164 uint8_t *nextDesc; /*!< Chain custom descriptor */
Kojto 148:fd96258d940d 165 dma_xfercfg_t xfercfg; /*!< Transfer options */
Kojto 148:fd96258d940d 166 bool isPeriph; /*!< DMA transfer is driven by peripheral */
Kojto 148:fd96258d940d 167 } dma_transfer_config_t;
Kojto 148:fd96258d940d 168
Kojto 148:fd96258d940d 169 /*! @brief Callback for DMA */
Kojto 148:fd96258d940d 170 struct _dma_handle;
Kojto 148:fd96258d940d 171
Kojto 148:fd96258d940d 172 /*! @brief Define Callback function for DMA. */
Kojto 148:fd96258d940d 173 typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode);
Kojto 148:fd96258d940d 174
Kojto 148:fd96258d940d 175 /*! @brief DMA transfer handle structure */
Kojto 148:fd96258d940d 176 typedef struct _dma_handle
Kojto 148:fd96258d940d 177 {
Kojto 148:fd96258d940d 178 dma_callback callback; /*!< Callback function. Invoked when transfer
Kojto 148:fd96258d940d 179 of descriptor with interrupt flag finishes */
Kojto 148:fd96258d940d 180 void *userData; /*!< Callback function parameter */
Kojto 148:fd96258d940d 181 DMA_Type *base; /*!< DMA peripheral base address */
Kojto 148:fd96258d940d 182 uint8_t channel; /*!< DMA channel number */
Kojto 148:fd96258d940d 183 } dma_handle_t;
Kojto 148:fd96258d940d 184
Kojto 148:fd96258d940d 185 /*******************************************************************************
Kojto 148:fd96258d940d 186 * APIs
Kojto 148:fd96258d940d 187 ******************************************************************************/
Kojto 148:fd96258d940d 188 #if defined(__cplusplus)
Kojto 148:fd96258d940d 189 extern "C" {
Kojto 148:fd96258d940d 190 #endif /* __cplusplus */
Kojto 148:fd96258d940d 191
Kojto 148:fd96258d940d 192 /*!
Kojto 148:fd96258d940d 193 * @name DMA initialization and De-initialization
Kojto 148:fd96258d940d 194 * @{
Kojto 148:fd96258d940d 195 */
Kojto 148:fd96258d940d 196
Kojto 148:fd96258d940d 197 /*!
Kojto 148:fd96258d940d 198 * @brief Initializes DMA peripheral.
Kojto 148:fd96258d940d 199 *
Kojto 148:fd96258d940d 200 * This function enable the DMA clock, set descriptor table and
Kojto 148:fd96258d940d 201 * enable DMA peripheral.
Kojto 148:fd96258d940d 202 *
Kojto 148:fd96258d940d 203 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 204 */
Kojto 148:fd96258d940d 205 void DMA_Init(DMA_Type *base);
Kojto 148:fd96258d940d 206
Kojto 148:fd96258d940d 207 /*!
Kojto 148:fd96258d940d 208 * @brief Deinitializes DMA peripheral.
Kojto 148:fd96258d940d 209 *
Kojto 148:fd96258d940d 210 * This function gates the DMA clock.
Kojto 148:fd96258d940d 211 *
Kojto 148:fd96258d940d 212 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 213 */
Kojto 148:fd96258d940d 214 void DMA_Deinit(DMA_Type *base);
Kojto 148:fd96258d940d 215
Kojto 148:fd96258d940d 216 /* @} */
Kojto 148:fd96258d940d 217 /*!
Kojto 148:fd96258d940d 218 * @name DMA Channel Operation
Kojto 148:fd96258d940d 219 * @{
Kojto 148:fd96258d940d 220 */
Kojto 148:fd96258d940d 221
Kojto 148:fd96258d940d 222 /*!
Kojto 148:fd96258d940d 223 * @brief Return whether DMA channel is processing transfer
Kojto 148:fd96258d940d 224 *
Kojto 148:fd96258d940d 225 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 226 * @param channel DMA channel number.
Kojto 148:fd96258d940d 227 * @return True for active state, false otherwise.
Kojto 148:fd96258d940d 228 */
Kojto 148:fd96258d940d 229 static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)
Kojto 148:fd96258d940d 230 {
Kojto 148:fd96258d940d 231 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
Kojto 148:fd96258d940d 232 return (base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false;
Kojto 148:fd96258d940d 233 }
Kojto 148:fd96258d940d 234
Kojto 148:fd96258d940d 235 /*!
Kojto 148:fd96258d940d 236 * @brief Enables the interrupt source for the DMA transfer.
Kojto 148:fd96258d940d 237 *
Kojto 148:fd96258d940d 238 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 239 * @param channel DMA channel number.
Kojto 148:fd96258d940d 240 */
Kojto 148:fd96258d940d 241 static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel)
Kojto 148:fd96258d940d 242 {
Kojto 148:fd96258d940d 243 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
Kojto 148:fd96258d940d 244 base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(channel);
Kojto 148:fd96258d940d 245 }
Kojto 148:fd96258d940d 246
Kojto 148:fd96258d940d 247 /*!
Kojto 148:fd96258d940d 248 * @brief Disables the interrupt source for the DMA transfer.
Kojto 148:fd96258d940d 249 *
Kojto 148:fd96258d940d 250 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 251 * @param channel DMA channel number.
Kojto 148:fd96258d940d 252 */
Kojto 148:fd96258d940d 253 static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel)
Kojto 148:fd96258d940d 254 {
Kojto 148:fd96258d940d 255 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
Kojto 148:fd96258d940d 256 base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENCLR |= 1U << DMA_CHANNEL_INDEX(channel);
Kojto 148:fd96258d940d 257 }
Kojto 148:fd96258d940d 258
Kojto 148:fd96258d940d 259 /*!
Kojto 148:fd96258d940d 260 * @brief Enable DMA channel.
Kojto 148:fd96258d940d 261 *
Kojto 148:fd96258d940d 262 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 263 * @param channel DMA channel number.
Kojto 148:fd96258d940d 264 */
Kojto 148:fd96258d940d 265 static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel)
Kojto 148:fd96258d940d 266 {
Kojto 148:fd96258d940d 267 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
Kojto 148:fd96258d940d 268 base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLESET |= 1U << DMA_CHANNEL_INDEX(channel);
Kojto 148:fd96258d940d 269 }
Kojto 148:fd96258d940d 270
Kojto 148:fd96258d940d 271 /*!
Kojto 148:fd96258d940d 272 * @brief Disable DMA channel.
Kojto 148:fd96258d940d 273 *
Kojto 148:fd96258d940d 274 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 275 * @param channel DMA channel number.
Kojto 148:fd96258d940d 276 */
Kojto 148:fd96258d940d 277 static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel)
Kojto 148:fd96258d940d 278 {
Kojto 148:fd96258d940d 279 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
Kojto 148:fd96258d940d 280 base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLECLR |= 1U << DMA_CHANNEL_INDEX(channel);
Kojto 148:fd96258d940d 281 }
Kojto 148:fd96258d940d 282
Kojto 148:fd96258d940d 283 /*!
Kojto 148:fd96258d940d 284 * @brief Set PERIPHREQEN of channel configuration register.
Kojto 148:fd96258d940d 285 *
Kojto 148:fd96258d940d 286 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 287 * @param channel DMA channel number.
Kojto 148:fd96258d940d 288 */
Kojto 148:fd96258d940d 289 static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel)
Kojto 148:fd96258d940d 290 {
Kojto 148:fd96258d940d 291 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
Kojto 148:fd96258d940d 292 base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
Kojto 148:fd96258d940d 293 }
Kojto 148:fd96258d940d 294
Kojto 148:fd96258d940d 295 /*!
Kojto 148:fd96258d940d 296 * @brief Get PERIPHREQEN value of channel configuration register.
Kojto 148:fd96258d940d 297 *
Kojto 148:fd96258d940d 298 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 299 * @param channel DMA channel number.
Kojto 148:fd96258d940d 300 * @return True for enabled PeriphRq, false for disabled.
Kojto 148:fd96258d940d 301 */
Kojto 148:fd96258d940d 302 static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)
Kojto 148:fd96258d940d 303 {
Kojto 148:fd96258d940d 304 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
Kojto 148:fd96258d940d 305 base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
Kojto 148:fd96258d940d 306 }
Kojto 148:fd96258d940d 307
Kojto 148:fd96258d940d 308 /*!
Kojto 148:fd96258d940d 309 * @brief Set trigger settings of DMA channel.
Kojto 148:fd96258d940d 310 *
Kojto 148:fd96258d940d 311 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 312 * @param channel DMA channel number.
Kojto 148:fd96258d940d 313 * @param trigger trigger configuration.
Kojto 148:fd96258d940d 314 */
Kojto 148:fd96258d940d 315 void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger);
Kojto 148:fd96258d940d 316
Kojto 148:fd96258d940d 317 /*!
Kojto 148:fd96258d940d 318 * @brief Gets the remaining bytes of the current DMA descriptor transfer.
Kojto 148:fd96258d940d 319 *
Kojto 148:fd96258d940d 320 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 321 * @param channel DMA channel number.
Kojto 148:fd96258d940d 322 * @return The number of bytes which have not been transferred yet.
Kojto 148:fd96258d940d 323 */
Kojto 148:fd96258d940d 324 uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
Kojto 148:fd96258d940d 325
Kojto 148:fd96258d940d 326 /*!
Kojto 148:fd96258d940d 327 * @brief Set priority of channel configuration register.
Kojto 148:fd96258d940d 328 *
Kojto 148:fd96258d940d 329 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 330 * @param channel DMA channel number.
Kojto 148:fd96258d940d 331 * @param priority Channel priority value.
Kojto 148:fd96258d940d 332 */
Kojto 148:fd96258d940d 333 static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority)
Kojto 148:fd96258d940d 334 {
Kojto 148:fd96258d940d 335 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
Kojto 148:fd96258d940d 336 base->CHANNEL[channel].CFG = (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority);
Kojto 148:fd96258d940d 337 }
Kojto 148:fd96258d940d 338
Kojto 148:fd96258d940d 339 /*!
Kojto 148:fd96258d940d 340 * @brief Get priority of channel configuration register.
Kojto 148:fd96258d940d 341 *
Kojto 148:fd96258d940d 342 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 343 * @param channel DMA channel number.
Kojto 148:fd96258d940d 344 * @return Channel priority value.
Kojto 148:fd96258d940d 345 */
Kojto 148:fd96258d940d 346 static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel)
Kojto 148:fd96258d940d 347 {
Kojto 148:fd96258d940d 348 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
Kojto 148:fd96258d940d 349 return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
Kojto 148:fd96258d940d 350 }
Kojto 148:fd96258d940d 351
Kojto 148:fd96258d940d 352 /*!
Kojto 148:fd96258d940d 353 * @brief Create application specific DMA descriptor
Kojto 148:fd96258d940d 354 * to be used in a chain in transfer
Kojto 148:fd96258d940d 355 *
Kojto 148:fd96258d940d 356 * @param desc DMA descriptor address.
Kojto 148:fd96258d940d 357 * @param xfercfg Transfer configuration for DMA descriptor.
Kojto 148:fd96258d940d 358 * @param srcAddr Address of last item to transmit
Kojto 148:fd96258d940d 359 * @param dstAddr Address of last item to receive.
Kojto 148:fd96258d940d 360 * @param nextDesc Address of next descriptor in chain.
Kojto 148:fd96258d940d 361 */
Kojto 148:fd96258d940d 362 void DMA_CreateDescriptor(
Kojto 148:fd96258d940d 363 dma_descriptor_t *desc,
Kojto 148:fd96258d940d 364 dma_xfercfg_t *xfercfg,
Kojto 148:fd96258d940d 365 void *srcAddr,
Kojto 148:fd96258d940d 366 void *dstAddr,
Kojto 148:fd96258d940d 367 void *nextDesc
Kojto 148:fd96258d940d 368 );
Kojto 148:fd96258d940d 369
Kojto 148:fd96258d940d 370 /* @} */
Kojto 148:fd96258d940d 371
Kojto 148:fd96258d940d 372 /*!
Kojto 148:fd96258d940d 373 * @name DMA Transactional Operation
Kojto 148:fd96258d940d 374 * @{
Kojto 148:fd96258d940d 375 */
Kojto 148:fd96258d940d 376
Kojto 148:fd96258d940d 377 /*!
Kojto 148:fd96258d940d 378 * @brief Abort running transfer by handle.
Kojto 148:fd96258d940d 379 *
Kojto 148:fd96258d940d 380 * This function aborts DMA transfer specified by handle.
Kojto 148:fd96258d940d 381 *
Kojto 148:fd96258d940d 382 * @param handle DMA handle pointer.
Kojto 148:fd96258d940d 383 */
Kojto 148:fd96258d940d 384 void DMA_AbortTransfer(dma_handle_t *handle);
Kojto 148:fd96258d940d 385
Kojto 148:fd96258d940d 386 /*!
Kojto 148:fd96258d940d 387 * @brief Creates the DMA handle.
Kojto 148:fd96258d940d 388 *
Kojto 148:fd96258d940d 389 * This function is called if using transaction API for DMA. This function
Kojto 148:fd96258d940d 390 * initializes the internal state of DMA handle.
Kojto 148:fd96258d940d 391 *
Kojto 148:fd96258d940d 392 * @param handle DMA handle pointer. The DMA handle stores callback function and
Kojto 148:fd96258d940d 393 * parameters.
Kojto 148:fd96258d940d 394 * @param base DMA peripheral base address.
Kojto 148:fd96258d940d 395 * @param channel DMA channel number.
Kojto 148:fd96258d940d 396 */
Kojto 148:fd96258d940d 397 void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel);
Kojto 148:fd96258d940d 398
Kojto 148:fd96258d940d 399 /*!
Kojto 148:fd96258d940d 400 * @brief Installs a callback function for the DMA transfer.
Kojto 148:fd96258d940d 401 *
Kojto 148:fd96258d940d 402 * This callback is called in DMA IRQ handler. Use the callback to do something after
Kojto 148:fd96258d940d 403 * the current major loop transfer completes.
Kojto 148:fd96258d940d 404 *
Kojto 148:fd96258d940d 405 * @param handle DMA handle pointer.
Kojto 148:fd96258d940d 406 * @param callback DMA callback function pointer.
Kojto 148:fd96258d940d 407 * @param userData Parameter for callback function.
Kojto 148:fd96258d940d 408 */
Kojto 148:fd96258d940d 409 void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData);
Kojto 148:fd96258d940d 410
Kojto 148:fd96258d940d 411 /*!
Kojto 148:fd96258d940d 412 * @brief Prepares the DMA transfer structure.
Kojto 148:fd96258d940d 413 *
Kojto 148:fd96258d940d 414 * This function prepares the transfer configuration structure according to the user input.
Kojto 148:fd96258d940d 415 *
Kojto 148:fd96258d940d 416 * @param config The user configuration structure of type dma_transfer_t.
Kojto 148:fd96258d940d 417 * @param srcAddr DMA transfer source address.
Kojto 148:fd96258d940d 418 * @param dstAddr DMA transfer destination address.
Kojto 148:fd96258d940d 419 * @param byteWidth DMA transfer destination address width(bytes).
Kojto 148:fd96258d940d 420 * @param transferBytes DMA transfer bytes to be transferred.
Kojto 148:fd96258d940d 421 * @param type DMA transfer type.
Kojto 148:fd96258d940d 422 * @param nextDesc Chain custom descriptor to transfer.
Kojto 148:fd96258d940d 423 * @note The data address and the data width must be consistent. For example, if the SRC
Kojto 148:fd96258d940d 424 * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
Kojto 148:fd96258d940d 425 * source address error(SAE).
Kojto 148:fd96258d940d 426 */
Kojto 148:fd96258d940d 427 void DMA_PrepareTransfer(dma_transfer_config_t *config,
Kojto 148:fd96258d940d 428 void *srcAddr,
Kojto 148:fd96258d940d 429 void *dstAddr,
Kojto 148:fd96258d940d 430 uint32_t byteWidth,
Kojto 148:fd96258d940d 431 uint32_t transferBytes,
Kojto 148:fd96258d940d 432 dma_transfer_type_t type,
Kojto 148:fd96258d940d 433 void *nextDesc);
Kojto 148:fd96258d940d 434
Kojto 148:fd96258d940d 435 /*!
Kojto 148:fd96258d940d 436 * @brief Submits the DMA transfer request.
Kojto 148:fd96258d940d 437 *
Kojto 148:fd96258d940d 438 * This function submits the DMA transfer request according to the transfer configuration structure.
Kojto 148:fd96258d940d 439 * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
Kojto 148:fd96258d940d 440 * a TCD and enables scatter/gather feature to process it in the next time.
Kojto 148:fd96258d940d 441 *
Kojto 148:fd96258d940d 442 * @param handle DMA handle pointer.
Kojto 148:fd96258d940d 443 * @param config Pointer to DMA transfer configuration structure.
Kojto 148:fd96258d940d 444 * @retval kStatus_DMA_Success It means submit transfer request succeed.
Kojto 148:fd96258d940d 445 * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
Kojto 148:fd96258d940d 446 * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
Kojto 148:fd96258d940d 447 */
Kojto 148:fd96258d940d 448 status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config);
Kojto 148:fd96258d940d 449
Kojto 148:fd96258d940d 450 /*!
Kojto 148:fd96258d940d 451 * @brief DMA start transfer.
Kojto 148:fd96258d940d 452 *
Kojto 148:fd96258d940d 453 * This function enables the channel request. User can call this function after submitting the transfer request
Kojto 148:fd96258d940d 454 * or before submitting the transfer request.
Kojto 148:fd96258d940d 455 *
Kojto 148:fd96258d940d 456 * @param handle DMA handle pointer.
Kojto 148:fd96258d940d 457 */
Kojto 148:fd96258d940d 458 void DMA_StartTransfer(dma_handle_t *handle);
Kojto 148:fd96258d940d 459
Kojto 148:fd96258d940d 460 /*!
Kojto 148:fd96258d940d 461 * @brief DMA IRQ handler for descriptor transfer complete.
Kojto 148:fd96258d940d 462 *
Kojto 148:fd96258d940d 463 * This function clears the channel major interrupt flag and call
Kojto 148:fd96258d940d 464 * the callback function if it is not NULL.
Kojto 148:fd96258d940d 465 */
Kojto 148:fd96258d940d 466 void DMA_HandleIRQ(void);
Kojto 148:fd96258d940d 467
Kojto 148:fd96258d940d 468 /* @} */
Kojto 148:fd96258d940d 469
Kojto 148:fd96258d940d 470 #if defined(__cplusplus)
Kojto 148:fd96258d940d 471 }
Kojto 148:fd96258d940d 472 #endif /* __cplusplus */
Kojto 148:fd96258d940d 473
Kojto 148:fd96258d940d 474 /* @} */
Kojto 148:fd96258d940d 475
Kojto 148:fd96258d940d 476 #endif /*_FSL_DMA_H_*/