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TARGET_LPC4088_DM/TOOLCHAIN_GCC_ARM/LPC407x_8x_177x_8x.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /****************************************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * $Id$ LPC407x_8x_177x_8x.h 2012-04-25
AnnaBridge 171:3a7713b1edbc 3 *//**
AnnaBridge 171:3a7713b1edbc 4 * @file LPC407x_8x_177x_8x.h
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for
AnnaBridge 171:3a7713b1edbc 7 * NXP LPC407x_8x_177x_8x.
AnnaBridge 171:3a7713b1edbc 8 * @version V0.7
AnnaBridge 171:3a7713b1edbc 9 * @date 20. June 2012
AnnaBridge 171:3a7713b1edbc 10 * @author NXP MCU SW Application Team
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Copyright(C) 2012, NXP Semiconductor
AnnaBridge 171:3a7713b1edbc 13 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 ***********************************************************************
AnnaBridge 171:3a7713b1edbc 16 * Software that is described herein is for illustrative purposes only
AnnaBridge 171:3a7713b1edbc 17 * which provides customers with programming information regarding the
AnnaBridge 171:3a7713b1edbc 18 * products. This software is supplied "AS IS" without any warranties.
AnnaBridge 171:3a7713b1edbc 19 * NXP Semiconductors assumes no responsibility or liability for the
AnnaBridge 171:3a7713b1edbc 20 * use of the software, conveys no license or title under any patent,
AnnaBridge 171:3a7713b1edbc 21 * copyright, or mask work right to the product. NXP Semiconductors
AnnaBridge 171:3a7713b1edbc 22 * reserves the right to make changes in the software without
AnnaBridge 171:3a7713b1edbc 23 * notification. NXP Semiconductors also make no representation or
AnnaBridge 171:3a7713b1edbc 24 * warranty that such application will be suitable for the specified
AnnaBridge 171:3a7713b1edbc 25 * use without further testing or modification.
AnnaBridge 171:3a7713b1edbc 26 * Permission to use, copy, modify, and distribute this software and its
AnnaBridge 171:3a7713b1edbc 27 * documentation is hereby granted, under NXP Semiconductors'
AnnaBridge 171:3a7713b1edbc 28 * relevant copyright in the software, without fee, provided that it
AnnaBridge 171:3a7713b1edbc 29 * is used in conjunction with NXP Semiconductors microcontrollers. This
AnnaBridge 171:3a7713b1edbc 30 * copyright, permission, and disclaimer notice must appear in all copies of
AnnaBridge 171:3a7713b1edbc 31 * this code.
AnnaBridge 171:3a7713b1edbc 32 **********************************************************************/
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef __LPC407x_8x_177x_8x_H__
AnnaBridge 171:3a7713b1edbc 35 #define __LPC407x_8x_177x_8x_H__
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #if defined(__CORTEX_M4) && !defined(CORE_M4)
AnnaBridge 171:3a7713b1edbc 38 #define CORE_M4
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 // ##################
AnnaBridge 171:3a7713b1edbc 42 // Code Red - excluded extern "C" as unrequired
AnnaBridge 171:3a7713b1edbc 43 // ##################
AnnaBridge 171:3a7713b1edbc 44 #if 0
AnnaBridge 171:3a7713b1edbc 45 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 46 extern "C" {
AnnaBridge 171:3a7713b1edbc 47 #endif
AnnaBridge 171:3a7713b1edbc 48 #endif
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /* ------------------------- Interrupt Number Definition ------------------------ */
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 typedef enum IRQn
AnnaBridge 171:3a7713b1edbc 54 {
AnnaBridge 171:3a7713b1edbc 55 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
AnnaBridge 171:3a7713b1edbc 56 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
AnnaBridge 171:3a7713b1edbc 57 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 58 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
AnnaBridge 171:3a7713b1edbc 59 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 60 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 61 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 62 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 63 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 64 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 65 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/
AnnaBridge 171:3a7713b1edbc 68 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
AnnaBridge 171:3a7713b1edbc 69 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
AnnaBridge 171:3a7713b1edbc 70 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
AnnaBridge 171:3a7713b1edbc 71 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
AnnaBridge 171:3a7713b1edbc 72 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
AnnaBridge 171:3a7713b1edbc 73 UART0_IRQn = 5, /*!< UART0 Interrupt */
AnnaBridge 171:3a7713b1edbc 74 UART1_IRQn = 6, /*!< UART1 Interrupt */
AnnaBridge 171:3a7713b1edbc 75 UART2_IRQn = 7, /*!< UART2 Interrupt */
AnnaBridge 171:3a7713b1edbc 76 UART3_IRQn = 8, /*!< UART3 Interrupt */
AnnaBridge 171:3a7713b1edbc 77 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
AnnaBridge 171:3a7713b1edbc 78 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
AnnaBridge 171:3a7713b1edbc 79 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
AnnaBridge 171:3a7713b1edbc 80 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
AnnaBridge 171:3a7713b1edbc 81 Reserved0_IRQn = 13, /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 82 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
AnnaBridge 171:3a7713b1edbc 83 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
AnnaBridge 171:3a7713b1edbc 84 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
AnnaBridge 171:3a7713b1edbc 85 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
AnnaBridge 171:3a7713b1edbc 86 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 87 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 88 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
AnnaBridge 171:3a7713b1edbc 89 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
AnnaBridge 171:3a7713b1edbc 90 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
AnnaBridge 171:3a7713b1edbc 91 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
AnnaBridge 171:3a7713b1edbc 92 USB_IRQn = 24, /*!< USB Interrupt */
AnnaBridge 171:3a7713b1edbc 93 CAN_IRQn = 25, /*!< CAN Interrupt */
AnnaBridge 171:3a7713b1edbc 94 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
AnnaBridge 171:3a7713b1edbc 95 I2S_IRQn = 27, /*!< I2S Interrupt */
AnnaBridge 171:3a7713b1edbc 96 ENET_IRQn = 28, /*!< Ethernet Interrupt */
AnnaBridge 171:3a7713b1edbc 97 MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */
AnnaBridge 171:3a7713b1edbc 98 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
AnnaBridge 171:3a7713b1edbc 99 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
AnnaBridge 171:3a7713b1edbc 100 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
AnnaBridge 171:3a7713b1edbc 101 USBActivity_IRQn = 33, /*!< USB Activity interrupt */
AnnaBridge 171:3a7713b1edbc 102 CANActivity_IRQn = 34, /*!< CAN Activity interrupt */
AnnaBridge 171:3a7713b1edbc 103 UART4_IRQn = 35, /*!< UART4 Interrupt */
AnnaBridge 171:3a7713b1edbc 104 SSP2_IRQn = 36, /*!< SSP2 Interrupt */
AnnaBridge 171:3a7713b1edbc 105 LCD_IRQn = 37, /*!< LCD Interrupt */
AnnaBridge 171:3a7713b1edbc 106 GPIO_IRQn = 38, /*!< GPIO Interrupt */
AnnaBridge 171:3a7713b1edbc 107 PWM0_IRQn = 39, /*!< 39 PWM0 */
AnnaBridge 171:3a7713b1edbc 108 EEPROM_IRQn = 40, /*!< 40 EEPROM */
AnnaBridge 171:3a7713b1edbc 109 CMP0_IRQn = 41, /*!< 41 CMP0 */
AnnaBridge 171:3a7713b1edbc 110 CMP1_IRQn = 42 /*!< 42 CMP1 */
AnnaBridge 171:3a7713b1edbc 111 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 114 /* ================ Processor and Core Peripheral Section ================ */
AnnaBridge 171:3a7713b1edbc 115 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 116 #ifdef CORE_M4
AnnaBridge 171:3a7713b1edbc 117 /* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */
AnnaBridge 171:3a7713b1edbc 118 #define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */
AnnaBridge 171:3a7713b1edbc 119 #define __MPU_PRESENT 1 /*!< MPU present or not */
AnnaBridge 171:3a7713b1edbc 120 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
AnnaBridge 171:3a7713b1edbc 121 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 122 #define __FPU_PRESENT 1 /*!< FPU present or not */
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 126 #else
AnnaBridge 171:3a7713b1edbc 127 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
AnnaBridge 171:3a7713b1edbc 128 #define __MPU_PRESENT 1 /*!< MPU present or not */
AnnaBridge 171:3a7713b1edbc 129 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
AnnaBridge 171:3a7713b1edbc 130 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 #endif
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 #include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140
AnnaBridge 171:3a7713b1edbc 141
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143
AnnaBridge 171:3a7713b1edbc 144 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 145 /* ================ Device Specific Peripheral Section ================ */
AnnaBridge 171:3a7713b1edbc 146 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 149 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 150 #endif
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
AnnaBridge 171:3a7713b1edbc 153 typedef struct /* Common Registers */
AnnaBridge 171:3a7713b1edbc 154 {
AnnaBridge 171:3a7713b1edbc 155 __I uint32_t IntStat;
AnnaBridge 171:3a7713b1edbc 156 __I uint32_t IntTCStat;
AnnaBridge 171:3a7713b1edbc 157 __O uint32_t IntTCClear;
AnnaBridge 171:3a7713b1edbc 158 __I uint32_t IntErrStat;
AnnaBridge 171:3a7713b1edbc 159 __O uint32_t IntErrClr;
AnnaBridge 171:3a7713b1edbc 160 __I uint32_t RawIntTCStat;
AnnaBridge 171:3a7713b1edbc 161 __I uint32_t RawIntErrStat;
AnnaBridge 171:3a7713b1edbc 162 __I uint32_t EnbldChns;
AnnaBridge 171:3a7713b1edbc 163 __IO uint32_t SoftBReq;
AnnaBridge 171:3a7713b1edbc 164 __IO uint32_t SoftSReq;
AnnaBridge 171:3a7713b1edbc 165 __IO uint32_t SoftLBReq;
AnnaBridge 171:3a7713b1edbc 166 __IO uint32_t SoftLSReq;
AnnaBridge 171:3a7713b1edbc 167 __IO uint32_t Config;
AnnaBridge 171:3a7713b1edbc 168 __IO uint32_t Sync;
AnnaBridge 171:3a7713b1edbc 169 } LPC_GPDMA_TypeDef;
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 typedef struct /* Channel Registers */
AnnaBridge 171:3a7713b1edbc 172 {
AnnaBridge 171:3a7713b1edbc 173 __IO uint32_t CSrcAddr;
AnnaBridge 171:3a7713b1edbc 174 __IO uint32_t CDestAddr;
AnnaBridge 171:3a7713b1edbc 175 __IO uint32_t CLLI;
AnnaBridge 171:3a7713b1edbc 176 __IO uint32_t CControl;
AnnaBridge 171:3a7713b1edbc 177 __IO uint32_t CConfig;
AnnaBridge 171:3a7713b1edbc 178 } LPC_GPDMACH_TypeDef;
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 /*------------- System Control (SC) ------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 181 typedef struct
AnnaBridge 171:3a7713b1edbc 182 {
AnnaBridge 171:3a7713b1edbc 183 __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
AnnaBridge 171:3a7713b1edbc 184 uint32_t RESERVED0[31];
AnnaBridge 171:3a7713b1edbc 185 __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */
AnnaBridge 171:3a7713b1edbc 186 __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */
AnnaBridge 171:3a7713b1edbc 187 __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */
AnnaBridge 171:3a7713b1edbc 188 __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */
AnnaBridge 171:3a7713b1edbc 189 uint32_t RESERVED1[4];
AnnaBridge 171:3a7713b1edbc 190 __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */
AnnaBridge 171:3a7713b1edbc 191 __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */
AnnaBridge 171:3a7713b1edbc 192 __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */
AnnaBridge 171:3a7713b1edbc 193 __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */
AnnaBridge 171:3a7713b1edbc 194 uint32_t RESERVED2[4];
AnnaBridge 171:3a7713b1edbc 195 __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */
AnnaBridge 171:3a7713b1edbc 196 __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
AnnaBridge 171:3a7713b1edbc 197 __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */
AnnaBridge 171:3a7713b1edbc 198 uint32_t RESERVED3[13];
AnnaBridge 171:3a7713b1edbc 199 __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
AnnaBridge 171:3a7713b1edbc 200 __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */
AnnaBridge 171:3a7713b1edbc 201 __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */
AnnaBridge 171:3a7713b1edbc 202 __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */
AnnaBridge 171:3a7713b1edbc 203 __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */
AnnaBridge 171:3a7713b1edbc 204 __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */
AnnaBridge 171:3a7713b1edbc 205 uint32_t RESERVED4[10];
AnnaBridge 171:3a7713b1edbc 206 __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 207 uint32_t RESERVED5[1];
AnnaBridge 171:3a7713b1edbc 208 __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */
AnnaBridge 171:3a7713b1edbc 209 __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */
AnnaBridge 171:3a7713b1edbc 210 uint32_t RESERVED6[12];
AnnaBridge 171:3a7713b1edbc 211 __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */
AnnaBridge 171:3a7713b1edbc 212 uint32_t RESERVED7[1];
AnnaBridge 171:3a7713b1edbc 213 __IO uint32_t MATRIXARB; /*!< Offset: 0x188 (R/W) Matrix Arbitration Register */
AnnaBridge 171:3a7713b1edbc 214 uint32_t RESERVED71[5];
AnnaBridge 171:3a7713b1edbc 215 __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */
AnnaBridge 171:3a7713b1edbc 216 __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */
AnnaBridge 171:3a7713b1edbc 217 __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
AnnaBridge 171:3a7713b1edbc 218 uint32_t RESERVED8;
AnnaBridge 171:3a7713b1edbc 219 __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */
AnnaBridge 171:3a7713b1edbc 220 __IO uint32_t SPIFICLKSEL;
AnnaBridge 171:3a7713b1edbc 221 __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
AnnaBridge 171:3a7713b1edbc 222 uint32_t RESERVED10[1];
AnnaBridge 171:3a7713b1edbc 223 __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 224 __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */
AnnaBridge 171:3a7713b1edbc 225 __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */
AnnaBridge 171:3a7713b1edbc 226 __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */
AnnaBridge 171:3a7713b1edbc 227 __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */
AnnaBridge 171:3a7713b1edbc 228 uint32_t RESERVED11[2];
AnnaBridge 171:3a7713b1edbc 229 __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */
AnnaBridge 171:3a7713b1edbc 230 __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */
AnnaBridge 171:3a7713b1edbc 231 } LPC_SC_TypeDef;
AnnaBridge 171:3a7713b1edbc 232 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
AnnaBridge 171:3a7713b1edbc 233 typedef struct
AnnaBridge 171:3a7713b1edbc 234 {
AnnaBridge 171:3a7713b1edbc 235 __IO uint32_t MAC1; /* MAC Registers */
AnnaBridge 171:3a7713b1edbc 236 __IO uint32_t MAC2;
AnnaBridge 171:3a7713b1edbc 237 __IO uint32_t IPGT;
AnnaBridge 171:3a7713b1edbc 238 __IO uint32_t IPGR;
AnnaBridge 171:3a7713b1edbc 239 __IO uint32_t CLRT;
AnnaBridge 171:3a7713b1edbc 240 __IO uint32_t MAXF;
AnnaBridge 171:3a7713b1edbc 241 __IO uint32_t SUPP;
AnnaBridge 171:3a7713b1edbc 242 __IO uint32_t TEST;
AnnaBridge 171:3a7713b1edbc 243 __IO uint32_t MCFG;
AnnaBridge 171:3a7713b1edbc 244 __IO uint32_t MCMD;
AnnaBridge 171:3a7713b1edbc 245 __IO uint32_t MADR;
AnnaBridge 171:3a7713b1edbc 246 __O uint32_t MWTD;
AnnaBridge 171:3a7713b1edbc 247 __I uint32_t MRDD;
AnnaBridge 171:3a7713b1edbc 248 __I uint32_t MIND;
AnnaBridge 171:3a7713b1edbc 249 uint32_t RESERVED0[2];
AnnaBridge 171:3a7713b1edbc 250 __IO uint32_t SA0;
AnnaBridge 171:3a7713b1edbc 251 __IO uint32_t SA1;
AnnaBridge 171:3a7713b1edbc 252 __IO uint32_t SA2;
AnnaBridge 171:3a7713b1edbc 253 uint32_t RESERVED1[45];
AnnaBridge 171:3a7713b1edbc 254 __IO uint32_t Command; /* Control Registers */
AnnaBridge 171:3a7713b1edbc 255 __I uint32_t Status;
AnnaBridge 171:3a7713b1edbc 256 __IO uint32_t RxDescriptor;
AnnaBridge 171:3a7713b1edbc 257 __IO uint32_t RxStatus;
AnnaBridge 171:3a7713b1edbc 258 __IO uint32_t RxDescriptorNumber;
AnnaBridge 171:3a7713b1edbc 259 __I uint32_t RxProduceIndex;
AnnaBridge 171:3a7713b1edbc 260 __IO uint32_t RxConsumeIndex;
AnnaBridge 171:3a7713b1edbc 261 __IO uint32_t TxDescriptor;
AnnaBridge 171:3a7713b1edbc 262 __IO uint32_t TxStatus;
AnnaBridge 171:3a7713b1edbc 263 __IO uint32_t TxDescriptorNumber;
AnnaBridge 171:3a7713b1edbc 264 __IO uint32_t TxProduceIndex;
AnnaBridge 171:3a7713b1edbc 265 __I uint32_t TxConsumeIndex;
AnnaBridge 171:3a7713b1edbc 266 uint32_t RESERVED2[10];
AnnaBridge 171:3a7713b1edbc 267 __I uint32_t TSV0;
AnnaBridge 171:3a7713b1edbc 268 __I uint32_t TSV1;
AnnaBridge 171:3a7713b1edbc 269 __I uint32_t RSV;
AnnaBridge 171:3a7713b1edbc 270 uint32_t RESERVED3[3];
AnnaBridge 171:3a7713b1edbc 271 __IO uint32_t FlowControlCounter;
AnnaBridge 171:3a7713b1edbc 272 __I uint32_t FlowControlStatus;
AnnaBridge 171:3a7713b1edbc 273 uint32_t RESERVED4[34];
AnnaBridge 171:3a7713b1edbc 274 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
AnnaBridge 171:3a7713b1edbc 275 __I uint32_t RxFilterWoLStatus;
AnnaBridge 171:3a7713b1edbc 276 __O uint32_t RxFilterWoLClear;
AnnaBridge 171:3a7713b1edbc 277 uint32_t RESERVED5;
AnnaBridge 171:3a7713b1edbc 278 __IO uint32_t HashFilterL;
AnnaBridge 171:3a7713b1edbc 279 __IO uint32_t HashFilterH;
AnnaBridge 171:3a7713b1edbc 280 uint32_t RESERVED6[882];
AnnaBridge 171:3a7713b1edbc 281 __I uint32_t IntStatus; /* Module Control Registers */
AnnaBridge 171:3a7713b1edbc 282 __IO uint32_t IntEnable;
AnnaBridge 171:3a7713b1edbc 283 __O uint32_t IntClear;
AnnaBridge 171:3a7713b1edbc 284 __O uint32_t IntSet;
AnnaBridge 171:3a7713b1edbc 285 uint32_t RESERVED7;
AnnaBridge 171:3a7713b1edbc 286 __IO uint32_t PowerDown;
AnnaBridge 171:3a7713b1edbc 287 uint32_t RESERVED8;
AnnaBridge 171:3a7713b1edbc 288 __IO uint32_t Module_ID;
AnnaBridge 171:3a7713b1edbc 289 } LPC_EMAC_TypeDef;
AnnaBridge 171:3a7713b1edbc 290
AnnaBridge 171:3a7713b1edbc 291 /*------------- LCD controller (LCD) -----------------------------------------*/
AnnaBridge 171:3a7713b1edbc 292 typedef struct
AnnaBridge 171:3a7713b1edbc 293 {
AnnaBridge 171:3a7713b1edbc 294 __IO uint32_t TIMH; /* LCD Registers */
AnnaBridge 171:3a7713b1edbc 295 __IO uint32_t TIMV;
AnnaBridge 171:3a7713b1edbc 296 __IO uint32_t POL;
AnnaBridge 171:3a7713b1edbc 297 __IO uint32_t LE;
AnnaBridge 171:3a7713b1edbc 298 __IO uint32_t UPBASE;
AnnaBridge 171:3a7713b1edbc 299 __IO uint32_t LPBASE;
AnnaBridge 171:3a7713b1edbc 300 __IO uint32_t CTRL;
AnnaBridge 171:3a7713b1edbc 301 __IO uint32_t INTMSK;
AnnaBridge 171:3a7713b1edbc 302 __I uint32_t INTRAW;
AnnaBridge 171:3a7713b1edbc 303 __I uint32_t INTSTAT;
AnnaBridge 171:3a7713b1edbc 304 __O uint32_t INTCLR;
AnnaBridge 171:3a7713b1edbc 305 __I uint32_t UPCURR;
AnnaBridge 171:3a7713b1edbc 306 __I uint32_t LPCURR;
AnnaBridge 171:3a7713b1edbc 307 uint32_t RESERVED0[115];
AnnaBridge 171:3a7713b1edbc 308 __IO uint32_t PAL[128];
AnnaBridge 171:3a7713b1edbc 309 uint32_t RESERVED1[256];
AnnaBridge 171:3a7713b1edbc 310 __IO uint32_t CRSR_IMG[256];
AnnaBridge 171:3a7713b1edbc 311 __IO uint32_t CRSR_CTRL;
AnnaBridge 171:3a7713b1edbc 312 __IO uint32_t CRSR_CFG;
AnnaBridge 171:3a7713b1edbc 313 __IO uint32_t CRSR_PAL0;
AnnaBridge 171:3a7713b1edbc 314 __IO uint32_t CRSR_PAL1;
AnnaBridge 171:3a7713b1edbc 315 __IO uint32_t CRSR_XY;
AnnaBridge 171:3a7713b1edbc 316 __IO uint32_t CRSR_CLIP;
AnnaBridge 171:3a7713b1edbc 317 uint32_t RESERVED2[2];
AnnaBridge 171:3a7713b1edbc 318 __IO uint32_t CRSR_INTMSK;
AnnaBridge 171:3a7713b1edbc 319 __O uint32_t CRSR_INTCLR;
AnnaBridge 171:3a7713b1edbc 320 __I uint32_t CRSR_INTRAW;
AnnaBridge 171:3a7713b1edbc 321 __I uint32_t CRSR_INTSTAT;
AnnaBridge 171:3a7713b1edbc 322 } LPC_LCD_TypeDef;
AnnaBridge 171:3a7713b1edbc 323
AnnaBridge 171:3a7713b1edbc 324 /*------------- Universal Serial Bus (USB) -----------------------------------*/
AnnaBridge 171:3a7713b1edbc 325 typedef struct
AnnaBridge 171:3a7713b1edbc 326 {
AnnaBridge 171:3a7713b1edbc 327 __I uint32_t Revision; /* USB Host Registers */
AnnaBridge 171:3a7713b1edbc 328 __IO uint32_t Control;
AnnaBridge 171:3a7713b1edbc 329 __IO uint32_t CommandStatus;
AnnaBridge 171:3a7713b1edbc 330 __IO uint32_t InterruptStatus;
AnnaBridge 171:3a7713b1edbc 331 __IO uint32_t InterruptEnable;
AnnaBridge 171:3a7713b1edbc 332 __IO uint32_t InterruptDisable;
AnnaBridge 171:3a7713b1edbc 333 __IO uint32_t HCCA;
AnnaBridge 171:3a7713b1edbc 334 __I uint32_t PeriodCurrentED;
AnnaBridge 171:3a7713b1edbc 335 __IO uint32_t ControlHeadED;
AnnaBridge 171:3a7713b1edbc 336 __IO uint32_t ControlCurrentED;
AnnaBridge 171:3a7713b1edbc 337 __IO uint32_t BulkHeadED;
AnnaBridge 171:3a7713b1edbc 338 __IO uint32_t BulkCurrentED;
AnnaBridge 171:3a7713b1edbc 339 __I uint32_t DoneHead;
AnnaBridge 171:3a7713b1edbc 340 __IO uint32_t FmInterval;
AnnaBridge 171:3a7713b1edbc 341 __I uint32_t FmRemaining;
AnnaBridge 171:3a7713b1edbc 342 __I uint32_t FmNumber;
AnnaBridge 171:3a7713b1edbc 343 __IO uint32_t PeriodicStart;
AnnaBridge 171:3a7713b1edbc 344 __IO uint32_t LSTreshold;
AnnaBridge 171:3a7713b1edbc 345 __IO uint32_t RhDescriptorA;
AnnaBridge 171:3a7713b1edbc 346 __IO uint32_t RhDescriptorB;
AnnaBridge 171:3a7713b1edbc 347 __IO uint32_t RhStatus;
AnnaBridge 171:3a7713b1edbc 348 __IO uint32_t RhPortStatus1;
AnnaBridge 171:3a7713b1edbc 349 __IO uint32_t RhPortStatus2;
AnnaBridge 171:3a7713b1edbc 350 uint32_t RESERVED0[40];
AnnaBridge 171:3a7713b1edbc 351 __I uint32_t Module_ID;
AnnaBridge 171:3a7713b1edbc 352
AnnaBridge 171:3a7713b1edbc 353 __I uint32_t IntSt; /* USB On-The-Go Registers */
AnnaBridge 171:3a7713b1edbc 354 __IO uint32_t IntEn;
AnnaBridge 171:3a7713b1edbc 355 __O uint32_t IntSet;
AnnaBridge 171:3a7713b1edbc 356 __O uint32_t IntClr;
AnnaBridge 171:3a7713b1edbc 357 __IO uint32_t StCtrl;
AnnaBridge 171:3a7713b1edbc 358 __IO uint32_t Tmr;
AnnaBridge 171:3a7713b1edbc 359 uint32_t RESERVED1[58];
AnnaBridge 171:3a7713b1edbc 360
AnnaBridge 171:3a7713b1edbc 361 __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
AnnaBridge 171:3a7713b1edbc 362 __IO uint32_t DevIntEn;
AnnaBridge 171:3a7713b1edbc 363 __O uint32_t DevIntClr;
AnnaBridge 171:3a7713b1edbc 364 __O uint32_t DevIntSet;
AnnaBridge 171:3a7713b1edbc 365
AnnaBridge 171:3a7713b1edbc 366 __O uint32_t CmdCode; /* USB Device SIE Command Registers */
AnnaBridge 171:3a7713b1edbc 367 __I uint32_t CmdData;
AnnaBridge 171:3a7713b1edbc 368
AnnaBridge 171:3a7713b1edbc 369 __I uint32_t RxData; /* USB Device Transfer Registers */
AnnaBridge 171:3a7713b1edbc 370 __O uint32_t TxData;
AnnaBridge 171:3a7713b1edbc 371 __I uint32_t RxPLen;
AnnaBridge 171:3a7713b1edbc 372 __O uint32_t TxPLen;
AnnaBridge 171:3a7713b1edbc 373 __IO uint32_t Ctrl;
AnnaBridge 171:3a7713b1edbc 374 __O uint32_t DevIntPri;
AnnaBridge 171:3a7713b1edbc 375
AnnaBridge 171:3a7713b1edbc 376 __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
AnnaBridge 171:3a7713b1edbc 377 __IO uint32_t EpIntEn;
AnnaBridge 171:3a7713b1edbc 378 __O uint32_t EpIntClr;
AnnaBridge 171:3a7713b1edbc 379 __O uint32_t EpIntSet;
AnnaBridge 171:3a7713b1edbc 380 __O uint32_t EpIntPri;
AnnaBridge 171:3a7713b1edbc 381
AnnaBridge 171:3a7713b1edbc 382 __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
AnnaBridge 171:3a7713b1edbc 383 __O uint32_t EpInd;
AnnaBridge 171:3a7713b1edbc 384 __IO uint32_t MaxPSize;
AnnaBridge 171:3a7713b1edbc 385
AnnaBridge 171:3a7713b1edbc 386 __I uint32_t DMARSt; /* USB Device DMA Registers */
AnnaBridge 171:3a7713b1edbc 387 __O uint32_t DMARClr;
AnnaBridge 171:3a7713b1edbc 388 __O uint32_t DMARSet;
AnnaBridge 171:3a7713b1edbc 389 uint32_t RESERVED2[9];
AnnaBridge 171:3a7713b1edbc 390 __IO uint32_t UDCAH;
AnnaBridge 171:3a7713b1edbc 391 __I uint32_t EpDMASt;
AnnaBridge 171:3a7713b1edbc 392 __O uint32_t EpDMAEn;
AnnaBridge 171:3a7713b1edbc 393 __O uint32_t EpDMADis;
AnnaBridge 171:3a7713b1edbc 394 __I uint32_t DMAIntSt;
AnnaBridge 171:3a7713b1edbc 395 __IO uint32_t DMAIntEn;
AnnaBridge 171:3a7713b1edbc 396 uint32_t RESERVED3[2];
AnnaBridge 171:3a7713b1edbc 397 __I uint32_t EoTIntSt;
AnnaBridge 171:3a7713b1edbc 398 __O uint32_t EoTIntClr;
AnnaBridge 171:3a7713b1edbc 399 __O uint32_t EoTIntSet;
AnnaBridge 171:3a7713b1edbc 400 __I uint32_t NDDRIntSt;
AnnaBridge 171:3a7713b1edbc 401 __O uint32_t NDDRIntClr;
AnnaBridge 171:3a7713b1edbc 402 __O uint32_t NDDRIntSet;
AnnaBridge 171:3a7713b1edbc 403 __I uint32_t SysErrIntSt;
AnnaBridge 171:3a7713b1edbc 404 __O uint32_t SysErrIntClr;
AnnaBridge 171:3a7713b1edbc 405 __O uint32_t SysErrIntSet;
AnnaBridge 171:3a7713b1edbc 406 uint32_t RESERVED4[15];
AnnaBridge 171:3a7713b1edbc 407
AnnaBridge 171:3a7713b1edbc 408 union {
AnnaBridge 171:3a7713b1edbc 409 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
AnnaBridge 171:3a7713b1edbc 410 __O uint32_t I2C_TX;
AnnaBridge 171:3a7713b1edbc 411 };
AnnaBridge 171:3a7713b1edbc 412 __IO uint32_t I2C_STS;
AnnaBridge 171:3a7713b1edbc 413 __IO uint32_t I2C_CTL;
AnnaBridge 171:3a7713b1edbc 414 __IO uint32_t I2C_CLKHI;
AnnaBridge 171:3a7713b1edbc 415 __O uint32_t I2C_CLKLO;
AnnaBridge 171:3a7713b1edbc 416 uint32_t RESERVED5[824];
AnnaBridge 171:3a7713b1edbc 417
AnnaBridge 171:3a7713b1edbc 418 union {
AnnaBridge 171:3a7713b1edbc 419 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
AnnaBridge 171:3a7713b1edbc 420 __IO uint32_t OTGClkCtrl;
AnnaBridge 171:3a7713b1edbc 421 };
AnnaBridge 171:3a7713b1edbc 422 union {
AnnaBridge 171:3a7713b1edbc 423 __I uint32_t USBClkSt;
AnnaBridge 171:3a7713b1edbc 424 __I uint32_t OTGClkSt;
AnnaBridge 171:3a7713b1edbc 425 };
AnnaBridge 171:3a7713b1edbc 426 } LPC_USB_TypeDef;
AnnaBridge 171:3a7713b1edbc 427
AnnaBridge 171:3a7713b1edbc 428 /*------------- CRC Engine (CRC) -----------------------------------------*/
AnnaBridge 171:3a7713b1edbc 429 typedef struct
AnnaBridge 171:3a7713b1edbc 430 {
AnnaBridge 171:3a7713b1edbc 431 __IO uint32_t MODE;
AnnaBridge 171:3a7713b1edbc 432 __IO uint32_t SEED;
AnnaBridge 171:3a7713b1edbc 433 union {
AnnaBridge 171:3a7713b1edbc 434 __I uint32_t SUM;
AnnaBridge 171:3a7713b1edbc 435 struct {
AnnaBridge 171:3a7713b1edbc 436 __O uint32_t DATA;
AnnaBridge 171:3a7713b1edbc 437 } WR_DATA_DWORD;
AnnaBridge 171:3a7713b1edbc 438
AnnaBridge 171:3a7713b1edbc 439 struct {
AnnaBridge 171:3a7713b1edbc 440 __O uint16_t DATA;
AnnaBridge 171:3a7713b1edbc 441 uint16_t RESERVED;
AnnaBridge 171:3a7713b1edbc 442 }WR_DATA_WORD;
AnnaBridge 171:3a7713b1edbc 443
AnnaBridge 171:3a7713b1edbc 444 struct {
AnnaBridge 171:3a7713b1edbc 445 __O uint8_t DATA;
AnnaBridge 171:3a7713b1edbc 446 uint8_t RESERVED[3];
AnnaBridge 171:3a7713b1edbc 447 }WR_DATA_BYTE;
AnnaBridge 171:3a7713b1edbc 448 };
AnnaBridge 171:3a7713b1edbc 449 } LPC_CRC_TypeDef;
AnnaBridge 171:3a7713b1edbc 450 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
AnnaBridge 171:3a7713b1edbc 451 typedef struct
AnnaBridge 171:3a7713b1edbc 452 {
AnnaBridge 171:3a7713b1edbc 453 __IO uint32_t DIR;
AnnaBridge 171:3a7713b1edbc 454 uint32_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 455 __IO uint32_t MASK;
AnnaBridge 171:3a7713b1edbc 456 __IO uint32_t PIN;
AnnaBridge 171:3a7713b1edbc 457 __IO uint32_t SET;
AnnaBridge 171:3a7713b1edbc 458 __O uint32_t CLR;
AnnaBridge 171:3a7713b1edbc 459 } LPC_GPIO_TypeDef;
AnnaBridge 171:3a7713b1edbc 460
AnnaBridge 171:3a7713b1edbc 461 typedef struct
AnnaBridge 171:3a7713b1edbc 462 {
AnnaBridge 171:3a7713b1edbc 463 __I uint32_t IntStatus;
AnnaBridge 171:3a7713b1edbc 464 __I uint32_t IO0IntStatR;
AnnaBridge 171:3a7713b1edbc 465 __I uint32_t IO0IntStatF;
AnnaBridge 171:3a7713b1edbc 466 __O uint32_t IO0IntClr;
AnnaBridge 171:3a7713b1edbc 467 __IO uint32_t IO0IntEnR;
AnnaBridge 171:3a7713b1edbc 468 __IO uint32_t IO0IntEnF;
AnnaBridge 171:3a7713b1edbc 469 uint32_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 470 __I uint32_t IO2IntStatR;
AnnaBridge 171:3a7713b1edbc 471 __I uint32_t IO2IntStatF;
AnnaBridge 171:3a7713b1edbc 472 __O uint32_t IO2IntClr;
AnnaBridge 171:3a7713b1edbc 473 __IO uint32_t IO2IntEnR;
AnnaBridge 171:3a7713b1edbc 474 __IO uint32_t IO2IntEnF;
AnnaBridge 171:3a7713b1edbc 475 } LPC_GPIOINT_TypeDef;
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 /*------------- External Memory Controller (EMC) -----------------------------*/
AnnaBridge 171:3a7713b1edbc 478 typedef struct
AnnaBridge 171:3a7713b1edbc 479 {
AnnaBridge 171:3a7713b1edbc 480 __IO uint32_t Control;
AnnaBridge 171:3a7713b1edbc 481 __I uint32_t Status;
AnnaBridge 171:3a7713b1edbc 482 __IO uint32_t Config;
AnnaBridge 171:3a7713b1edbc 483 uint32_t RESERVED0[5];
AnnaBridge 171:3a7713b1edbc 484 __IO uint32_t DynamicControl;
AnnaBridge 171:3a7713b1edbc 485 __IO uint32_t DynamicRefresh;
AnnaBridge 171:3a7713b1edbc 486 __IO uint32_t DynamicReadConfig;
AnnaBridge 171:3a7713b1edbc 487 uint32_t RESERVED1[1];
AnnaBridge 171:3a7713b1edbc 488 __IO uint32_t DynamicRP;
AnnaBridge 171:3a7713b1edbc 489 __IO uint32_t DynamicRAS;
AnnaBridge 171:3a7713b1edbc 490 __IO uint32_t DynamicSREX;
AnnaBridge 171:3a7713b1edbc 491 __IO uint32_t DynamicAPR;
AnnaBridge 171:3a7713b1edbc 492 __IO uint32_t DynamicDAL;
AnnaBridge 171:3a7713b1edbc 493 __IO uint32_t DynamicWR;
AnnaBridge 171:3a7713b1edbc 494 __IO uint32_t DynamicRC;
AnnaBridge 171:3a7713b1edbc 495 __IO uint32_t DynamicRFC;
AnnaBridge 171:3a7713b1edbc 496 __IO uint32_t DynamicXSR;
AnnaBridge 171:3a7713b1edbc 497 __IO uint32_t DynamicRRD;
AnnaBridge 171:3a7713b1edbc 498 __IO uint32_t DynamicMRD;
AnnaBridge 171:3a7713b1edbc 499 uint32_t RESERVED2[9];
AnnaBridge 171:3a7713b1edbc 500 __IO uint32_t StaticExtendedWait;
AnnaBridge 171:3a7713b1edbc 501 uint32_t RESERVED3[31];
AnnaBridge 171:3a7713b1edbc 502 __IO uint32_t DynamicConfig0;
AnnaBridge 171:3a7713b1edbc 503 __IO uint32_t DynamicRasCas0;
AnnaBridge 171:3a7713b1edbc 504 uint32_t RESERVED4[6];
AnnaBridge 171:3a7713b1edbc 505 __IO uint32_t DynamicConfig1;
AnnaBridge 171:3a7713b1edbc 506 __IO uint32_t DynamicRasCas1;
AnnaBridge 171:3a7713b1edbc 507 uint32_t RESERVED5[6];
AnnaBridge 171:3a7713b1edbc 508 __IO uint32_t DynamicConfig2;
AnnaBridge 171:3a7713b1edbc 509 __IO uint32_t DynamicRasCas2;
AnnaBridge 171:3a7713b1edbc 510 uint32_t RESERVED6[6];
AnnaBridge 171:3a7713b1edbc 511 __IO uint32_t DynamicConfig3;
AnnaBridge 171:3a7713b1edbc 512 __IO uint32_t DynamicRasCas3;
AnnaBridge 171:3a7713b1edbc 513 uint32_t RESERVED7[38];
AnnaBridge 171:3a7713b1edbc 514 __IO uint32_t StaticConfig0;
AnnaBridge 171:3a7713b1edbc 515 __IO uint32_t StaticWaitWen0;
AnnaBridge 171:3a7713b1edbc 516 __IO uint32_t StaticWaitOen0;
AnnaBridge 171:3a7713b1edbc 517 __IO uint32_t StaticWaitRd0;
AnnaBridge 171:3a7713b1edbc 518 __IO uint32_t StaticWaitPage0;
AnnaBridge 171:3a7713b1edbc 519 __IO uint32_t StaticWaitWr0;
AnnaBridge 171:3a7713b1edbc 520 __IO uint32_t StaticWaitTurn0;
AnnaBridge 171:3a7713b1edbc 521 uint32_t RESERVED8[1];
AnnaBridge 171:3a7713b1edbc 522 __IO uint32_t StaticConfig1;
AnnaBridge 171:3a7713b1edbc 523 __IO uint32_t StaticWaitWen1;
AnnaBridge 171:3a7713b1edbc 524 __IO uint32_t StaticWaitOen1;
AnnaBridge 171:3a7713b1edbc 525 __IO uint32_t StaticWaitRd1;
AnnaBridge 171:3a7713b1edbc 526 __IO uint32_t StaticWaitPage1;
AnnaBridge 171:3a7713b1edbc 527 __IO uint32_t StaticWaitWr1;
AnnaBridge 171:3a7713b1edbc 528 __IO uint32_t StaticWaitTurn1;
AnnaBridge 171:3a7713b1edbc 529 uint32_t RESERVED9[1];
AnnaBridge 171:3a7713b1edbc 530 __IO uint32_t StaticConfig2;
AnnaBridge 171:3a7713b1edbc 531 __IO uint32_t StaticWaitWen2;
AnnaBridge 171:3a7713b1edbc 532 __IO uint32_t StaticWaitOen2;
AnnaBridge 171:3a7713b1edbc 533 __IO uint32_t StaticWaitRd2;
AnnaBridge 171:3a7713b1edbc 534 __IO uint32_t StaticWaitPage2;
AnnaBridge 171:3a7713b1edbc 535 __IO uint32_t StaticWaitWr2;
AnnaBridge 171:3a7713b1edbc 536 __IO uint32_t StaticWaitTurn2;
AnnaBridge 171:3a7713b1edbc 537 uint32_t RESERVED10[1];
AnnaBridge 171:3a7713b1edbc 538 __IO uint32_t StaticConfig3;
AnnaBridge 171:3a7713b1edbc 539 __IO uint32_t StaticWaitWen3;
AnnaBridge 171:3a7713b1edbc 540 __IO uint32_t StaticWaitOen3;
AnnaBridge 171:3a7713b1edbc 541 __IO uint32_t StaticWaitRd3;
AnnaBridge 171:3a7713b1edbc 542 __IO uint32_t StaticWaitPage3;
AnnaBridge 171:3a7713b1edbc 543 __IO uint32_t StaticWaitWr3;
AnnaBridge 171:3a7713b1edbc 544 __IO uint32_t StaticWaitTurn3;
AnnaBridge 171:3a7713b1edbc 545 } LPC_EMC_TypeDef;
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
AnnaBridge 171:3a7713b1edbc 548 typedef struct
AnnaBridge 171:3a7713b1edbc 549 {
AnnaBridge 171:3a7713b1edbc 550 __IO uint8_t MOD;
AnnaBridge 171:3a7713b1edbc 551 uint8_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 552 __IO uint32_t TC;
AnnaBridge 171:3a7713b1edbc 553 __O uint8_t FEED;
AnnaBridge 171:3a7713b1edbc 554 uint8_t RESERVED1[3];
AnnaBridge 171:3a7713b1edbc 555 __I uint32_t TV;
AnnaBridge 171:3a7713b1edbc 556 uint32_t RESERVED2;
AnnaBridge 171:3a7713b1edbc 557 __IO uint32_t WARNINT;
AnnaBridge 171:3a7713b1edbc 558 __IO uint32_t WINDOW;
AnnaBridge 171:3a7713b1edbc 559 } LPC_WDT_TypeDef;
AnnaBridge 171:3a7713b1edbc 560
AnnaBridge 171:3a7713b1edbc 561 /*------------- Timer (TIM) --------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 562 typedef struct
AnnaBridge 171:3a7713b1edbc 563 {
AnnaBridge 171:3a7713b1edbc 564 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
AnnaBridge 171:3a7713b1edbc 565 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 566 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
AnnaBridge 171:3a7713b1edbc 567 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
AnnaBridge 171:3a7713b1edbc 568 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
AnnaBridge 171:3a7713b1edbc 569 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 570 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
AnnaBridge 171:3a7713b1edbc 571 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
AnnaBridge 171:3a7713b1edbc 572 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
AnnaBridge 171:3a7713b1edbc 573 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
AnnaBridge 171:3a7713b1edbc 574 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 575 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
AnnaBridge 171:3a7713b1edbc 576 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
AnnaBridge 171:3a7713b1edbc 577 uint32_t RESERVED0[2];
AnnaBridge 171:3a7713b1edbc 578 __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
AnnaBridge 171:3a7713b1edbc 579 uint32_t RESERVED1[12];
AnnaBridge 171:3a7713b1edbc 580 __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 581 } LPC_TIM_TypeDef;
AnnaBridge 171:3a7713b1edbc 582
AnnaBridge 171:3a7713b1edbc 583
AnnaBridge 171:3a7713b1edbc 584 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
AnnaBridge 171:3a7713b1edbc 585 typedef struct
AnnaBridge 171:3a7713b1edbc 586 {
AnnaBridge 171:3a7713b1edbc 587 __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
AnnaBridge 171:3a7713b1edbc 588 __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 589 __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
AnnaBridge 171:3a7713b1edbc 590 __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
AnnaBridge 171:3a7713b1edbc 591 __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
AnnaBridge 171:3a7713b1edbc 592 __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 593 __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
AnnaBridge 171:3a7713b1edbc 594 __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
AnnaBridge 171:3a7713b1edbc 595 __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
AnnaBridge 171:3a7713b1edbc 596 __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
AnnaBridge 171:3a7713b1edbc 597 __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 598 __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
AnnaBridge 171:3a7713b1edbc 599 __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */
AnnaBridge 171:3a7713b1edbc 600 __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */
AnnaBridge 171:3a7713b1edbc 601 __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */
AnnaBridge 171:3a7713b1edbc 602 uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 603 __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */
AnnaBridge 171:3a7713b1edbc 604 __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */
AnnaBridge 171:3a7713b1edbc 605 __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */
AnnaBridge 171:3a7713b1edbc 606 __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 607 __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */
AnnaBridge 171:3a7713b1edbc 608 uint32_t RESERVED1[7];
AnnaBridge 171:3a7713b1edbc 609 __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 610 } LPC_PWM_TypeDef;
AnnaBridge 171:3a7713b1edbc 611
AnnaBridge 171:3a7713b1edbc 612 /*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
AnnaBridge 171:3a7713b1edbc 613 /* There are three types of UARTs on the chip:
AnnaBridge 171:3a7713b1edbc 614 (1) UART0,UART2, and UART3 are the standard UART.
AnnaBridge 171:3a7713b1edbc 615 (2) UART1 is the standard with modem capability.
AnnaBridge 171:3a7713b1edbc 616 (3) USART(UART4) is the sync/async UART with smart card capability.
AnnaBridge 171:3a7713b1edbc 617 More details can be found on the Users Manual. */
AnnaBridge 171:3a7713b1edbc 618
AnnaBridge 171:3a7713b1edbc 619 #if 0
AnnaBridge 171:3a7713b1edbc 620 typedef struct
AnnaBridge 171:3a7713b1edbc 621 {
AnnaBridge 171:3a7713b1edbc 622 union {
AnnaBridge 171:3a7713b1edbc 623 __I uint8_t RBR;
AnnaBridge 171:3a7713b1edbc 624 __O uint8_t THR;
AnnaBridge 171:3a7713b1edbc 625 __IO uint8_t DLL;
AnnaBridge 171:3a7713b1edbc 626 uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 627 };
AnnaBridge 171:3a7713b1edbc 628 union {
AnnaBridge 171:3a7713b1edbc 629 __IO uint8_t DLM;
AnnaBridge 171:3a7713b1edbc 630 __IO uint32_t IER;
AnnaBridge 171:3a7713b1edbc 631 };
AnnaBridge 171:3a7713b1edbc 632 union {
AnnaBridge 171:3a7713b1edbc 633 __I uint32_t IIR;
AnnaBridge 171:3a7713b1edbc 634 __O uint8_t FCR;
AnnaBridge 171:3a7713b1edbc 635 };
AnnaBridge 171:3a7713b1edbc 636 __IO uint8_t LCR;
AnnaBridge 171:3a7713b1edbc 637 uint8_t RESERVED1[7];
AnnaBridge 171:3a7713b1edbc 638 __I uint8_t LSR;
AnnaBridge 171:3a7713b1edbc 639 uint8_t RESERVED2[7];
AnnaBridge 171:3a7713b1edbc 640 __IO uint8_t SCR;
AnnaBridge 171:3a7713b1edbc 641 uint8_t RESERVED3[3];
AnnaBridge 171:3a7713b1edbc 642 __IO uint32_t ACR;
AnnaBridge 171:3a7713b1edbc 643 __IO uint8_t ICR;
AnnaBridge 171:3a7713b1edbc 644 uint8_t RESERVED4[3];
AnnaBridge 171:3a7713b1edbc 645 __IO uint8_t FDR;
AnnaBridge 171:3a7713b1edbc 646 uint8_t RESERVED5[7];
AnnaBridge 171:3a7713b1edbc 647 __IO uint8_t TER;
AnnaBridge 171:3a7713b1edbc 648 uint8_t RESERVED6[39];
AnnaBridge 171:3a7713b1edbc 649 __I uint8_t FIFOLVL;
AnnaBridge 171:3a7713b1edbc 650 } LPC_UART_TypeDef;
AnnaBridge 171:3a7713b1edbc 651 #else
AnnaBridge 171:3a7713b1edbc 652 typedef struct
AnnaBridge 171:3a7713b1edbc 653 {
AnnaBridge 171:3a7713b1edbc 654 union
AnnaBridge 171:3a7713b1edbc 655 {
AnnaBridge 171:3a7713b1edbc 656 __I uint8_t RBR;
AnnaBridge 171:3a7713b1edbc 657 __O uint8_t THR;
AnnaBridge 171:3a7713b1edbc 658 __IO uint8_t DLL;
AnnaBridge 171:3a7713b1edbc 659 uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 660 };
AnnaBridge 171:3a7713b1edbc 661 union
AnnaBridge 171:3a7713b1edbc 662 {
AnnaBridge 171:3a7713b1edbc 663 __IO uint8_t DLM;
AnnaBridge 171:3a7713b1edbc 664 __IO uint32_t IER;
AnnaBridge 171:3a7713b1edbc 665 };
AnnaBridge 171:3a7713b1edbc 666 union
AnnaBridge 171:3a7713b1edbc 667 {
AnnaBridge 171:3a7713b1edbc 668 __I uint32_t IIR;
AnnaBridge 171:3a7713b1edbc 669 __O uint8_t FCR;
AnnaBridge 171:3a7713b1edbc 670 };
AnnaBridge 171:3a7713b1edbc 671 __IO uint8_t LCR;
AnnaBridge 171:3a7713b1edbc 672 uint8_t RESERVED1[7];//Reserved
AnnaBridge 171:3a7713b1edbc 673 __I uint8_t LSR;
AnnaBridge 171:3a7713b1edbc 674 uint8_t RESERVED2[7];//Reserved
AnnaBridge 171:3a7713b1edbc 675 __IO uint8_t SCR;
AnnaBridge 171:3a7713b1edbc 676 uint8_t RESERVED3[3];//Reserved
AnnaBridge 171:3a7713b1edbc 677 __IO uint32_t ACR;
AnnaBridge 171:3a7713b1edbc 678 __IO uint8_t ICR;
AnnaBridge 171:3a7713b1edbc 679 uint8_t RESERVED4[3];//Reserved
AnnaBridge 171:3a7713b1edbc 680 __IO uint8_t FDR;
AnnaBridge 171:3a7713b1edbc 681 uint8_t RESERVED5[7];//Reserved
AnnaBridge 171:3a7713b1edbc 682 __IO uint8_t TER;
AnnaBridge 171:3a7713b1edbc 683 uint8_t RESERVED8[27];//Reserved
AnnaBridge 171:3a7713b1edbc 684 __IO uint8_t RS485CTRL;
AnnaBridge 171:3a7713b1edbc 685 uint8_t RESERVED9[3];//Reserved
AnnaBridge 171:3a7713b1edbc 686 __IO uint8_t ADRMATCH;
AnnaBridge 171:3a7713b1edbc 687 uint8_t RESERVED10[3];//Reserved
AnnaBridge 171:3a7713b1edbc 688 __IO uint8_t RS485DLY;
AnnaBridge 171:3a7713b1edbc 689 uint8_t RESERVED11[3];//Reserved
AnnaBridge 171:3a7713b1edbc 690 __I uint8_t FIFOLVL;
AnnaBridge 171:3a7713b1edbc 691 }LPC_UART_TypeDef;
AnnaBridge 171:3a7713b1edbc 692 #endif
AnnaBridge 171:3a7713b1edbc 693
AnnaBridge 171:3a7713b1edbc 694
AnnaBridge 171:3a7713b1edbc 695 typedef struct
AnnaBridge 171:3a7713b1edbc 696 {
AnnaBridge 171:3a7713b1edbc 697 union {
AnnaBridge 171:3a7713b1edbc 698 __I uint8_t RBR;
AnnaBridge 171:3a7713b1edbc 699 __O uint8_t THR;
AnnaBridge 171:3a7713b1edbc 700 __IO uint8_t DLL;
AnnaBridge 171:3a7713b1edbc 701 uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 702 };
AnnaBridge 171:3a7713b1edbc 703 union {
AnnaBridge 171:3a7713b1edbc 704 __IO uint8_t DLM;
AnnaBridge 171:3a7713b1edbc 705 __IO uint32_t IER;
AnnaBridge 171:3a7713b1edbc 706 };
AnnaBridge 171:3a7713b1edbc 707 union {
AnnaBridge 171:3a7713b1edbc 708 __I uint32_t IIR;
AnnaBridge 171:3a7713b1edbc 709 __O uint8_t FCR;
AnnaBridge 171:3a7713b1edbc 710 };
AnnaBridge 171:3a7713b1edbc 711 __IO uint8_t LCR;
AnnaBridge 171:3a7713b1edbc 712 uint8_t RESERVED1[3];
AnnaBridge 171:3a7713b1edbc 713 __IO uint8_t MCR;
AnnaBridge 171:3a7713b1edbc 714 uint8_t RESERVED2[3];
AnnaBridge 171:3a7713b1edbc 715 __I uint8_t LSR;
AnnaBridge 171:3a7713b1edbc 716 uint8_t RESERVED3[3];
AnnaBridge 171:3a7713b1edbc 717 __I uint8_t MSR;
AnnaBridge 171:3a7713b1edbc 718 uint8_t RESERVED4[3];
AnnaBridge 171:3a7713b1edbc 719 __IO uint8_t SCR;
AnnaBridge 171:3a7713b1edbc 720 uint8_t RESERVED5[3];
AnnaBridge 171:3a7713b1edbc 721 __IO uint32_t ACR;
AnnaBridge 171:3a7713b1edbc 722 uint32_t RESERVED6;
AnnaBridge 171:3a7713b1edbc 723 __IO uint32_t FDR;
AnnaBridge 171:3a7713b1edbc 724 uint32_t RESERVED7;
AnnaBridge 171:3a7713b1edbc 725 __IO uint8_t TER;
AnnaBridge 171:3a7713b1edbc 726 uint8_t RESERVED8[27];
AnnaBridge 171:3a7713b1edbc 727 __IO uint8_t RS485CTRL;
AnnaBridge 171:3a7713b1edbc 728 uint8_t RESERVED9[3];
AnnaBridge 171:3a7713b1edbc 729 __IO uint8_t ADRMATCH;
AnnaBridge 171:3a7713b1edbc 730 uint8_t RESERVED10[3];
AnnaBridge 171:3a7713b1edbc 731 __IO uint8_t RS485DLY;
AnnaBridge 171:3a7713b1edbc 732 uint8_t RESERVED11[3];
AnnaBridge 171:3a7713b1edbc 733 __I uint8_t FIFOLVL;
AnnaBridge 171:3a7713b1edbc 734 } LPC_UART1_TypeDef;
AnnaBridge 171:3a7713b1edbc 735
AnnaBridge 171:3a7713b1edbc 736 typedef struct
AnnaBridge 171:3a7713b1edbc 737 {
AnnaBridge 171:3a7713b1edbc 738 union {
AnnaBridge 171:3a7713b1edbc 739 __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
AnnaBridge 171:3a7713b1edbc 740 __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
AnnaBridge 171:3a7713b1edbc 741 __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
AnnaBridge 171:3a7713b1edbc 742 };
AnnaBridge 171:3a7713b1edbc 743 union {
AnnaBridge 171:3a7713b1edbc 744 __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
AnnaBridge 171:3a7713b1edbc 745 __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
AnnaBridge 171:3a7713b1edbc 746 };
AnnaBridge 171:3a7713b1edbc 747 union {
AnnaBridge 171:3a7713b1edbc 748 __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
AnnaBridge 171:3a7713b1edbc 749 __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
AnnaBridge 171:3a7713b1edbc 750 };
AnnaBridge 171:3a7713b1edbc 751 __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 752 __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 753 __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
AnnaBridge 171:3a7713b1edbc 754 __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
AnnaBridge 171:3a7713b1edbc 755 __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
AnnaBridge 171:3a7713b1edbc 756 __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 757 __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 758 __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
AnnaBridge 171:3a7713b1edbc 759 __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */
AnnaBridge 171:3a7713b1edbc 760 __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */
AnnaBridge 171:3a7713b1edbc 761 __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */
AnnaBridge 171:3a7713b1edbc 762 uint32_t RESERVED0[2];
AnnaBridge 171:3a7713b1edbc 763 __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */
AnnaBridge 171:3a7713b1edbc 764 uint32_t RESERVED1;
AnnaBridge 171:3a7713b1edbc 765 __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 766 __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 767 __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
AnnaBridge 171:3a7713b1edbc 768 __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
AnnaBridge 171:3a7713b1edbc 769 __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */
AnnaBridge 171:3a7713b1edbc 770 __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */
AnnaBridge 171:3a7713b1edbc 771 uint32_t RESERVED2[989];
AnnaBridge 171:3a7713b1edbc 772 __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */
AnnaBridge 171:3a7713b1edbc 773 __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */
AnnaBridge 171:3a7713b1edbc 774 __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */
AnnaBridge 171:3a7713b1edbc 775 __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */
AnnaBridge 171:3a7713b1edbc 776 __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */
AnnaBridge 171:3a7713b1edbc 777 __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */
AnnaBridge 171:3a7713b1edbc 778 __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */
AnnaBridge 171:3a7713b1edbc 779 uint32_t RESERVED3[3];
AnnaBridge 171:3a7713b1edbc 780 __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */
AnnaBridge 171:3a7713b1edbc 781 } LPC_UART4_TypeDef;
AnnaBridge 171:3a7713b1edbc 782 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
AnnaBridge 171:3a7713b1edbc 783 typedef struct
AnnaBridge 171:3a7713b1edbc 784 {
AnnaBridge 171:3a7713b1edbc 785 __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
AnnaBridge 171:3a7713b1edbc 786 __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
AnnaBridge 171:3a7713b1edbc 787 __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
AnnaBridge 171:3a7713b1edbc 788 __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
AnnaBridge 171:3a7713b1edbc 789 __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
AnnaBridge 171:3a7713b1edbc 790 __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
AnnaBridge 171:3a7713b1edbc 791 __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
AnnaBridge 171:3a7713b1edbc 792 __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
AnnaBridge 171:3a7713b1edbc 793 __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
AnnaBridge 171:3a7713b1edbc 794 __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
AnnaBridge 171:3a7713b1edbc 795 __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
AnnaBridge 171:3a7713b1edbc 796 __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
AnnaBridge 171:3a7713b1edbc 797 __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
AnnaBridge 171:3a7713b1edbc 798 __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
AnnaBridge 171:3a7713b1edbc 799 __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
AnnaBridge 171:3a7713b1edbc 800 __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
AnnaBridge 171:3a7713b1edbc 801 } LPC_I2C_TypeDef;
AnnaBridge 171:3a7713b1edbc 802
AnnaBridge 171:3a7713b1edbc 803 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
AnnaBridge 171:3a7713b1edbc 804 typedef struct
AnnaBridge 171:3a7713b1edbc 805 {
AnnaBridge 171:3a7713b1edbc 806 __IO uint8_t ILR;
AnnaBridge 171:3a7713b1edbc 807 uint8_t RESERVED0[7];
AnnaBridge 171:3a7713b1edbc 808 __IO uint8_t CCR;
AnnaBridge 171:3a7713b1edbc 809 uint8_t RESERVED1[3];
AnnaBridge 171:3a7713b1edbc 810 __IO uint8_t CIIR;
AnnaBridge 171:3a7713b1edbc 811 uint8_t RESERVED2[3];
AnnaBridge 171:3a7713b1edbc 812 __IO uint8_t AMR;
AnnaBridge 171:3a7713b1edbc 813 uint8_t RESERVED3[3];
AnnaBridge 171:3a7713b1edbc 814 __I uint32_t CTIME0;
AnnaBridge 171:3a7713b1edbc 815 __I uint32_t CTIME1;
AnnaBridge 171:3a7713b1edbc 816 __I uint32_t CTIME2;
AnnaBridge 171:3a7713b1edbc 817 __IO uint8_t SEC;
AnnaBridge 171:3a7713b1edbc 818 uint8_t RESERVED4[3];
AnnaBridge 171:3a7713b1edbc 819 __IO uint8_t MIN;
AnnaBridge 171:3a7713b1edbc 820 uint8_t RESERVED5[3];
AnnaBridge 171:3a7713b1edbc 821 __IO uint8_t HOUR;
AnnaBridge 171:3a7713b1edbc 822 uint8_t RESERVED6[3];
AnnaBridge 171:3a7713b1edbc 823 __IO uint8_t DOM;
AnnaBridge 171:3a7713b1edbc 824 uint8_t RESERVED7[3];
AnnaBridge 171:3a7713b1edbc 825 __IO uint8_t DOW;
AnnaBridge 171:3a7713b1edbc 826 uint8_t RESERVED8[3];
AnnaBridge 171:3a7713b1edbc 827 __IO uint16_t DOY;
AnnaBridge 171:3a7713b1edbc 828 uint16_t RESERVED9;
AnnaBridge 171:3a7713b1edbc 829 __IO uint8_t MONTH;
AnnaBridge 171:3a7713b1edbc 830 uint8_t RESERVED10[3];
AnnaBridge 171:3a7713b1edbc 831 __IO uint16_t YEAR;
AnnaBridge 171:3a7713b1edbc 832 uint16_t RESERVED11;
AnnaBridge 171:3a7713b1edbc 833 __IO uint32_t CALIBRATION;
AnnaBridge 171:3a7713b1edbc 834 __IO uint32_t GPREG0;
AnnaBridge 171:3a7713b1edbc 835 __IO uint32_t GPREG1;
AnnaBridge 171:3a7713b1edbc 836 __IO uint32_t GPREG2;
AnnaBridge 171:3a7713b1edbc 837 __IO uint32_t GPREG3;
AnnaBridge 171:3a7713b1edbc 838 __IO uint32_t GPREG4;
AnnaBridge 171:3a7713b1edbc 839 __IO uint8_t RTC_AUXEN;
AnnaBridge 171:3a7713b1edbc 840 uint8_t RESERVED12[3];
AnnaBridge 171:3a7713b1edbc 841 __IO uint8_t RTC_AUX;
AnnaBridge 171:3a7713b1edbc 842 uint8_t RESERVED13[3];
AnnaBridge 171:3a7713b1edbc 843 __IO uint8_t ALSEC;
AnnaBridge 171:3a7713b1edbc 844 uint8_t RESERVED14[3];
AnnaBridge 171:3a7713b1edbc 845 __IO uint8_t ALMIN;
AnnaBridge 171:3a7713b1edbc 846 uint8_t RESERVED15[3];
AnnaBridge 171:3a7713b1edbc 847 __IO uint8_t ALHOUR;
AnnaBridge 171:3a7713b1edbc 848 uint8_t RESERVED16[3];
AnnaBridge 171:3a7713b1edbc 849 __IO uint8_t ALDOM;
AnnaBridge 171:3a7713b1edbc 850 uint8_t RESERVED17[3];
AnnaBridge 171:3a7713b1edbc 851 __IO uint8_t ALDOW;
AnnaBridge 171:3a7713b1edbc 852 uint8_t RESERVED18[3];
AnnaBridge 171:3a7713b1edbc 853 __IO uint16_t ALDOY;
AnnaBridge 171:3a7713b1edbc 854 uint16_t RESERVED19;
AnnaBridge 171:3a7713b1edbc 855 __IO uint8_t ALMON;
AnnaBridge 171:3a7713b1edbc 856 uint8_t RESERVED20[3];
AnnaBridge 171:3a7713b1edbc 857 __IO uint16_t ALYEAR;
AnnaBridge 171:3a7713b1edbc 858 uint16_t RESERVED21;
AnnaBridge 171:3a7713b1edbc 859 __IO uint32_t ERSTATUS;
AnnaBridge 171:3a7713b1edbc 860 __IO uint32_t ERCONTROL;
AnnaBridge 171:3a7713b1edbc 861 __IO uint32_t ERCOUNTERS;
AnnaBridge 171:3a7713b1edbc 862 uint32_t RESERVED22;
AnnaBridge 171:3a7713b1edbc 863 __IO uint32_t ERFIRSTSTAMP0;
AnnaBridge 171:3a7713b1edbc 864 __IO uint32_t ERFIRSTSTAMP1;
AnnaBridge 171:3a7713b1edbc 865 __IO uint32_t ERFIRSTSTAMP2;
AnnaBridge 171:3a7713b1edbc 866 uint32_t RESERVED23;
AnnaBridge 171:3a7713b1edbc 867 __IO uint32_t ERLASTSTAMP0;
AnnaBridge 171:3a7713b1edbc 868 __IO uint32_t ERLASTSTAMP1;
AnnaBridge 171:3a7713b1edbc 869 __IO uint32_t ERLASTSTAMP2;
AnnaBridge 171:3a7713b1edbc 870 } LPC_RTC_TypeDef;
AnnaBridge 171:3a7713b1edbc 871
AnnaBridge 171:3a7713b1edbc 872
AnnaBridge 171:3a7713b1edbc 873
AnnaBridge 171:3a7713b1edbc 874 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
AnnaBridge 171:3a7713b1edbc 875 typedef struct
AnnaBridge 171:3a7713b1edbc 876 {
AnnaBridge 171:3a7713b1edbc 877 __IO uint32_t P0_0; /* 0x000 */
AnnaBridge 171:3a7713b1edbc 878 __IO uint32_t P0_1;
AnnaBridge 171:3a7713b1edbc 879 __IO uint32_t P0_2;
AnnaBridge 171:3a7713b1edbc 880 __IO uint32_t P0_3;
AnnaBridge 171:3a7713b1edbc 881 __IO uint32_t P0_4;
AnnaBridge 171:3a7713b1edbc 882 __IO uint32_t P0_5;
AnnaBridge 171:3a7713b1edbc 883 __IO uint32_t P0_6;
AnnaBridge 171:3a7713b1edbc 884 __IO uint32_t P0_7;
AnnaBridge 171:3a7713b1edbc 885
AnnaBridge 171:3a7713b1edbc 886 __IO uint32_t P0_8; /* 0x020 */
AnnaBridge 171:3a7713b1edbc 887 __IO uint32_t P0_9;
AnnaBridge 171:3a7713b1edbc 888 __IO uint32_t P0_10;
AnnaBridge 171:3a7713b1edbc 889 __IO uint32_t P0_11;
AnnaBridge 171:3a7713b1edbc 890 __IO uint32_t P0_12;
AnnaBridge 171:3a7713b1edbc 891 __IO uint32_t P0_13;
AnnaBridge 171:3a7713b1edbc 892 __IO uint32_t P0_14;
AnnaBridge 171:3a7713b1edbc 893 __IO uint32_t P0_15;
AnnaBridge 171:3a7713b1edbc 894
AnnaBridge 171:3a7713b1edbc 895 __IO uint32_t P0_16; /* 0x040 */
AnnaBridge 171:3a7713b1edbc 896 __IO uint32_t P0_17;
AnnaBridge 171:3a7713b1edbc 897 __IO uint32_t P0_18;
AnnaBridge 171:3a7713b1edbc 898 __IO uint32_t P0_19;
AnnaBridge 171:3a7713b1edbc 899 __IO uint32_t P0_20;
AnnaBridge 171:3a7713b1edbc 900 __IO uint32_t P0_21;
AnnaBridge 171:3a7713b1edbc 901 __IO uint32_t P0_22;
AnnaBridge 171:3a7713b1edbc 902 __IO uint32_t P0_23;
AnnaBridge 171:3a7713b1edbc 903
AnnaBridge 171:3a7713b1edbc 904 __IO uint32_t P0_24; /* 0x060 */
AnnaBridge 171:3a7713b1edbc 905 __IO uint32_t P0_25;
AnnaBridge 171:3a7713b1edbc 906 __IO uint32_t P0_26;
AnnaBridge 171:3a7713b1edbc 907 __IO uint32_t P0_27;
AnnaBridge 171:3a7713b1edbc 908 __IO uint32_t P0_28;
AnnaBridge 171:3a7713b1edbc 909 __IO uint32_t P0_29;
AnnaBridge 171:3a7713b1edbc 910 __IO uint32_t P0_30;
AnnaBridge 171:3a7713b1edbc 911 __IO uint32_t P0_31;
AnnaBridge 171:3a7713b1edbc 912
AnnaBridge 171:3a7713b1edbc 913 __IO uint32_t P1_0; /* 0x080 */
AnnaBridge 171:3a7713b1edbc 914 __IO uint32_t P1_1;
AnnaBridge 171:3a7713b1edbc 915 __IO uint32_t P1_2;
AnnaBridge 171:3a7713b1edbc 916 __IO uint32_t P1_3;
AnnaBridge 171:3a7713b1edbc 917 __IO uint32_t P1_4;
AnnaBridge 171:3a7713b1edbc 918 __IO uint32_t P1_5;
AnnaBridge 171:3a7713b1edbc 919 __IO uint32_t P1_6;
AnnaBridge 171:3a7713b1edbc 920 __IO uint32_t P1_7;
AnnaBridge 171:3a7713b1edbc 921
AnnaBridge 171:3a7713b1edbc 922 __IO uint32_t P1_8; /* 0x0A0 */
AnnaBridge 171:3a7713b1edbc 923 __IO uint32_t P1_9;
AnnaBridge 171:3a7713b1edbc 924 __IO uint32_t P1_10;
AnnaBridge 171:3a7713b1edbc 925 __IO uint32_t P1_11;
AnnaBridge 171:3a7713b1edbc 926 __IO uint32_t P1_12;
AnnaBridge 171:3a7713b1edbc 927 __IO uint32_t P1_13;
AnnaBridge 171:3a7713b1edbc 928 __IO uint32_t P1_14;
AnnaBridge 171:3a7713b1edbc 929 __IO uint32_t P1_15;
AnnaBridge 171:3a7713b1edbc 930
AnnaBridge 171:3a7713b1edbc 931 __IO uint32_t P1_16; /* 0x0C0 */
AnnaBridge 171:3a7713b1edbc 932 __IO uint32_t P1_17;
AnnaBridge 171:3a7713b1edbc 933 __IO uint32_t P1_18;
AnnaBridge 171:3a7713b1edbc 934 __IO uint32_t P1_19;
AnnaBridge 171:3a7713b1edbc 935 __IO uint32_t P1_20;
AnnaBridge 171:3a7713b1edbc 936 __IO uint32_t P1_21;
AnnaBridge 171:3a7713b1edbc 937 __IO uint32_t P1_22;
AnnaBridge 171:3a7713b1edbc 938 __IO uint32_t P1_23;
AnnaBridge 171:3a7713b1edbc 939
AnnaBridge 171:3a7713b1edbc 940 __IO uint32_t P1_24; /* 0x0E0 */
AnnaBridge 171:3a7713b1edbc 941 __IO uint32_t P1_25;
AnnaBridge 171:3a7713b1edbc 942 __IO uint32_t P1_26;
AnnaBridge 171:3a7713b1edbc 943 __IO uint32_t P1_27;
AnnaBridge 171:3a7713b1edbc 944 __IO uint32_t P1_28;
AnnaBridge 171:3a7713b1edbc 945 __IO uint32_t P1_29;
AnnaBridge 171:3a7713b1edbc 946 __IO uint32_t P1_30;
AnnaBridge 171:3a7713b1edbc 947 __IO uint32_t P1_31;
AnnaBridge 171:3a7713b1edbc 948
AnnaBridge 171:3a7713b1edbc 949 __IO uint32_t P2_0; /* 0x100 */
AnnaBridge 171:3a7713b1edbc 950 __IO uint32_t P2_1;
AnnaBridge 171:3a7713b1edbc 951 __IO uint32_t P2_2;
AnnaBridge 171:3a7713b1edbc 952 __IO uint32_t P2_3;
AnnaBridge 171:3a7713b1edbc 953 __IO uint32_t P2_4;
AnnaBridge 171:3a7713b1edbc 954 __IO uint32_t P2_5;
AnnaBridge 171:3a7713b1edbc 955 __IO uint32_t P2_6;
AnnaBridge 171:3a7713b1edbc 956 __IO uint32_t P2_7;
AnnaBridge 171:3a7713b1edbc 957
AnnaBridge 171:3a7713b1edbc 958 __IO uint32_t P2_8; /* 0x120 */
AnnaBridge 171:3a7713b1edbc 959 __IO uint32_t P2_9;
AnnaBridge 171:3a7713b1edbc 960 __IO uint32_t P2_10;
AnnaBridge 171:3a7713b1edbc 961 __IO uint32_t P2_11;
AnnaBridge 171:3a7713b1edbc 962 __IO uint32_t P2_12;
AnnaBridge 171:3a7713b1edbc 963 __IO uint32_t P2_13;
AnnaBridge 171:3a7713b1edbc 964 __IO uint32_t P2_14;
AnnaBridge 171:3a7713b1edbc 965 __IO uint32_t P2_15;
AnnaBridge 171:3a7713b1edbc 966
AnnaBridge 171:3a7713b1edbc 967 __IO uint32_t P2_16; /* 0x140 */
AnnaBridge 171:3a7713b1edbc 968 __IO uint32_t P2_17;
AnnaBridge 171:3a7713b1edbc 969 __IO uint32_t P2_18;
AnnaBridge 171:3a7713b1edbc 970 __IO uint32_t P2_19;
AnnaBridge 171:3a7713b1edbc 971 __IO uint32_t P2_20;
AnnaBridge 171:3a7713b1edbc 972 __IO uint32_t P2_21;
AnnaBridge 171:3a7713b1edbc 973 __IO uint32_t P2_22;
AnnaBridge 171:3a7713b1edbc 974 __IO uint32_t P2_23;
AnnaBridge 171:3a7713b1edbc 975
AnnaBridge 171:3a7713b1edbc 976 __IO uint32_t P2_24; /* 0x160 */
AnnaBridge 171:3a7713b1edbc 977 __IO uint32_t P2_25;
AnnaBridge 171:3a7713b1edbc 978 __IO uint32_t P2_26;
AnnaBridge 171:3a7713b1edbc 979 __IO uint32_t P2_27;
AnnaBridge 171:3a7713b1edbc 980 __IO uint32_t P2_28;
AnnaBridge 171:3a7713b1edbc 981 __IO uint32_t P2_29;
AnnaBridge 171:3a7713b1edbc 982 __IO uint32_t P2_30;
AnnaBridge 171:3a7713b1edbc 983 __IO uint32_t P2_31;
AnnaBridge 171:3a7713b1edbc 984
AnnaBridge 171:3a7713b1edbc 985 __IO uint32_t P3_0; /* 0x180 */
AnnaBridge 171:3a7713b1edbc 986 __IO uint32_t P3_1;
AnnaBridge 171:3a7713b1edbc 987 __IO uint32_t P3_2;
AnnaBridge 171:3a7713b1edbc 988 __IO uint32_t P3_3;
AnnaBridge 171:3a7713b1edbc 989 __IO uint32_t P3_4;
AnnaBridge 171:3a7713b1edbc 990 __IO uint32_t P3_5;
AnnaBridge 171:3a7713b1edbc 991 __IO uint32_t P3_6;
AnnaBridge 171:3a7713b1edbc 992 __IO uint32_t P3_7;
AnnaBridge 171:3a7713b1edbc 993
AnnaBridge 171:3a7713b1edbc 994 __IO uint32_t P3_8; /* 0x1A0 */
AnnaBridge 171:3a7713b1edbc 995 __IO uint32_t P3_9;
AnnaBridge 171:3a7713b1edbc 996 __IO uint32_t P3_10;
AnnaBridge 171:3a7713b1edbc 997 __IO uint32_t P3_11;
AnnaBridge 171:3a7713b1edbc 998 __IO uint32_t P3_12;
AnnaBridge 171:3a7713b1edbc 999 __IO uint32_t P3_13;
AnnaBridge 171:3a7713b1edbc 1000 __IO uint32_t P3_14;
AnnaBridge 171:3a7713b1edbc 1001 __IO uint32_t P3_15;
AnnaBridge 171:3a7713b1edbc 1002
AnnaBridge 171:3a7713b1edbc 1003 __IO uint32_t P3_16; /* 0x1C0 */
AnnaBridge 171:3a7713b1edbc 1004 __IO uint32_t P3_17;
AnnaBridge 171:3a7713b1edbc 1005 __IO uint32_t P3_18;
AnnaBridge 171:3a7713b1edbc 1006 __IO uint32_t P3_19;
AnnaBridge 171:3a7713b1edbc 1007 __IO uint32_t P3_20;
AnnaBridge 171:3a7713b1edbc 1008 __IO uint32_t P3_21;
AnnaBridge 171:3a7713b1edbc 1009 __IO uint32_t P3_22;
AnnaBridge 171:3a7713b1edbc 1010 __IO uint32_t P3_23;
AnnaBridge 171:3a7713b1edbc 1011
AnnaBridge 171:3a7713b1edbc 1012 __IO uint32_t P3_24; /* 0x1E0 */
AnnaBridge 171:3a7713b1edbc 1013 __IO uint32_t P3_25;
AnnaBridge 171:3a7713b1edbc 1014 __IO uint32_t P3_26;
AnnaBridge 171:3a7713b1edbc 1015 __IO uint32_t P3_27;
AnnaBridge 171:3a7713b1edbc 1016 __IO uint32_t P3_28;
AnnaBridge 171:3a7713b1edbc 1017 __IO uint32_t P3_29;
AnnaBridge 171:3a7713b1edbc 1018 __IO uint32_t P3_30;
AnnaBridge 171:3a7713b1edbc 1019 __IO uint32_t P3_31;
AnnaBridge 171:3a7713b1edbc 1020
AnnaBridge 171:3a7713b1edbc 1021 __IO uint32_t P4_0; /* 0x200 */
AnnaBridge 171:3a7713b1edbc 1022 __IO uint32_t P4_1;
AnnaBridge 171:3a7713b1edbc 1023 __IO uint32_t P4_2;
AnnaBridge 171:3a7713b1edbc 1024 __IO uint32_t P4_3;
AnnaBridge 171:3a7713b1edbc 1025 __IO uint32_t P4_4;
AnnaBridge 171:3a7713b1edbc 1026 __IO uint32_t P4_5;
AnnaBridge 171:3a7713b1edbc 1027 __IO uint32_t P4_6;
AnnaBridge 171:3a7713b1edbc 1028 __IO uint32_t P4_7;
AnnaBridge 171:3a7713b1edbc 1029
AnnaBridge 171:3a7713b1edbc 1030 __IO uint32_t P4_8; /* 0x220 */
AnnaBridge 171:3a7713b1edbc 1031 __IO uint32_t P4_9;
AnnaBridge 171:3a7713b1edbc 1032 __IO uint32_t P4_10;
AnnaBridge 171:3a7713b1edbc 1033 __IO uint32_t P4_11;
AnnaBridge 171:3a7713b1edbc 1034 __IO uint32_t P4_12;
AnnaBridge 171:3a7713b1edbc 1035 __IO uint32_t P4_13;
AnnaBridge 171:3a7713b1edbc 1036 __IO uint32_t P4_14;
AnnaBridge 171:3a7713b1edbc 1037 __IO uint32_t P4_15;
AnnaBridge 171:3a7713b1edbc 1038
AnnaBridge 171:3a7713b1edbc 1039 __IO uint32_t P4_16; /* 0x240 */
AnnaBridge 171:3a7713b1edbc 1040 __IO uint32_t P4_17;
AnnaBridge 171:3a7713b1edbc 1041 __IO uint32_t P4_18;
AnnaBridge 171:3a7713b1edbc 1042 __IO uint32_t P4_19;
AnnaBridge 171:3a7713b1edbc 1043 __IO uint32_t P4_20;
AnnaBridge 171:3a7713b1edbc 1044 __IO uint32_t P4_21;
AnnaBridge 171:3a7713b1edbc 1045 __IO uint32_t P4_22;
AnnaBridge 171:3a7713b1edbc 1046 __IO uint32_t P4_23;
AnnaBridge 171:3a7713b1edbc 1047
AnnaBridge 171:3a7713b1edbc 1048 __IO uint32_t P4_24; /* 0x260 */
AnnaBridge 171:3a7713b1edbc 1049 __IO uint32_t P4_25;
AnnaBridge 171:3a7713b1edbc 1050 __IO uint32_t P4_26;
AnnaBridge 171:3a7713b1edbc 1051 __IO uint32_t P4_27;
AnnaBridge 171:3a7713b1edbc 1052 __IO uint32_t P4_28;
AnnaBridge 171:3a7713b1edbc 1053 __IO uint32_t P4_29;
AnnaBridge 171:3a7713b1edbc 1054 __IO uint32_t P4_30;
AnnaBridge 171:3a7713b1edbc 1055 __IO uint32_t P4_31;
AnnaBridge 171:3a7713b1edbc 1056
AnnaBridge 171:3a7713b1edbc 1057 __IO uint32_t P5_0; /* 0x280 */
AnnaBridge 171:3a7713b1edbc 1058 __IO uint32_t P5_1;
AnnaBridge 171:3a7713b1edbc 1059 __IO uint32_t P5_2;
AnnaBridge 171:3a7713b1edbc 1060 __IO uint32_t P5_3;
AnnaBridge 171:3a7713b1edbc 1061 __IO uint32_t P5_4; /* 0x290 */
AnnaBridge 171:3a7713b1edbc 1062 } LPC_IOCON_TypeDef;
AnnaBridge 171:3a7713b1edbc 1063
AnnaBridge 171:3a7713b1edbc 1064
AnnaBridge 171:3a7713b1edbc 1065
AnnaBridge 171:3a7713b1edbc 1066
AnnaBridge 171:3a7713b1edbc 1067
AnnaBridge 171:3a7713b1edbc 1068
AnnaBridge 171:3a7713b1edbc 1069 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
AnnaBridge 171:3a7713b1edbc 1070 typedef struct
AnnaBridge 171:3a7713b1edbc 1071 {
AnnaBridge 171:3a7713b1edbc 1072 __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
AnnaBridge 171:3a7713b1edbc 1073 __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
AnnaBridge 171:3a7713b1edbc 1074 __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
AnnaBridge 171:3a7713b1edbc 1075 __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
AnnaBridge 171:3a7713b1edbc 1076 __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
AnnaBridge 171:3a7713b1edbc 1077 __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
AnnaBridge 171:3a7713b1edbc 1078 __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
AnnaBridge 171:3a7713b1edbc 1079 __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
AnnaBridge 171:3a7713b1edbc 1080 __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
AnnaBridge 171:3a7713b1edbc 1081 __IO uint32_t DMACR;
AnnaBridge 171:3a7713b1edbc 1082 } LPC_SSP_TypeDef;
AnnaBridge 171:3a7713b1edbc 1083
AnnaBridge 171:3a7713b1edbc 1084 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
AnnaBridge 171:3a7713b1edbc 1085 typedef struct
AnnaBridge 171:3a7713b1edbc 1086 {
AnnaBridge 171:3a7713b1edbc 1087 __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
AnnaBridge 171:3a7713b1edbc 1088 __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
AnnaBridge 171:3a7713b1edbc 1089 uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 1090 __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
AnnaBridge 171:3a7713b1edbc 1091 __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
AnnaBridge 171:3a7713b1edbc 1092 __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
AnnaBridge 171:3a7713b1edbc 1093 __IO uint32_t ADTRM;
AnnaBridge 171:3a7713b1edbc 1094 } LPC_ADC_TypeDef;
AnnaBridge 171:3a7713b1edbc 1095
AnnaBridge 171:3a7713b1edbc 1096 /*------------- Controller Area Network (CAN) --------------------------------*/
AnnaBridge 171:3a7713b1edbc 1097 typedef struct
AnnaBridge 171:3a7713b1edbc 1098 {
AnnaBridge 171:3a7713b1edbc 1099 __IO uint32_t mask[512]; /* ID Masks */
AnnaBridge 171:3a7713b1edbc 1100 } LPC_CANAF_RAM_TypeDef;
AnnaBridge 171:3a7713b1edbc 1101
AnnaBridge 171:3a7713b1edbc 1102 typedef struct /* Acceptance Filter Registers */
AnnaBridge 171:3a7713b1edbc 1103 {
AnnaBridge 171:3a7713b1edbc 1104 ///Offset: 0x00000000 - Acceptance Filter Register
AnnaBridge 171:3a7713b1edbc 1105 __IO uint32_t AFMR;
AnnaBridge 171:3a7713b1edbc 1106
AnnaBridge 171:3a7713b1edbc 1107 ///Offset: 0x00000004 - Standard Frame Individual Start Address Register
AnnaBridge 171:3a7713b1edbc 1108 __IO uint32_t SFF_sa;
AnnaBridge 171:3a7713b1edbc 1109
AnnaBridge 171:3a7713b1edbc 1110 ///Offset: 0x00000008 - Standard Frame Group Start Address Register
AnnaBridge 171:3a7713b1edbc 1111 __IO uint32_t SFF_GRP_sa;
AnnaBridge 171:3a7713b1edbc 1112
AnnaBridge 171:3a7713b1edbc 1113 ///Offset: 0x0000000C - Extended Frame Start Address Register
AnnaBridge 171:3a7713b1edbc 1114 __IO uint32_t EFF_sa;
AnnaBridge 171:3a7713b1edbc 1115
AnnaBridge 171:3a7713b1edbc 1116 ///Offset: 0x00000010 - Extended Frame Group Start Address Register
AnnaBridge 171:3a7713b1edbc 1117 __IO uint32_t EFF_GRP_sa;
AnnaBridge 171:3a7713b1edbc 1118
AnnaBridge 171:3a7713b1edbc 1119 ///Offset: 0x00000014 - End of AF Tables register
AnnaBridge 171:3a7713b1edbc 1120 __IO uint32_t ENDofTable;
AnnaBridge 171:3a7713b1edbc 1121
AnnaBridge 171:3a7713b1edbc 1122 ///Offset: 0x00000018 - LUT Error Address register
AnnaBridge 171:3a7713b1edbc 1123 __I uint32_t LUTerrAd;
AnnaBridge 171:3a7713b1edbc 1124
AnnaBridge 171:3a7713b1edbc 1125 ///Offset: 0x0000001C - LUT Error Register
AnnaBridge 171:3a7713b1edbc 1126 __I uint32_t LUTerr;
AnnaBridge 171:3a7713b1edbc 1127
AnnaBridge 171:3a7713b1edbc 1128 ///Offset: 0x00000020 - CAN Central Transmit Status Register
AnnaBridge 171:3a7713b1edbc 1129 __IO uint32_t FCANIE;
AnnaBridge 171:3a7713b1edbc 1130
AnnaBridge 171:3a7713b1edbc 1131 ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0
AnnaBridge 171:3a7713b1edbc 1132 __IO uint32_t FCANIC0;
AnnaBridge 171:3a7713b1edbc 1133
AnnaBridge 171:3a7713b1edbc 1134 ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1
AnnaBridge 171:3a7713b1edbc 1135 __IO uint32_t FCANIC1;
AnnaBridge 171:3a7713b1edbc 1136 } LPC_CANAF_TypeDef;
AnnaBridge 171:3a7713b1edbc 1137
AnnaBridge 171:3a7713b1edbc 1138 typedef struct /* Central Registers */
AnnaBridge 171:3a7713b1edbc 1139 {
AnnaBridge 171:3a7713b1edbc 1140 __I uint32_t TxSR;
AnnaBridge 171:3a7713b1edbc 1141 __I uint32_t RxSR;
AnnaBridge 171:3a7713b1edbc 1142 __I uint32_t MSR;
AnnaBridge 171:3a7713b1edbc 1143 } LPC_CANCR_TypeDef;
AnnaBridge 171:3a7713b1edbc 1144
AnnaBridge 171:3a7713b1edbc 1145 typedef struct /* Controller Registers */
AnnaBridge 171:3a7713b1edbc 1146 {
AnnaBridge 171:3a7713b1edbc 1147 ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller
AnnaBridge 171:3a7713b1edbc 1148 __IO uint32_t MOD;
AnnaBridge 171:3a7713b1edbc 1149
AnnaBridge 171:3a7713b1edbc 1150 ///Offset: 0x00000004 - Command bits that affect the state
AnnaBridge 171:3a7713b1edbc 1151 __O uint32_t CMR;
AnnaBridge 171:3a7713b1edbc 1152
AnnaBridge 171:3a7713b1edbc 1153 ///Offset: 0x00000008 - Global Controller Status and Error Counters
AnnaBridge 171:3a7713b1edbc 1154 __IO uint32_t GSR;
AnnaBridge 171:3a7713b1edbc 1155
AnnaBridge 171:3a7713b1edbc 1156 ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture
AnnaBridge 171:3a7713b1edbc 1157 __I uint32_t ICR;
AnnaBridge 171:3a7713b1edbc 1158
AnnaBridge 171:3a7713b1edbc 1159 ///Offset: 0x00000010 - Interrupt Enable Register
AnnaBridge 171:3a7713b1edbc 1160 __IO uint32_t IER;
AnnaBridge 171:3a7713b1edbc 1161
AnnaBridge 171:3a7713b1edbc 1162 ///Offset: 0x00000014 - Bus Timing Register
AnnaBridge 171:3a7713b1edbc 1163 __IO uint32_t BTR;
AnnaBridge 171:3a7713b1edbc 1164
AnnaBridge 171:3a7713b1edbc 1165 ///Offset: 0x00000018 - Error Warning Limit
AnnaBridge 171:3a7713b1edbc 1166 __IO uint32_t EWL;
AnnaBridge 171:3a7713b1edbc 1167
AnnaBridge 171:3a7713b1edbc 1168 ///Offset: 0x0000001C - Status Register
AnnaBridge 171:3a7713b1edbc 1169 __I uint32_t SR;
AnnaBridge 171:3a7713b1edbc 1170
AnnaBridge 171:3a7713b1edbc 1171 ///Offset: 0x00000020 - Receive frame status
AnnaBridge 171:3a7713b1edbc 1172 __IO uint32_t RFS;
AnnaBridge 171:3a7713b1edbc 1173
AnnaBridge 171:3a7713b1edbc 1174 ///Offset: 0x00000024 - Received Identifier
AnnaBridge 171:3a7713b1edbc 1175 __IO uint32_t RID;
AnnaBridge 171:3a7713b1edbc 1176
AnnaBridge 171:3a7713b1edbc 1177 ///Offset: 0x00000028 - Received data bytes 1-4
AnnaBridge 171:3a7713b1edbc 1178 __IO uint32_t RDA;
AnnaBridge 171:3a7713b1edbc 1179
AnnaBridge 171:3a7713b1edbc 1180 ///Offset: 0x0000002C - Received data bytes 5-8
AnnaBridge 171:3a7713b1edbc 1181 __IO uint32_t RDB;
AnnaBridge 171:3a7713b1edbc 1182
AnnaBridge 171:3a7713b1edbc 1183 ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1)
AnnaBridge 171:3a7713b1edbc 1184 __IO uint32_t TFI1;
AnnaBridge 171:3a7713b1edbc 1185
AnnaBridge 171:3a7713b1edbc 1186 ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1)
AnnaBridge 171:3a7713b1edbc 1187 __IO uint32_t TID1;
AnnaBridge 171:3a7713b1edbc 1188
AnnaBridge 171:3a7713b1edbc 1189 ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1)
AnnaBridge 171:3a7713b1edbc 1190 __IO uint32_t TDA1;
AnnaBridge 171:3a7713b1edbc 1191
AnnaBridge 171:3a7713b1edbc 1192 ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1)
AnnaBridge 171:3a7713b1edbc 1193 __IO uint32_t TDB1;
AnnaBridge 171:3a7713b1edbc 1194
AnnaBridge 171:3a7713b1edbc 1195 ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2)
AnnaBridge 171:3a7713b1edbc 1196 __IO uint32_t TFI2;
AnnaBridge 171:3a7713b1edbc 1197
AnnaBridge 171:3a7713b1edbc 1198 ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2)
AnnaBridge 171:3a7713b1edbc 1199 __IO uint32_t TID2;
AnnaBridge 171:3a7713b1edbc 1200
AnnaBridge 171:3a7713b1edbc 1201 ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2)
AnnaBridge 171:3a7713b1edbc 1202 __IO uint32_t TDA2;
AnnaBridge 171:3a7713b1edbc 1203
AnnaBridge 171:3a7713b1edbc 1204 ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2)
AnnaBridge 171:3a7713b1edbc 1205 __IO uint32_t TDB2;
AnnaBridge 171:3a7713b1edbc 1206
AnnaBridge 171:3a7713b1edbc 1207 ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3)
AnnaBridge 171:3a7713b1edbc 1208 __IO uint32_t TFI3;
AnnaBridge 171:3a7713b1edbc 1209
AnnaBridge 171:3a7713b1edbc 1210 ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3)
AnnaBridge 171:3a7713b1edbc 1211 __IO uint32_t TID3;
AnnaBridge 171:3a7713b1edbc 1212
AnnaBridge 171:3a7713b1edbc 1213 ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3)
AnnaBridge 171:3a7713b1edbc 1214 __IO uint32_t TDA3;
AnnaBridge 171:3a7713b1edbc 1215
AnnaBridge 171:3a7713b1edbc 1216 ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3)
AnnaBridge 171:3a7713b1edbc 1217 __IO uint32_t TDB3;
AnnaBridge 171:3a7713b1edbc 1218 } LPC_CAN_TypeDef;
AnnaBridge 171:3a7713b1edbc 1219
AnnaBridge 171:3a7713b1edbc 1220 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
AnnaBridge 171:3a7713b1edbc 1221 typedef struct
AnnaBridge 171:3a7713b1edbc 1222 {
AnnaBridge 171:3a7713b1edbc 1223 __IO uint32_t CR;
AnnaBridge 171:3a7713b1edbc 1224 __IO uint32_t CTRL;
AnnaBridge 171:3a7713b1edbc 1225 __IO uint32_t CNTVAL;
AnnaBridge 171:3a7713b1edbc 1226 } LPC_DAC_TypeDef;
AnnaBridge 171:3a7713b1edbc 1227
AnnaBridge 171:3a7713b1edbc 1228
AnnaBridge 171:3a7713b1edbc 1229 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1230 typedef struct
AnnaBridge 171:3a7713b1edbc 1231 {
AnnaBridge 171:3a7713b1edbc 1232 __IO uint32_t DAO;
AnnaBridge 171:3a7713b1edbc 1233 __IO uint32_t DAI;
AnnaBridge 171:3a7713b1edbc 1234 __O uint32_t TXFIFO;
AnnaBridge 171:3a7713b1edbc 1235 __I uint32_t RXFIFO;
AnnaBridge 171:3a7713b1edbc 1236 __I uint32_t STATE;
AnnaBridge 171:3a7713b1edbc 1237 __IO uint32_t DMA1;
AnnaBridge 171:3a7713b1edbc 1238 __IO uint32_t DMA2;
AnnaBridge 171:3a7713b1edbc 1239 __IO uint32_t IRQ;
AnnaBridge 171:3a7713b1edbc 1240 __IO uint32_t TXRATE;
AnnaBridge 171:3a7713b1edbc 1241 __IO uint32_t RXRATE;
AnnaBridge 171:3a7713b1edbc 1242 __IO uint32_t TXBITRATE;
AnnaBridge 171:3a7713b1edbc 1243 __IO uint32_t RXBITRATE;
AnnaBridge 171:3a7713b1edbc 1244 __IO uint32_t TXMODE;
AnnaBridge 171:3a7713b1edbc 1245 __IO uint32_t RXMODE;
AnnaBridge 171:3a7713b1edbc 1246 } LPC_I2S_TypeDef;
AnnaBridge 171:3a7713b1edbc 1247
AnnaBridge 171:3a7713b1edbc 1248
AnnaBridge 171:3a7713b1edbc 1249
AnnaBridge 171:3a7713b1edbc 1250
AnnaBridge 171:3a7713b1edbc 1251
AnnaBridge 171:3a7713b1edbc 1252
AnnaBridge 171:3a7713b1edbc 1253 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
AnnaBridge 171:3a7713b1edbc 1254 typedef struct
AnnaBridge 171:3a7713b1edbc 1255 {
AnnaBridge 171:3a7713b1edbc 1256 __I uint32_t CON;
AnnaBridge 171:3a7713b1edbc 1257 __O uint32_t CON_SET;
AnnaBridge 171:3a7713b1edbc 1258 __O uint32_t CON_CLR;
AnnaBridge 171:3a7713b1edbc 1259 __I uint32_t CAPCON;
AnnaBridge 171:3a7713b1edbc 1260 __O uint32_t CAPCON_SET;
AnnaBridge 171:3a7713b1edbc 1261 __O uint32_t CAPCON_CLR;
AnnaBridge 171:3a7713b1edbc 1262 __IO uint32_t TC0;
AnnaBridge 171:3a7713b1edbc 1263 __IO uint32_t TC1;
AnnaBridge 171:3a7713b1edbc 1264 __IO uint32_t TC2;
AnnaBridge 171:3a7713b1edbc 1265 __IO uint32_t LIM0;
AnnaBridge 171:3a7713b1edbc 1266 __IO uint32_t LIM1;
AnnaBridge 171:3a7713b1edbc 1267 __IO uint32_t LIM2;
AnnaBridge 171:3a7713b1edbc 1268 __IO uint32_t MAT0;
AnnaBridge 171:3a7713b1edbc 1269 __IO uint32_t MAT1;
AnnaBridge 171:3a7713b1edbc 1270 __IO uint32_t MAT2;
AnnaBridge 171:3a7713b1edbc 1271 __IO uint32_t DT;
AnnaBridge 171:3a7713b1edbc 1272 __IO uint32_t CP;
AnnaBridge 171:3a7713b1edbc 1273 __IO uint32_t CAP0;
AnnaBridge 171:3a7713b1edbc 1274 __IO uint32_t CAP1;
AnnaBridge 171:3a7713b1edbc 1275 __IO uint32_t CAP2;
AnnaBridge 171:3a7713b1edbc 1276 __I uint32_t INTEN;
AnnaBridge 171:3a7713b1edbc 1277 __O uint32_t INTEN_SET;
AnnaBridge 171:3a7713b1edbc 1278 __O uint32_t INTEN_CLR;
AnnaBridge 171:3a7713b1edbc 1279 __I uint32_t CNTCON;
AnnaBridge 171:3a7713b1edbc 1280 __O uint32_t CNTCON_SET;
AnnaBridge 171:3a7713b1edbc 1281 __O uint32_t CNTCON_CLR;
AnnaBridge 171:3a7713b1edbc 1282 __I uint32_t INTF;
AnnaBridge 171:3a7713b1edbc 1283 __O uint32_t INTF_SET;
AnnaBridge 171:3a7713b1edbc 1284 __O uint32_t INTF_CLR;
AnnaBridge 171:3a7713b1edbc 1285 __O uint32_t CAP_CLR;
AnnaBridge 171:3a7713b1edbc 1286 } LPC_MCPWM_TypeDef;
AnnaBridge 171:3a7713b1edbc 1287
AnnaBridge 171:3a7713b1edbc 1288 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
AnnaBridge 171:3a7713b1edbc 1289 typedef struct
AnnaBridge 171:3a7713b1edbc 1290 {
AnnaBridge 171:3a7713b1edbc 1291 __O uint32_t CON;
AnnaBridge 171:3a7713b1edbc 1292 __I uint32_t STAT;
AnnaBridge 171:3a7713b1edbc 1293 __IO uint32_t CONF;
AnnaBridge 171:3a7713b1edbc 1294 __I uint32_t POS;
AnnaBridge 171:3a7713b1edbc 1295 __IO uint32_t MAXPOS;
AnnaBridge 171:3a7713b1edbc 1296 __IO uint32_t CMPOS0;
AnnaBridge 171:3a7713b1edbc 1297 __IO uint32_t CMPOS1;
AnnaBridge 171:3a7713b1edbc 1298 __IO uint32_t CMPOS2;
AnnaBridge 171:3a7713b1edbc 1299 __I uint32_t INXCNT;
AnnaBridge 171:3a7713b1edbc 1300 __IO uint32_t INXCMP0;
AnnaBridge 171:3a7713b1edbc 1301 __IO uint32_t LOAD;
AnnaBridge 171:3a7713b1edbc 1302 __I uint32_t TIME;
AnnaBridge 171:3a7713b1edbc 1303 __I uint32_t VEL;
AnnaBridge 171:3a7713b1edbc 1304 __I uint32_t CAP;
AnnaBridge 171:3a7713b1edbc 1305 __IO uint32_t VELCOMP;
AnnaBridge 171:3a7713b1edbc 1306 __IO uint32_t FILTERPHA;
AnnaBridge 171:3a7713b1edbc 1307 __IO uint32_t FILTERPHB;
AnnaBridge 171:3a7713b1edbc 1308 __IO uint32_t FILTERINX;
AnnaBridge 171:3a7713b1edbc 1309 __IO uint32_t WINDOW;
AnnaBridge 171:3a7713b1edbc 1310 __IO uint32_t INXCMP1;
AnnaBridge 171:3a7713b1edbc 1311 __IO uint32_t INXCMP2;
AnnaBridge 171:3a7713b1edbc 1312 uint32_t RESERVED0[993];
AnnaBridge 171:3a7713b1edbc 1313 __O uint32_t IEC;
AnnaBridge 171:3a7713b1edbc 1314 __O uint32_t IES;
AnnaBridge 171:3a7713b1edbc 1315 __I uint32_t INTSTAT;
AnnaBridge 171:3a7713b1edbc 1316 __I uint32_t IE;
AnnaBridge 171:3a7713b1edbc 1317 __O uint32_t CLR;
AnnaBridge 171:3a7713b1edbc 1318 __O uint32_t SET;
AnnaBridge 171:3a7713b1edbc 1319 } LPC_QEI_TypeDef;
AnnaBridge 171:3a7713b1edbc 1320
AnnaBridge 171:3a7713b1edbc 1321 /*------------- SD/MMC card Interface (MCI)-----------------------------------*/
AnnaBridge 171:3a7713b1edbc 1322 typedef struct
AnnaBridge 171:3a7713b1edbc 1323 {
AnnaBridge 171:3a7713b1edbc 1324 __IO uint32_t POWER;
AnnaBridge 171:3a7713b1edbc 1325 __IO uint32_t CLOCK;
AnnaBridge 171:3a7713b1edbc 1326 __IO uint32_t ARGUMENT;
AnnaBridge 171:3a7713b1edbc 1327 __IO uint32_t COMMAND;
AnnaBridge 171:3a7713b1edbc 1328 __I uint32_t RESP_CMD;
AnnaBridge 171:3a7713b1edbc 1329 __I uint32_t RESP0;
AnnaBridge 171:3a7713b1edbc 1330 __I uint32_t RESP1;
AnnaBridge 171:3a7713b1edbc 1331 __I uint32_t RESP2;
AnnaBridge 171:3a7713b1edbc 1332 __I uint32_t RESP3;
AnnaBridge 171:3a7713b1edbc 1333 __IO uint32_t DATATMR;
AnnaBridge 171:3a7713b1edbc 1334 __IO uint32_t DATALEN;
AnnaBridge 171:3a7713b1edbc 1335 __IO uint32_t DATACTRL;
AnnaBridge 171:3a7713b1edbc 1336 __I uint32_t DATACNT;
AnnaBridge 171:3a7713b1edbc 1337 __I uint32_t STATUS;
AnnaBridge 171:3a7713b1edbc 1338 __O uint32_t CLEAR;
AnnaBridge 171:3a7713b1edbc 1339 __IO uint32_t MASK0;
AnnaBridge 171:3a7713b1edbc 1340 uint32_t RESERVED0[2];
AnnaBridge 171:3a7713b1edbc 1341 __I uint32_t FIFOCNT;
AnnaBridge 171:3a7713b1edbc 1342 uint32_t RESERVED1[13];
AnnaBridge 171:3a7713b1edbc 1343 __IO uint32_t FIFO[16];
AnnaBridge 171:3a7713b1edbc 1344 } LPC_MCI_TypeDef;
AnnaBridge 171:3a7713b1edbc 1345
AnnaBridge 171:3a7713b1edbc 1346
AnnaBridge 171:3a7713b1edbc 1347
AnnaBridge 171:3a7713b1edbc 1348
AnnaBridge 171:3a7713b1edbc 1349
AnnaBridge 171:3a7713b1edbc 1350
AnnaBridge 171:3a7713b1edbc 1351
AnnaBridge 171:3a7713b1edbc 1352
AnnaBridge 171:3a7713b1edbc 1353
AnnaBridge 171:3a7713b1edbc 1354
AnnaBridge 171:3a7713b1edbc 1355 /*------------- EEPROM Controller (EEPROM) -----------------------------------*/
AnnaBridge 171:3a7713b1edbc 1356 typedef struct
AnnaBridge 171:3a7713b1edbc 1357 {
AnnaBridge 171:3a7713b1edbc 1358 __IO uint32_t CMD; /* 0x0080 */
AnnaBridge 171:3a7713b1edbc 1359 __IO uint32_t ADDR;
AnnaBridge 171:3a7713b1edbc 1360 __IO uint32_t WDATA;
AnnaBridge 171:3a7713b1edbc 1361 __IO uint32_t RDATA;
AnnaBridge 171:3a7713b1edbc 1362 __IO uint32_t WSTATE; /* 0x0090 */
AnnaBridge 171:3a7713b1edbc 1363 __IO uint32_t CLKDIV;
AnnaBridge 171:3a7713b1edbc 1364 __IO uint32_t PWRDWN; /* 0x0098 */
AnnaBridge 171:3a7713b1edbc 1365 uint32_t RESERVED0[975];
AnnaBridge 171:3a7713b1edbc 1366 __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */
AnnaBridge 171:3a7713b1edbc 1367 __IO uint32_t INT_SET_ENABLE;
AnnaBridge 171:3a7713b1edbc 1368 __IO uint32_t INT_STATUS; /* 0x0FE0 */
AnnaBridge 171:3a7713b1edbc 1369 __IO uint32_t INT_ENABLE;
AnnaBridge 171:3a7713b1edbc 1370 __IO uint32_t INT_CLR_STATUS;
AnnaBridge 171:3a7713b1edbc 1371 __IO uint32_t INT_SET_STATUS;
AnnaBridge 171:3a7713b1edbc 1372 } LPC_EEPROM_TypeDef;
AnnaBridge 171:3a7713b1edbc 1373
AnnaBridge 171:3a7713b1edbc 1374
AnnaBridge 171:3a7713b1edbc 1375 /*------------- COMPARATOR ----------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1376
AnnaBridge 171:3a7713b1edbc 1377 typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */
AnnaBridge 171:3a7713b1edbc 1378 __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */
AnnaBridge 171:3a7713b1edbc 1379 __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */
AnnaBridge 171:3a7713b1edbc 1380 __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */
AnnaBridge 171:3a7713b1edbc 1381 } LPC_COMPARATOR_Type;
AnnaBridge 171:3a7713b1edbc 1382
AnnaBridge 171:3a7713b1edbc 1383
AnnaBridge 171:3a7713b1edbc 1384 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 1385 #pragma no_anon_unions
AnnaBridge 171:3a7713b1edbc 1386 #endif
AnnaBridge 171:3a7713b1edbc 1387
AnnaBridge 171:3a7713b1edbc 1388 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1389 /* Peripheral memory map */
AnnaBridge 171:3a7713b1edbc 1390 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1391 /* Base addresses */
AnnaBridge 171:3a7713b1edbc 1392 #define LPC_FLASH_BASE (0x00000000UL)
AnnaBridge 171:3a7713b1edbc 1393 #define LPC_RAM_BASE (0x10000000UL)
AnnaBridge 171:3a7713b1edbc 1394 #define LPC_PERI_RAM_BASE (0x20000000UL)
AnnaBridge 171:3a7713b1edbc 1395 #define LPC_APB0_BASE (0x40000000UL)
AnnaBridge 171:3a7713b1edbc 1396 #define LPC_APB1_BASE (0x40080000UL)
AnnaBridge 171:3a7713b1edbc 1397 #define LPC_AHBRAM1_BASE (0x20004000UL)
AnnaBridge 171:3a7713b1edbc 1398 #define LPC_AHB_BASE (0x20080000UL)
AnnaBridge 171:3a7713b1edbc 1399 #define LPC_CM3_BASE (0xE0000000UL)
AnnaBridge 171:3a7713b1edbc 1400
AnnaBridge 171:3a7713b1edbc 1401 /* APB0 peripherals */
AnnaBridge 171:3a7713b1edbc 1402 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
AnnaBridge 171:3a7713b1edbc 1403 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
AnnaBridge 171:3a7713b1edbc 1404 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
AnnaBridge 171:3a7713b1edbc 1405 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
AnnaBridge 171:3a7713b1edbc 1406 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
AnnaBridge 171:3a7713b1edbc 1407 #define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000)
AnnaBridge 171:3a7713b1edbc 1408 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
AnnaBridge 171:3a7713b1edbc 1409 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
AnnaBridge 171:3a7713b1edbc 1410 #define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000)
AnnaBridge 171:3a7713b1edbc 1411 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
AnnaBridge 171:3a7713b1edbc 1412 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
AnnaBridge 171:3a7713b1edbc 1413 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000)
AnnaBridge 171:3a7713b1edbc 1414 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
AnnaBridge 171:3a7713b1edbc 1415 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
AnnaBridge 171:3a7713b1edbc 1416 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
AnnaBridge 171:3a7713b1edbc 1417 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
AnnaBridge 171:3a7713b1edbc 1418 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
AnnaBridge 171:3a7713b1edbc 1419 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
AnnaBridge 171:3a7713b1edbc 1420 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
AnnaBridge 171:3a7713b1edbc 1421 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
AnnaBridge 171:3a7713b1edbc 1422
AnnaBridge 171:3a7713b1edbc 1423 /* APB1 peripherals */
AnnaBridge 171:3a7713b1edbc 1424 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
AnnaBridge 171:3a7713b1edbc 1425 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
AnnaBridge 171:3a7713b1edbc 1426 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
AnnaBridge 171:3a7713b1edbc 1427 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
AnnaBridge 171:3a7713b1edbc 1428 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
AnnaBridge 171:3a7713b1edbc 1429 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
AnnaBridge 171:3a7713b1edbc 1430 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
AnnaBridge 171:3a7713b1edbc 1431 #define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000)
AnnaBridge 171:3a7713b1edbc 1432 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
AnnaBridge 171:3a7713b1edbc 1433 #define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000)
AnnaBridge 171:3a7713b1edbc 1434 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
AnnaBridge 171:3a7713b1edbc 1435 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
AnnaBridge 171:3a7713b1edbc 1436 #define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000)
AnnaBridge 171:3a7713b1edbc 1437 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
AnnaBridge 171:3a7713b1edbc 1438
AnnaBridge 171:3a7713b1edbc 1439 /* AHB peripherals */
AnnaBridge 171:3a7713b1edbc 1440 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000)
AnnaBridge 171:3a7713b1edbc 1441 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100)
AnnaBridge 171:3a7713b1edbc 1442 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120)
AnnaBridge 171:3a7713b1edbc 1443 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140)
AnnaBridge 171:3a7713b1edbc 1444 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160)
AnnaBridge 171:3a7713b1edbc 1445 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180)
AnnaBridge 171:3a7713b1edbc 1446 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0)
AnnaBridge 171:3a7713b1edbc 1447 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0)
AnnaBridge 171:3a7713b1edbc 1448 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0)
AnnaBridge 171:3a7713b1edbc 1449 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000)
AnnaBridge 171:3a7713b1edbc 1450 #define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000)
AnnaBridge 171:3a7713b1edbc 1451 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
AnnaBridge 171:3a7713b1edbc 1452 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000)
AnnaBridge 171:3a7713b1edbc 1453 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000)
AnnaBridge 171:3a7713b1edbc 1454 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020)
AnnaBridge 171:3a7713b1edbc 1455 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040)
AnnaBridge 171:3a7713b1edbc 1456 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060)
AnnaBridge 171:3a7713b1edbc 1457 #define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080)
AnnaBridge 171:3a7713b1edbc 1458 #define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0)
AnnaBridge 171:3a7713b1edbc 1459 #define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000)
AnnaBridge 171:3a7713b1edbc 1460
AnnaBridge 171:3a7713b1edbc 1461 #define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080)
AnnaBridge 171:3a7713b1edbc 1462
AnnaBridge 171:3a7713b1edbc 1463
AnnaBridge 171:3a7713b1edbc 1464 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1465 /* Peripheral declaration */
AnnaBridge 171:3a7713b1edbc 1466 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1467 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
AnnaBridge 171:3a7713b1edbc 1468 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
AnnaBridge 171:3a7713b1edbc 1469 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
AnnaBridge 171:3a7713b1edbc 1470 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
AnnaBridge 171:3a7713b1edbc 1471 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
AnnaBridge 171:3a7713b1edbc 1472 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
AnnaBridge 171:3a7713b1edbc 1473 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
AnnaBridge 171:3a7713b1edbc 1474 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
AnnaBridge 171:3a7713b1edbc 1475 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
AnnaBridge 171:3a7713b1edbc 1476 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
AnnaBridge 171:3a7713b1edbc 1477 #define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE )
AnnaBridge 171:3a7713b1edbc 1478 #define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
AnnaBridge 171:3a7713b1edbc 1479 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
AnnaBridge 171:3a7713b1edbc 1480 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
AnnaBridge 171:3a7713b1edbc 1481 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
AnnaBridge 171:3a7713b1edbc 1482 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
AnnaBridge 171:3a7713b1edbc 1483 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
AnnaBridge 171:3a7713b1edbc 1484 #define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE)
AnnaBridge 171:3a7713b1edbc 1485 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
AnnaBridge 171:3a7713b1edbc 1486 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
AnnaBridge 171:3a7713b1edbc 1487 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
AnnaBridge 171:3a7713b1edbc 1488 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
AnnaBridge 171:3a7713b1edbc 1489 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
AnnaBridge 171:3a7713b1edbc 1490 #define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )
AnnaBridge 171:3a7713b1edbc 1491 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
AnnaBridge 171:3a7713b1edbc 1492 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
AnnaBridge 171:3a7713b1edbc 1493 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
AnnaBridge 171:3a7713b1edbc 1494 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
AnnaBridge 171:3a7713b1edbc 1495 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
AnnaBridge 171:3a7713b1edbc 1496 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
AnnaBridge 171:3a7713b1edbc 1497 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
AnnaBridge 171:3a7713b1edbc 1498 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
AnnaBridge 171:3a7713b1edbc 1499 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
AnnaBridge 171:3a7713b1edbc 1500 #define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
AnnaBridge 171:3a7713b1edbc 1501 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
AnnaBridge 171:3a7713b1edbc 1502 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
AnnaBridge 171:3a7713b1edbc 1503 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
AnnaBridge 171:3a7713b1edbc 1504 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
AnnaBridge 171:3a7713b1edbc 1505 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
AnnaBridge 171:3a7713b1edbc 1506 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
AnnaBridge 171:3a7713b1edbc 1507 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
AnnaBridge 171:3a7713b1edbc 1508 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
AnnaBridge 171:3a7713b1edbc 1509 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
AnnaBridge 171:3a7713b1edbc 1510 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
AnnaBridge 171:3a7713b1edbc 1511 #define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE )
AnnaBridge 171:3a7713b1edbc 1512 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
AnnaBridge 171:3a7713b1edbc 1513 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
AnnaBridge 171:3a7713b1edbc 1514 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
AnnaBridge 171:3a7713b1edbc 1515 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
AnnaBridge 171:3a7713b1edbc 1516 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
AnnaBridge 171:3a7713b1edbc 1517 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
AnnaBridge 171:3a7713b1edbc 1518 #define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )
AnnaBridge 171:3a7713b1edbc 1519 #define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
AnnaBridge 171:3a7713b1edbc 1520 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
AnnaBridge 171:3a7713b1edbc 1521 #define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )
AnnaBridge 171:3a7713b1edbc 1522
AnnaBridge 171:3a7713b1edbc 1523
AnnaBridge 171:3a7713b1edbc 1524
AnnaBridge 171:3a7713b1edbc 1525 #endif // __LPC407x_8x_177x_8x_H__