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TARGET_LPC1768/TOOLCHAIN_ARM_STD/core_sc300.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file core_sc300.h
AnnaBridge 171:3a7713b1edbc 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
AnnaBridge 171:3a7713b1edbc 4 * @version V5.0.6
AnnaBridge 171:3a7713b1edbc 5 * @date 04. June 2018
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7 /*
AnnaBridge 171:3a7713b1edbc 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 171:3a7713b1edbc 13 * not use this file except in compliance with the License.
AnnaBridge 171:3a7713b1edbc 14 * You may obtain a copy of the License at
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 171:3a7713b1edbc 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 171:3a7713b1edbc 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 171:3a7713b1edbc 21 * See the License for the specific language governing permissions and
AnnaBridge 171:3a7713b1edbc 22 * limitations under the License.
AnnaBridge 171:3a7713b1edbc 23 */
AnnaBridge 171:3a7713b1edbc 24
AnnaBridge 171:3a7713b1edbc 25 #if defined ( __ICCARM__ )
AnnaBridge 171:3a7713b1edbc 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 171:3a7713b1edbc 27 #elif defined (__clang__)
AnnaBridge 171:3a7713b1edbc 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 171:3a7713b1edbc 29 #endif
AnnaBridge 171:3a7713b1edbc 30
AnnaBridge 171:3a7713b1edbc 31 #ifndef __CORE_SC300_H_GENERIC
AnnaBridge 171:3a7713b1edbc 32 #define __CORE_SC300_H_GENERIC
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 37 extern "C" {
AnnaBridge 171:3a7713b1edbc 38 #endif
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 /**
AnnaBridge 171:3a7713b1edbc 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 171:3a7713b1edbc 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 171:3a7713b1edbc 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 171:3a7713b1edbc 48 Unions are used for effective representation of core registers.
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 171:3a7713b1edbc 51 Function-like macros are used to allow more efficient code.
AnnaBridge 171:3a7713b1edbc 52 */
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 56 * CMSIS definitions
AnnaBridge 171:3a7713b1edbc 57 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 58 /**
AnnaBridge 171:3a7713b1edbc 59 \ingroup SC3000
AnnaBridge 171:3a7713b1edbc 60 @{
AnnaBridge 171:3a7713b1edbc 61 */
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 #include "cmsis_version.h"
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 /* CMSIS SC300 definitions */
AnnaBridge 171:3a7713b1edbc 66 #define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
AnnaBridge 171:3a7713b1edbc 67 #define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 171:3a7713b1edbc 68 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 171:3a7713b1edbc 69 __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 #define __CORTEX_SC (300U) /*!< Cortex secure core */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 171:3a7713b1edbc 74 This core does not support an FPU at all
AnnaBridge 171:3a7713b1edbc 75 */
AnnaBridge 171:3a7713b1edbc 76 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 79 #if defined __TARGET_FPU_VFP
AnnaBridge 171:3a7713b1edbc 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 81 #endif
AnnaBridge 171:3a7713b1edbc 82
AnnaBridge 171:3a7713b1edbc 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 172:65be27845400 84 #if defined __ARM_FP
AnnaBridge 171:3a7713b1edbc 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 86 #endif
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 #elif defined ( __GNUC__ )
AnnaBridge 171:3a7713b1edbc 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 171:3a7713b1edbc 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 91 #endif
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 #elif defined ( __ICCARM__ )
AnnaBridge 171:3a7713b1edbc 94 #if defined __ARMVFP__
AnnaBridge 171:3a7713b1edbc 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 96 #endif
AnnaBridge 171:3a7713b1edbc 97
AnnaBridge 171:3a7713b1edbc 98 #elif defined ( __TI_ARM__ )
AnnaBridge 171:3a7713b1edbc 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 171:3a7713b1edbc 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 101 #endif
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 #elif defined ( __TASKING__ )
AnnaBridge 171:3a7713b1edbc 104 #if defined __FPU_VFP__
AnnaBridge 171:3a7713b1edbc 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 106 #endif
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 #elif defined ( __CSMC__ )
AnnaBridge 171:3a7713b1edbc 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 171:3a7713b1edbc 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 111 #endif
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 #endif
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 119 }
AnnaBridge 171:3a7713b1edbc 120 #endif
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 #endif /* __CORE_SC300_H_GENERIC */
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 #ifndef __CMSIS_GENERIC
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 #ifndef __CORE_SC300_H_DEPENDANT
AnnaBridge 171:3a7713b1edbc 127 #define __CORE_SC300_H_DEPENDANT
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 130 extern "C" {
AnnaBridge 171:3a7713b1edbc 131 #endif
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 /* check device defines and use defaults */
AnnaBridge 171:3a7713b1edbc 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 171:3a7713b1edbc 135 #ifndef __SC300_REV
AnnaBridge 171:3a7713b1edbc 136 #define __SC300_REV 0x0000U
AnnaBridge 171:3a7713b1edbc 137 #warning "__SC300_REV not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 138 #endif
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 #ifndef __MPU_PRESENT
AnnaBridge 171:3a7713b1edbc 141 #define __MPU_PRESENT 0U
AnnaBridge 171:3a7713b1edbc 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 143 #endif
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 #ifndef __NVIC_PRIO_BITS
AnnaBridge 171:3a7713b1edbc 146 #define __NVIC_PRIO_BITS 3U
AnnaBridge 171:3a7713b1edbc 147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 148 #endif
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 #ifndef __Vendor_SysTickConfig
AnnaBridge 171:3a7713b1edbc 151 #define __Vendor_SysTickConfig 0U
AnnaBridge 171:3a7713b1edbc 152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 153 #endif
AnnaBridge 171:3a7713b1edbc 154 #endif
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 171:3a7713b1edbc 157 /**
AnnaBridge 171:3a7713b1edbc 158 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 171:3a7713b1edbc 161 \li to specify the access to peripheral variables.
AnnaBridge 171:3a7713b1edbc 162 \li for automatic generation of peripheral register debug information.
AnnaBridge 171:3a7713b1edbc 163 */
AnnaBridge 171:3a7713b1edbc 164 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 165 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 171:3a7713b1edbc 166 #else
AnnaBridge 171:3a7713b1edbc 167 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 171:3a7713b1edbc 168 #endif
AnnaBridge 171:3a7713b1edbc 169 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 171:3a7713b1edbc 170 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 /* following defines should be used for structure members */
AnnaBridge 171:3a7713b1edbc 173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 171:3a7713b1edbc 174 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 171:3a7713b1edbc 175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 /*@} end of group SC300 */
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180
AnnaBridge 171:3a7713b1edbc 181 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 182 * Register Abstraction
AnnaBridge 171:3a7713b1edbc 183 Core Register contain:
AnnaBridge 171:3a7713b1edbc 184 - Core Register
AnnaBridge 171:3a7713b1edbc 185 - Core NVIC Register
AnnaBridge 171:3a7713b1edbc 186 - Core SCB Register
AnnaBridge 171:3a7713b1edbc 187 - Core SysTick Register
AnnaBridge 171:3a7713b1edbc 188 - Core Debug Register
AnnaBridge 171:3a7713b1edbc 189 - Core MPU Register
AnnaBridge 171:3a7713b1edbc 190 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 191 /**
AnnaBridge 171:3a7713b1edbc 192 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 171:3a7713b1edbc 193 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 171:3a7713b1edbc 194 */
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 /**
AnnaBridge 171:3a7713b1edbc 197 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 198 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 171:3a7713b1edbc 199 \brief Core Register type definitions.
AnnaBridge 171:3a7713b1edbc 200 @{
AnnaBridge 171:3a7713b1edbc 201 */
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 /**
AnnaBridge 171:3a7713b1edbc 204 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 171:3a7713b1edbc 205 */
AnnaBridge 171:3a7713b1edbc 206 typedef union
AnnaBridge 171:3a7713b1edbc 207 {
AnnaBridge 171:3a7713b1edbc 208 struct
AnnaBridge 171:3a7713b1edbc 209 {
AnnaBridge 171:3a7713b1edbc 210 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
AnnaBridge 171:3a7713b1edbc 211 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 171:3a7713b1edbc 212 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 171:3a7713b1edbc 213 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 171:3a7713b1edbc 214 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 171:3a7713b1edbc 215 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 171:3a7713b1edbc 216 } b; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 217 uint32_t w; /*!< Type used for word access */
AnnaBridge 171:3a7713b1edbc 218 } APSR_Type;
AnnaBridge 171:3a7713b1edbc 219
AnnaBridge 171:3a7713b1edbc 220 /* APSR Register Definitions */
AnnaBridge 171:3a7713b1edbc 221 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 171:3a7713b1edbc 222 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 171:3a7713b1edbc 223
AnnaBridge 171:3a7713b1edbc 224 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 171:3a7713b1edbc 225 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 171:3a7713b1edbc 226
AnnaBridge 171:3a7713b1edbc 227 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 171:3a7713b1edbc 228 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 171:3a7713b1edbc 229
AnnaBridge 171:3a7713b1edbc 230 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 171:3a7713b1edbc 231 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
AnnaBridge 171:3a7713b1edbc 234 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236
AnnaBridge 171:3a7713b1edbc 237 /**
AnnaBridge 171:3a7713b1edbc 238 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 171:3a7713b1edbc 239 */
AnnaBridge 171:3a7713b1edbc 240 typedef union
AnnaBridge 171:3a7713b1edbc 241 {
AnnaBridge 171:3a7713b1edbc 242 struct
AnnaBridge 171:3a7713b1edbc 243 {
AnnaBridge 171:3a7713b1edbc 244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 171:3a7713b1edbc 245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 171:3a7713b1edbc 246 } b; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 247 uint32_t w; /*!< Type used for word access */
AnnaBridge 171:3a7713b1edbc 248 } IPSR_Type;
AnnaBridge 171:3a7713b1edbc 249
AnnaBridge 171:3a7713b1edbc 250 /* IPSR Register Definitions */
AnnaBridge 171:3a7713b1edbc 251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 171:3a7713b1edbc 252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 171:3a7713b1edbc 253
AnnaBridge 171:3a7713b1edbc 254
AnnaBridge 171:3a7713b1edbc 255 /**
AnnaBridge 171:3a7713b1edbc 256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 171:3a7713b1edbc 257 */
AnnaBridge 171:3a7713b1edbc 258 typedef union
AnnaBridge 171:3a7713b1edbc 259 {
AnnaBridge 171:3a7713b1edbc 260 struct
AnnaBridge 171:3a7713b1edbc 261 {
AnnaBridge 171:3a7713b1edbc 262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 171:3a7713b1edbc 263 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
AnnaBridge 171:3a7713b1edbc 264 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
AnnaBridge 171:3a7713b1edbc 265 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
AnnaBridge 171:3a7713b1edbc 266 uint32_t T:1; /*!< bit: 24 Thumb bit */
AnnaBridge 171:3a7713b1edbc 267 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
AnnaBridge 171:3a7713b1edbc 268 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 171:3a7713b1edbc 269 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 171:3a7713b1edbc 270 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 171:3a7713b1edbc 271 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 171:3a7713b1edbc 272 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 171:3a7713b1edbc 273 } b; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 274 uint32_t w; /*!< Type used for word access */
AnnaBridge 171:3a7713b1edbc 275 } xPSR_Type;
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 /* xPSR Register Definitions */
AnnaBridge 171:3a7713b1edbc 278 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 171:3a7713b1edbc 279 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 171:3a7713b1edbc 280
AnnaBridge 171:3a7713b1edbc 281 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 171:3a7713b1edbc 282 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 171:3a7713b1edbc 283
AnnaBridge 171:3a7713b1edbc 284 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 171:3a7713b1edbc 285 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 171:3a7713b1edbc 288 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 171:3a7713b1edbc 289
AnnaBridge 171:3a7713b1edbc 290 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
AnnaBridge 171:3a7713b1edbc 291 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
AnnaBridge 171:3a7713b1edbc 292
AnnaBridge 171:3a7713b1edbc 293 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
AnnaBridge 171:3a7713b1edbc 294 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 171:3a7713b1edbc 297 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
AnnaBridge 171:3a7713b1edbc 300 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
AnnaBridge 171:3a7713b1edbc 301
AnnaBridge 171:3a7713b1edbc 302 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 171:3a7713b1edbc 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 171:3a7713b1edbc 304
AnnaBridge 171:3a7713b1edbc 305
AnnaBridge 171:3a7713b1edbc 306 /**
AnnaBridge 171:3a7713b1edbc 307 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 171:3a7713b1edbc 308 */
AnnaBridge 171:3a7713b1edbc 309 typedef union
AnnaBridge 171:3a7713b1edbc 310 {
AnnaBridge 171:3a7713b1edbc 311 struct
AnnaBridge 171:3a7713b1edbc 312 {
AnnaBridge 171:3a7713b1edbc 313 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 171:3a7713b1edbc 314 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 171:3a7713b1edbc 315 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 171:3a7713b1edbc 316 } b; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 317 uint32_t w; /*!< Type used for word access */
AnnaBridge 171:3a7713b1edbc 318 } CONTROL_Type;
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 /* CONTROL Register Definitions */
AnnaBridge 171:3a7713b1edbc 321 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 171:3a7713b1edbc 322 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 171:3a7713b1edbc 323
AnnaBridge 171:3a7713b1edbc 324 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 171:3a7713b1edbc 325 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 /*@} end of group CMSIS_CORE */
AnnaBridge 171:3a7713b1edbc 328
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 /**
AnnaBridge 171:3a7713b1edbc 331 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 332 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 171:3a7713b1edbc 333 \brief Type definitions for the NVIC Registers
AnnaBridge 171:3a7713b1edbc 334 @{
AnnaBridge 171:3a7713b1edbc 335 */
AnnaBridge 171:3a7713b1edbc 336
AnnaBridge 171:3a7713b1edbc 337 /**
AnnaBridge 171:3a7713b1edbc 338 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 171:3a7713b1edbc 339 */
AnnaBridge 171:3a7713b1edbc 340 typedef struct
AnnaBridge 171:3a7713b1edbc 341 {
AnnaBridge 171:3a7713b1edbc 342 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 171:3a7713b1edbc 343 uint32_t RESERVED0[24U];
AnnaBridge 171:3a7713b1edbc 344 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 171:3a7713b1edbc 345 uint32_t RSERVED1[24U];
AnnaBridge 171:3a7713b1edbc 346 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 171:3a7713b1edbc 347 uint32_t RESERVED2[24U];
AnnaBridge 171:3a7713b1edbc 348 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 171:3a7713b1edbc 349 uint32_t RESERVED3[24U];
AnnaBridge 171:3a7713b1edbc 350 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 171:3a7713b1edbc 351 uint32_t RESERVED4[56U];
AnnaBridge 171:3a7713b1edbc 352 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
AnnaBridge 171:3a7713b1edbc 353 uint32_t RESERVED5[644U];
AnnaBridge 171:3a7713b1edbc 354 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
AnnaBridge 171:3a7713b1edbc 355 } NVIC_Type;
AnnaBridge 171:3a7713b1edbc 356
AnnaBridge 171:3a7713b1edbc 357 /* Software Triggered Interrupt Register Definitions */
AnnaBridge 171:3a7713b1edbc 358 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
AnnaBridge 171:3a7713b1edbc 359 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
AnnaBridge 171:3a7713b1edbc 360
AnnaBridge 171:3a7713b1edbc 361 /*@} end of group CMSIS_NVIC */
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363
AnnaBridge 171:3a7713b1edbc 364 /**
AnnaBridge 171:3a7713b1edbc 365 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 366 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 171:3a7713b1edbc 367 \brief Type definitions for the System Control Block Registers
AnnaBridge 171:3a7713b1edbc 368 @{
AnnaBridge 171:3a7713b1edbc 369 */
AnnaBridge 171:3a7713b1edbc 370
AnnaBridge 171:3a7713b1edbc 371 /**
AnnaBridge 171:3a7713b1edbc 372 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 171:3a7713b1edbc 373 */
AnnaBridge 171:3a7713b1edbc 374 typedef struct
AnnaBridge 171:3a7713b1edbc 375 {
AnnaBridge 171:3a7713b1edbc 376 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 171:3a7713b1edbc 377 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 171:3a7713b1edbc 378 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 171:3a7713b1edbc 379 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 171:3a7713b1edbc 380 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 171:3a7713b1edbc 381 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 171:3a7713b1edbc 382 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
AnnaBridge 171:3a7713b1edbc 383 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 171:3a7713b1edbc 384 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
AnnaBridge 171:3a7713b1edbc 385 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
AnnaBridge 171:3a7713b1edbc 386 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
AnnaBridge 171:3a7713b1edbc 387 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
AnnaBridge 171:3a7713b1edbc 388 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
AnnaBridge 171:3a7713b1edbc 389 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
AnnaBridge 171:3a7713b1edbc 390 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
AnnaBridge 171:3a7713b1edbc 391 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
AnnaBridge 171:3a7713b1edbc 392 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
AnnaBridge 171:3a7713b1edbc 393 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
AnnaBridge 171:3a7713b1edbc 394 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
AnnaBridge 171:3a7713b1edbc 395 uint32_t RESERVED0[5U];
AnnaBridge 171:3a7713b1edbc 396 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
AnnaBridge 171:3a7713b1edbc 397 uint32_t RESERVED1[129U];
AnnaBridge 171:3a7713b1edbc 398 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
AnnaBridge 171:3a7713b1edbc 399 } SCB_Type;
AnnaBridge 171:3a7713b1edbc 400
AnnaBridge 171:3a7713b1edbc 401 /* SCB CPUID Register Definitions */
AnnaBridge 171:3a7713b1edbc 402 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 171:3a7713b1edbc 403 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 171:3a7713b1edbc 404
AnnaBridge 171:3a7713b1edbc 405 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 171:3a7713b1edbc 406 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 171:3a7713b1edbc 407
AnnaBridge 171:3a7713b1edbc 408 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 171:3a7713b1edbc 409 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 171:3a7713b1edbc 410
AnnaBridge 171:3a7713b1edbc 411 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 171:3a7713b1edbc 412 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 171:3a7713b1edbc 413
AnnaBridge 171:3a7713b1edbc 414 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 171:3a7713b1edbc 415 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 171:3a7713b1edbc 416
AnnaBridge 171:3a7713b1edbc 417 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 171:3a7713b1edbc 418 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 171:3a7713b1edbc 419 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 171:3a7713b1edbc 420
AnnaBridge 171:3a7713b1edbc 421 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 171:3a7713b1edbc 422 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 171:3a7713b1edbc 423
AnnaBridge 171:3a7713b1edbc 424 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 171:3a7713b1edbc 425 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 171:3a7713b1edbc 428 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 171:3a7713b1edbc 429
AnnaBridge 171:3a7713b1edbc 430 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 171:3a7713b1edbc 431 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 171:3a7713b1edbc 432
AnnaBridge 171:3a7713b1edbc 433 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 171:3a7713b1edbc 434 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 171:3a7713b1edbc 435
AnnaBridge 171:3a7713b1edbc 436 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 171:3a7713b1edbc 437 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 171:3a7713b1edbc 438
AnnaBridge 171:3a7713b1edbc 439 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 171:3a7713b1edbc 440 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 171:3a7713b1edbc 441
AnnaBridge 171:3a7713b1edbc 442 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 171:3a7713b1edbc 443 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 171:3a7713b1edbc 444
AnnaBridge 171:3a7713b1edbc 445 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 171:3a7713b1edbc 446 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 447
AnnaBridge 171:3a7713b1edbc 448 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 171:3a7713b1edbc 449 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
AnnaBridge 171:3a7713b1edbc 450 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
AnnaBridge 171:3a7713b1edbc 451
AnnaBridge 171:3a7713b1edbc 452 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 171:3a7713b1edbc 453 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 171:3a7713b1edbc 454
AnnaBridge 171:3a7713b1edbc 455 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 456 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 171:3a7713b1edbc 457 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 171:3a7713b1edbc 458
AnnaBridge 171:3a7713b1edbc 459 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 171:3a7713b1edbc 460 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 171:3a7713b1edbc 461
AnnaBridge 171:3a7713b1edbc 462 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 171:3a7713b1edbc 463 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 171:3a7713b1edbc 464
AnnaBridge 171:3a7713b1edbc 465 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
AnnaBridge 171:3a7713b1edbc 466 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
AnnaBridge 171:3a7713b1edbc 467
AnnaBridge 171:3a7713b1edbc 468 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 171:3a7713b1edbc 469 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 171:3a7713b1edbc 470
AnnaBridge 171:3a7713b1edbc 471 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 171:3a7713b1edbc 472 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 473
AnnaBridge 171:3a7713b1edbc 474 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
AnnaBridge 171:3a7713b1edbc 475 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 /* SCB System Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 478 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 171:3a7713b1edbc 479 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 171:3a7713b1edbc 480
AnnaBridge 171:3a7713b1edbc 481 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 171:3a7713b1edbc 482 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 171:3a7713b1edbc 483
AnnaBridge 171:3a7713b1edbc 484 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 171:3a7713b1edbc 485 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 171:3a7713b1edbc 486
AnnaBridge 171:3a7713b1edbc 487 /* SCB Configuration Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 488 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 171:3a7713b1edbc 489 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 171:3a7713b1edbc 492 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 171:3a7713b1edbc 495 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 171:3a7713b1edbc 498 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 171:3a7713b1edbc 499
AnnaBridge 171:3a7713b1edbc 500 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 171:3a7713b1edbc 501 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 171:3a7713b1edbc 502
AnnaBridge 171:3a7713b1edbc 503 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
AnnaBridge 171:3a7713b1edbc 504 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
AnnaBridge 171:3a7713b1edbc 505
AnnaBridge 171:3a7713b1edbc 506 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 171:3a7713b1edbc 507 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
AnnaBridge 171:3a7713b1edbc 508 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
AnnaBridge 171:3a7713b1edbc 509
AnnaBridge 171:3a7713b1edbc 510 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
AnnaBridge 171:3a7713b1edbc 511 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
AnnaBridge 171:3a7713b1edbc 512
AnnaBridge 171:3a7713b1edbc 513 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
AnnaBridge 171:3a7713b1edbc 514 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
AnnaBridge 171:3a7713b1edbc 515
AnnaBridge 171:3a7713b1edbc 516 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 171:3a7713b1edbc 517 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 171:3a7713b1edbc 518
AnnaBridge 171:3a7713b1edbc 519 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
AnnaBridge 171:3a7713b1edbc 520 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
AnnaBridge 171:3a7713b1edbc 521
AnnaBridge 171:3a7713b1edbc 522 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
AnnaBridge 171:3a7713b1edbc 523 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
AnnaBridge 171:3a7713b1edbc 524
AnnaBridge 171:3a7713b1edbc 525 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
AnnaBridge 171:3a7713b1edbc 526 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
AnnaBridge 171:3a7713b1edbc 527
AnnaBridge 171:3a7713b1edbc 528 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 171:3a7713b1edbc 529 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 171:3a7713b1edbc 530
AnnaBridge 171:3a7713b1edbc 531 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 171:3a7713b1edbc 532 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 171:3a7713b1edbc 533
AnnaBridge 171:3a7713b1edbc 534 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
AnnaBridge 171:3a7713b1edbc 535 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
AnnaBridge 171:3a7713b1edbc 536
AnnaBridge 171:3a7713b1edbc 537 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 171:3a7713b1edbc 538 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 171:3a7713b1edbc 539
AnnaBridge 171:3a7713b1edbc 540 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
AnnaBridge 171:3a7713b1edbc 541 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
AnnaBridge 171:3a7713b1edbc 542
AnnaBridge 171:3a7713b1edbc 543 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
AnnaBridge 171:3a7713b1edbc 544 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
AnnaBridge 171:3a7713b1edbc 545
AnnaBridge 171:3a7713b1edbc 546 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
AnnaBridge 171:3a7713b1edbc 547 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
AnnaBridge 171:3a7713b1edbc 548
AnnaBridge 171:3a7713b1edbc 549 /* SCB Configurable Fault Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 550 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
AnnaBridge 171:3a7713b1edbc 551 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
AnnaBridge 171:3a7713b1edbc 552
AnnaBridge 171:3a7713b1edbc 553 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
AnnaBridge 171:3a7713b1edbc 554 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
AnnaBridge 171:3a7713b1edbc 555
AnnaBridge 171:3a7713b1edbc 556 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
AnnaBridge 171:3a7713b1edbc 557 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
AnnaBridge 171:3a7713b1edbc 558
AnnaBridge 171:3a7713b1edbc 559 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 171:3a7713b1edbc 560 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
AnnaBridge 171:3a7713b1edbc 561 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
AnnaBridge 171:3a7713b1edbc 562
AnnaBridge 171:3a7713b1edbc 563 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
AnnaBridge 171:3a7713b1edbc 564 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
AnnaBridge 171:3a7713b1edbc 565
AnnaBridge 171:3a7713b1edbc 566 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
AnnaBridge 171:3a7713b1edbc 567 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
AnnaBridge 171:3a7713b1edbc 568
AnnaBridge 171:3a7713b1edbc 569 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
AnnaBridge 171:3a7713b1edbc 570 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
AnnaBridge 171:3a7713b1edbc 571
AnnaBridge 171:3a7713b1edbc 572 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
AnnaBridge 171:3a7713b1edbc 573 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
AnnaBridge 171:3a7713b1edbc 574
AnnaBridge 171:3a7713b1edbc 575 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 171:3a7713b1edbc 576 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
AnnaBridge 171:3a7713b1edbc 577 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
AnnaBridge 171:3a7713b1edbc 578
AnnaBridge 171:3a7713b1edbc 579 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
AnnaBridge 171:3a7713b1edbc 580 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
AnnaBridge 171:3a7713b1edbc 581
AnnaBridge 171:3a7713b1edbc 582 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
AnnaBridge 171:3a7713b1edbc 583 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
AnnaBridge 171:3a7713b1edbc 584
AnnaBridge 171:3a7713b1edbc 585 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
AnnaBridge 171:3a7713b1edbc 586 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
AnnaBridge 171:3a7713b1edbc 587
AnnaBridge 171:3a7713b1edbc 588 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
AnnaBridge 171:3a7713b1edbc 589 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
AnnaBridge 171:3a7713b1edbc 590
AnnaBridge 171:3a7713b1edbc 591 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
AnnaBridge 171:3a7713b1edbc 592 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 171:3a7713b1edbc 595 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
AnnaBridge 171:3a7713b1edbc 596 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
AnnaBridge 171:3a7713b1edbc 597
AnnaBridge 171:3a7713b1edbc 598 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
AnnaBridge 171:3a7713b1edbc 599 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
AnnaBridge 171:3a7713b1edbc 600
AnnaBridge 171:3a7713b1edbc 601 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
AnnaBridge 171:3a7713b1edbc 602 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
AnnaBridge 171:3a7713b1edbc 603
AnnaBridge 171:3a7713b1edbc 604 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
AnnaBridge 171:3a7713b1edbc 605 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
AnnaBridge 171:3a7713b1edbc 606
AnnaBridge 171:3a7713b1edbc 607 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
AnnaBridge 171:3a7713b1edbc 608 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
AnnaBridge 171:3a7713b1edbc 609
AnnaBridge 171:3a7713b1edbc 610 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
AnnaBridge 171:3a7713b1edbc 611 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
AnnaBridge 171:3a7713b1edbc 612
AnnaBridge 171:3a7713b1edbc 613 /* SCB Hard Fault Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 614 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
AnnaBridge 171:3a7713b1edbc 615 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
AnnaBridge 171:3a7713b1edbc 616
AnnaBridge 171:3a7713b1edbc 617 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
AnnaBridge 171:3a7713b1edbc 618 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
AnnaBridge 171:3a7713b1edbc 619
AnnaBridge 171:3a7713b1edbc 620 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
AnnaBridge 171:3a7713b1edbc 621 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
AnnaBridge 171:3a7713b1edbc 622
AnnaBridge 171:3a7713b1edbc 623 /* SCB Debug Fault Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 624 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
AnnaBridge 171:3a7713b1edbc 625 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
AnnaBridge 171:3a7713b1edbc 626
AnnaBridge 171:3a7713b1edbc 627 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
AnnaBridge 171:3a7713b1edbc 628 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
AnnaBridge 171:3a7713b1edbc 629
AnnaBridge 171:3a7713b1edbc 630 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
AnnaBridge 171:3a7713b1edbc 631 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
AnnaBridge 171:3a7713b1edbc 632
AnnaBridge 171:3a7713b1edbc 633 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
AnnaBridge 171:3a7713b1edbc 634 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
AnnaBridge 171:3a7713b1edbc 635
AnnaBridge 171:3a7713b1edbc 636 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
AnnaBridge 171:3a7713b1edbc 637 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
AnnaBridge 171:3a7713b1edbc 638
AnnaBridge 171:3a7713b1edbc 639 /*@} end of group CMSIS_SCB */
AnnaBridge 171:3a7713b1edbc 640
AnnaBridge 171:3a7713b1edbc 641
AnnaBridge 171:3a7713b1edbc 642 /**
AnnaBridge 171:3a7713b1edbc 643 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 644 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 171:3a7713b1edbc 645 \brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge 171:3a7713b1edbc 646 @{
AnnaBridge 171:3a7713b1edbc 647 */
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 /**
AnnaBridge 171:3a7713b1edbc 650 \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge 171:3a7713b1edbc 651 */
AnnaBridge 171:3a7713b1edbc 652 typedef struct
AnnaBridge 171:3a7713b1edbc 653 {
AnnaBridge 171:3a7713b1edbc 654 uint32_t RESERVED0[1U];
AnnaBridge 171:3a7713b1edbc 655 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
AnnaBridge 171:3a7713b1edbc 656 uint32_t RESERVED1[1U];
AnnaBridge 171:3a7713b1edbc 657 } SCnSCB_Type;
AnnaBridge 171:3a7713b1edbc 658
AnnaBridge 171:3a7713b1edbc 659 /* Interrupt Controller Type Register Definitions */
AnnaBridge 171:3a7713b1edbc 660 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
AnnaBridge 171:3a7713b1edbc 661 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
AnnaBridge 171:3a7713b1edbc 662
AnnaBridge 171:3a7713b1edbc 663 /*@} end of group CMSIS_SCnotSCB */
AnnaBridge 171:3a7713b1edbc 664
AnnaBridge 171:3a7713b1edbc 665
AnnaBridge 171:3a7713b1edbc 666 /**
AnnaBridge 171:3a7713b1edbc 667 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 668 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 171:3a7713b1edbc 669 \brief Type definitions for the System Timer Registers.
AnnaBridge 171:3a7713b1edbc 670 @{
AnnaBridge 171:3a7713b1edbc 671 */
AnnaBridge 171:3a7713b1edbc 672
AnnaBridge 171:3a7713b1edbc 673 /**
AnnaBridge 171:3a7713b1edbc 674 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 171:3a7713b1edbc 675 */
AnnaBridge 171:3a7713b1edbc 676 typedef struct
AnnaBridge 171:3a7713b1edbc 677 {
AnnaBridge 171:3a7713b1edbc 678 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 171:3a7713b1edbc 679 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 171:3a7713b1edbc 680 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 171:3a7713b1edbc 681 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 171:3a7713b1edbc 682 } SysTick_Type;
AnnaBridge 171:3a7713b1edbc 683
AnnaBridge 171:3a7713b1edbc 684 /* SysTick Control / Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 685 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 171:3a7713b1edbc 686 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 171:3a7713b1edbc 687
AnnaBridge 171:3a7713b1edbc 688 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 171:3a7713b1edbc 689 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 171:3a7713b1edbc 690
AnnaBridge 171:3a7713b1edbc 691 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 171:3a7713b1edbc 692 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 171:3a7713b1edbc 693
AnnaBridge 171:3a7713b1edbc 694 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 171:3a7713b1edbc 695 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 696
AnnaBridge 171:3a7713b1edbc 697 /* SysTick Reload Register Definitions */
AnnaBridge 171:3a7713b1edbc 698 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 171:3a7713b1edbc 699 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 171:3a7713b1edbc 700
AnnaBridge 171:3a7713b1edbc 701 /* SysTick Current Register Definitions */
AnnaBridge 171:3a7713b1edbc 702 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 171:3a7713b1edbc 703 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 171:3a7713b1edbc 704
AnnaBridge 171:3a7713b1edbc 705 /* SysTick Calibration Register Definitions */
AnnaBridge 171:3a7713b1edbc 706 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 171:3a7713b1edbc 707 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 171:3a7713b1edbc 708
AnnaBridge 171:3a7713b1edbc 709 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 171:3a7713b1edbc 710 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 171:3a7713b1edbc 711
AnnaBridge 171:3a7713b1edbc 712 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 171:3a7713b1edbc 713 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 171:3a7713b1edbc 714
AnnaBridge 171:3a7713b1edbc 715 /*@} end of group CMSIS_SysTick */
AnnaBridge 171:3a7713b1edbc 716
AnnaBridge 171:3a7713b1edbc 717
AnnaBridge 171:3a7713b1edbc 718 /**
AnnaBridge 171:3a7713b1edbc 719 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 720 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge 171:3a7713b1edbc 721 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge 171:3a7713b1edbc 722 @{
AnnaBridge 171:3a7713b1edbc 723 */
AnnaBridge 171:3a7713b1edbc 724
AnnaBridge 171:3a7713b1edbc 725 /**
AnnaBridge 171:3a7713b1edbc 726 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge 171:3a7713b1edbc 727 */
AnnaBridge 171:3a7713b1edbc 728 typedef struct
AnnaBridge 171:3a7713b1edbc 729 {
AnnaBridge 171:3a7713b1edbc 730 __OM union
AnnaBridge 171:3a7713b1edbc 731 {
AnnaBridge 171:3a7713b1edbc 732 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
AnnaBridge 171:3a7713b1edbc 733 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
AnnaBridge 171:3a7713b1edbc 734 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
AnnaBridge 171:3a7713b1edbc 735 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
AnnaBridge 171:3a7713b1edbc 736 uint32_t RESERVED0[864U];
AnnaBridge 171:3a7713b1edbc 737 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
AnnaBridge 171:3a7713b1edbc 738 uint32_t RESERVED1[15U];
AnnaBridge 171:3a7713b1edbc 739 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
AnnaBridge 171:3a7713b1edbc 740 uint32_t RESERVED2[15U];
AnnaBridge 171:3a7713b1edbc 741 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
AnnaBridge 171:3a7713b1edbc 742 uint32_t RESERVED3[29U];
AnnaBridge 171:3a7713b1edbc 743 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
AnnaBridge 171:3a7713b1edbc 744 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
AnnaBridge 171:3a7713b1edbc 745 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
AnnaBridge 171:3a7713b1edbc 746 uint32_t RESERVED4[43U];
AnnaBridge 171:3a7713b1edbc 747 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
AnnaBridge 171:3a7713b1edbc 748 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
AnnaBridge 171:3a7713b1edbc 749 uint32_t RESERVED5[6U];
AnnaBridge 171:3a7713b1edbc 750 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
AnnaBridge 171:3a7713b1edbc 751 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
AnnaBridge 171:3a7713b1edbc 752 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
AnnaBridge 171:3a7713b1edbc 753 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
AnnaBridge 171:3a7713b1edbc 754 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
AnnaBridge 171:3a7713b1edbc 755 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
AnnaBridge 171:3a7713b1edbc 756 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
AnnaBridge 171:3a7713b1edbc 757 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
AnnaBridge 171:3a7713b1edbc 758 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
AnnaBridge 171:3a7713b1edbc 759 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
AnnaBridge 171:3a7713b1edbc 760 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
AnnaBridge 171:3a7713b1edbc 761 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
AnnaBridge 171:3a7713b1edbc 762 } ITM_Type;
AnnaBridge 171:3a7713b1edbc 763
AnnaBridge 171:3a7713b1edbc 764 /* ITM Trace Privilege Register Definitions */
AnnaBridge 171:3a7713b1edbc 765 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
AnnaBridge 171:3a7713b1edbc 766 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
AnnaBridge 171:3a7713b1edbc 767
AnnaBridge 171:3a7713b1edbc 768 /* ITM Trace Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 769 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
AnnaBridge 171:3a7713b1edbc 770 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
AnnaBridge 171:3a7713b1edbc 771
AnnaBridge 171:3a7713b1edbc 772 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
AnnaBridge 171:3a7713b1edbc 773 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
AnnaBridge 171:3a7713b1edbc 774
AnnaBridge 171:3a7713b1edbc 775 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
AnnaBridge 171:3a7713b1edbc 776 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
AnnaBridge 171:3a7713b1edbc 777
AnnaBridge 171:3a7713b1edbc 778 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
AnnaBridge 171:3a7713b1edbc 779 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
AnnaBridge 171:3a7713b1edbc 780
AnnaBridge 171:3a7713b1edbc 781 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
AnnaBridge 171:3a7713b1edbc 782 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
AnnaBridge 171:3a7713b1edbc 783
AnnaBridge 171:3a7713b1edbc 784 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
AnnaBridge 171:3a7713b1edbc 785 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
AnnaBridge 171:3a7713b1edbc 786
AnnaBridge 171:3a7713b1edbc 787 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
AnnaBridge 171:3a7713b1edbc 788 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
AnnaBridge 171:3a7713b1edbc 789
AnnaBridge 171:3a7713b1edbc 790 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
AnnaBridge 171:3a7713b1edbc 791 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
AnnaBridge 171:3a7713b1edbc 792
AnnaBridge 171:3a7713b1edbc 793 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
AnnaBridge 171:3a7713b1edbc 794 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
AnnaBridge 171:3a7713b1edbc 795
AnnaBridge 171:3a7713b1edbc 796 /* ITM Integration Write Register Definitions */
AnnaBridge 171:3a7713b1edbc 797 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
AnnaBridge 171:3a7713b1edbc 798 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
AnnaBridge 171:3a7713b1edbc 799
AnnaBridge 171:3a7713b1edbc 800 /* ITM Integration Read Register Definitions */
AnnaBridge 171:3a7713b1edbc 801 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
AnnaBridge 171:3a7713b1edbc 802 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
AnnaBridge 171:3a7713b1edbc 803
AnnaBridge 171:3a7713b1edbc 804 /* ITM Integration Mode Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 805 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
AnnaBridge 171:3a7713b1edbc 806 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
AnnaBridge 171:3a7713b1edbc 807
AnnaBridge 171:3a7713b1edbc 808 /* ITM Lock Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 809 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
AnnaBridge 171:3a7713b1edbc 810 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
AnnaBridge 171:3a7713b1edbc 811
AnnaBridge 171:3a7713b1edbc 812 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
AnnaBridge 171:3a7713b1edbc 813 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
AnnaBridge 171:3a7713b1edbc 814
AnnaBridge 171:3a7713b1edbc 815 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
AnnaBridge 171:3a7713b1edbc 816 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
AnnaBridge 171:3a7713b1edbc 817
AnnaBridge 171:3a7713b1edbc 818 /*@}*/ /* end of group CMSIS_ITM */
AnnaBridge 171:3a7713b1edbc 819
AnnaBridge 171:3a7713b1edbc 820
AnnaBridge 171:3a7713b1edbc 821 /**
AnnaBridge 171:3a7713b1edbc 822 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 823 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 171:3a7713b1edbc 824 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 171:3a7713b1edbc 825 @{
AnnaBridge 171:3a7713b1edbc 826 */
AnnaBridge 171:3a7713b1edbc 827
AnnaBridge 171:3a7713b1edbc 828 /**
AnnaBridge 171:3a7713b1edbc 829 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 171:3a7713b1edbc 830 */
AnnaBridge 171:3a7713b1edbc 831 typedef struct
AnnaBridge 171:3a7713b1edbc 832 {
AnnaBridge 171:3a7713b1edbc 833 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 171:3a7713b1edbc 834 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
AnnaBridge 171:3a7713b1edbc 835 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
AnnaBridge 171:3a7713b1edbc 836 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
AnnaBridge 171:3a7713b1edbc 837 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
AnnaBridge 171:3a7713b1edbc 838 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
AnnaBridge 171:3a7713b1edbc 839 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
AnnaBridge 171:3a7713b1edbc 840 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 171:3a7713b1edbc 841 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 171:3a7713b1edbc 842 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
AnnaBridge 171:3a7713b1edbc 843 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 171:3a7713b1edbc 844 uint32_t RESERVED0[1U];
AnnaBridge 171:3a7713b1edbc 845 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 171:3a7713b1edbc 846 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
AnnaBridge 171:3a7713b1edbc 847 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 171:3a7713b1edbc 848 uint32_t RESERVED1[1U];
AnnaBridge 171:3a7713b1edbc 849 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 171:3a7713b1edbc 850 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
AnnaBridge 171:3a7713b1edbc 851 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 171:3a7713b1edbc 852 uint32_t RESERVED2[1U];
AnnaBridge 171:3a7713b1edbc 853 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 171:3a7713b1edbc 854 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
AnnaBridge 171:3a7713b1edbc 855 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 171:3a7713b1edbc 856 } DWT_Type;
AnnaBridge 171:3a7713b1edbc 857
AnnaBridge 171:3a7713b1edbc 858 /* DWT Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 859 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 171:3a7713b1edbc 860 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 171:3a7713b1edbc 861
AnnaBridge 171:3a7713b1edbc 862 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 171:3a7713b1edbc 863 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 171:3a7713b1edbc 864
AnnaBridge 171:3a7713b1edbc 865 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 171:3a7713b1edbc 866 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 171:3a7713b1edbc 867
AnnaBridge 171:3a7713b1edbc 868 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 171:3a7713b1edbc 869 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 171:3a7713b1edbc 870
AnnaBridge 171:3a7713b1edbc 871 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 171:3a7713b1edbc 872 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 171:3a7713b1edbc 873
AnnaBridge 171:3a7713b1edbc 874 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
AnnaBridge 171:3a7713b1edbc 875 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
AnnaBridge 171:3a7713b1edbc 876
AnnaBridge 171:3a7713b1edbc 877 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
AnnaBridge 171:3a7713b1edbc 878 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
AnnaBridge 171:3a7713b1edbc 879
AnnaBridge 171:3a7713b1edbc 880 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
AnnaBridge 171:3a7713b1edbc 881 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
AnnaBridge 171:3a7713b1edbc 882
AnnaBridge 171:3a7713b1edbc 883 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
AnnaBridge 171:3a7713b1edbc 884 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
AnnaBridge 171:3a7713b1edbc 885
AnnaBridge 171:3a7713b1edbc 886 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
AnnaBridge 171:3a7713b1edbc 887 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
AnnaBridge 171:3a7713b1edbc 888
AnnaBridge 171:3a7713b1edbc 889 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
AnnaBridge 171:3a7713b1edbc 890 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
AnnaBridge 171:3a7713b1edbc 891
AnnaBridge 171:3a7713b1edbc 892 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
AnnaBridge 171:3a7713b1edbc 893 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
AnnaBridge 171:3a7713b1edbc 894
AnnaBridge 171:3a7713b1edbc 895 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
AnnaBridge 171:3a7713b1edbc 896 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
AnnaBridge 171:3a7713b1edbc 897
AnnaBridge 171:3a7713b1edbc 898 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
AnnaBridge 171:3a7713b1edbc 899 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
AnnaBridge 171:3a7713b1edbc 900
AnnaBridge 171:3a7713b1edbc 901 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
AnnaBridge 171:3a7713b1edbc 902 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
AnnaBridge 171:3a7713b1edbc 903
AnnaBridge 171:3a7713b1edbc 904 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
AnnaBridge 171:3a7713b1edbc 905 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
AnnaBridge 171:3a7713b1edbc 906
AnnaBridge 171:3a7713b1edbc 907 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
AnnaBridge 171:3a7713b1edbc 908 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
AnnaBridge 171:3a7713b1edbc 909
AnnaBridge 171:3a7713b1edbc 910 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
AnnaBridge 171:3a7713b1edbc 911 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
AnnaBridge 171:3a7713b1edbc 912
AnnaBridge 171:3a7713b1edbc 913 /* DWT CPI Count Register Definitions */
AnnaBridge 171:3a7713b1edbc 914 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
AnnaBridge 171:3a7713b1edbc 915 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
AnnaBridge 171:3a7713b1edbc 916
AnnaBridge 171:3a7713b1edbc 917 /* DWT Exception Overhead Count Register Definitions */
AnnaBridge 171:3a7713b1edbc 918 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
AnnaBridge 171:3a7713b1edbc 919 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
AnnaBridge 171:3a7713b1edbc 920
AnnaBridge 171:3a7713b1edbc 921 /* DWT Sleep Count Register Definitions */
AnnaBridge 171:3a7713b1edbc 922 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
AnnaBridge 171:3a7713b1edbc 923 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
AnnaBridge 171:3a7713b1edbc 924
AnnaBridge 171:3a7713b1edbc 925 /* DWT LSU Count Register Definitions */
AnnaBridge 171:3a7713b1edbc 926 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
AnnaBridge 171:3a7713b1edbc 927 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
AnnaBridge 171:3a7713b1edbc 928
AnnaBridge 171:3a7713b1edbc 929 /* DWT Folded-instruction Count Register Definitions */
AnnaBridge 171:3a7713b1edbc 930 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
AnnaBridge 171:3a7713b1edbc 931 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
AnnaBridge 171:3a7713b1edbc 932
AnnaBridge 171:3a7713b1edbc 933 /* DWT Comparator Mask Register Definitions */
AnnaBridge 171:3a7713b1edbc 934 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
AnnaBridge 171:3a7713b1edbc 935 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
AnnaBridge 171:3a7713b1edbc 936
AnnaBridge 171:3a7713b1edbc 937 /* DWT Comparator Function Register Definitions */
AnnaBridge 171:3a7713b1edbc 938 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 171:3a7713b1edbc 939 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 171:3a7713b1edbc 940
AnnaBridge 171:3a7713b1edbc 941 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
AnnaBridge 171:3a7713b1edbc 942 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
AnnaBridge 171:3a7713b1edbc 943
AnnaBridge 171:3a7713b1edbc 944 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
AnnaBridge 171:3a7713b1edbc 945 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
AnnaBridge 171:3a7713b1edbc 946
AnnaBridge 171:3a7713b1edbc 947 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 171:3a7713b1edbc 948 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 171:3a7713b1edbc 949
AnnaBridge 171:3a7713b1edbc 950 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
AnnaBridge 171:3a7713b1edbc 951 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
AnnaBridge 171:3a7713b1edbc 952
AnnaBridge 171:3a7713b1edbc 953 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
AnnaBridge 171:3a7713b1edbc 954 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
AnnaBridge 171:3a7713b1edbc 955
AnnaBridge 171:3a7713b1edbc 956 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
AnnaBridge 171:3a7713b1edbc 957 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
AnnaBridge 171:3a7713b1edbc 958
AnnaBridge 171:3a7713b1edbc 959 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
AnnaBridge 171:3a7713b1edbc 960 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
AnnaBridge 171:3a7713b1edbc 961
AnnaBridge 171:3a7713b1edbc 962 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
AnnaBridge 171:3a7713b1edbc 963 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
AnnaBridge 171:3a7713b1edbc 964
AnnaBridge 171:3a7713b1edbc 965 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 171:3a7713b1edbc 966
AnnaBridge 171:3a7713b1edbc 967
AnnaBridge 171:3a7713b1edbc 968 /**
AnnaBridge 171:3a7713b1edbc 969 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 970 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 171:3a7713b1edbc 971 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 171:3a7713b1edbc 972 @{
AnnaBridge 171:3a7713b1edbc 973 */
AnnaBridge 171:3a7713b1edbc 974
AnnaBridge 171:3a7713b1edbc 975 /**
AnnaBridge 171:3a7713b1edbc 976 \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 171:3a7713b1edbc 977 */
AnnaBridge 171:3a7713b1edbc 978 typedef struct
AnnaBridge 171:3a7713b1edbc 979 {
AnnaBridge 171:3a7713b1edbc 980 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 171:3a7713b1edbc 981 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 171:3a7713b1edbc 982 uint32_t RESERVED0[2U];
AnnaBridge 171:3a7713b1edbc 983 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 171:3a7713b1edbc 984 uint32_t RESERVED1[55U];
AnnaBridge 171:3a7713b1edbc 985 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 171:3a7713b1edbc 986 uint32_t RESERVED2[131U];
AnnaBridge 171:3a7713b1edbc 987 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 171:3a7713b1edbc 988 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 171:3a7713b1edbc 989 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
AnnaBridge 171:3a7713b1edbc 990 uint32_t RESERVED3[759U];
AnnaBridge 171:3a7713b1edbc 991 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
AnnaBridge 171:3a7713b1edbc 992 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
AnnaBridge 171:3a7713b1edbc 993 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
AnnaBridge 171:3a7713b1edbc 994 uint32_t RESERVED4[1U];
AnnaBridge 171:3a7713b1edbc 995 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
AnnaBridge 171:3a7713b1edbc 996 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
AnnaBridge 171:3a7713b1edbc 997 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 171:3a7713b1edbc 998 uint32_t RESERVED5[39U];
AnnaBridge 171:3a7713b1edbc 999 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 171:3a7713b1edbc 1000 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 171:3a7713b1edbc 1001 uint32_t RESERVED7[8U];
AnnaBridge 171:3a7713b1edbc 1002 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
AnnaBridge 171:3a7713b1edbc 1003 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
AnnaBridge 171:3a7713b1edbc 1004 } TPI_Type;
AnnaBridge 171:3a7713b1edbc 1005
AnnaBridge 171:3a7713b1edbc 1006 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 171:3a7713b1edbc 1007 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
AnnaBridge 171:3a7713b1edbc 1008 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
AnnaBridge 171:3a7713b1edbc 1009
AnnaBridge 171:3a7713b1edbc 1010 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 171:3a7713b1edbc 1011 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
AnnaBridge 171:3a7713b1edbc 1012 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 171:3a7713b1edbc 1013
AnnaBridge 171:3a7713b1edbc 1014 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 1015 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 171:3a7713b1edbc 1016 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 171:3a7713b1edbc 1017
AnnaBridge 171:3a7713b1edbc 1018 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
AnnaBridge 171:3a7713b1edbc 1019 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 171:3a7713b1edbc 1020
AnnaBridge 171:3a7713b1edbc 1021 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
AnnaBridge 171:3a7713b1edbc 1022 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 171:3a7713b1edbc 1023
AnnaBridge 171:3a7713b1edbc 1024 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
AnnaBridge 171:3a7713b1edbc 1025 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 171:3a7713b1edbc 1026
AnnaBridge 171:3a7713b1edbc 1027 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1028 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
AnnaBridge 171:3a7713b1edbc 1029 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 171:3a7713b1edbc 1030
AnnaBridge 171:3a7713b1edbc 1031 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
AnnaBridge 171:3a7713b1edbc 1032 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 171:3a7713b1edbc 1033
AnnaBridge 171:3a7713b1edbc 1034 /* TPI TRIGGER Register Definitions */
AnnaBridge 171:3a7713b1edbc 1035 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
AnnaBridge 171:3a7713b1edbc 1036 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
AnnaBridge 171:3a7713b1edbc 1037
AnnaBridge 171:3a7713b1edbc 1038 /* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge 171:3a7713b1edbc 1039 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
AnnaBridge 171:3a7713b1edbc 1040 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
AnnaBridge 171:3a7713b1edbc 1041
AnnaBridge 171:3a7713b1edbc 1042 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
AnnaBridge 171:3a7713b1edbc 1043 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
AnnaBridge 171:3a7713b1edbc 1044
AnnaBridge 171:3a7713b1edbc 1045 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
AnnaBridge 171:3a7713b1edbc 1046 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
AnnaBridge 171:3a7713b1edbc 1047
AnnaBridge 171:3a7713b1edbc 1048 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
AnnaBridge 171:3a7713b1edbc 1049 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
AnnaBridge 171:3a7713b1edbc 1050
AnnaBridge 171:3a7713b1edbc 1051 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
AnnaBridge 171:3a7713b1edbc 1052 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
AnnaBridge 171:3a7713b1edbc 1053
AnnaBridge 171:3a7713b1edbc 1054 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
AnnaBridge 171:3a7713b1edbc 1055 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
AnnaBridge 171:3a7713b1edbc 1056
AnnaBridge 171:3a7713b1edbc 1057 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
AnnaBridge 171:3a7713b1edbc 1058 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
AnnaBridge 171:3a7713b1edbc 1059
AnnaBridge 171:3a7713b1edbc 1060 /* TPI ITATBCTR2 Register Definitions */
AnnaBridge 171:3a7713b1edbc 1061 #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
AnnaBridge 171:3a7713b1edbc 1062 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
AnnaBridge 171:3a7713b1edbc 1063
AnnaBridge 171:3a7713b1edbc 1064 #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
AnnaBridge 171:3a7713b1edbc 1065 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
AnnaBridge 171:3a7713b1edbc 1066
AnnaBridge 171:3a7713b1edbc 1067 /* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge 171:3a7713b1edbc 1068 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
AnnaBridge 171:3a7713b1edbc 1069 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
AnnaBridge 171:3a7713b1edbc 1070
AnnaBridge 171:3a7713b1edbc 1071 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
AnnaBridge 171:3a7713b1edbc 1072 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
AnnaBridge 171:3a7713b1edbc 1073
AnnaBridge 171:3a7713b1edbc 1074 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
AnnaBridge 171:3a7713b1edbc 1075 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
AnnaBridge 171:3a7713b1edbc 1076
AnnaBridge 171:3a7713b1edbc 1077 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
AnnaBridge 171:3a7713b1edbc 1078 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
AnnaBridge 171:3a7713b1edbc 1079
AnnaBridge 171:3a7713b1edbc 1080 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
AnnaBridge 171:3a7713b1edbc 1081 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
AnnaBridge 171:3a7713b1edbc 1082
AnnaBridge 171:3a7713b1edbc 1083 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
AnnaBridge 171:3a7713b1edbc 1084 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
AnnaBridge 171:3a7713b1edbc 1085
AnnaBridge 171:3a7713b1edbc 1086 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
AnnaBridge 171:3a7713b1edbc 1087 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
AnnaBridge 171:3a7713b1edbc 1088
AnnaBridge 171:3a7713b1edbc 1089 /* TPI ITATBCTR0 Register Definitions */
AnnaBridge 171:3a7713b1edbc 1090 #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
AnnaBridge 171:3a7713b1edbc 1091 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
AnnaBridge 171:3a7713b1edbc 1092
AnnaBridge 171:3a7713b1edbc 1093 #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
AnnaBridge 171:3a7713b1edbc 1094 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
AnnaBridge 171:3a7713b1edbc 1095
AnnaBridge 171:3a7713b1edbc 1096 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1097 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
AnnaBridge 171:3a7713b1edbc 1098 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
AnnaBridge 171:3a7713b1edbc 1099
AnnaBridge 171:3a7713b1edbc 1100 /* TPI DEVID Register Definitions */
AnnaBridge 171:3a7713b1edbc 1101 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 171:3a7713b1edbc 1102 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 171:3a7713b1edbc 1103
AnnaBridge 171:3a7713b1edbc 1104 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 171:3a7713b1edbc 1105 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 171:3a7713b1edbc 1106
AnnaBridge 171:3a7713b1edbc 1107 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 171:3a7713b1edbc 1108 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 171:3a7713b1edbc 1109
AnnaBridge 171:3a7713b1edbc 1110 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
AnnaBridge 171:3a7713b1edbc 1111 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
AnnaBridge 171:3a7713b1edbc 1112
AnnaBridge 171:3a7713b1edbc 1113 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
AnnaBridge 171:3a7713b1edbc 1114 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
AnnaBridge 171:3a7713b1edbc 1115
AnnaBridge 171:3a7713b1edbc 1116 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 171:3a7713b1edbc 1117 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
AnnaBridge 171:3a7713b1edbc 1118
AnnaBridge 171:3a7713b1edbc 1119 /* TPI DEVTYPE Register Definitions */
AnnaBridge 171:3a7713b1edbc 1120 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 171:3a7713b1edbc 1121 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 171:3a7713b1edbc 1122
AnnaBridge 171:3a7713b1edbc 1123 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 171:3a7713b1edbc 1124 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 171:3a7713b1edbc 1125
AnnaBridge 171:3a7713b1edbc 1126 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 171:3a7713b1edbc 1127
AnnaBridge 171:3a7713b1edbc 1128
AnnaBridge 171:3a7713b1edbc 1129 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 1130 /**
AnnaBridge 171:3a7713b1edbc 1131 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1132 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 171:3a7713b1edbc 1133 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 171:3a7713b1edbc 1134 @{
AnnaBridge 171:3a7713b1edbc 1135 */
AnnaBridge 171:3a7713b1edbc 1136
AnnaBridge 171:3a7713b1edbc 1137 /**
AnnaBridge 171:3a7713b1edbc 1138 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 171:3a7713b1edbc 1139 */
AnnaBridge 171:3a7713b1edbc 1140 typedef struct
AnnaBridge 171:3a7713b1edbc 1141 {
AnnaBridge 171:3a7713b1edbc 1142 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 171:3a7713b1edbc 1143 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 171:3a7713b1edbc 1144 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 171:3a7713b1edbc 1145 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 171:3a7713b1edbc 1146 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 171:3a7713b1edbc 1147 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
AnnaBridge 171:3a7713b1edbc 1148 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
AnnaBridge 171:3a7713b1edbc 1149 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
AnnaBridge 171:3a7713b1edbc 1150 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
AnnaBridge 171:3a7713b1edbc 1151 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
AnnaBridge 171:3a7713b1edbc 1152 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
AnnaBridge 171:3a7713b1edbc 1153 } MPU_Type;
AnnaBridge 171:3a7713b1edbc 1154
AnnaBridge 171:3a7713b1edbc 1155 /* MPU Type Register Definitions */
AnnaBridge 171:3a7713b1edbc 1156 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 171:3a7713b1edbc 1157 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 171:3a7713b1edbc 1158
AnnaBridge 171:3a7713b1edbc 1159 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 171:3a7713b1edbc 1160 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 171:3a7713b1edbc 1161
AnnaBridge 171:3a7713b1edbc 1162 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 171:3a7713b1edbc 1163 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 171:3a7713b1edbc 1164
AnnaBridge 171:3a7713b1edbc 1165 /* MPU Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1166 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 171:3a7713b1edbc 1167 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 171:3a7713b1edbc 1168
AnnaBridge 171:3a7713b1edbc 1169 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 171:3a7713b1edbc 1170 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 171:3a7713b1edbc 1171
AnnaBridge 171:3a7713b1edbc 1172 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 171:3a7713b1edbc 1173 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 1174
AnnaBridge 171:3a7713b1edbc 1175 /* MPU Region Number Register Definitions */
AnnaBridge 171:3a7713b1edbc 1176 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 171:3a7713b1edbc 1177 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 171:3a7713b1edbc 1178
AnnaBridge 171:3a7713b1edbc 1179 /* MPU Region Base Address Register Definitions */
AnnaBridge 171:3a7713b1edbc 1180 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
AnnaBridge 171:3a7713b1edbc 1181 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 171:3a7713b1edbc 1182
AnnaBridge 171:3a7713b1edbc 1183 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
AnnaBridge 171:3a7713b1edbc 1184 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 171:3a7713b1edbc 1185
AnnaBridge 171:3a7713b1edbc 1186 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
AnnaBridge 171:3a7713b1edbc 1187 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 171:3a7713b1edbc 1188
AnnaBridge 171:3a7713b1edbc 1189 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 171:3a7713b1edbc 1190 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 171:3a7713b1edbc 1191 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 171:3a7713b1edbc 1192
AnnaBridge 171:3a7713b1edbc 1193 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 171:3a7713b1edbc 1194 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 171:3a7713b1edbc 1195
AnnaBridge 171:3a7713b1edbc 1196 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 171:3a7713b1edbc 1197 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 171:3a7713b1edbc 1198
AnnaBridge 171:3a7713b1edbc 1199 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 171:3a7713b1edbc 1200 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 171:3a7713b1edbc 1201
AnnaBridge 171:3a7713b1edbc 1202 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 171:3a7713b1edbc 1203 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 171:3a7713b1edbc 1204
AnnaBridge 171:3a7713b1edbc 1205 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 171:3a7713b1edbc 1206 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 171:3a7713b1edbc 1207
AnnaBridge 171:3a7713b1edbc 1208 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 171:3a7713b1edbc 1209 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 171:3a7713b1edbc 1210
AnnaBridge 171:3a7713b1edbc 1211 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 171:3a7713b1edbc 1212 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 171:3a7713b1edbc 1213
AnnaBridge 171:3a7713b1edbc 1214 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
AnnaBridge 171:3a7713b1edbc 1215 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 171:3a7713b1edbc 1216
AnnaBridge 171:3a7713b1edbc 1217 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
AnnaBridge 171:3a7713b1edbc 1218 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 171:3a7713b1edbc 1219
AnnaBridge 171:3a7713b1edbc 1220 /*@} end of group CMSIS_MPU */
AnnaBridge 171:3a7713b1edbc 1221 #endif
AnnaBridge 171:3a7713b1edbc 1222
AnnaBridge 171:3a7713b1edbc 1223
AnnaBridge 171:3a7713b1edbc 1224 /**
AnnaBridge 171:3a7713b1edbc 1225 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1226 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 171:3a7713b1edbc 1227 \brief Type definitions for the Core Debug Registers
AnnaBridge 171:3a7713b1edbc 1228 @{
AnnaBridge 171:3a7713b1edbc 1229 */
AnnaBridge 171:3a7713b1edbc 1230
AnnaBridge 171:3a7713b1edbc 1231 /**
AnnaBridge 171:3a7713b1edbc 1232 \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 171:3a7713b1edbc 1233 */
AnnaBridge 171:3a7713b1edbc 1234 typedef struct
AnnaBridge 171:3a7713b1edbc 1235 {
AnnaBridge 171:3a7713b1edbc 1236 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 171:3a7713b1edbc 1237 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 171:3a7713b1edbc 1238 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 171:3a7713b1edbc 1239 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 171:3a7713b1edbc 1240 } CoreDebug_Type;
AnnaBridge 171:3a7713b1edbc 1241
AnnaBridge 171:3a7713b1edbc 1242 /* Debug Halting Control and Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 1243 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 171:3a7713b1edbc 1244 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 171:3a7713b1edbc 1245
AnnaBridge 171:3a7713b1edbc 1246 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 171:3a7713b1edbc 1247 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 171:3a7713b1edbc 1248
AnnaBridge 171:3a7713b1edbc 1249 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 171:3a7713b1edbc 1250 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 171:3a7713b1edbc 1251
AnnaBridge 171:3a7713b1edbc 1252 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 171:3a7713b1edbc 1253 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 171:3a7713b1edbc 1254
AnnaBridge 171:3a7713b1edbc 1255 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 171:3a7713b1edbc 1256 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 171:3a7713b1edbc 1257
AnnaBridge 171:3a7713b1edbc 1258 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 171:3a7713b1edbc 1259 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 171:3a7713b1edbc 1260
AnnaBridge 171:3a7713b1edbc 1261 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 171:3a7713b1edbc 1262 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 171:3a7713b1edbc 1263
AnnaBridge 171:3a7713b1edbc 1264 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
AnnaBridge 171:3a7713b1edbc 1265 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
AnnaBridge 171:3a7713b1edbc 1266
AnnaBridge 171:3a7713b1edbc 1267 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 171:3a7713b1edbc 1268 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 171:3a7713b1edbc 1269
AnnaBridge 171:3a7713b1edbc 1270 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 171:3a7713b1edbc 1271 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 171:3a7713b1edbc 1272
AnnaBridge 171:3a7713b1edbc 1273 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 171:3a7713b1edbc 1274 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 171:3a7713b1edbc 1275
AnnaBridge 171:3a7713b1edbc 1276 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 171:3a7713b1edbc 1277 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 171:3a7713b1edbc 1278
AnnaBridge 171:3a7713b1edbc 1279 /* Debug Core Register Selector Register Definitions */
AnnaBridge 171:3a7713b1edbc 1280 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 171:3a7713b1edbc 1281 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 171:3a7713b1edbc 1282
AnnaBridge 171:3a7713b1edbc 1283 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 171:3a7713b1edbc 1284 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 171:3a7713b1edbc 1285
AnnaBridge 171:3a7713b1edbc 1286 /* Debug Exception and Monitor Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1287 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
AnnaBridge 171:3a7713b1edbc 1288 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
AnnaBridge 171:3a7713b1edbc 1289
AnnaBridge 171:3a7713b1edbc 1290 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
AnnaBridge 171:3a7713b1edbc 1291 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
AnnaBridge 171:3a7713b1edbc 1292
AnnaBridge 171:3a7713b1edbc 1293 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
AnnaBridge 171:3a7713b1edbc 1294 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
AnnaBridge 171:3a7713b1edbc 1295
AnnaBridge 171:3a7713b1edbc 1296 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
AnnaBridge 171:3a7713b1edbc 1297 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
AnnaBridge 171:3a7713b1edbc 1298
AnnaBridge 171:3a7713b1edbc 1299 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
AnnaBridge 171:3a7713b1edbc 1300 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
AnnaBridge 171:3a7713b1edbc 1301
AnnaBridge 171:3a7713b1edbc 1302 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 171:3a7713b1edbc 1303 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 171:3a7713b1edbc 1304
AnnaBridge 171:3a7713b1edbc 1305 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
AnnaBridge 171:3a7713b1edbc 1306 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
AnnaBridge 171:3a7713b1edbc 1307
AnnaBridge 171:3a7713b1edbc 1308 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
AnnaBridge 171:3a7713b1edbc 1309 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
AnnaBridge 171:3a7713b1edbc 1310
AnnaBridge 171:3a7713b1edbc 1311 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
AnnaBridge 171:3a7713b1edbc 1312 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
AnnaBridge 171:3a7713b1edbc 1313
AnnaBridge 171:3a7713b1edbc 1314 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
AnnaBridge 171:3a7713b1edbc 1315 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
AnnaBridge 171:3a7713b1edbc 1316
AnnaBridge 171:3a7713b1edbc 1317 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
AnnaBridge 171:3a7713b1edbc 1318 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
AnnaBridge 171:3a7713b1edbc 1319
AnnaBridge 171:3a7713b1edbc 1320 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
AnnaBridge 171:3a7713b1edbc 1321 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
AnnaBridge 171:3a7713b1edbc 1322
AnnaBridge 171:3a7713b1edbc 1323 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 171:3a7713b1edbc 1324 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 171:3a7713b1edbc 1325
AnnaBridge 171:3a7713b1edbc 1326 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 171:3a7713b1edbc 1327
AnnaBridge 171:3a7713b1edbc 1328
AnnaBridge 171:3a7713b1edbc 1329 /**
AnnaBridge 171:3a7713b1edbc 1330 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1331 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 171:3a7713b1edbc 1332 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 171:3a7713b1edbc 1333 @{
AnnaBridge 171:3a7713b1edbc 1334 */
AnnaBridge 171:3a7713b1edbc 1335
AnnaBridge 171:3a7713b1edbc 1336 /**
AnnaBridge 171:3a7713b1edbc 1337 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 171:3a7713b1edbc 1338 \param[in] field Name of the register bit field.
AnnaBridge 171:3a7713b1edbc 1339 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 171:3a7713b1edbc 1340 \return Masked and shifted value.
AnnaBridge 171:3a7713b1edbc 1341 */
AnnaBridge 171:3a7713b1edbc 1342 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 171:3a7713b1edbc 1343
AnnaBridge 171:3a7713b1edbc 1344 /**
AnnaBridge 171:3a7713b1edbc 1345 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 171:3a7713b1edbc 1346 \param[in] field Name of the register bit field.
AnnaBridge 171:3a7713b1edbc 1347 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 171:3a7713b1edbc 1348 \return Masked and shifted bit field value.
AnnaBridge 171:3a7713b1edbc 1349 */
AnnaBridge 171:3a7713b1edbc 1350 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 171:3a7713b1edbc 1351
AnnaBridge 171:3a7713b1edbc 1352 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 171:3a7713b1edbc 1353
AnnaBridge 171:3a7713b1edbc 1354
AnnaBridge 171:3a7713b1edbc 1355 /**
AnnaBridge 171:3a7713b1edbc 1356 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1357 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 171:3a7713b1edbc 1358 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 171:3a7713b1edbc 1359 @{
AnnaBridge 171:3a7713b1edbc 1360 */
AnnaBridge 171:3a7713b1edbc 1361
AnnaBridge 171:3a7713b1edbc 1362 /* Memory mapping of Core Hardware */
AnnaBridge 171:3a7713b1edbc 1363 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 171:3a7713b1edbc 1364 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
AnnaBridge 171:3a7713b1edbc 1365 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 171:3a7713b1edbc 1366 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 171:3a7713b1edbc 1367 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 171:3a7713b1edbc 1368 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 171:3a7713b1edbc 1369 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 171:3a7713b1edbc 1370 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 171:3a7713b1edbc 1371
AnnaBridge 171:3a7713b1edbc 1372 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 171:3a7713b1edbc 1373 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 171:3a7713b1edbc 1374 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 171:3a7713b1edbc 1375 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 171:3a7713b1edbc 1376 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
AnnaBridge 171:3a7713b1edbc 1377 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 171:3a7713b1edbc 1378 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 171:3a7713b1edbc 1379 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
AnnaBridge 171:3a7713b1edbc 1380
AnnaBridge 171:3a7713b1edbc 1381 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 1382 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 171:3a7713b1edbc 1383 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 171:3a7713b1edbc 1384 #endif
AnnaBridge 171:3a7713b1edbc 1385
AnnaBridge 171:3a7713b1edbc 1386 /*@} */
AnnaBridge 171:3a7713b1edbc 1387
AnnaBridge 171:3a7713b1edbc 1388
AnnaBridge 171:3a7713b1edbc 1389
AnnaBridge 171:3a7713b1edbc 1390 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 1391 * Hardware Abstraction Layer
AnnaBridge 171:3a7713b1edbc 1392 Core Function Interface contains:
AnnaBridge 171:3a7713b1edbc 1393 - Core NVIC Functions
AnnaBridge 171:3a7713b1edbc 1394 - Core SysTick Functions
AnnaBridge 171:3a7713b1edbc 1395 - Core Debug Functions
AnnaBridge 171:3a7713b1edbc 1396 - Core Register Access Functions
AnnaBridge 171:3a7713b1edbc 1397 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1398 /**
AnnaBridge 171:3a7713b1edbc 1399 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 171:3a7713b1edbc 1400 */
AnnaBridge 171:3a7713b1edbc 1401
AnnaBridge 171:3a7713b1edbc 1402
AnnaBridge 171:3a7713b1edbc 1403
AnnaBridge 171:3a7713b1edbc 1404 /* ########################## NVIC functions #################################### */
AnnaBridge 171:3a7713b1edbc 1405 /**
AnnaBridge 171:3a7713b1edbc 1406 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 1407 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 171:3a7713b1edbc 1408 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 171:3a7713b1edbc 1409 @{
AnnaBridge 171:3a7713b1edbc 1410 */
AnnaBridge 171:3a7713b1edbc 1411
AnnaBridge 171:3a7713b1edbc 1412 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 171:3a7713b1edbc 1413 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 171:3a7713b1edbc 1414 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 171:3a7713b1edbc 1415 #endif
AnnaBridge 171:3a7713b1edbc 1416 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 171:3a7713b1edbc 1417 #else
AnnaBridge 171:3a7713b1edbc 1418 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge 171:3a7713b1edbc 1419 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge 171:3a7713b1edbc 1420 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 171:3a7713b1edbc 1421 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 171:3a7713b1edbc 1422 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 171:3a7713b1edbc 1423 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 171:3a7713b1edbc 1424 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 171:3a7713b1edbc 1425 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 171:3a7713b1edbc 1426 #define NVIC_GetActive __NVIC_GetActive
AnnaBridge 171:3a7713b1edbc 1427 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 171:3a7713b1edbc 1428 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 171:3a7713b1edbc 1429 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 171:3a7713b1edbc 1430 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 171:3a7713b1edbc 1431
AnnaBridge 171:3a7713b1edbc 1432 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 171:3a7713b1edbc 1433 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 171:3a7713b1edbc 1434 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 171:3a7713b1edbc 1435 #endif
AnnaBridge 171:3a7713b1edbc 1436 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 171:3a7713b1edbc 1437 #else
AnnaBridge 171:3a7713b1edbc 1438 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 171:3a7713b1edbc 1439 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 171:3a7713b1edbc 1440 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 171:3a7713b1edbc 1441
AnnaBridge 171:3a7713b1edbc 1442 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 171:3a7713b1edbc 1443
AnnaBridge 171:3a7713b1edbc 1444
AnnaBridge 171:3a7713b1edbc 1445 /* The following EXC_RETURN values are saved the LR on exception entry */
AnnaBridge 171:3a7713b1edbc 1446 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
AnnaBridge 171:3a7713b1edbc 1447 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
AnnaBridge 171:3a7713b1edbc 1448 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
AnnaBridge 171:3a7713b1edbc 1449
AnnaBridge 171:3a7713b1edbc 1450
AnnaBridge 171:3a7713b1edbc 1451
AnnaBridge 171:3a7713b1edbc 1452 /**
AnnaBridge 171:3a7713b1edbc 1453 \brief Set Priority Grouping
AnnaBridge 171:3a7713b1edbc 1454 \details Sets the priority grouping field using the required unlock sequence.
AnnaBridge 171:3a7713b1edbc 1455 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge 171:3a7713b1edbc 1456 Only values from 0..7 are used.
AnnaBridge 171:3a7713b1edbc 1457 In case of a conflict between priority grouping and available
AnnaBridge 171:3a7713b1edbc 1458 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 171:3a7713b1edbc 1459 \param [in] PriorityGroup Priority grouping field.
AnnaBridge 171:3a7713b1edbc 1460 */
AnnaBridge 171:3a7713b1edbc 1461 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge 171:3a7713b1edbc 1462 {
AnnaBridge 171:3a7713b1edbc 1463 uint32_t reg_value;
AnnaBridge 171:3a7713b1edbc 1464 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 171:3a7713b1edbc 1465
AnnaBridge 171:3a7713b1edbc 1466 reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge 171:3a7713b1edbc 1467 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge 171:3a7713b1edbc 1468 reg_value = (reg_value |
AnnaBridge 171:3a7713b1edbc 1469 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 171:3a7713b1edbc 1470 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
AnnaBridge 171:3a7713b1edbc 1471 SCB->AIRCR = reg_value;
AnnaBridge 171:3a7713b1edbc 1472 }
AnnaBridge 171:3a7713b1edbc 1473
AnnaBridge 171:3a7713b1edbc 1474
AnnaBridge 171:3a7713b1edbc 1475 /**
AnnaBridge 171:3a7713b1edbc 1476 \brief Get Priority Grouping
AnnaBridge 171:3a7713b1edbc 1477 \details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge 171:3a7713b1edbc 1478 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge 171:3a7713b1edbc 1479 */
AnnaBridge 171:3a7713b1edbc 1480 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge 171:3a7713b1edbc 1481 {
AnnaBridge 171:3a7713b1edbc 1482 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge 171:3a7713b1edbc 1483 }
AnnaBridge 171:3a7713b1edbc 1484
AnnaBridge 171:3a7713b1edbc 1485
AnnaBridge 171:3a7713b1edbc 1486 /**
AnnaBridge 171:3a7713b1edbc 1487 \brief Enable Interrupt
AnnaBridge 171:3a7713b1edbc 1488 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 171:3a7713b1edbc 1489 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 1490 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 1491 */
AnnaBridge 171:3a7713b1edbc 1492 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 1493 {
AnnaBridge 171:3a7713b1edbc 1494 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 1495 {
AnnaBridge 171:3a7713b1edbc 1496 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 1497 }
AnnaBridge 171:3a7713b1edbc 1498 }
AnnaBridge 171:3a7713b1edbc 1499
AnnaBridge 171:3a7713b1edbc 1500
AnnaBridge 171:3a7713b1edbc 1501 /**
AnnaBridge 171:3a7713b1edbc 1502 \brief Get Interrupt Enable status
AnnaBridge 171:3a7713b1edbc 1503 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 171:3a7713b1edbc 1504 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 1505 \return 0 Interrupt is not enabled.
AnnaBridge 171:3a7713b1edbc 1506 \return 1 Interrupt is enabled.
AnnaBridge 171:3a7713b1edbc 1507 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 1508 */
AnnaBridge 171:3a7713b1edbc 1509 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 1510 {
AnnaBridge 171:3a7713b1edbc 1511 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 1512 {
AnnaBridge 171:3a7713b1edbc 1513 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 1514 }
AnnaBridge 171:3a7713b1edbc 1515 else
AnnaBridge 171:3a7713b1edbc 1516 {
AnnaBridge 171:3a7713b1edbc 1517 return(0U);
AnnaBridge 171:3a7713b1edbc 1518 }
AnnaBridge 171:3a7713b1edbc 1519 }
AnnaBridge 171:3a7713b1edbc 1520
AnnaBridge 171:3a7713b1edbc 1521
AnnaBridge 171:3a7713b1edbc 1522 /**
AnnaBridge 171:3a7713b1edbc 1523 \brief Disable Interrupt
AnnaBridge 171:3a7713b1edbc 1524 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 171:3a7713b1edbc 1525 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 1526 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 1527 */
AnnaBridge 171:3a7713b1edbc 1528 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 1529 {
AnnaBridge 171:3a7713b1edbc 1530 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 1531 {
AnnaBridge 171:3a7713b1edbc 1532 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 1533 __DSB();
AnnaBridge 171:3a7713b1edbc 1534 __ISB();
AnnaBridge 171:3a7713b1edbc 1535 }
AnnaBridge 171:3a7713b1edbc 1536 }
AnnaBridge 171:3a7713b1edbc 1537
AnnaBridge 171:3a7713b1edbc 1538
AnnaBridge 171:3a7713b1edbc 1539 /**
AnnaBridge 171:3a7713b1edbc 1540 \brief Get Pending Interrupt
AnnaBridge 171:3a7713b1edbc 1541 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 171:3a7713b1edbc 1542 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 1543 \return 0 Interrupt status is not pending.
AnnaBridge 171:3a7713b1edbc 1544 \return 1 Interrupt status is pending.
AnnaBridge 171:3a7713b1edbc 1545 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 1546 */
AnnaBridge 171:3a7713b1edbc 1547 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 1548 {
AnnaBridge 171:3a7713b1edbc 1549 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 1550 {
AnnaBridge 171:3a7713b1edbc 1551 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 1552 }
AnnaBridge 171:3a7713b1edbc 1553 else
AnnaBridge 171:3a7713b1edbc 1554 {
AnnaBridge 171:3a7713b1edbc 1555 return(0U);
AnnaBridge 171:3a7713b1edbc 1556 }
AnnaBridge 171:3a7713b1edbc 1557 }
AnnaBridge 171:3a7713b1edbc 1558
AnnaBridge 171:3a7713b1edbc 1559
AnnaBridge 171:3a7713b1edbc 1560 /**
AnnaBridge 171:3a7713b1edbc 1561 \brief Set Pending Interrupt
AnnaBridge 171:3a7713b1edbc 1562 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 171:3a7713b1edbc 1563 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 1564 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 1565 */
AnnaBridge 171:3a7713b1edbc 1566 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 1567 {
AnnaBridge 171:3a7713b1edbc 1568 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 1569 {
AnnaBridge 171:3a7713b1edbc 1570 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 1571 }
AnnaBridge 171:3a7713b1edbc 1572 }
AnnaBridge 171:3a7713b1edbc 1573
AnnaBridge 171:3a7713b1edbc 1574
AnnaBridge 171:3a7713b1edbc 1575 /**
AnnaBridge 171:3a7713b1edbc 1576 \brief Clear Pending Interrupt
AnnaBridge 171:3a7713b1edbc 1577 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 171:3a7713b1edbc 1578 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 1579 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 1580 */
AnnaBridge 171:3a7713b1edbc 1581 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 1582 {
AnnaBridge 171:3a7713b1edbc 1583 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 1584 {
AnnaBridge 171:3a7713b1edbc 1585 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 1586 }
AnnaBridge 171:3a7713b1edbc 1587 }
AnnaBridge 171:3a7713b1edbc 1588
AnnaBridge 171:3a7713b1edbc 1589
AnnaBridge 171:3a7713b1edbc 1590 /**
AnnaBridge 171:3a7713b1edbc 1591 \brief Get Active Interrupt
AnnaBridge 171:3a7713b1edbc 1592 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge 171:3a7713b1edbc 1593 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 1594 \return 0 Interrupt status is not active.
AnnaBridge 171:3a7713b1edbc 1595 \return 1 Interrupt status is active.
AnnaBridge 171:3a7713b1edbc 1596 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 1597 */
AnnaBridge 171:3a7713b1edbc 1598 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 1599 {
AnnaBridge 171:3a7713b1edbc 1600 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 1601 {
AnnaBridge 171:3a7713b1edbc 1602 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 1603 }
AnnaBridge 171:3a7713b1edbc 1604 else
AnnaBridge 171:3a7713b1edbc 1605 {
AnnaBridge 171:3a7713b1edbc 1606 return(0U);
AnnaBridge 171:3a7713b1edbc 1607 }
AnnaBridge 171:3a7713b1edbc 1608 }
AnnaBridge 171:3a7713b1edbc 1609
AnnaBridge 171:3a7713b1edbc 1610
AnnaBridge 171:3a7713b1edbc 1611 /**
AnnaBridge 171:3a7713b1edbc 1612 \brief Set Interrupt Priority
AnnaBridge 171:3a7713b1edbc 1613 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 171:3a7713b1edbc 1614 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 1615 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 1616 \param [in] IRQn Interrupt number.
AnnaBridge 171:3a7713b1edbc 1617 \param [in] priority Priority to set.
AnnaBridge 171:3a7713b1edbc 1618 \note The priority cannot be set for every processor exception.
AnnaBridge 171:3a7713b1edbc 1619 */
AnnaBridge 171:3a7713b1edbc 1620 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 171:3a7713b1edbc 1621 {
AnnaBridge 171:3a7713b1edbc 1622 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 1623 {
AnnaBridge 171:3a7713b1edbc 1624 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 171:3a7713b1edbc 1625 }
AnnaBridge 171:3a7713b1edbc 1626 else
AnnaBridge 171:3a7713b1edbc 1627 {
AnnaBridge 171:3a7713b1edbc 1628 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 171:3a7713b1edbc 1629 }
AnnaBridge 171:3a7713b1edbc 1630 }
AnnaBridge 171:3a7713b1edbc 1631
AnnaBridge 171:3a7713b1edbc 1632
AnnaBridge 171:3a7713b1edbc 1633 /**
AnnaBridge 171:3a7713b1edbc 1634 \brief Get Interrupt Priority
AnnaBridge 171:3a7713b1edbc 1635 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 171:3a7713b1edbc 1636 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 1637 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 1638 \param [in] IRQn Interrupt number.
AnnaBridge 171:3a7713b1edbc 1639 \return Interrupt Priority.
AnnaBridge 171:3a7713b1edbc 1640 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 171:3a7713b1edbc 1641 */
AnnaBridge 171:3a7713b1edbc 1642 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 1643 {
AnnaBridge 171:3a7713b1edbc 1644
AnnaBridge 171:3a7713b1edbc 1645 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 1646 {
AnnaBridge 171:3a7713b1edbc 1647 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 171:3a7713b1edbc 1648 }
AnnaBridge 171:3a7713b1edbc 1649 else
AnnaBridge 171:3a7713b1edbc 1650 {
AnnaBridge 171:3a7713b1edbc 1651 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 171:3a7713b1edbc 1652 }
AnnaBridge 171:3a7713b1edbc 1653 }
AnnaBridge 171:3a7713b1edbc 1654
AnnaBridge 171:3a7713b1edbc 1655
AnnaBridge 171:3a7713b1edbc 1656 /**
AnnaBridge 171:3a7713b1edbc 1657 \brief Encode Priority
AnnaBridge 171:3a7713b1edbc 1658 \details Encodes the priority for an interrupt with the given priority group,
AnnaBridge 171:3a7713b1edbc 1659 preemptive priority value, and subpriority value.
AnnaBridge 171:3a7713b1edbc 1660 In case of a conflict between priority grouping and available
AnnaBridge 171:3a7713b1edbc 1661 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 171:3a7713b1edbc 1662 \param [in] PriorityGroup Used priority group.
AnnaBridge 171:3a7713b1edbc 1663 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 171:3a7713b1edbc 1664 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 171:3a7713b1edbc 1665 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge 171:3a7713b1edbc 1666 */
AnnaBridge 171:3a7713b1edbc 1667 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 171:3a7713b1edbc 1668 {
AnnaBridge 171:3a7713b1edbc 1669 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 171:3a7713b1edbc 1670 uint32_t PreemptPriorityBits;
AnnaBridge 171:3a7713b1edbc 1671 uint32_t SubPriorityBits;
AnnaBridge 171:3a7713b1edbc 1672
AnnaBridge 171:3a7713b1edbc 1673 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 171:3a7713b1edbc 1674 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 171:3a7713b1edbc 1675
AnnaBridge 171:3a7713b1edbc 1676 return (
AnnaBridge 171:3a7713b1edbc 1677 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
AnnaBridge 171:3a7713b1edbc 1678 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge 171:3a7713b1edbc 1679 );
AnnaBridge 171:3a7713b1edbc 1680 }
AnnaBridge 171:3a7713b1edbc 1681
AnnaBridge 171:3a7713b1edbc 1682
AnnaBridge 171:3a7713b1edbc 1683 /**
AnnaBridge 171:3a7713b1edbc 1684 \brief Decode Priority
AnnaBridge 171:3a7713b1edbc 1685 \details Decodes an interrupt priority value with a given priority group to
AnnaBridge 171:3a7713b1edbc 1686 preemptive priority value and subpriority value.
AnnaBridge 171:3a7713b1edbc 1687 In case of a conflict between priority grouping and available
AnnaBridge 171:3a7713b1edbc 1688 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 171:3a7713b1edbc 1689 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 171:3a7713b1edbc 1690 \param [in] PriorityGroup Used priority group.
AnnaBridge 171:3a7713b1edbc 1691 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 171:3a7713b1edbc 1692 \param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge 171:3a7713b1edbc 1693 */
AnnaBridge 171:3a7713b1edbc 1694 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge 171:3a7713b1edbc 1695 {
AnnaBridge 171:3a7713b1edbc 1696 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 171:3a7713b1edbc 1697 uint32_t PreemptPriorityBits;
AnnaBridge 171:3a7713b1edbc 1698 uint32_t SubPriorityBits;
AnnaBridge 171:3a7713b1edbc 1699
AnnaBridge 171:3a7713b1edbc 1700 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 171:3a7713b1edbc 1701 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 171:3a7713b1edbc 1702
AnnaBridge 171:3a7713b1edbc 1703 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge 171:3a7713b1edbc 1704 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge 171:3a7713b1edbc 1705 }
AnnaBridge 171:3a7713b1edbc 1706
AnnaBridge 171:3a7713b1edbc 1707
AnnaBridge 171:3a7713b1edbc 1708 /**
AnnaBridge 171:3a7713b1edbc 1709 \brief Set Interrupt Vector
AnnaBridge 171:3a7713b1edbc 1710 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 171:3a7713b1edbc 1711 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 1712 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 1713 VTOR must been relocated to SRAM before.
AnnaBridge 171:3a7713b1edbc 1714 \param [in] IRQn Interrupt number
AnnaBridge 171:3a7713b1edbc 1715 \param [in] vector Address of interrupt handler function
AnnaBridge 171:3a7713b1edbc 1716 */
AnnaBridge 171:3a7713b1edbc 1717 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 171:3a7713b1edbc 1718 {
AnnaBridge 171:3a7713b1edbc 1719 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 171:3a7713b1edbc 1720 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 171:3a7713b1edbc 1721 }
AnnaBridge 171:3a7713b1edbc 1722
AnnaBridge 171:3a7713b1edbc 1723
AnnaBridge 171:3a7713b1edbc 1724 /**
AnnaBridge 171:3a7713b1edbc 1725 \brief Get Interrupt Vector
AnnaBridge 171:3a7713b1edbc 1726 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 171:3a7713b1edbc 1727 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 1728 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 1729 \param [in] IRQn Interrupt number.
AnnaBridge 171:3a7713b1edbc 1730 \return Address of interrupt handler function
AnnaBridge 171:3a7713b1edbc 1731 */
AnnaBridge 171:3a7713b1edbc 1732 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 1733 {
AnnaBridge 171:3a7713b1edbc 1734 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 171:3a7713b1edbc 1735 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 171:3a7713b1edbc 1736 }
AnnaBridge 171:3a7713b1edbc 1737
AnnaBridge 171:3a7713b1edbc 1738
AnnaBridge 171:3a7713b1edbc 1739 /**
AnnaBridge 171:3a7713b1edbc 1740 \brief System Reset
AnnaBridge 171:3a7713b1edbc 1741 \details Initiates a system reset request to reset the MCU.
AnnaBridge 171:3a7713b1edbc 1742 */
AnnaBridge 171:3a7713b1edbc 1743 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 171:3a7713b1edbc 1744 {
AnnaBridge 171:3a7713b1edbc 1745 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 171:3a7713b1edbc 1746 buffered write are completed before reset */
AnnaBridge 171:3a7713b1edbc 1747 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 171:3a7713b1edbc 1748 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
AnnaBridge 171:3a7713b1edbc 1749 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge 171:3a7713b1edbc 1750 __DSB(); /* Ensure completion of memory access */
AnnaBridge 171:3a7713b1edbc 1751
AnnaBridge 171:3a7713b1edbc 1752 for(;;) /* wait until reset */
AnnaBridge 171:3a7713b1edbc 1753 {
AnnaBridge 171:3a7713b1edbc 1754 __NOP();
AnnaBridge 171:3a7713b1edbc 1755 }
AnnaBridge 171:3a7713b1edbc 1756 }
AnnaBridge 171:3a7713b1edbc 1757
AnnaBridge 171:3a7713b1edbc 1758 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 171:3a7713b1edbc 1759
AnnaBridge 171:3a7713b1edbc 1760
AnnaBridge 171:3a7713b1edbc 1761 /* ########################## FPU functions #################################### */
AnnaBridge 171:3a7713b1edbc 1762 /**
AnnaBridge 171:3a7713b1edbc 1763 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 1764 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 171:3a7713b1edbc 1765 \brief Function that provides FPU type.
AnnaBridge 171:3a7713b1edbc 1766 @{
AnnaBridge 171:3a7713b1edbc 1767 */
AnnaBridge 171:3a7713b1edbc 1768
AnnaBridge 171:3a7713b1edbc 1769 /**
AnnaBridge 171:3a7713b1edbc 1770 \brief get FPU type
AnnaBridge 171:3a7713b1edbc 1771 \details returns the FPU type
AnnaBridge 171:3a7713b1edbc 1772 \returns
AnnaBridge 171:3a7713b1edbc 1773 - \b 0: No FPU
AnnaBridge 171:3a7713b1edbc 1774 - \b 1: Single precision FPU
AnnaBridge 171:3a7713b1edbc 1775 - \b 2: Double + Single precision FPU
AnnaBridge 171:3a7713b1edbc 1776 */
AnnaBridge 171:3a7713b1edbc 1777 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 171:3a7713b1edbc 1778 {
AnnaBridge 171:3a7713b1edbc 1779 return 0U; /* No FPU */
AnnaBridge 171:3a7713b1edbc 1780 }
AnnaBridge 171:3a7713b1edbc 1781
AnnaBridge 171:3a7713b1edbc 1782
AnnaBridge 171:3a7713b1edbc 1783 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 171:3a7713b1edbc 1784
AnnaBridge 171:3a7713b1edbc 1785
AnnaBridge 171:3a7713b1edbc 1786
AnnaBridge 171:3a7713b1edbc 1787 /* ################################## SysTick function ############################################ */
AnnaBridge 171:3a7713b1edbc 1788 /**
AnnaBridge 171:3a7713b1edbc 1789 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 1790 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 171:3a7713b1edbc 1791 \brief Functions that configure the System.
AnnaBridge 171:3a7713b1edbc 1792 @{
AnnaBridge 171:3a7713b1edbc 1793 */
AnnaBridge 171:3a7713b1edbc 1794
AnnaBridge 171:3a7713b1edbc 1795 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 171:3a7713b1edbc 1796
AnnaBridge 171:3a7713b1edbc 1797 /**
AnnaBridge 171:3a7713b1edbc 1798 \brief System Tick Configuration
AnnaBridge 171:3a7713b1edbc 1799 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 171:3a7713b1edbc 1800 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 171:3a7713b1edbc 1801 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 171:3a7713b1edbc 1802 \return 0 Function succeeded.
AnnaBridge 171:3a7713b1edbc 1803 \return 1 Function failed.
AnnaBridge 171:3a7713b1edbc 1804 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 171:3a7713b1edbc 1805 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 171:3a7713b1edbc 1806 must contain a vendor-specific implementation of this function.
AnnaBridge 171:3a7713b1edbc 1807 */
AnnaBridge 171:3a7713b1edbc 1808 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 171:3a7713b1edbc 1809 {
AnnaBridge 171:3a7713b1edbc 1810 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 171:3a7713b1edbc 1811 {
AnnaBridge 171:3a7713b1edbc 1812 return (1UL); /* Reload value impossible */
AnnaBridge 171:3a7713b1edbc 1813 }
AnnaBridge 171:3a7713b1edbc 1814
AnnaBridge 171:3a7713b1edbc 1815 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 171:3a7713b1edbc 1816 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 171:3a7713b1edbc 1817 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 171:3a7713b1edbc 1818 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 171:3a7713b1edbc 1819 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 171:3a7713b1edbc 1820 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 171:3a7713b1edbc 1821 return (0UL); /* Function successful */
AnnaBridge 171:3a7713b1edbc 1822 }
AnnaBridge 171:3a7713b1edbc 1823
AnnaBridge 171:3a7713b1edbc 1824 #endif
AnnaBridge 171:3a7713b1edbc 1825
AnnaBridge 171:3a7713b1edbc 1826 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 171:3a7713b1edbc 1827
AnnaBridge 171:3a7713b1edbc 1828
AnnaBridge 171:3a7713b1edbc 1829
AnnaBridge 171:3a7713b1edbc 1830 /* ##################################### Debug In/Output function ########################################### */
AnnaBridge 171:3a7713b1edbc 1831 /**
AnnaBridge 171:3a7713b1edbc 1832 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 1833 \defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge 171:3a7713b1edbc 1834 \brief Functions that access the ITM debug interface.
AnnaBridge 171:3a7713b1edbc 1835 @{
AnnaBridge 171:3a7713b1edbc 1836 */
AnnaBridge 171:3a7713b1edbc 1837
AnnaBridge 171:3a7713b1edbc 1838 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
AnnaBridge 171:3a7713b1edbc 1839 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
AnnaBridge 171:3a7713b1edbc 1840
AnnaBridge 171:3a7713b1edbc 1841
AnnaBridge 171:3a7713b1edbc 1842 /**
AnnaBridge 171:3a7713b1edbc 1843 \brief ITM Send Character
AnnaBridge 171:3a7713b1edbc 1844 \details Transmits a character via the ITM channel 0, and
AnnaBridge 171:3a7713b1edbc 1845 \li Just returns when no debugger is connected that has booked the output.
AnnaBridge 171:3a7713b1edbc 1846 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge 171:3a7713b1edbc 1847 \param [in] ch Character to transmit.
AnnaBridge 171:3a7713b1edbc 1848 \returns Character to transmit.
AnnaBridge 171:3a7713b1edbc 1849 */
AnnaBridge 171:3a7713b1edbc 1850 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge 171:3a7713b1edbc 1851 {
AnnaBridge 171:3a7713b1edbc 1852 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge 171:3a7713b1edbc 1853 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge 171:3a7713b1edbc 1854 {
AnnaBridge 171:3a7713b1edbc 1855 while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge 171:3a7713b1edbc 1856 {
AnnaBridge 171:3a7713b1edbc 1857 __NOP();
AnnaBridge 171:3a7713b1edbc 1858 }
AnnaBridge 171:3a7713b1edbc 1859 ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge 171:3a7713b1edbc 1860 }
AnnaBridge 171:3a7713b1edbc 1861 return (ch);
AnnaBridge 171:3a7713b1edbc 1862 }
AnnaBridge 171:3a7713b1edbc 1863
AnnaBridge 171:3a7713b1edbc 1864
AnnaBridge 171:3a7713b1edbc 1865 /**
AnnaBridge 171:3a7713b1edbc 1866 \brief ITM Receive Character
AnnaBridge 171:3a7713b1edbc 1867 \details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge 171:3a7713b1edbc 1868 \return Received character.
AnnaBridge 171:3a7713b1edbc 1869 \return -1 No character pending.
AnnaBridge 171:3a7713b1edbc 1870 */
AnnaBridge 171:3a7713b1edbc 1871 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge 171:3a7713b1edbc 1872 {
AnnaBridge 171:3a7713b1edbc 1873 int32_t ch = -1; /* no character available */
AnnaBridge 171:3a7713b1edbc 1874
AnnaBridge 171:3a7713b1edbc 1875 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge 171:3a7713b1edbc 1876 {
AnnaBridge 171:3a7713b1edbc 1877 ch = ITM_RxBuffer;
AnnaBridge 171:3a7713b1edbc 1878 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge 171:3a7713b1edbc 1879 }
AnnaBridge 171:3a7713b1edbc 1880
AnnaBridge 171:3a7713b1edbc 1881 return (ch);
AnnaBridge 171:3a7713b1edbc 1882 }
AnnaBridge 171:3a7713b1edbc 1883
AnnaBridge 171:3a7713b1edbc 1884
AnnaBridge 171:3a7713b1edbc 1885 /**
AnnaBridge 171:3a7713b1edbc 1886 \brief ITM Check Character
AnnaBridge 171:3a7713b1edbc 1887 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge 171:3a7713b1edbc 1888 \return 0 No character available.
AnnaBridge 171:3a7713b1edbc 1889 \return 1 Character available.
AnnaBridge 171:3a7713b1edbc 1890 */
AnnaBridge 171:3a7713b1edbc 1891 __STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge 171:3a7713b1edbc 1892 {
AnnaBridge 171:3a7713b1edbc 1893
AnnaBridge 171:3a7713b1edbc 1894 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge 171:3a7713b1edbc 1895 {
AnnaBridge 171:3a7713b1edbc 1896 return (0); /* no character available */
AnnaBridge 171:3a7713b1edbc 1897 }
AnnaBridge 171:3a7713b1edbc 1898 else
AnnaBridge 171:3a7713b1edbc 1899 {
AnnaBridge 171:3a7713b1edbc 1900 return (1); /* character available */
AnnaBridge 171:3a7713b1edbc 1901 }
AnnaBridge 171:3a7713b1edbc 1902 }
AnnaBridge 171:3a7713b1edbc 1903
AnnaBridge 171:3a7713b1edbc 1904 /*@} end of CMSIS_core_DebugFunctions */
AnnaBridge 171:3a7713b1edbc 1905
AnnaBridge 171:3a7713b1edbc 1906
AnnaBridge 171:3a7713b1edbc 1907
AnnaBridge 171:3a7713b1edbc 1908
AnnaBridge 171:3a7713b1edbc 1909 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 1910 }
AnnaBridge 171:3a7713b1edbc 1911 #endif
AnnaBridge 171:3a7713b1edbc 1912
AnnaBridge 171:3a7713b1edbc 1913 #endif /* __CORE_SC300_H_DEPENDANT */
AnnaBridge 171:3a7713b1edbc 1914
AnnaBridge 171:3a7713b1edbc 1915 #endif /* __CMSIS_GENERIC */