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TARGET_LPC1768/TOOLCHAIN_ARM_STD/core_cm33.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file core_cm33.h
AnnaBridge 171:3a7713b1edbc 3 * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
AnnaBridge 171:3a7713b1edbc 4 * @version V5.0.9
AnnaBridge 171:3a7713b1edbc 5 * @date 06. July 2018
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7 /*
AnnaBridge 171:3a7713b1edbc 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 171:3a7713b1edbc 13 * not use this file except in compliance with the License.
AnnaBridge 171:3a7713b1edbc 14 * You may obtain a copy of the License at
AnnaBridge 171:3a7713b1edbc 15 *
AnnaBridge 171:3a7713b1edbc 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 171:3a7713b1edbc 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 171:3a7713b1edbc 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 171:3a7713b1edbc 21 * See the License for the specific language governing permissions and
AnnaBridge 171:3a7713b1edbc 22 * limitations under the License.
AnnaBridge 171:3a7713b1edbc 23 */
AnnaBridge 171:3a7713b1edbc 24
AnnaBridge 171:3a7713b1edbc 25 #if defined ( __ICCARM__ )
AnnaBridge 171:3a7713b1edbc 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 171:3a7713b1edbc 27 #elif defined (__clang__)
AnnaBridge 171:3a7713b1edbc 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 171:3a7713b1edbc 29 #endif
AnnaBridge 171:3a7713b1edbc 30
AnnaBridge 171:3a7713b1edbc 31 #ifndef __CORE_CM33_H_GENERIC
AnnaBridge 171:3a7713b1edbc 32 #define __CORE_CM33_H_GENERIC
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 37 extern "C" {
AnnaBridge 171:3a7713b1edbc 38 #endif
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 /**
AnnaBridge 171:3a7713b1edbc 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 171:3a7713b1edbc 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 171:3a7713b1edbc 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 171:3a7713b1edbc 48 Unions are used for effective representation of core registers.
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 171:3a7713b1edbc 51 Function-like macros are used to allow more efficient code.
AnnaBridge 171:3a7713b1edbc 52 */
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 56 * CMSIS definitions
AnnaBridge 171:3a7713b1edbc 57 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 58 /**
AnnaBridge 171:3a7713b1edbc 59 \ingroup Cortex_M33
AnnaBridge 171:3a7713b1edbc 60 @{
AnnaBridge 171:3a7713b1edbc 61 */
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 #include "cmsis_version.h"
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 /* CMSIS CM33 definitions */
AnnaBridge 171:3a7713b1edbc 66 #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
AnnaBridge 171:3a7713b1edbc 67 #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 171:3a7713b1edbc 68 #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 171:3a7713b1edbc 69 __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 #define __CORTEX_M (33U) /*!< Cortex-M Core */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 171:3a7713b1edbc 74 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
AnnaBridge 171:3a7713b1edbc 75 */
AnnaBridge 171:3a7713b1edbc 76 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 77 #if defined (__TARGET_FPU_VFP)
AnnaBridge 171:3a7713b1edbc 78 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 79 #define __FPU_USED 1U
AnnaBridge 171:3a7713b1edbc 80 #else
AnnaBridge 171:3a7713b1edbc 81 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 82 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 83 #endif
AnnaBridge 171:3a7713b1edbc 84 #else
AnnaBridge 171:3a7713b1edbc 85 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 86 #endif
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
AnnaBridge 171:3a7713b1edbc 89 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 90 #define __DSP_USED 1U
AnnaBridge 171:3a7713b1edbc 91 #else
AnnaBridge 171:3a7713b1edbc 92 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
AnnaBridge 171:3a7713b1edbc 93 #define __DSP_USED 0U
AnnaBridge 171:3a7713b1edbc 94 #endif
AnnaBridge 171:3a7713b1edbc 95 #else
AnnaBridge 171:3a7713b1edbc 96 #define __DSP_USED 0U
AnnaBridge 171:3a7713b1edbc 97 #endif
AnnaBridge 171:3a7713b1edbc 98
AnnaBridge 171:3a7713b1edbc 99 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 172:65be27845400 100 #if defined (__ARM_FP)
AnnaBridge 171:3a7713b1edbc 101 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 102 #define __FPU_USED 1U
AnnaBridge 171:3a7713b1edbc 103 #else
AnnaBridge 171:3a7713b1edbc 104 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 105 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 106 #endif
AnnaBridge 171:3a7713b1edbc 107 #else
AnnaBridge 171:3a7713b1edbc 108 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 109 #endif
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
AnnaBridge 171:3a7713b1edbc 112 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 113 #define __DSP_USED 1U
AnnaBridge 171:3a7713b1edbc 114 #else
AnnaBridge 171:3a7713b1edbc 115 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
AnnaBridge 171:3a7713b1edbc 116 #define __DSP_USED 0U
AnnaBridge 171:3a7713b1edbc 117 #endif
AnnaBridge 171:3a7713b1edbc 118 #else
AnnaBridge 171:3a7713b1edbc 119 #define __DSP_USED 0U
AnnaBridge 171:3a7713b1edbc 120 #endif
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 #elif defined ( __GNUC__ )
AnnaBridge 171:3a7713b1edbc 123 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 171:3a7713b1edbc 124 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 125 #define __FPU_USED 1U
AnnaBridge 171:3a7713b1edbc 126 #else
AnnaBridge 171:3a7713b1edbc 127 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 128 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 129 #endif
AnnaBridge 171:3a7713b1edbc 130 #else
AnnaBridge 171:3a7713b1edbc 131 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 132 #endif
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
AnnaBridge 171:3a7713b1edbc 135 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 136 #define __DSP_USED 1U
AnnaBridge 171:3a7713b1edbc 137 #else
AnnaBridge 171:3a7713b1edbc 138 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
AnnaBridge 171:3a7713b1edbc 139 #define __DSP_USED 0U
AnnaBridge 171:3a7713b1edbc 140 #endif
AnnaBridge 171:3a7713b1edbc 141 #else
AnnaBridge 171:3a7713b1edbc 142 #define __DSP_USED 0U
AnnaBridge 171:3a7713b1edbc 143 #endif
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 #elif defined ( __ICCARM__ )
AnnaBridge 171:3a7713b1edbc 146 #if defined (__ARMVFP__)
AnnaBridge 171:3a7713b1edbc 147 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 148 #define __FPU_USED 1U
AnnaBridge 171:3a7713b1edbc 149 #else
AnnaBridge 171:3a7713b1edbc 150 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 151 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 152 #endif
AnnaBridge 171:3a7713b1edbc 153 #else
AnnaBridge 171:3a7713b1edbc 154 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 155 #endif
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
AnnaBridge 171:3a7713b1edbc 158 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 159 #define __DSP_USED 1U
AnnaBridge 171:3a7713b1edbc 160 #else
AnnaBridge 171:3a7713b1edbc 161 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
AnnaBridge 171:3a7713b1edbc 162 #define __DSP_USED 0U
AnnaBridge 171:3a7713b1edbc 163 #endif
AnnaBridge 171:3a7713b1edbc 164 #else
AnnaBridge 171:3a7713b1edbc 165 #define __DSP_USED 0U
AnnaBridge 171:3a7713b1edbc 166 #endif
AnnaBridge 171:3a7713b1edbc 167
AnnaBridge 171:3a7713b1edbc 168 #elif defined ( __TI_ARM__ )
AnnaBridge 171:3a7713b1edbc 169 #if defined (__TI_VFP_SUPPORT__)
AnnaBridge 171:3a7713b1edbc 170 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 171 #define __FPU_USED 1U
AnnaBridge 171:3a7713b1edbc 172 #else
AnnaBridge 171:3a7713b1edbc 173 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 174 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 175 #endif
AnnaBridge 171:3a7713b1edbc 176 #else
AnnaBridge 171:3a7713b1edbc 177 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 178 #endif
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 #elif defined ( __TASKING__ )
AnnaBridge 171:3a7713b1edbc 181 #if defined (__FPU_VFP__)
AnnaBridge 171:3a7713b1edbc 182 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 183 #define __FPU_USED 1U
AnnaBridge 171:3a7713b1edbc 184 #else
AnnaBridge 171:3a7713b1edbc 185 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 186 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 187 #endif
AnnaBridge 171:3a7713b1edbc 188 #else
AnnaBridge 171:3a7713b1edbc 189 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 190 #endif
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192 #elif defined ( __CSMC__ )
AnnaBridge 171:3a7713b1edbc 193 #if ( __CSMC__ & 0x400U)
AnnaBridge 171:3a7713b1edbc 194 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 195 #define __FPU_USED 1U
AnnaBridge 171:3a7713b1edbc 196 #else
AnnaBridge 171:3a7713b1edbc 197 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 171:3a7713b1edbc 198 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 199 #endif
AnnaBridge 171:3a7713b1edbc 200 #else
AnnaBridge 171:3a7713b1edbc 201 #define __FPU_USED 0U
AnnaBridge 171:3a7713b1edbc 202 #endif
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204 #endif
AnnaBridge 171:3a7713b1edbc 205
AnnaBridge 171:3a7713b1edbc 206 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 210 }
AnnaBridge 171:3a7713b1edbc 211 #endif
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 #endif /* __CORE_CM33_H_GENERIC */
AnnaBridge 171:3a7713b1edbc 214
AnnaBridge 171:3a7713b1edbc 215 #ifndef __CMSIS_GENERIC
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 #ifndef __CORE_CM33_H_DEPENDANT
AnnaBridge 171:3a7713b1edbc 218 #define __CORE_CM33_H_DEPENDANT
AnnaBridge 171:3a7713b1edbc 219
AnnaBridge 171:3a7713b1edbc 220 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 221 extern "C" {
AnnaBridge 171:3a7713b1edbc 222 #endif
AnnaBridge 171:3a7713b1edbc 223
AnnaBridge 171:3a7713b1edbc 224 /* check device defines and use defaults */
AnnaBridge 171:3a7713b1edbc 225 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 171:3a7713b1edbc 226 #ifndef __CM33_REV
AnnaBridge 171:3a7713b1edbc 227 #define __CM33_REV 0x0000U
AnnaBridge 171:3a7713b1edbc 228 #warning "__CM33_REV not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 229 #endif
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 #ifndef __FPU_PRESENT
AnnaBridge 171:3a7713b1edbc 232 #define __FPU_PRESENT 0U
AnnaBridge 171:3a7713b1edbc 233 #warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 234 #endif
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 #ifndef __MPU_PRESENT
AnnaBridge 171:3a7713b1edbc 237 #define __MPU_PRESENT 0U
AnnaBridge 171:3a7713b1edbc 238 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 239 #endif
AnnaBridge 171:3a7713b1edbc 240
AnnaBridge 171:3a7713b1edbc 241 #ifndef __SAUREGION_PRESENT
AnnaBridge 171:3a7713b1edbc 242 #define __SAUREGION_PRESENT 0U
AnnaBridge 171:3a7713b1edbc 243 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 244 #endif
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 #ifndef __DSP_PRESENT
AnnaBridge 171:3a7713b1edbc 247 #define __DSP_PRESENT 0U
AnnaBridge 171:3a7713b1edbc 248 #warning "__DSP_PRESENT not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 249 #endif
AnnaBridge 171:3a7713b1edbc 250
AnnaBridge 171:3a7713b1edbc 251 #ifndef __NVIC_PRIO_BITS
AnnaBridge 171:3a7713b1edbc 252 #define __NVIC_PRIO_BITS 3U
AnnaBridge 171:3a7713b1edbc 253 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 254 #endif
AnnaBridge 171:3a7713b1edbc 255
AnnaBridge 171:3a7713b1edbc 256 #ifndef __Vendor_SysTickConfig
AnnaBridge 171:3a7713b1edbc 257 #define __Vendor_SysTickConfig 0U
AnnaBridge 171:3a7713b1edbc 258 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 171:3a7713b1edbc 259 #endif
AnnaBridge 171:3a7713b1edbc 260 #endif
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 171:3a7713b1edbc 263 /**
AnnaBridge 171:3a7713b1edbc 264 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 171:3a7713b1edbc 265
AnnaBridge 171:3a7713b1edbc 266 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 171:3a7713b1edbc 267 \li to specify the access to peripheral variables.
AnnaBridge 171:3a7713b1edbc 268 \li for automatic generation of peripheral register debug information.
AnnaBridge 171:3a7713b1edbc 269 */
AnnaBridge 171:3a7713b1edbc 270 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 271 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 171:3a7713b1edbc 272 #else
AnnaBridge 171:3a7713b1edbc 273 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 171:3a7713b1edbc 274 #endif
AnnaBridge 171:3a7713b1edbc 275 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 171:3a7713b1edbc 276 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 /* following defines should be used for structure members */
AnnaBridge 171:3a7713b1edbc 279 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 171:3a7713b1edbc 280 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 171:3a7713b1edbc 281 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 /*@} end of group Cortex_M33 */
AnnaBridge 171:3a7713b1edbc 284
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 288 * Register Abstraction
AnnaBridge 171:3a7713b1edbc 289 Core Register contain:
AnnaBridge 171:3a7713b1edbc 290 - Core Register
AnnaBridge 171:3a7713b1edbc 291 - Core NVIC Register
AnnaBridge 171:3a7713b1edbc 292 - Core SCB Register
AnnaBridge 171:3a7713b1edbc 293 - Core SysTick Register
AnnaBridge 171:3a7713b1edbc 294 - Core Debug Register
AnnaBridge 171:3a7713b1edbc 295 - Core MPU Register
AnnaBridge 171:3a7713b1edbc 296 - Core SAU Register
AnnaBridge 171:3a7713b1edbc 297 - Core FPU Register
AnnaBridge 171:3a7713b1edbc 298 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 299 /**
AnnaBridge 171:3a7713b1edbc 300 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 171:3a7713b1edbc 301 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 171:3a7713b1edbc 302 */
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304 /**
AnnaBridge 171:3a7713b1edbc 305 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 306 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 171:3a7713b1edbc 307 \brief Core Register type definitions.
AnnaBridge 171:3a7713b1edbc 308 @{
AnnaBridge 171:3a7713b1edbc 309 */
AnnaBridge 171:3a7713b1edbc 310
AnnaBridge 171:3a7713b1edbc 311 /**
AnnaBridge 171:3a7713b1edbc 312 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 171:3a7713b1edbc 313 */
AnnaBridge 171:3a7713b1edbc 314 typedef union
AnnaBridge 171:3a7713b1edbc 315 {
AnnaBridge 171:3a7713b1edbc 316 struct
AnnaBridge 171:3a7713b1edbc 317 {
AnnaBridge 171:3a7713b1edbc 318 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
AnnaBridge 171:3a7713b1edbc 319 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
AnnaBridge 171:3a7713b1edbc 320 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
AnnaBridge 171:3a7713b1edbc 321 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 171:3a7713b1edbc 322 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 171:3a7713b1edbc 323 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 171:3a7713b1edbc 324 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 171:3a7713b1edbc 325 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 171:3a7713b1edbc 326 } b; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 327 uint32_t w; /*!< Type used for word access */
AnnaBridge 171:3a7713b1edbc 328 } APSR_Type;
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 /* APSR Register Definitions */
AnnaBridge 171:3a7713b1edbc 331 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 171:3a7713b1edbc 332 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 171:3a7713b1edbc 335 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 171:3a7713b1edbc 336
AnnaBridge 171:3a7713b1edbc 337 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 171:3a7713b1edbc 338 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 171:3a7713b1edbc 339
AnnaBridge 171:3a7713b1edbc 340 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 171:3a7713b1edbc 341 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
AnnaBridge 171:3a7713b1edbc 344 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
AnnaBridge 171:3a7713b1edbc 345
AnnaBridge 171:3a7713b1edbc 346 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
AnnaBridge 171:3a7713b1edbc 347 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
AnnaBridge 171:3a7713b1edbc 348
AnnaBridge 171:3a7713b1edbc 349
AnnaBridge 171:3a7713b1edbc 350 /**
AnnaBridge 171:3a7713b1edbc 351 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 171:3a7713b1edbc 352 */
AnnaBridge 171:3a7713b1edbc 353 typedef union
AnnaBridge 171:3a7713b1edbc 354 {
AnnaBridge 171:3a7713b1edbc 355 struct
AnnaBridge 171:3a7713b1edbc 356 {
AnnaBridge 171:3a7713b1edbc 357 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 171:3a7713b1edbc 358 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 171:3a7713b1edbc 359 } b; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 360 uint32_t w; /*!< Type used for word access */
AnnaBridge 171:3a7713b1edbc 361 } IPSR_Type;
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363 /* IPSR Register Definitions */
AnnaBridge 171:3a7713b1edbc 364 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 171:3a7713b1edbc 365 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 171:3a7713b1edbc 366
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 /**
AnnaBridge 171:3a7713b1edbc 369 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 171:3a7713b1edbc 370 */
AnnaBridge 171:3a7713b1edbc 371 typedef union
AnnaBridge 171:3a7713b1edbc 372 {
AnnaBridge 171:3a7713b1edbc 373 struct
AnnaBridge 171:3a7713b1edbc 374 {
AnnaBridge 171:3a7713b1edbc 375 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 171:3a7713b1edbc 376 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
AnnaBridge 171:3a7713b1edbc 377 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
AnnaBridge 171:3a7713b1edbc 378 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
AnnaBridge 171:3a7713b1edbc 379 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 171:3a7713b1edbc 380 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
AnnaBridge 171:3a7713b1edbc 381 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
AnnaBridge 171:3a7713b1edbc 382 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 171:3a7713b1edbc 383 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 171:3a7713b1edbc 384 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 171:3a7713b1edbc 385 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 171:3a7713b1edbc 386 } b; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 387 uint32_t w; /*!< Type used for word access */
AnnaBridge 171:3a7713b1edbc 388 } xPSR_Type;
AnnaBridge 171:3a7713b1edbc 389
AnnaBridge 171:3a7713b1edbc 390 /* xPSR Register Definitions */
AnnaBridge 171:3a7713b1edbc 391 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 171:3a7713b1edbc 392 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 171:3a7713b1edbc 395 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 171:3a7713b1edbc 396
AnnaBridge 171:3a7713b1edbc 397 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 171:3a7713b1edbc 398 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 171:3a7713b1edbc 399
AnnaBridge 171:3a7713b1edbc 400 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 171:3a7713b1edbc 401 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 171:3a7713b1edbc 402
AnnaBridge 171:3a7713b1edbc 403 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
AnnaBridge 171:3a7713b1edbc 404 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
AnnaBridge 171:3a7713b1edbc 405
AnnaBridge 171:3a7713b1edbc 406 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
AnnaBridge 171:3a7713b1edbc 407 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
AnnaBridge 171:3a7713b1edbc 408
AnnaBridge 171:3a7713b1edbc 409 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 171:3a7713b1edbc 410 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 171:3a7713b1edbc 411
AnnaBridge 171:3a7713b1edbc 412 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
AnnaBridge 171:3a7713b1edbc 413 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
AnnaBridge 171:3a7713b1edbc 414
AnnaBridge 171:3a7713b1edbc 415 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 171:3a7713b1edbc 416 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 171:3a7713b1edbc 417
AnnaBridge 171:3a7713b1edbc 418
AnnaBridge 171:3a7713b1edbc 419 /**
AnnaBridge 171:3a7713b1edbc 420 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 171:3a7713b1edbc 421 */
AnnaBridge 171:3a7713b1edbc 422 typedef union
AnnaBridge 171:3a7713b1edbc 423 {
AnnaBridge 171:3a7713b1edbc 424 struct
AnnaBridge 171:3a7713b1edbc 425 {
AnnaBridge 171:3a7713b1edbc 426 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
AnnaBridge 171:3a7713b1edbc 427 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
AnnaBridge 171:3a7713b1edbc 428 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
AnnaBridge 171:3a7713b1edbc 429 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
AnnaBridge 171:3a7713b1edbc 430 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
AnnaBridge 171:3a7713b1edbc 431 } b; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 432 uint32_t w; /*!< Type used for word access */
AnnaBridge 171:3a7713b1edbc 433 } CONTROL_Type;
AnnaBridge 171:3a7713b1edbc 434
AnnaBridge 171:3a7713b1edbc 435 /* CONTROL Register Definitions */
AnnaBridge 171:3a7713b1edbc 436 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
AnnaBridge 171:3a7713b1edbc 437 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
AnnaBridge 171:3a7713b1edbc 438
AnnaBridge 171:3a7713b1edbc 439 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
AnnaBridge 171:3a7713b1edbc 440 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
AnnaBridge 171:3a7713b1edbc 441
AnnaBridge 171:3a7713b1edbc 442 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 171:3a7713b1edbc 443 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 171:3a7713b1edbc 444
AnnaBridge 171:3a7713b1edbc 445 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
AnnaBridge 171:3a7713b1edbc 446 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
AnnaBridge 171:3a7713b1edbc 447
AnnaBridge 171:3a7713b1edbc 448 /*@} end of group CMSIS_CORE */
AnnaBridge 171:3a7713b1edbc 449
AnnaBridge 171:3a7713b1edbc 450
AnnaBridge 171:3a7713b1edbc 451 /**
AnnaBridge 171:3a7713b1edbc 452 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 453 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 171:3a7713b1edbc 454 \brief Type definitions for the NVIC Registers
AnnaBridge 171:3a7713b1edbc 455 @{
AnnaBridge 171:3a7713b1edbc 456 */
AnnaBridge 171:3a7713b1edbc 457
AnnaBridge 171:3a7713b1edbc 458 /**
AnnaBridge 171:3a7713b1edbc 459 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 171:3a7713b1edbc 460 */
AnnaBridge 171:3a7713b1edbc 461 typedef struct
AnnaBridge 171:3a7713b1edbc 462 {
AnnaBridge 171:3a7713b1edbc 463 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 171:3a7713b1edbc 464 uint32_t RESERVED0[16U];
AnnaBridge 171:3a7713b1edbc 465 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 171:3a7713b1edbc 466 uint32_t RSERVED1[16U];
AnnaBridge 171:3a7713b1edbc 467 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 171:3a7713b1edbc 468 uint32_t RESERVED2[16U];
AnnaBridge 171:3a7713b1edbc 469 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 171:3a7713b1edbc 470 uint32_t RESERVED3[16U];
AnnaBridge 171:3a7713b1edbc 471 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
AnnaBridge 171:3a7713b1edbc 472 uint32_t RESERVED4[16U];
AnnaBridge 171:3a7713b1edbc 473 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
AnnaBridge 171:3a7713b1edbc 474 uint32_t RESERVED5[16U];
AnnaBridge 171:3a7713b1edbc 475 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
AnnaBridge 171:3a7713b1edbc 476 uint32_t RESERVED6[580U];
AnnaBridge 171:3a7713b1edbc 477 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
AnnaBridge 171:3a7713b1edbc 478 } NVIC_Type;
AnnaBridge 171:3a7713b1edbc 479
AnnaBridge 171:3a7713b1edbc 480 /* Software Triggered Interrupt Register Definitions */
AnnaBridge 171:3a7713b1edbc 481 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
AnnaBridge 171:3a7713b1edbc 482 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
AnnaBridge 171:3a7713b1edbc 483
AnnaBridge 171:3a7713b1edbc 484 /*@} end of group CMSIS_NVIC */
AnnaBridge 171:3a7713b1edbc 485
AnnaBridge 171:3a7713b1edbc 486
AnnaBridge 171:3a7713b1edbc 487 /**
AnnaBridge 171:3a7713b1edbc 488 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 489 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 171:3a7713b1edbc 490 \brief Type definitions for the System Control Block Registers
AnnaBridge 171:3a7713b1edbc 491 @{
AnnaBridge 171:3a7713b1edbc 492 */
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 /**
AnnaBridge 171:3a7713b1edbc 495 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 171:3a7713b1edbc 496 */
AnnaBridge 171:3a7713b1edbc 497 typedef struct
AnnaBridge 171:3a7713b1edbc 498 {
AnnaBridge 171:3a7713b1edbc 499 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 171:3a7713b1edbc 500 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 171:3a7713b1edbc 501 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 171:3a7713b1edbc 502 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 171:3a7713b1edbc 503 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 171:3a7713b1edbc 504 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 171:3a7713b1edbc 505 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
AnnaBridge 171:3a7713b1edbc 506 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 171:3a7713b1edbc 507 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
AnnaBridge 171:3a7713b1edbc 508 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
AnnaBridge 171:3a7713b1edbc 509 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
AnnaBridge 171:3a7713b1edbc 510 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
AnnaBridge 171:3a7713b1edbc 511 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
AnnaBridge 171:3a7713b1edbc 512 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
AnnaBridge 171:3a7713b1edbc 513 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
AnnaBridge 171:3a7713b1edbc 514 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
AnnaBridge 171:3a7713b1edbc 515 __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
AnnaBridge 171:3a7713b1edbc 516 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
AnnaBridge 171:3a7713b1edbc 517 __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
AnnaBridge 171:3a7713b1edbc 518 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
AnnaBridge 171:3a7713b1edbc 519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
AnnaBridge 171:3a7713b1edbc 520 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
AnnaBridge 171:3a7713b1edbc 521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
AnnaBridge 171:3a7713b1edbc 522 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
AnnaBridge 171:3a7713b1edbc 523 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
AnnaBridge 171:3a7713b1edbc 524 uint32_t RESERVED3[92U];
AnnaBridge 171:3a7713b1edbc 525 __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
AnnaBridge 171:3a7713b1edbc 526 uint32_t RESERVED4[15U];
AnnaBridge 171:3a7713b1edbc 527 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
AnnaBridge 171:3a7713b1edbc 528 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
AnnaBridge 171:3a7713b1edbc 529 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
AnnaBridge 171:3a7713b1edbc 530 uint32_t RESERVED5[1U];
AnnaBridge 171:3a7713b1edbc 531 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
AnnaBridge 171:3a7713b1edbc 532 uint32_t RESERVED6[1U];
AnnaBridge 171:3a7713b1edbc 533 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
AnnaBridge 171:3a7713b1edbc 534 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
AnnaBridge 171:3a7713b1edbc 535 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
AnnaBridge 171:3a7713b1edbc 536 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
AnnaBridge 171:3a7713b1edbc 537 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
AnnaBridge 171:3a7713b1edbc 538 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
AnnaBridge 171:3a7713b1edbc 539 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
AnnaBridge 171:3a7713b1edbc 540 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
AnnaBridge 171:3a7713b1edbc 541 uint32_t RESERVED7[6U];
AnnaBridge 171:3a7713b1edbc 542 __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
AnnaBridge 171:3a7713b1edbc 543 __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
AnnaBridge 171:3a7713b1edbc 544 __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
AnnaBridge 171:3a7713b1edbc 545 __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
AnnaBridge 171:3a7713b1edbc 546 __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
AnnaBridge 171:3a7713b1edbc 547 uint32_t RESERVED8[1U];
AnnaBridge 171:3a7713b1edbc 548 __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
AnnaBridge 171:3a7713b1edbc 549 } SCB_Type;
AnnaBridge 171:3a7713b1edbc 550
AnnaBridge 171:3a7713b1edbc 551 /* SCB CPUID Register Definitions */
AnnaBridge 171:3a7713b1edbc 552 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 171:3a7713b1edbc 553 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 171:3a7713b1edbc 554
AnnaBridge 171:3a7713b1edbc 555 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 171:3a7713b1edbc 556 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 171:3a7713b1edbc 559 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 171:3a7713b1edbc 560
AnnaBridge 171:3a7713b1edbc 561 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 171:3a7713b1edbc 562 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 171:3a7713b1edbc 563
AnnaBridge 171:3a7713b1edbc 564 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 171:3a7713b1edbc 565 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 171:3a7713b1edbc 566
AnnaBridge 171:3a7713b1edbc 567 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 171:3a7713b1edbc 568 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
AnnaBridge 171:3a7713b1edbc 569 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
AnnaBridge 171:3a7713b1edbc 570
AnnaBridge 171:3a7713b1edbc 571 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
AnnaBridge 171:3a7713b1edbc 572 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
AnnaBridge 171:3a7713b1edbc 573
AnnaBridge 171:3a7713b1edbc 574 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
AnnaBridge 171:3a7713b1edbc 575 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
AnnaBridge 171:3a7713b1edbc 576
AnnaBridge 171:3a7713b1edbc 577 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 171:3a7713b1edbc 578 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 171:3a7713b1edbc 579
AnnaBridge 171:3a7713b1edbc 580 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 171:3a7713b1edbc 581 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 171:3a7713b1edbc 582
AnnaBridge 171:3a7713b1edbc 583 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 171:3a7713b1edbc 584 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 171:3a7713b1edbc 585
AnnaBridge 171:3a7713b1edbc 586 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 171:3a7713b1edbc 587 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 171:3a7713b1edbc 588
AnnaBridge 171:3a7713b1edbc 589 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
AnnaBridge 171:3a7713b1edbc 590 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
AnnaBridge 171:3a7713b1edbc 591
AnnaBridge 171:3a7713b1edbc 592 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 171:3a7713b1edbc 593 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 171:3a7713b1edbc 594
AnnaBridge 171:3a7713b1edbc 595 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 171:3a7713b1edbc 596 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 171:3a7713b1edbc 597
AnnaBridge 171:3a7713b1edbc 598 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 171:3a7713b1edbc 599 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 171:3a7713b1edbc 600
AnnaBridge 171:3a7713b1edbc 601 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
AnnaBridge 171:3a7713b1edbc 602 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
AnnaBridge 171:3a7713b1edbc 603
AnnaBridge 171:3a7713b1edbc 604 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 171:3a7713b1edbc 605 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 606
AnnaBridge 171:3a7713b1edbc 607 /* SCB Vector Table Offset Register Definitions */
AnnaBridge 171:3a7713b1edbc 608 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 171:3a7713b1edbc 609 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 171:3a7713b1edbc 610
AnnaBridge 171:3a7713b1edbc 611 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 612 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 171:3a7713b1edbc 613 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 171:3a7713b1edbc 614
AnnaBridge 171:3a7713b1edbc 615 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 171:3a7713b1edbc 616 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 171:3a7713b1edbc 617
AnnaBridge 171:3a7713b1edbc 618 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 171:3a7713b1edbc 619 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 171:3a7713b1edbc 620
AnnaBridge 171:3a7713b1edbc 621 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
AnnaBridge 171:3a7713b1edbc 622 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
AnnaBridge 171:3a7713b1edbc 623
AnnaBridge 171:3a7713b1edbc 624 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
AnnaBridge 171:3a7713b1edbc 625 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
AnnaBridge 171:3a7713b1edbc 626
AnnaBridge 171:3a7713b1edbc 627 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
AnnaBridge 171:3a7713b1edbc 628 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
AnnaBridge 171:3a7713b1edbc 629
AnnaBridge 171:3a7713b1edbc 630 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
AnnaBridge 171:3a7713b1edbc 631 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
AnnaBridge 171:3a7713b1edbc 632
AnnaBridge 171:3a7713b1edbc 633 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 171:3a7713b1edbc 634 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 171:3a7713b1edbc 635
AnnaBridge 171:3a7713b1edbc 636 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 171:3a7713b1edbc 637 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 171:3a7713b1edbc 638
AnnaBridge 171:3a7713b1edbc 639 /* SCB System Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 640 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 171:3a7713b1edbc 641 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 171:3a7713b1edbc 642
AnnaBridge 171:3a7713b1edbc 643 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
AnnaBridge 171:3a7713b1edbc 644 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
AnnaBridge 171:3a7713b1edbc 645
AnnaBridge 171:3a7713b1edbc 646 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 171:3a7713b1edbc 647 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 171:3a7713b1edbc 650 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 171:3a7713b1edbc 651
AnnaBridge 171:3a7713b1edbc 652 /* SCB Configuration Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 653 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
AnnaBridge 171:3a7713b1edbc 654 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
AnnaBridge 171:3a7713b1edbc 655
AnnaBridge 171:3a7713b1edbc 656 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
AnnaBridge 171:3a7713b1edbc 657 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
AnnaBridge 171:3a7713b1edbc 658
AnnaBridge 171:3a7713b1edbc 659 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
AnnaBridge 171:3a7713b1edbc 660 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
AnnaBridge 171:3a7713b1edbc 661
AnnaBridge 171:3a7713b1edbc 662 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
AnnaBridge 171:3a7713b1edbc 663 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
AnnaBridge 171:3a7713b1edbc 664
AnnaBridge 171:3a7713b1edbc 665 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
AnnaBridge 171:3a7713b1edbc 666 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
AnnaBridge 171:3a7713b1edbc 667
AnnaBridge 171:3a7713b1edbc 668 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
AnnaBridge 171:3a7713b1edbc 669 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
AnnaBridge 171:3a7713b1edbc 670
AnnaBridge 171:3a7713b1edbc 671 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 171:3a7713b1edbc 672 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 171:3a7713b1edbc 673
AnnaBridge 171:3a7713b1edbc 674 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
AnnaBridge 171:3a7713b1edbc 675 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
AnnaBridge 171:3a7713b1edbc 676
AnnaBridge 171:3a7713b1edbc 677 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 171:3a7713b1edbc 678 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
AnnaBridge 171:3a7713b1edbc 679 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
AnnaBridge 171:3a7713b1edbc 680
AnnaBridge 171:3a7713b1edbc 681 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
AnnaBridge 171:3a7713b1edbc 682 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
AnnaBridge 171:3a7713b1edbc 683
AnnaBridge 171:3a7713b1edbc 684 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
AnnaBridge 171:3a7713b1edbc 685 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
AnnaBridge 171:3a7713b1edbc 686
AnnaBridge 171:3a7713b1edbc 687 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
AnnaBridge 171:3a7713b1edbc 688 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
AnnaBridge 171:3a7713b1edbc 689
AnnaBridge 171:3a7713b1edbc 690 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
AnnaBridge 171:3a7713b1edbc 691 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
AnnaBridge 171:3a7713b1edbc 692
AnnaBridge 171:3a7713b1edbc 693 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
AnnaBridge 171:3a7713b1edbc 694 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
AnnaBridge 171:3a7713b1edbc 695
AnnaBridge 171:3a7713b1edbc 696 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 171:3a7713b1edbc 697 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 171:3a7713b1edbc 698
AnnaBridge 171:3a7713b1edbc 699 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
AnnaBridge 171:3a7713b1edbc 700 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
AnnaBridge 171:3a7713b1edbc 701
AnnaBridge 171:3a7713b1edbc 702 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
AnnaBridge 171:3a7713b1edbc 703 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
AnnaBridge 171:3a7713b1edbc 704
AnnaBridge 171:3a7713b1edbc 705 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
AnnaBridge 171:3a7713b1edbc 706 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
AnnaBridge 171:3a7713b1edbc 707
AnnaBridge 171:3a7713b1edbc 708 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
AnnaBridge 171:3a7713b1edbc 709 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
AnnaBridge 171:3a7713b1edbc 710
AnnaBridge 171:3a7713b1edbc 711 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
AnnaBridge 171:3a7713b1edbc 712 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
AnnaBridge 171:3a7713b1edbc 713
AnnaBridge 171:3a7713b1edbc 714 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
AnnaBridge 171:3a7713b1edbc 715 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
AnnaBridge 171:3a7713b1edbc 716
AnnaBridge 171:3a7713b1edbc 717 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
AnnaBridge 171:3a7713b1edbc 718 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
AnnaBridge 171:3a7713b1edbc 719
AnnaBridge 171:3a7713b1edbc 720 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
AnnaBridge 171:3a7713b1edbc 721 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
AnnaBridge 171:3a7713b1edbc 722
AnnaBridge 171:3a7713b1edbc 723 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
AnnaBridge 171:3a7713b1edbc 724 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
AnnaBridge 171:3a7713b1edbc 725
AnnaBridge 171:3a7713b1edbc 726 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
AnnaBridge 171:3a7713b1edbc 727 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
AnnaBridge 171:3a7713b1edbc 728
AnnaBridge 171:3a7713b1edbc 729 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
AnnaBridge 171:3a7713b1edbc 730 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
AnnaBridge 171:3a7713b1edbc 731
AnnaBridge 171:3a7713b1edbc 732 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
AnnaBridge 171:3a7713b1edbc 733 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
AnnaBridge 171:3a7713b1edbc 734
AnnaBridge 171:3a7713b1edbc 735 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
AnnaBridge 171:3a7713b1edbc 736 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
AnnaBridge 171:3a7713b1edbc 737
AnnaBridge 171:3a7713b1edbc 738 /* SCB Configurable Fault Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 739 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
AnnaBridge 171:3a7713b1edbc 740 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
AnnaBridge 171:3a7713b1edbc 741
AnnaBridge 171:3a7713b1edbc 742 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
AnnaBridge 171:3a7713b1edbc 743 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
AnnaBridge 171:3a7713b1edbc 744
AnnaBridge 171:3a7713b1edbc 745 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
AnnaBridge 171:3a7713b1edbc 746 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
AnnaBridge 171:3a7713b1edbc 747
AnnaBridge 171:3a7713b1edbc 748 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 171:3a7713b1edbc 749 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
AnnaBridge 171:3a7713b1edbc 750 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
AnnaBridge 171:3a7713b1edbc 751
AnnaBridge 171:3a7713b1edbc 752 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
AnnaBridge 171:3a7713b1edbc 753 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
AnnaBridge 171:3a7713b1edbc 754
AnnaBridge 171:3a7713b1edbc 755 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
AnnaBridge 171:3a7713b1edbc 756 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
AnnaBridge 171:3a7713b1edbc 757
AnnaBridge 171:3a7713b1edbc 758 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
AnnaBridge 171:3a7713b1edbc 759 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
AnnaBridge 171:3a7713b1edbc 760
AnnaBridge 171:3a7713b1edbc 761 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
AnnaBridge 171:3a7713b1edbc 762 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
AnnaBridge 171:3a7713b1edbc 763
AnnaBridge 171:3a7713b1edbc 764 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
AnnaBridge 171:3a7713b1edbc 765 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
AnnaBridge 171:3a7713b1edbc 766
AnnaBridge 171:3a7713b1edbc 767 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 171:3a7713b1edbc 768 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
AnnaBridge 171:3a7713b1edbc 769 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
AnnaBridge 171:3a7713b1edbc 770
AnnaBridge 171:3a7713b1edbc 771 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
AnnaBridge 171:3a7713b1edbc 772 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
AnnaBridge 171:3a7713b1edbc 773
AnnaBridge 171:3a7713b1edbc 774 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
AnnaBridge 171:3a7713b1edbc 775 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
AnnaBridge 171:3a7713b1edbc 776
AnnaBridge 171:3a7713b1edbc 777 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
AnnaBridge 171:3a7713b1edbc 778 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
AnnaBridge 171:3a7713b1edbc 779
AnnaBridge 171:3a7713b1edbc 780 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
AnnaBridge 171:3a7713b1edbc 781 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
AnnaBridge 171:3a7713b1edbc 782
AnnaBridge 171:3a7713b1edbc 783 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
AnnaBridge 171:3a7713b1edbc 784 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
AnnaBridge 171:3a7713b1edbc 785
AnnaBridge 171:3a7713b1edbc 786 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
AnnaBridge 171:3a7713b1edbc 787 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
AnnaBridge 171:3a7713b1edbc 788
AnnaBridge 171:3a7713b1edbc 789 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge 171:3a7713b1edbc 790 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
AnnaBridge 171:3a7713b1edbc 791 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
AnnaBridge 171:3a7713b1edbc 792
AnnaBridge 171:3a7713b1edbc 793 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
AnnaBridge 171:3a7713b1edbc 794 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
AnnaBridge 171:3a7713b1edbc 795
AnnaBridge 171:3a7713b1edbc 796 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
AnnaBridge 171:3a7713b1edbc 797 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
AnnaBridge 171:3a7713b1edbc 798
AnnaBridge 171:3a7713b1edbc 799 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
AnnaBridge 171:3a7713b1edbc 800 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
AnnaBridge 171:3a7713b1edbc 801
AnnaBridge 171:3a7713b1edbc 802 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
AnnaBridge 171:3a7713b1edbc 803 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
AnnaBridge 171:3a7713b1edbc 804
AnnaBridge 171:3a7713b1edbc 805 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
AnnaBridge 171:3a7713b1edbc 806 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
AnnaBridge 171:3a7713b1edbc 807
AnnaBridge 171:3a7713b1edbc 808 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
AnnaBridge 171:3a7713b1edbc 809 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
AnnaBridge 171:3a7713b1edbc 810
AnnaBridge 171:3a7713b1edbc 811 /* SCB Hard Fault Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 812 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
AnnaBridge 171:3a7713b1edbc 813 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
AnnaBridge 171:3a7713b1edbc 814
AnnaBridge 171:3a7713b1edbc 815 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
AnnaBridge 171:3a7713b1edbc 816 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
AnnaBridge 171:3a7713b1edbc 817
AnnaBridge 171:3a7713b1edbc 818 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
AnnaBridge 171:3a7713b1edbc 819 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
AnnaBridge 171:3a7713b1edbc 820
AnnaBridge 171:3a7713b1edbc 821 /* SCB Debug Fault Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 822 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
AnnaBridge 171:3a7713b1edbc 823 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
AnnaBridge 171:3a7713b1edbc 824
AnnaBridge 171:3a7713b1edbc 825 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
AnnaBridge 171:3a7713b1edbc 826 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
AnnaBridge 171:3a7713b1edbc 827
AnnaBridge 171:3a7713b1edbc 828 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
AnnaBridge 171:3a7713b1edbc 829 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
AnnaBridge 171:3a7713b1edbc 830
AnnaBridge 171:3a7713b1edbc 831 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
AnnaBridge 171:3a7713b1edbc 832 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
AnnaBridge 171:3a7713b1edbc 833
AnnaBridge 171:3a7713b1edbc 834 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
AnnaBridge 171:3a7713b1edbc 835 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
AnnaBridge 171:3a7713b1edbc 836
AnnaBridge 171:3a7713b1edbc 837 /* SCB Non-Secure Access Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 838 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
AnnaBridge 171:3a7713b1edbc 839 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
AnnaBridge 171:3a7713b1edbc 840
AnnaBridge 171:3a7713b1edbc 841 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
AnnaBridge 171:3a7713b1edbc 842 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
AnnaBridge 171:3a7713b1edbc 843
AnnaBridge 171:3a7713b1edbc 844 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
AnnaBridge 171:3a7713b1edbc 845 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
AnnaBridge 171:3a7713b1edbc 846
AnnaBridge 171:3a7713b1edbc 847 /* SCB Cache Level ID Register Definitions */
AnnaBridge 171:3a7713b1edbc 848 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
AnnaBridge 171:3a7713b1edbc 849 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
AnnaBridge 171:3a7713b1edbc 850
AnnaBridge 171:3a7713b1edbc 851 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
AnnaBridge 171:3a7713b1edbc 852 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
AnnaBridge 171:3a7713b1edbc 853
AnnaBridge 171:3a7713b1edbc 854 /* SCB Cache Type Register Definitions */
AnnaBridge 171:3a7713b1edbc 855 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
AnnaBridge 171:3a7713b1edbc 856 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
AnnaBridge 171:3a7713b1edbc 857
AnnaBridge 171:3a7713b1edbc 858 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
AnnaBridge 171:3a7713b1edbc 859 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
AnnaBridge 171:3a7713b1edbc 860
AnnaBridge 171:3a7713b1edbc 861 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
AnnaBridge 171:3a7713b1edbc 862 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
AnnaBridge 171:3a7713b1edbc 863
AnnaBridge 171:3a7713b1edbc 864 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
AnnaBridge 171:3a7713b1edbc 865 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
AnnaBridge 171:3a7713b1edbc 866
AnnaBridge 171:3a7713b1edbc 867 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
AnnaBridge 171:3a7713b1edbc 868 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
AnnaBridge 171:3a7713b1edbc 869
AnnaBridge 171:3a7713b1edbc 870 /* SCB Cache Size ID Register Definitions */
AnnaBridge 171:3a7713b1edbc 871 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
AnnaBridge 171:3a7713b1edbc 872 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
AnnaBridge 171:3a7713b1edbc 873
AnnaBridge 171:3a7713b1edbc 874 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
AnnaBridge 171:3a7713b1edbc 875 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
AnnaBridge 171:3a7713b1edbc 876
AnnaBridge 171:3a7713b1edbc 877 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
AnnaBridge 171:3a7713b1edbc 878 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
AnnaBridge 171:3a7713b1edbc 879
AnnaBridge 171:3a7713b1edbc 880 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
AnnaBridge 171:3a7713b1edbc 881 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
AnnaBridge 171:3a7713b1edbc 882
AnnaBridge 171:3a7713b1edbc 883 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
AnnaBridge 171:3a7713b1edbc 884 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
AnnaBridge 171:3a7713b1edbc 885
AnnaBridge 171:3a7713b1edbc 886 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
AnnaBridge 171:3a7713b1edbc 887 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
AnnaBridge 171:3a7713b1edbc 888
AnnaBridge 171:3a7713b1edbc 889 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
AnnaBridge 171:3a7713b1edbc 890 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
AnnaBridge 171:3a7713b1edbc 891
AnnaBridge 171:3a7713b1edbc 892 /* SCB Cache Size Selection Register Definitions */
AnnaBridge 171:3a7713b1edbc 893 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
AnnaBridge 171:3a7713b1edbc 894 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
AnnaBridge 171:3a7713b1edbc 895
AnnaBridge 171:3a7713b1edbc 896 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
AnnaBridge 171:3a7713b1edbc 897 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
AnnaBridge 171:3a7713b1edbc 898
AnnaBridge 171:3a7713b1edbc 899 /* SCB Software Triggered Interrupt Register Definitions */
AnnaBridge 171:3a7713b1edbc 900 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
AnnaBridge 171:3a7713b1edbc 901 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
AnnaBridge 171:3a7713b1edbc 902
AnnaBridge 171:3a7713b1edbc 903 /* SCB D-Cache Invalidate by Set-way Register Definitions */
AnnaBridge 171:3a7713b1edbc 904 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
AnnaBridge 171:3a7713b1edbc 905 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
AnnaBridge 171:3a7713b1edbc 906
AnnaBridge 171:3a7713b1edbc 907 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
AnnaBridge 171:3a7713b1edbc 908 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
AnnaBridge 171:3a7713b1edbc 909
AnnaBridge 171:3a7713b1edbc 910 /* SCB D-Cache Clean by Set-way Register Definitions */
AnnaBridge 171:3a7713b1edbc 911 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
AnnaBridge 171:3a7713b1edbc 912 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
AnnaBridge 171:3a7713b1edbc 913
AnnaBridge 171:3a7713b1edbc 914 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
AnnaBridge 171:3a7713b1edbc 915 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
AnnaBridge 171:3a7713b1edbc 916
AnnaBridge 171:3a7713b1edbc 917 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
AnnaBridge 171:3a7713b1edbc 918 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
AnnaBridge 171:3a7713b1edbc 919 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
AnnaBridge 171:3a7713b1edbc 920
AnnaBridge 171:3a7713b1edbc 921 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
AnnaBridge 171:3a7713b1edbc 922 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
AnnaBridge 171:3a7713b1edbc 923
AnnaBridge 171:3a7713b1edbc 924 /* Instruction Tightly-Coupled Memory Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 925 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
AnnaBridge 171:3a7713b1edbc 926 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
AnnaBridge 171:3a7713b1edbc 927
AnnaBridge 171:3a7713b1edbc 928 #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */
AnnaBridge 171:3a7713b1edbc 929 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
AnnaBridge 171:3a7713b1edbc 930
AnnaBridge 171:3a7713b1edbc 931 #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */
AnnaBridge 171:3a7713b1edbc 932 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
AnnaBridge 171:3a7713b1edbc 933
AnnaBridge 171:3a7713b1edbc 934 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
AnnaBridge 171:3a7713b1edbc 935 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
AnnaBridge 171:3a7713b1edbc 936
AnnaBridge 171:3a7713b1edbc 937 /* Data Tightly-Coupled Memory Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 938 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
AnnaBridge 171:3a7713b1edbc 939 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
AnnaBridge 171:3a7713b1edbc 940
AnnaBridge 171:3a7713b1edbc 941 #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */
AnnaBridge 171:3a7713b1edbc 942 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
AnnaBridge 171:3a7713b1edbc 943
AnnaBridge 171:3a7713b1edbc 944 #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */
AnnaBridge 171:3a7713b1edbc 945 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
AnnaBridge 171:3a7713b1edbc 946
AnnaBridge 171:3a7713b1edbc 947 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
AnnaBridge 171:3a7713b1edbc 948 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
AnnaBridge 171:3a7713b1edbc 949
AnnaBridge 171:3a7713b1edbc 950 /* AHBP Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 951 #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */
AnnaBridge 171:3a7713b1edbc 952 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
AnnaBridge 171:3a7713b1edbc 953
AnnaBridge 171:3a7713b1edbc 954 #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */
AnnaBridge 171:3a7713b1edbc 955 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
AnnaBridge 171:3a7713b1edbc 956
AnnaBridge 171:3a7713b1edbc 957 /* L1 Cache Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 958 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
AnnaBridge 171:3a7713b1edbc 959 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
AnnaBridge 171:3a7713b1edbc 960
AnnaBridge 171:3a7713b1edbc 961 #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */
AnnaBridge 171:3a7713b1edbc 962 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
AnnaBridge 171:3a7713b1edbc 963
AnnaBridge 171:3a7713b1edbc 964 #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */
AnnaBridge 171:3a7713b1edbc 965 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
AnnaBridge 171:3a7713b1edbc 966
AnnaBridge 171:3a7713b1edbc 967 /* AHBS Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 968 #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */
AnnaBridge 171:3a7713b1edbc 969 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
AnnaBridge 171:3a7713b1edbc 970
AnnaBridge 171:3a7713b1edbc 971 #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */
AnnaBridge 171:3a7713b1edbc 972 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
AnnaBridge 171:3a7713b1edbc 973
AnnaBridge 171:3a7713b1edbc 974 #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/
AnnaBridge 171:3a7713b1edbc 975 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
AnnaBridge 171:3a7713b1edbc 976
AnnaBridge 171:3a7713b1edbc 977 /* Auxiliary Bus Fault Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 978 #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/
AnnaBridge 171:3a7713b1edbc 979 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
AnnaBridge 171:3a7713b1edbc 980
AnnaBridge 171:3a7713b1edbc 981 #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/
AnnaBridge 171:3a7713b1edbc 982 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
AnnaBridge 171:3a7713b1edbc 983
AnnaBridge 171:3a7713b1edbc 984 #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/
AnnaBridge 171:3a7713b1edbc 985 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
AnnaBridge 171:3a7713b1edbc 986
AnnaBridge 171:3a7713b1edbc 987 #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/
AnnaBridge 171:3a7713b1edbc 988 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
AnnaBridge 171:3a7713b1edbc 989
AnnaBridge 171:3a7713b1edbc 990 #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/
AnnaBridge 171:3a7713b1edbc 991 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
AnnaBridge 171:3a7713b1edbc 992
AnnaBridge 171:3a7713b1edbc 993 #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/
AnnaBridge 171:3a7713b1edbc 994 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
AnnaBridge 171:3a7713b1edbc 995
AnnaBridge 171:3a7713b1edbc 996 /*@} end of group CMSIS_SCB */
AnnaBridge 171:3a7713b1edbc 997
AnnaBridge 171:3a7713b1edbc 998
AnnaBridge 171:3a7713b1edbc 999 /**
AnnaBridge 171:3a7713b1edbc 1000 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1001 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 171:3a7713b1edbc 1002 \brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge 171:3a7713b1edbc 1003 @{
AnnaBridge 171:3a7713b1edbc 1004 */
AnnaBridge 171:3a7713b1edbc 1005
AnnaBridge 171:3a7713b1edbc 1006 /**
AnnaBridge 171:3a7713b1edbc 1007 \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge 171:3a7713b1edbc 1008 */
AnnaBridge 171:3a7713b1edbc 1009 typedef struct
AnnaBridge 171:3a7713b1edbc 1010 {
AnnaBridge 171:3a7713b1edbc 1011 uint32_t RESERVED0[1U];
AnnaBridge 171:3a7713b1edbc 1012 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
AnnaBridge 171:3a7713b1edbc 1013 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
AnnaBridge 171:3a7713b1edbc 1014 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
AnnaBridge 171:3a7713b1edbc 1015 } SCnSCB_Type;
AnnaBridge 171:3a7713b1edbc 1016
AnnaBridge 171:3a7713b1edbc 1017 /* Interrupt Controller Type Register Definitions */
AnnaBridge 171:3a7713b1edbc 1018 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
AnnaBridge 171:3a7713b1edbc 1019 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
AnnaBridge 171:3a7713b1edbc 1020
AnnaBridge 171:3a7713b1edbc 1021 /*@} end of group CMSIS_SCnotSCB */
AnnaBridge 171:3a7713b1edbc 1022
AnnaBridge 171:3a7713b1edbc 1023
AnnaBridge 171:3a7713b1edbc 1024 /**
AnnaBridge 171:3a7713b1edbc 1025 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1026 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 171:3a7713b1edbc 1027 \brief Type definitions for the System Timer Registers.
AnnaBridge 171:3a7713b1edbc 1028 @{
AnnaBridge 171:3a7713b1edbc 1029 */
AnnaBridge 171:3a7713b1edbc 1030
AnnaBridge 171:3a7713b1edbc 1031 /**
AnnaBridge 171:3a7713b1edbc 1032 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 171:3a7713b1edbc 1033 */
AnnaBridge 171:3a7713b1edbc 1034 typedef struct
AnnaBridge 171:3a7713b1edbc 1035 {
AnnaBridge 171:3a7713b1edbc 1036 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 171:3a7713b1edbc 1037 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 171:3a7713b1edbc 1038 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 171:3a7713b1edbc 1039 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 171:3a7713b1edbc 1040 } SysTick_Type;
AnnaBridge 171:3a7713b1edbc 1041
AnnaBridge 171:3a7713b1edbc 1042 /* SysTick Control / Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 1043 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 171:3a7713b1edbc 1044 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 171:3a7713b1edbc 1045
AnnaBridge 171:3a7713b1edbc 1046 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 171:3a7713b1edbc 1047 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 171:3a7713b1edbc 1048
AnnaBridge 171:3a7713b1edbc 1049 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 171:3a7713b1edbc 1050 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 171:3a7713b1edbc 1051
AnnaBridge 171:3a7713b1edbc 1052 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 171:3a7713b1edbc 1053 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 1054
AnnaBridge 171:3a7713b1edbc 1055 /* SysTick Reload Register Definitions */
AnnaBridge 171:3a7713b1edbc 1056 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 171:3a7713b1edbc 1057 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 171:3a7713b1edbc 1058
AnnaBridge 171:3a7713b1edbc 1059 /* SysTick Current Register Definitions */
AnnaBridge 171:3a7713b1edbc 1060 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 171:3a7713b1edbc 1061 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 171:3a7713b1edbc 1062
AnnaBridge 171:3a7713b1edbc 1063 /* SysTick Calibration Register Definitions */
AnnaBridge 171:3a7713b1edbc 1064 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 171:3a7713b1edbc 1065 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 171:3a7713b1edbc 1066
AnnaBridge 171:3a7713b1edbc 1067 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 171:3a7713b1edbc 1068 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 171:3a7713b1edbc 1069
AnnaBridge 171:3a7713b1edbc 1070 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 171:3a7713b1edbc 1071 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 171:3a7713b1edbc 1072
AnnaBridge 171:3a7713b1edbc 1073 /*@} end of group CMSIS_SysTick */
AnnaBridge 171:3a7713b1edbc 1074
AnnaBridge 171:3a7713b1edbc 1075
AnnaBridge 171:3a7713b1edbc 1076 /**
AnnaBridge 171:3a7713b1edbc 1077 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1078 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge 171:3a7713b1edbc 1079 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
AnnaBridge 171:3a7713b1edbc 1080 @{
AnnaBridge 171:3a7713b1edbc 1081 */
AnnaBridge 171:3a7713b1edbc 1082
AnnaBridge 171:3a7713b1edbc 1083 /**
AnnaBridge 171:3a7713b1edbc 1084 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
AnnaBridge 171:3a7713b1edbc 1085 */
AnnaBridge 171:3a7713b1edbc 1086 typedef struct
AnnaBridge 171:3a7713b1edbc 1087 {
AnnaBridge 171:3a7713b1edbc 1088 __OM union
AnnaBridge 171:3a7713b1edbc 1089 {
AnnaBridge 171:3a7713b1edbc 1090 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
AnnaBridge 171:3a7713b1edbc 1091 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
AnnaBridge 171:3a7713b1edbc 1092 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
AnnaBridge 171:3a7713b1edbc 1093 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
AnnaBridge 171:3a7713b1edbc 1094 uint32_t RESERVED0[864U];
AnnaBridge 171:3a7713b1edbc 1095 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
AnnaBridge 171:3a7713b1edbc 1096 uint32_t RESERVED1[15U];
AnnaBridge 171:3a7713b1edbc 1097 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
AnnaBridge 171:3a7713b1edbc 1098 uint32_t RESERVED2[15U];
AnnaBridge 171:3a7713b1edbc 1099 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
AnnaBridge 171:3a7713b1edbc 1100 uint32_t RESERVED3[29U];
AnnaBridge 171:3a7713b1edbc 1101 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
AnnaBridge 171:3a7713b1edbc 1102 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
AnnaBridge 171:3a7713b1edbc 1103 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
AnnaBridge 171:3a7713b1edbc 1104 uint32_t RESERVED4[43U];
AnnaBridge 171:3a7713b1edbc 1105 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
AnnaBridge 171:3a7713b1edbc 1106 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
AnnaBridge 171:3a7713b1edbc 1107 uint32_t RESERVED5[1U];
AnnaBridge 171:3a7713b1edbc 1108 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
AnnaBridge 171:3a7713b1edbc 1109 uint32_t RESERVED6[4U];
AnnaBridge 171:3a7713b1edbc 1110 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
AnnaBridge 171:3a7713b1edbc 1111 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
AnnaBridge 171:3a7713b1edbc 1112 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
AnnaBridge 171:3a7713b1edbc 1113 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
AnnaBridge 171:3a7713b1edbc 1114 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
AnnaBridge 171:3a7713b1edbc 1115 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
AnnaBridge 171:3a7713b1edbc 1116 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
AnnaBridge 171:3a7713b1edbc 1117 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
AnnaBridge 171:3a7713b1edbc 1118 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
AnnaBridge 171:3a7713b1edbc 1119 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
AnnaBridge 171:3a7713b1edbc 1120 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
AnnaBridge 171:3a7713b1edbc 1121 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
AnnaBridge 171:3a7713b1edbc 1122 } ITM_Type;
AnnaBridge 171:3a7713b1edbc 1123
AnnaBridge 171:3a7713b1edbc 1124 /* ITM Stimulus Port Register Definitions */
AnnaBridge 171:3a7713b1edbc 1125 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
AnnaBridge 171:3a7713b1edbc 1126 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
AnnaBridge 171:3a7713b1edbc 1127
AnnaBridge 171:3a7713b1edbc 1128 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
AnnaBridge 171:3a7713b1edbc 1129 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
AnnaBridge 171:3a7713b1edbc 1130
AnnaBridge 171:3a7713b1edbc 1131 /* ITM Trace Privilege Register Definitions */
AnnaBridge 171:3a7713b1edbc 1132 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
AnnaBridge 171:3a7713b1edbc 1133 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
AnnaBridge 171:3a7713b1edbc 1134
AnnaBridge 171:3a7713b1edbc 1135 /* ITM Trace Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1136 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
AnnaBridge 171:3a7713b1edbc 1137 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
AnnaBridge 171:3a7713b1edbc 1138
AnnaBridge 171:3a7713b1edbc 1139 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
AnnaBridge 171:3a7713b1edbc 1140 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
AnnaBridge 171:3a7713b1edbc 1141
AnnaBridge 171:3a7713b1edbc 1142 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
AnnaBridge 171:3a7713b1edbc 1143 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
AnnaBridge 171:3a7713b1edbc 1144
AnnaBridge 171:3a7713b1edbc 1145 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
AnnaBridge 171:3a7713b1edbc 1146 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
AnnaBridge 171:3a7713b1edbc 1147
AnnaBridge 171:3a7713b1edbc 1148 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
AnnaBridge 171:3a7713b1edbc 1149 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
AnnaBridge 171:3a7713b1edbc 1150
AnnaBridge 171:3a7713b1edbc 1151 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
AnnaBridge 171:3a7713b1edbc 1152 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
AnnaBridge 171:3a7713b1edbc 1153
AnnaBridge 171:3a7713b1edbc 1154 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
AnnaBridge 171:3a7713b1edbc 1155 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
AnnaBridge 171:3a7713b1edbc 1156
AnnaBridge 171:3a7713b1edbc 1157 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
AnnaBridge 171:3a7713b1edbc 1158 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
AnnaBridge 171:3a7713b1edbc 1159
AnnaBridge 171:3a7713b1edbc 1160 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
AnnaBridge 171:3a7713b1edbc 1161 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
AnnaBridge 171:3a7713b1edbc 1162
AnnaBridge 171:3a7713b1edbc 1163 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
AnnaBridge 171:3a7713b1edbc 1164 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
AnnaBridge 171:3a7713b1edbc 1165
AnnaBridge 171:3a7713b1edbc 1166 /* ITM Integration Write Register Definitions */
AnnaBridge 171:3a7713b1edbc 1167 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
AnnaBridge 171:3a7713b1edbc 1168 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
AnnaBridge 171:3a7713b1edbc 1169
AnnaBridge 171:3a7713b1edbc 1170 /* ITM Integration Read Register Definitions */
AnnaBridge 171:3a7713b1edbc 1171 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
AnnaBridge 171:3a7713b1edbc 1172 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
AnnaBridge 171:3a7713b1edbc 1173
AnnaBridge 171:3a7713b1edbc 1174 /* ITM Integration Mode Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1175 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
AnnaBridge 171:3a7713b1edbc 1176 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
AnnaBridge 171:3a7713b1edbc 1177
AnnaBridge 171:3a7713b1edbc 1178 /* ITM Lock Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 1179 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
AnnaBridge 171:3a7713b1edbc 1180 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
AnnaBridge 171:3a7713b1edbc 1181
AnnaBridge 171:3a7713b1edbc 1182 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
AnnaBridge 171:3a7713b1edbc 1183 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
AnnaBridge 171:3a7713b1edbc 1184
AnnaBridge 171:3a7713b1edbc 1185 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
AnnaBridge 171:3a7713b1edbc 1186 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
AnnaBridge 171:3a7713b1edbc 1187
AnnaBridge 171:3a7713b1edbc 1188 /*@}*/ /* end of group CMSIS_ITM */
AnnaBridge 171:3a7713b1edbc 1189
AnnaBridge 171:3a7713b1edbc 1190
AnnaBridge 171:3a7713b1edbc 1191 /**
AnnaBridge 171:3a7713b1edbc 1192 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1193 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge 171:3a7713b1edbc 1194 \brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge 171:3a7713b1edbc 1195 @{
AnnaBridge 171:3a7713b1edbc 1196 */
AnnaBridge 171:3a7713b1edbc 1197
AnnaBridge 171:3a7713b1edbc 1198 /**
AnnaBridge 171:3a7713b1edbc 1199 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge 171:3a7713b1edbc 1200 */
AnnaBridge 171:3a7713b1edbc 1201 typedef struct
AnnaBridge 171:3a7713b1edbc 1202 {
AnnaBridge 171:3a7713b1edbc 1203 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
AnnaBridge 171:3a7713b1edbc 1204 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
AnnaBridge 171:3a7713b1edbc 1205 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
AnnaBridge 171:3a7713b1edbc 1206 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
AnnaBridge 171:3a7713b1edbc 1207 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
AnnaBridge 171:3a7713b1edbc 1208 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
AnnaBridge 171:3a7713b1edbc 1209 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
AnnaBridge 171:3a7713b1edbc 1210 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
AnnaBridge 171:3a7713b1edbc 1211 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
AnnaBridge 171:3a7713b1edbc 1212 uint32_t RESERVED1[1U];
AnnaBridge 171:3a7713b1edbc 1213 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
AnnaBridge 171:3a7713b1edbc 1214 uint32_t RESERVED2[1U];
AnnaBridge 171:3a7713b1edbc 1215 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
AnnaBridge 171:3a7713b1edbc 1216 uint32_t RESERVED3[1U];
AnnaBridge 171:3a7713b1edbc 1217 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
AnnaBridge 171:3a7713b1edbc 1218 uint32_t RESERVED4[1U];
AnnaBridge 171:3a7713b1edbc 1219 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
AnnaBridge 171:3a7713b1edbc 1220 uint32_t RESERVED5[1U];
AnnaBridge 171:3a7713b1edbc 1221 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
AnnaBridge 171:3a7713b1edbc 1222 uint32_t RESERVED6[1U];
AnnaBridge 171:3a7713b1edbc 1223 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
AnnaBridge 171:3a7713b1edbc 1224 uint32_t RESERVED7[1U];
AnnaBridge 171:3a7713b1edbc 1225 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
AnnaBridge 171:3a7713b1edbc 1226 uint32_t RESERVED8[1U];
AnnaBridge 171:3a7713b1edbc 1227 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
AnnaBridge 171:3a7713b1edbc 1228 uint32_t RESERVED9[1U];
AnnaBridge 171:3a7713b1edbc 1229 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
AnnaBridge 171:3a7713b1edbc 1230 uint32_t RESERVED10[1U];
AnnaBridge 171:3a7713b1edbc 1231 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
AnnaBridge 171:3a7713b1edbc 1232 uint32_t RESERVED11[1U];
AnnaBridge 171:3a7713b1edbc 1233 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
AnnaBridge 171:3a7713b1edbc 1234 uint32_t RESERVED12[1U];
AnnaBridge 171:3a7713b1edbc 1235 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
AnnaBridge 171:3a7713b1edbc 1236 uint32_t RESERVED13[1U];
AnnaBridge 171:3a7713b1edbc 1237 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
AnnaBridge 171:3a7713b1edbc 1238 uint32_t RESERVED14[1U];
AnnaBridge 171:3a7713b1edbc 1239 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
AnnaBridge 171:3a7713b1edbc 1240 uint32_t RESERVED15[1U];
AnnaBridge 171:3a7713b1edbc 1241 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
AnnaBridge 171:3a7713b1edbc 1242 uint32_t RESERVED16[1U];
AnnaBridge 171:3a7713b1edbc 1243 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
AnnaBridge 171:3a7713b1edbc 1244 uint32_t RESERVED17[1U];
AnnaBridge 171:3a7713b1edbc 1245 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
AnnaBridge 171:3a7713b1edbc 1246 uint32_t RESERVED18[1U];
AnnaBridge 171:3a7713b1edbc 1247 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
AnnaBridge 171:3a7713b1edbc 1248 uint32_t RESERVED19[1U];
AnnaBridge 171:3a7713b1edbc 1249 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
AnnaBridge 171:3a7713b1edbc 1250 uint32_t RESERVED20[1U];
AnnaBridge 171:3a7713b1edbc 1251 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
AnnaBridge 171:3a7713b1edbc 1252 uint32_t RESERVED21[1U];
AnnaBridge 171:3a7713b1edbc 1253 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
AnnaBridge 171:3a7713b1edbc 1254 uint32_t RESERVED22[1U];
AnnaBridge 171:3a7713b1edbc 1255 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
AnnaBridge 171:3a7713b1edbc 1256 uint32_t RESERVED23[1U];
AnnaBridge 171:3a7713b1edbc 1257 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
AnnaBridge 171:3a7713b1edbc 1258 uint32_t RESERVED24[1U];
AnnaBridge 171:3a7713b1edbc 1259 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
AnnaBridge 171:3a7713b1edbc 1260 uint32_t RESERVED25[1U];
AnnaBridge 171:3a7713b1edbc 1261 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
AnnaBridge 171:3a7713b1edbc 1262 uint32_t RESERVED26[1U];
AnnaBridge 171:3a7713b1edbc 1263 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
AnnaBridge 171:3a7713b1edbc 1264 uint32_t RESERVED27[1U];
AnnaBridge 171:3a7713b1edbc 1265 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
AnnaBridge 171:3a7713b1edbc 1266 uint32_t RESERVED28[1U];
AnnaBridge 171:3a7713b1edbc 1267 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
AnnaBridge 171:3a7713b1edbc 1268 uint32_t RESERVED29[1U];
AnnaBridge 171:3a7713b1edbc 1269 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
AnnaBridge 171:3a7713b1edbc 1270 uint32_t RESERVED30[1U];
AnnaBridge 171:3a7713b1edbc 1271 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
AnnaBridge 171:3a7713b1edbc 1272 uint32_t RESERVED31[1U];
AnnaBridge 171:3a7713b1edbc 1273 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
AnnaBridge 171:3a7713b1edbc 1274 uint32_t RESERVED32[934U];
AnnaBridge 171:3a7713b1edbc 1275 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
AnnaBridge 171:3a7713b1edbc 1276 uint32_t RESERVED33[1U];
AnnaBridge 171:3a7713b1edbc 1277 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
AnnaBridge 171:3a7713b1edbc 1278 } DWT_Type;
AnnaBridge 171:3a7713b1edbc 1279
AnnaBridge 171:3a7713b1edbc 1280 /* DWT Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1281 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
AnnaBridge 171:3a7713b1edbc 1282 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
AnnaBridge 171:3a7713b1edbc 1283
AnnaBridge 171:3a7713b1edbc 1284 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
AnnaBridge 171:3a7713b1edbc 1285 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
AnnaBridge 171:3a7713b1edbc 1286
AnnaBridge 171:3a7713b1edbc 1287 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
AnnaBridge 171:3a7713b1edbc 1288 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
AnnaBridge 171:3a7713b1edbc 1289
AnnaBridge 171:3a7713b1edbc 1290 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
AnnaBridge 171:3a7713b1edbc 1291 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
AnnaBridge 171:3a7713b1edbc 1292
AnnaBridge 171:3a7713b1edbc 1293 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
AnnaBridge 171:3a7713b1edbc 1294 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
AnnaBridge 171:3a7713b1edbc 1295
AnnaBridge 171:3a7713b1edbc 1296 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
AnnaBridge 171:3a7713b1edbc 1297 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
AnnaBridge 171:3a7713b1edbc 1298
AnnaBridge 171:3a7713b1edbc 1299 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
AnnaBridge 171:3a7713b1edbc 1300 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
AnnaBridge 171:3a7713b1edbc 1301
AnnaBridge 171:3a7713b1edbc 1302 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
AnnaBridge 171:3a7713b1edbc 1303 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
AnnaBridge 171:3a7713b1edbc 1304
AnnaBridge 171:3a7713b1edbc 1305 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
AnnaBridge 171:3a7713b1edbc 1306 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
AnnaBridge 171:3a7713b1edbc 1307
AnnaBridge 171:3a7713b1edbc 1308 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
AnnaBridge 171:3a7713b1edbc 1309 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
AnnaBridge 171:3a7713b1edbc 1310
AnnaBridge 171:3a7713b1edbc 1311 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
AnnaBridge 171:3a7713b1edbc 1312 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
AnnaBridge 171:3a7713b1edbc 1313
AnnaBridge 171:3a7713b1edbc 1314 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
AnnaBridge 171:3a7713b1edbc 1315 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
AnnaBridge 171:3a7713b1edbc 1316
AnnaBridge 171:3a7713b1edbc 1317 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
AnnaBridge 171:3a7713b1edbc 1318 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
AnnaBridge 171:3a7713b1edbc 1319
AnnaBridge 171:3a7713b1edbc 1320 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
AnnaBridge 171:3a7713b1edbc 1321 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
AnnaBridge 171:3a7713b1edbc 1322
AnnaBridge 171:3a7713b1edbc 1323 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
AnnaBridge 171:3a7713b1edbc 1324 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
AnnaBridge 171:3a7713b1edbc 1325
AnnaBridge 171:3a7713b1edbc 1326 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
AnnaBridge 171:3a7713b1edbc 1327 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
AnnaBridge 171:3a7713b1edbc 1328
AnnaBridge 171:3a7713b1edbc 1329 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
AnnaBridge 171:3a7713b1edbc 1330 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
AnnaBridge 171:3a7713b1edbc 1331
AnnaBridge 171:3a7713b1edbc 1332 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
AnnaBridge 171:3a7713b1edbc 1333 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
AnnaBridge 171:3a7713b1edbc 1334
AnnaBridge 171:3a7713b1edbc 1335 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
AnnaBridge 171:3a7713b1edbc 1336 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
AnnaBridge 171:3a7713b1edbc 1337
AnnaBridge 171:3a7713b1edbc 1338 /* DWT CPI Count Register Definitions */
AnnaBridge 171:3a7713b1edbc 1339 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
AnnaBridge 171:3a7713b1edbc 1340 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
AnnaBridge 171:3a7713b1edbc 1341
AnnaBridge 171:3a7713b1edbc 1342 /* DWT Exception Overhead Count Register Definitions */
AnnaBridge 171:3a7713b1edbc 1343 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
AnnaBridge 171:3a7713b1edbc 1344 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
AnnaBridge 171:3a7713b1edbc 1345
AnnaBridge 171:3a7713b1edbc 1346 /* DWT Sleep Count Register Definitions */
AnnaBridge 171:3a7713b1edbc 1347 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
AnnaBridge 171:3a7713b1edbc 1348 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
AnnaBridge 171:3a7713b1edbc 1349
AnnaBridge 171:3a7713b1edbc 1350 /* DWT LSU Count Register Definitions */
AnnaBridge 171:3a7713b1edbc 1351 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
AnnaBridge 171:3a7713b1edbc 1352 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
AnnaBridge 171:3a7713b1edbc 1353
AnnaBridge 171:3a7713b1edbc 1354 /* DWT Folded-instruction Count Register Definitions */
AnnaBridge 171:3a7713b1edbc 1355 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
AnnaBridge 171:3a7713b1edbc 1356 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
AnnaBridge 171:3a7713b1edbc 1357
AnnaBridge 171:3a7713b1edbc 1358 /* DWT Comparator Function Register Definitions */
AnnaBridge 171:3a7713b1edbc 1359 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
AnnaBridge 171:3a7713b1edbc 1360 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
AnnaBridge 171:3a7713b1edbc 1361
AnnaBridge 171:3a7713b1edbc 1362 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
AnnaBridge 171:3a7713b1edbc 1363 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
AnnaBridge 171:3a7713b1edbc 1364
AnnaBridge 171:3a7713b1edbc 1365 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
AnnaBridge 171:3a7713b1edbc 1366 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
AnnaBridge 171:3a7713b1edbc 1367
AnnaBridge 171:3a7713b1edbc 1368 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
AnnaBridge 171:3a7713b1edbc 1369 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
AnnaBridge 171:3a7713b1edbc 1370
AnnaBridge 171:3a7713b1edbc 1371 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
AnnaBridge 171:3a7713b1edbc 1372 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
AnnaBridge 171:3a7713b1edbc 1373
AnnaBridge 171:3a7713b1edbc 1374 /*@}*/ /* end of group CMSIS_DWT */
AnnaBridge 171:3a7713b1edbc 1375
AnnaBridge 171:3a7713b1edbc 1376
AnnaBridge 171:3a7713b1edbc 1377 /**
AnnaBridge 171:3a7713b1edbc 1378 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1379 \defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge 171:3a7713b1edbc 1380 \brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge 171:3a7713b1edbc 1381 @{
AnnaBridge 171:3a7713b1edbc 1382 */
AnnaBridge 171:3a7713b1edbc 1383
AnnaBridge 171:3a7713b1edbc 1384 /**
AnnaBridge 171:3a7713b1edbc 1385 \brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge 171:3a7713b1edbc 1386 */
AnnaBridge 171:3a7713b1edbc 1387 typedef struct
AnnaBridge 171:3a7713b1edbc 1388 {
AnnaBridge 171:3a7713b1edbc 1389 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
AnnaBridge 171:3a7713b1edbc 1390 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
AnnaBridge 171:3a7713b1edbc 1391 uint32_t RESERVED0[2U];
AnnaBridge 171:3a7713b1edbc 1392 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
AnnaBridge 171:3a7713b1edbc 1393 uint32_t RESERVED1[55U];
AnnaBridge 171:3a7713b1edbc 1394 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
AnnaBridge 171:3a7713b1edbc 1395 uint32_t RESERVED2[131U];
AnnaBridge 171:3a7713b1edbc 1396 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
AnnaBridge 171:3a7713b1edbc 1397 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
AnnaBridge 171:3a7713b1edbc 1398 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
AnnaBridge 171:3a7713b1edbc 1399 uint32_t RESERVED3[759U];
AnnaBridge 171:3a7713b1edbc 1400 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
AnnaBridge 171:3a7713b1edbc 1401 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
AnnaBridge 171:3a7713b1edbc 1402 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
AnnaBridge 171:3a7713b1edbc 1403 uint32_t RESERVED4[1U];
AnnaBridge 171:3a7713b1edbc 1404 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
AnnaBridge 171:3a7713b1edbc 1405 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
AnnaBridge 171:3a7713b1edbc 1406 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
AnnaBridge 171:3a7713b1edbc 1407 uint32_t RESERVED5[39U];
AnnaBridge 171:3a7713b1edbc 1408 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
AnnaBridge 171:3a7713b1edbc 1409 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
AnnaBridge 171:3a7713b1edbc 1410 uint32_t RESERVED7[8U];
AnnaBridge 171:3a7713b1edbc 1411 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
AnnaBridge 171:3a7713b1edbc 1412 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
AnnaBridge 171:3a7713b1edbc 1413 } TPI_Type;
AnnaBridge 171:3a7713b1edbc 1414
AnnaBridge 171:3a7713b1edbc 1415 /* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge 171:3a7713b1edbc 1416 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
AnnaBridge 171:3a7713b1edbc 1417 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
AnnaBridge 171:3a7713b1edbc 1418
AnnaBridge 171:3a7713b1edbc 1419 /* TPI Selected Pin Protocol Register Definitions */
AnnaBridge 171:3a7713b1edbc 1420 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
AnnaBridge 171:3a7713b1edbc 1421 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
AnnaBridge 171:3a7713b1edbc 1422
AnnaBridge 171:3a7713b1edbc 1423 /* TPI Formatter and Flush Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 1424 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
AnnaBridge 171:3a7713b1edbc 1425 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
AnnaBridge 171:3a7713b1edbc 1426
AnnaBridge 171:3a7713b1edbc 1427 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
AnnaBridge 171:3a7713b1edbc 1428 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
AnnaBridge 171:3a7713b1edbc 1429
AnnaBridge 171:3a7713b1edbc 1430 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
AnnaBridge 171:3a7713b1edbc 1431 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
AnnaBridge 171:3a7713b1edbc 1432
AnnaBridge 171:3a7713b1edbc 1433 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
AnnaBridge 171:3a7713b1edbc 1434 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
AnnaBridge 171:3a7713b1edbc 1435
AnnaBridge 171:3a7713b1edbc 1436 /* TPI Formatter and Flush Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1437 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
AnnaBridge 171:3a7713b1edbc 1438 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
AnnaBridge 171:3a7713b1edbc 1439
AnnaBridge 171:3a7713b1edbc 1440 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
AnnaBridge 171:3a7713b1edbc 1441 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
AnnaBridge 171:3a7713b1edbc 1442
AnnaBridge 171:3a7713b1edbc 1443 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
AnnaBridge 171:3a7713b1edbc 1444 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
AnnaBridge 171:3a7713b1edbc 1445
AnnaBridge 171:3a7713b1edbc 1446 /* TPI TRIGGER Register Definitions */
AnnaBridge 171:3a7713b1edbc 1447 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
AnnaBridge 171:3a7713b1edbc 1448 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
AnnaBridge 171:3a7713b1edbc 1449
AnnaBridge 171:3a7713b1edbc 1450 /* TPI Integration Test FIFO Test Data 0 Register Definitions */
AnnaBridge 171:3a7713b1edbc 1451 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
AnnaBridge 171:3a7713b1edbc 1452 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
AnnaBridge 171:3a7713b1edbc 1453
AnnaBridge 171:3a7713b1edbc 1454 #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
AnnaBridge 171:3a7713b1edbc 1455 #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
AnnaBridge 171:3a7713b1edbc 1456
AnnaBridge 171:3a7713b1edbc 1457 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
AnnaBridge 171:3a7713b1edbc 1458 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
AnnaBridge 171:3a7713b1edbc 1459
AnnaBridge 171:3a7713b1edbc 1460 #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
AnnaBridge 171:3a7713b1edbc 1461 #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
AnnaBridge 171:3a7713b1edbc 1462
AnnaBridge 171:3a7713b1edbc 1463 #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
AnnaBridge 171:3a7713b1edbc 1464 #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
AnnaBridge 171:3a7713b1edbc 1465
AnnaBridge 171:3a7713b1edbc 1466 #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
AnnaBridge 171:3a7713b1edbc 1467 #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
AnnaBridge 171:3a7713b1edbc 1468
AnnaBridge 171:3a7713b1edbc 1469 #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
AnnaBridge 171:3a7713b1edbc 1470 #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
AnnaBridge 171:3a7713b1edbc 1471
AnnaBridge 171:3a7713b1edbc 1472 /* TPI Integration Test ATB Control Register 2 Register Definitions */
AnnaBridge 171:3a7713b1edbc 1473 #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
AnnaBridge 171:3a7713b1edbc 1474 #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
AnnaBridge 171:3a7713b1edbc 1475
AnnaBridge 171:3a7713b1edbc 1476 #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
AnnaBridge 171:3a7713b1edbc 1477 #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
AnnaBridge 171:3a7713b1edbc 1478
AnnaBridge 171:3a7713b1edbc 1479 #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
AnnaBridge 171:3a7713b1edbc 1480 #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
AnnaBridge 171:3a7713b1edbc 1481
AnnaBridge 171:3a7713b1edbc 1482 #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
AnnaBridge 171:3a7713b1edbc 1483 #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
AnnaBridge 171:3a7713b1edbc 1484
AnnaBridge 171:3a7713b1edbc 1485 /* TPI Integration Test FIFO Test Data 1 Register Definitions */
AnnaBridge 171:3a7713b1edbc 1486 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
AnnaBridge 171:3a7713b1edbc 1487 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
AnnaBridge 171:3a7713b1edbc 1488
AnnaBridge 171:3a7713b1edbc 1489 #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
AnnaBridge 171:3a7713b1edbc 1490 #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
AnnaBridge 171:3a7713b1edbc 1491
AnnaBridge 171:3a7713b1edbc 1492 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
AnnaBridge 171:3a7713b1edbc 1493 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
AnnaBridge 171:3a7713b1edbc 1494
AnnaBridge 171:3a7713b1edbc 1495 #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
AnnaBridge 171:3a7713b1edbc 1496 #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
AnnaBridge 171:3a7713b1edbc 1497
AnnaBridge 171:3a7713b1edbc 1498 #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
AnnaBridge 171:3a7713b1edbc 1499 #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
AnnaBridge 171:3a7713b1edbc 1500
AnnaBridge 171:3a7713b1edbc 1501 #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
AnnaBridge 171:3a7713b1edbc 1502 #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
AnnaBridge 171:3a7713b1edbc 1503
AnnaBridge 171:3a7713b1edbc 1504 #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
AnnaBridge 171:3a7713b1edbc 1505 #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
AnnaBridge 171:3a7713b1edbc 1506
AnnaBridge 171:3a7713b1edbc 1507 /* TPI Integration Test ATB Control Register 0 Definitions */
AnnaBridge 171:3a7713b1edbc 1508 #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
AnnaBridge 171:3a7713b1edbc 1509 #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
AnnaBridge 171:3a7713b1edbc 1510
AnnaBridge 171:3a7713b1edbc 1511 #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
AnnaBridge 171:3a7713b1edbc 1512 #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
AnnaBridge 171:3a7713b1edbc 1513
AnnaBridge 171:3a7713b1edbc 1514 #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
AnnaBridge 171:3a7713b1edbc 1515 #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
AnnaBridge 171:3a7713b1edbc 1516
AnnaBridge 171:3a7713b1edbc 1517 #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
AnnaBridge 171:3a7713b1edbc 1518 #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
AnnaBridge 171:3a7713b1edbc 1519
AnnaBridge 171:3a7713b1edbc 1520 /* TPI Integration Mode Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1521 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
AnnaBridge 171:3a7713b1edbc 1522 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
AnnaBridge 171:3a7713b1edbc 1523
AnnaBridge 171:3a7713b1edbc 1524 /* TPI DEVID Register Definitions */
AnnaBridge 171:3a7713b1edbc 1525 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
AnnaBridge 171:3a7713b1edbc 1526 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
AnnaBridge 171:3a7713b1edbc 1527
AnnaBridge 171:3a7713b1edbc 1528 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
AnnaBridge 171:3a7713b1edbc 1529 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
AnnaBridge 171:3a7713b1edbc 1530
AnnaBridge 171:3a7713b1edbc 1531 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
AnnaBridge 171:3a7713b1edbc 1532 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
AnnaBridge 171:3a7713b1edbc 1533
AnnaBridge 171:3a7713b1edbc 1534 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
AnnaBridge 171:3a7713b1edbc 1535 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
AnnaBridge 171:3a7713b1edbc 1536
AnnaBridge 171:3a7713b1edbc 1537 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
AnnaBridge 171:3a7713b1edbc 1538 #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
AnnaBridge 171:3a7713b1edbc 1539
AnnaBridge 171:3a7713b1edbc 1540 /* TPI DEVTYPE Register Definitions */
AnnaBridge 171:3a7713b1edbc 1541 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
AnnaBridge 171:3a7713b1edbc 1542 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
AnnaBridge 171:3a7713b1edbc 1543
AnnaBridge 171:3a7713b1edbc 1544 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
AnnaBridge 171:3a7713b1edbc 1545 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
AnnaBridge 171:3a7713b1edbc 1546
AnnaBridge 171:3a7713b1edbc 1547 /*@}*/ /* end of group CMSIS_TPI */
AnnaBridge 171:3a7713b1edbc 1548
AnnaBridge 171:3a7713b1edbc 1549
AnnaBridge 171:3a7713b1edbc 1550 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 1551 /**
AnnaBridge 171:3a7713b1edbc 1552 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1553 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 171:3a7713b1edbc 1554 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 171:3a7713b1edbc 1555 @{
AnnaBridge 171:3a7713b1edbc 1556 */
AnnaBridge 171:3a7713b1edbc 1557
AnnaBridge 171:3a7713b1edbc 1558 /**
AnnaBridge 171:3a7713b1edbc 1559 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 171:3a7713b1edbc 1560 */
AnnaBridge 171:3a7713b1edbc 1561 typedef struct
AnnaBridge 171:3a7713b1edbc 1562 {
AnnaBridge 171:3a7713b1edbc 1563 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 171:3a7713b1edbc 1564 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 171:3a7713b1edbc 1565 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
AnnaBridge 171:3a7713b1edbc 1566 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 171:3a7713b1edbc 1567 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
AnnaBridge 171:3a7713b1edbc 1568 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
AnnaBridge 171:3a7713b1edbc 1569 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
AnnaBridge 171:3a7713b1edbc 1570 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
AnnaBridge 171:3a7713b1edbc 1571 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
AnnaBridge 171:3a7713b1edbc 1572 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
AnnaBridge 171:3a7713b1edbc 1573 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
AnnaBridge 171:3a7713b1edbc 1574 uint32_t RESERVED0[1];
AnnaBridge 171:3a7713b1edbc 1575 union {
AnnaBridge 171:3a7713b1edbc 1576 __IOM uint32_t MAIR[2];
AnnaBridge 171:3a7713b1edbc 1577 struct {
AnnaBridge 171:3a7713b1edbc 1578 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
AnnaBridge 171:3a7713b1edbc 1579 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
AnnaBridge 171:3a7713b1edbc 1580 };
AnnaBridge 171:3a7713b1edbc 1581 };
AnnaBridge 171:3a7713b1edbc 1582 } MPU_Type;
AnnaBridge 171:3a7713b1edbc 1583
AnnaBridge 171:3a7713b1edbc 1584 #define MPU_TYPE_RALIASES 4U
AnnaBridge 171:3a7713b1edbc 1585
AnnaBridge 171:3a7713b1edbc 1586 /* MPU Type Register Definitions */
AnnaBridge 171:3a7713b1edbc 1587 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 171:3a7713b1edbc 1588 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 171:3a7713b1edbc 1589
AnnaBridge 171:3a7713b1edbc 1590 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 171:3a7713b1edbc 1591 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 171:3a7713b1edbc 1592
AnnaBridge 171:3a7713b1edbc 1593 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 171:3a7713b1edbc 1594 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 171:3a7713b1edbc 1595
AnnaBridge 171:3a7713b1edbc 1596 /* MPU Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1597 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 171:3a7713b1edbc 1598 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 171:3a7713b1edbc 1599
AnnaBridge 171:3a7713b1edbc 1600 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 171:3a7713b1edbc 1601 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 171:3a7713b1edbc 1602
AnnaBridge 171:3a7713b1edbc 1603 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 171:3a7713b1edbc 1604 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 1605
AnnaBridge 171:3a7713b1edbc 1606 /* MPU Region Number Register Definitions */
AnnaBridge 171:3a7713b1edbc 1607 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 171:3a7713b1edbc 1608 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 171:3a7713b1edbc 1609
AnnaBridge 171:3a7713b1edbc 1610 /* MPU Region Base Address Register Definitions */
AnnaBridge 171:3a7713b1edbc 1611 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
AnnaBridge 171:3a7713b1edbc 1612 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
AnnaBridge 171:3a7713b1edbc 1613
AnnaBridge 171:3a7713b1edbc 1614 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
AnnaBridge 171:3a7713b1edbc 1615 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
AnnaBridge 171:3a7713b1edbc 1616
AnnaBridge 171:3a7713b1edbc 1617 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
AnnaBridge 171:3a7713b1edbc 1618 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
AnnaBridge 171:3a7713b1edbc 1619
AnnaBridge 171:3a7713b1edbc 1620 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
AnnaBridge 171:3a7713b1edbc 1621 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
AnnaBridge 171:3a7713b1edbc 1622
AnnaBridge 171:3a7713b1edbc 1623 /* MPU Region Limit Address Register Definitions */
AnnaBridge 171:3a7713b1edbc 1624 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
AnnaBridge 171:3a7713b1edbc 1625 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
AnnaBridge 171:3a7713b1edbc 1626
AnnaBridge 171:3a7713b1edbc 1627 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
AnnaBridge 171:3a7713b1edbc 1628 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
AnnaBridge 171:3a7713b1edbc 1629
AnnaBridge 171:3a7713b1edbc 1630 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
AnnaBridge 171:3a7713b1edbc 1631 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
AnnaBridge 171:3a7713b1edbc 1632
AnnaBridge 171:3a7713b1edbc 1633 /* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge 171:3a7713b1edbc 1634 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
AnnaBridge 171:3a7713b1edbc 1635 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
AnnaBridge 171:3a7713b1edbc 1636
AnnaBridge 171:3a7713b1edbc 1637 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
AnnaBridge 171:3a7713b1edbc 1638 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
AnnaBridge 171:3a7713b1edbc 1639
AnnaBridge 171:3a7713b1edbc 1640 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
AnnaBridge 171:3a7713b1edbc 1641 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
AnnaBridge 171:3a7713b1edbc 1642
AnnaBridge 171:3a7713b1edbc 1643 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
AnnaBridge 171:3a7713b1edbc 1644 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
AnnaBridge 171:3a7713b1edbc 1645
AnnaBridge 171:3a7713b1edbc 1646 /* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge 171:3a7713b1edbc 1647 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
AnnaBridge 171:3a7713b1edbc 1648 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
AnnaBridge 171:3a7713b1edbc 1649
AnnaBridge 171:3a7713b1edbc 1650 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
AnnaBridge 171:3a7713b1edbc 1651 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
AnnaBridge 171:3a7713b1edbc 1652
AnnaBridge 171:3a7713b1edbc 1653 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
AnnaBridge 171:3a7713b1edbc 1654 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
AnnaBridge 171:3a7713b1edbc 1655
AnnaBridge 171:3a7713b1edbc 1656 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
AnnaBridge 171:3a7713b1edbc 1657 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
AnnaBridge 171:3a7713b1edbc 1658
AnnaBridge 171:3a7713b1edbc 1659 /*@} end of group CMSIS_MPU */
AnnaBridge 171:3a7713b1edbc 1660 #endif
AnnaBridge 171:3a7713b1edbc 1661
AnnaBridge 171:3a7713b1edbc 1662
AnnaBridge 171:3a7713b1edbc 1663 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 171:3a7713b1edbc 1664 /**
AnnaBridge 171:3a7713b1edbc 1665 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1666 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge 171:3a7713b1edbc 1667 \brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge 171:3a7713b1edbc 1668 @{
AnnaBridge 171:3a7713b1edbc 1669 */
AnnaBridge 171:3a7713b1edbc 1670
AnnaBridge 171:3a7713b1edbc 1671 /**
AnnaBridge 171:3a7713b1edbc 1672 \brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge 171:3a7713b1edbc 1673 */
AnnaBridge 171:3a7713b1edbc 1674 typedef struct
AnnaBridge 171:3a7713b1edbc 1675 {
AnnaBridge 171:3a7713b1edbc 1676 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
AnnaBridge 171:3a7713b1edbc 1677 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
AnnaBridge 171:3a7713b1edbc 1678 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 1679 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
AnnaBridge 171:3a7713b1edbc 1680 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
AnnaBridge 171:3a7713b1edbc 1681 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
AnnaBridge 171:3a7713b1edbc 1682 #else
AnnaBridge 171:3a7713b1edbc 1683 uint32_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 1684 #endif
AnnaBridge 171:3a7713b1edbc 1685 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
AnnaBridge 171:3a7713b1edbc 1686 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
AnnaBridge 171:3a7713b1edbc 1687 } SAU_Type;
AnnaBridge 171:3a7713b1edbc 1688
AnnaBridge 171:3a7713b1edbc 1689 /* SAU Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1690 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
AnnaBridge 171:3a7713b1edbc 1691 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
AnnaBridge 171:3a7713b1edbc 1692
AnnaBridge 171:3a7713b1edbc 1693 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
AnnaBridge 171:3a7713b1edbc 1694 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 1695
AnnaBridge 171:3a7713b1edbc 1696 /* SAU Type Register Definitions */
AnnaBridge 171:3a7713b1edbc 1697 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
AnnaBridge 171:3a7713b1edbc 1698 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
AnnaBridge 171:3a7713b1edbc 1699
AnnaBridge 171:3a7713b1edbc 1700 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 1701 /* SAU Region Number Register Definitions */
AnnaBridge 171:3a7713b1edbc 1702 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
AnnaBridge 171:3a7713b1edbc 1703 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
AnnaBridge 171:3a7713b1edbc 1704
AnnaBridge 171:3a7713b1edbc 1705 /* SAU Region Base Address Register Definitions */
AnnaBridge 171:3a7713b1edbc 1706 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
AnnaBridge 171:3a7713b1edbc 1707 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
AnnaBridge 171:3a7713b1edbc 1708
AnnaBridge 171:3a7713b1edbc 1709 /* SAU Region Limit Address Register Definitions */
AnnaBridge 171:3a7713b1edbc 1710 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
AnnaBridge 171:3a7713b1edbc 1711 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
AnnaBridge 171:3a7713b1edbc 1712
AnnaBridge 171:3a7713b1edbc 1713 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
AnnaBridge 171:3a7713b1edbc 1714 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
AnnaBridge 171:3a7713b1edbc 1715
AnnaBridge 171:3a7713b1edbc 1716 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
AnnaBridge 171:3a7713b1edbc 1717 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
AnnaBridge 171:3a7713b1edbc 1718
AnnaBridge 171:3a7713b1edbc 1719 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge 171:3a7713b1edbc 1720
AnnaBridge 171:3a7713b1edbc 1721 /* Secure Fault Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 1722 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
AnnaBridge 171:3a7713b1edbc 1723 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
AnnaBridge 171:3a7713b1edbc 1724
AnnaBridge 171:3a7713b1edbc 1725 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
AnnaBridge 171:3a7713b1edbc 1726 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
AnnaBridge 171:3a7713b1edbc 1727
AnnaBridge 171:3a7713b1edbc 1728 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
AnnaBridge 171:3a7713b1edbc 1729 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
AnnaBridge 171:3a7713b1edbc 1730
AnnaBridge 171:3a7713b1edbc 1731 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
AnnaBridge 171:3a7713b1edbc 1732 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
AnnaBridge 171:3a7713b1edbc 1733
AnnaBridge 171:3a7713b1edbc 1734 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
AnnaBridge 171:3a7713b1edbc 1735 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
AnnaBridge 171:3a7713b1edbc 1736
AnnaBridge 171:3a7713b1edbc 1737 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
AnnaBridge 171:3a7713b1edbc 1738 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
AnnaBridge 171:3a7713b1edbc 1739
AnnaBridge 171:3a7713b1edbc 1740 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
AnnaBridge 171:3a7713b1edbc 1741 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
AnnaBridge 171:3a7713b1edbc 1742
AnnaBridge 171:3a7713b1edbc 1743 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
AnnaBridge 171:3a7713b1edbc 1744 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
AnnaBridge 171:3a7713b1edbc 1745
AnnaBridge 171:3a7713b1edbc 1746 /*@} end of group CMSIS_SAU */
AnnaBridge 171:3a7713b1edbc 1747 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 171:3a7713b1edbc 1748
AnnaBridge 171:3a7713b1edbc 1749
AnnaBridge 171:3a7713b1edbc 1750 /**
AnnaBridge 171:3a7713b1edbc 1751 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1752 \defgroup CMSIS_FPU Floating Point Unit (FPU)
AnnaBridge 171:3a7713b1edbc 1753 \brief Type definitions for the Floating Point Unit (FPU)
AnnaBridge 171:3a7713b1edbc 1754 @{
AnnaBridge 171:3a7713b1edbc 1755 */
AnnaBridge 171:3a7713b1edbc 1756
AnnaBridge 171:3a7713b1edbc 1757 /**
AnnaBridge 171:3a7713b1edbc 1758 \brief Structure type to access the Floating Point Unit (FPU).
AnnaBridge 171:3a7713b1edbc 1759 */
AnnaBridge 171:3a7713b1edbc 1760 typedef struct
AnnaBridge 171:3a7713b1edbc 1761 {
AnnaBridge 171:3a7713b1edbc 1762 uint32_t RESERVED0[1U];
AnnaBridge 171:3a7713b1edbc 1763 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
AnnaBridge 171:3a7713b1edbc 1764 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
AnnaBridge 171:3a7713b1edbc 1765 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
AnnaBridge 171:3a7713b1edbc 1766 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
AnnaBridge 171:3a7713b1edbc 1767 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
AnnaBridge 171:3a7713b1edbc 1768 } FPU_Type;
AnnaBridge 171:3a7713b1edbc 1769
AnnaBridge 171:3a7713b1edbc 1770 /* Floating-Point Context Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1771 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
AnnaBridge 171:3a7713b1edbc 1772 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
AnnaBridge 171:3a7713b1edbc 1773
AnnaBridge 171:3a7713b1edbc 1774 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
AnnaBridge 171:3a7713b1edbc 1775 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
AnnaBridge 171:3a7713b1edbc 1776
AnnaBridge 171:3a7713b1edbc 1777 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
AnnaBridge 171:3a7713b1edbc 1778 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
AnnaBridge 171:3a7713b1edbc 1779
AnnaBridge 171:3a7713b1edbc 1780 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
AnnaBridge 171:3a7713b1edbc 1781 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
AnnaBridge 171:3a7713b1edbc 1782
AnnaBridge 171:3a7713b1edbc 1783 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
AnnaBridge 171:3a7713b1edbc 1784 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
AnnaBridge 171:3a7713b1edbc 1785
AnnaBridge 171:3a7713b1edbc 1786 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
AnnaBridge 171:3a7713b1edbc 1787 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
AnnaBridge 171:3a7713b1edbc 1788
AnnaBridge 171:3a7713b1edbc 1789 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
AnnaBridge 171:3a7713b1edbc 1790 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
AnnaBridge 171:3a7713b1edbc 1791
AnnaBridge 171:3a7713b1edbc 1792 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
AnnaBridge 171:3a7713b1edbc 1793 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
AnnaBridge 171:3a7713b1edbc 1794
AnnaBridge 171:3a7713b1edbc 1795 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
AnnaBridge 171:3a7713b1edbc 1796 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
AnnaBridge 171:3a7713b1edbc 1797
AnnaBridge 171:3a7713b1edbc 1798 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
AnnaBridge 171:3a7713b1edbc 1799 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
AnnaBridge 171:3a7713b1edbc 1800
AnnaBridge 171:3a7713b1edbc 1801 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
AnnaBridge 171:3a7713b1edbc 1802 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
AnnaBridge 171:3a7713b1edbc 1803
AnnaBridge 171:3a7713b1edbc 1804 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
AnnaBridge 171:3a7713b1edbc 1805 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
AnnaBridge 171:3a7713b1edbc 1806
AnnaBridge 171:3a7713b1edbc 1807 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
AnnaBridge 171:3a7713b1edbc 1808 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
AnnaBridge 171:3a7713b1edbc 1809
AnnaBridge 171:3a7713b1edbc 1810 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
AnnaBridge 171:3a7713b1edbc 1811 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
AnnaBridge 171:3a7713b1edbc 1812
AnnaBridge 171:3a7713b1edbc 1813 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
AnnaBridge 171:3a7713b1edbc 1814 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
AnnaBridge 171:3a7713b1edbc 1815
AnnaBridge 171:3a7713b1edbc 1816 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
AnnaBridge 171:3a7713b1edbc 1817 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
AnnaBridge 171:3a7713b1edbc 1818
AnnaBridge 171:3a7713b1edbc 1819 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
AnnaBridge 171:3a7713b1edbc 1820 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
AnnaBridge 171:3a7713b1edbc 1821
AnnaBridge 171:3a7713b1edbc 1822 /* Floating-Point Context Address Register Definitions */
AnnaBridge 171:3a7713b1edbc 1823 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
AnnaBridge 171:3a7713b1edbc 1824 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
AnnaBridge 171:3a7713b1edbc 1825
AnnaBridge 171:3a7713b1edbc 1826 /* Floating-Point Default Status Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1827 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
AnnaBridge 171:3a7713b1edbc 1828 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
AnnaBridge 171:3a7713b1edbc 1829
AnnaBridge 171:3a7713b1edbc 1830 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
AnnaBridge 171:3a7713b1edbc 1831 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
AnnaBridge 171:3a7713b1edbc 1832
AnnaBridge 171:3a7713b1edbc 1833 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
AnnaBridge 171:3a7713b1edbc 1834 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
AnnaBridge 171:3a7713b1edbc 1835
AnnaBridge 171:3a7713b1edbc 1836 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
AnnaBridge 171:3a7713b1edbc 1837 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
AnnaBridge 171:3a7713b1edbc 1838
AnnaBridge 171:3a7713b1edbc 1839 /* Media and FP Feature Register 0 Definitions */
AnnaBridge 171:3a7713b1edbc 1840 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
AnnaBridge 171:3a7713b1edbc 1841 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
AnnaBridge 171:3a7713b1edbc 1842
AnnaBridge 171:3a7713b1edbc 1843 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
AnnaBridge 171:3a7713b1edbc 1844 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
AnnaBridge 171:3a7713b1edbc 1845
AnnaBridge 171:3a7713b1edbc 1846 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
AnnaBridge 171:3a7713b1edbc 1847 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
AnnaBridge 171:3a7713b1edbc 1848
AnnaBridge 171:3a7713b1edbc 1849 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
AnnaBridge 171:3a7713b1edbc 1850 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
AnnaBridge 171:3a7713b1edbc 1851
AnnaBridge 171:3a7713b1edbc 1852 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
AnnaBridge 171:3a7713b1edbc 1853 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
AnnaBridge 171:3a7713b1edbc 1854
AnnaBridge 171:3a7713b1edbc 1855 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
AnnaBridge 171:3a7713b1edbc 1856 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
AnnaBridge 171:3a7713b1edbc 1857
AnnaBridge 171:3a7713b1edbc 1858 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
AnnaBridge 171:3a7713b1edbc 1859 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
AnnaBridge 171:3a7713b1edbc 1860
AnnaBridge 171:3a7713b1edbc 1861 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
AnnaBridge 171:3a7713b1edbc 1862 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
AnnaBridge 171:3a7713b1edbc 1863
AnnaBridge 171:3a7713b1edbc 1864 /* Media and FP Feature Register 1 Definitions */
AnnaBridge 171:3a7713b1edbc 1865 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
AnnaBridge 171:3a7713b1edbc 1866 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
AnnaBridge 171:3a7713b1edbc 1867
AnnaBridge 171:3a7713b1edbc 1868 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
AnnaBridge 171:3a7713b1edbc 1869 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
AnnaBridge 171:3a7713b1edbc 1870
AnnaBridge 171:3a7713b1edbc 1871 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
AnnaBridge 171:3a7713b1edbc 1872 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
AnnaBridge 171:3a7713b1edbc 1873
AnnaBridge 171:3a7713b1edbc 1874 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
AnnaBridge 171:3a7713b1edbc 1875 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
AnnaBridge 171:3a7713b1edbc 1876
AnnaBridge 171:3a7713b1edbc 1877 /*@} end of group CMSIS_FPU */
AnnaBridge 171:3a7713b1edbc 1878
AnnaBridge 171:3a7713b1edbc 1879
AnnaBridge 171:3a7713b1edbc 1880 /**
AnnaBridge 171:3a7713b1edbc 1881 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 1882 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 171:3a7713b1edbc 1883 \brief Type definitions for the Core Debug Registers
AnnaBridge 171:3a7713b1edbc 1884 @{
AnnaBridge 171:3a7713b1edbc 1885 */
AnnaBridge 171:3a7713b1edbc 1886
AnnaBridge 171:3a7713b1edbc 1887 /**
AnnaBridge 171:3a7713b1edbc 1888 \brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge 171:3a7713b1edbc 1889 */
AnnaBridge 171:3a7713b1edbc 1890 typedef struct
AnnaBridge 171:3a7713b1edbc 1891 {
AnnaBridge 171:3a7713b1edbc 1892 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
AnnaBridge 171:3a7713b1edbc 1893 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
AnnaBridge 171:3a7713b1edbc 1894 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
AnnaBridge 171:3a7713b1edbc 1895 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
AnnaBridge 171:3a7713b1edbc 1896 uint32_t RESERVED4[1U];
AnnaBridge 171:3a7713b1edbc 1897 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
AnnaBridge 171:3a7713b1edbc 1898 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
AnnaBridge 171:3a7713b1edbc 1899 } CoreDebug_Type;
AnnaBridge 171:3a7713b1edbc 1900
AnnaBridge 171:3a7713b1edbc 1901 /* Debug Halting Control and Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 1902 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
AnnaBridge 171:3a7713b1edbc 1903 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
AnnaBridge 171:3a7713b1edbc 1904
AnnaBridge 171:3a7713b1edbc 1905 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */
AnnaBridge 171:3a7713b1edbc 1906 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
AnnaBridge 171:3a7713b1edbc 1907
AnnaBridge 171:3a7713b1edbc 1908 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
AnnaBridge 171:3a7713b1edbc 1909 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
AnnaBridge 171:3a7713b1edbc 1910
AnnaBridge 171:3a7713b1edbc 1911 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
AnnaBridge 171:3a7713b1edbc 1912 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
AnnaBridge 171:3a7713b1edbc 1913
AnnaBridge 171:3a7713b1edbc 1914 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
AnnaBridge 171:3a7713b1edbc 1915 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
AnnaBridge 171:3a7713b1edbc 1916
AnnaBridge 171:3a7713b1edbc 1917 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
AnnaBridge 171:3a7713b1edbc 1918 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
AnnaBridge 171:3a7713b1edbc 1919
AnnaBridge 171:3a7713b1edbc 1920 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
AnnaBridge 171:3a7713b1edbc 1921 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
AnnaBridge 171:3a7713b1edbc 1922
AnnaBridge 171:3a7713b1edbc 1923 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
AnnaBridge 171:3a7713b1edbc 1924 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
AnnaBridge 171:3a7713b1edbc 1925
AnnaBridge 171:3a7713b1edbc 1926 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
AnnaBridge 171:3a7713b1edbc 1927 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
AnnaBridge 171:3a7713b1edbc 1928
AnnaBridge 171:3a7713b1edbc 1929 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
AnnaBridge 171:3a7713b1edbc 1930 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
AnnaBridge 171:3a7713b1edbc 1931
AnnaBridge 171:3a7713b1edbc 1932 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
AnnaBridge 171:3a7713b1edbc 1933 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
AnnaBridge 171:3a7713b1edbc 1934
AnnaBridge 171:3a7713b1edbc 1935 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
AnnaBridge 171:3a7713b1edbc 1936 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
AnnaBridge 171:3a7713b1edbc 1937
AnnaBridge 171:3a7713b1edbc 1938 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
AnnaBridge 171:3a7713b1edbc 1939 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
AnnaBridge 171:3a7713b1edbc 1940
AnnaBridge 171:3a7713b1edbc 1941 /* Debug Core Register Selector Register Definitions */
AnnaBridge 171:3a7713b1edbc 1942 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
AnnaBridge 171:3a7713b1edbc 1943 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
AnnaBridge 171:3a7713b1edbc 1944
AnnaBridge 171:3a7713b1edbc 1945 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
AnnaBridge 171:3a7713b1edbc 1946 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
AnnaBridge 171:3a7713b1edbc 1947
AnnaBridge 171:3a7713b1edbc 1948 /* Debug Exception and Monitor Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1949 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
AnnaBridge 171:3a7713b1edbc 1950 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
AnnaBridge 171:3a7713b1edbc 1951
AnnaBridge 171:3a7713b1edbc 1952 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
AnnaBridge 171:3a7713b1edbc 1953 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
AnnaBridge 171:3a7713b1edbc 1954
AnnaBridge 171:3a7713b1edbc 1955 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
AnnaBridge 171:3a7713b1edbc 1956 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
AnnaBridge 171:3a7713b1edbc 1957
AnnaBridge 171:3a7713b1edbc 1958 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
AnnaBridge 171:3a7713b1edbc 1959 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
AnnaBridge 171:3a7713b1edbc 1960
AnnaBridge 171:3a7713b1edbc 1961 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
AnnaBridge 171:3a7713b1edbc 1962 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
AnnaBridge 171:3a7713b1edbc 1963
AnnaBridge 171:3a7713b1edbc 1964 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
AnnaBridge 171:3a7713b1edbc 1965 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
AnnaBridge 171:3a7713b1edbc 1966
AnnaBridge 171:3a7713b1edbc 1967 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
AnnaBridge 171:3a7713b1edbc 1968 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
AnnaBridge 171:3a7713b1edbc 1969
AnnaBridge 171:3a7713b1edbc 1970 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
AnnaBridge 171:3a7713b1edbc 1971 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
AnnaBridge 171:3a7713b1edbc 1972
AnnaBridge 171:3a7713b1edbc 1973 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
AnnaBridge 171:3a7713b1edbc 1974 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
AnnaBridge 171:3a7713b1edbc 1975
AnnaBridge 171:3a7713b1edbc 1976 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
AnnaBridge 171:3a7713b1edbc 1977 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
AnnaBridge 171:3a7713b1edbc 1978
AnnaBridge 171:3a7713b1edbc 1979 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
AnnaBridge 171:3a7713b1edbc 1980 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
AnnaBridge 171:3a7713b1edbc 1981
AnnaBridge 171:3a7713b1edbc 1982 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
AnnaBridge 171:3a7713b1edbc 1983 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
AnnaBridge 171:3a7713b1edbc 1984
AnnaBridge 171:3a7713b1edbc 1985 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
AnnaBridge 171:3a7713b1edbc 1986 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
AnnaBridge 171:3a7713b1edbc 1987
AnnaBridge 171:3a7713b1edbc 1988 /* Debug Authentication Control Register Definitions */
AnnaBridge 171:3a7713b1edbc 1989 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
AnnaBridge 171:3a7713b1edbc 1990 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
AnnaBridge 171:3a7713b1edbc 1991
AnnaBridge 171:3a7713b1edbc 1992 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
AnnaBridge 171:3a7713b1edbc 1993 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
AnnaBridge 171:3a7713b1edbc 1994
AnnaBridge 171:3a7713b1edbc 1995 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
AnnaBridge 171:3a7713b1edbc 1996 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
AnnaBridge 171:3a7713b1edbc 1997
AnnaBridge 171:3a7713b1edbc 1998 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
AnnaBridge 171:3a7713b1edbc 1999 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
AnnaBridge 171:3a7713b1edbc 2000
AnnaBridge 171:3a7713b1edbc 2001 /* Debug Security Control and Status Register Definitions */
AnnaBridge 171:3a7713b1edbc 2002 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */
AnnaBridge 171:3a7713b1edbc 2003 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */
AnnaBridge 171:3a7713b1edbc 2004
AnnaBridge 171:3a7713b1edbc 2005 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */
AnnaBridge 171:3a7713b1edbc 2006 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */
AnnaBridge 171:3a7713b1edbc 2007
AnnaBridge 171:3a7713b1edbc 2008 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */
AnnaBridge 171:3a7713b1edbc 2009 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */
AnnaBridge 171:3a7713b1edbc 2010
AnnaBridge 171:3a7713b1edbc 2011 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 171:3a7713b1edbc 2012
AnnaBridge 171:3a7713b1edbc 2013
AnnaBridge 171:3a7713b1edbc 2014 /**
AnnaBridge 171:3a7713b1edbc 2015 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 2016 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 171:3a7713b1edbc 2017 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 171:3a7713b1edbc 2018 @{
AnnaBridge 171:3a7713b1edbc 2019 */
AnnaBridge 171:3a7713b1edbc 2020
AnnaBridge 171:3a7713b1edbc 2021 /**
AnnaBridge 171:3a7713b1edbc 2022 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 171:3a7713b1edbc 2023 \param[in] field Name of the register bit field.
AnnaBridge 171:3a7713b1edbc 2024 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 171:3a7713b1edbc 2025 \return Masked and shifted value.
AnnaBridge 171:3a7713b1edbc 2026 */
AnnaBridge 171:3a7713b1edbc 2027 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 171:3a7713b1edbc 2028
AnnaBridge 171:3a7713b1edbc 2029 /**
AnnaBridge 171:3a7713b1edbc 2030 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 171:3a7713b1edbc 2031 \param[in] field Name of the register bit field.
AnnaBridge 171:3a7713b1edbc 2032 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 171:3a7713b1edbc 2033 \return Masked and shifted bit field value.
AnnaBridge 171:3a7713b1edbc 2034 */
AnnaBridge 171:3a7713b1edbc 2035 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 171:3a7713b1edbc 2036
AnnaBridge 171:3a7713b1edbc 2037 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 171:3a7713b1edbc 2038
AnnaBridge 171:3a7713b1edbc 2039
AnnaBridge 171:3a7713b1edbc 2040 /**
AnnaBridge 171:3a7713b1edbc 2041 \ingroup CMSIS_core_register
AnnaBridge 171:3a7713b1edbc 2042 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 171:3a7713b1edbc 2043 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 171:3a7713b1edbc 2044 @{
AnnaBridge 171:3a7713b1edbc 2045 */
AnnaBridge 171:3a7713b1edbc 2046
AnnaBridge 171:3a7713b1edbc 2047 /* Memory mapping of Core Hardware */
AnnaBridge 171:3a7713b1edbc 2048 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 171:3a7713b1edbc 2049 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
AnnaBridge 171:3a7713b1edbc 2050 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
AnnaBridge 171:3a7713b1edbc 2051 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
AnnaBridge 171:3a7713b1edbc 2052 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
AnnaBridge 171:3a7713b1edbc 2053 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 171:3a7713b1edbc 2054 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 171:3a7713b1edbc 2055 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 171:3a7713b1edbc 2056
AnnaBridge 171:3a7713b1edbc 2057 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 171:3a7713b1edbc 2058 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 171:3a7713b1edbc 2059 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 171:3a7713b1edbc 2060 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 171:3a7713b1edbc 2061 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
AnnaBridge 171:3a7713b1edbc 2062 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
AnnaBridge 171:3a7713b1edbc 2063 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
AnnaBridge 171:3a7713b1edbc 2064 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */
AnnaBridge 171:3a7713b1edbc 2065
AnnaBridge 171:3a7713b1edbc 2066 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 2067 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 171:3a7713b1edbc 2068 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 171:3a7713b1edbc 2069 #endif
AnnaBridge 171:3a7713b1edbc 2070
AnnaBridge 171:3a7713b1edbc 2071 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 171:3a7713b1edbc 2072 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
AnnaBridge 171:3a7713b1edbc 2073 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
AnnaBridge 171:3a7713b1edbc 2074 #endif
AnnaBridge 171:3a7713b1edbc 2075
AnnaBridge 171:3a7713b1edbc 2076 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
AnnaBridge 171:3a7713b1edbc 2077 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
AnnaBridge 171:3a7713b1edbc 2078
AnnaBridge 171:3a7713b1edbc 2079 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 171:3a7713b1edbc 2080 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2081 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2082 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2083 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2084 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2085
AnnaBridge 171:3a7713b1edbc 2086 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2087 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2088 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2089 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2090 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2091
AnnaBridge 171:3a7713b1edbc 2092 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 2093 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2094 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2095 #endif
AnnaBridge 171:3a7713b1edbc 2096
AnnaBridge 171:3a7713b1edbc 2097 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2098 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
AnnaBridge 171:3a7713b1edbc 2099
AnnaBridge 171:3a7713b1edbc 2100 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 171:3a7713b1edbc 2101 /*@} */
AnnaBridge 171:3a7713b1edbc 2102
AnnaBridge 171:3a7713b1edbc 2103
AnnaBridge 171:3a7713b1edbc 2104
AnnaBridge 171:3a7713b1edbc 2105 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2106 * Hardware Abstraction Layer
AnnaBridge 171:3a7713b1edbc 2107 Core Function Interface contains:
AnnaBridge 171:3a7713b1edbc 2108 - Core NVIC Functions
AnnaBridge 171:3a7713b1edbc 2109 - Core SysTick Functions
AnnaBridge 171:3a7713b1edbc 2110 - Core Debug Functions
AnnaBridge 171:3a7713b1edbc 2111 - Core Register Access Functions
AnnaBridge 171:3a7713b1edbc 2112 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2113 /**
AnnaBridge 171:3a7713b1edbc 2114 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 171:3a7713b1edbc 2115 */
AnnaBridge 171:3a7713b1edbc 2116
AnnaBridge 171:3a7713b1edbc 2117
AnnaBridge 171:3a7713b1edbc 2118
AnnaBridge 171:3a7713b1edbc 2119 /* ########################## NVIC functions #################################### */
AnnaBridge 171:3a7713b1edbc 2120 /**
AnnaBridge 171:3a7713b1edbc 2121 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 2122 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 171:3a7713b1edbc 2123 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 171:3a7713b1edbc 2124 @{
AnnaBridge 171:3a7713b1edbc 2125 */
AnnaBridge 171:3a7713b1edbc 2126
AnnaBridge 171:3a7713b1edbc 2127 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 171:3a7713b1edbc 2128 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 171:3a7713b1edbc 2129 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 171:3a7713b1edbc 2130 #endif
AnnaBridge 171:3a7713b1edbc 2131 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 171:3a7713b1edbc 2132 #else
AnnaBridge 171:3a7713b1edbc 2133 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge 171:3a7713b1edbc 2134 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge 171:3a7713b1edbc 2135 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 171:3a7713b1edbc 2136 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 171:3a7713b1edbc 2137 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 171:3a7713b1edbc 2138 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 171:3a7713b1edbc 2139 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 171:3a7713b1edbc 2140 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 171:3a7713b1edbc 2141 #define NVIC_GetActive __NVIC_GetActive
AnnaBridge 171:3a7713b1edbc 2142 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 171:3a7713b1edbc 2143 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 171:3a7713b1edbc 2144 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 171:3a7713b1edbc 2145 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 171:3a7713b1edbc 2146
AnnaBridge 171:3a7713b1edbc 2147 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 171:3a7713b1edbc 2148 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 171:3a7713b1edbc 2149 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 171:3a7713b1edbc 2150 #endif
AnnaBridge 171:3a7713b1edbc 2151 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 171:3a7713b1edbc 2152 #else
AnnaBridge 171:3a7713b1edbc 2153 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 171:3a7713b1edbc 2154 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 171:3a7713b1edbc 2155 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 171:3a7713b1edbc 2156
AnnaBridge 171:3a7713b1edbc 2157 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 171:3a7713b1edbc 2158
AnnaBridge 171:3a7713b1edbc 2159
AnnaBridge 171:3a7713b1edbc 2160 /* Special LR values for Secure/Non-Secure call handling and exception handling */
AnnaBridge 171:3a7713b1edbc 2161
AnnaBridge 171:3a7713b1edbc 2162 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
AnnaBridge 171:3a7713b1edbc 2163 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
AnnaBridge 171:3a7713b1edbc 2164
AnnaBridge 171:3a7713b1edbc 2165 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
AnnaBridge 171:3a7713b1edbc 2166 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
AnnaBridge 171:3a7713b1edbc 2167 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
AnnaBridge 171:3a7713b1edbc 2168 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
AnnaBridge 171:3a7713b1edbc 2169 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
AnnaBridge 171:3a7713b1edbc 2170 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
AnnaBridge 171:3a7713b1edbc 2171 #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
AnnaBridge 171:3a7713b1edbc 2172 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
AnnaBridge 171:3a7713b1edbc 2173
AnnaBridge 171:3a7713b1edbc 2174 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
AnnaBridge 171:3a7713b1edbc 2175 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
AnnaBridge 171:3a7713b1edbc 2176 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
AnnaBridge 171:3a7713b1edbc 2177 #else
AnnaBridge 171:3a7713b1edbc 2178 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
AnnaBridge 171:3a7713b1edbc 2179 #endif
AnnaBridge 171:3a7713b1edbc 2180
AnnaBridge 171:3a7713b1edbc 2181
AnnaBridge 171:3a7713b1edbc 2182 /**
AnnaBridge 171:3a7713b1edbc 2183 \brief Set Priority Grouping
AnnaBridge 171:3a7713b1edbc 2184 \details Sets the priority grouping field using the required unlock sequence.
AnnaBridge 171:3a7713b1edbc 2185 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge 171:3a7713b1edbc 2186 Only values from 0..7 are used.
AnnaBridge 171:3a7713b1edbc 2187 In case of a conflict between priority grouping and available
AnnaBridge 171:3a7713b1edbc 2188 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 171:3a7713b1edbc 2189 \param [in] PriorityGroup Priority grouping field.
AnnaBridge 171:3a7713b1edbc 2190 */
AnnaBridge 171:3a7713b1edbc 2191 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
AnnaBridge 171:3a7713b1edbc 2192 {
AnnaBridge 171:3a7713b1edbc 2193 uint32_t reg_value;
AnnaBridge 171:3a7713b1edbc 2194 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 171:3a7713b1edbc 2195
AnnaBridge 171:3a7713b1edbc 2196 reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge 171:3a7713b1edbc 2197 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge 171:3a7713b1edbc 2198 reg_value = (reg_value |
AnnaBridge 171:3a7713b1edbc 2199 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 171:3a7713b1edbc 2200 (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */
AnnaBridge 171:3a7713b1edbc 2201 SCB->AIRCR = reg_value;
AnnaBridge 171:3a7713b1edbc 2202 }
AnnaBridge 171:3a7713b1edbc 2203
AnnaBridge 171:3a7713b1edbc 2204
AnnaBridge 171:3a7713b1edbc 2205 /**
AnnaBridge 171:3a7713b1edbc 2206 \brief Get Priority Grouping
AnnaBridge 171:3a7713b1edbc 2207 \details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge 171:3a7713b1edbc 2208 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge 171:3a7713b1edbc 2209 */
AnnaBridge 171:3a7713b1edbc 2210 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
AnnaBridge 171:3a7713b1edbc 2211 {
AnnaBridge 171:3a7713b1edbc 2212 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge 171:3a7713b1edbc 2213 }
AnnaBridge 171:3a7713b1edbc 2214
AnnaBridge 171:3a7713b1edbc 2215
AnnaBridge 171:3a7713b1edbc 2216 /**
AnnaBridge 171:3a7713b1edbc 2217 \brief Enable Interrupt
AnnaBridge 171:3a7713b1edbc 2218 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 171:3a7713b1edbc 2219 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2220 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2221 */
AnnaBridge 171:3a7713b1edbc 2222 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2223 {
AnnaBridge 171:3a7713b1edbc 2224 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2225 {
AnnaBridge 171:3a7713b1edbc 2226 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 2227 }
AnnaBridge 171:3a7713b1edbc 2228 }
AnnaBridge 171:3a7713b1edbc 2229
AnnaBridge 171:3a7713b1edbc 2230
AnnaBridge 171:3a7713b1edbc 2231 /**
AnnaBridge 171:3a7713b1edbc 2232 \brief Get Interrupt Enable status
AnnaBridge 171:3a7713b1edbc 2233 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 171:3a7713b1edbc 2234 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2235 \return 0 Interrupt is not enabled.
AnnaBridge 171:3a7713b1edbc 2236 \return 1 Interrupt is enabled.
AnnaBridge 171:3a7713b1edbc 2237 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2238 */
AnnaBridge 171:3a7713b1edbc 2239 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2240 {
AnnaBridge 171:3a7713b1edbc 2241 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2242 {
AnnaBridge 171:3a7713b1edbc 2243 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 2244 }
AnnaBridge 171:3a7713b1edbc 2245 else
AnnaBridge 171:3a7713b1edbc 2246 {
AnnaBridge 171:3a7713b1edbc 2247 return(0U);
AnnaBridge 171:3a7713b1edbc 2248 }
AnnaBridge 171:3a7713b1edbc 2249 }
AnnaBridge 171:3a7713b1edbc 2250
AnnaBridge 171:3a7713b1edbc 2251
AnnaBridge 171:3a7713b1edbc 2252 /**
AnnaBridge 171:3a7713b1edbc 2253 \brief Disable Interrupt
AnnaBridge 171:3a7713b1edbc 2254 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 171:3a7713b1edbc 2255 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2256 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2257 */
AnnaBridge 171:3a7713b1edbc 2258 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2259 {
AnnaBridge 171:3a7713b1edbc 2260 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2261 {
AnnaBridge 171:3a7713b1edbc 2262 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 2263 __DSB();
AnnaBridge 171:3a7713b1edbc 2264 __ISB();
AnnaBridge 171:3a7713b1edbc 2265 }
AnnaBridge 171:3a7713b1edbc 2266 }
AnnaBridge 171:3a7713b1edbc 2267
AnnaBridge 171:3a7713b1edbc 2268
AnnaBridge 171:3a7713b1edbc 2269 /**
AnnaBridge 171:3a7713b1edbc 2270 \brief Get Pending Interrupt
AnnaBridge 171:3a7713b1edbc 2271 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 171:3a7713b1edbc 2272 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2273 \return 0 Interrupt status is not pending.
AnnaBridge 171:3a7713b1edbc 2274 \return 1 Interrupt status is pending.
AnnaBridge 171:3a7713b1edbc 2275 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2276 */
AnnaBridge 171:3a7713b1edbc 2277 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2278 {
AnnaBridge 171:3a7713b1edbc 2279 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2280 {
AnnaBridge 171:3a7713b1edbc 2281 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 2282 }
AnnaBridge 171:3a7713b1edbc 2283 else
AnnaBridge 171:3a7713b1edbc 2284 {
AnnaBridge 171:3a7713b1edbc 2285 return(0U);
AnnaBridge 171:3a7713b1edbc 2286 }
AnnaBridge 171:3a7713b1edbc 2287 }
AnnaBridge 171:3a7713b1edbc 2288
AnnaBridge 171:3a7713b1edbc 2289
AnnaBridge 171:3a7713b1edbc 2290 /**
AnnaBridge 171:3a7713b1edbc 2291 \brief Set Pending Interrupt
AnnaBridge 171:3a7713b1edbc 2292 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 171:3a7713b1edbc 2293 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2294 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2295 */
AnnaBridge 171:3a7713b1edbc 2296 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2297 {
AnnaBridge 171:3a7713b1edbc 2298 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2299 {
AnnaBridge 171:3a7713b1edbc 2300 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 2301 }
AnnaBridge 171:3a7713b1edbc 2302 }
AnnaBridge 171:3a7713b1edbc 2303
AnnaBridge 171:3a7713b1edbc 2304
AnnaBridge 171:3a7713b1edbc 2305 /**
AnnaBridge 171:3a7713b1edbc 2306 \brief Clear Pending Interrupt
AnnaBridge 171:3a7713b1edbc 2307 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 171:3a7713b1edbc 2308 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2309 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2310 */
AnnaBridge 171:3a7713b1edbc 2311 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2312 {
AnnaBridge 171:3a7713b1edbc 2313 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2314 {
AnnaBridge 171:3a7713b1edbc 2315 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 2316 }
AnnaBridge 171:3a7713b1edbc 2317 }
AnnaBridge 171:3a7713b1edbc 2318
AnnaBridge 171:3a7713b1edbc 2319
AnnaBridge 171:3a7713b1edbc 2320 /**
AnnaBridge 171:3a7713b1edbc 2321 \brief Get Active Interrupt
AnnaBridge 171:3a7713b1edbc 2322 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge 171:3a7713b1edbc 2323 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2324 \return 0 Interrupt status is not active.
AnnaBridge 171:3a7713b1edbc 2325 \return 1 Interrupt status is active.
AnnaBridge 171:3a7713b1edbc 2326 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2327 */
AnnaBridge 171:3a7713b1edbc 2328 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2329 {
AnnaBridge 171:3a7713b1edbc 2330 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2331 {
AnnaBridge 171:3a7713b1edbc 2332 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 2333 }
AnnaBridge 171:3a7713b1edbc 2334 else
AnnaBridge 171:3a7713b1edbc 2335 {
AnnaBridge 171:3a7713b1edbc 2336 return(0U);
AnnaBridge 171:3a7713b1edbc 2337 }
AnnaBridge 171:3a7713b1edbc 2338 }
AnnaBridge 171:3a7713b1edbc 2339
AnnaBridge 171:3a7713b1edbc 2340
AnnaBridge 171:3a7713b1edbc 2341 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 171:3a7713b1edbc 2342 /**
AnnaBridge 171:3a7713b1edbc 2343 \brief Get Interrupt Target State
AnnaBridge 171:3a7713b1edbc 2344 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 171:3a7713b1edbc 2345 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2346 \return 0 if interrupt is assigned to Secure
AnnaBridge 171:3a7713b1edbc 2347 \return 1 if interrupt is assigned to Non Secure
AnnaBridge 171:3a7713b1edbc 2348 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2349 */
AnnaBridge 171:3a7713b1edbc 2350 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2351 {
AnnaBridge 171:3a7713b1edbc 2352 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2353 {
AnnaBridge 171:3a7713b1edbc 2354 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 2355 }
AnnaBridge 171:3a7713b1edbc 2356 else
AnnaBridge 171:3a7713b1edbc 2357 {
AnnaBridge 171:3a7713b1edbc 2358 return(0U);
AnnaBridge 171:3a7713b1edbc 2359 }
AnnaBridge 171:3a7713b1edbc 2360 }
AnnaBridge 171:3a7713b1edbc 2361
AnnaBridge 171:3a7713b1edbc 2362
AnnaBridge 171:3a7713b1edbc 2363 /**
AnnaBridge 171:3a7713b1edbc 2364 \brief Set Interrupt Target State
AnnaBridge 171:3a7713b1edbc 2365 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 171:3a7713b1edbc 2366 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2367 \return 0 if interrupt is assigned to Secure
AnnaBridge 171:3a7713b1edbc 2368 1 if interrupt is assigned to Non Secure
AnnaBridge 171:3a7713b1edbc 2369 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2370 */
AnnaBridge 171:3a7713b1edbc 2371 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2372 {
AnnaBridge 171:3a7713b1edbc 2373 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2374 {
AnnaBridge 171:3a7713b1edbc 2375 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
AnnaBridge 171:3a7713b1edbc 2376 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 2377 }
AnnaBridge 171:3a7713b1edbc 2378 else
AnnaBridge 171:3a7713b1edbc 2379 {
AnnaBridge 171:3a7713b1edbc 2380 return(0U);
AnnaBridge 171:3a7713b1edbc 2381 }
AnnaBridge 171:3a7713b1edbc 2382 }
AnnaBridge 171:3a7713b1edbc 2383
AnnaBridge 171:3a7713b1edbc 2384
AnnaBridge 171:3a7713b1edbc 2385 /**
AnnaBridge 171:3a7713b1edbc 2386 \brief Clear Interrupt Target State
AnnaBridge 171:3a7713b1edbc 2387 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge 171:3a7713b1edbc 2388 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2389 \return 0 if interrupt is assigned to Secure
AnnaBridge 171:3a7713b1edbc 2390 1 if interrupt is assigned to Non Secure
AnnaBridge 171:3a7713b1edbc 2391 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2392 */
AnnaBridge 171:3a7713b1edbc 2393 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2394 {
AnnaBridge 171:3a7713b1edbc 2395 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2396 {
AnnaBridge 171:3a7713b1edbc 2397 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
AnnaBridge 171:3a7713b1edbc 2398 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 2399 }
AnnaBridge 171:3a7713b1edbc 2400 else
AnnaBridge 171:3a7713b1edbc 2401 {
AnnaBridge 171:3a7713b1edbc 2402 return(0U);
AnnaBridge 171:3a7713b1edbc 2403 }
AnnaBridge 171:3a7713b1edbc 2404 }
AnnaBridge 171:3a7713b1edbc 2405 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 171:3a7713b1edbc 2406
AnnaBridge 171:3a7713b1edbc 2407
AnnaBridge 171:3a7713b1edbc 2408 /**
AnnaBridge 171:3a7713b1edbc 2409 \brief Set Interrupt Priority
AnnaBridge 171:3a7713b1edbc 2410 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 171:3a7713b1edbc 2411 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 2412 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 2413 \param [in] IRQn Interrupt number.
AnnaBridge 171:3a7713b1edbc 2414 \param [in] priority Priority to set.
AnnaBridge 171:3a7713b1edbc 2415 \note The priority cannot be set for every processor exception.
AnnaBridge 171:3a7713b1edbc 2416 */
AnnaBridge 171:3a7713b1edbc 2417 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 171:3a7713b1edbc 2418 {
AnnaBridge 171:3a7713b1edbc 2419 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2420 {
AnnaBridge 171:3a7713b1edbc 2421 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 171:3a7713b1edbc 2422 }
AnnaBridge 171:3a7713b1edbc 2423 else
AnnaBridge 171:3a7713b1edbc 2424 {
AnnaBridge 171:3a7713b1edbc 2425 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 171:3a7713b1edbc 2426 }
AnnaBridge 171:3a7713b1edbc 2427 }
AnnaBridge 171:3a7713b1edbc 2428
AnnaBridge 171:3a7713b1edbc 2429
AnnaBridge 171:3a7713b1edbc 2430 /**
AnnaBridge 171:3a7713b1edbc 2431 \brief Get Interrupt Priority
AnnaBridge 171:3a7713b1edbc 2432 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 171:3a7713b1edbc 2433 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 2434 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 2435 \param [in] IRQn Interrupt number.
AnnaBridge 171:3a7713b1edbc 2436 \return Interrupt Priority.
AnnaBridge 171:3a7713b1edbc 2437 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 171:3a7713b1edbc 2438 */
AnnaBridge 171:3a7713b1edbc 2439 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2440 {
AnnaBridge 171:3a7713b1edbc 2441
AnnaBridge 171:3a7713b1edbc 2442 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2443 {
AnnaBridge 171:3a7713b1edbc 2444 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 171:3a7713b1edbc 2445 }
AnnaBridge 171:3a7713b1edbc 2446 else
AnnaBridge 171:3a7713b1edbc 2447 {
AnnaBridge 171:3a7713b1edbc 2448 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 171:3a7713b1edbc 2449 }
AnnaBridge 171:3a7713b1edbc 2450 }
AnnaBridge 171:3a7713b1edbc 2451
AnnaBridge 171:3a7713b1edbc 2452
AnnaBridge 171:3a7713b1edbc 2453 /**
AnnaBridge 171:3a7713b1edbc 2454 \brief Encode Priority
AnnaBridge 171:3a7713b1edbc 2455 \details Encodes the priority for an interrupt with the given priority group,
AnnaBridge 171:3a7713b1edbc 2456 preemptive priority value, and subpriority value.
AnnaBridge 171:3a7713b1edbc 2457 In case of a conflict between priority grouping and available
AnnaBridge 171:3a7713b1edbc 2458 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 171:3a7713b1edbc 2459 \param [in] PriorityGroup Used priority group.
AnnaBridge 171:3a7713b1edbc 2460 \param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 171:3a7713b1edbc 2461 \param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge 171:3a7713b1edbc 2462 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge 171:3a7713b1edbc 2463 */
AnnaBridge 171:3a7713b1edbc 2464 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge 171:3a7713b1edbc 2465 {
AnnaBridge 171:3a7713b1edbc 2466 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 171:3a7713b1edbc 2467 uint32_t PreemptPriorityBits;
AnnaBridge 171:3a7713b1edbc 2468 uint32_t SubPriorityBits;
AnnaBridge 171:3a7713b1edbc 2469
AnnaBridge 171:3a7713b1edbc 2470 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 171:3a7713b1edbc 2471 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 171:3a7713b1edbc 2472
AnnaBridge 171:3a7713b1edbc 2473 return (
AnnaBridge 171:3a7713b1edbc 2474 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
AnnaBridge 171:3a7713b1edbc 2475 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge 171:3a7713b1edbc 2476 );
AnnaBridge 171:3a7713b1edbc 2477 }
AnnaBridge 171:3a7713b1edbc 2478
AnnaBridge 171:3a7713b1edbc 2479
AnnaBridge 171:3a7713b1edbc 2480 /**
AnnaBridge 171:3a7713b1edbc 2481 \brief Decode Priority
AnnaBridge 171:3a7713b1edbc 2482 \details Decodes an interrupt priority value with a given priority group to
AnnaBridge 171:3a7713b1edbc 2483 preemptive priority value and subpriority value.
AnnaBridge 171:3a7713b1edbc 2484 In case of a conflict between priority grouping and available
AnnaBridge 171:3a7713b1edbc 2485 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge 171:3a7713b1edbc 2486 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge 171:3a7713b1edbc 2487 \param [in] PriorityGroup Used priority group.
AnnaBridge 171:3a7713b1edbc 2488 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge 171:3a7713b1edbc 2489 \param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge 171:3a7713b1edbc 2490 */
AnnaBridge 171:3a7713b1edbc 2491 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge 171:3a7713b1edbc 2492 {
AnnaBridge 171:3a7713b1edbc 2493 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 171:3a7713b1edbc 2494 uint32_t PreemptPriorityBits;
AnnaBridge 171:3a7713b1edbc 2495 uint32_t SubPriorityBits;
AnnaBridge 171:3a7713b1edbc 2496
AnnaBridge 171:3a7713b1edbc 2497 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge 171:3a7713b1edbc 2498 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge 171:3a7713b1edbc 2499
AnnaBridge 171:3a7713b1edbc 2500 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge 171:3a7713b1edbc 2501 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge 171:3a7713b1edbc 2502 }
AnnaBridge 171:3a7713b1edbc 2503
AnnaBridge 171:3a7713b1edbc 2504
AnnaBridge 171:3a7713b1edbc 2505 /**
AnnaBridge 171:3a7713b1edbc 2506 \brief Set Interrupt Vector
AnnaBridge 171:3a7713b1edbc 2507 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 171:3a7713b1edbc 2508 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 2509 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 2510 VTOR must been relocated to SRAM before.
AnnaBridge 171:3a7713b1edbc 2511 \param [in] IRQn Interrupt number
AnnaBridge 171:3a7713b1edbc 2512 \param [in] vector Address of interrupt handler function
AnnaBridge 171:3a7713b1edbc 2513 */
AnnaBridge 171:3a7713b1edbc 2514 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 171:3a7713b1edbc 2515 {
AnnaBridge 171:3a7713b1edbc 2516 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 171:3a7713b1edbc 2517 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 171:3a7713b1edbc 2518 }
AnnaBridge 171:3a7713b1edbc 2519
AnnaBridge 171:3a7713b1edbc 2520
AnnaBridge 171:3a7713b1edbc 2521 /**
AnnaBridge 171:3a7713b1edbc 2522 \brief Get Interrupt Vector
AnnaBridge 171:3a7713b1edbc 2523 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 171:3a7713b1edbc 2524 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 2525 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 2526 \param [in] IRQn Interrupt number.
AnnaBridge 171:3a7713b1edbc 2527 \return Address of interrupt handler function
AnnaBridge 171:3a7713b1edbc 2528 */
AnnaBridge 171:3a7713b1edbc 2529 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2530 {
AnnaBridge 171:3a7713b1edbc 2531 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 171:3a7713b1edbc 2532 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 171:3a7713b1edbc 2533 }
AnnaBridge 171:3a7713b1edbc 2534
AnnaBridge 171:3a7713b1edbc 2535
AnnaBridge 171:3a7713b1edbc 2536 /**
AnnaBridge 171:3a7713b1edbc 2537 \brief System Reset
AnnaBridge 171:3a7713b1edbc 2538 \details Initiates a system reset request to reset the MCU.
AnnaBridge 171:3a7713b1edbc 2539 */
AnnaBridge 171:3a7713b1edbc 2540 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 171:3a7713b1edbc 2541 {
AnnaBridge 171:3a7713b1edbc 2542 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 171:3a7713b1edbc 2543 buffered write are completed before reset */
AnnaBridge 171:3a7713b1edbc 2544 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 171:3a7713b1edbc 2545 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
AnnaBridge 171:3a7713b1edbc 2546 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
AnnaBridge 171:3a7713b1edbc 2547 __DSB(); /* Ensure completion of memory access */
AnnaBridge 171:3a7713b1edbc 2548
AnnaBridge 171:3a7713b1edbc 2549 for(;;) /* wait until reset */
AnnaBridge 171:3a7713b1edbc 2550 {
AnnaBridge 171:3a7713b1edbc 2551 __NOP();
AnnaBridge 171:3a7713b1edbc 2552 }
AnnaBridge 171:3a7713b1edbc 2553 }
AnnaBridge 171:3a7713b1edbc 2554
AnnaBridge 171:3a7713b1edbc 2555 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 171:3a7713b1edbc 2556 /**
AnnaBridge 171:3a7713b1edbc 2557 \brief Set Priority Grouping (non-secure)
AnnaBridge 171:3a7713b1edbc 2558 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
AnnaBridge 171:3a7713b1edbc 2559 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge 171:3a7713b1edbc 2560 Only values from 0..7 are used.
AnnaBridge 171:3a7713b1edbc 2561 In case of a conflict between priority grouping and available
AnnaBridge 171:3a7713b1edbc 2562 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge 171:3a7713b1edbc 2563 \param [in] PriorityGroup Priority grouping field.
AnnaBridge 171:3a7713b1edbc 2564 */
AnnaBridge 171:3a7713b1edbc 2565 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
AnnaBridge 171:3a7713b1edbc 2566 {
AnnaBridge 171:3a7713b1edbc 2567 uint32_t reg_value;
AnnaBridge 171:3a7713b1edbc 2568 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge 171:3a7713b1edbc 2569
AnnaBridge 171:3a7713b1edbc 2570 reg_value = SCB_NS->AIRCR; /* read old register configuration */
AnnaBridge 171:3a7713b1edbc 2571 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
AnnaBridge 171:3a7713b1edbc 2572 reg_value = (reg_value |
AnnaBridge 171:3a7713b1edbc 2573 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 171:3a7713b1edbc 2574 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
AnnaBridge 171:3a7713b1edbc 2575 SCB_NS->AIRCR = reg_value;
AnnaBridge 171:3a7713b1edbc 2576 }
AnnaBridge 171:3a7713b1edbc 2577
AnnaBridge 171:3a7713b1edbc 2578
AnnaBridge 171:3a7713b1edbc 2579 /**
AnnaBridge 171:3a7713b1edbc 2580 \brief Get Priority Grouping (non-secure)
AnnaBridge 171:3a7713b1edbc 2581 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
AnnaBridge 171:3a7713b1edbc 2582 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
AnnaBridge 171:3a7713b1edbc 2583 */
AnnaBridge 171:3a7713b1edbc 2584 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
AnnaBridge 171:3a7713b1edbc 2585 {
AnnaBridge 171:3a7713b1edbc 2586 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
AnnaBridge 171:3a7713b1edbc 2587 }
AnnaBridge 171:3a7713b1edbc 2588
AnnaBridge 171:3a7713b1edbc 2589
AnnaBridge 171:3a7713b1edbc 2590 /**
AnnaBridge 171:3a7713b1edbc 2591 \brief Enable Interrupt (non-secure)
AnnaBridge 171:3a7713b1edbc 2592 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 171:3a7713b1edbc 2593 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2594 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2595 */
AnnaBridge 171:3a7713b1edbc 2596 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2597 {
AnnaBridge 171:3a7713b1edbc 2598 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2599 {
AnnaBridge 171:3a7713b1edbc 2600 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 2601 }
AnnaBridge 171:3a7713b1edbc 2602 }
AnnaBridge 171:3a7713b1edbc 2603
AnnaBridge 171:3a7713b1edbc 2604
AnnaBridge 171:3a7713b1edbc 2605 /**
AnnaBridge 171:3a7713b1edbc 2606 \brief Get Interrupt Enable status (non-secure)
AnnaBridge 171:3a7713b1edbc 2607 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 171:3a7713b1edbc 2608 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2609 \return 0 Interrupt is not enabled.
AnnaBridge 171:3a7713b1edbc 2610 \return 1 Interrupt is enabled.
AnnaBridge 171:3a7713b1edbc 2611 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2612 */
AnnaBridge 171:3a7713b1edbc 2613 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2614 {
AnnaBridge 171:3a7713b1edbc 2615 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2616 {
AnnaBridge 171:3a7713b1edbc 2617 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 2618 }
AnnaBridge 171:3a7713b1edbc 2619 else
AnnaBridge 171:3a7713b1edbc 2620 {
AnnaBridge 171:3a7713b1edbc 2621 return(0U);
AnnaBridge 171:3a7713b1edbc 2622 }
AnnaBridge 171:3a7713b1edbc 2623 }
AnnaBridge 171:3a7713b1edbc 2624
AnnaBridge 171:3a7713b1edbc 2625
AnnaBridge 171:3a7713b1edbc 2626 /**
AnnaBridge 171:3a7713b1edbc 2627 \brief Disable Interrupt (non-secure)
AnnaBridge 171:3a7713b1edbc 2628 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge 171:3a7713b1edbc 2629 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2630 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2631 */
AnnaBridge 171:3a7713b1edbc 2632 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2633 {
AnnaBridge 171:3a7713b1edbc 2634 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2635 {
AnnaBridge 171:3a7713b1edbc 2636 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 2637 }
AnnaBridge 171:3a7713b1edbc 2638 }
AnnaBridge 171:3a7713b1edbc 2639
AnnaBridge 171:3a7713b1edbc 2640
AnnaBridge 171:3a7713b1edbc 2641 /**
AnnaBridge 171:3a7713b1edbc 2642 \brief Get Pending Interrupt (non-secure)
AnnaBridge 171:3a7713b1edbc 2643 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge 171:3a7713b1edbc 2644 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2645 \return 0 Interrupt status is not pending.
AnnaBridge 171:3a7713b1edbc 2646 \return 1 Interrupt status is pending.
AnnaBridge 171:3a7713b1edbc 2647 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2648 */
AnnaBridge 171:3a7713b1edbc 2649 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2650 {
AnnaBridge 171:3a7713b1edbc 2651 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2652 {
AnnaBridge 171:3a7713b1edbc 2653 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 2654 }
AnnaBridge 171:3a7713b1edbc 2655 else
AnnaBridge 171:3a7713b1edbc 2656 {
AnnaBridge 171:3a7713b1edbc 2657 return(0U);
AnnaBridge 171:3a7713b1edbc 2658 }
AnnaBridge 171:3a7713b1edbc 2659 }
AnnaBridge 171:3a7713b1edbc 2660
AnnaBridge 171:3a7713b1edbc 2661
AnnaBridge 171:3a7713b1edbc 2662 /**
AnnaBridge 171:3a7713b1edbc 2663 \brief Set Pending Interrupt (non-secure)
AnnaBridge 171:3a7713b1edbc 2664 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge 171:3a7713b1edbc 2665 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2666 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2667 */
AnnaBridge 171:3a7713b1edbc 2668 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2669 {
AnnaBridge 171:3a7713b1edbc 2670 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2671 {
AnnaBridge 171:3a7713b1edbc 2672 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 2673 }
AnnaBridge 171:3a7713b1edbc 2674 }
AnnaBridge 171:3a7713b1edbc 2675
AnnaBridge 171:3a7713b1edbc 2676
AnnaBridge 171:3a7713b1edbc 2677 /**
AnnaBridge 171:3a7713b1edbc 2678 \brief Clear Pending Interrupt (non-secure)
AnnaBridge 171:3a7713b1edbc 2679 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge 171:3a7713b1edbc 2680 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2681 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2682 */
AnnaBridge 171:3a7713b1edbc 2683 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2684 {
AnnaBridge 171:3a7713b1edbc 2685 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2686 {
AnnaBridge 171:3a7713b1edbc 2687 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 171:3a7713b1edbc 2688 }
AnnaBridge 171:3a7713b1edbc 2689 }
AnnaBridge 171:3a7713b1edbc 2690
AnnaBridge 171:3a7713b1edbc 2691
AnnaBridge 171:3a7713b1edbc 2692 /**
AnnaBridge 171:3a7713b1edbc 2693 \brief Get Active Interrupt (non-secure)
AnnaBridge 171:3a7713b1edbc 2694 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge 171:3a7713b1edbc 2695 \param [in] IRQn Device specific interrupt number.
AnnaBridge 171:3a7713b1edbc 2696 \return 0 Interrupt status is not active.
AnnaBridge 171:3a7713b1edbc 2697 \return 1 Interrupt status is active.
AnnaBridge 171:3a7713b1edbc 2698 \note IRQn must not be negative.
AnnaBridge 171:3a7713b1edbc 2699 */
AnnaBridge 171:3a7713b1edbc 2700 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2701 {
AnnaBridge 171:3a7713b1edbc 2702 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2703 {
AnnaBridge 171:3a7713b1edbc 2704 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 171:3a7713b1edbc 2705 }
AnnaBridge 171:3a7713b1edbc 2706 else
AnnaBridge 171:3a7713b1edbc 2707 {
AnnaBridge 171:3a7713b1edbc 2708 return(0U);
AnnaBridge 171:3a7713b1edbc 2709 }
AnnaBridge 171:3a7713b1edbc 2710 }
AnnaBridge 171:3a7713b1edbc 2711
AnnaBridge 171:3a7713b1edbc 2712
AnnaBridge 171:3a7713b1edbc 2713 /**
AnnaBridge 171:3a7713b1edbc 2714 \brief Set Interrupt Priority (non-secure)
AnnaBridge 171:3a7713b1edbc 2715 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge 171:3a7713b1edbc 2716 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 2717 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 2718 \param [in] IRQn Interrupt number.
AnnaBridge 171:3a7713b1edbc 2719 \param [in] priority Priority to set.
AnnaBridge 171:3a7713b1edbc 2720 \note The priority cannot be set for every non-secure processor exception.
AnnaBridge 171:3a7713b1edbc 2721 */
AnnaBridge 171:3a7713b1edbc 2722 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 171:3a7713b1edbc 2723 {
AnnaBridge 171:3a7713b1edbc 2724 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2725 {
AnnaBridge 171:3a7713b1edbc 2726 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 171:3a7713b1edbc 2727 }
AnnaBridge 171:3a7713b1edbc 2728 else
AnnaBridge 171:3a7713b1edbc 2729 {
AnnaBridge 171:3a7713b1edbc 2730 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge 171:3a7713b1edbc 2731 }
AnnaBridge 171:3a7713b1edbc 2732 }
AnnaBridge 171:3a7713b1edbc 2733
AnnaBridge 171:3a7713b1edbc 2734
AnnaBridge 171:3a7713b1edbc 2735 /**
AnnaBridge 171:3a7713b1edbc 2736 \brief Get Interrupt Priority (non-secure)
AnnaBridge 171:3a7713b1edbc 2737 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge 171:3a7713b1edbc 2738 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 171:3a7713b1edbc 2739 or negative to specify a processor exception.
AnnaBridge 171:3a7713b1edbc 2740 \param [in] IRQn Interrupt number.
AnnaBridge 171:3a7713b1edbc 2741 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 171:3a7713b1edbc 2742 */
AnnaBridge 171:3a7713b1edbc 2743 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge 171:3a7713b1edbc 2744 {
AnnaBridge 171:3a7713b1edbc 2745
AnnaBridge 171:3a7713b1edbc 2746 if ((int32_t)(IRQn) >= 0)
AnnaBridge 171:3a7713b1edbc 2747 {
AnnaBridge 171:3a7713b1edbc 2748 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 171:3a7713b1edbc 2749 }
AnnaBridge 171:3a7713b1edbc 2750 else
AnnaBridge 171:3a7713b1edbc 2751 {
AnnaBridge 171:3a7713b1edbc 2752 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 171:3a7713b1edbc 2753 }
AnnaBridge 171:3a7713b1edbc 2754 }
AnnaBridge 171:3a7713b1edbc 2755 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 171:3a7713b1edbc 2756
AnnaBridge 171:3a7713b1edbc 2757 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 171:3a7713b1edbc 2758
AnnaBridge 171:3a7713b1edbc 2759 /* ########################## MPU functions #################################### */
AnnaBridge 171:3a7713b1edbc 2760
AnnaBridge 171:3a7713b1edbc 2761 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 171:3a7713b1edbc 2762
AnnaBridge 171:3a7713b1edbc 2763 #include "mpu_armv8.h"
AnnaBridge 171:3a7713b1edbc 2764
AnnaBridge 171:3a7713b1edbc 2765 #endif
AnnaBridge 171:3a7713b1edbc 2766
AnnaBridge 171:3a7713b1edbc 2767 /* ########################## FPU functions #################################### */
AnnaBridge 171:3a7713b1edbc 2768 /**
AnnaBridge 171:3a7713b1edbc 2769 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 2770 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 171:3a7713b1edbc 2771 \brief Function that provides FPU type.
AnnaBridge 171:3a7713b1edbc 2772 @{
AnnaBridge 171:3a7713b1edbc 2773 */
AnnaBridge 171:3a7713b1edbc 2774
AnnaBridge 171:3a7713b1edbc 2775 /**
AnnaBridge 171:3a7713b1edbc 2776 \brief get FPU type
AnnaBridge 171:3a7713b1edbc 2777 \details returns the FPU type
AnnaBridge 171:3a7713b1edbc 2778 \returns
AnnaBridge 171:3a7713b1edbc 2779 - \b 0: No FPU
AnnaBridge 171:3a7713b1edbc 2780 - \b 1: Single precision FPU
AnnaBridge 171:3a7713b1edbc 2781 - \b 2: Double + Single precision FPU
AnnaBridge 171:3a7713b1edbc 2782 */
AnnaBridge 171:3a7713b1edbc 2783 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 171:3a7713b1edbc 2784 {
AnnaBridge 171:3a7713b1edbc 2785 uint32_t mvfr0;
AnnaBridge 171:3a7713b1edbc 2786
AnnaBridge 171:3a7713b1edbc 2787 mvfr0 = FPU->MVFR0;
AnnaBridge 171:3a7713b1edbc 2788 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
AnnaBridge 171:3a7713b1edbc 2789 {
AnnaBridge 171:3a7713b1edbc 2790 return 2U; /* Double + Single precision FPU */
AnnaBridge 171:3a7713b1edbc 2791 }
AnnaBridge 171:3a7713b1edbc 2792 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
AnnaBridge 171:3a7713b1edbc 2793 {
AnnaBridge 171:3a7713b1edbc 2794 return 1U; /* Single precision FPU */
AnnaBridge 171:3a7713b1edbc 2795 }
AnnaBridge 171:3a7713b1edbc 2796 else
AnnaBridge 171:3a7713b1edbc 2797 {
AnnaBridge 171:3a7713b1edbc 2798 return 0U; /* No FPU */
AnnaBridge 171:3a7713b1edbc 2799 }
AnnaBridge 171:3a7713b1edbc 2800 }
AnnaBridge 171:3a7713b1edbc 2801
AnnaBridge 171:3a7713b1edbc 2802
AnnaBridge 171:3a7713b1edbc 2803 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 171:3a7713b1edbc 2804
AnnaBridge 171:3a7713b1edbc 2805
AnnaBridge 171:3a7713b1edbc 2806
AnnaBridge 171:3a7713b1edbc 2807 /* ########################## SAU functions #################################### */
AnnaBridge 171:3a7713b1edbc 2808 /**
AnnaBridge 171:3a7713b1edbc 2809 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 2810 \defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge 171:3a7713b1edbc 2811 \brief Functions that configure the SAU.
AnnaBridge 171:3a7713b1edbc 2812 @{
AnnaBridge 171:3a7713b1edbc 2813 */
AnnaBridge 171:3a7713b1edbc 2814
AnnaBridge 171:3a7713b1edbc 2815 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 171:3a7713b1edbc 2816
AnnaBridge 171:3a7713b1edbc 2817 /**
AnnaBridge 171:3a7713b1edbc 2818 \brief Enable SAU
AnnaBridge 171:3a7713b1edbc 2819 \details Enables the Security Attribution Unit (SAU).
AnnaBridge 171:3a7713b1edbc 2820 */
AnnaBridge 171:3a7713b1edbc 2821 __STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge 171:3a7713b1edbc 2822 {
AnnaBridge 171:3a7713b1edbc 2823 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
AnnaBridge 171:3a7713b1edbc 2824 }
AnnaBridge 171:3a7713b1edbc 2825
AnnaBridge 171:3a7713b1edbc 2826
AnnaBridge 171:3a7713b1edbc 2827
AnnaBridge 171:3a7713b1edbc 2828 /**
AnnaBridge 171:3a7713b1edbc 2829 \brief Disable SAU
AnnaBridge 171:3a7713b1edbc 2830 \details Disables the Security Attribution Unit (SAU).
AnnaBridge 171:3a7713b1edbc 2831 */
AnnaBridge 171:3a7713b1edbc 2832 __STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge 171:3a7713b1edbc 2833 {
AnnaBridge 171:3a7713b1edbc 2834 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge 171:3a7713b1edbc 2835 }
AnnaBridge 171:3a7713b1edbc 2836
AnnaBridge 171:3a7713b1edbc 2837 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 171:3a7713b1edbc 2838
AnnaBridge 171:3a7713b1edbc 2839 /*@} end of CMSIS_Core_SAUFunctions */
AnnaBridge 171:3a7713b1edbc 2840
AnnaBridge 171:3a7713b1edbc 2841
AnnaBridge 171:3a7713b1edbc 2842
AnnaBridge 171:3a7713b1edbc 2843
AnnaBridge 171:3a7713b1edbc 2844 /* ################################## SysTick function ############################################ */
AnnaBridge 171:3a7713b1edbc 2845 /**
AnnaBridge 171:3a7713b1edbc 2846 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 2847 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 171:3a7713b1edbc 2848 \brief Functions that configure the System.
AnnaBridge 171:3a7713b1edbc 2849 @{
AnnaBridge 171:3a7713b1edbc 2850 */
AnnaBridge 171:3a7713b1edbc 2851
AnnaBridge 171:3a7713b1edbc 2852 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 171:3a7713b1edbc 2853
AnnaBridge 171:3a7713b1edbc 2854 /**
AnnaBridge 171:3a7713b1edbc 2855 \brief System Tick Configuration
AnnaBridge 171:3a7713b1edbc 2856 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 171:3a7713b1edbc 2857 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 171:3a7713b1edbc 2858 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 171:3a7713b1edbc 2859 \return 0 Function succeeded.
AnnaBridge 171:3a7713b1edbc 2860 \return 1 Function failed.
AnnaBridge 171:3a7713b1edbc 2861 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 171:3a7713b1edbc 2862 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 171:3a7713b1edbc 2863 must contain a vendor-specific implementation of this function.
AnnaBridge 171:3a7713b1edbc 2864 */
AnnaBridge 171:3a7713b1edbc 2865 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 171:3a7713b1edbc 2866 {
AnnaBridge 171:3a7713b1edbc 2867 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 171:3a7713b1edbc 2868 {
AnnaBridge 171:3a7713b1edbc 2869 return (1UL); /* Reload value impossible */
AnnaBridge 171:3a7713b1edbc 2870 }
AnnaBridge 171:3a7713b1edbc 2871
AnnaBridge 171:3a7713b1edbc 2872 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 171:3a7713b1edbc 2873 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 171:3a7713b1edbc 2874 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 171:3a7713b1edbc 2875 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 171:3a7713b1edbc 2876 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 171:3a7713b1edbc 2877 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 171:3a7713b1edbc 2878 return (0UL); /* Function successful */
AnnaBridge 171:3a7713b1edbc 2879 }
AnnaBridge 171:3a7713b1edbc 2880
AnnaBridge 171:3a7713b1edbc 2881 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge 171:3a7713b1edbc 2882 /**
AnnaBridge 171:3a7713b1edbc 2883 \brief System Tick Configuration (non-secure)
AnnaBridge 171:3a7713b1edbc 2884 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge 171:3a7713b1edbc 2885 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 171:3a7713b1edbc 2886 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 171:3a7713b1edbc 2887 \return 0 Function succeeded.
AnnaBridge 171:3a7713b1edbc 2888 \return 1 Function failed.
AnnaBridge 171:3a7713b1edbc 2889 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 171:3a7713b1edbc 2890 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 171:3a7713b1edbc 2891 must contain a vendor-specific implementation of this function.
AnnaBridge 171:3a7713b1edbc 2892
AnnaBridge 171:3a7713b1edbc 2893 */
AnnaBridge 171:3a7713b1edbc 2894 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge 171:3a7713b1edbc 2895 {
AnnaBridge 171:3a7713b1edbc 2896 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 171:3a7713b1edbc 2897 {
AnnaBridge 171:3a7713b1edbc 2898 return (1UL); /* Reload value impossible */
AnnaBridge 171:3a7713b1edbc 2899 }
AnnaBridge 171:3a7713b1edbc 2900
AnnaBridge 171:3a7713b1edbc 2901 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 171:3a7713b1edbc 2902 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 171:3a7713b1edbc 2903 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 171:3a7713b1edbc 2904 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 171:3a7713b1edbc 2905 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 171:3a7713b1edbc 2906 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 171:3a7713b1edbc 2907 return (0UL); /* Function successful */
AnnaBridge 171:3a7713b1edbc 2908 }
AnnaBridge 171:3a7713b1edbc 2909 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge 171:3a7713b1edbc 2910
AnnaBridge 171:3a7713b1edbc 2911 #endif
AnnaBridge 171:3a7713b1edbc 2912
AnnaBridge 171:3a7713b1edbc 2913 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 171:3a7713b1edbc 2914
AnnaBridge 171:3a7713b1edbc 2915
AnnaBridge 171:3a7713b1edbc 2916
AnnaBridge 171:3a7713b1edbc 2917 /* ##################################### Debug In/Output function ########################################### */
AnnaBridge 171:3a7713b1edbc 2918 /**
AnnaBridge 171:3a7713b1edbc 2919 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 171:3a7713b1edbc 2920 \defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge 171:3a7713b1edbc 2921 \brief Functions that access the ITM debug interface.
AnnaBridge 171:3a7713b1edbc 2922 @{
AnnaBridge 171:3a7713b1edbc 2923 */
AnnaBridge 171:3a7713b1edbc 2924
AnnaBridge 171:3a7713b1edbc 2925 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
AnnaBridge 171:3a7713b1edbc 2926 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
AnnaBridge 171:3a7713b1edbc 2927
AnnaBridge 171:3a7713b1edbc 2928
AnnaBridge 171:3a7713b1edbc 2929 /**
AnnaBridge 171:3a7713b1edbc 2930 \brief ITM Send Character
AnnaBridge 171:3a7713b1edbc 2931 \details Transmits a character via the ITM channel 0, and
AnnaBridge 171:3a7713b1edbc 2932 \li Just returns when no debugger is connected that has booked the output.
AnnaBridge 171:3a7713b1edbc 2933 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge 171:3a7713b1edbc 2934 \param [in] ch Character to transmit.
AnnaBridge 171:3a7713b1edbc 2935 \returns Character to transmit.
AnnaBridge 171:3a7713b1edbc 2936 */
AnnaBridge 171:3a7713b1edbc 2937 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
AnnaBridge 171:3a7713b1edbc 2938 {
AnnaBridge 171:3a7713b1edbc 2939 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
AnnaBridge 171:3a7713b1edbc 2940 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
AnnaBridge 171:3a7713b1edbc 2941 {
AnnaBridge 171:3a7713b1edbc 2942 while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge 171:3a7713b1edbc 2943 {
AnnaBridge 171:3a7713b1edbc 2944 __NOP();
AnnaBridge 171:3a7713b1edbc 2945 }
AnnaBridge 171:3a7713b1edbc 2946 ITM->PORT[0U].u8 = (uint8_t)ch;
AnnaBridge 171:3a7713b1edbc 2947 }
AnnaBridge 171:3a7713b1edbc 2948 return (ch);
AnnaBridge 171:3a7713b1edbc 2949 }
AnnaBridge 171:3a7713b1edbc 2950
AnnaBridge 171:3a7713b1edbc 2951
AnnaBridge 171:3a7713b1edbc 2952 /**
AnnaBridge 171:3a7713b1edbc 2953 \brief ITM Receive Character
AnnaBridge 171:3a7713b1edbc 2954 \details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge 171:3a7713b1edbc 2955 \return Received character.
AnnaBridge 171:3a7713b1edbc 2956 \return -1 No character pending.
AnnaBridge 171:3a7713b1edbc 2957 */
AnnaBridge 171:3a7713b1edbc 2958 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge 171:3a7713b1edbc 2959 {
AnnaBridge 171:3a7713b1edbc 2960 int32_t ch = -1; /* no character available */
AnnaBridge 171:3a7713b1edbc 2961
AnnaBridge 171:3a7713b1edbc 2962 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge 171:3a7713b1edbc 2963 {
AnnaBridge 171:3a7713b1edbc 2964 ch = ITM_RxBuffer;
AnnaBridge 171:3a7713b1edbc 2965 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
AnnaBridge 171:3a7713b1edbc 2966 }
AnnaBridge 171:3a7713b1edbc 2967
AnnaBridge 171:3a7713b1edbc 2968 return (ch);
AnnaBridge 171:3a7713b1edbc 2969 }
AnnaBridge 171:3a7713b1edbc 2970
AnnaBridge 171:3a7713b1edbc 2971
AnnaBridge 171:3a7713b1edbc 2972 /**
AnnaBridge 171:3a7713b1edbc 2973 \brief ITM Check Character
AnnaBridge 171:3a7713b1edbc 2974 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge 171:3a7713b1edbc 2975 \return 0 No character available.
AnnaBridge 171:3a7713b1edbc 2976 \return 1 Character available.
AnnaBridge 171:3a7713b1edbc 2977 */
AnnaBridge 171:3a7713b1edbc 2978 __STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge 171:3a7713b1edbc 2979 {
AnnaBridge 171:3a7713b1edbc 2980
AnnaBridge 171:3a7713b1edbc 2981 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge 171:3a7713b1edbc 2982 {
AnnaBridge 171:3a7713b1edbc 2983 return (0); /* no character available */
AnnaBridge 171:3a7713b1edbc 2984 }
AnnaBridge 171:3a7713b1edbc 2985 else
AnnaBridge 171:3a7713b1edbc 2986 {
AnnaBridge 171:3a7713b1edbc 2987 return (1); /* character available */
AnnaBridge 171:3a7713b1edbc 2988 }
AnnaBridge 171:3a7713b1edbc 2989 }
AnnaBridge 171:3a7713b1edbc 2990
AnnaBridge 171:3a7713b1edbc 2991 /*@} end of CMSIS_core_DebugFunctions */
AnnaBridge 171:3a7713b1edbc 2992
AnnaBridge 171:3a7713b1edbc 2993
AnnaBridge 171:3a7713b1edbc 2994
AnnaBridge 171:3a7713b1edbc 2995
AnnaBridge 171:3a7713b1edbc 2996 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 2997 }
AnnaBridge 171:3a7713b1edbc 2998 #endif
AnnaBridge 171:3a7713b1edbc 2999
AnnaBridge 171:3a7713b1edbc 3000 #endif /* __CORE_CM33_H_DEPENDANT */
AnnaBridge 171:3a7713b1edbc 3001
AnnaBridge 171:3a7713b1edbc 3002 #endif /* __CMSIS_GENERIC */