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TARGET_KW41Z/TOOLCHAIN_GCC_ARM/fsl_xcvr.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/*
AnnaBridge	172:65be27845400	2	* Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge	172:65be27845400	3	* Copyright 2016-2017 NXP.
AnnaBridge	172:65be27845400	4	*
AnnaBridge	172:65be27845400	5	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	172:65be27845400	6	* are permitted provided that the following conditions are met:
AnnaBridge	172:65be27845400	7	*
AnnaBridge	172:65be27845400	8	* o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge	172:65be27845400	9	* of conditions and the following disclaimer.
AnnaBridge	172:65be27845400	10	*
AnnaBridge	172:65be27845400	11	* o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge	172:65be27845400	12	* list of conditions and the following disclaimer in the documentation and/or
AnnaBridge	172:65be27845400	13	* other materials provided with the distribution.
AnnaBridge	172:65be27845400	14	*
AnnaBridge	172:65be27845400	15	* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge	172:65be27845400	16	* contributors may be used to endorse or promote products derived from this
AnnaBridge	172:65be27845400	17	* software without specific prior written permission.
AnnaBridge	172:65be27845400	18	*
AnnaBridge	172:65be27845400	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge	172:65be27845400	20	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge	172:65be27845400	21	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	172:65be27845400	22	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge	172:65be27845400	23	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge	172:65be27845400	24	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge	172:65be27845400	25	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge	172:65be27845400	26	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge	172:65be27845400	27	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge	172:65be27845400	28	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	172:65be27845400	29	*/
AnnaBridge	172:65be27845400	30	#ifndef _FSL_XCVR_H_
AnnaBridge	172:65be27845400	31	/* clang-format off */
AnnaBridge	172:65be27845400	32	#define _FSL_XCVR_H_
AnnaBridge	172:65be27845400	33	/* clang-format on */
AnnaBridge	172:65be27845400	34
AnnaBridge	172:65be27845400	35	#include "fsl_device_registers.h"
AnnaBridge	172:65be27845400	36	#include "fsl_xcvr_trim.h"
AnnaBridge	172:65be27845400	37
AnnaBridge	172:65be27845400	38	#if gMWS_UseCoexistence_d
AnnaBridge	172:65be27845400	39	#include "MWS.h"
AnnaBridge	172:65be27845400	40	#endif /* gMWS_UseCoexistence_d */
AnnaBridge	172:65be27845400	41	/*!
AnnaBridge	172:65be27845400	42	* @addtogroup xcvr
AnnaBridge	172:65be27845400	43	* @{
AnnaBridge	172:65be27845400	44	*/
AnnaBridge	172:65be27845400	45
AnnaBridge	172:65be27845400	46	/! @file/
AnnaBridge	172:65be27845400	47
AnnaBridge	172:65be27845400	48	/*******************************************************************************
AnnaBridge	172:65be27845400	49	* Definitions
AnnaBridge	172:65be27845400	50	******************************************************************************/
AnnaBridge	172:65be27845400	51	/* KW4xZ/KW3xZ/KW2xZ Radio type */
AnnaBridge	172:65be27845400	52	#define RADIO_IS_GEN_2P0 (1)
AnnaBridge	172:65be27845400	53
AnnaBridge	172:65be27845400	54	/* Default RF OSC definition. Allows for compile time clock frequency definition */
AnnaBridge	172:65be27845400	55	#ifdef CLOCK_MAIN
AnnaBridge	172:65be27845400	56
AnnaBridge	172:65be27845400	57	#else
AnnaBridge	172:65be27845400	58	#if RF_OSC_26MHZ == 1
AnnaBridge	172:65be27845400	59	#define CLOCK_MAIN (EXT_CLK_26_MHZ) /* See ext_clock_config_t for this value */
AnnaBridge	172:65be27845400	60	#else
AnnaBridge	172:65be27845400	61	#define CLOCK_MAIN (EXT_CLK_32_MHZ) /* See ext_clock_config_t for this value */
AnnaBridge	172:65be27845400	62	#endif /* RF_OSC_26MHZ == 1 */
AnnaBridge	172:65be27845400	63	#endif /* CLOCK_MAIN */
AnnaBridge	172:65be27845400	64
AnnaBridge	172:65be27845400	65	#define TBD_ZERO (0)
AnnaBridge	172:65be27845400	66	#define FSL_XCVR_DRIVER_VERSION (MAKE_VERSION(0, 1, 0))
AnnaBridge	172:65be27845400	67
AnnaBridge	172:65be27845400	68	#define B0(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0xFFU)
AnnaBridge	172:65be27845400	69	#define B1(x) (((uint32_t)(((uint32_t)(x)) << 8)) & 0xFF00U)
AnnaBridge	172:65be27845400	70	#define B2(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0xFF0000U)
AnnaBridge	172:65be27845400	71	#define B3(x) (((uint32_t)(((uint32_t)(x)) << 24)) & 0xFF000000U)
AnnaBridge	172:65be27845400	72
AnnaBridge	172:65be27845400	73	#define USE_DEFAULT_PRE_REF (0)
AnnaBridge	172:65be27845400	74	#define TRIM_BBA_DCOC_DAC_AT_INIT (1)
AnnaBridge	172:65be27845400	75	#define PRESLOW_ENA (1)
AnnaBridge	172:65be27845400	76
AnnaBridge	172:65be27845400	77	/* GEN3 TSM defines */
AnnaBridge	172:65be27845400	78	#if RADIO_IS_GEN_3P0
AnnaBridge	172:65be27845400	79
AnnaBridge	172:65be27845400	80	/* TSM timings initializations for Gen3 radio */
AnnaBridge	172:65be27845400	81	/* NOTE: These timings are stored in 32MHz or 26MHz "baseline" settings, selected by conditional compile below */
AnnaBridge	172:65be27845400	82	/* The init structures for 32Mhz and 26MHz are made identical to allow the same code in fsl_xcvr.c to apply the */
AnnaBridge	172:65be27845400	83	/* settings for all radio generations. The Gen2 radio init value storage had a different structure so this preserves compatibility */
AnnaBridge	172:65be27845400	84	#if RF_OSC_26MHZ == 1
AnnaBridge	172:65be27845400	85	#define TSM_TIMING00init (0x6d006f00U) /* (bb_ldo_hf_en) */
AnnaBridge	172:65be27845400	86	#define TSM_TIMING01init (0x6d006f00U) /* (bb_ldo_adcdac_en) */
AnnaBridge	172:65be27845400	87	#define TSM_TIMING02init (0x6d00ffffU) /* (bb_ldo_bba_en) */
AnnaBridge	172:65be27845400	88	#define TSM_TIMING03init (0x6d006f00U) /* (bb_ldo_pd_en) */
AnnaBridge	172:65be27845400	89	#define TSM_TIMING04init (0x6d006f00U) /* (bb_ldo_fdbk_en) */
AnnaBridge	172:65be27845400	90	#define TSM_TIMING05init (0x6d006f00U) /* (bb_ldo_vcolo_en) */
AnnaBridge	172:65be27845400	91	#define TSM_TIMING06init (0x6d006f00U) /* (bb_ldo_vtref_en) */
AnnaBridge	172:65be27845400	92	#define TSM_TIMING07init (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */
AnnaBridge	172:65be27845400	93	#define TSM_TIMING08init (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */
AnnaBridge	172:65be27845400	94	#define TSM_TIMING09init (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */
AnnaBridge	172:65be27845400	95	#define TSM_TIMING10init (0x6d036f03U) /* (bb_xtal_pll_ref_clk_en) */
AnnaBridge	172:65be27845400	96	#define TSM_TIMING11init (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */
AnnaBridge	172:65be27845400	97	#define TSM_TIMING12init (0x6d03ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */
AnnaBridge	172:65be27845400	98	#define TSM_TIMING13init (0x18004c00U) /* (sy_vco_autotune_en) */
AnnaBridge	172:65be27845400	99	#define TSM_TIMING14init (0x6d356863U) /* (sy_pd_cycle_slip_ld_ft_en) */
AnnaBridge	172:65be27845400	100	#define TSM_TIMING15init (0x6d036f03U) /* (sy_vco_en) */
AnnaBridge	172:65be27845400	101	#define TSM_TIMING16init (0x6d20ffffU) /* (sy_lo_rx_buf_en) */
AnnaBridge	172:65be27845400	102	#define TSM_TIMING17init (0xffff6f58U) /* (sy_lo_tx_buf_en) */
AnnaBridge	172:65be27845400	103	#define TSM_TIMING18init (0x6d056f05U) /* (sy_divn_en) */
AnnaBridge	172:65be27845400	104	#define TSM_TIMING19init (0x18034c03U) /* (sy_pd_filter_charge_en) */
AnnaBridge	172:65be27845400	105	#define TSM_TIMING20init (0x6d036f03U) /* (sy_pd_en) */
AnnaBridge	172:65be27845400	106	#define TSM_TIMING21init (0x6d046f04U) /* (sy_lo_divn_en) */
AnnaBridge	172:65be27845400	107	#define TSM_TIMING22init (0x6d04ffffU) /* (sy_lo_rx_en) */
AnnaBridge	172:65be27845400	108	#define TSM_TIMING23init (0xffff6f04U) /* (sy_lo_tx_en) */
AnnaBridge	172:65be27845400	109	#define TSM_TIMING24init (0x18004c00U) /* (sy_divn_cal_en) */
AnnaBridge	172:65be27845400	110	#define TSM_TIMING25init (0x6d21ffffU) /* (rx_lna_mixer_en) */
AnnaBridge	172:65be27845400	111	#define TSM_TIMING26init (0xffff6e58U) /* (tx_pa_en) */
AnnaBridge	172:65be27845400	112	#define TSM_TIMING27init (0x6d24ffffU) /* (rx_adc_i_q_en) */
AnnaBridge	172:65be27845400	113	#define TSM_TIMING28init (0x2524ffffU) /* (rx_adc_reset_en) */
AnnaBridge	172:65be27845400	114	#define TSM_TIMING29init (0x6d22ffffU) /* (rx_bba_i_q_en) */
AnnaBridge	172:65be27845400	115	#define TSM_TIMING30init (0x6d24ffffU) /* (rx_bba_pdet_en) */
AnnaBridge	172:65be27845400	116	#define TSM_TIMING31init (0x6d23ffffU) /* (rx_bba_tza_dcoc_en) */
AnnaBridge	172:65be27845400	117	#define TSM_TIMING32init (0x6d21ffffU) /* (rx_tza_i_q_en) */
AnnaBridge	172:65be27845400	118	#define TSM_TIMING33init (0x6d24ffffU) /* (rx_tza_pdet_en) */
AnnaBridge	172:65be27845400	119	#define TSM_TIMING34init (0x6d076f07U) /* (pll_dig_en) */
AnnaBridge	172:65be27845400	120	#define TSM_TIMING35init (0xffff6f5fU) /* (tx_dig_en) */
AnnaBridge	172:65be27845400	121	#define TSM_TIMING36init (0x6d6affffU) /* (rx_dig_en) */
AnnaBridge	172:65be27845400	122	#define TSM_TIMING37init (0x6b6affffU) /* (rx_init) */
AnnaBridge	172:65be27845400	123	#define TSM_TIMING38init (0x6d0e6f42U) /* (sigma_delta_en) */
AnnaBridge	172:65be27845400	124	#define TSM_TIMING39init (0x6d6affffU) /* (rx_phy_en) */
AnnaBridge	172:65be27845400	125	#define TSM_TIMING40init (0x6d2affffU) /* (dcoc_en) */
AnnaBridge	172:65be27845400	126	#define TSM_TIMING41init (0x2b2affffU) /* (dcoc_init) */
AnnaBridge	172:65be27845400	127	#define TSM_TIMING42init (0xffffffffU) /* (sar_adc_trig_en) */
AnnaBridge	172:65be27845400	128	#define TSM_TIMING43init (0xffffffffU) /* (tsm_spare0_en) */
AnnaBridge	172:65be27845400	129	#define TSM_TIMING44init (0xffffffffU) /* (tsm_spare1_en) */
AnnaBridge	172:65be27845400	130	#define TSM_TIMING45init (0xffffffffU) /* (tsm_spare2_en) */
AnnaBridge	172:65be27845400	131	#define TSM_TIMING46init (0xffffffffU) /* (tsm_spare3_en) */
AnnaBridge	172:65be27845400	132	#define TSM_TIMING47init (0xffffffffU) /* (gpio0_trig_en) */
AnnaBridge	172:65be27845400	133	#define TSM_TIMING48init (0xffffffffU) /* (gpio1_trig_en) */
AnnaBridge	172:65be27845400	134	#define TSM_TIMING49init (0xffffffffU) /* (gpio2_trig_en) */
AnnaBridge	172:65be27845400	135	#define TSM_TIMING50init (0xffffffffU) /* (gpio3_trig_en) */
AnnaBridge	172:65be27845400	136	#define TSM_TIMING51init (0x6d03ffffU) /* (rxtx_auxpll_bias_en) */
AnnaBridge	172:65be27845400	137	#define TSM_TIMING52init (0x1b06ffffU) /* (rxtx_auxpll_fcal_en) */
AnnaBridge	172:65be27845400	138	#define TSM_TIMING53init (0x6d03ffffU) /* (rxtx_auxpll_lf_pd_en) */
AnnaBridge	172:65be27845400	139	#define TSM_TIMING54init (0x1b03ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */
AnnaBridge	172:65be27845400	140	#define TSM_TIMING55init (0x6d24ffffU) /* (rxtx_auxpll_adc_buf_en) */
AnnaBridge	172:65be27845400	141	#define TSM_TIMING56init (0x6d24ffffU) /* (rxtx_auxpll_dig_buf_en) */
AnnaBridge	172:65be27845400	142	#define TSM_TIMING57init (0x1a03ffffU) /* (rxtx_rccal_en) */
AnnaBridge	172:65be27845400	143	#define TSM_TIMING58init (0xffff6f03U) /* (tx_hpm_dac_en) */
AnnaBridge	172:65be27845400	144	#define END_OF_SEQinit (0x6d6c6f67U) /* */
AnnaBridge	172:65be27845400	145	#define TX_RX_ON_DELinit (0x00008a86U) /* */
AnnaBridge	172:65be27845400	146	#define TX_RX_SYNTH_init (0x00002318U) /* */
AnnaBridge	172:65be27845400	147	#else
AnnaBridge	172:65be27845400	148	#define TSM_TIMING00init (0x69006f00U) /* (bb_ldo_hf_en) */
AnnaBridge	172:65be27845400	149	#define TSM_TIMING01init (0x69006f00U) /* (bb_ldo_adcdac_en) */
AnnaBridge	172:65be27845400	150	#define TSM_TIMING02init (0x6900ffffU) /* (bb_ldo_bba_en) */
AnnaBridge	172:65be27845400	151	#define TSM_TIMING03init (0x69006f00U) /* (bb_ldo_pd_en) */
AnnaBridge	172:65be27845400	152	#define TSM_TIMING04init (0x69006f00U) /* (bb_ldo_fdbk_en) */
AnnaBridge	172:65be27845400	153	#define TSM_TIMING05init (0x69006f00U) /* (bb_ldo_vcolo_en) */
AnnaBridge	172:65be27845400	154	#define TSM_TIMING06init (0x69006f00U) /* (bb_ldo_vtref_en) */
AnnaBridge	172:65be27845400	155	#define TSM_TIMING07init (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */
AnnaBridge	172:65be27845400	156	#define TSM_TIMING08init (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */
AnnaBridge	172:65be27845400	157	#define TSM_TIMING09init (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */
AnnaBridge	172:65be27845400	158	#define TSM_TIMING10init (0x69036f03U) /* (bb_xtal_pll_ref_clk_en) */
AnnaBridge	172:65be27845400	159	#define TSM_TIMING11init (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */
AnnaBridge	172:65be27845400	160	#define TSM_TIMING12init (0x6903ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */
AnnaBridge	172:65be27845400	161	#define TSM_TIMING13init (0x18004c00U) /* (sy_vco_autotune_en) */
AnnaBridge	172:65be27845400	162	#define TSM_TIMING14init (0x69316863U) /* (sy_pd_cycle_slip_ld_ft_en) */
AnnaBridge	172:65be27845400	163	#define TSM_TIMING15init (0x69036f03U) /* (sy_vco_en) */
AnnaBridge	172:65be27845400	164	#define TSM_TIMING16init (0x691cffffU) /* (sy_lo_rx_buf_en) */
AnnaBridge	172:65be27845400	165	#define TSM_TIMING17init (0xffff6f58U) /* (sy_lo_tx_buf_en) */
AnnaBridge	172:65be27845400	166	#define TSM_TIMING18init (0x69056f05U) /* (sy_divn_en) */
AnnaBridge	172:65be27845400	167	#define TSM_TIMING19init (0x18034c03U) /* (sy_pd_filter_charge_en) */
AnnaBridge	172:65be27845400	168	#define TSM_TIMING20init (0x69036f03U) /* (sy_pd_en) */
AnnaBridge	172:65be27845400	169	#define TSM_TIMING21init (0x69046f04U) /* (sy_lo_divn_en) */
AnnaBridge	172:65be27845400	170	#define TSM_TIMING22init (0x6904ffffU) /* (sy_lo_rx_en) */
AnnaBridge	172:65be27845400	171	#define TSM_TIMING23init (0xffff6f04U) /* (sy_lo_tx_en) */
AnnaBridge	172:65be27845400	172	#define TSM_TIMING24init (0x18004c00U) /* (sy_divn_cal_en) */
AnnaBridge	172:65be27845400	173	#define TSM_TIMING25init (0x691dffffU) /* (rx_lna_mixer_en) */
AnnaBridge	172:65be27845400	174	#define TSM_TIMING26init (0xffff6e58U) /* (tx_pa_en) */
AnnaBridge	172:65be27845400	175	#define TSM_TIMING27init (0x6920ffffU) /* (rx_adc_i_q_en) */
AnnaBridge	172:65be27845400	176	#define TSM_TIMING28init (0x2120ffffU) /* (rx_adc_reset_en) */
AnnaBridge	172:65be27845400	177	#define TSM_TIMING29init (0x691effffU) /* (rx_bba_i_q_en) */
AnnaBridge	172:65be27845400	178	#define TSM_TIMING30init (0x6920ffffU) /* (rx_bba_pdet_en) */
AnnaBridge	172:65be27845400	179	#define TSM_TIMING31init (0x691fffffU) /* (rx_bba_tza_dcoc_en) */
AnnaBridge	172:65be27845400	180	#define TSM_TIMING32init (0x691dffffU) /* (rx_tza_i_q_en) */
AnnaBridge	172:65be27845400	181	#define TSM_TIMING33init (0x6920ffffU) /* (rx_tza_pdet_en) */
AnnaBridge	172:65be27845400	182	#define TSM_TIMING34init (0x69076f07U) /* (pll_dig_en) */
AnnaBridge	172:65be27845400	183	#define TSM_TIMING35init (0xffff6f5fU) /* (tx_dig_en) */
AnnaBridge	172:65be27845400	184	#define TSM_TIMING36init (0x6966ffffU) /* (rx_dig_en) */
AnnaBridge	172:65be27845400	185	#define TSM_TIMING37init (0x6766ffffU) /* (rx_init) */
AnnaBridge	172:65be27845400	186	#define TSM_TIMING38init (0x690e6f42U) /* (sigma_delta_en) */
AnnaBridge	172:65be27845400	187	#define TSM_TIMING39init (0x6966ffffU) /* (rx_phy_en) */
AnnaBridge	172:65be27845400	188	#define TSM_TIMING40init (0x6926ffffU) /* (dcoc_en) */
AnnaBridge	172:65be27845400	189	#define TSM_TIMING41init (0x2726ffffU) /* (dcoc_init) */
AnnaBridge	172:65be27845400	190	#define TSM_TIMING42init (0xffffffffU) /* (sar_adc_trig_en) */
AnnaBridge	172:65be27845400	191	#define TSM_TIMING43init (0xffffffffU) /* (tsm_spare0_en) */
AnnaBridge	172:65be27845400	192	#define TSM_TIMING44init (0xffffffffU) /* (tsm_spare1_en) */
AnnaBridge	172:65be27845400	193	#define TSM_TIMING45init (0xffffffffU) /* (tsm_spare2_en) */
AnnaBridge	172:65be27845400	194	#define TSM_TIMING46init (0xffffffffU) /* (tsm_spare3_en) */
AnnaBridge	172:65be27845400	195	#define TSM_TIMING47init (0xffffffffU) /* (gpio0_trig_en) */
AnnaBridge	172:65be27845400	196	#define TSM_TIMING48init (0xffffffffU) /* (gpio1_trig_en) */
AnnaBridge	172:65be27845400	197	#define TSM_TIMING49init (0xffffffffU) /* (gpio2_trig_en) */
AnnaBridge	172:65be27845400	198	#define TSM_TIMING50init (0xffffffffU) /* (gpio3_trig_en) */
AnnaBridge	172:65be27845400	199	#define TSM_TIMING51init (0x6903ffffU) /* (rxtx_auxpll_bias_en) */
AnnaBridge	172:65be27845400	200	#define TSM_TIMING52init (0x1706ffffU) /* (rxtx_auxpll_fcal_en) */
AnnaBridge	172:65be27845400	201	#define TSM_TIMING53init (0x6903ffffU) /* (rxtx_auxpll_lf_pd_en) */
AnnaBridge	172:65be27845400	202	#define TSM_TIMING54init (0x1703ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */
AnnaBridge	172:65be27845400	203	#define TSM_TIMING55init (0x6920ffffU) /* (rxtx_auxpll_adc_buf_en) */
AnnaBridge	172:65be27845400	204	#define TSM_TIMING56init (0x6920ffffU) /* (rxtx_auxpll_dig_buf_en) */
AnnaBridge	172:65be27845400	205	#define TSM_TIMING57init (0x1a03ffffU) /* (rxtx_rccal_en) */
AnnaBridge	172:65be27845400	206	#define TSM_TIMING58init (0xffff6f03U) /* (tx_hpm_dac_en) */
AnnaBridge	172:65be27845400	207	#define END_OF_SEQinit (0x69686f67U) /* */
AnnaBridge	172:65be27845400	208	#define TX_RX_ON_DELinit (0x00008a86U) /* */
AnnaBridge	172:65be27845400	209	#define TX_RX_SYNTH_init (0x00002318U) /* */
AnnaBridge	172:65be27845400	210	#endif /* RF_OSC_26MHZ == 1 */
AnnaBridge	172:65be27845400	211
AnnaBridge	172:65be27845400	212	#define AUX_PLL_DELAY (0)
AnnaBridge	172:65be27845400	213	/* TSM bitfield shift and value definitions */
AnnaBridge	172:65be27845400	214	#define TX_DIG_EN_ASSERT (95) /* Assertion time for TX_DIG_EN, used in mode specific settings */
AnnaBridge	172:65be27845400	215	#define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */
AnnaBridge	172:65be27845400	216	/* EDIT THIS LINE TO CONTROL PA_RAMP! */
AnnaBridge	172:65be27845400	217	#define PA_RAMP_TIME (2) /* Only allowable values are [0, 1, 2, or 4] in Gen3 */
AnnaBridge	172:65be27845400	218	#define PA_RAMP_SEL_0US (0)
AnnaBridge	172:65be27845400	219	#define PA_RAMP_SEL_1US (1)
AnnaBridge	172:65be27845400	220	#define PA_RAMP_SEL_2US (2)
AnnaBridge	172:65be27845400	221	#define PA_RAMP_SEL_4US (3)
AnnaBridge	172:65be27845400	222	#if !((PA_RAMP_TIME == 0) \|\| (PA_RAMP_TIME == 1) \|\| (PA_RAMP_TIME == 2) \|\| (PA_RAMP_TIME == 4))
AnnaBridge	172:65be27845400	223	#error "Invalid value for PA_RAMP_TIME macro"
AnnaBridge	172:65be27845400	224	#endif /* Error check of PA RAMP TIME */
AnnaBridge	172:65be27845400	225
AnnaBridge	172:65be27845400	226	#define ADD_FOR_26MHZ (4)
AnnaBridge	172:65be27845400	227	#define END_OF_TX_WU_NORAMP (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */
AnnaBridge	172:65be27845400	228	#define END_OF_TX_WD_NORAMP (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */
AnnaBridge	172:65be27845400	229	/* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */
AnnaBridge	172:65be27845400	230	/* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */
AnnaBridge	172:65be27845400	231	#if ((PA_RAMP_TIME == 0) \|\| (PA_RAMP_TIME == 1) \|\| (PA_RAMP_TIME == 2))
AnnaBridge	172:65be27845400	232	#define END_OF_TX_WU (END_OF_TX_WU_NORAMP)
AnnaBridge	172:65be27845400	233	#define END_OF_TX_WD (END_OF_TX_WD_NORAMP)
AnnaBridge	172:65be27845400	234	#if (PA_RAMP_TIME == 0)
AnnaBridge	172:65be27845400	235	#define PA_RAMP_SEL PA_RAMP_SEL_0US
AnnaBridge	172:65be27845400	236	#define DATA_PADDING_EN (0)
AnnaBridge	172:65be27845400	237	#else
AnnaBridge	172:65be27845400	238	#define DATA_PADDING_EN (1)
AnnaBridge	172:65be27845400	239	#if (PA_RAMP_TIME == 1)
AnnaBridge	172:65be27845400	240	#define PA_RAMP_SEL PA_RAMP_SEL_1US
AnnaBridge	172:65be27845400	241	#else
AnnaBridge	172:65be27845400	242	#define PA_RAMP_SEL PA_RAMP_SEL_2US
AnnaBridge	172:65be27845400	243	#endif /* (PA_RAMP_TIME == 1) */
AnnaBridge	172:65be27845400	244	#endif /* (PA_RAMP_TIME == 0) */
AnnaBridge	172:65be27845400	245	#else /* ((PA_RAMP_TIME == 0) \|\| (PA_RAMP_TIME == 1) \|\| (PA_RAMP_TIME == 2)) */
AnnaBridge	172:65be27845400	246	#if (PA_RAMP_TIME == 4)
AnnaBridge	172:65be27845400	247	#define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 2)
AnnaBridge	172:65be27845400	248	#define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 4)
AnnaBridge	172:65be27845400	249	#define PA_RAMP_SEL PA_RAMP_SEL_4US
AnnaBridge	172:65be27845400	250	#define DATA_PADDING_EN (1)
AnnaBridge	172:65be27845400	251	#else /* (PA_RAMP_TIME == 4) */
AnnaBridge	172:65be27845400	252	#error "Invalid value for PA_RAMP_TIME macro"
AnnaBridge	172:65be27845400	253	#endif /* (PA_RAMP_TIME == 4) */
AnnaBridge	172:65be27845400	254	#endif/* (PA_RAMP_TIME == 4) */
AnnaBridge	172:65be27845400	255
AnnaBridge	172:65be27845400	256	#define END_OF_RX_WU (104 + AUX_PLL_DELAY)
AnnaBridge	172:65be27845400	257
AnnaBridge	172:65be27845400	258	#if RF_OSC_26MHZ == 1
AnnaBridge	172:65be27845400	259	#define END_OF_RX_WD (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */
AnnaBridge	172:65be27845400	260	#else
AnnaBridge	172:65be27845400	261	#define END_OF_RX_WD (END_OF_RX_WU + 1)
AnnaBridge	172:65be27845400	262	#endif /* RF_OSC_26MHZ == 1 */
AnnaBridge	172:65be27845400	263
AnnaBridge	172:65be27845400	264	#define END_OF_RX_WU_26MHZ (END_OF_RX_WU + ADD_FOR_26MHZ)
AnnaBridge	172:65be27845400	265	#define END_OF_RX_WD_26MHZ (END_OF_RX_WU + 1 + ADD_FOR_26MHZ)
AnnaBridge	172:65be27845400	266
AnnaBridge	172:65be27845400	267	/* PA Bias Table - Gen3 version */
AnnaBridge	172:65be27845400	268	#define PA_RAMP_0 0x1
AnnaBridge	172:65be27845400	269	#define PA_RAMP_1 0x2
AnnaBridge	172:65be27845400	270	#define PA_RAMP_2 0x4
AnnaBridge	172:65be27845400	271	#define PA_RAMP_3 0x6
AnnaBridge	172:65be27845400	272	#define PA_RAMP_4 0x8
AnnaBridge	172:65be27845400	273	#define PA_RAMP_5 0xc
AnnaBridge	172:65be27845400	274	#define PA_RAMP_6 0x10
AnnaBridge	172:65be27845400	275	#define PA_RAMP_7 0x14
AnnaBridge	172:65be27845400	276	#define PA_RAMP_8 0x18
AnnaBridge	172:65be27845400	277	#define PA_RAMP_9 0x1c
AnnaBridge	172:65be27845400	278	#define PA_RAMP_10 0x22
AnnaBridge	172:65be27845400	279	#define PA_RAMP_11 0x28
AnnaBridge	172:65be27845400	280	#define PA_RAMP_12 0x2c
AnnaBridge	172:65be27845400	281	#define PA_RAMP_13 0x30
AnnaBridge	172:65be27845400	282	#define PA_RAMP_14 0x36
AnnaBridge	172:65be27845400	283	#define PA_RAMP_15 0x3c
AnnaBridge	172:65be27845400	284
AnnaBridge	172:65be27845400	285	#else /* Gen2 TSM definitions */
AnnaBridge	172:65be27845400	286	/* GEN2 TSM defines */
AnnaBridge	172:65be27845400	287	#define AUX_PLL_DELAY (0)
AnnaBridge	172:65be27845400	288	/* TSM bitfield shift and value definitions */
AnnaBridge	172:65be27845400	289	#define TX_DIG_EN_ASSERT (95)
AnnaBridge	172:65be27845400	290	#define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */
AnnaBridge	172:65be27845400	291	/* EDIT THIS LINE TO CONTROL PA_RAMP! */
AnnaBridge	172:65be27845400	292	#define PA_RAMP_TIME (2) /* Only allowable values are [0, 2, 4, or 8] for PA RAMP times in Gen2.0 */
AnnaBridge	172:65be27845400	293	#define PA_RAMP_SEL_0US (0)
AnnaBridge	172:65be27845400	294	#define PA_RAMP_SEL_2US (1)
AnnaBridge	172:65be27845400	295	#define PA_RAMP_SEL_4US (2)
AnnaBridge	172:65be27845400	296	#define PA_RAMP_SEL_8US (3)
AnnaBridge	172:65be27845400	297
AnnaBridge	172:65be27845400	298	#if !((PA_RAMP_TIME == 0) \|\| (PA_RAMP_TIME == 2) \|\| (PA_RAMP_TIME == 4) \|\| (PA_RAMP_TIME == 8))
AnnaBridge	172:65be27845400	299	#error "Invalid value for PA_RAMP_TIME macro"
AnnaBridge	172:65be27845400	300	#endif /* Error check of PA RAMP TIME */
AnnaBridge	172:65be27845400	301	#define ADD_FOR_26MHZ (4)
AnnaBridge	172:65be27845400	302	#define END_OF_TX_WU_NORAMP (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */
AnnaBridge	172:65be27845400	303	#define END_OF_TX_WD_NORAMP (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */
AnnaBridge	172:65be27845400	304	/* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */
AnnaBridge	172:65be27845400	305	/* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */
AnnaBridge	172:65be27845400	306	#if ((PA_RAMP_TIME == 0) \|\| (PA_RAMP_TIME == 2))
AnnaBridge	172:65be27845400	307	#define END_OF_TX_WU (END_OF_TX_WU_NORAMP)
AnnaBridge	172:65be27845400	308	#define END_OF_TX_WD (END_OF_TX_WD_NORAMP)
AnnaBridge	172:65be27845400	309	#define TX_SYNTH_DELAY_ADJ (0)
AnnaBridge	172:65be27845400	310	#define PD_CYCLE_SLIP_TX_HI_ADJ (0)
AnnaBridge	172:65be27845400	311	#define PD_CYCLE_SLIP_TX_LO_ADJ (1)
AnnaBridge	172:65be27845400	312	#define ZGBE_TX_DIG_EN_TX_HI_ADJ (-5) /* Only applies to Zigbee mode */
AnnaBridge	172:65be27845400	313	#if (PA_RAMP_TIME == 0)
AnnaBridge	172:65be27845400	314	#define PA_RAMP_SEL PA_RAMP_SEL_0US
AnnaBridge	172:65be27845400	315	#define DATA_PADDING_EN (0)
AnnaBridge	172:65be27845400	316	#define TX_DIG_EN_TX_HI_ADJ (-2)
AnnaBridge	172:65be27845400	317	#else
AnnaBridge	172:65be27845400	318	#define DATA_PADDING_EN (1)
AnnaBridge	172:65be27845400	319	#define TX_DIG_EN_TX_HI_ADJ (0)
AnnaBridge	172:65be27845400	320	#define PA_RAMP_SEL PA_RAMP_SEL_2US
AnnaBridge	172:65be27845400	321	#endif /* (PA_RAMP_TIME == 0) */
AnnaBridge	172:65be27845400	322	#else /* ((PA_RAMP_TIME == 0) \|\| (PA_RAMP_TIME == 2)) */
AnnaBridge	172:65be27845400	323	#if (PA_RAMP_TIME == 4)
AnnaBridge	172:65be27845400	324	#define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 2)
AnnaBridge	172:65be27845400	325	#define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 4)
AnnaBridge	172:65be27845400	326	#define TX_SYNTH_DELAY_ADJ (2)
AnnaBridge	172:65be27845400	327	#define PD_CYCLE_SLIP_TX_HI_ADJ (2)
AnnaBridge	172:65be27845400	328	#define PD_CYCLE_SLIP_TX_LO_ADJ (1)
AnnaBridge	172:65be27845400	329	#define TX_DIG_EN_TX_HI_ADJ (0)
AnnaBridge	172:65be27845400	330	#define ZGBE_TX_DIG_EN_TX_HI_ADJ (-3) /* Only applies to Zigbee mode */
AnnaBridge	172:65be27845400	331	#define PA_RAMP_SEL PA_RAMP_SEL_4US
AnnaBridge	172:65be27845400	332	#define DATA_PADDING_EN (1)
AnnaBridge	172:65be27845400	333	#else /* (PA_RAMP_TIME==4) */
AnnaBridge	172:65be27845400	334	#if ((PA_RAMP_TIME == 8) && (!RADIO_IS_GEN_3P0))
AnnaBridge	172:65be27845400	335	#define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 6)
AnnaBridge	172:65be27845400	336	#define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 12)
AnnaBridge	172:65be27845400	337	#define TX_SYNTH_DELAY_ADJ (6)
AnnaBridge	172:65be27845400	338	#define PD_CYCLE_SLIP_TX_HI_ADJ (6)
AnnaBridge	172:65be27845400	339	#define PD_CYCLE_SLIP_TX_LO_ADJ (1)
AnnaBridge	172:65be27845400	340	#define TX_DIG_EN_TX_HI_ADJ (4)
AnnaBridge	172:65be27845400	341	#define ZGBE_TX_DIG_EN_TX_HI_ADJ (1) /* Only applies to Zigbee mode */
AnnaBridge	172:65be27845400	342	#define PA_RAMP_SEL PA_RAMP_SEL_8US
AnnaBridge	172:65be27845400	343	#define DATA_PADDING_EN (1)
AnnaBridge	172:65be27845400	344	#else /* (PA_RAMP_TIME == 8) */
AnnaBridge	172:65be27845400	345	#error "Invalid value for PA_RAMP_TIME macro"
AnnaBridge	172:65be27845400	346	#endif /* (PA_RAMP_TIME == 8) */
AnnaBridge	172:65be27845400	347	#endif/* (PA_RAMP_TIME == 4) */
AnnaBridge	172:65be27845400	348	#endif /* ((PA_RAMP_TIME == 0) \|\| (PA_RAMP_TIME == 2)) */
AnnaBridge	172:65be27845400	349
AnnaBridge	172:65be27845400	350	#define TX_DIG_EN_ASSERT_MSK500 (END_OF_TX_WU - 3)
AnnaBridge	172:65be27845400	351
AnnaBridge	172:65be27845400	352	#define END_OF_RX_WU (104 + AUX_PLL_DELAY)
AnnaBridge	172:65be27845400	353	#if RF_OSC_26MHZ == 1
AnnaBridge	172:65be27845400	354	#define END_OF_RX_WD (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */
AnnaBridge	172:65be27845400	355	#else
AnnaBridge	172:65be27845400	356	#define END_OF_RX_WD (END_OF_RX_WU + 1)
AnnaBridge	172:65be27845400	357	#endif /* RF_OSC_26MHZ == 1 */
AnnaBridge	172:65be27845400	358	#define END_OF_RX_WU_26MHZ (END_OF_RX_WU + ADD_FOR_26MHZ)
AnnaBridge	172:65be27845400	359	#define END_OF_RX_WD_26MHZ (END_OF_RX_WU + 1 + ADD_FOR_26MHZ)
AnnaBridge	172:65be27845400	360
AnnaBridge	172:65be27845400	361	/* PA Bias Table */
AnnaBridge	172:65be27845400	362	#define PA_RAMP_0 0x1
AnnaBridge	172:65be27845400	363	#define PA_RAMP_1 0x2
AnnaBridge	172:65be27845400	364	#define PA_RAMP_2 0x4
AnnaBridge	172:65be27845400	365	#define PA_RAMP_3 0x8
AnnaBridge	172:65be27845400	366	#define PA_RAMP_4 0xe
AnnaBridge	172:65be27845400	367	#define PA_RAMP_5 0x16
AnnaBridge	172:65be27845400	368	#define PA_RAMP_6 0x22
AnnaBridge	172:65be27845400	369	#define PA_RAMP_7 0x2e
AnnaBridge	172:65be27845400	370
AnnaBridge	172:65be27845400	371	/* BLE LL timing definitions */
AnnaBridge	172:65be27845400	372	#define TX_ON_DELAY (0x85) /* Adjusted TX_ON_DELAY to make turnaround time 150usec */
AnnaBridge	172:65be27845400	373	#define RX_ON_DELAY (29 + END_OF_RX_WU)
AnnaBridge	172:65be27845400	374	#define RX_ON_DELAY_26MHZ (29 + END_OF_RX_WU_26MHZ)
AnnaBridge	172:65be27845400	375	#define TX_RX_ON_DELAY_VAL (TX_ON_DELAY << 8 \| RX_ON_DELAY)
AnnaBridge	172:65be27845400	376	#define TX_RX_ON_DELAY_VAL_26MHZ (TX_ON_DELAY << 8 \| RX_ON_DELAY_26MHZ)
AnnaBridge	172:65be27845400	377	#define TX_SYNTH_DELAY (TX_ON_DELAY - END_OF_TX_WU - TX_SYNTH_DELAY_ADJ) /* Adjustment to TX_SYNTH_DELAY due to DATA_PADDING */
AnnaBridge	172:65be27845400	378	#define RX_SYNTH_DELAY (0x18)
AnnaBridge	172:65be27845400	379	#define TX_RX_SYNTH_DELAY_VAL (TX_SYNTH_DELAY << 8 \| RX_SYNTH_DELAY)
AnnaBridge	172:65be27845400	380
AnnaBridge	172:65be27845400	381	/* PHY reference waveform assembly */
AnnaBridge	172:65be27845400	382	#define RW0PS(loc, val) (((val) & 0x1F) << ((loc) * 5)) /* Ref Word 0 - loc is the phase info symbol number, val is the value of the phase info */
AnnaBridge	172:65be27845400	383	#define RW1PS(loc, val) (((val) & 0x1F) << (((loc) * 5) - 32)) /* Ref Word 1 - loc is the phase info symbol number, val is the value of the phase info */
AnnaBridge	172:65be27845400	384	#define RW2PS(loc, val) (((val) & 0x1F) << (((loc) * 5) - 64)) /* Ref Word 2 - loc is the phase info symbol number, val is the value of the phase info */
AnnaBridge	172:65be27845400	385	#endif /* RADIO_IS_GEN_3P0 */
AnnaBridge	172:65be27845400	386
AnnaBridge	172:65be27845400	387	/! @brief Error codes for the XCVR driver. /
AnnaBridge	172:65be27845400	388	typedef enum _xcvrStatus
AnnaBridge	172:65be27845400	389	{
AnnaBridge	172:65be27845400	390	gXcvrSuccess_c = 0,
AnnaBridge	172:65be27845400	391	gXcvrInvalidParameters_c,
AnnaBridge	172:65be27845400	392	gXcvrUnsupportedOperation_c,
AnnaBridge	172:65be27845400	393	gXcvrTrimFailure_c
AnnaBridge	172:65be27845400	394	} xcvrStatus_t;
AnnaBridge	172:65be27845400	395
AnnaBridge	172:65be27845400	396	/! @brief Health status returned from PHY upon status check function return. /
AnnaBridge	172:65be27845400	397	typedef enum _healthStatus
AnnaBridge	172:65be27845400	398	{
AnnaBridge	172:65be27845400	399	NO_ERRORS = 0,
AnnaBridge	172:65be27845400	400	PLL_CTUNE_FAIL = 1,
AnnaBridge	172:65be27845400	401	PLL_CYCLE_SLIP_FAIL = 2,
AnnaBridge	172:65be27845400	402	PLL_FREQ_TARG_FAIL = 4,
AnnaBridge	172:65be27845400	403	PLL_TSM_ABORT_FAIL = 8,
AnnaBridge	172:65be27845400	404	} healthStatus_t;
AnnaBridge	172:65be27845400	405
AnnaBridge	172:65be27845400	406	/! @brief Health status returned from PHY upon status check function return. /
AnnaBridge	172:65be27845400	407	typedef enum _ext_clock_config
AnnaBridge	172:65be27845400	408	{
AnnaBridge	172:65be27845400	409	EXT_CLK_32_MHZ = 0,
AnnaBridge	172:65be27845400	410	EXT_CLK_26_MHZ = 1,
AnnaBridge	172:65be27845400	411	} ext_clock_config_t;
AnnaBridge	172:65be27845400	412
AnnaBridge	172:65be27845400	413	/! @brief Radio operating mode setting types. /
AnnaBridge	172:65be27845400	414	typedef enum _radio_mode
AnnaBridge	172:65be27845400	415	{
AnnaBridge	172:65be27845400	416	BLE_MODE = 0,
AnnaBridge	172:65be27845400	417	ZIGBEE_MODE = 1,
AnnaBridge	172:65be27845400	418	ANT_MODE = 2,
AnnaBridge	172:65be27845400	419
AnnaBridge	172:65be27845400	420	/* BT=0.5, h=** */
AnnaBridge	172:65be27845400	421	GFSK_BT_0p5_h_0p5 = 3, /* < BT=0.5, h=0.5 [BLE at 1MBPS data rate; CS4 at 250KBPS data rate] */
AnnaBridge	172:65be27845400	422	GFSK_BT_0p5_h_0p32 = 4, /* < BT=0.5, h=0.32*/
AnnaBridge	172:65be27845400	423	GFSK_BT_0p5_h_0p7 = 5, /* < BT=0.5, h=0.7 [ CS1 at 500KBPS data rate] */
AnnaBridge	172:65be27845400	424	GFSK_BT_0p5_h_1p0 = 6, /* < BT=0.5, h=1.0 [ CS4 at 250KBPS data rate] */
AnnaBridge	172:65be27845400	425
AnnaBridge	172:65be27845400	426	/* BT=** h=0.5 */
AnnaBridge	172:65be27845400	427	GFSK_BT_0p3_h_0p5 = 7, /* < BT=0.3, h=0.5 [ CS2 at 1MBPS data rate] */
AnnaBridge	172:65be27845400	428	GFSK_BT_0p7_h_0p5 = 8, /* < BT=0.7, h=0.5 */
AnnaBridge	172:65be27845400	429
AnnaBridge	172:65be27845400	430	MSK = 9,
AnnaBridge	172:65be27845400	431	NUM_RADIO_MODES = 10,
AnnaBridge	172:65be27845400	432	} radio_mode_t;
AnnaBridge	172:65be27845400	433
AnnaBridge	172:65be27845400	434	/! @brief Link layer types. /
AnnaBridge	172:65be27845400	435	typedef enum _link_layer
AnnaBridge	172:65be27845400	436	{
AnnaBridge	172:65be27845400	437	BLE_LL = 0, /* Must match bit assignment in RADIO1_IRQ_SEL */
AnnaBridge	172:65be27845400	438	ZIGBEE_LL = 1, /* Must match bit assignment in RADIO1_IRQ_SEL */
AnnaBridge	172:65be27845400	439	ANT_LL = 2, /* Must match bit assignment in RADIO1_IRQ_SEL */
AnnaBridge	172:65be27845400	440	GENFSK_LL = 3, /* Must match bit assignment in RADIO1_IRQ_SEL */
AnnaBridge	172:65be27845400	441	UNASSIGNED_LL = 4, /* Must match bit assignment in RADIO1_IRQ_SEL */
AnnaBridge	172:65be27845400	442	} link_layer_t;
AnnaBridge	172:65be27845400	443
AnnaBridge	172:65be27845400	444	/! @brief Data rate selections. /
AnnaBridge	172:65be27845400	445	typedef enum _data_rate
AnnaBridge	172:65be27845400	446	{
AnnaBridge	172:65be27845400	447	DR_1MBPS = 0, /* Must match bit assignment in BITRATE field */
AnnaBridge	172:65be27845400	448	DR_500KBPS = 1, /* Must match bit assignment in BITRATE field */
AnnaBridge	172:65be27845400	449	DR_250KBPS = 2, /* Must match bit assignment in BITRATE field */
AnnaBridge	172:65be27845400	450	#if RADIO_IS_GEN_3P0
AnnaBridge	172:65be27845400	451	DR_2MBPS = 3, /* Must match bit assignment in BITRATE field */
AnnaBridge	172:65be27845400	452	#endif /* RADIO_IS_GEN_3P0 */
AnnaBridge	172:65be27845400	453	DR_UNASSIGNED = 4, /* Must match bit assignment in BITRATE field */
AnnaBridge	172:65be27845400	454	} data_rate_t;
AnnaBridge	172:65be27845400	455
AnnaBridge	172:65be27845400	456	/! @brief Control settings for Fast Antenna Diversity /
AnnaBridge	172:65be27845400	457	typedef enum _FAD_LPPS_CTRL
AnnaBridge	172:65be27845400	458	{
AnnaBridge	172:65be27845400	459	NONE = 0,
AnnaBridge	172:65be27845400	460	FAD_ENABLED = 1,
AnnaBridge	172:65be27845400	461	LPPS_ENABLED = 2
AnnaBridge	172:65be27845400	462	} FAD_LPPS_CTRL_T;
AnnaBridge	172:65be27845400	463
AnnaBridge	172:65be27845400	464	/! @brief XCVR XCVR Panic codes for indicating panic reason. /
AnnaBridge	172:65be27845400	465	typedef enum _XCVR_PANIC_ID
AnnaBridge	172:65be27845400	466	{
AnnaBridge	172:65be27845400	467	WRONG_RADIO_ID_DETECTED = 1,
AnnaBridge	172:65be27845400	468	CALIBRATION_INVALID = 2,
AnnaBridge	172:65be27845400	469	} XCVR_PANIC_ID_T;
AnnaBridge	172:65be27845400	470
AnnaBridge	172:65be27845400	471	/! @brief Initialization or mode change selection for config routine. /
AnnaBridge	172:65be27845400	472	typedef enum _XCVR_INIT_MODE_CHG
AnnaBridge	172:65be27845400	473	{
AnnaBridge	172:65be27845400	474	XCVR_MODE_CHANGE = 0,
AnnaBridge	172:65be27845400	475	XCVR_FIRST_INIT = 1,
AnnaBridge	172:65be27845400	476	} XCVR_INIT_MODE_CHG_T;
AnnaBridge	172:65be27845400	477
AnnaBridge	172:65be27845400	478	typedef enum _XCVR_COEX_PRIORITY
AnnaBridge	172:65be27845400	479	{
AnnaBridge	172:65be27845400	480	XCVR_COEX_LOW_PRIO = 0,
AnnaBridge	172:65be27845400	481	XCVR_COEX_HIGH_PRIO = 1
AnnaBridge	172:65be27845400	482	} XCVR_COEX_PRIORITY_T;
AnnaBridge	172:65be27845400	483
AnnaBridge	172:65be27845400	484	/! @brief Current configuration of the radio. /
AnnaBridge	172:65be27845400	485	typedef struct xcvr_currConfig_tag
AnnaBridge	172:65be27845400	486	{
AnnaBridge	172:65be27845400	487	radio_mode_t radio_mode;
AnnaBridge	172:65be27845400	488	data_rate_t data_rate;
AnnaBridge	172:65be27845400	489	} xcvr_currConfig_t;
AnnaBridge	172:65be27845400	490
AnnaBridge	172:65be27845400	491	/*!
AnnaBridge	172:65be27845400	492	* @brief XCVR RX_DIG channel filter coefficient storage
AnnaBridge	172:65be27845400	493	* Storage of the coefficients varies from 6 bits to 10 bits so all use int16_t for storage.
AnnaBridge	172:65be27845400	494	*/
AnnaBridge	172:65be27845400	495	typedef struct _xcvr_rx_chf_coeffs
AnnaBridge	172:65be27845400	496	{
AnnaBridge	172:65be27845400	497	uint16_t rx_chf_coef_0; /* < 6 bit two's complement stored in a uint16_t */
AnnaBridge	172:65be27845400	498	uint16_t rx_chf_coef_1; /* < 6 bit two's complement stored in a uint16_t */
AnnaBridge	172:65be27845400	499	uint16_t rx_chf_coef_2; /* < 7 bit two's complement stored in a uint16_t */
AnnaBridge	172:65be27845400	500	uint16_t rx_chf_coef_3; /* < 7 bit two's complement stored in a uint16_t */
AnnaBridge	172:65be27845400	501	uint16_t rx_chf_coef_4; /* < 7 bit two's complement stored in a uint16_t */
AnnaBridge	172:65be27845400	502	uint16_t rx_chf_coef_5; /* < 7 bit two's complement stored in a uint16_t */
AnnaBridge	172:65be27845400	503	uint16_t rx_chf_coef_6; /* < 8 bit two's complement stored in a uint16_t */
AnnaBridge	172:65be27845400	504	uint16_t rx_chf_coef_7; /* < 8 bit two's complement stored in a uint16_t */
AnnaBridge	172:65be27845400	505	uint16_t rx_chf_coef_8; /* < 9 bit two's complement stored in a uint16_t */
AnnaBridge	172:65be27845400	506	uint16_t rx_chf_coef_9; /* < 9 bit two's complement stored in a uint16_t */
AnnaBridge	172:65be27845400	507	uint16_t rx_chf_coef_10; /* < 10 bit two's complement stored in a uint16_t */
AnnaBridge	172:65be27845400	508	uint16_t rx_chf_coef_11; /* < 10 bit two's complement stored in a uint16_t */
AnnaBridge	172:65be27845400	509	} xcvr_rx_chf_coeffs_t;
AnnaBridge	172:65be27845400	510
AnnaBridge	172:65be27845400	511	/*!
AnnaBridge	172:65be27845400	512	* @brief XCVR masked init type for 32 bit registers
AnnaBridge	172:65be27845400	513	* Initialization uses the mask to clear selected fields of the register and then OR's in the init value. All init values must be in their proper field position.
AnnaBridge	172:65be27845400	514	*/
AnnaBridge	172:65be27845400	515	typedef struct _xcvr_masked_init_32
AnnaBridge	172:65be27845400	516	{
AnnaBridge	172:65be27845400	517	uint32_t mask;
AnnaBridge	172:65be27845400	518	uint32_t init;
AnnaBridge	172:65be27845400	519	} xcvr_masked_init_32_t;
AnnaBridge	172:65be27845400	520
AnnaBridge	172:65be27845400	521	/*!
AnnaBridge	172:65be27845400	522	* @brief XCVR common configure structure
AnnaBridge	172:65be27845400	523	*/
AnnaBridge	172:65be27845400	524	typedef struct _xcvr_common_config
AnnaBridge	172:65be27845400	525	{
AnnaBridge	172:65be27845400	526	/* XCVR_ANA configs */
AnnaBridge	172:65be27845400	527	xcvr_masked_init_32_t ana_sy_ctrl1;
AnnaBridge	172:65be27845400	528
AnnaBridge	172:65be27845400	529	/* XCVR_PLL_DIG configs */
AnnaBridge	172:65be27845400	530	uint32_t pll_hpm_bump;
AnnaBridge	172:65be27845400	531	uint32_t pll_mod_ctrl;
AnnaBridge	172:65be27845400	532	uint32_t pll_chan_map;
AnnaBridge	172:65be27845400	533	uint32_t pll_lock_detect;
AnnaBridge	172:65be27845400	534	uint32_t pll_hpm_ctrl;
AnnaBridge	172:65be27845400	535	#if !RADIO_IS_GEN_2P1
AnnaBridge	172:65be27845400	536	uint32_t pll_hpmcal_ctrl;
AnnaBridge	172:65be27845400	537	#endif /* !RADIO_IS_GEN_2P1 */
AnnaBridge	172:65be27845400	538	uint32_t pll_hpm_sdm_res;
AnnaBridge	172:65be27845400	539	uint32_t pll_lpm_ctrl;
AnnaBridge	172:65be27845400	540	uint32_t pll_lpm_sdm_ctrl1;
AnnaBridge	172:65be27845400	541	uint32_t pll_delay_match;
AnnaBridge	172:65be27845400	542	uint32_t pll_ctune_ctrl;
AnnaBridge	172:65be27845400	543
AnnaBridge	172:65be27845400	544	/* XCVR_RX_DIG configs */
AnnaBridge	172:65be27845400	545	uint32_t rx_dig_ctrl_init; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
AnnaBridge	172:65be27845400	546	uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */
AnnaBridge	172:65be27845400	547	uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */
AnnaBridge	172:65be27845400	548	uint32_t dcoc_ctrl_1_init;
AnnaBridge	172:65be27845400	549	uint32_t dcoc_cal_gain_init;
AnnaBridge	172:65be27845400	550	uint32_t dc_resid_ctrl_init; /* NOTE: This will be OR'd with datarate specific init for DCOC_RESID_CTRL to form complete register initialization */
AnnaBridge	172:65be27845400	551	uint32_t dcoc_cal_rcp_init;
AnnaBridge	172:65be27845400	552	uint32_t lna_gain_val_3_0;
AnnaBridge	172:65be27845400	553	uint32_t lna_gain_val_7_4;
AnnaBridge	172:65be27845400	554	uint32_t lna_gain_val_8;
AnnaBridge	172:65be27845400	555	uint32_t bba_res_tune_val_7_0;
AnnaBridge	172:65be27845400	556	uint32_t bba_res_tune_val_10_8;
AnnaBridge	172:65be27845400	557	uint32_t lna_gain_lin_val_2_0_init;
AnnaBridge	172:65be27845400	558	uint32_t lna_gain_lin_val_5_3_init;
AnnaBridge	172:65be27845400	559	uint32_t lna_gain_lin_val_8_6_init;
AnnaBridge	172:65be27845400	560	uint32_t lna_gain_lin_val_9_init;
AnnaBridge	172:65be27845400	561	uint32_t bba_res_tune_lin_val_3_0_init;
AnnaBridge	172:65be27845400	562	uint32_t bba_res_tune_lin_val_7_4_init;
AnnaBridge	172:65be27845400	563	uint32_t bba_res_tune_lin_val_10_8_init;
AnnaBridge	172:65be27845400	564	uint32_t dcoc_bba_step_init;
AnnaBridge	172:65be27845400	565	uint32_t dcoc_tza_step_00_init;
AnnaBridge	172:65be27845400	566	uint32_t dcoc_tza_step_01_init;
AnnaBridge	172:65be27845400	567	uint32_t dcoc_tza_step_02_init;
AnnaBridge	172:65be27845400	568	uint32_t dcoc_tza_step_03_init;
AnnaBridge	172:65be27845400	569	uint32_t dcoc_tza_step_04_init;
AnnaBridge	172:65be27845400	570	uint32_t dcoc_tza_step_05_init;
AnnaBridge	172:65be27845400	571	uint32_t dcoc_tza_step_06_init;
AnnaBridge	172:65be27845400	572	uint32_t dcoc_tza_step_07_init;
AnnaBridge	172:65be27845400	573	uint32_t dcoc_tza_step_08_init;
AnnaBridge	172:65be27845400	574	uint32_t dcoc_tza_step_09_init;
AnnaBridge	172:65be27845400	575	uint32_t dcoc_tza_step_10_init;
AnnaBridge	172:65be27845400	576	#if (RADIO_IS_GEN_3P0 \|\| RADIO_IS_GEN_2P1)
AnnaBridge	172:65be27845400	577	uint32_t dcoc_cal_fail_th_init;
AnnaBridge	172:65be27845400	578	uint32_t dcoc_cal_pass_th_init;
AnnaBridge	172:65be27845400	579	#endif /* (RADIO_IS_GEN_3P0 \|\| RADIO_IS_GEN_2P1) */
AnnaBridge	172:65be27845400	580	uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */
AnnaBridge	172:65be27845400	581	uint32_t agc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */
AnnaBridge	172:65be27845400	582	uint32_t agc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */
AnnaBridge	172:65be27845400	583	uint32_t agc_ctrl_3_init;
AnnaBridge	172:65be27845400	584	/* Other agc config inits moved to modeXdatarate config table */
AnnaBridge	172:65be27845400	585	uint32_t agc_gain_tbl_03_00_init;
AnnaBridge	172:65be27845400	586	uint32_t agc_gain_tbl_07_04_init;
AnnaBridge	172:65be27845400	587	uint32_t agc_gain_tbl_11_08_init;
AnnaBridge	172:65be27845400	588	uint32_t agc_gain_tbl_15_12_init;
AnnaBridge	172:65be27845400	589	uint32_t agc_gain_tbl_19_16_init;
AnnaBridge	172:65be27845400	590	uint32_t agc_gain_tbl_23_20_init;
AnnaBridge	172:65be27845400	591	uint32_t agc_gain_tbl_26_24_init;
AnnaBridge	172:65be27845400	592	uint32_t rssi_ctrl_0_init;
AnnaBridge	172:65be27845400	593	#if RADIO_IS_GEN_3P0
AnnaBridge	172:65be27845400	594	uint32_t rssi_ctrl_1_init;
AnnaBridge	172:65be27845400	595	#endif /* RADIO_IS_GEN_3P0 */
AnnaBridge	172:65be27845400	596	uint32_t cca_ed_lqi_ctrl_0_init;
AnnaBridge	172:65be27845400	597	uint32_t cca_ed_lqi_ctrl_1_init;
AnnaBridge	172:65be27845400	598
AnnaBridge	172:65be27845400	599	/* XCVR_TSM configs */
AnnaBridge	172:65be27845400	600	uint32_t tsm_ctrl;
AnnaBridge	172:65be27845400	601	uint32_t tsm_ovrd2_init;
AnnaBridge	172:65be27845400	602	uint32_t end_of_seq_init_26mhz;
AnnaBridge	172:65be27845400	603	uint32_t end_of_seq_init_32mhz;
AnnaBridge	172:65be27845400	604	#if !RADIO_IS_GEN_2P1
AnnaBridge	172:65be27845400	605	uint32_t lpps_ctrl_init;
AnnaBridge	172:65be27845400	606	#endif /* !RADIO_IS_GEN_2P1 */
AnnaBridge	172:65be27845400	607	uint32_t tsm_fast_ctrl2_init_26mhz;
AnnaBridge	172:65be27845400	608	uint32_t tsm_fast_ctrl2_init_32mhz;
AnnaBridge	172:65be27845400	609	uint32_t recycle_count_init_26mhz;
AnnaBridge	172:65be27845400	610	uint32_t recycle_count_init_32mhz;
AnnaBridge	172:65be27845400	611	uint32_t pa_ramp_tbl_0_init;
AnnaBridge	172:65be27845400	612	uint32_t pa_ramp_tbl_1_init;
AnnaBridge	172:65be27845400	613	#if RADIO_IS_GEN_3P0
AnnaBridge	172:65be27845400	614	uint32_t pa_ramp_tbl_2_init;
AnnaBridge	172:65be27845400	615	uint32_t pa_ramp_tbl_3_init;
AnnaBridge	172:65be27845400	616	#endif /* RADIO_IS_GEN_3P0 */
AnnaBridge	172:65be27845400	617	uint32_t tsm_timing_00_init;
AnnaBridge	172:65be27845400	618	uint32_t tsm_timing_01_init;
AnnaBridge	172:65be27845400	619	uint32_t tsm_timing_02_init;
AnnaBridge	172:65be27845400	620	uint32_t tsm_timing_03_init;
AnnaBridge	172:65be27845400	621	uint32_t tsm_timing_04_init;
AnnaBridge	172:65be27845400	622	uint32_t tsm_timing_05_init;
AnnaBridge	172:65be27845400	623	uint32_t tsm_timing_06_init;
AnnaBridge	172:65be27845400	624	uint32_t tsm_timing_07_init;
AnnaBridge	172:65be27845400	625	uint32_t tsm_timing_08_init;
AnnaBridge	172:65be27845400	626	uint32_t tsm_timing_09_init;
AnnaBridge	172:65be27845400	627	uint32_t tsm_timing_10_init;
AnnaBridge	172:65be27845400	628	uint32_t tsm_timing_11_init;
AnnaBridge	172:65be27845400	629	uint32_t tsm_timing_12_init;
AnnaBridge	172:65be27845400	630	uint32_t tsm_timing_13_init;
AnnaBridge	172:65be27845400	631	uint32_t tsm_timing_14_init_26mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */
AnnaBridge	172:65be27845400	632	uint32_t tsm_timing_14_init_32mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */
AnnaBridge	172:65be27845400	633	uint32_t tsm_timing_15_init;
AnnaBridge	172:65be27845400	634	uint32_t tsm_timing_16_init_26mhz;
AnnaBridge	172:65be27845400	635	uint32_t tsm_timing_16_init_32mhz;
AnnaBridge	172:65be27845400	636	uint32_t tsm_timing_17_init;
AnnaBridge	172:65be27845400	637	uint32_t tsm_timing_18_init;
AnnaBridge	172:65be27845400	638	uint32_t tsm_timing_19_init;
AnnaBridge	172:65be27845400	639	uint32_t tsm_timing_20_init;
AnnaBridge	172:65be27845400	640	uint32_t tsm_timing_21_init;
AnnaBridge	172:65be27845400	641	uint32_t tsm_timing_22_init;
AnnaBridge	172:65be27845400	642	uint32_t tsm_timing_23_init;
AnnaBridge	172:65be27845400	643	uint32_t tsm_timing_24_init;
AnnaBridge	172:65be27845400	644	uint32_t tsm_timing_25_init_26mhz;
AnnaBridge	172:65be27845400	645	uint32_t tsm_timing_25_init_32mhz;
AnnaBridge	172:65be27845400	646	uint32_t tsm_timing_26_init;
AnnaBridge	172:65be27845400	647	uint32_t tsm_timing_27_init_26mhz;
AnnaBridge	172:65be27845400	648	uint32_t tsm_timing_27_init_32mhz;
AnnaBridge	172:65be27845400	649	uint32_t tsm_timing_28_init_26mhz;
AnnaBridge	172:65be27845400	650	uint32_t tsm_timing_28_init_32mhz;
AnnaBridge	172:65be27845400	651	uint32_t tsm_timing_29_init_26mhz;
AnnaBridge	172:65be27845400	652	uint32_t tsm_timing_29_init_32mhz;
AnnaBridge	172:65be27845400	653	uint32_t tsm_timing_30_init_26mhz;
AnnaBridge	172:65be27845400	654	uint32_t tsm_timing_30_init_32mhz;
AnnaBridge	172:65be27845400	655	uint32_t tsm_timing_31_init_26mhz;
AnnaBridge	172:65be27845400	656	uint32_t tsm_timing_31_init_32mhz;
AnnaBridge	172:65be27845400	657	uint32_t tsm_timing_32_init_26mhz;
AnnaBridge	172:65be27845400	658	uint32_t tsm_timing_32_init_32mhz;
AnnaBridge	172:65be27845400	659	uint32_t tsm_timing_33_init_26mhz;
AnnaBridge	172:65be27845400	660	uint32_t tsm_timing_33_init_32mhz;
AnnaBridge	172:65be27845400	661	uint32_t tsm_timing_34_init;
AnnaBridge	172:65be27845400	662	uint32_t tsm_timing_35_init; /* tsm_timing_35 has a mode specific LSbyte*/
AnnaBridge	172:65be27845400	663	uint32_t tsm_timing_36_init_26mhz;
AnnaBridge	172:65be27845400	664	uint32_t tsm_timing_36_init_32mhz;
AnnaBridge	172:65be27845400	665	uint32_t tsm_timing_37_init_26mhz;
AnnaBridge	172:65be27845400	666	uint32_t tsm_timing_37_init_32mhz;
AnnaBridge	172:65be27845400	667	uint32_t tsm_timing_38_init;
AnnaBridge	172:65be27845400	668	uint32_t tsm_timing_39_init_26mhz;
AnnaBridge	172:65be27845400	669	uint32_t tsm_timing_39_init_32mhz;
AnnaBridge	172:65be27845400	670	uint32_t tsm_timing_40_init_26mhz;
AnnaBridge	172:65be27845400	671	uint32_t tsm_timing_40_init_32mhz;
AnnaBridge	172:65be27845400	672	uint32_t tsm_timing_41_init_26mhz;
AnnaBridge	172:65be27845400	673	uint32_t tsm_timing_41_init_32mhz;
AnnaBridge	172:65be27845400	674	uint32_t tsm_timing_51_init;
AnnaBridge	172:65be27845400	675	uint32_t tsm_timing_52_init_26mhz;
AnnaBridge	172:65be27845400	676	uint32_t tsm_timing_52_init_32mhz;
AnnaBridge	172:65be27845400	677	uint32_t tsm_timing_53_init;
AnnaBridge	172:65be27845400	678	uint32_t tsm_timing_54_init_26mhz;
AnnaBridge	172:65be27845400	679	uint32_t tsm_timing_54_init_32mhz;
AnnaBridge	172:65be27845400	680	uint32_t tsm_timing_55_init_26mhz;
AnnaBridge	172:65be27845400	681	uint32_t tsm_timing_55_init_32mhz;
AnnaBridge	172:65be27845400	682	uint32_t tsm_timing_56_init_26mhz;
AnnaBridge	172:65be27845400	683	uint32_t tsm_timing_56_init_32mhz;
AnnaBridge	172:65be27845400	684	uint32_t tsm_timing_57_init;
AnnaBridge	172:65be27845400	685	uint32_t tsm_timing_58_init;
AnnaBridge	172:65be27845400	686
AnnaBridge	172:65be27845400	687	/* XCVR_TX_DIG configs */
AnnaBridge	172:65be27845400	688	uint32_t tx_ctrl;
AnnaBridge	172:65be27845400	689	uint32_t tx_data_padding;
AnnaBridge	172:65be27845400	690	uint32_t tx_dft_pattern;
AnnaBridge	172:65be27845400	691	#if !RADIO_IS_GEN_2P1
AnnaBridge	172:65be27845400	692	uint32_t rf_dft_bist_1;
AnnaBridge	172:65be27845400	693	uint32_t rf_dft_bist_2;
AnnaBridge	172:65be27845400	694	#endif /* !RADIO_IS_GEN_2P1 */
AnnaBridge	172:65be27845400	695	} xcvr_common_config_t;
AnnaBridge	172:65be27845400	696
AnnaBridge	172:65be27845400	697	/! @brief XCVR mode specific configure structure (varies by radio mode) /
AnnaBridge	172:65be27845400	698	typedef struct _xcvr_mode_config
AnnaBridge	172:65be27845400	699	{
AnnaBridge	172:65be27845400	700	radio_mode_t radio_mode;
AnnaBridge	172:65be27845400	701	uint32_t scgc5_clock_ena_bits;
AnnaBridge	172:65be27845400	702
AnnaBridge	172:65be27845400	703	/* XCVR_MISC configs */
AnnaBridge	172:65be27845400	704	xcvr_masked_init_32_t xcvr_ctrl;
AnnaBridge	172:65be27845400	705
AnnaBridge	172:65be27845400	706	/* XCVR_PHY configs */
AnnaBridge	172:65be27845400	707	#if RADIO_IS_GEN_3P0
AnnaBridge	172:65be27845400	708	uint32_t phy_fsk_pd_cfg0;
AnnaBridge	172:65be27845400	709	uint32_t phy_fsk_pd_cfg1;
AnnaBridge	172:65be27845400	710	uint32_t phy_fsk_cfg;
AnnaBridge	172:65be27845400	711	uint32_t phy_fsk_misc;
AnnaBridge	172:65be27845400	712	uint32_t phy_fad_ctrl;
AnnaBridge	172:65be27845400	713	#else
AnnaBridge	172:65be27845400	714	uint32_t phy_pre_ref0_init;
AnnaBridge	172:65be27845400	715	uint32_t phy_pre_ref1_init;
AnnaBridge	172:65be27845400	716	uint32_t phy_pre_ref2_init;
AnnaBridge	172:65be27845400	717	uint32_t phy_cfg1_init;
AnnaBridge	172:65be27845400	718	uint32_t phy_el_cfg_init; /* Should leave EL_WIN_SIZE and EL_INTERVAL to the data_rate specific configuration */
AnnaBridge	172:65be27845400	719	#endif /* RADIO_IS_GEN_3P0 */
AnnaBridge	172:65be27845400	720
AnnaBridge	172:65be27845400	721	/* XCVR_RX_DIG configs */
AnnaBridge	172:65be27845400	722	uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
AnnaBridge	172:65be27845400	723	uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
AnnaBridge	172:65be27845400	724	uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */
AnnaBridge	172:65be27845400	725
AnnaBridge	172:65be27845400	726	/* XCVR_TSM configs */
AnnaBridge	172:65be27845400	727	#if (RADIO_IS_GEN_2P0 \|\| RADIO_IS_GEN_2P1)
AnnaBridge	172:65be27845400	728	uint32_t tsm_timing_35_init; /* Only the LSbyte is mode specific */
AnnaBridge	172:65be27845400	729	#endif /* (RADIO_IS_GEN_2P0 \|\| RADIO_IS_GEN_2P1) */
AnnaBridge	172:65be27845400	730
AnnaBridge	172:65be27845400	731	/* XCVR_TX_DIG configs */
AnnaBridge	172:65be27845400	732	uint32_t tx_gfsk_ctrl;
AnnaBridge	172:65be27845400	733	uint32_t tx_gfsk_coeff1_26mhz;
AnnaBridge	172:65be27845400	734	uint32_t tx_gfsk_coeff2_26mhz;
AnnaBridge	172:65be27845400	735	uint32_t tx_gfsk_coeff1_32mhz;
AnnaBridge	172:65be27845400	736	uint32_t tx_gfsk_coeff2_32mhz;
AnnaBridge	172:65be27845400	737	} xcvr_mode_config_t;
AnnaBridge	172:65be27845400	738
AnnaBridge	172:65be27845400	739	/*!
AnnaBridge	172:65be27845400	740	* @brief XCVR modeXdatarate specific configure structure (varies by radio mode AND data rate)
AnnaBridge	172:65be27845400	741	* This structure is used to store all of the XCVR settings which are dependent upon both radio mode and data rate. It is used as an overlay
AnnaBridge	172:65be27845400	742	* on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate.
AnnaBridge	172:65be27845400	743	*/
AnnaBridge	172:65be27845400	744	typedef struct _xcvr_mode_datarate_config
AnnaBridge	172:65be27845400	745	{
AnnaBridge	172:65be27845400	746	radio_mode_t radio_mode;
AnnaBridge	172:65be27845400	747	data_rate_t data_rate;
AnnaBridge	172:65be27845400	748
AnnaBridge	172:65be27845400	749	/* XCVR_ANA configs */
AnnaBridge	172:65be27845400	750	xcvr_masked_init_32_t ana_sy_ctrl2;
AnnaBridge	172:65be27845400	751	xcvr_masked_init_32_t ana_rx_bba;
AnnaBridge	172:65be27845400	752	xcvr_masked_init_32_t ana_rx_tza;
AnnaBridge	172:65be27845400	753
AnnaBridge	172:65be27845400	754	/* XCVR_PHY configs */
AnnaBridge	172:65be27845400	755	#if RADIO_IS_GEN_3P0
AnnaBridge	172:65be27845400	756	uint32_t phy_fsk_misc_mode_datarate;
AnnaBridge	172:65be27845400	757	#else
AnnaBridge	172:65be27845400	758	uint32_t phy_cfg2_init;
AnnaBridge	172:65be27845400	759	#endif /* RADIO_IS_GEN_3P0 */
AnnaBridge	172:65be27845400	760
AnnaBridge	172:65be27845400	761	uint32_t agc_ctrl_2_init_26mhz;
AnnaBridge	172:65be27845400	762	uint32_t agc_ctrl_2_init_32mhz;
AnnaBridge	172:65be27845400	763	xcvr_rx_chf_coeffs_t rx_chf_coeffs_26mhz; /* 26MHz ext clk */
AnnaBridge	172:65be27845400	764	xcvr_rx_chf_coeffs_t rx_chf_coeffs_32mhz; /* 32MHz ext clk */
AnnaBridge	172:65be27845400	765	uint32_t rx_rccal_ctrl_0;
AnnaBridge	172:65be27845400	766	uint32_t rx_rccal_ctrl_1;
AnnaBridge	172:65be27845400	767
AnnaBridge	172:65be27845400	768	/* XCVR_TX_DIG configs */
AnnaBridge	172:65be27845400	769	uint32_t tx_fsk_scale_26mhz; /* Only used by MSK mode, but dependent on datarate */
AnnaBridge	172:65be27845400	770	uint32_t tx_fsk_scale_32mhz; /* Only used by MSK mode, but dependent on datarate */
AnnaBridge	172:65be27845400	771	} xcvr_mode_datarate_config_t;
AnnaBridge	172:65be27845400	772
AnnaBridge	172:65be27845400	773	/*!
AnnaBridge	172:65be27845400	774	* @brief XCVR datarate specific configure structure (varies by data rate)
AnnaBridge	172:65be27845400	775	* This structure is used to store all of the XCVR settings which are dependent upon data rate. It is used as an overlay
AnnaBridge	172:65be27845400	776	* on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate.
AnnaBridge	172:65be27845400	777	*/
AnnaBridge	172:65be27845400	778	typedef struct _xcvr_datarate_config
AnnaBridge	172:65be27845400	779	{
AnnaBridge	172:65be27845400	780	data_rate_t data_rate;
AnnaBridge	172:65be27845400	781
AnnaBridge	172:65be27845400	782	/* XCVR_PHY configs */
AnnaBridge	172:65be27845400	783	uint32_t phy_el_cfg_init; /* Note: EL_ENABLE is set in xcvr_mode_config_t settings */
AnnaBridge	172:65be27845400	784
AnnaBridge	172:65be27845400	785	/* XCVR_RX_DIG configs */
AnnaBridge	172:65be27845400	786	uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
AnnaBridge	172:65be27845400	787	uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */
AnnaBridge	172:65be27845400	788	uint32_t agc_ctrl_1_init_26mhz;
AnnaBridge	172:65be27845400	789	uint32_t agc_ctrl_1_init_32mhz;
AnnaBridge	172:65be27845400	790	uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */
AnnaBridge	172:65be27845400	791	uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */
AnnaBridge	172:65be27845400	792	uint32_t dcoc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */
AnnaBridge	172:65be27845400	793	uint32_t dcoc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */
AnnaBridge	172:65be27845400	794	uint32_t dcoc_ctrl_2_init_26mhz;
AnnaBridge	172:65be27845400	795	uint32_t dcoc_ctrl_2_init_32mhz;
AnnaBridge	172:65be27845400	796	uint32_t dcoc_cal_iir_init_26mhz;
AnnaBridge	172:65be27845400	797	uint32_t dcoc_cal_iir_init_32mhz;
AnnaBridge	172:65be27845400	798	uint32_t dc_resid_ctrl_26mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */
AnnaBridge	172:65be27845400	799	uint32_t dc_resid_ctrl_32mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */
AnnaBridge	172:65be27845400	800	} xcvr_datarate_config_t;
AnnaBridge	172:65be27845400	801
AnnaBridge	172:65be27845400	802	/*!
AnnaBridge	172:65be27845400	803	* @brief LPUART callback function type
AnnaBridge	172:65be27845400	804	*
AnnaBridge	172:65be27845400	805	* The panic callback function is defined by system if system need to be informed of XCVR fatal errors.
AnnaBridge	172:65be27845400	806	* refer to #XCVR_RegisterPanicCb
AnnaBridge	172:65be27845400	807	*/
AnnaBridge	172:65be27845400	808	typedef void (*panic_fptr)(uint32_t panic_id, uint32_t location, uint32_t extra1, uint32_t extra2);
AnnaBridge	172:65be27845400	809
AnnaBridge	172:65be27845400	810	/* Make available const structures from config files */
AnnaBridge	172:65be27845400	811	extern const xcvr_common_config_t xcvr_common_config;
AnnaBridge	172:65be27845400	812	extern const xcvr_mode_config_t zgbe_mode_config;
AnnaBridge	172:65be27845400	813	extern const xcvr_mode_config_t ble_mode_config;
AnnaBridge	172:65be27845400	814	extern const xcvr_mode_config_t ant_mode_config;
AnnaBridge	172:65be27845400	815	extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config;
AnnaBridge	172:65be27845400	816	extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config;
AnnaBridge	172:65be27845400	817	extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config;
AnnaBridge	172:65be27845400	818	extern const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config;
AnnaBridge	172:65be27845400	819	extern const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config;
AnnaBridge	172:65be27845400	820	extern const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config;
AnnaBridge	172:65be27845400	821	extern const xcvr_mode_config_t msk_mode_config;
AnnaBridge	172:65be27845400	822
AnnaBridge	172:65be27845400	823	#if RADIO_IS_GEN_3P0
AnnaBridge	172:65be27845400	824	extern const xcvr_datarate_config_t xcvr_2mbps_config;
AnnaBridge	172:65be27845400	825	#endif /* RADIO_IS_GEN_3P0 */
AnnaBridge	172:65be27845400	826	extern const xcvr_datarate_config_t xcvr_1mbps_config;
AnnaBridge	172:65be27845400	827	extern const xcvr_datarate_config_t xcvr_500kbps_config;
AnnaBridge	172:65be27845400	828	extern const xcvr_datarate_config_t xcvr_250kbps_config;
AnnaBridge	172:65be27845400	829	extern const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config; /* Custom datarate settings for 802.15.4 since it is 2MChips/sec */
AnnaBridge	172:65be27845400	830
AnnaBridge	172:65be27845400	831	#if RADIO_IS_GEN_3P0
AnnaBridge	172:65be27845400	832	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_2mbps_config;
AnnaBridge	172:65be27845400	833	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_2mbps_config;
AnnaBridge	172:65be27845400	834	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_2mbps_config;
AnnaBridge	172:65be27845400	835	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_2mbps_config;
AnnaBridge	172:65be27845400	836	extern const xcvr_mode_datarate_config_t xcvr_MSK_2mbps_config;
AnnaBridge	172:65be27845400	837	#endif /* RADIO_IS_GEN_3P0 */
AnnaBridge	172:65be27845400	838	extern const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config;
AnnaBridge	172:65be27845400	839	extern const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config;
AnnaBridge	172:65be27845400	840	extern const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config;
AnnaBridge	172:65be27845400	841	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config;
AnnaBridge	172:65be27845400	842	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config;
AnnaBridge	172:65be27845400	843	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config;
AnnaBridge	172:65be27845400	844	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config;
AnnaBridge	172:65be27845400	845	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config;
AnnaBridge	172:65be27845400	846	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config;
AnnaBridge	172:65be27845400	847	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config;
AnnaBridge	172:65be27845400	848	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config;
AnnaBridge	172:65be27845400	849	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config;
AnnaBridge	172:65be27845400	850	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config;
AnnaBridge	172:65be27845400	851	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config;
AnnaBridge	172:65be27845400	852	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config;
AnnaBridge	172:65be27845400	853	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config;
AnnaBridge	172:65be27845400	854	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config;
AnnaBridge	172:65be27845400	855	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config;
AnnaBridge	172:65be27845400	856	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config;
AnnaBridge	172:65be27845400	857	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config;
AnnaBridge	172:65be27845400	858	extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config;
AnnaBridge	172:65be27845400	859	extern const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config;
AnnaBridge	172:65be27845400	860	extern const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config;
AnnaBridge	172:65be27845400	861	extern const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config;
AnnaBridge	172:65be27845400	862
AnnaBridge	172:65be27845400	863	/*******************************************************************************
AnnaBridge	172:65be27845400	864	* API
AnnaBridge	172:65be27845400	865	******************************************************************************/
AnnaBridge	172:65be27845400	866
AnnaBridge	172:65be27845400	867	#if defined(__cplusplus)
AnnaBridge	172:65be27845400	868	extern "C" {
AnnaBridge	172:65be27845400	869	#endif
AnnaBridge	172:65be27845400	870
AnnaBridge	172:65be27845400	871	/*!
AnnaBridge	172:65be27845400	872	* @name XCVR functional Operation
AnnaBridge	172:65be27845400	873	* @{
AnnaBridge	172:65be27845400	874	*/
AnnaBridge	172:65be27845400	875
AnnaBridge	172:65be27845400	876	/*!
AnnaBridge	172:65be27845400	877	* @brief Initializes an XCVR instance.
AnnaBridge	172:65be27845400	878	*
AnnaBridge	172:65be27845400	879	* This function initializes the XCVR module according to the radio_mode and data_rate settings. This the only function call required to
AnnaBridge	172:65be27845400	880	* start up the XCVR in most situations.
AnnaBridge	172:65be27845400	881	*
AnnaBridge	172:65be27845400	882	* @param radio_mode The radio mode for which the XCVR should be configured.
AnnaBridge	172:65be27845400	883	* @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected.
AnnaBridge	172:65be27845400	884	* @note This function encompasses the ::XCVRGetDefafultConfig() and ::XCVR_Configure() functions.
AnnaBridge	172:65be27845400	885	*/
AnnaBridge	172:65be27845400	886	xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate);
AnnaBridge	172:65be27845400	887
AnnaBridge	172:65be27845400	888	/*!
AnnaBridge	172:65be27845400	889	* @brief Deinitializes an XCVR instance.
AnnaBridge	172:65be27845400	890	*
AnnaBridge	172:65be27845400	891	* This function gate the XCVR module clock and set all register value to reset value.
AnnaBridge	172:65be27845400	892	*
AnnaBridge	172:65be27845400	893	*/
AnnaBridge	172:65be27845400	894	void XCVR_Deinit(void);
AnnaBridge	172:65be27845400	895
AnnaBridge	172:65be27845400	896	/*!
AnnaBridge	172:65be27845400	897	* @brief Initializes XCVR configure structure.
AnnaBridge	172:65be27845400	898	*
AnnaBridge	172:65be27845400	899	* This function updates pointers to the XCVR configure structures with default values.
AnnaBridge	172:65be27845400	900	* The configurations are divided into a common structure, a set of radio mode specific
AnnaBridge	172:65be27845400	901	* structures (one per radio_mode), a set of mode&datarate specific structures (for each mode at
AnnaBridge	172:65be27845400	902	* each datarate), and a set of data rate specific structures.
AnnaBridge	172:65be27845400	903	* The pointers provided by this routine point to const structures which can be
AnnaBridge	172:65be27845400	904	* copied to variable structures if changes to settings are required.
AnnaBridge	172:65be27845400	905	*
AnnaBridge	172:65be27845400	906	* @param radio_mode [in] The radio mode for which the configuration structures are requested.
AnnaBridge	172:65be27845400	907	* @param data_rate [in] The data rate for which the configuration structures are requested.
AnnaBridge	172:65be27845400	908	* @param com_config [in,out] Pointer to a pointer to the common configuration settings structure.
AnnaBridge	172:65be27845400	909	* @param mode_config [in,out] Pointer to a pointer to the mode specific configuration settings structure.
AnnaBridge	172:65be27845400	910	* @param mode_datarate_config [in,out] Pointer to a pointer to the modeXdata rate specific configuration settings structure.
AnnaBridge	172:65be27845400	911	* @param datarate_config [in,out] Pointer to a pointer to the data rate specific configuration settings structure.
AnnaBridge	172:65be27845400	912	* @return 0 success, others failure
AnnaBridge	172:65be27845400	913	* @see XCVR_Configure
AnnaBridge	172:65be27845400	914	*/
AnnaBridge	172:65be27845400	915	xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode,
AnnaBridge	172:65be27845400	916	data_rate_t data_rate,
AnnaBridge	172:65be27845400	917	const xcvr_common_config_t ** com_config,
AnnaBridge	172:65be27845400	918	const xcvr_mode_config_t ** mode_config,
AnnaBridge	172:65be27845400	919	const xcvr_mode_datarate_config_t ** mode_datarate_config,
AnnaBridge	172:65be27845400	920	const xcvr_datarate_config_t ** datarate_config);
AnnaBridge	172:65be27845400	921
AnnaBridge	172:65be27845400	922	/*!
AnnaBridge	172:65be27845400	923	* @brief Initializes an XCVR instance.
AnnaBridge	172:65be27845400	924	*
AnnaBridge	172:65be27845400	925	* This function initializes the XCVR module with user-defined settings.
AnnaBridge	172:65be27845400	926	*
AnnaBridge	172:65be27845400	927	* @param com_config Pointer to the common configuration settings structure.
AnnaBridge	172:65be27845400	928	* @param mode_config Pointer to the mode specific configuration settings structure.
AnnaBridge	172:65be27845400	929	* @param mode_datarate_config Pointer to a pointer to the modeXdata rate specific configuration settings structure.
AnnaBridge	172:65be27845400	930	* @param datarate_config Pointer to a pointer to the data rate specific configuration settings structure.
AnnaBridge	172:65be27845400	931	* @param tempDegC temperature of the die in degrees C.
AnnaBridge	172:65be27845400	932	* @param ext_clk indicates the external clock setting, 32MHz or 26MHz.
AnnaBridge	172:65be27845400	933	* @param first_init indicates whether the call is to initialize (== 1) or the call is to perform a mode change (== 0)
AnnaBridge	172:65be27845400	934	* @return 0 succeed, others failed
AnnaBridge	172:65be27845400	935	*/
AnnaBridge	172:65be27845400	936	xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config,
AnnaBridge	172:65be27845400	937	const xcvr_mode_config_t *mode_config,
AnnaBridge	172:65be27845400	938	const xcvr_mode_datarate_config_t *mode_datarate_config,
AnnaBridge	172:65be27845400	939	const xcvr_datarate_config_t *datarate_config,
AnnaBridge	172:65be27845400	940	int16_t tempDegC,
AnnaBridge	172:65be27845400	941	XCVR_INIT_MODE_CHG_T first_init);
AnnaBridge	172:65be27845400	942
AnnaBridge	172:65be27845400	943	/*!
AnnaBridge	172:65be27845400	944	* @brief Set XCVR register to reset value.
AnnaBridge	172:65be27845400	945	*
AnnaBridge	172:65be27845400	946	* This function set XCVR register to the reset value.
AnnaBridge	172:65be27845400	947	*
AnnaBridge	172:65be27845400	948	*/
AnnaBridge	172:65be27845400	949	void XCVR_Reset(void);
AnnaBridge	172:65be27845400	950
AnnaBridge	172:65be27845400	951	/*!
AnnaBridge	172:65be27845400	952	* @brief Change the operating mode of the radio.
AnnaBridge	172:65be27845400	953	*
AnnaBridge	172:65be27845400	954	* This function changes the XCVR to a new radio operating mode.
AnnaBridge	172:65be27845400	955	*
AnnaBridge	172:65be27845400	956	* @param new_radio_mode The radio mode for which the XCVR should be configured.
AnnaBridge	172:65be27845400	957	* @param new_data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected.
AnnaBridge	172:65be27845400	958	* @return status of the mode change.
AnnaBridge	172:65be27845400	959	*/
AnnaBridge	172:65be27845400	960	xcvrStatus_t XCVR_ChangeMode(radio_mode_t new_radio_mode, data_rate_t new_data_rate);
AnnaBridge	172:65be27845400	961
AnnaBridge	172:65be27845400	962	/*!
AnnaBridge	172:65be27845400	963	* @brief Enable Narrowband RSSI measurement.
AnnaBridge	172:65be27845400	964	*
AnnaBridge	172:65be27845400	965	* This function enables the narrowband RSSI measurement
AnnaBridge	172:65be27845400	966	*
AnnaBridge	172:65be27845400	967	* @param IIRnbEnable true causes the NB RSSI to be enabled, false disabled.
AnnaBridge	172:65be27845400	968	*/
AnnaBridge	172:65be27845400	969	void XCVR_EnaNBRSSIMeas(uint8_t IIRnbEnable);
AnnaBridge	172:65be27845400	970
AnnaBridge	172:65be27845400	971	/*!
AnnaBridge	172:65be27845400	972	* @brief Set an arbitrary frequency for RX and TX for the radio.
AnnaBridge	172:65be27845400	973	*
AnnaBridge	172:65be27845400	974	* This function sets the radio frequency used for RX and RX..
AnnaBridge	172:65be27845400	975	*
AnnaBridge	172:65be27845400	976	* @param freq target frequency setting in Hz.
AnnaBridge	172:65be27845400	977	* @param refOsc reference oscillator setting in Hz.
AnnaBridge	172:65be27845400	978	* @return status of the frequency change.
AnnaBridge	172:65be27845400	979	* @details
AnnaBridge	172:65be27845400	980	*/
AnnaBridge	172:65be27845400	981	xcvrStatus_t XCVR_OverrideFrequency(uint32_t freq, uint32_t refOsc);
AnnaBridge	172:65be27845400	982
AnnaBridge	172:65be27845400	983	/*!
AnnaBridge	172:65be27845400	984	* @brief Register a callback from upper layers.
AnnaBridge	172:65be27845400	985	*
AnnaBridge	172:65be27845400	986	* This function registers a callback from the upper layers for the radio to call in case of fatal errors.
AnnaBridge	172:65be27845400	987	*
AnnaBridge	172:65be27845400	988	* @param fptr The function pointer to a panic callback.
AnnaBridge	172:65be27845400	989	*/
AnnaBridge	172:65be27845400	990	void XCVR_RegisterPanicCb(panic_fptr fptr); /* allow upper layers to provide PANIC callback */
AnnaBridge	172:65be27845400	991
AnnaBridge	172:65be27845400	992	/*!
AnnaBridge	172:65be27845400	993	* @brief Read the health status of the XCVR to detect errors.
AnnaBridge	172:65be27845400	994	*
AnnaBridge	172:65be27845400	995	* This function enables the upper layers to request the current radio health.
AnnaBridge	172:65be27845400	996	*
AnnaBridge	172:65be27845400	997	* @return The health status of the radio..
AnnaBridge	172:65be27845400	998	*/
AnnaBridge	172:65be27845400	999	healthStatus_t XCVR_HealthCheck(void); /* allow upper layers to poll the radio health */
AnnaBridge	172:65be27845400	1000
AnnaBridge	172:65be27845400	1001	/*!
AnnaBridge	172:65be27845400	1002	* @brief Control FAD and LPPS features.
AnnaBridge	172:65be27845400	1003	*
AnnaBridge	172:65be27845400	1004	* This function controls the Fast Antenna Diversity (FAD) and Low Power Preamble Search.
AnnaBridge	172:65be27845400	1005	*
AnnaBridge	172:65be27845400	1006	* @param fptr control the FAD and LPPS settings.
AnnaBridge	172:65be27845400	1007	*
AnnaBridge	172:65be27845400	1008	*/
AnnaBridge	172:65be27845400	1009	void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control);
AnnaBridge	172:65be27845400	1010
AnnaBridge	172:65be27845400	1011	/*!
AnnaBridge	172:65be27845400	1012	* @brief Change the mapping of the radio IRQs.
AnnaBridge	172:65be27845400	1013	*
AnnaBridge	172:65be27845400	1014	* This function changes the mapping of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines.
AnnaBridge	172:65be27845400	1015	*
AnnaBridge	172:65be27845400	1016	* @param irq0_mapping the LL which should be mapped to the INT0 line.
AnnaBridge	172:65be27845400	1017	* @param irq1_mapping the LL which should be mapped to the INT1 line.
AnnaBridge	172:65be27845400	1018	* @return status of the mapping request.
AnnaBridge	172:65be27845400	1019	* @ note The radio_mode_t parameters map to ::link_layer_t selections for the LL which is connected to the INT line.
AnnaBridge	172:65be27845400	1020	* @warning
AnnaBridge	172:65be27845400	1021	* The same LL must NOT be mapped to both INT lines.
AnnaBridge	172:65be27845400	1022	*/
AnnaBridge	172:65be27845400	1023	xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping);
AnnaBridge	172:65be27845400	1024
AnnaBridge	172:65be27845400	1025	#if RADIO_IS_GEN_3P0
AnnaBridge	172:65be27845400	1026	/*!
AnnaBridge	172:65be27845400	1027	* @brief Sets the network address used by the PHY during BLE Bit Streaming Mode.
AnnaBridge	172:65be27845400	1028	*
AnnaBridge	172:65be27845400	1029	* This function programs the register in the PHY which contains the network address used during BSM.
AnnaBridge	172:65be27845400	1030	*
AnnaBridge	172:65be27845400	1031	* @param bsm_ntw_address the address to be used during BSM.
AnnaBridge	172:65be27845400	1032	* @ note This routine does NOT enable BSM.
AnnaBridge	172:65be27845400	1033	*/
AnnaBridge	172:65be27845400	1034	void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address);
AnnaBridge	172:65be27845400	1035
AnnaBridge	172:65be27845400	1036	/*!
AnnaBridge	172:65be27845400	1037	* @brief Reads the currently programmed network address used by the PHY during BLE Bit Streaming Mode.
AnnaBridge	172:65be27845400	1038	*
AnnaBridge	172:65be27845400	1039	* This function reads the register in the PHY which contains the network address used during BSM.
AnnaBridge	172:65be27845400	1040	*
AnnaBridge	172:65be27845400	1041	* @return bsm_ntw_address the address to be used during BSM.
AnnaBridge	172:65be27845400	1042	* @ note This routine does NOT enable BSM.
AnnaBridge	172:65be27845400	1043	*/
AnnaBridge	172:65be27845400	1044	uint32_t XCVR_GetBSM_NTW_Address(void);
AnnaBridge	172:65be27845400	1045	#endif /* RADIO_IS_GEN_3P0 */
AnnaBridge	172:65be27845400	1046
AnnaBridge	172:65be27845400	1047	/*!
AnnaBridge	172:65be27845400	1048	* @brief Get the mapping of the one of the radio IRQs.
AnnaBridge	172:65be27845400	1049	*
AnnaBridge	172:65be27845400	1050	* This function reads the setting for the mapping of one of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines.
AnnaBridge	172:65be27845400	1051	*
AnnaBridge	172:65be27845400	1052	* @param int_num the number, 0 or 1, of the INT line to fetched.
AnnaBridge	172:65be27845400	1053	* @return the mapping setting of the specified line.
AnnaBridge	172:65be27845400	1054	* @note Any value passed into this routine other than 0 will be treated as a 1.
AnnaBridge	172:65be27845400	1055	*/
AnnaBridge	172:65be27845400	1056	link_layer_t XCVR_GetIRQMapping(uint8_t int_num);
AnnaBridge	172:65be27845400	1057
AnnaBridge	172:65be27845400	1058	/*!
AnnaBridge	172:65be27845400	1059	* @brief Get the current configuration of the XCVR.
AnnaBridge	172:65be27845400	1060	*
AnnaBridge	172:65be27845400	1061	* This function fetches the current configuration (radio mode and radio data rate) of the XCVR to allow LL to properly config data rates, etc
AnnaBridge	172:65be27845400	1062	*
AnnaBridge	172:65be27845400	1063	* @param curr_config pointer to a structure to be updated with the current mode and data rate.
AnnaBridge	172:65be27845400	1064	* @return the status of the request, success or invalid parameter (null pointer).
AnnaBridge	172:65be27845400	1065	* @note This API will return meaningless results if called before the radio is initialized...
AnnaBridge	172:65be27845400	1066	*/
AnnaBridge	172:65be27845400	1067	xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config);
AnnaBridge	172:65be27845400	1068
AnnaBridge	172:65be27845400	1069	/*******************************************************************************
AnnaBridge	172:65be27845400	1070	* Customer level trim functions
AnnaBridge	172:65be27845400	1071	******************************************************************************/
AnnaBridge	172:65be27845400	1072	/*!
AnnaBridge	172:65be27845400	1073	* @brief Controls setting the XTAL trim value..
AnnaBridge	172:65be27845400	1074	*
AnnaBridge	172:65be27845400	1075	* This function enables the upper layers set a crystal trim compensation facor
AnnaBridge	172:65be27845400	1076	*
AnnaBridge	172:65be27845400	1077	* @param xtalTrim the trim value to apply to the XTAL trimming register. Only the 7 LSB are valid, setting the 8th bit returns an error.
AnnaBridge	172:65be27845400	1078	* @return The health status of the radio..
AnnaBridge	172:65be27845400	1079	*/
AnnaBridge	172:65be27845400	1080	xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim);
AnnaBridge	172:65be27845400	1081
AnnaBridge	172:65be27845400	1082	/*!
AnnaBridge	172:65be27845400	1083	* @brief Controls getting the XTAL trim value..
AnnaBridge	172:65be27845400	1084	*
AnnaBridge	172:65be27845400	1085	* This function enables the upper layers to read the current XTAL compensation factors.
AnnaBridge	172:65be27845400	1086	* The returned value is in the range 0..127 (7 bits).
AnnaBridge	172:65be27845400	1087	*
AnnaBridge	172:65be27845400	1088	* @return The XTAL trim compensation factors..
AnnaBridge	172:65be27845400	1089	*/
AnnaBridge	172:65be27845400	1090	uint8_t XCVR_GetXtalTrim(void);
AnnaBridge	172:65be27845400	1091
AnnaBridge	172:65be27845400	1092	/*!
AnnaBridge	172:65be27845400	1093	* @brief Controls setting the RSSI adjustment..
AnnaBridge	172:65be27845400	1094	*
AnnaBridge	172:65be27845400	1095	* This function enables the upper layers to set an RSSI adjustment value.
AnnaBridge	172:65be27845400	1096	*
AnnaBridge	172:65be27845400	1097	* @param adj the adjustment value to apply to the RSSI adjustment register. The value must be a signed 8-bit value, in 1/4 dBm step.
AnnaBridge	172:65be27845400	1098	* @return The health status of the radio..
AnnaBridge	172:65be27845400	1099	*/
AnnaBridge	172:65be27845400	1100	xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj);
AnnaBridge	172:65be27845400	1101
AnnaBridge	172:65be27845400	1102	/*!
AnnaBridge	172:65be27845400	1103	* @brief Controls getting the RSSI adjustment..
AnnaBridge	172:65be27845400	1104	*
AnnaBridge	172:65be27845400	1105	* This function enables the upper layers to read the current XCVR RSSI adjustment value.
AnnaBridge	172:65be27845400	1106	* The returned value is a signed 8-bit value, in 1/4 dBm step.
AnnaBridge	172:65be27845400	1107	*
AnnaBridge	172:65be27845400	1108	* @return The RSSI adjustment value..
AnnaBridge	172:65be27845400	1109	*/
AnnaBridge	172:65be27845400	1110	int8_t XCVR_GetRssiAdjustment(void);
AnnaBridge	172:65be27845400	1111
AnnaBridge	172:65be27845400	1112	/*!
AnnaBridge	172:65be27845400	1113	* @brief Controls setting the PLL to a particular channel.
AnnaBridge	172:65be27845400	1114	*
AnnaBridge	172:65be27845400	1115	* This function enables setting the radio channel for TX and RX.
AnnaBridge	172:65be27845400	1116	*
AnnaBridge	172:65be27845400	1117	* @param channel the channel number to set
AnnaBridge	172:65be27845400	1118	* @param useMappedChannel when true, channel is assumed to be from the protocol specific channel map. when false, channel is assumed to be from the 128 general channel list..
AnnaBridge	172:65be27845400	1119	* @return The status of the channel over-ride.
AnnaBridge	172:65be27845400	1120	*/
AnnaBridge	172:65be27845400	1121	xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel);
AnnaBridge	172:65be27845400	1122
AnnaBridge	172:65be27845400	1123	/*!
AnnaBridge	172:65be27845400	1124	* @brief Reads the current frequency for RX and TX for the radio.
AnnaBridge	172:65be27845400	1125	*
AnnaBridge	172:65be27845400	1126	* This function reads the radio frequency used for RX and RX..
AnnaBridge	172:65be27845400	1127	*
AnnaBridge	172:65be27845400	1128	* @return Current radio frequency setting.
AnnaBridge	172:65be27845400	1129	*/
AnnaBridge	172:65be27845400	1130	uint32_t XCVR_GetFreq(void);
AnnaBridge	172:65be27845400	1131
AnnaBridge	172:65be27845400	1132	/*!
AnnaBridge	172:65be27845400	1133	* @brief Force receiver warmup.
AnnaBridge	172:65be27845400	1134	*
AnnaBridge	172:65be27845400	1135	* This function forces the initiation of a receiver warmup sequence.
AnnaBridge	172:65be27845400	1136	*
AnnaBridge	172:65be27845400	1137	*/
AnnaBridge	172:65be27845400	1138	void XCVR_ForceRxWu(void);
AnnaBridge	172:65be27845400	1139
AnnaBridge	172:65be27845400	1140	/*!
AnnaBridge	172:65be27845400	1141	* @brief Force receiver warmdown.
AnnaBridge	172:65be27845400	1142	*
AnnaBridge	172:65be27845400	1143	* This function forces the initiation of a receiver warmdown sequence.
AnnaBridge	172:65be27845400	1144	*
AnnaBridge	172:65be27845400	1145	*/
AnnaBridge	172:65be27845400	1146	void XCVR_ForceRxWd(void);
AnnaBridge	172:65be27845400	1147
AnnaBridge	172:65be27845400	1148	/*!
AnnaBridge	172:65be27845400	1149	* @brief Force transmitter warmup.
AnnaBridge	172:65be27845400	1150	*
AnnaBridge	172:65be27845400	1151	* This function forces the initiation of a transmit warmup sequence.
AnnaBridge	172:65be27845400	1152	*
AnnaBridge	172:65be27845400	1153	*/
AnnaBridge	172:65be27845400	1154	void XCVR_ForceTxWu(void);
AnnaBridge	172:65be27845400	1155
AnnaBridge	172:65be27845400	1156	/*!
AnnaBridge	172:65be27845400	1157	* @brief Force transmitter warmdown.
AnnaBridge	172:65be27845400	1158	*
AnnaBridge	172:65be27845400	1159	* This function forces the initiation of a transmit warmdown sequence.
AnnaBridge	172:65be27845400	1160	*
AnnaBridge	172:65be27845400	1161	*/
AnnaBridge	172:65be27845400	1162	void XCVR_ForceTxWd(void);
AnnaBridge	172:65be27845400	1163
AnnaBridge	172:65be27845400	1164	/*!
AnnaBridge	172:65be27845400	1165	* @brief Starts transmit with a TX pattern register data sequence.
AnnaBridge	172:65be27845400	1166	*
AnnaBridge	172:65be27845400	1167	* This function starts transmitting using the DFT pattern register mode.
AnnaBridge	172:65be27845400	1168	*
AnnaBridge	172:65be27845400	1169	* @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation.
AnnaBridge	172:65be27845400	1170	* @param radio_mode The radio mode for which the XCVR should be configured.
AnnaBridge	172:65be27845400	1171	* @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected.
AnnaBridge	172:65be27845400	1172	* @param tx_pattern - the data pattern to transmit on.
AnnaBridge	172:65be27845400	1173	* @return The status of the pattern reg transmit.
AnnaBridge	172:65be27845400	1174	* @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode
AnnaBridge	172:65be27845400	1175	* and data rate.
AnnaBridge	172:65be27845400	1176	*/
AnnaBridge	172:65be27845400	1177	xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern);
AnnaBridge	172:65be27845400	1178
AnnaBridge	172:65be27845400	1179	/*!
AnnaBridge	172:65be27845400	1180	* @brief Starts transmit with a TX LFSR register data sequence.
AnnaBridge	172:65be27845400	1181	*
AnnaBridge	172:65be27845400	1182	* This function starts transmitting using the DFT LFSR register mode.
AnnaBridge	172:65be27845400	1183	*
AnnaBridge	172:65be27845400	1184	* @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation.
AnnaBridge	172:65be27845400	1185	* @param radio_mode The radio mode for which the XCVR should be configured.
AnnaBridge	172:65be27845400	1186	* @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected.
AnnaBridge	172:65be27845400	1187	* @param lfsr_length - the length of the LFSR sequence to use.
AnnaBridge	172:65be27845400	1188	* @return The status of the LFSR reg transmit.
AnnaBridge	172:65be27845400	1189	* @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode
AnnaBridge	172:65be27845400	1190	* and data rate.
AnnaBridge	172:65be27845400	1191	*/
AnnaBridge	172:65be27845400	1192	xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length);
AnnaBridge	172:65be27845400	1193
AnnaBridge	172:65be27845400	1194	/*!
AnnaBridge	172:65be27845400	1195	* @brief Controls clearing all TX DFT settings.
AnnaBridge	172:65be27845400	1196	*
AnnaBridge	172:65be27845400	1197	* This function reverts all TX DFT settings from the test modes to normal operating mode.
AnnaBridge	172:65be27845400	1198	*
AnnaBridge	172:65be27845400	1199	*/
AnnaBridge	172:65be27845400	1200	void XCVR_DftTxOff(void);
AnnaBridge	172:65be27845400	1201
AnnaBridge	172:65be27845400	1202	/*!
AnnaBridge	172:65be27845400	1203	* @brief Controls setting the PA power level.
AnnaBridge	172:65be27845400	1204	*
AnnaBridge	172:65be27845400	1205	* This function enables setting the PA power level to a specific setting, overriding any link layer settings.
AnnaBridge	172:65be27845400	1206	*
AnnaBridge	172:65be27845400	1207	* @param pa_power - the power level to set. Valid values are 0, 1, and even values from 2 to 0x3E, inclusive.
AnnaBridge	172:65be27845400	1208	* @return The status of the PA power over-ride.
AnnaBridge	172:65be27845400	1209	*/
AnnaBridge	172:65be27845400	1210	xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power);
AnnaBridge	172:65be27845400	1211
AnnaBridge	172:65be27845400	1212	/*!
AnnaBridge	172:65be27845400	1213	* @brief Starts CW TX.
AnnaBridge	172:65be27845400	1214	*
AnnaBridge	172:65be27845400	1215	* This function starts transmitting CW (no modulation).
AnnaBridge	172:65be27845400	1216	*
AnnaBridge	172:65be27845400	1217	* @param rf_channel_freq - the RF channel to transmit on. Valid values are integer values from 2360 to 2487MHz, inclusive.
AnnaBridge	172:65be27845400	1218	* @param protocol - the protocol setting to use, valid settings are 6 (GFSK) and 7 (FSK).
AnnaBridge	172:65be27845400	1219	* @return The status of the CW transmit.
AnnaBridge	172:65be27845400	1220	*/
AnnaBridge	172:65be27845400	1221	xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol);
AnnaBridge	172:65be27845400	1222
AnnaBridge	172:65be27845400	1223	xcvrStatus_t XCVR_CoexistenceInit(void);
AnnaBridge	172:65be27845400	1224	xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority);
AnnaBridge	172:65be27845400	1225	xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings);
AnnaBridge	172:65be27845400	1226
AnnaBridge	172:65be27845400	1227	/* @} */
AnnaBridge	172:65be27845400	1228
AnnaBridge	172:65be27845400	1229	#if defined(__cplusplus)
AnnaBridge	172:65be27845400	1230	}
AnnaBridge	172:65be27845400	1231	#endif
AnnaBridge	172:65be27845400	1232
AnnaBridge	172:65be27845400	1233	/! @}/
AnnaBridge	172:65be27845400	1234
AnnaBridge	172:65be27845400	1235	#endif /* _FSL_XCVR_H_ */
AnnaBridge	172:65be27845400	1236