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TARGET_KW41Z/TOOLCHAIN_GCC_ARM/MKW41Z4.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 3 ** Processors: MKW41Z256VHT4
AnnaBridge 171:3a7713b1edbc 4 ** MKW41Z512VHT4
AnnaBridge 171:3a7713b1edbc 5 **
AnnaBridge 171:3a7713b1edbc 6 ** Compilers: Keil ARM C/C++ Compiler
AnnaBridge 171:3a7713b1edbc 7 ** GNU C Compiler
AnnaBridge 171:3a7713b1edbc 8 ** IAR ANSI C/C++ Compiler for ARM
AnnaBridge 171:3a7713b1edbc 9 **
AnnaBridge 171:3a7713b1edbc 10 ** Reference manual: MKW41Z512RM Rev. 0.1, 04/2016
AnnaBridge 171:3a7713b1edbc 11 ** Version: rev. 1.0, 2015-09-23
AnnaBridge 171:3a7713b1edbc 12 ** Build: b160720
AnnaBridge 171:3a7713b1edbc 13 **
AnnaBridge 171:3a7713b1edbc 14 ** Abstract:
AnnaBridge 171:3a7713b1edbc 15 ** CMSIS Peripheral Access Layer for MKW41Z4
AnnaBridge 171:3a7713b1edbc 16 **
AnnaBridge 171:3a7713b1edbc 17 ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 18 ** All rights reserved.
AnnaBridge 171:3a7713b1edbc 19 **
AnnaBridge 171:3a7713b1edbc 20 ** Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 21 ** are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 22 **
AnnaBridge 171:3a7713b1edbc 23 ** o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 24 ** of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 25 **
AnnaBridge 171:3a7713b1edbc 26 ** o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 27 ** list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 28 ** other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 29 **
AnnaBridge 171:3a7713b1edbc 30 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 171:3a7713b1edbc 31 ** contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 32 ** software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 33 **
AnnaBridge 171:3a7713b1edbc 34 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 35 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 36 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 37 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 38 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 39 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 40 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 41 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 42 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 43 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 44 **
AnnaBridge 171:3a7713b1edbc 45 ** http: www.freescale.com
AnnaBridge 171:3a7713b1edbc 46 ** mail: support@freescale.com
AnnaBridge 171:3a7713b1edbc 47 **
AnnaBridge 171:3a7713b1edbc 48 ** Revisions:
AnnaBridge 171:3a7713b1edbc 49 ** - rev. 1.0 (2015-09-23)
AnnaBridge 171:3a7713b1edbc 50 ** Initial version.
AnnaBridge 171:3a7713b1edbc 51 **
AnnaBridge 171:3a7713b1edbc 52 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 53 */
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /*!
AnnaBridge 171:3a7713b1edbc 56 * @file MKW41Z4.h
AnnaBridge 171:3a7713b1edbc 57 * @version 1.0
AnnaBridge 171:3a7713b1edbc 58 * @date 2015-09-23
AnnaBridge 171:3a7713b1edbc 59 * @brief CMSIS Peripheral Access Layer for MKW41Z4
AnnaBridge 171:3a7713b1edbc 60 *
AnnaBridge 171:3a7713b1edbc 61 * CMSIS Peripheral Access Layer for MKW41Z4
AnnaBridge 171:3a7713b1edbc 62 */
AnnaBridge 171:3a7713b1edbc 63
AnnaBridge 171:3a7713b1edbc 64 #ifndef _MKW41Z4_H_
AnnaBridge 171:3a7713b1edbc 65 #define _MKW41Z4_H_ /**< Symbol preventing repeated inclusion */
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /** Memory map major version (memory maps with equal major version number are
AnnaBridge 171:3a7713b1edbc 68 * compatible) */
AnnaBridge 171:3a7713b1edbc 69 #define MCU_MEM_MAP_VERSION 0x0100U
AnnaBridge 171:3a7713b1edbc 70 /** Memory map minor version */
AnnaBridge 171:3a7713b1edbc 71 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 75 -- Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 76 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 /*!
AnnaBridge 171:3a7713b1edbc 79 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 80 * @{
AnnaBridge 171:3a7713b1edbc 81 */
AnnaBridge 171:3a7713b1edbc 82
AnnaBridge 171:3a7713b1edbc 83 /** Interrupt Number Definitions */
AnnaBridge 171:3a7713b1edbc 84 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
AnnaBridge 171:3a7713b1edbc 85
AnnaBridge 171:3a7713b1edbc 86 typedef enum IRQn {
AnnaBridge 171:3a7713b1edbc 87 /* Auxiliary constants */
AnnaBridge 171:3a7713b1edbc 88 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 /* Core interrupts */
AnnaBridge 171:3a7713b1edbc 91 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 92 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 93 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 94 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 95 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 /* Device specific interrupts */
AnnaBridge 171:3a7713b1edbc 98 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
AnnaBridge 171:3a7713b1edbc 99 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
AnnaBridge 171:3a7713b1edbc 100 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
AnnaBridge 171:3a7713b1edbc 101 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
AnnaBridge 171:3a7713b1edbc 102 Reserved20_IRQn = 4, /**< Reserved interrupt */
AnnaBridge 171:3a7713b1edbc 103 FTFA_IRQn = 5, /**< Command complete and read collision */
AnnaBridge 171:3a7713b1edbc 104 LVD_LVW_DCDC_IRQn = 6, /**< Low-voltage detect, low-voltage warning, DCDC */
AnnaBridge 171:3a7713b1edbc 105 LLWU_IRQn = 7, /**< Low leakage wakeup Unit */
AnnaBridge 171:3a7713b1edbc 106 I2C0_IRQn = 8, /**< I2C0 interrupt */
AnnaBridge 171:3a7713b1edbc 107 I2C1_IRQn = 9, /**< I2C1 interrupt */
AnnaBridge 171:3a7713b1edbc 108 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
AnnaBridge 171:3a7713b1edbc 109 TSI0_IRQn = 11, /**< TSI0 single interrupt vector for all sources */
AnnaBridge 171:3a7713b1edbc 110 LPUART0_IRQn = 12, /**< LPUART0 status and error */
AnnaBridge 171:3a7713b1edbc 111 TRNG0_IRQn = 13, /**< TRNG0 interrupt */
AnnaBridge 171:3a7713b1edbc 112 CMT_IRQn = 14, /**< CMT interrupt */
AnnaBridge 171:3a7713b1edbc 113 ADC0_IRQn = 15, /**< ADC0 interrupt */
AnnaBridge 171:3a7713b1edbc 114 CMP0_IRQn = 16, /**< CMP0 interrupt */
AnnaBridge 171:3a7713b1edbc 115 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
AnnaBridge 171:3a7713b1edbc 116 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
AnnaBridge 171:3a7713b1edbc 117 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
AnnaBridge 171:3a7713b1edbc 118 RTC_IRQn = 20, /**< RTC alarm */
AnnaBridge 171:3a7713b1edbc 119 RTC_Seconds_IRQn = 21, /**< RTC seconds */
AnnaBridge 171:3a7713b1edbc 120 PIT_IRQn = 22, /**< PIT interrupt */
AnnaBridge 171:3a7713b1edbc 121 LTC0_IRQn = 23, /**< LTC0 interrupt */
AnnaBridge 171:3a7713b1edbc 122 Radio_0_IRQn = 24, /**< BTLE, ZIGBEE, ANT, GENFSK interrupt 0 */
AnnaBridge 171:3a7713b1edbc 123 DAC0_IRQn = 25, /**< DAC0 interrupt */
AnnaBridge 171:3a7713b1edbc 124 Radio_1_IRQn = 26, /**< BTLE, ZIGBEE, ANT, GENFSK interrupt 1 */
AnnaBridge 171:3a7713b1edbc 125 MCG_IRQn = 27, /**< MCG interrupt */
AnnaBridge 171:3a7713b1edbc 126 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
AnnaBridge 171:3a7713b1edbc 127 SPI1_IRQn = 29, /**< SPI1 single interrupt vector for all sources */
AnnaBridge 171:3a7713b1edbc 128 PORTA_IRQn = 30, /**< PORTA Pin detect */
AnnaBridge 171:3a7713b1edbc 129 PORTB_PORTC_IRQn = 31 /**< PORTB and PORTC Pin detect */
AnnaBridge 171:3a7713b1edbc 130 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 /*!
AnnaBridge 171:3a7713b1edbc 133 * @}
AnnaBridge 171:3a7713b1edbc 134 */ /* end of group Interrupt_vector_numbers */
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 138 -- Cortex M0 Core Configuration
AnnaBridge 171:3a7713b1edbc 139 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 140
AnnaBridge 171:3a7713b1edbc 141 /*!
AnnaBridge 171:3a7713b1edbc 142 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
AnnaBridge 171:3a7713b1edbc 143 * @{
AnnaBridge 171:3a7713b1edbc 144 */
AnnaBridge 171:3a7713b1edbc 145
AnnaBridge 171:3a7713b1edbc 146 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
AnnaBridge 171:3a7713b1edbc 147 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
AnnaBridge 171:3a7713b1edbc 148 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */
AnnaBridge 171:3a7713b1edbc 149 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
AnnaBridge 171:3a7713b1edbc 150 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
AnnaBridge 171:3a7713b1edbc 153 #include "system_MKW41Z4.h" /* Device specific configuration file */
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 /*!
AnnaBridge 171:3a7713b1edbc 156 * @}
AnnaBridge 171:3a7713b1edbc 157 */ /* end of group Cortex_Core_Configuration */
AnnaBridge 171:3a7713b1edbc 158
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 161 -- Mapping Information
AnnaBridge 171:3a7713b1edbc 162 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 /*!
AnnaBridge 171:3a7713b1edbc 165 * @addtogroup Mapping_Information Mapping Information
AnnaBridge 171:3a7713b1edbc 166 * @{
AnnaBridge 171:3a7713b1edbc 167 */
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 /** Mapping Information */
AnnaBridge 171:3a7713b1edbc 170 /*!
AnnaBridge 171:3a7713b1edbc 171 * @addtogroup edma_request
AnnaBridge 171:3a7713b1edbc 172 * @{
AnnaBridge 171:3a7713b1edbc 173 */
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 176 * Definitions
AnnaBridge 171:3a7713b1edbc 177 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 /*!
AnnaBridge 171:3a7713b1edbc 180 * @brief Structure for the DMA hardware request
AnnaBridge 171:3a7713b1edbc 181 *
AnnaBridge 171:3a7713b1edbc 182 * Defines the structure for the DMA hardware request collections. The user can configure the
AnnaBridge 171:3a7713b1edbc 183 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
AnnaBridge 171:3a7713b1edbc 184 * of the hardware request varies according to the to SoC.
AnnaBridge 171:3a7713b1edbc 185 */
AnnaBridge 171:3a7713b1edbc 186 typedef enum _dma_request_source
AnnaBridge 171:3a7713b1edbc 187 {
AnnaBridge 171:3a7713b1edbc 188 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
AnnaBridge 171:3a7713b1edbc 189 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
AnnaBridge 171:3a7713b1edbc 190 kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */
AnnaBridge 171:3a7713b1edbc 191 kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */
AnnaBridge 171:3a7713b1edbc 192 kDmaRequestMux0Reserved4 = 4|0x100U, /**< Reserved4 */
AnnaBridge 171:3a7713b1edbc 193 kDmaRequestMux0Reserved5 = 5|0x100U, /**< Reserved5 */
AnnaBridge 171:3a7713b1edbc 194 kDmaRequestMux0Reserved6 = 6|0x100U, /**< Reserved6 */
AnnaBridge 171:3a7713b1edbc 195 kDmaRequestMux0Reserved7 = 7|0x100U, /**< Reserved7 */
AnnaBridge 171:3a7713b1edbc 196 kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
AnnaBridge 171:3a7713b1edbc 197 kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
AnnaBridge 171:3a7713b1edbc 198 kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */
AnnaBridge 171:3a7713b1edbc 199 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
AnnaBridge 171:3a7713b1edbc 200 kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */
AnnaBridge 171:3a7713b1edbc 201 kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */
AnnaBridge 171:3a7713b1edbc 202 kDmaRequestMux0Reserved14 = 14|0x100U, /**< Reserved14 */
AnnaBridge 171:3a7713b1edbc 203 kDmaRequestMux0Reserved15 = 15|0x100U, /**< Reserved15 */
AnnaBridge 171:3a7713b1edbc 204 kDmaRequestMux0SPI0Rx = 16|0x100U, /**< SPI0 Receive. */
AnnaBridge 171:3a7713b1edbc 205 kDmaRequestMux0SPI0Tx = 17|0x100U, /**< SPI0 Transmit. */
AnnaBridge 171:3a7713b1edbc 206 kDmaRequestMux0SPI1Rx = 18|0x100U, /**< SPI1 Receive. */
AnnaBridge 171:3a7713b1edbc 207 kDmaRequestMux0SPI1Tx = 19|0x100U, /**< SPI1 Transmit. */
AnnaBridge 171:3a7713b1edbc 208 kDmaRequestMux0LTC0InputFIFO = 20|0x100U, /**< LTC0 Input FIFO. */
AnnaBridge 171:3a7713b1edbc 209 kDmaRequestMux0LTC0OutputFIFO = 21|0x100U, /**< LTC0 Output FIFO. */
AnnaBridge 171:3a7713b1edbc 210 kDmaRequestMux0I2C0 = 22|0x100U, /**< I2C0. */
AnnaBridge 171:3a7713b1edbc 211 kDmaRequestMux0I2C1 = 23|0x100U, /**< I2C1. */
AnnaBridge 171:3a7713b1edbc 212 kDmaRequestMux0TPM0Channel0 = 24|0x100U, /**< TPM0 C0V. */
AnnaBridge 171:3a7713b1edbc 213 kDmaRequestMux0TPM0Channel1 = 25|0x100U, /**< TPM0 C1V. */
AnnaBridge 171:3a7713b1edbc 214 kDmaRequestMux0TPM0Channel2 = 26|0x100U, /**< TPM0 C2V. */
AnnaBridge 171:3a7713b1edbc 215 kDmaRequestMux0TPM0Channel3 = 27|0x100U, /**< TPM0 C3V. */
AnnaBridge 171:3a7713b1edbc 216 kDmaRequestMux0Reserved28 = 28|0x100U, /**< Reserved28 */
AnnaBridge 171:3a7713b1edbc 217 kDmaRequestMux0Reserved29 = 29|0x100U, /**< Reserved29 */
AnnaBridge 171:3a7713b1edbc 218 kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */
AnnaBridge 171:3a7713b1edbc 219 kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */
AnnaBridge 171:3a7713b1edbc 220 kDmaRequestMux0TPM1Channel0 = 32|0x100U, /**< TPM1 C0V. */
AnnaBridge 171:3a7713b1edbc 221 kDmaRequestMux0TPM1Channel1 = 33|0x100U, /**< TPM1 C1V. */
AnnaBridge 171:3a7713b1edbc 222 kDmaRequestMux0TPM2Channel0 = 34|0x100U, /**< TPM2 C0V. */
AnnaBridge 171:3a7713b1edbc 223 kDmaRequestMux0TPM2Channel1 = 35|0x100U, /**< TPM2 C1V. */
AnnaBridge 171:3a7713b1edbc 224 kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
AnnaBridge 171:3a7713b1edbc 225 kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
AnnaBridge 171:3a7713b1edbc 226 kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
AnnaBridge 171:3a7713b1edbc 227 kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
AnnaBridge 171:3a7713b1edbc 228 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
AnnaBridge 171:3a7713b1edbc 229 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
AnnaBridge 171:3a7713b1edbc 230 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
AnnaBridge 171:3a7713b1edbc 231 kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */
AnnaBridge 171:3a7713b1edbc 232 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
AnnaBridge 171:3a7713b1edbc 233 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
AnnaBridge 171:3a7713b1edbc 234 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
AnnaBridge 171:3a7713b1edbc 235 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
AnnaBridge 171:3a7713b1edbc 236 kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */
AnnaBridge 171:3a7713b1edbc 237 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
AnnaBridge 171:3a7713b1edbc 238 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
AnnaBridge 171:3a7713b1edbc 239 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
AnnaBridge 171:3a7713b1edbc 240 kDmaRequestMux0Reserved52 = 52|0x100U, /**< Reserved52 */
AnnaBridge 171:3a7713b1edbc 241 kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */
AnnaBridge 171:3a7713b1edbc 242 kDmaRequestMux0TPM0Overflow = 54|0x100U, /**< TPM0. */
AnnaBridge 171:3a7713b1edbc 243 kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1. */
AnnaBridge 171:3a7713b1edbc 244 kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2. */
AnnaBridge 171:3a7713b1edbc 245 kDmaRequestMux0TSI0 = 57|0x100U, /**< TSI0. */
AnnaBridge 171:3a7713b1edbc 246 kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */
AnnaBridge 171:3a7713b1edbc 247 kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */
AnnaBridge 171:3a7713b1edbc 248 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 249 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 250 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 251 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 252 } dma_request_source_t;
AnnaBridge 171:3a7713b1edbc 253
AnnaBridge 171:3a7713b1edbc 254 /* @} */
AnnaBridge 171:3a7713b1edbc 255
AnnaBridge 171:3a7713b1edbc 256
AnnaBridge 171:3a7713b1edbc 257 /*!
AnnaBridge 171:3a7713b1edbc 258 * @}
AnnaBridge 171:3a7713b1edbc 259 */ /* end of group Mapping_Information */
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 263 -- Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 264 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 265
AnnaBridge 171:3a7713b1edbc 266 /*!
AnnaBridge 171:3a7713b1edbc 267 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 268 * @{
AnnaBridge 171:3a7713b1edbc 269 */
AnnaBridge 171:3a7713b1edbc 270
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 /*
AnnaBridge 171:3a7713b1edbc 273 ** Start of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 274 */
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 277 #pragma push
AnnaBridge 171:3a7713b1edbc 278 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 279 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 280 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 281 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 282 #pragma language=extended
AnnaBridge 171:3a7713b1edbc 283 #else
AnnaBridge 171:3a7713b1edbc 284 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 285 #endif
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 288 -- ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 289 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 290
AnnaBridge 171:3a7713b1edbc 291 /*!
AnnaBridge 171:3a7713b1edbc 292 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 293 * @{
AnnaBridge 171:3a7713b1edbc 294 */
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 /** ADC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 297 typedef struct {
AnnaBridge 171:3a7713b1edbc 298 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 299 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 300 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 301 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 302 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 303 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 304 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 305 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 306 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 307 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 308 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 309 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 310 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 311 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 312 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 313 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 314 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 315 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 316 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 317 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 318 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 319 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 320 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 321 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 322 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 323 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 324 } ADC_Type;
AnnaBridge 171:3a7713b1edbc 325
AnnaBridge 171:3a7713b1edbc 326 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 327 -- ADC Register Masks
AnnaBridge 171:3a7713b1edbc 328 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 /*!
AnnaBridge 171:3a7713b1edbc 331 * @addtogroup ADC_Register_Masks ADC Register Masks
AnnaBridge 171:3a7713b1edbc 332 * @{
AnnaBridge 171:3a7713b1edbc 333 */
AnnaBridge 171:3a7713b1edbc 334
AnnaBridge 171:3a7713b1edbc 335 /*! @name SC1 - ADC Status and Control Registers 1 */
AnnaBridge 171:3a7713b1edbc 336 #define ADC_SC1_ADCH_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 337 #define ADC_SC1_ADCH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 338 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
AnnaBridge 171:3a7713b1edbc 339 #define ADC_SC1_DIFF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 340 #define ADC_SC1_DIFF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 341 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
AnnaBridge 171:3a7713b1edbc 342 #define ADC_SC1_AIEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 343 #define ADC_SC1_AIEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 344 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
AnnaBridge 171:3a7713b1edbc 345 #define ADC_SC1_COCO_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 346 #define ADC_SC1_COCO_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 347 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
AnnaBridge 171:3a7713b1edbc 348
AnnaBridge 171:3a7713b1edbc 349 /* The count of ADC_SC1 */
AnnaBridge 171:3a7713b1edbc 350 #define ADC_SC1_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 351
AnnaBridge 171:3a7713b1edbc 352 /*! @name CFG1 - ADC Configuration Register 1 */
AnnaBridge 171:3a7713b1edbc 353 #define ADC_CFG1_ADICLK_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 354 #define ADC_CFG1_ADICLK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 355 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
AnnaBridge 171:3a7713b1edbc 356 #define ADC_CFG1_MODE_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 357 #define ADC_CFG1_MODE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 358 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 359 #define ADC_CFG1_ADLSMP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 360 #define ADC_CFG1_ADLSMP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 361 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
AnnaBridge 171:3a7713b1edbc 362 #define ADC_CFG1_ADIV_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 363 #define ADC_CFG1_ADIV_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 364 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
AnnaBridge 171:3a7713b1edbc 365 #define ADC_CFG1_ADLPC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 366 #define ADC_CFG1_ADLPC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 367 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
AnnaBridge 171:3a7713b1edbc 368
AnnaBridge 171:3a7713b1edbc 369 /*! @name CFG2 - ADC Configuration Register 2 */
AnnaBridge 171:3a7713b1edbc 370 #define ADC_CFG2_ADLSTS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 371 #define ADC_CFG2_ADLSTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 372 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
AnnaBridge 171:3a7713b1edbc 373 #define ADC_CFG2_ADHSC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 374 #define ADC_CFG2_ADHSC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 375 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
AnnaBridge 171:3a7713b1edbc 376 #define ADC_CFG2_ADACKEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 377 #define ADC_CFG2_ADACKEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 378 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
AnnaBridge 171:3a7713b1edbc 379 #define ADC_CFG2_MUXSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 380 #define ADC_CFG2_MUXSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 381 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
AnnaBridge 171:3a7713b1edbc 382
AnnaBridge 171:3a7713b1edbc 383 /*! @name R - ADC Data Result Register */
AnnaBridge 171:3a7713b1edbc 384 #define ADC_R_D_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 385 #define ADC_R_D_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 386 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
AnnaBridge 171:3a7713b1edbc 387
AnnaBridge 171:3a7713b1edbc 388 /* The count of ADC_R */
AnnaBridge 171:3a7713b1edbc 389 #define ADC_R_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 390
AnnaBridge 171:3a7713b1edbc 391 /*! @name CV1 - Compare Value Registers */
AnnaBridge 171:3a7713b1edbc 392 #define ADC_CV1_CV_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 393 #define ADC_CV1_CV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 394 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
AnnaBridge 171:3a7713b1edbc 395
AnnaBridge 171:3a7713b1edbc 396 /*! @name CV2 - Compare Value Registers */
AnnaBridge 171:3a7713b1edbc 397 #define ADC_CV2_CV_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 398 #define ADC_CV2_CV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 399 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
AnnaBridge 171:3a7713b1edbc 400
AnnaBridge 171:3a7713b1edbc 401 /*! @name SC2 - Status and Control Register 2 */
AnnaBridge 171:3a7713b1edbc 402 #define ADC_SC2_REFSEL_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 403 #define ADC_SC2_REFSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 404 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
AnnaBridge 171:3a7713b1edbc 405 #define ADC_SC2_DMAEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 406 #define ADC_SC2_DMAEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 407 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 408 #define ADC_SC2_ACREN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 409 #define ADC_SC2_ACREN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 410 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
AnnaBridge 171:3a7713b1edbc 411 #define ADC_SC2_ACFGT_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 412 #define ADC_SC2_ACFGT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 413 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
AnnaBridge 171:3a7713b1edbc 414 #define ADC_SC2_ACFE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 415 #define ADC_SC2_ACFE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 416 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
AnnaBridge 171:3a7713b1edbc 417 #define ADC_SC2_ADTRG_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 418 #define ADC_SC2_ADTRG_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 419 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
AnnaBridge 171:3a7713b1edbc 420 #define ADC_SC2_ADACT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 421 #define ADC_SC2_ADACT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 422 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
AnnaBridge 171:3a7713b1edbc 423
AnnaBridge 171:3a7713b1edbc 424 /*! @name SC3 - Status and Control Register 3 */
AnnaBridge 171:3a7713b1edbc 425 #define ADC_SC3_AVGS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 426 #define ADC_SC3_AVGS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 427 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
AnnaBridge 171:3a7713b1edbc 428 #define ADC_SC3_AVGE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 429 #define ADC_SC3_AVGE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 430 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
AnnaBridge 171:3a7713b1edbc 431 #define ADC_SC3_ADCO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 432 #define ADC_SC3_ADCO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 433 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
AnnaBridge 171:3a7713b1edbc 434 #define ADC_SC3_CALF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 435 #define ADC_SC3_CALF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 436 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
AnnaBridge 171:3a7713b1edbc 437 #define ADC_SC3_CAL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 438 #define ADC_SC3_CAL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 439 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 440
AnnaBridge 171:3a7713b1edbc 441 /*! @name OFS - ADC Offset Correction Register */
AnnaBridge 171:3a7713b1edbc 442 #define ADC_OFS_OFS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 443 #define ADC_OFS_OFS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 444 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
AnnaBridge 171:3a7713b1edbc 445
AnnaBridge 171:3a7713b1edbc 446 /*! @name PG - ADC Plus-Side Gain Register */
AnnaBridge 171:3a7713b1edbc 447 #define ADC_PG_PG_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 448 #define ADC_PG_PG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 449 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
AnnaBridge 171:3a7713b1edbc 450
AnnaBridge 171:3a7713b1edbc 451 /*! @name MG - ADC Minus-Side Gain Register */
AnnaBridge 171:3a7713b1edbc 452 #define ADC_MG_MG_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 453 #define ADC_MG_MG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 454 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
AnnaBridge 171:3a7713b1edbc 455
AnnaBridge 171:3a7713b1edbc 456 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 457 #define ADC_CLPD_CLPD_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 458 #define ADC_CLPD_CLPD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 459 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
AnnaBridge 171:3a7713b1edbc 460
AnnaBridge 171:3a7713b1edbc 461 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 462 #define ADC_CLPS_CLPS_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 463 #define ADC_CLPS_CLPS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 464 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
AnnaBridge 171:3a7713b1edbc 465
AnnaBridge 171:3a7713b1edbc 466 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 467 #define ADC_CLP4_CLP4_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 468 #define ADC_CLP4_CLP4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 469 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
AnnaBridge 171:3a7713b1edbc 470
AnnaBridge 171:3a7713b1edbc 471 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 472 #define ADC_CLP3_CLP3_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 473 #define ADC_CLP3_CLP3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 474 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
AnnaBridge 171:3a7713b1edbc 475
AnnaBridge 171:3a7713b1edbc 476 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 477 #define ADC_CLP2_CLP2_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 478 #define ADC_CLP2_CLP2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 479 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
AnnaBridge 171:3a7713b1edbc 480
AnnaBridge 171:3a7713b1edbc 481 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 482 #define ADC_CLP1_CLP1_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 483 #define ADC_CLP1_CLP1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 484 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
AnnaBridge 171:3a7713b1edbc 485
AnnaBridge 171:3a7713b1edbc 486 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 487 #define ADC_CLP0_CLP0_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 488 #define ADC_CLP0_CLP0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 489 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 492 #define ADC_CLMD_CLMD_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 493 #define ADC_CLMD_CLMD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 494 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
AnnaBridge 171:3a7713b1edbc 495
AnnaBridge 171:3a7713b1edbc 496 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 497 #define ADC_CLMS_CLMS_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 498 #define ADC_CLMS_CLMS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 499 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
AnnaBridge 171:3a7713b1edbc 500
AnnaBridge 171:3a7713b1edbc 501 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 502 #define ADC_CLM4_CLM4_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 503 #define ADC_CLM4_CLM4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 504 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
AnnaBridge 171:3a7713b1edbc 505
AnnaBridge 171:3a7713b1edbc 506 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 507 #define ADC_CLM3_CLM3_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 508 #define ADC_CLM3_CLM3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 509 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
AnnaBridge 171:3a7713b1edbc 510
AnnaBridge 171:3a7713b1edbc 511 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 512 #define ADC_CLM2_CLM2_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 513 #define ADC_CLM2_CLM2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 514 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
AnnaBridge 171:3a7713b1edbc 515
AnnaBridge 171:3a7713b1edbc 516 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 517 #define ADC_CLM1_CLM1_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 518 #define ADC_CLM1_CLM1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 519 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
AnnaBridge 171:3a7713b1edbc 520
AnnaBridge 171:3a7713b1edbc 521 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 522 #define ADC_CLM0_CLM0_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 523 #define ADC_CLM0_CLM0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 524 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
AnnaBridge 171:3a7713b1edbc 525
AnnaBridge 171:3a7713b1edbc 526
AnnaBridge 171:3a7713b1edbc 527 /*!
AnnaBridge 171:3a7713b1edbc 528 * @}
AnnaBridge 171:3a7713b1edbc 529 */ /* end of group ADC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 530
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 /* ADC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 533 /** Peripheral ADC0 base address */
AnnaBridge 171:3a7713b1edbc 534 #define ADC0_BASE (0x4003B000u)
AnnaBridge 171:3a7713b1edbc 535 /** Peripheral ADC0 base pointer */
AnnaBridge 171:3a7713b1edbc 536 #define ADC0 ((ADC_Type *)ADC0_BASE)
AnnaBridge 171:3a7713b1edbc 537 /** Array initializer of ADC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 538 #define ADC_BASE_ADDRS { ADC0_BASE }
AnnaBridge 171:3a7713b1edbc 539 /** Array initializer of ADC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 540 #define ADC_BASE_PTRS { ADC0 }
AnnaBridge 171:3a7713b1edbc 541 /** Interrupt vectors for the ADC peripheral type */
AnnaBridge 171:3a7713b1edbc 542 #define ADC_IRQS { ADC0_IRQn }
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544 /*!
AnnaBridge 171:3a7713b1edbc 545 * @}
AnnaBridge 171:3a7713b1edbc 546 */ /* end of group ADC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 547
AnnaBridge 171:3a7713b1edbc 548
AnnaBridge 171:3a7713b1edbc 549 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 550 -- ANT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 551 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 552
AnnaBridge 171:3a7713b1edbc 553 /*!
AnnaBridge 171:3a7713b1edbc 554 * @addtogroup ANT_Peripheral_Access_Layer ANT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 555 * @{
AnnaBridge 171:3a7713b1edbc 556 */
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 /** ANT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 559 typedef struct {
AnnaBridge 171:3a7713b1edbc 560 __IO uint32_t IRQ_CTRL; /**< IRQ CONTROL, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 561 __IO uint32_t EVENT_TMR; /**< EVENT TIMER, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 562 __IO uint32_t T1_CMP; /**< T1 COMPARE, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 563 __IO uint32_t T2_CMP; /**< T2 COMPARE, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 564 __I uint32_t TIMESTAMP; /**< TIMESTAMP, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 565 __IO uint32_t XCVR_CTRL; /**< TRANSCEIVER CONTROL, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 566 __I uint32_t XCVR_STS; /**< TRANSCEIVER STATUS, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 567 __IO uint32_t XCVR_CFG; /**< TRANSCEIVER CONFIGURATION, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 568 __IO uint32_t CHANNEL_NUM; /**< CHANNEL NUMBER, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 569 __IO uint32_t TX_POWER; /**< TRANSMIT POWER, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 570 __IO uint32_t NTW_ADR_CTRL; /**< NETWORK ADDRESS CONTROL, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 571 __IO uint32_t NTW_ADR_0; /**< NETWORK ADDRESS 0, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 572 __IO uint32_t NTW_ADR_1; /**< NETWORK ADDRESS 1, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 573 __IO uint32_t NTW_ADR_2; /**< NETWORK ADDRESS 2, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 574 __IO uint32_t NTW_ADR_3; /**< NETWORK ADDRESS 3, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 575 __IO uint32_t RX_WATERMARK; /**< RX WATERMARK, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 576 __IO uint32_t DSM_CTRL; /**< DSM CONTROL, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 577 __I uint32_t PART_ID; /**< PART ID, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 578 uint8_t RESERVED_0[184];
AnnaBridge 171:3a7713b1edbc 579 __IO uint16_t PACKET_BUFFER[64]; /**< PACKET BUFFER, array offset: 0x100, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 580 } ANT_Type;
AnnaBridge 171:3a7713b1edbc 581
AnnaBridge 171:3a7713b1edbc 582 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 583 -- ANT Register Masks
AnnaBridge 171:3a7713b1edbc 584 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 585
AnnaBridge 171:3a7713b1edbc 586 /*!
AnnaBridge 171:3a7713b1edbc 587 * @addtogroup ANT_Register_Masks ANT Register Masks
AnnaBridge 171:3a7713b1edbc 588 * @{
AnnaBridge 171:3a7713b1edbc 589 */
AnnaBridge 171:3a7713b1edbc 590
AnnaBridge 171:3a7713b1edbc 591 /*! @name IRQ_CTRL - IRQ CONTROL */
AnnaBridge 171:3a7713b1edbc 592 #define ANT_IRQ_CTRL_SEQ_END_IRQ_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 593 #define ANT_IRQ_CTRL_SEQ_END_IRQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 594 #define ANT_IRQ_CTRL_SEQ_END_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_SEQ_END_IRQ_SHIFT)) & ANT_IRQ_CTRL_SEQ_END_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 595 #define ANT_IRQ_CTRL_TX_IRQ_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 596 #define ANT_IRQ_CTRL_TX_IRQ_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 597 #define ANT_IRQ_CTRL_TX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TX_IRQ_SHIFT)) & ANT_IRQ_CTRL_TX_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 598 #define ANT_IRQ_CTRL_RX_IRQ_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 599 #define ANT_IRQ_CTRL_RX_IRQ_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 600 #define ANT_IRQ_CTRL_RX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_IRQ_SHIFT)) & ANT_IRQ_CTRL_RX_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 601 #define ANT_IRQ_CTRL_NTW_ADR_IRQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 602 #define ANT_IRQ_CTRL_NTW_ADR_IRQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 603 #define ANT_IRQ_CTRL_NTW_ADR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_NTW_ADR_IRQ_SHIFT)) & ANT_IRQ_CTRL_NTW_ADR_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 604 #define ANT_IRQ_CTRL_T1_IRQ_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 605 #define ANT_IRQ_CTRL_T1_IRQ_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 606 #define ANT_IRQ_CTRL_T1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T1_IRQ_SHIFT)) & ANT_IRQ_CTRL_T1_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 607 #define ANT_IRQ_CTRL_T2_IRQ_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 608 #define ANT_IRQ_CTRL_T2_IRQ_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 609 #define ANT_IRQ_CTRL_T2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T2_IRQ_SHIFT)) & ANT_IRQ_CTRL_T2_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 610 #define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 611 #define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 612 #define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT)) & ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 613 #define ANT_IRQ_CTRL_WAKE_IRQ_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 614 #define ANT_IRQ_CTRL_WAKE_IRQ_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 615 #define ANT_IRQ_CTRL_WAKE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_WAKE_IRQ_SHIFT)) & ANT_IRQ_CTRL_WAKE_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 616 #define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 617 #define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 618 #define ANT_IRQ_CTRL_RX_WATERMARK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT)) & ANT_IRQ_CTRL_RX_WATERMARK_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 619 #define ANT_IRQ_CTRL_TSM_IRQ_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 620 #define ANT_IRQ_CTRL_TSM_IRQ_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 621 #define ANT_IRQ_CTRL_TSM_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TSM_IRQ_SHIFT)) & ANT_IRQ_CTRL_TSM_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 622 #define ANT_IRQ_CTRL_SEQ_END_IRQ_EN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 623 #define ANT_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 624 #define ANT_IRQ_CTRL_SEQ_END_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_SEQ_END_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 625 #define ANT_IRQ_CTRL_TX_IRQ_EN_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 626 #define ANT_IRQ_CTRL_TX_IRQ_EN_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 627 #define ANT_IRQ_CTRL_TX_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TX_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_TX_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 628 #define ANT_IRQ_CTRL_RX_IRQ_EN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 629 #define ANT_IRQ_CTRL_RX_IRQ_EN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 630 #define ANT_IRQ_CTRL_RX_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_RX_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 631 #define ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 632 #define ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 633 #define ANT_IRQ_CTRL_NTW_ADR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 634 #define ANT_IRQ_CTRL_T1_IRQ_EN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 635 #define ANT_IRQ_CTRL_T1_IRQ_EN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 636 #define ANT_IRQ_CTRL_T1_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T1_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_T1_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 637 #define ANT_IRQ_CTRL_T2_IRQ_EN_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 638 #define ANT_IRQ_CTRL_T2_IRQ_EN_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 639 #define ANT_IRQ_CTRL_T2_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_T2_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_T2_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 640 #define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 641 #define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 642 #define ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 643 #define ANT_IRQ_CTRL_WAKE_IRQ_EN_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 644 #define ANT_IRQ_CTRL_WAKE_IRQ_EN_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 645 #define ANT_IRQ_CTRL_WAKE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_WAKE_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_WAKE_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 646 #define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 647 #define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 648 #define ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 649 #define ANT_IRQ_CTRL_TSM_IRQ_EN_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 650 #define ANT_IRQ_CTRL_TSM_IRQ_EN_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 651 #define ANT_IRQ_CTRL_TSM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_TSM_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_TSM_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 652 #define ANT_IRQ_CTRL_ANT_IRQ_EN_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 653 #define ANT_IRQ_CTRL_ANT_IRQ_EN_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 654 #define ANT_IRQ_CTRL_ANT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_ANT_IRQ_EN_SHIFT)) & ANT_IRQ_CTRL_ANT_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 655 #define ANT_IRQ_CTRL_CRC_IGNORE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 656 #define ANT_IRQ_CTRL_CRC_IGNORE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 657 #define ANT_IRQ_CTRL_CRC_IGNORE(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_CRC_IGNORE_SHIFT)) & ANT_IRQ_CTRL_CRC_IGNORE_MASK)
AnnaBridge 171:3a7713b1edbc 658 #define ANT_IRQ_CTRL_CRC_VALID_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 659 #define ANT_IRQ_CTRL_CRC_VALID_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 660 #define ANT_IRQ_CTRL_CRC_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANT_IRQ_CTRL_CRC_VALID_SHIFT)) & ANT_IRQ_CTRL_CRC_VALID_MASK)
AnnaBridge 171:3a7713b1edbc 661
AnnaBridge 171:3a7713b1edbc 662 /*! @name EVENT_TMR - EVENT TIMER */
AnnaBridge 171:3a7713b1edbc 663 #define ANT_EVENT_TMR_EVENT_TMR_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 664 #define ANT_EVENT_TMR_EVENT_TMR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 665 #define ANT_EVENT_TMR_EVENT_TMR(x) (((uint32_t)(((uint32_t)(x)) << ANT_EVENT_TMR_EVENT_TMR_SHIFT)) & ANT_EVENT_TMR_EVENT_TMR_MASK)
AnnaBridge 171:3a7713b1edbc 666 #define ANT_EVENT_TMR_EVENT_TMR_LD_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 667 #define ANT_EVENT_TMR_EVENT_TMR_LD_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 668 #define ANT_EVENT_TMR_EVENT_TMR_LD(x) (((uint32_t)(((uint32_t)(x)) << ANT_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & ANT_EVENT_TMR_EVENT_TMR_LD_MASK)
AnnaBridge 171:3a7713b1edbc 669 #define ANT_EVENT_TMR_EVENT_TMR_ADD_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 670 #define ANT_EVENT_TMR_EVENT_TMR_ADD_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 671 #define ANT_EVENT_TMR_EVENT_TMR_ADD(x) (((uint32_t)(((uint32_t)(x)) << ANT_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & ANT_EVENT_TMR_EVENT_TMR_ADD_MASK)
AnnaBridge 171:3a7713b1edbc 672
AnnaBridge 171:3a7713b1edbc 673 /*! @name T1_CMP - T1 COMPARE */
AnnaBridge 171:3a7713b1edbc 674 #define ANT_T1_CMP_T1_CMP_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 675 #define ANT_T1_CMP_T1_CMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 676 #define ANT_T1_CMP_T1_CMP(x) (((uint32_t)(((uint32_t)(x)) << ANT_T1_CMP_T1_CMP_SHIFT)) & ANT_T1_CMP_T1_CMP_MASK)
AnnaBridge 171:3a7713b1edbc 677 #define ANT_T1_CMP_T1_CMP_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 678 #define ANT_T1_CMP_T1_CMP_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 679 #define ANT_T1_CMP_T1_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_T1_CMP_T1_CMP_EN_SHIFT)) & ANT_T1_CMP_T1_CMP_EN_MASK)
AnnaBridge 171:3a7713b1edbc 680
AnnaBridge 171:3a7713b1edbc 681 /*! @name T2_CMP - T2 COMPARE */
AnnaBridge 171:3a7713b1edbc 682 #define ANT_T2_CMP_T2_CMP_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 683 #define ANT_T2_CMP_T2_CMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 684 #define ANT_T2_CMP_T2_CMP(x) (((uint32_t)(((uint32_t)(x)) << ANT_T2_CMP_T2_CMP_SHIFT)) & ANT_T2_CMP_T2_CMP_MASK)
AnnaBridge 171:3a7713b1edbc 685 #define ANT_T2_CMP_T2_CMP_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 686 #define ANT_T2_CMP_T2_CMP_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 687 #define ANT_T2_CMP_T2_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_T2_CMP_T2_CMP_EN_SHIFT)) & ANT_T2_CMP_T2_CMP_EN_MASK)
AnnaBridge 171:3a7713b1edbc 688
AnnaBridge 171:3a7713b1edbc 689 /*! @name TIMESTAMP - TIMESTAMP */
AnnaBridge 171:3a7713b1edbc 690 #define ANT_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 691 #define ANT_TIMESTAMP_TIMESTAMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 692 #define ANT_TIMESTAMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ANT_TIMESTAMP_TIMESTAMP_SHIFT)) & ANT_TIMESTAMP_TIMESTAMP_MASK)
AnnaBridge 171:3a7713b1edbc 693
AnnaBridge 171:3a7713b1edbc 694 /*! @name XCVR_CTRL - TRANSCEIVER CONTROL */
AnnaBridge 171:3a7713b1edbc 695 #define ANT_XCVR_CTRL_SEQCMD_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 696 #define ANT_XCVR_CTRL_SEQCMD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 697 #define ANT_XCVR_CTRL_SEQCMD(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_SEQCMD_SHIFT)) & ANT_XCVR_CTRL_SEQCMD_MASK)
AnnaBridge 171:3a7713b1edbc 698 #define ANT_XCVR_CTRL_TX_PKT_LENGTH_MASK (0x3F00U)
AnnaBridge 171:3a7713b1edbc 699 #define ANT_XCVR_CTRL_TX_PKT_LENGTH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 700 #define ANT_XCVR_CTRL_TX_PKT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_TX_PKT_LENGTH_SHIFT)) & ANT_XCVR_CTRL_TX_PKT_LENGTH_MASK)
AnnaBridge 171:3a7713b1edbc 701 #define ANT_XCVR_CTRL_RX_PKT_LENGTH_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 702 #define ANT_XCVR_CTRL_RX_PKT_LENGTH_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 703 #define ANT_XCVR_CTRL_RX_PKT_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_RX_PKT_LENGTH_SHIFT)) & ANT_XCVR_CTRL_RX_PKT_LENGTH_MASK)
AnnaBridge 171:3a7713b1edbc 704 #define ANT_XCVR_CTRL_CMDDEC_CS_MASK (0x7000000U)
AnnaBridge 171:3a7713b1edbc 705 #define ANT_XCVR_CTRL_CMDDEC_CS_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 706 #define ANT_XCVR_CTRL_CMDDEC_CS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_CMDDEC_CS_SHIFT)) & ANT_XCVR_CTRL_CMDDEC_CS_MASK)
AnnaBridge 171:3a7713b1edbc 707 #define ANT_XCVR_CTRL_XCVR_BUSY_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 708 #define ANT_XCVR_CTRL_XCVR_BUSY_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 709 #define ANT_XCVR_CTRL_XCVR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CTRL_XCVR_BUSY_SHIFT)) & ANT_XCVR_CTRL_XCVR_BUSY_MASK)
AnnaBridge 171:3a7713b1edbc 710
AnnaBridge 171:3a7713b1edbc 711 /*! @name XCVR_STS - TRANSCEIVER STATUS */
AnnaBridge 171:3a7713b1edbc 712 #define ANT_XCVR_STS_TX_START_T1_PEND_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 713 #define ANT_XCVR_STS_TX_START_T1_PEND_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 714 #define ANT_XCVR_STS_TX_START_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_START_T1_PEND_SHIFT)) & ANT_XCVR_STS_TX_START_T1_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 715 #define ANT_XCVR_STS_TX_START_T2_PEND_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 716 #define ANT_XCVR_STS_TX_START_T2_PEND_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 717 #define ANT_XCVR_STS_TX_START_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_START_T2_PEND_SHIFT)) & ANT_XCVR_STS_TX_START_T2_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 718 #define ANT_XCVR_STS_TX_IN_WARMUP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 719 #define ANT_XCVR_STS_TX_IN_WARMUP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 720 #define ANT_XCVR_STS_TX_IN_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_IN_WARMUP_SHIFT)) & ANT_XCVR_STS_TX_IN_WARMUP_MASK)
AnnaBridge 171:3a7713b1edbc 721 #define ANT_XCVR_STS_TX_IN_PROGRESS_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 722 #define ANT_XCVR_STS_TX_IN_PROGRESS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 723 #define ANT_XCVR_STS_TX_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_IN_PROGRESS_SHIFT)) & ANT_XCVR_STS_TX_IN_PROGRESS_MASK)
AnnaBridge 171:3a7713b1edbc 724 #define ANT_XCVR_STS_TX_IN_WARMDN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 725 #define ANT_XCVR_STS_TX_IN_WARMDN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 726 #define ANT_XCVR_STS_TX_IN_WARMDN(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_TX_IN_WARMDN_SHIFT)) & ANT_XCVR_STS_TX_IN_WARMDN_MASK)
AnnaBridge 171:3a7713b1edbc 727 #define ANT_XCVR_STS_RX_START_T1_PEND_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 728 #define ANT_XCVR_STS_RX_START_T1_PEND_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 729 #define ANT_XCVR_STS_RX_START_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_START_T1_PEND_SHIFT)) & ANT_XCVR_STS_RX_START_T1_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 730 #define ANT_XCVR_STS_RX_START_T2_PEND_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 731 #define ANT_XCVR_STS_RX_START_T2_PEND_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 732 #define ANT_XCVR_STS_RX_START_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_START_T2_PEND_SHIFT)) & ANT_XCVR_STS_RX_START_T2_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 733 #define ANT_XCVR_STS_RX_STOP_T1_PEND_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 734 #define ANT_XCVR_STS_RX_STOP_T1_PEND_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 735 #define ANT_XCVR_STS_RX_STOP_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_STOP_T1_PEND_SHIFT)) & ANT_XCVR_STS_RX_STOP_T1_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 736 #define ANT_XCVR_STS_RX_STOP_T2_PEND_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 737 #define ANT_XCVR_STS_RX_STOP_T2_PEND_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 738 #define ANT_XCVR_STS_RX_STOP_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_STOP_T2_PEND_SHIFT)) & ANT_XCVR_STS_RX_STOP_T2_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 739 #define ANT_XCVR_STS_RX_IN_WARMUP_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 740 #define ANT_XCVR_STS_RX_IN_WARMUP_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 741 #define ANT_XCVR_STS_RX_IN_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_WARMUP_SHIFT)) & ANT_XCVR_STS_RX_IN_WARMUP_MASK)
AnnaBridge 171:3a7713b1edbc 742 #define ANT_XCVR_STS_RX_IN_SEARCH_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 743 #define ANT_XCVR_STS_RX_IN_SEARCH_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 744 #define ANT_XCVR_STS_RX_IN_SEARCH(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_SEARCH_SHIFT)) & ANT_XCVR_STS_RX_IN_SEARCH_MASK)
AnnaBridge 171:3a7713b1edbc 745 #define ANT_XCVR_STS_RX_IN_PROGRESS_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 746 #define ANT_XCVR_STS_RX_IN_PROGRESS_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 747 #define ANT_XCVR_STS_RX_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_PROGRESS_SHIFT)) & ANT_XCVR_STS_RX_IN_PROGRESS_MASK)
AnnaBridge 171:3a7713b1edbc 748 #define ANT_XCVR_STS_RX_IN_WARMDN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 749 #define ANT_XCVR_STS_RX_IN_WARMDN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 750 #define ANT_XCVR_STS_RX_IN_WARMDN(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RX_IN_WARMDN_SHIFT)) & ANT_XCVR_STS_RX_IN_WARMDN_MASK)
AnnaBridge 171:3a7713b1edbc 751 #define ANT_XCVR_STS_CRC_VALID_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 752 #define ANT_XCVR_STS_CRC_VALID_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 753 #define ANT_XCVR_STS_CRC_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_CRC_VALID_SHIFT)) & ANT_XCVR_STS_CRC_VALID_MASK)
AnnaBridge 171:3a7713b1edbc 754 #define ANT_XCVR_STS_RSSI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 755 #define ANT_XCVR_STS_RSSI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 756 #define ANT_XCVR_STS_RSSI(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_STS_RSSI_SHIFT)) & ANT_XCVR_STS_RSSI_MASK)
AnnaBridge 171:3a7713b1edbc 757
AnnaBridge 171:3a7713b1edbc 758 /*! @name XCVR_CFG - TRANSCEIVER CONFIGURATION */
AnnaBridge 171:3a7713b1edbc 759 #define ANT_XCVR_CFG_TX_WHITEN_DIS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 760 #define ANT_XCVR_CFG_TX_WHITEN_DIS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 761 #define ANT_XCVR_CFG_TX_WHITEN_DIS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_TX_WHITEN_DIS_SHIFT)) & ANT_XCVR_CFG_TX_WHITEN_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 762 #define ANT_XCVR_CFG_RX_DEWHITEN_DIS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 763 #define ANT_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 764 #define ANT_XCVR_CFG_RX_DEWHITEN_DIS(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT)) & ANT_XCVR_CFG_RX_DEWHITEN_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 765 #define ANT_XCVR_CFG_SW_CRC_EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 766 #define ANT_XCVR_CFG_SW_CRC_EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 767 #define ANT_XCVR_CFG_SW_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_SW_CRC_EN_SHIFT)) & ANT_XCVR_CFG_SW_CRC_EN_MASK)
AnnaBridge 171:3a7713b1edbc 768 #define ANT_XCVR_CFG_PREAMBLE_SZ_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 769 #define ANT_XCVR_CFG_PREAMBLE_SZ_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 770 #define ANT_XCVR_CFG_PREAMBLE_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_PREAMBLE_SZ_SHIFT)) & ANT_XCVR_CFG_PREAMBLE_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 771 #define ANT_XCVR_CFG_TX_WARMUP_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 772 #define ANT_XCVR_CFG_TX_WARMUP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 773 #define ANT_XCVR_CFG_TX_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_TX_WARMUP_SHIFT)) & ANT_XCVR_CFG_TX_WARMUP_MASK)
AnnaBridge 171:3a7713b1edbc 774 #define ANT_XCVR_CFG_RX_WARMUP_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 775 #define ANT_XCVR_CFG_RX_WARMUP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 776 #define ANT_XCVR_CFG_RX_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ANT_XCVR_CFG_RX_WARMUP_SHIFT)) & ANT_XCVR_CFG_RX_WARMUP_MASK)
AnnaBridge 171:3a7713b1edbc 777
AnnaBridge 171:3a7713b1edbc 778 /*! @name CHANNEL_NUM - CHANNEL NUMBER */
AnnaBridge 171:3a7713b1edbc 779 #define ANT_CHANNEL_NUM_CHANNEL_NUM_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 780 #define ANT_CHANNEL_NUM_CHANNEL_NUM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 781 #define ANT_CHANNEL_NUM_CHANNEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANT_CHANNEL_NUM_CHANNEL_NUM_SHIFT)) & ANT_CHANNEL_NUM_CHANNEL_NUM_MASK)
AnnaBridge 171:3a7713b1edbc 782
AnnaBridge 171:3a7713b1edbc 783 /*! @name TX_POWER - TRANSMIT POWER */
AnnaBridge 171:3a7713b1edbc 784 #define ANT_TX_POWER_TX_POWER_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 785 #define ANT_TX_POWER_TX_POWER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 786 #define ANT_TX_POWER_TX_POWER(x) (((uint32_t)(((uint32_t)(x)) << ANT_TX_POWER_TX_POWER_SHIFT)) & ANT_TX_POWER_TX_POWER_MASK)
AnnaBridge 171:3a7713b1edbc 787
AnnaBridge 171:3a7713b1edbc 788 /*! @name NTW_ADR_CTRL - NETWORK ADDRESS CONTROL */
AnnaBridge 171:3a7713b1edbc 789 #define ANT_NTW_ADR_CTRL_NTW_ADR_EN_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 790 #define ANT_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 791 #define ANT_NTW_ADR_CTRL_NTW_ADR_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_EN_MASK)
AnnaBridge 171:3a7713b1edbc 792 #define ANT_NTW_ADR_CTRL_NTW_ADR_MCH_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 793 #define ANT_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 794 #define ANT_NTW_ADR_CTRL_NTW_ADR_MCH(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_MCH_MASK)
AnnaBridge 171:3a7713b1edbc 795 #define ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 796 #define ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 797 #define ANT_NTW_ADR_CTRL_NTW_ADR0_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 798 #define ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK (0xC00U)
AnnaBridge 171:3a7713b1edbc 799 #define ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 800 #define ANT_NTW_ADR_CTRL_NTW_ADR1_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 801 #define ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 802 #define ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 803 #define ANT_NTW_ADR_CTRL_NTW_ADR2_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 804 #define ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 805 #define ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 806 #define ANT_NTW_ADR_CTRL_NTW_ADR3_SZ(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 807 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR0_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 808 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 809 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR0(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR0_MASK)
AnnaBridge 171:3a7713b1edbc 810 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR1_MASK (0x700000U)
AnnaBridge 171:3a7713b1edbc 811 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 812 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR1(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR1_MASK)
AnnaBridge 171:3a7713b1edbc 813 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR2_MASK (0x7000000U)
AnnaBridge 171:3a7713b1edbc 814 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 815 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR2(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR2_MASK)
AnnaBridge 171:3a7713b1edbc 816 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR3_MASK (0x70000000U)
AnnaBridge 171:3a7713b1edbc 817 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 818 #define ANT_NTW_ADR_CTRL_NTW_ADR_THR3(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT)) & ANT_NTW_ADR_CTRL_NTW_ADR_THR3_MASK)
AnnaBridge 171:3a7713b1edbc 819
AnnaBridge 171:3a7713b1edbc 820 /*! @name NTW_ADR_0 - NETWORK ADDRESS 0 */
AnnaBridge 171:3a7713b1edbc 821 #define ANT_NTW_ADR_0_NTW_ADR_0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 822 #define ANT_NTW_ADR_0_NTW_ADR_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 823 #define ANT_NTW_ADR_0_NTW_ADR_0(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_0_NTW_ADR_0_SHIFT)) & ANT_NTW_ADR_0_NTW_ADR_0_MASK)
AnnaBridge 171:3a7713b1edbc 824
AnnaBridge 171:3a7713b1edbc 825 /*! @name NTW_ADR_1 - NETWORK ADDRESS 1 */
AnnaBridge 171:3a7713b1edbc 826 #define ANT_NTW_ADR_1_NTW_ADR_1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 827 #define ANT_NTW_ADR_1_NTW_ADR_1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 828 #define ANT_NTW_ADR_1_NTW_ADR_1(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_1_NTW_ADR_1_SHIFT)) & ANT_NTW_ADR_1_NTW_ADR_1_MASK)
AnnaBridge 171:3a7713b1edbc 829
AnnaBridge 171:3a7713b1edbc 830 /*! @name NTW_ADR_2 - NETWORK ADDRESS 2 */
AnnaBridge 171:3a7713b1edbc 831 #define ANT_NTW_ADR_2_NTW_ADR_2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 832 #define ANT_NTW_ADR_2_NTW_ADR_2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 833 #define ANT_NTW_ADR_2_NTW_ADR_2(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_2_NTW_ADR_2_SHIFT)) & ANT_NTW_ADR_2_NTW_ADR_2_MASK)
AnnaBridge 171:3a7713b1edbc 834
AnnaBridge 171:3a7713b1edbc 835 /*! @name NTW_ADR_3 - NETWORK ADDRESS 3 */
AnnaBridge 171:3a7713b1edbc 836 #define ANT_NTW_ADR_3_NTW_ADR_3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 837 #define ANT_NTW_ADR_3_NTW_ADR_3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 838 #define ANT_NTW_ADR_3_NTW_ADR_3(x) (((uint32_t)(((uint32_t)(x)) << ANT_NTW_ADR_3_NTW_ADR_3_SHIFT)) & ANT_NTW_ADR_3_NTW_ADR_3_MASK)
AnnaBridge 171:3a7713b1edbc 839
AnnaBridge 171:3a7713b1edbc 840 /*! @name RX_WATERMARK - RX WATERMARK */
AnnaBridge 171:3a7713b1edbc 841 #define ANT_RX_WATERMARK_RX_WATERMARK_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 842 #define ANT_RX_WATERMARK_RX_WATERMARK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 843 #define ANT_RX_WATERMARK_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << ANT_RX_WATERMARK_RX_WATERMARK_SHIFT)) & ANT_RX_WATERMARK_RX_WATERMARK_MASK)
AnnaBridge 171:3a7713b1edbc 844 #define ANT_RX_WATERMARK_BYTE_COUNTER_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 845 #define ANT_RX_WATERMARK_BYTE_COUNTER_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 846 #define ANT_RX_WATERMARK_BYTE_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << ANT_RX_WATERMARK_BYTE_COUNTER_SHIFT)) & ANT_RX_WATERMARK_BYTE_COUNTER_MASK)
AnnaBridge 171:3a7713b1edbc 847
AnnaBridge 171:3a7713b1edbc 848 /*! @name DSM_CTRL - DSM CONTROL */
AnnaBridge 171:3a7713b1edbc 849 #define ANT_DSM_CTRL_ANT_SLEEP_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 850 #define ANT_DSM_CTRL_ANT_SLEEP_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 851 #define ANT_DSM_CTRL_ANT_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANT_DSM_CTRL_ANT_SLEEP_EN_SHIFT)) & ANT_DSM_CTRL_ANT_SLEEP_EN_MASK)
AnnaBridge 171:3a7713b1edbc 852
AnnaBridge 171:3a7713b1edbc 853 /*! @name PART_ID - PART ID */
AnnaBridge 171:3a7713b1edbc 854 #define ANT_PART_ID_PART_ID_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 855 #define ANT_PART_ID_PART_ID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 856 #define ANT_PART_ID_PART_ID(x) (((uint32_t)(((uint32_t)(x)) << ANT_PART_ID_PART_ID_SHIFT)) & ANT_PART_ID_PART_ID_MASK)
AnnaBridge 171:3a7713b1edbc 857
AnnaBridge 171:3a7713b1edbc 858 /*! @name PACKET_BUFFER - PACKET BUFFER */
AnnaBridge 171:3a7713b1edbc 859 #define ANT_PACKET_BUFFER_PACKET_BUFFER_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 860 #define ANT_PACKET_BUFFER_PACKET_BUFFER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 861 #define ANT_PACKET_BUFFER_PACKET_BUFFER(x) (((uint16_t)(((uint16_t)(x)) << ANT_PACKET_BUFFER_PACKET_BUFFER_SHIFT)) & ANT_PACKET_BUFFER_PACKET_BUFFER_MASK)
AnnaBridge 171:3a7713b1edbc 862
AnnaBridge 171:3a7713b1edbc 863 /* The count of ANT_PACKET_BUFFER */
AnnaBridge 171:3a7713b1edbc 864 #define ANT_PACKET_BUFFER_COUNT (64U)
AnnaBridge 171:3a7713b1edbc 865
AnnaBridge 171:3a7713b1edbc 866
AnnaBridge 171:3a7713b1edbc 867 /*!
AnnaBridge 171:3a7713b1edbc 868 * @}
AnnaBridge 171:3a7713b1edbc 869 */ /* end of group ANT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 870
AnnaBridge 171:3a7713b1edbc 871
AnnaBridge 171:3a7713b1edbc 872 /* ANT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 873 /** Peripheral ANT base address */
AnnaBridge 171:3a7713b1edbc 874 #define ANT_BASE (0x4005E000u)
AnnaBridge 171:3a7713b1edbc 875 /** Peripheral ANT base pointer */
AnnaBridge 171:3a7713b1edbc 876 #define ANT ((ANT_Type *)ANT_BASE)
AnnaBridge 171:3a7713b1edbc 877 /** Array initializer of ANT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 878 #define ANT_BASE_ADDRS { ANT_BASE }
AnnaBridge 171:3a7713b1edbc 879 /** Array initializer of ANT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 880 #define ANT_BASE_PTRS { ANT }
AnnaBridge 171:3a7713b1edbc 881
AnnaBridge 171:3a7713b1edbc 882 /*!
AnnaBridge 171:3a7713b1edbc 883 * @}
AnnaBridge 171:3a7713b1edbc 884 */ /* end of group ANT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 885
AnnaBridge 171:3a7713b1edbc 886
AnnaBridge 171:3a7713b1edbc 887 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 888 -- BTLE_RF Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 889 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 890
AnnaBridge 171:3a7713b1edbc 891 /*!
AnnaBridge 171:3a7713b1edbc 892 * @addtogroup BTLE_RF_Peripheral_Access_Layer BTLE_RF Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 893 * @{
AnnaBridge 171:3a7713b1edbc 894 */
AnnaBridge 171:3a7713b1edbc 895
AnnaBridge 171:3a7713b1edbc 896 /** BTLE_RF - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 897 typedef struct {
AnnaBridge 171:3a7713b1edbc 898 uint8_t RESERVED_0[1536];
AnnaBridge 171:3a7713b1edbc 899 __I uint16_t BLE_PART_ID; /**< BLUETOOTH LOW ENERGY PART ID, offset: 0x600 */
AnnaBridge 171:3a7713b1edbc 900 uint8_t RESERVED_1[2];
AnnaBridge 171:3a7713b1edbc 901 __I uint16_t DSM_STATUS; /**< BLE DSM STATUS, offset: 0x604 */
AnnaBridge 171:3a7713b1edbc 902 uint8_t RESERVED_2[2];
AnnaBridge 171:3a7713b1edbc 903 __IO uint16_t MISC_CTRL; /**< BLUETOOTH LOW ENERGY MISCELLANEOUS CONTROL, offset: 0x608 */
AnnaBridge 171:3a7713b1edbc 904 } BTLE_RF_Type;
AnnaBridge 171:3a7713b1edbc 905
AnnaBridge 171:3a7713b1edbc 906 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 907 -- BTLE_RF Register Masks
AnnaBridge 171:3a7713b1edbc 908 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 909
AnnaBridge 171:3a7713b1edbc 910 /*!
AnnaBridge 171:3a7713b1edbc 911 * @addtogroup BTLE_RF_Register_Masks BTLE_RF Register Masks
AnnaBridge 171:3a7713b1edbc 912 * @{
AnnaBridge 171:3a7713b1edbc 913 */
AnnaBridge 171:3a7713b1edbc 914
AnnaBridge 171:3a7713b1edbc 915 /*! @name BLE_PART_ID - BLUETOOTH LOW ENERGY PART ID */
AnnaBridge 171:3a7713b1edbc 916 #define BTLE_RF_BLE_PART_ID_BLE_PART_ID_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 917 #define BTLE_RF_BLE_PART_ID_BLE_PART_ID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 918 #define BTLE_RF_BLE_PART_ID_BLE_PART_ID(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_BLE_PART_ID_BLE_PART_ID_SHIFT)) & BTLE_RF_BLE_PART_ID_BLE_PART_ID_MASK)
AnnaBridge 171:3a7713b1edbc 919
AnnaBridge 171:3a7713b1edbc 920 /*! @name DSM_STATUS - BLE DSM STATUS */
AnnaBridge 171:3a7713b1edbc 921 #define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 922 #define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 923 #define BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT)) & BTLE_RF_DSM_STATUS_ORF_SYSCLK_REQ_MASK)
AnnaBridge 171:3a7713b1edbc 924 #define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 925 #define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 926 #define BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_SHIFT)) & BTLE_RF_DSM_STATUS_RIF_LL_ACTIVE_MASK)
AnnaBridge 171:3a7713b1edbc 927 #define BTLE_RF_DSM_STATUS_XCVR_BUSY_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 928 #define BTLE_RF_DSM_STATUS_XCVR_BUSY_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 929 #define BTLE_RF_DSM_STATUS_XCVR_BUSY(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_DSM_STATUS_XCVR_BUSY_SHIFT)) & BTLE_RF_DSM_STATUS_XCVR_BUSY_MASK)
AnnaBridge 171:3a7713b1edbc 930
AnnaBridge 171:3a7713b1edbc 931 /*! @name MISC_CTRL - BLUETOOTH LOW ENERGY MISCELLANEOUS CONTROL */
AnnaBridge 171:3a7713b1edbc 932 #define BTLE_RF_MISC_CTRL_TSM_INTR_EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 933 #define BTLE_RF_MISC_CTRL_TSM_INTR_EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 934 #define BTLE_RF_MISC_CTRL_TSM_INTR_EN(x) (((uint16_t)(((uint16_t)(x)) << BTLE_RF_MISC_CTRL_TSM_INTR_EN_SHIFT)) & BTLE_RF_MISC_CTRL_TSM_INTR_EN_MASK)
AnnaBridge 171:3a7713b1edbc 935
AnnaBridge 171:3a7713b1edbc 936
AnnaBridge 171:3a7713b1edbc 937 /*!
AnnaBridge 171:3a7713b1edbc 938 * @}
AnnaBridge 171:3a7713b1edbc 939 */ /* end of group BTLE_RF_Register_Masks */
AnnaBridge 171:3a7713b1edbc 940
AnnaBridge 171:3a7713b1edbc 941
AnnaBridge 171:3a7713b1edbc 942 /* BTLE_RF - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 943 /** Peripheral BTLE_RF base address */
AnnaBridge 171:3a7713b1edbc 944 #define BTLE_RF_BASE (0x4005B000u)
AnnaBridge 171:3a7713b1edbc 945 /** Peripheral BTLE_RF base pointer */
AnnaBridge 171:3a7713b1edbc 946 #define BTLE_RF ((BTLE_RF_Type *)BTLE_RF_BASE)
AnnaBridge 171:3a7713b1edbc 947 /** Array initializer of BTLE_RF peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 948 #define BTLE_RF_BASE_ADDRS { BTLE_RF_BASE }
AnnaBridge 171:3a7713b1edbc 949 /** Array initializer of BTLE_RF peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 950 #define BTLE_RF_BASE_PTRS { BTLE_RF }
AnnaBridge 171:3a7713b1edbc 951
AnnaBridge 171:3a7713b1edbc 952 /*!
AnnaBridge 171:3a7713b1edbc 953 * @}
AnnaBridge 171:3a7713b1edbc 954 */ /* end of group BTLE_RF_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 955
AnnaBridge 171:3a7713b1edbc 956
AnnaBridge 171:3a7713b1edbc 957 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 958 -- CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 959 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 960
AnnaBridge 171:3a7713b1edbc 961 /*!
AnnaBridge 171:3a7713b1edbc 962 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 963 * @{
AnnaBridge 171:3a7713b1edbc 964 */
AnnaBridge 171:3a7713b1edbc 965
AnnaBridge 171:3a7713b1edbc 966 /** CMP - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 967 typedef struct {
AnnaBridge 171:3a7713b1edbc 968 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 969 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 970 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 971 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 972 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 973 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 974 } CMP_Type;
AnnaBridge 171:3a7713b1edbc 975
AnnaBridge 171:3a7713b1edbc 976 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 977 -- CMP Register Masks
AnnaBridge 171:3a7713b1edbc 978 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 979
AnnaBridge 171:3a7713b1edbc 980 /*!
AnnaBridge 171:3a7713b1edbc 981 * @addtogroup CMP_Register_Masks CMP Register Masks
AnnaBridge 171:3a7713b1edbc 982 * @{
AnnaBridge 171:3a7713b1edbc 983 */
AnnaBridge 171:3a7713b1edbc 984
AnnaBridge 171:3a7713b1edbc 985 /*! @name CR0 - CMP Control Register 0 */
AnnaBridge 171:3a7713b1edbc 986 #define CMP_CR0_HYSTCTR_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 987 #define CMP_CR0_HYSTCTR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 988 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
AnnaBridge 171:3a7713b1edbc 989 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 990 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 991 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 992
AnnaBridge 171:3a7713b1edbc 993 /*! @name CR1 - CMP Control Register 1 */
AnnaBridge 171:3a7713b1edbc 994 #define CMP_CR1_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 995 #define CMP_CR1_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 996 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
AnnaBridge 171:3a7713b1edbc 997 #define CMP_CR1_OPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 998 #define CMP_CR1_OPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 999 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
AnnaBridge 171:3a7713b1edbc 1000 #define CMP_CR1_COS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1001 #define CMP_CR1_COS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1002 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
AnnaBridge 171:3a7713b1edbc 1003 #define CMP_CR1_INV_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1004 #define CMP_CR1_INV_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1005 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
AnnaBridge 171:3a7713b1edbc 1006 #define CMP_CR1_PMODE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1007 #define CMP_CR1_PMODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1008 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
AnnaBridge 171:3a7713b1edbc 1009 #define CMP_CR1_TRIGM_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1010 #define CMP_CR1_TRIGM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1011 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
AnnaBridge 171:3a7713b1edbc 1012 #define CMP_CR1_WE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1013 #define CMP_CR1_WE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1014 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
AnnaBridge 171:3a7713b1edbc 1015 #define CMP_CR1_SE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1016 #define CMP_CR1_SE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1017 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
AnnaBridge 171:3a7713b1edbc 1018
AnnaBridge 171:3a7713b1edbc 1019 /*! @name FPR - CMP Filter Period Register */
AnnaBridge 171:3a7713b1edbc 1020 #define CMP_FPR_FILT_PER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1021 #define CMP_FPR_FILT_PER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1022 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
AnnaBridge 171:3a7713b1edbc 1023
AnnaBridge 171:3a7713b1edbc 1024 /*! @name SCR - CMP Status and Control Register */
AnnaBridge 171:3a7713b1edbc 1025 #define CMP_SCR_COUT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1026 #define CMP_SCR_COUT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1027 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
AnnaBridge 171:3a7713b1edbc 1028 #define CMP_SCR_CFF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1029 #define CMP_SCR_CFF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1030 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
AnnaBridge 171:3a7713b1edbc 1031 #define CMP_SCR_CFR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1032 #define CMP_SCR_CFR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1033 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
AnnaBridge 171:3a7713b1edbc 1034 #define CMP_SCR_IEF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1035 #define CMP_SCR_IEF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1036 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
AnnaBridge 171:3a7713b1edbc 1037 #define CMP_SCR_IER_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1038 #define CMP_SCR_IER_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1039 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
AnnaBridge 171:3a7713b1edbc 1040 #define CMP_SCR_DMAEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1041 #define CMP_SCR_DMAEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1042 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 1043
AnnaBridge 171:3a7713b1edbc 1044 /*! @name DACCR - DAC Control Register */
AnnaBridge 171:3a7713b1edbc 1045 #define CMP_DACCR_VOSEL_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 1046 #define CMP_DACCR_VOSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1047 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1048 #define CMP_DACCR_VRSEL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1049 #define CMP_DACCR_VRSEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1050 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1051 #define CMP_DACCR_DACEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1052 #define CMP_DACCR_DACEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1053 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
AnnaBridge 171:3a7713b1edbc 1054
AnnaBridge 171:3a7713b1edbc 1055 /*! @name MUXCR - MUX Control Register */
AnnaBridge 171:3a7713b1edbc 1056 #define CMP_MUXCR_MSEL_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 1057 #define CMP_MUXCR_MSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1058 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1059 #define CMP_MUXCR_PSEL_MASK (0x38U)
AnnaBridge 171:3a7713b1edbc 1060 #define CMP_MUXCR_PSEL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1061 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1062 #define CMP_MUXCR_PSTM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1063 #define CMP_MUXCR_PSTM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1064 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
AnnaBridge 171:3a7713b1edbc 1065
AnnaBridge 171:3a7713b1edbc 1066
AnnaBridge 171:3a7713b1edbc 1067 /*!
AnnaBridge 171:3a7713b1edbc 1068 * @}
AnnaBridge 171:3a7713b1edbc 1069 */ /* end of group CMP_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1070
AnnaBridge 171:3a7713b1edbc 1071
AnnaBridge 171:3a7713b1edbc 1072 /* CMP - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1073 /** Peripheral CMP0 base address */
AnnaBridge 171:3a7713b1edbc 1074 #define CMP0_BASE (0x40073000u)
AnnaBridge 171:3a7713b1edbc 1075 /** Peripheral CMP0 base pointer */
AnnaBridge 171:3a7713b1edbc 1076 #define CMP0 ((CMP_Type *)CMP0_BASE)
AnnaBridge 171:3a7713b1edbc 1077 /** Array initializer of CMP peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1078 #define CMP_BASE_ADDRS { CMP0_BASE }
AnnaBridge 171:3a7713b1edbc 1079 /** Array initializer of CMP peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1080 #define CMP_BASE_PTRS { CMP0 }
AnnaBridge 171:3a7713b1edbc 1081 /** Interrupt vectors for the CMP peripheral type */
AnnaBridge 171:3a7713b1edbc 1082 #define CMP_IRQS { CMP0_IRQn }
AnnaBridge 171:3a7713b1edbc 1083
AnnaBridge 171:3a7713b1edbc 1084 /*!
AnnaBridge 171:3a7713b1edbc 1085 * @}
AnnaBridge 171:3a7713b1edbc 1086 */ /* end of group CMP_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1087
AnnaBridge 171:3a7713b1edbc 1088
AnnaBridge 171:3a7713b1edbc 1089 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1090 -- CMT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1091 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1092
AnnaBridge 171:3a7713b1edbc 1093 /*!
AnnaBridge 171:3a7713b1edbc 1094 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1095 * @{
AnnaBridge 171:3a7713b1edbc 1096 */
AnnaBridge 171:3a7713b1edbc 1097
AnnaBridge 171:3a7713b1edbc 1098 /** CMT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1099 typedef struct {
AnnaBridge 171:3a7713b1edbc 1100 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1101 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 1102 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 1103 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 1104 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1105 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 1106 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 1107 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 1108 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1109 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 1110 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 1111 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 1112 } CMT_Type;
AnnaBridge 171:3a7713b1edbc 1113
AnnaBridge 171:3a7713b1edbc 1114 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1115 -- CMT Register Masks
AnnaBridge 171:3a7713b1edbc 1116 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1117
AnnaBridge 171:3a7713b1edbc 1118 /*!
AnnaBridge 171:3a7713b1edbc 1119 * @addtogroup CMT_Register_Masks CMT Register Masks
AnnaBridge 171:3a7713b1edbc 1120 * @{
AnnaBridge 171:3a7713b1edbc 1121 */
AnnaBridge 171:3a7713b1edbc 1122
AnnaBridge 171:3a7713b1edbc 1123 /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
AnnaBridge 171:3a7713b1edbc 1124 #define CMT_CGH1_PH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1125 #define CMT_CGH1_PH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1126 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
AnnaBridge 171:3a7713b1edbc 1127
AnnaBridge 171:3a7713b1edbc 1128 /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
AnnaBridge 171:3a7713b1edbc 1129 #define CMT_CGL1_PL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1130 #define CMT_CGL1_PL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1131 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
AnnaBridge 171:3a7713b1edbc 1132
AnnaBridge 171:3a7713b1edbc 1133 /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
AnnaBridge 171:3a7713b1edbc 1134 #define CMT_CGH2_SH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1135 #define CMT_CGH2_SH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1136 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
AnnaBridge 171:3a7713b1edbc 1137
AnnaBridge 171:3a7713b1edbc 1138 /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
AnnaBridge 171:3a7713b1edbc 1139 #define CMT_CGL2_SL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1140 #define CMT_CGL2_SL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1141 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
AnnaBridge 171:3a7713b1edbc 1142
AnnaBridge 171:3a7713b1edbc 1143 /*! @name OC - CMT Output Control Register */
AnnaBridge 171:3a7713b1edbc 1144 #define CMT_OC_IROPEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1145 #define CMT_OC_IROPEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1146 #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
AnnaBridge 171:3a7713b1edbc 1147 #define CMT_OC_CMTPOL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1148 #define CMT_OC_CMTPOL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1149 #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
AnnaBridge 171:3a7713b1edbc 1150 #define CMT_OC_IROL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1151 #define CMT_OC_IROL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1152 #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
AnnaBridge 171:3a7713b1edbc 1153
AnnaBridge 171:3a7713b1edbc 1154 /*! @name MSC - CMT Modulator Status and Control Register */
AnnaBridge 171:3a7713b1edbc 1155 #define CMT_MSC_MCGEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1156 #define CMT_MSC_MCGEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1157 #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
AnnaBridge 171:3a7713b1edbc 1158 #define CMT_MSC_EOCIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1159 #define CMT_MSC_EOCIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1160 #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
AnnaBridge 171:3a7713b1edbc 1161 #define CMT_MSC_FSK_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1162 #define CMT_MSC_FSK_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1163 #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
AnnaBridge 171:3a7713b1edbc 1164 #define CMT_MSC_BASE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1165 #define CMT_MSC_BASE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1166 #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
AnnaBridge 171:3a7713b1edbc 1167 #define CMT_MSC_EXSPC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1168 #define CMT_MSC_EXSPC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1169 #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
AnnaBridge 171:3a7713b1edbc 1170 #define CMT_MSC_CMTDIV_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 1171 #define CMT_MSC_CMTDIV_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1172 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
AnnaBridge 171:3a7713b1edbc 1173 #define CMT_MSC_EOCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1174 #define CMT_MSC_EOCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1175 #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
AnnaBridge 171:3a7713b1edbc 1176
AnnaBridge 171:3a7713b1edbc 1177 /*! @name CMD1 - CMT Modulator Data Register Mark High */
AnnaBridge 171:3a7713b1edbc 1178 #define CMT_CMD1_MB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1179 #define CMT_CMD1_MB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1180 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
AnnaBridge 171:3a7713b1edbc 1181
AnnaBridge 171:3a7713b1edbc 1182 /*! @name CMD2 - CMT Modulator Data Register Mark Low */
AnnaBridge 171:3a7713b1edbc 1183 #define CMT_CMD2_MB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1184 #define CMT_CMD2_MB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1185 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
AnnaBridge 171:3a7713b1edbc 1186
AnnaBridge 171:3a7713b1edbc 1187 /*! @name CMD3 - CMT Modulator Data Register Space High */
AnnaBridge 171:3a7713b1edbc 1188 #define CMT_CMD3_SB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1189 #define CMT_CMD3_SB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1190 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
AnnaBridge 171:3a7713b1edbc 1191
AnnaBridge 171:3a7713b1edbc 1192 /*! @name CMD4 - CMT Modulator Data Register Space Low */
AnnaBridge 171:3a7713b1edbc 1193 #define CMT_CMD4_SB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1194 #define CMT_CMD4_SB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1195 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
AnnaBridge 171:3a7713b1edbc 1196
AnnaBridge 171:3a7713b1edbc 1197 /*! @name PPS - CMT Primary Prescaler Register */
AnnaBridge 171:3a7713b1edbc 1198 #define CMT_PPS_PPSDIV_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1199 #define CMT_PPS_PPSDIV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1200 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
AnnaBridge 171:3a7713b1edbc 1201
AnnaBridge 171:3a7713b1edbc 1202 /*! @name DMA - CMT Direct Memory Access Register */
AnnaBridge 171:3a7713b1edbc 1203 #define CMT_DMA_DMA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1204 #define CMT_DMA_DMA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1205 #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 1206
AnnaBridge 171:3a7713b1edbc 1207
AnnaBridge 171:3a7713b1edbc 1208 /*!
AnnaBridge 171:3a7713b1edbc 1209 * @}
AnnaBridge 171:3a7713b1edbc 1210 */ /* end of group CMT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1211
AnnaBridge 171:3a7713b1edbc 1212
AnnaBridge 171:3a7713b1edbc 1213 /* CMT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1214 /** Peripheral CMT base address */
AnnaBridge 171:3a7713b1edbc 1215 #define CMT_BASE (0x40062000u)
AnnaBridge 171:3a7713b1edbc 1216 /** Peripheral CMT base pointer */
AnnaBridge 171:3a7713b1edbc 1217 #define CMT ((CMT_Type *)CMT_BASE)
AnnaBridge 171:3a7713b1edbc 1218 /** Array initializer of CMT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1219 #define CMT_BASE_ADDRS { CMT_BASE }
AnnaBridge 171:3a7713b1edbc 1220 /** Array initializer of CMT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1221 #define CMT_BASE_PTRS { CMT }
AnnaBridge 171:3a7713b1edbc 1222 /** Interrupt vectors for the CMT peripheral type */
AnnaBridge 171:3a7713b1edbc 1223 #define CMT_IRQS { CMT_IRQn }
AnnaBridge 171:3a7713b1edbc 1224
AnnaBridge 171:3a7713b1edbc 1225 /*!
AnnaBridge 171:3a7713b1edbc 1226 * @}
AnnaBridge 171:3a7713b1edbc 1227 */ /* end of group CMT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1228
AnnaBridge 171:3a7713b1edbc 1229
AnnaBridge 171:3a7713b1edbc 1230 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1231 -- DAC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1232 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1233
AnnaBridge 171:3a7713b1edbc 1234 /*!
AnnaBridge 171:3a7713b1edbc 1235 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1236 * @{
AnnaBridge 171:3a7713b1edbc 1237 */
AnnaBridge 171:3a7713b1edbc 1238
AnnaBridge 171:3a7713b1edbc 1239 /** DAC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1240 typedef struct {
AnnaBridge 171:3a7713b1edbc 1241 struct { /* offset: 0x0, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 1242 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 1243 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 1244 } DAT[2];
AnnaBridge 171:3a7713b1edbc 1245 uint8_t RESERVED_0[28];
AnnaBridge 171:3a7713b1edbc 1246 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 1247 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
AnnaBridge 171:3a7713b1edbc 1248 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
AnnaBridge 171:3a7713b1edbc 1249 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
AnnaBridge 171:3a7713b1edbc 1250 } DAC_Type;
AnnaBridge 171:3a7713b1edbc 1251
AnnaBridge 171:3a7713b1edbc 1252 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1253 -- DAC Register Masks
AnnaBridge 171:3a7713b1edbc 1254 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1255
AnnaBridge 171:3a7713b1edbc 1256 /*!
AnnaBridge 171:3a7713b1edbc 1257 * @addtogroup DAC_Register_Masks DAC Register Masks
AnnaBridge 171:3a7713b1edbc 1258 * @{
AnnaBridge 171:3a7713b1edbc 1259 */
AnnaBridge 171:3a7713b1edbc 1260
AnnaBridge 171:3a7713b1edbc 1261 /*! @name DATL - DAC Data Low Register */
AnnaBridge 171:3a7713b1edbc 1262 #define DAC_DATL_DATA0_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 1263 #define DAC_DATL_DATA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1264 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
AnnaBridge 171:3a7713b1edbc 1265
AnnaBridge 171:3a7713b1edbc 1266 /* The count of DAC_DATL */
AnnaBridge 171:3a7713b1edbc 1267 #define DAC_DATL_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 1268
AnnaBridge 171:3a7713b1edbc 1269 /*! @name DATH - DAC Data High Register */
AnnaBridge 171:3a7713b1edbc 1270 #define DAC_DATH_DATA1_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 1271 #define DAC_DATH_DATA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1272 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
AnnaBridge 171:3a7713b1edbc 1273
AnnaBridge 171:3a7713b1edbc 1274 /* The count of DAC_DATH */
AnnaBridge 171:3a7713b1edbc 1275 #define DAC_DATH_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 1276
AnnaBridge 171:3a7713b1edbc 1277 /*! @name SR - DAC Status Register */
AnnaBridge 171:3a7713b1edbc 1278 #define DAC_SR_DACBFRPBF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1279 #define DAC_SR_DACBFRPBF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1280 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
AnnaBridge 171:3a7713b1edbc 1281 #define DAC_SR_DACBFRPTF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1282 #define DAC_SR_DACBFRPTF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1283 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
AnnaBridge 171:3a7713b1edbc 1284 #define DAC_SR_DACBFWMF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1285 #define DAC_SR_DACBFWMF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1286 #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
AnnaBridge 171:3a7713b1edbc 1287
AnnaBridge 171:3a7713b1edbc 1288 /*! @name C0 - DAC Control Register */
AnnaBridge 171:3a7713b1edbc 1289 #define DAC_C0_DACBBIEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1290 #define DAC_C0_DACBBIEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1291 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
AnnaBridge 171:3a7713b1edbc 1292 #define DAC_C0_DACBTIEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1293 #define DAC_C0_DACBTIEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1294 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
AnnaBridge 171:3a7713b1edbc 1295 #define DAC_C0_DACBWIEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1296 #define DAC_C0_DACBWIEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1297 #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
AnnaBridge 171:3a7713b1edbc 1298 #define DAC_C0_LPEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1299 #define DAC_C0_LPEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1300 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
AnnaBridge 171:3a7713b1edbc 1301 #define DAC_C0_DACSWTRG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1302 #define DAC_C0_DACSWTRG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1303 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
AnnaBridge 171:3a7713b1edbc 1304 #define DAC_C0_DACTRGSEL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1305 #define DAC_C0_DACTRGSEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1306 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 1307 #define DAC_C0_DACRFS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1308 #define DAC_C0_DACRFS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1309 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
AnnaBridge 171:3a7713b1edbc 1310 #define DAC_C0_DACEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1311 #define DAC_C0_DACEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1312 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
AnnaBridge 171:3a7713b1edbc 1313
AnnaBridge 171:3a7713b1edbc 1314 /*! @name C1 - DAC Control Register 1 */
AnnaBridge 171:3a7713b1edbc 1315 #define DAC_C1_DACBFEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1316 #define DAC_C1_DACBFEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1317 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
AnnaBridge 171:3a7713b1edbc 1318 #define DAC_C1_DACBFMD_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1319 #define DAC_C1_DACBFMD_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1320 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
AnnaBridge 171:3a7713b1edbc 1321 #define DAC_C1_DACBFWM_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 1322 #define DAC_C1_DACBFWM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1323 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
AnnaBridge 171:3a7713b1edbc 1324 #define DAC_C1_DMAEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1325 #define DAC_C1_DMAEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1326 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 1327
AnnaBridge 171:3a7713b1edbc 1328 /*! @name C2 - DAC Control Register 2 */
AnnaBridge 171:3a7713b1edbc 1329 #define DAC_C2_DACBFUP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1330 #define DAC_C2_DACBFUP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1331 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
AnnaBridge 171:3a7713b1edbc 1332 #define DAC_C2_DACBFRP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1333 #define DAC_C2_DACBFRP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1334 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
AnnaBridge 171:3a7713b1edbc 1335
AnnaBridge 171:3a7713b1edbc 1336
AnnaBridge 171:3a7713b1edbc 1337 /*!
AnnaBridge 171:3a7713b1edbc 1338 * @}
AnnaBridge 171:3a7713b1edbc 1339 */ /* end of group DAC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1340
AnnaBridge 171:3a7713b1edbc 1341
AnnaBridge 171:3a7713b1edbc 1342 /* DAC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1343 /** Peripheral DAC0 base address */
AnnaBridge 171:3a7713b1edbc 1344 #define DAC0_BASE (0x4003F000u)
AnnaBridge 171:3a7713b1edbc 1345 /** Peripheral DAC0 base pointer */
AnnaBridge 171:3a7713b1edbc 1346 #define DAC0 ((DAC_Type *)DAC0_BASE)
AnnaBridge 171:3a7713b1edbc 1347 /** Array initializer of DAC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1348 #define DAC_BASE_ADDRS { DAC0_BASE }
AnnaBridge 171:3a7713b1edbc 1349 /** Array initializer of DAC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1350 #define DAC_BASE_PTRS { DAC0 }
AnnaBridge 171:3a7713b1edbc 1351 /** Interrupt vectors for the DAC peripheral type */
AnnaBridge 171:3a7713b1edbc 1352 #define DAC_IRQS { DAC0_IRQn }
AnnaBridge 171:3a7713b1edbc 1353
AnnaBridge 171:3a7713b1edbc 1354 /*!
AnnaBridge 171:3a7713b1edbc 1355 * @}
AnnaBridge 171:3a7713b1edbc 1356 */ /* end of group DAC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1357
AnnaBridge 171:3a7713b1edbc 1358
AnnaBridge 171:3a7713b1edbc 1359 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1360 -- DCDC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1361 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1362
AnnaBridge 171:3a7713b1edbc 1363 /*!
AnnaBridge 171:3a7713b1edbc 1364 * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1365 * @{
AnnaBridge 171:3a7713b1edbc 1366 */
AnnaBridge 171:3a7713b1edbc 1367
AnnaBridge 171:3a7713b1edbc 1368 /** DCDC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1369 typedef struct {
AnnaBridge 171:3a7713b1edbc 1370 __IO uint32_t REG0; /**< DCDC REGISTER 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1371 __IO uint32_t REG1; /**< DCDC REGISTER 1, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1372 __IO uint32_t REG2; /**< DCDC REGISTER 2, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 1373 __IO uint32_t REG3; /**< DCDC REGISTER 3, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1374 __IO uint32_t REG4; /**< DCDC REGISTER 4, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 1375 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 1376 __IO uint32_t REG6; /**< DCDC REGISTER 6, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 1377 __IO uint32_t REG7; /**< DCDC REGISTER 7, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 1378 } DCDC_Type;
AnnaBridge 171:3a7713b1edbc 1379
AnnaBridge 171:3a7713b1edbc 1380 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1381 -- DCDC Register Masks
AnnaBridge 171:3a7713b1edbc 1382 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1383
AnnaBridge 171:3a7713b1edbc 1384 /*!
AnnaBridge 171:3a7713b1edbc 1385 * @addtogroup DCDC_Register_Masks DCDC Register Masks
AnnaBridge 171:3a7713b1edbc 1386 * @{
AnnaBridge 171:3a7713b1edbc 1387 */
AnnaBridge 171:3a7713b1edbc 1388
AnnaBridge 171:3a7713b1edbc 1389 /*! @name REG0 - DCDC REGISTER 0 */
AnnaBridge 171:3a7713b1edbc 1390 #define DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1391 #define DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1392 #define DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK)
AnnaBridge 171:3a7713b1edbc 1393 #define DCDC_REG0_DCDC_SEL_CLK_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1394 #define DCDC_REG0_DCDC_SEL_CLK_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1395 #define DCDC_REG0_DCDC_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_SEL_CLK_SHIFT)) & DCDC_REG0_DCDC_SEL_CLK_MASK)
AnnaBridge 171:3a7713b1edbc 1396 #define DCDC_REG0_DCDC_PWD_OSC_INT_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1397 #define DCDC_REG0_DCDC_PWD_OSC_INT_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1398 #define DCDC_REG0_DCDC_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_PWD_OSC_INT_SHIFT)) & DCDC_REG0_DCDC_PWD_OSC_INT_MASK)
AnnaBridge 171:3a7713b1edbc 1399 #define DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1400 #define DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1401 #define DCDC_REG0_DCDC_LP_DF_CMP_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_SHIFT)) & DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_MASK)
AnnaBridge 171:3a7713b1edbc 1402 #define DCDC_REG0_DCDC_VBAT_DIV_CTRL_MASK (0xC00U)
AnnaBridge 171:3a7713b1edbc 1403 #define DCDC_REG0_DCDC_VBAT_DIV_CTRL_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1404 #define DCDC_REG0_DCDC_VBAT_DIV_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_VBAT_DIV_CTRL_SHIFT)) & DCDC_REG0_DCDC_VBAT_DIV_CTRL_MASK)
AnnaBridge 171:3a7713b1edbc 1405 #define DCDC_REG0_DCDC_LP_STATE_HYS_L_MASK (0x60000U)
AnnaBridge 171:3a7713b1edbc 1406 #define DCDC_REG0_DCDC_LP_STATE_HYS_L_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1407 #define DCDC_REG0_DCDC_LP_STATE_HYS_L(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LP_STATE_HYS_L_SHIFT)) & DCDC_REG0_DCDC_LP_STATE_HYS_L_MASK)
AnnaBridge 171:3a7713b1edbc 1408 #define DCDC_REG0_DCDC_LP_STATE_HYS_H_MASK (0x180000U)
AnnaBridge 171:3a7713b1edbc 1409 #define DCDC_REG0_DCDC_LP_STATE_HYS_H_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 1410 #define DCDC_REG0_DCDC_LP_STATE_HYS_H(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LP_STATE_HYS_H_SHIFT)) & DCDC_REG0_DCDC_LP_STATE_HYS_H_MASK)
AnnaBridge 171:3a7713b1edbc 1411 #define DCDC_REG0_HYST_LP_COMP_ADJ_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1412 #define DCDC_REG0_HYST_LP_COMP_ADJ_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1413 #define DCDC_REG0_HYST_LP_COMP_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_HYST_LP_COMP_ADJ_SHIFT)) & DCDC_REG0_HYST_LP_COMP_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 1414 #define DCDC_REG0_HYST_LP_CMP_DISABLE_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1415 #define DCDC_REG0_HYST_LP_CMP_DISABLE_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1416 #define DCDC_REG0_HYST_LP_CMP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_HYST_LP_CMP_DISABLE_SHIFT)) & DCDC_REG0_HYST_LP_CMP_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 1417 #define DCDC_REG0_OFFSET_RSNS_LP_ADJ_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 1418 #define DCDC_REG0_OFFSET_RSNS_LP_ADJ_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 1419 #define DCDC_REG0_OFFSET_RSNS_LP_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OFFSET_RSNS_LP_ADJ_SHIFT)) & DCDC_REG0_OFFSET_RSNS_LP_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 1420 #define DCDC_REG0_OFFSET_RSNS_LP_DISABLE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1421 #define DCDC_REG0_OFFSET_RSNS_LP_DISABLE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1422 #define DCDC_REG0_OFFSET_RSNS_LP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OFFSET_RSNS_LP_DISABLE_SHIFT)) & DCDC_REG0_OFFSET_RSNS_LP_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 1423 #define DCDC_REG0_DCDC_LESS_I_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1424 #define DCDC_REG0_DCDC_LESS_I_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1425 #define DCDC_REG0_DCDC_LESS_I(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_LESS_I_SHIFT)) & DCDC_REG0_DCDC_LESS_I_MASK)
AnnaBridge 171:3a7713b1edbc 1426 #define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1427 #define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1428 #define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
AnnaBridge 171:3a7713b1edbc 1429 #define DCDC_REG0_DCDC_XTALOK_DISABLE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 1430 #define DCDC_REG0_DCDC_XTALOK_DISABLE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 1431 #define DCDC_REG0_DCDC_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_DCDC_XTALOK_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 1432 #define DCDC_REG0_PSWITCH_STATUS_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1433 #define DCDC_REG0_PSWITCH_STATUS_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1434 #define DCDC_REG0_PSWITCH_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PSWITCH_STATUS_SHIFT)) & DCDC_REG0_PSWITCH_STATUS_MASK)
AnnaBridge 171:3a7713b1edbc 1435 #define DCDC_REG0_VLPS_CONFIG_DCDC_HP_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1436 #define DCDC_REG0_VLPS_CONFIG_DCDC_HP_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1437 #define DCDC_REG0_VLPS_CONFIG_DCDC_HP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_VLPS_CONFIG_DCDC_HP_SHIFT)) & DCDC_REG0_VLPS_CONFIG_DCDC_HP_MASK)
AnnaBridge 171:3a7713b1edbc 1438 #define DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1439 #define DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1440 #define DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_SHIFT)) & DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_MASK)
AnnaBridge 171:3a7713b1edbc 1441 #define DCDC_REG0_DCDC_STS_DC_OK_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 1442 #define DCDC_REG0_DCDC_STS_DC_OK_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 1443 #define DCDC_REG0_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DCDC_STS_DC_OK_SHIFT)) & DCDC_REG0_DCDC_STS_DC_OK_MASK)
AnnaBridge 171:3a7713b1edbc 1444
AnnaBridge 171:3a7713b1edbc 1445 /*! @name REG1 - DCDC REGISTER 1 */
AnnaBridge 171:3a7713b1edbc 1446 #define DCDC_REG1_POSLIMIT_BUCK_IN_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 1447 #define DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1448 #define DCDC_REG1_POSLIMIT_BUCK_IN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT)) & DCDC_REG1_POSLIMIT_BUCK_IN_MASK)
AnnaBridge 171:3a7713b1edbc 1449 #define DCDC_REG1_POSLIMIT_BOOST_IN_MASK (0x3F80U)
AnnaBridge 171:3a7713b1edbc 1450 #define DCDC_REG1_POSLIMIT_BOOST_IN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1451 #define DCDC_REG1_POSLIMIT_BOOST_IN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_POSLIMIT_BOOST_IN_SHIFT)) & DCDC_REG1_POSLIMIT_BOOST_IN_MASK)
AnnaBridge 171:3a7713b1edbc 1452 #define DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1453 #define DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1454 #define DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 1455 #define DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1456 #define DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1457 #define DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 1458 #define DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 1459 #define DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 1460 #define DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_MASK)
AnnaBridge 171:3a7713b1edbc 1461 #define DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1462 #define DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1463 #define DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_MASK)
AnnaBridge 171:3a7713b1edbc 1464
AnnaBridge 171:3a7713b1edbc 1465 /*! @name REG2 - DCDC REGISTER 2 */
AnnaBridge 171:3a7713b1edbc 1466 #define DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1467 #define DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1468 #define DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_MASK)
AnnaBridge 171:3a7713b1edbc 1469 #define DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 1470 #define DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 1471 #define DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_MASK)
AnnaBridge 171:3a7713b1edbc 1472 #define DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 1473 #define DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1474 #define DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 1475
AnnaBridge 171:3a7713b1edbc 1476 /*! @name REG3 - DCDC REGISTER 3 */
AnnaBridge 171:3a7713b1edbc 1477 #define DCDC_REG3_DCDC_VDD1P8CTRL_TRG_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 1478 #define DCDC_REG3_DCDC_VDD1P8CTRL_TRG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1479 #define DCDC_REG3_DCDC_VDD1P8CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P8CTRL_TRG_SHIFT)) & DCDC_REG3_DCDC_VDD1P8CTRL_TRG_MASK)
AnnaBridge 171:3a7713b1edbc 1480 #define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK_MASK (0x7C0U)
AnnaBridge 171:3a7713b1edbc 1481 #define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1482 #define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK_SHIFT)) & DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BUCK_MASK)
AnnaBridge 171:3a7713b1edbc 1483 #define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST_MASK (0xF800U)
AnnaBridge 171:3a7713b1edbc 1484 #define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 1485 #define DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST_SHIFT)) & DCDC_REG3_DCDC_VDD1P5CTRL_TRG_BOOST_MASK)
AnnaBridge 171:3a7713b1edbc 1486 #define DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN_MASK (0x1E0000U)
AnnaBridge 171:3a7713b1edbc 1487 #define DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1488 #define DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN_SHIFT)) & DCDC_REG3_DCDC_VDD1P5CTRL_ADJTN_MASK)
AnnaBridge 171:3a7713b1edbc 1489 #define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1490 #define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1491 #define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED_SHIFT)) & DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_PULSED_MASK)
AnnaBridge 171:3a7713b1edbc 1492 #define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1493 #define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1494 #define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_SHIFT)) & DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_PULSED_MASK)
AnnaBridge 171:3a7713b1edbc 1495 #define DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 1496 #define DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 1497 #define DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_SHIFT)) & DCDC_REG3_DCDC_MINPWR_HALF_FETS_PULSED_MASK)
AnnaBridge 171:3a7713b1edbc 1498 #define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1499 #define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1500 #define DCDC_REG3_DCDC_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_MASK)
AnnaBridge 171:3a7713b1edbc 1501 #define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1502 #define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1503 #define DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_SHIFT)) & DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_MASK)
AnnaBridge 171:3a7713b1edbc 1504 #define DCDC_REG3_DCDC_MINPWR_HALF_FETS_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1505 #define DCDC_REG3_DCDC_MINPWR_HALF_FETS_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1506 #define DCDC_REG3_DCDC_MINPWR_HALF_FETS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_DCDC_MINPWR_HALF_FETS_MASK)
AnnaBridge 171:3a7713b1edbc 1507 #define DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1508 #define DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1509 #define DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_DCDC_VDD1P5CTRL_DISABLE_STEP_MASK)
AnnaBridge 171:3a7713b1edbc 1510 #define DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1511 #define DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1512 #define DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK)
AnnaBridge 171:3a7713b1edbc 1513
AnnaBridge 171:3a7713b1edbc 1514 /*! @name REG4 - DCDC REGISTER 4 */
AnnaBridge 171:3a7713b1edbc 1515 #define DCDC_REG4_DCDC_SW_SHUTDOWN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1516 #define DCDC_REG4_DCDC_SW_SHUTDOWN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1517 #define DCDC_REG4_DCDC_SW_SHUTDOWN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_DCDC_SW_SHUTDOWN_SHIFT)) & DCDC_REG4_DCDC_SW_SHUTDOWN_MASK)
AnnaBridge 171:3a7713b1edbc 1518 #define DCDC_REG4_UNLOCK_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 1519 #define DCDC_REG4_UNLOCK_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1520 #define DCDC_REG4_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_UNLOCK_SHIFT)) & DCDC_REG4_UNLOCK_MASK)
AnnaBridge 171:3a7713b1edbc 1521
AnnaBridge 171:3a7713b1edbc 1522 /*! @name REG6 - DCDC REGISTER 6 */
AnnaBridge 171:3a7713b1edbc 1523 #define DCDC_REG6_PSWITCH_INT_RISE_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1524 #define DCDC_REG6_PSWITCH_INT_RISE_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1525 #define DCDC_REG6_PSWITCH_INT_RISE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_RISE_EN_SHIFT)) & DCDC_REG6_PSWITCH_INT_RISE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 1526 #define DCDC_REG6_PSWITCH_INT_FALL_EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1527 #define DCDC_REG6_PSWITCH_INT_FALL_EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1528 #define DCDC_REG6_PSWITCH_INT_FALL_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_FALL_EN_SHIFT)) & DCDC_REG6_PSWITCH_INT_FALL_EN_MASK)
AnnaBridge 171:3a7713b1edbc 1529 #define DCDC_REG6_PSWITCH_INT_CLEAR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1530 #define DCDC_REG6_PSWITCH_INT_CLEAR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1531 #define DCDC_REG6_PSWITCH_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_CLEAR_SHIFT)) & DCDC_REG6_PSWITCH_INT_CLEAR_MASK)
AnnaBridge 171:3a7713b1edbc 1532 #define DCDC_REG6_PSWITCH_INT_MUTE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1533 #define DCDC_REG6_PSWITCH_INT_MUTE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1534 #define DCDC_REG6_PSWITCH_INT_MUTE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_MUTE_SHIFT)) & DCDC_REG6_PSWITCH_INT_MUTE_MASK)
AnnaBridge 171:3a7713b1edbc 1535 #define DCDC_REG6_PSWITCH_INT_STS_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 1536 #define DCDC_REG6_PSWITCH_INT_STS_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 1537 #define DCDC_REG6_PSWITCH_INT_STS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_PSWITCH_INT_STS_SHIFT)) & DCDC_REG6_PSWITCH_INT_STS_MASK)
AnnaBridge 171:3a7713b1edbc 1538
AnnaBridge 171:3a7713b1edbc 1539 /*! @name REG7 - DCDC REGISTER 7 */
AnnaBridge 171:3a7713b1edbc 1540 #define DCDC_REG7_INTEGRATOR_VALUE_MASK (0x7FFFFU)
AnnaBridge 171:3a7713b1edbc 1541 #define DCDC_REG7_INTEGRATOR_VALUE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1542 #define DCDC_REG7_INTEGRATOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_INTEGRATOR_VALUE_SHIFT)) & DCDC_REG7_INTEGRATOR_VALUE_MASK)
AnnaBridge 171:3a7713b1edbc 1543 #define DCDC_REG7_INTEGRATOR_VALUE_SEL_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 1544 #define DCDC_REG7_INTEGRATOR_VALUE_SEL_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 1545 #define DCDC_REG7_INTEGRATOR_VALUE_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_INTEGRATOR_VALUE_SEL_SHIFT)) & DCDC_REG7_INTEGRATOR_VALUE_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 1546 #define DCDC_REG7_PULSE_RUN_SPEEDUP_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1547 #define DCDC_REG7_PULSE_RUN_SPEEDUP_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1548 #define DCDC_REG7_PULSE_RUN_SPEEDUP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_PULSE_RUN_SPEEDUP_SHIFT)) & DCDC_REG7_PULSE_RUN_SPEEDUP_MASK)
AnnaBridge 171:3a7713b1edbc 1549
AnnaBridge 171:3a7713b1edbc 1550
AnnaBridge 171:3a7713b1edbc 1551 /*!
AnnaBridge 171:3a7713b1edbc 1552 * @}
AnnaBridge 171:3a7713b1edbc 1553 */ /* end of group DCDC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1554
AnnaBridge 171:3a7713b1edbc 1555
AnnaBridge 171:3a7713b1edbc 1556 /* DCDC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 1557 /** Peripheral DCDC base address */
AnnaBridge 171:3a7713b1edbc 1558 #define DCDC_BASE (0x4005A000u)
AnnaBridge 171:3a7713b1edbc 1559 /** Peripheral DCDC base pointer */
AnnaBridge 171:3a7713b1edbc 1560 #define DCDC ((DCDC_Type *)DCDC_BASE)
AnnaBridge 171:3a7713b1edbc 1561 /** Array initializer of DCDC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 1562 #define DCDC_BASE_ADDRS { DCDC_BASE }
AnnaBridge 171:3a7713b1edbc 1563 /** Array initializer of DCDC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 1564 #define DCDC_BASE_PTRS { DCDC }
AnnaBridge 171:3a7713b1edbc 1565
AnnaBridge 171:3a7713b1edbc 1566 /*!
AnnaBridge 171:3a7713b1edbc 1567 * @}
AnnaBridge 171:3a7713b1edbc 1568 */ /* end of group DCDC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 1569
AnnaBridge 171:3a7713b1edbc 1570
AnnaBridge 171:3a7713b1edbc 1571 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1572 -- DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1573 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1574
AnnaBridge 171:3a7713b1edbc 1575 /*!
AnnaBridge 171:3a7713b1edbc 1576 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 1577 * @{
AnnaBridge 171:3a7713b1edbc 1578 */
AnnaBridge 171:3a7713b1edbc 1579
AnnaBridge 171:3a7713b1edbc 1580 /** DMA - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 1581 typedef struct {
AnnaBridge 171:3a7713b1edbc 1582 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 1583 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 1584 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 1585 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 1586 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 1587 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 1588 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 1589 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
AnnaBridge 171:3a7713b1edbc 1590 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
AnnaBridge 171:3a7713b1edbc 1591 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 1592 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 1593 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
AnnaBridge 171:3a7713b1edbc 1594 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
AnnaBridge 171:3a7713b1edbc 1595 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
AnnaBridge 171:3a7713b1edbc 1596 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 1597 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 1598 uint8_t RESERVED_3[4];
AnnaBridge 171:3a7713b1edbc 1599 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 1600 uint8_t RESERVED_4[4];
AnnaBridge 171:3a7713b1edbc 1601 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 1602 uint8_t RESERVED_5[12];
AnnaBridge 171:3a7713b1edbc 1603 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 1604 uint8_t RESERVED_6[184];
AnnaBridge 171:3a7713b1edbc 1605 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 1606 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
AnnaBridge 171:3a7713b1edbc 1607 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
AnnaBridge 171:3a7713b1edbc 1608 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
AnnaBridge 171:3a7713b1edbc 1609 uint8_t RESERVED_7[3836];
AnnaBridge 171:3a7713b1edbc 1610 struct { /* offset: 0x1000, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1611 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1612 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1613 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1614 union { /* offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1615 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1616 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1617 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1618 };
AnnaBridge 171:3a7713b1edbc 1619 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1620 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1621 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1622 union { /* offset: 0x1016, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1623 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1624 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1625 };
AnnaBridge 171:3a7713b1edbc 1626 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1627 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1628 union { /* offset: 0x101E, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1629 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1630 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 1631 };
AnnaBridge 171:3a7713b1edbc 1632 } TCD[4];
AnnaBridge 171:3a7713b1edbc 1633 } DMA_Type;
AnnaBridge 171:3a7713b1edbc 1634
AnnaBridge 171:3a7713b1edbc 1635 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 1636 -- DMA Register Masks
AnnaBridge 171:3a7713b1edbc 1637 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 1638
AnnaBridge 171:3a7713b1edbc 1639 /*!
AnnaBridge 171:3a7713b1edbc 1640 * @addtogroup DMA_Register_Masks DMA Register Masks
AnnaBridge 171:3a7713b1edbc 1641 * @{
AnnaBridge 171:3a7713b1edbc 1642 */
AnnaBridge 171:3a7713b1edbc 1643
AnnaBridge 171:3a7713b1edbc 1644 /*! @name CR - Control Register */
AnnaBridge 171:3a7713b1edbc 1645 #define DMA_CR_EDBG_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1646 #define DMA_CR_EDBG_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1647 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
AnnaBridge 171:3a7713b1edbc 1648 #define DMA_CR_ERCA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1649 #define DMA_CR_ERCA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1650 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
AnnaBridge 171:3a7713b1edbc 1651 #define DMA_CR_HOE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1652 #define DMA_CR_HOE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1653 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
AnnaBridge 171:3a7713b1edbc 1654 #define DMA_CR_HALT_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1655 #define DMA_CR_HALT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1656 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
AnnaBridge 171:3a7713b1edbc 1657 #define DMA_CR_CLM_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1658 #define DMA_CR_CLM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1659 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
AnnaBridge 171:3a7713b1edbc 1660 #define DMA_CR_EMLM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1661 #define DMA_CR_EMLM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1662 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
AnnaBridge 171:3a7713b1edbc 1663 #define DMA_CR_ECX_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1664 #define DMA_CR_ECX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1665 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
AnnaBridge 171:3a7713b1edbc 1666 #define DMA_CR_CX_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1667 #define DMA_CR_CX_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1668 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
AnnaBridge 171:3a7713b1edbc 1669 #define DMA_CR_ACTIVE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 1670 #define DMA_CR_ACTIVE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 1671 #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
AnnaBridge 171:3a7713b1edbc 1672
AnnaBridge 171:3a7713b1edbc 1673 /*! @name ES - Error Status Register */
AnnaBridge 171:3a7713b1edbc 1674 #define DMA_ES_DBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1675 #define DMA_ES_DBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1676 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
AnnaBridge 171:3a7713b1edbc 1677 #define DMA_ES_SBE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1678 #define DMA_ES_SBE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1679 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
AnnaBridge 171:3a7713b1edbc 1680 #define DMA_ES_SGE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1681 #define DMA_ES_SGE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1682 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
AnnaBridge 171:3a7713b1edbc 1683 #define DMA_ES_NCE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1684 #define DMA_ES_NCE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1685 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
AnnaBridge 171:3a7713b1edbc 1686 #define DMA_ES_DOE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1687 #define DMA_ES_DOE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1688 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
AnnaBridge 171:3a7713b1edbc 1689 #define DMA_ES_DAE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1690 #define DMA_ES_DAE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1691 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
AnnaBridge 171:3a7713b1edbc 1692 #define DMA_ES_SOE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1693 #define DMA_ES_SOE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1694 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
AnnaBridge 171:3a7713b1edbc 1695 #define DMA_ES_SAE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1696 #define DMA_ES_SAE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1697 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
AnnaBridge 171:3a7713b1edbc 1698 #define DMA_ES_ERRCHN_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 1699 #define DMA_ES_ERRCHN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1700 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
AnnaBridge 171:3a7713b1edbc 1701 #define DMA_ES_CPE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1702 #define DMA_ES_CPE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1703 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
AnnaBridge 171:3a7713b1edbc 1704 #define DMA_ES_ECX_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1705 #define DMA_ES_ECX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1706 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
AnnaBridge 171:3a7713b1edbc 1707 #define DMA_ES_VLD_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 1708 #define DMA_ES_VLD_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 1709 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
AnnaBridge 171:3a7713b1edbc 1710
AnnaBridge 171:3a7713b1edbc 1711 /*! @name ERQ - Enable Request Register */
AnnaBridge 171:3a7713b1edbc 1712 #define DMA_ERQ_ERQ0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1713 #define DMA_ERQ_ERQ0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1714 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
AnnaBridge 171:3a7713b1edbc 1715 #define DMA_ERQ_ERQ1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1716 #define DMA_ERQ_ERQ1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1717 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
AnnaBridge 171:3a7713b1edbc 1718 #define DMA_ERQ_ERQ2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1719 #define DMA_ERQ_ERQ2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1720 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
AnnaBridge 171:3a7713b1edbc 1721 #define DMA_ERQ_ERQ3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1722 #define DMA_ERQ_ERQ3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1723 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
AnnaBridge 171:3a7713b1edbc 1724
AnnaBridge 171:3a7713b1edbc 1725 /*! @name EEI - Enable Error Interrupt Register */
AnnaBridge 171:3a7713b1edbc 1726 #define DMA_EEI_EEI0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1727 #define DMA_EEI_EEI0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1728 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
AnnaBridge 171:3a7713b1edbc 1729 #define DMA_EEI_EEI1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1730 #define DMA_EEI_EEI1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1731 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
AnnaBridge 171:3a7713b1edbc 1732 #define DMA_EEI_EEI2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1733 #define DMA_EEI_EEI2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1734 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
AnnaBridge 171:3a7713b1edbc 1735 #define DMA_EEI_EEI3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1736 #define DMA_EEI_EEI3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1737 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
AnnaBridge 171:3a7713b1edbc 1738
AnnaBridge 171:3a7713b1edbc 1739 /*! @name CEEI - Clear Enable Error Interrupt Register */
AnnaBridge 171:3a7713b1edbc 1740 #define DMA_CEEI_CEEI_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1741 #define DMA_CEEI_CEEI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1742 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
AnnaBridge 171:3a7713b1edbc 1743 #define DMA_CEEI_CAEE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1744 #define DMA_CEEI_CAEE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1745 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
AnnaBridge 171:3a7713b1edbc 1746 #define DMA_CEEI_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1747 #define DMA_CEEI_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1748 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1749
AnnaBridge 171:3a7713b1edbc 1750 /*! @name SEEI - Set Enable Error Interrupt Register */
AnnaBridge 171:3a7713b1edbc 1751 #define DMA_SEEI_SEEI_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1752 #define DMA_SEEI_SEEI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1753 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
AnnaBridge 171:3a7713b1edbc 1754 #define DMA_SEEI_SAEE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1755 #define DMA_SEEI_SAEE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1756 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
AnnaBridge 171:3a7713b1edbc 1757 #define DMA_SEEI_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1758 #define DMA_SEEI_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1759 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1760
AnnaBridge 171:3a7713b1edbc 1761 /*! @name CERQ - Clear Enable Request Register */
AnnaBridge 171:3a7713b1edbc 1762 #define DMA_CERQ_CERQ_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1763 #define DMA_CERQ_CERQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1764 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
AnnaBridge 171:3a7713b1edbc 1765 #define DMA_CERQ_CAER_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1766 #define DMA_CERQ_CAER_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1767 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
AnnaBridge 171:3a7713b1edbc 1768 #define DMA_CERQ_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1769 #define DMA_CERQ_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1770 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1771
AnnaBridge 171:3a7713b1edbc 1772 /*! @name SERQ - Set Enable Request Register */
AnnaBridge 171:3a7713b1edbc 1773 #define DMA_SERQ_SERQ_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1774 #define DMA_SERQ_SERQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1775 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
AnnaBridge 171:3a7713b1edbc 1776 #define DMA_SERQ_SAER_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1777 #define DMA_SERQ_SAER_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1778 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
AnnaBridge 171:3a7713b1edbc 1779 #define DMA_SERQ_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1780 #define DMA_SERQ_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1781 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1782
AnnaBridge 171:3a7713b1edbc 1783 /*! @name CDNE - Clear DONE Status Bit Register */
AnnaBridge 171:3a7713b1edbc 1784 #define DMA_CDNE_CDNE_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1785 #define DMA_CDNE_CDNE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1786 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
AnnaBridge 171:3a7713b1edbc 1787 #define DMA_CDNE_CADN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1788 #define DMA_CDNE_CADN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1789 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
AnnaBridge 171:3a7713b1edbc 1790 #define DMA_CDNE_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1791 #define DMA_CDNE_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1792 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1793
AnnaBridge 171:3a7713b1edbc 1794 /*! @name SSRT - Set START Bit Register */
AnnaBridge 171:3a7713b1edbc 1795 #define DMA_SSRT_SSRT_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1796 #define DMA_SSRT_SSRT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1797 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
AnnaBridge 171:3a7713b1edbc 1798 #define DMA_SSRT_SAST_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1799 #define DMA_SSRT_SAST_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1800 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
AnnaBridge 171:3a7713b1edbc 1801 #define DMA_SSRT_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1802 #define DMA_SSRT_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1803 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1804
AnnaBridge 171:3a7713b1edbc 1805 /*! @name CERR - Clear Error Register */
AnnaBridge 171:3a7713b1edbc 1806 #define DMA_CERR_CERR_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1807 #define DMA_CERR_CERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1808 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
AnnaBridge 171:3a7713b1edbc 1809 #define DMA_CERR_CAEI_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1810 #define DMA_CERR_CAEI_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1811 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
AnnaBridge 171:3a7713b1edbc 1812 #define DMA_CERR_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1813 #define DMA_CERR_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1814 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1815
AnnaBridge 171:3a7713b1edbc 1816 /*! @name CINT - Clear Interrupt Request Register */
AnnaBridge 171:3a7713b1edbc 1817 #define DMA_CINT_CINT_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1818 #define DMA_CINT_CINT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1819 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
AnnaBridge 171:3a7713b1edbc 1820 #define DMA_CINT_CAIR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1821 #define DMA_CINT_CAIR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1822 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
AnnaBridge 171:3a7713b1edbc 1823 #define DMA_CINT_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1824 #define DMA_CINT_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1825 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 1826
AnnaBridge 171:3a7713b1edbc 1827 /*! @name INT - Interrupt Request Register */
AnnaBridge 171:3a7713b1edbc 1828 #define DMA_INT_INT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1829 #define DMA_INT_INT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1830 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
AnnaBridge 171:3a7713b1edbc 1831 #define DMA_INT_INT1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1832 #define DMA_INT_INT1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1833 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
AnnaBridge 171:3a7713b1edbc 1834 #define DMA_INT_INT2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1835 #define DMA_INT_INT2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1836 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
AnnaBridge 171:3a7713b1edbc 1837 #define DMA_INT_INT3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1838 #define DMA_INT_INT3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1839 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
AnnaBridge 171:3a7713b1edbc 1840
AnnaBridge 171:3a7713b1edbc 1841 /*! @name ERR - Error Register */
AnnaBridge 171:3a7713b1edbc 1842 #define DMA_ERR_ERR0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1843 #define DMA_ERR_ERR0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1844 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
AnnaBridge 171:3a7713b1edbc 1845 #define DMA_ERR_ERR1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1846 #define DMA_ERR_ERR1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1847 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
AnnaBridge 171:3a7713b1edbc 1848 #define DMA_ERR_ERR2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1849 #define DMA_ERR_ERR2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1850 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
AnnaBridge 171:3a7713b1edbc 1851 #define DMA_ERR_ERR3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1852 #define DMA_ERR_ERR3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1853 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
AnnaBridge 171:3a7713b1edbc 1854
AnnaBridge 171:3a7713b1edbc 1855 /*! @name HRS - Hardware Request Status Register */
AnnaBridge 171:3a7713b1edbc 1856 #define DMA_HRS_HRS0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1857 #define DMA_HRS_HRS0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1858 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
AnnaBridge 171:3a7713b1edbc 1859 #define DMA_HRS_HRS1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1860 #define DMA_HRS_HRS1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1861 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
AnnaBridge 171:3a7713b1edbc 1862 #define DMA_HRS_HRS2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1863 #define DMA_HRS_HRS2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1864 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
AnnaBridge 171:3a7713b1edbc 1865 #define DMA_HRS_HRS3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1866 #define DMA_HRS_HRS3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1867 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
AnnaBridge 171:3a7713b1edbc 1868
AnnaBridge 171:3a7713b1edbc 1869 /*! @name EARS - Enable Asynchronous Request in Stop Register */
AnnaBridge 171:3a7713b1edbc 1870 #define DMA_EARS_EDREQ_0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1871 #define DMA_EARS_EDREQ_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1872 #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
AnnaBridge 171:3a7713b1edbc 1873 #define DMA_EARS_EDREQ_1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1874 #define DMA_EARS_EDREQ_1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1875 #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
AnnaBridge 171:3a7713b1edbc 1876 #define DMA_EARS_EDREQ_2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1877 #define DMA_EARS_EDREQ_2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1878 #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
AnnaBridge 171:3a7713b1edbc 1879 #define DMA_EARS_EDREQ_3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 1880 #define DMA_EARS_EDREQ_3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1881 #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
AnnaBridge 171:3a7713b1edbc 1882
AnnaBridge 171:3a7713b1edbc 1883 /*! @name DCHPRI3 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 1884 #define DMA_DCHPRI3_CHPRI_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1885 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1886 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 1887 #define DMA_DCHPRI3_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1888 #define DMA_DCHPRI3_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1889 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 1890 #define DMA_DCHPRI3_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1891 #define DMA_DCHPRI3_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1892 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 1893
AnnaBridge 171:3a7713b1edbc 1894 /*! @name DCHPRI2 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 1895 #define DMA_DCHPRI2_CHPRI_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1896 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1897 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 1898 #define DMA_DCHPRI2_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1899 #define DMA_DCHPRI2_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1900 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 1901 #define DMA_DCHPRI2_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1902 #define DMA_DCHPRI2_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1903 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 1904
AnnaBridge 171:3a7713b1edbc 1905 /*! @name DCHPRI1 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 1906 #define DMA_DCHPRI1_CHPRI_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1907 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1908 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 1909 #define DMA_DCHPRI1_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1910 #define DMA_DCHPRI1_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1911 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 1912 #define DMA_DCHPRI1_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1913 #define DMA_DCHPRI1_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1914 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 1915
AnnaBridge 171:3a7713b1edbc 1916 /*! @name DCHPRI0 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 1917 #define DMA_DCHPRI0_CHPRI_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 1918 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1919 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 1920 #define DMA_DCHPRI0_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1921 #define DMA_DCHPRI0_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1922 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 1923 #define DMA_DCHPRI0_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 1924 #define DMA_DCHPRI0_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 1925 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 1926
AnnaBridge 171:3a7713b1edbc 1927 /*! @name SADDR - TCD Source Address */
AnnaBridge 171:3a7713b1edbc 1928 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1929 #define DMA_SADDR_SADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1930 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
AnnaBridge 171:3a7713b1edbc 1931
AnnaBridge 171:3a7713b1edbc 1932 /* The count of DMA_SADDR */
AnnaBridge 171:3a7713b1edbc 1933 #define DMA_SADDR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1934
AnnaBridge 171:3a7713b1edbc 1935 /*! @name SOFF - TCD Signed Source Address Offset */
AnnaBridge 171:3a7713b1edbc 1936 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 1937 #define DMA_SOFF_SOFF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1938 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
AnnaBridge 171:3a7713b1edbc 1939
AnnaBridge 171:3a7713b1edbc 1940 /* The count of DMA_SOFF */
AnnaBridge 171:3a7713b1edbc 1941 #define DMA_SOFF_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1942
AnnaBridge 171:3a7713b1edbc 1943 /*! @name ATTR - TCD Transfer Attributes */
AnnaBridge 171:3a7713b1edbc 1944 #define DMA_ATTR_DSIZE_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 1945 #define DMA_ATTR_DSIZE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1946 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 1947 #define DMA_ATTR_DMOD_MASK (0xF8U)
AnnaBridge 171:3a7713b1edbc 1948 #define DMA_ATTR_DMOD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 1949 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
AnnaBridge 171:3a7713b1edbc 1950 #define DMA_ATTR_SSIZE_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 1951 #define DMA_ATTR_SSIZE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1952 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 1953 #define DMA_ATTR_SMOD_MASK (0xF800U)
AnnaBridge 171:3a7713b1edbc 1954 #define DMA_ATTR_SMOD_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 1955 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
AnnaBridge 171:3a7713b1edbc 1956
AnnaBridge 171:3a7713b1edbc 1957 /* The count of DMA_ATTR */
AnnaBridge 171:3a7713b1edbc 1958 #define DMA_ATTR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1959
AnnaBridge 171:3a7713b1edbc 1960 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
AnnaBridge 171:3a7713b1edbc 1961 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1962 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1963 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
AnnaBridge 171:3a7713b1edbc 1964
AnnaBridge 171:3a7713b1edbc 1965 /* The count of DMA_NBYTES_MLNO */
AnnaBridge 171:3a7713b1edbc 1966 #define DMA_NBYTES_MLNO_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1967
AnnaBridge 171:3a7713b1edbc 1968 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
AnnaBridge 171:3a7713b1edbc 1969 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
AnnaBridge 171:3a7713b1edbc 1970 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1971 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
AnnaBridge 171:3a7713b1edbc 1972 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1973 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1974 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 1975 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 1976 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 1977 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 1978
AnnaBridge 171:3a7713b1edbc 1979 /* The count of DMA_NBYTES_MLOFFNO */
AnnaBridge 171:3a7713b1edbc 1980 #define DMA_NBYTES_MLOFFNO_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1981
AnnaBridge 171:3a7713b1edbc 1982 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
AnnaBridge 171:3a7713b1edbc 1983 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 1984 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1985 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
AnnaBridge 171:3a7713b1edbc 1986 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
AnnaBridge 171:3a7713b1edbc 1987 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1988 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
AnnaBridge 171:3a7713b1edbc 1989 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1990 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1991 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 1992 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 1993 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 1994 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 1995
AnnaBridge 171:3a7713b1edbc 1996 /* The count of DMA_NBYTES_MLOFFYES */
AnnaBridge 171:3a7713b1edbc 1997 #define DMA_NBYTES_MLOFFYES_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 1998
AnnaBridge 171:3a7713b1edbc 1999 /*! @name SLAST - TCD Last Source Address Adjustment */
AnnaBridge 171:3a7713b1edbc 2000 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2001 #define DMA_SLAST_SLAST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2002 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
AnnaBridge 171:3a7713b1edbc 2003
AnnaBridge 171:3a7713b1edbc 2004 /* The count of DMA_SLAST */
AnnaBridge 171:3a7713b1edbc 2005 #define DMA_SLAST_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2006
AnnaBridge 171:3a7713b1edbc 2007 /*! @name DADDR - TCD Destination Address */
AnnaBridge 171:3a7713b1edbc 2008 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2009 #define DMA_DADDR_DADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2010 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
AnnaBridge 171:3a7713b1edbc 2011
AnnaBridge 171:3a7713b1edbc 2012 /* The count of DMA_DADDR */
AnnaBridge 171:3a7713b1edbc 2013 #define DMA_DADDR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2014
AnnaBridge 171:3a7713b1edbc 2015 /*! @name DOFF - TCD Signed Destination Address Offset */
AnnaBridge 171:3a7713b1edbc 2016 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 2017 #define DMA_DOFF_DOFF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2018 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
AnnaBridge 171:3a7713b1edbc 2019
AnnaBridge 171:3a7713b1edbc 2020 /* The count of DMA_DOFF */
AnnaBridge 171:3a7713b1edbc 2021 #define DMA_DOFF_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2022
AnnaBridge 171:3a7713b1edbc 2023 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
AnnaBridge 171:3a7713b1edbc 2024 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
AnnaBridge 171:3a7713b1edbc 2025 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2026 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
AnnaBridge 171:3a7713b1edbc 2027 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2028 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2029 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 2030
AnnaBridge 171:3a7713b1edbc 2031 /* The count of DMA_CITER_ELINKNO */
AnnaBridge 171:3a7713b1edbc 2032 #define DMA_CITER_ELINKNO_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2033
AnnaBridge 171:3a7713b1edbc 2034 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
AnnaBridge 171:3a7713b1edbc 2035 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 2036 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2037 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
AnnaBridge 171:3a7713b1edbc 2038 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 2039 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2040 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
AnnaBridge 171:3a7713b1edbc 2041 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2042 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2043 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 2044
AnnaBridge 171:3a7713b1edbc 2045 /* The count of DMA_CITER_ELINKYES */
AnnaBridge 171:3a7713b1edbc 2046 #define DMA_CITER_ELINKYES_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2047
AnnaBridge 171:3a7713b1edbc 2048 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
AnnaBridge 171:3a7713b1edbc 2049 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2050 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2051 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
AnnaBridge 171:3a7713b1edbc 2052
AnnaBridge 171:3a7713b1edbc 2053 /* The count of DMA_DLAST_SGA */
AnnaBridge 171:3a7713b1edbc 2054 #define DMA_DLAST_SGA_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2055
AnnaBridge 171:3a7713b1edbc 2056 /*! @name CSR - TCD Control and Status */
AnnaBridge 171:3a7713b1edbc 2057 #define DMA_CSR_START_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2058 #define DMA_CSR_START_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2059 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
AnnaBridge 171:3a7713b1edbc 2060 #define DMA_CSR_INTMAJOR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2061 #define DMA_CSR_INTMAJOR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2062 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
AnnaBridge 171:3a7713b1edbc 2063 #define DMA_CSR_INTHALF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2064 #define DMA_CSR_INTHALF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2065 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
AnnaBridge 171:3a7713b1edbc 2066 #define DMA_CSR_DREQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2067 #define DMA_CSR_DREQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2068 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
AnnaBridge 171:3a7713b1edbc 2069 #define DMA_CSR_ESG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2070 #define DMA_CSR_ESG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2071 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
AnnaBridge 171:3a7713b1edbc 2072 #define DMA_CSR_MAJORELINK_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2073 #define DMA_CSR_MAJORELINK_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2074 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
AnnaBridge 171:3a7713b1edbc 2075 #define DMA_CSR_ACTIVE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2076 #define DMA_CSR_ACTIVE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2077 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
AnnaBridge 171:3a7713b1edbc 2078 #define DMA_CSR_DONE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2079 #define DMA_CSR_DONE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2080 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
AnnaBridge 171:3a7713b1edbc 2081 #define DMA_CSR_MAJORLINKCH_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 2082 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2083 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
AnnaBridge 171:3a7713b1edbc 2084 #define DMA_CSR_BWC_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 2085 #define DMA_CSR_BWC_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2086 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
AnnaBridge 171:3a7713b1edbc 2087
AnnaBridge 171:3a7713b1edbc 2088 /* The count of DMA_CSR */
AnnaBridge 171:3a7713b1edbc 2089 #define DMA_CSR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2090
AnnaBridge 171:3a7713b1edbc 2091 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
AnnaBridge 171:3a7713b1edbc 2092 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
AnnaBridge 171:3a7713b1edbc 2093 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2094 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
AnnaBridge 171:3a7713b1edbc 2095 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2096 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2097 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 2098
AnnaBridge 171:3a7713b1edbc 2099 /* The count of DMA_BITER_ELINKNO */
AnnaBridge 171:3a7713b1edbc 2100 #define DMA_BITER_ELINKNO_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2101
AnnaBridge 171:3a7713b1edbc 2102 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
AnnaBridge 171:3a7713b1edbc 2103 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 2104 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2105 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
AnnaBridge 171:3a7713b1edbc 2106 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 2107 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2108 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
AnnaBridge 171:3a7713b1edbc 2109 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2110 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2111 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 2112
AnnaBridge 171:3a7713b1edbc 2113 /* The count of DMA_BITER_ELINKYES */
AnnaBridge 171:3a7713b1edbc 2114 #define DMA_BITER_ELINKYES_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2115
AnnaBridge 171:3a7713b1edbc 2116
AnnaBridge 171:3a7713b1edbc 2117 /*!
AnnaBridge 171:3a7713b1edbc 2118 * @}
AnnaBridge 171:3a7713b1edbc 2119 */ /* end of group DMA_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2120
AnnaBridge 171:3a7713b1edbc 2121
AnnaBridge 171:3a7713b1edbc 2122 /* DMA - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2123 /** Peripheral DMA base address */
AnnaBridge 171:3a7713b1edbc 2124 #define DMA_BASE (0x40008000u)
AnnaBridge 171:3a7713b1edbc 2125 /** Peripheral DMA base pointer */
AnnaBridge 171:3a7713b1edbc 2126 #define DMA0 ((DMA_Type *)DMA_BASE)
AnnaBridge 171:3a7713b1edbc 2127 /** Array initializer of DMA peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2128 #define DMA_BASE_ADDRS { DMA_BASE }
AnnaBridge 171:3a7713b1edbc 2129 /** Array initializer of DMA peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2130 #define DMA_BASE_PTRS { DMA0 }
AnnaBridge 171:3a7713b1edbc 2131 /** Interrupt vectors for the DMA peripheral type */
AnnaBridge 171:3a7713b1edbc 2132 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
AnnaBridge 171:3a7713b1edbc 2133
AnnaBridge 171:3a7713b1edbc 2134 /*!
AnnaBridge 171:3a7713b1edbc 2135 * @}
AnnaBridge 171:3a7713b1edbc 2136 */ /* end of group DMA_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2137
AnnaBridge 171:3a7713b1edbc 2138
AnnaBridge 171:3a7713b1edbc 2139 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2140 -- DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2141 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2142
AnnaBridge 171:3a7713b1edbc 2143 /*!
AnnaBridge 171:3a7713b1edbc 2144 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2145 * @{
AnnaBridge 171:3a7713b1edbc 2146 */
AnnaBridge 171:3a7713b1edbc 2147
AnnaBridge 171:3a7713b1edbc 2148 /** DMAMUX - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2149 typedef struct {
AnnaBridge 171:3a7713b1edbc 2150 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
AnnaBridge 171:3a7713b1edbc 2151 } DMAMUX_Type;
AnnaBridge 171:3a7713b1edbc 2152
AnnaBridge 171:3a7713b1edbc 2153 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2154 -- DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 2155 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2156
AnnaBridge 171:3a7713b1edbc 2157 /*!
AnnaBridge 171:3a7713b1edbc 2158 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 2159 * @{
AnnaBridge 171:3a7713b1edbc 2160 */
AnnaBridge 171:3a7713b1edbc 2161
AnnaBridge 171:3a7713b1edbc 2162 /*! @name CHCFG - Channel Configuration register */
AnnaBridge 171:3a7713b1edbc 2163 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 2164 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2165 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
AnnaBridge 171:3a7713b1edbc 2166 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2167 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2168 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 2169 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2170 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2171 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
AnnaBridge 171:3a7713b1edbc 2172
AnnaBridge 171:3a7713b1edbc 2173 /* The count of DMAMUX_CHCFG */
AnnaBridge 171:3a7713b1edbc 2174 #define DMAMUX_CHCFG_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 2175
AnnaBridge 171:3a7713b1edbc 2176
AnnaBridge 171:3a7713b1edbc 2177 /*!
AnnaBridge 171:3a7713b1edbc 2178 * @}
AnnaBridge 171:3a7713b1edbc 2179 */ /* end of group DMAMUX_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2180
AnnaBridge 171:3a7713b1edbc 2181
AnnaBridge 171:3a7713b1edbc 2182 /* DMAMUX - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2183 /** Peripheral DMAMUX0 base address */
AnnaBridge 171:3a7713b1edbc 2184 #define DMAMUX0_BASE (0x40021000u)
AnnaBridge 171:3a7713b1edbc 2185 /** Peripheral DMAMUX0 base pointer */
AnnaBridge 171:3a7713b1edbc 2186 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
AnnaBridge 171:3a7713b1edbc 2187 /** Array initializer of DMAMUX peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2188 #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
AnnaBridge 171:3a7713b1edbc 2189 /** Array initializer of DMAMUX peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2190 #define DMAMUX_BASE_PTRS { DMAMUX0 }
AnnaBridge 171:3a7713b1edbc 2191
AnnaBridge 171:3a7713b1edbc 2192 /*!
AnnaBridge 171:3a7713b1edbc 2193 * @}
AnnaBridge 171:3a7713b1edbc 2194 */ /* end of group DMAMUX_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2195
AnnaBridge 171:3a7713b1edbc 2196
AnnaBridge 171:3a7713b1edbc 2197 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2198 -- FGPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2199 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2200
AnnaBridge 171:3a7713b1edbc 2201 /*!
AnnaBridge 171:3a7713b1edbc 2202 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2203 * @{
AnnaBridge 171:3a7713b1edbc 2204 */
AnnaBridge 171:3a7713b1edbc 2205
AnnaBridge 171:3a7713b1edbc 2206 /** FGPIO - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2207 typedef struct {
AnnaBridge 171:3a7713b1edbc 2208 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2209 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2210 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2211 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 2212 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 2213 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 2214 } FGPIO_Type;
AnnaBridge 171:3a7713b1edbc 2215
AnnaBridge 171:3a7713b1edbc 2216 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2217 -- FGPIO Register Masks
AnnaBridge 171:3a7713b1edbc 2218 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2219
AnnaBridge 171:3a7713b1edbc 2220 /*!
AnnaBridge 171:3a7713b1edbc 2221 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
AnnaBridge 171:3a7713b1edbc 2222 * @{
AnnaBridge 171:3a7713b1edbc 2223 */
AnnaBridge 171:3a7713b1edbc 2224
AnnaBridge 171:3a7713b1edbc 2225 /*! @name PDOR - Port Data Output Register */
AnnaBridge 171:3a7713b1edbc 2226 #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2227 #define FGPIO_PDOR_PDO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2228 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK)
AnnaBridge 171:3a7713b1edbc 2229
AnnaBridge 171:3a7713b1edbc 2230 /*! @name PSOR - Port Set Output Register */
AnnaBridge 171:3a7713b1edbc 2231 #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2232 #define FGPIO_PSOR_PTSO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2233 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK)
AnnaBridge 171:3a7713b1edbc 2234
AnnaBridge 171:3a7713b1edbc 2235 /*! @name PCOR - Port Clear Output Register */
AnnaBridge 171:3a7713b1edbc 2236 #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2237 #define FGPIO_PCOR_PTCO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2238 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK)
AnnaBridge 171:3a7713b1edbc 2239
AnnaBridge 171:3a7713b1edbc 2240 /*! @name PTOR - Port Toggle Output Register */
AnnaBridge 171:3a7713b1edbc 2241 #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2242 #define FGPIO_PTOR_PTTO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2243 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK)
AnnaBridge 171:3a7713b1edbc 2244
AnnaBridge 171:3a7713b1edbc 2245 /*! @name PDIR - Port Data Input Register */
AnnaBridge 171:3a7713b1edbc 2246 #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2247 #define FGPIO_PDIR_PDI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2248 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK)
AnnaBridge 171:3a7713b1edbc 2249
AnnaBridge 171:3a7713b1edbc 2250 /*! @name PDDR - Port Data Direction Register */
AnnaBridge 171:3a7713b1edbc 2251 #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2252 #define FGPIO_PDDR_PDD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2253 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK)
AnnaBridge 171:3a7713b1edbc 2254
AnnaBridge 171:3a7713b1edbc 2255
AnnaBridge 171:3a7713b1edbc 2256 /*!
AnnaBridge 171:3a7713b1edbc 2257 * @}
AnnaBridge 171:3a7713b1edbc 2258 */ /* end of group FGPIO_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2259
AnnaBridge 171:3a7713b1edbc 2260
AnnaBridge 171:3a7713b1edbc 2261 /* FGPIO - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2262 /** Peripheral FGPIOA base address */
AnnaBridge 171:3a7713b1edbc 2263 #define FGPIOA_BASE (0xF8000000u)
AnnaBridge 171:3a7713b1edbc 2264 /** Peripheral FGPIOA base pointer */
AnnaBridge 171:3a7713b1edbc 2265 #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 2266 /** Peripheral FGPIOB base address */
AnnaBridge 171:3a7713b1edbc 2267 #define FGPIOB_BASE (0xF8000040u)
AnnaBridge 171:3a7713b1edbc 2268 /** Peripheral FGPIOB base pointer */
AnnaBridge 171:3a7713b1edbc 2269 #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 2270 /** Peripheral FGPIOC base address */
AnnaBridge 171:3a7713b1edbc 2271 #define FGPIOC_BASE (0xF8000080u)
AnnaBridge 171:3a7713b1edbc 2272 /** Peripheral FGPIOC base pointer */
AnnaBridge 171:3a7713b1edbc 2273 #define FGPIOC ((FGPIO_Type *)FGPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 2274 /** Array initializer of FGPIO peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2275 #define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE }
AnnaBridge 171:3a7713b1edbc 2276 /** Array initializer of FGPIO peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2277 #define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC }
AnnaBridge 171:3a7713b1edbc 2278
AnnaBridge 171:3a7713b1edbc 2279 /*!
AnnaBridge 171:3a7713b1edbc 2280 * @}
AnnaBridge 171:3a7713b1edbc 2281 */ /* end of group FGPIO_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2282
AnnaBridge 171:3a7713b1edbc 2283
AnnaBridge 171:3a7713b1edbc 2284 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2285 -- FTFA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2286 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2287
AnnaBridge 171:3a7713b1edbc 2288 /*!
AnnaBridge 171:3a7713b1edbc 2289 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2290 * @{
AnnaBridge 171:3a7713b1edbc 2291 */
AnnaBridge 171:3a7713b1edbc 2292
AnnaBridge 171:3a7713b1edbc 2293 /** FTFA - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2294 typedef struct {
AnnaBridge 171:3a7713b1edbc 2295 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2296 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 2297 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 2298 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 2299 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2300 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 2301 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 2302 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 2303 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2304 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 2305 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 2306 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 2307 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 2308 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 2309 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 2310 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 2311 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 2312 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
AnnaBridge 171:3a7713b1edbc 2313 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 2314 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
AnnaBridge 171:3a7713b1edbc 2315 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 2316 __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 2317 __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
AnnaBridge 171:3a7713b1edbc 2318 __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
AnnaBridge 171:3a7713b1edbc 2319 __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 2320 __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 2321 __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
AnnaBridge 171:3a7713b1edbc 2322 __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
AnnaBridge 171:3a7713b1edbc 2323 __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
AnnaBridge 171:3a7713b1edbc 2324 __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 2325 __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
AnnaBridge 171:3a7713b1edbc 2326 __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
AnnaBridge 171:3a7713b1edbc 2327 __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
AnnaBridge 171:3a7713b1edbc 2328 __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 2329 __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
AnnaBridge 171:3a7713b1edbc 2330 __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
AnnaBridge 171:3a7713b1edbc 2331 __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
AnnaBridge 171:3a7713b1edbc 2332 __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 2333 uint8_t RESERVED_1[2];
AnnaBridge 171:3a7713b1edbc 2334 __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
AnnaBridge 171:3a7713b1edbc 2335 } FTFA_Type;
AnnaBridge 171:3a7713b1edbc 2336
AnnaBridge 171:3a7713b1edbc 2337 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2338 -- FTFA Register Masks
AnnaBridge 171:3a7713b1edbc 2339 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2340
AnnaBridge 171:3a7713b1edbc 2341 /*!
AnnaBridge 171:3a7713b1edbc 2342 * @addtogroup FTFA_Register_Masks FTFA Register Masks
AnnaBridge 171:3a7713b1edbc 2343 * @{
AnnaBridge 171:3a7713b1edbc 2344 */
AnnaBridge 171:3a7713b1edbc 2345
AnnaBridge 171:3a7713b1edbc 2346 /*! @name FSTAT - Flash Status Register */
AnnaBridge 171:3a7713b1edbc 2347 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2348 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2349 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
AnnaBridge 171:3a7713b1edbc 2350 #define FTFA_FSTAT_FPVIOL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2351 #define FTFA_FSTAT_FPVIOL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2352 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
AnnaBridge 171:3a7713b1edbc 2353 #define FTFA_FSTAT_ACCERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2354 #define FTFA_FSTAT_ACCERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2355 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
AnnaBridge 171:3a7713b1edbc 2356 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2357 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2358 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
AnnaBridge 171:3a7713b1edbc 2359 #define FTFA_FSTAT_CCIF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2360 #define FTFA_FSTAT_CCIF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2361 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
AnnaBridge 171:3a7713b1edbc 2362
AnnaBridge 171:3a7713b1edbc 2363 /*! @name FCNFG - Flash Configuration Register */
AnnaBridge 171:3a7713b1edbc 2364 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2365 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2366 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
AnnaBridge 171:3a7713b1edbc 2367 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2368 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2369 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
AnnaBridge 171:3a7713b1edbc 2370 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2371 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2372 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
AnnaBridge 171:3a7713b1edbc 2373 #define FTFA_FCNFG_CCIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2374 #define FTFA_FCNFG_CCIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2375 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
AnnaBridge 171:3a7713b1edbc 2376
AnnaBridge 171:3a7713b1edbc 2377 /*! @name FSEC - Flash Security Register */
AnnaBridge 171:3a7713b1edbc 2378 #define FTFA_FSEC_SEC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 2379 #define FTFA_FSEC_SEC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2380 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 2381 #define FTFA_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 2382 #define FTFA_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2383 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 2384 #define FTFA_FSEC_MEEN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 2385 #define FTFA_FSEC_MEEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2386 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 2387 #define FTFA_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 2388 #define FTFA_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2389 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 2390
AnnaBridge 171:3a7713b1edbc 2391 /*! @name FOPT - Flash Option Register */
AnnaBridge 171:3a7713b1edbc 2392 #define FTFA_FOPT_OPT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2393 #define FTFA_FOPT_OPT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2394 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
AnnaBridge 171:3a7713b1edbc 2395
AnnaBridge 171:3a7713b1edbc 2396 /*! @name FCCOB3 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2397 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2398 #define FTFA_FCCOB3_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2399 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2400
AnnaBridge 171:3a7713b1edbc 2401 /*! @name FCCOB2 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2402 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2403 #define FTFA_FCCOB2_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2404 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2405
AnnaBridge 171:3a7713b1edbc 2406 /*! @name FCCOB1 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2407 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2408 #define FTFA_FCCOB1_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2409 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2410
AnnaBridge 171:3a7713b1edbc 2411 /*! @name FCCOB0 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2412 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2413 #define FTFA_FCCOB0_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2414 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2415
AnnaBridge 171:3a7713b1edbc 2416 /*! @name FCCOB7 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2417 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2418 #define FTFA_FCCOB7_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2419 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2420
AnnaBridge 171:3a7713b1edbc 2421 /*! @name FCCOB6 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2422 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2423 #define FTFA_FCCOB6_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2424 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2425
AnnaBridge 171:3a7713b1edbc 2426 /*! @name FCCOB5 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2427 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2428 #define FTFA_FCCOB5_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2429 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2430
AnnaBridge 171:3a7713b1edbc 2431 /*! @name FCCOB4 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2432 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2433 #define FTFA_FCCOB4_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2434 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2435
AnnaBridge 171:3a7713b1edbc 2436 /*! @name FCCOBB - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2437 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2438 #define FTFA_FCCOBB_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2439 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2440
AnnaBridge 171:3a7713b1edbc 2441 /*! @name FCCOBA - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2442 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2443 #define FTFA_FCCOBA_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2444 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2445
AnnaBridge 171:3a7713b1edbc 2446 /*! @name FCCOB9 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2447 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2448 #define FTFA_FCCOB9_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2449 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2450
AnnaBridge 171:3a7713b1edbc 2451 /*! @name FCCOB8 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 2452 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2453 #define FTFA_FCCOB8_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2454 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 2455
AnnaBridge 171:3a7713b1edbc 2456 /*! @name FPROT3 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 2457 #define FTFA_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2458 #define FTFA_FPROT3_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2459 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 2460
AnnaBridge 171:3a7713b1edbc 2461 /*! @name FPROT2 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 2462 #define FTFA_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2463 #define FTFA_FPROT2_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2464 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 2465
AnnaBridge 171:3a7713b1edbc 2466 /*! @name FPROT1 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 2467 #define FTFA_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2468 #define FTFA_FPROT1_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2469 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 2470
AnnaBridge 171:3a7713b1edbc 2471 /*! @name FPROT0 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 2472 #define FTFA_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2473 #define FTFA_FPROT0_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2474 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 2475
AnnaBridge 171:3a7713b1edbc 2476 /*! @name XACCH3 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2477 #define FTFA_XACCH3_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2478 #define FTFA_XACCH3_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2479 #define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
AnnaBridge 171:3a7713b1edbc 2480
AnnaBridge 171:3a7713b1edbc 2481 /*! @name XACCH2 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2482 #define FTFA_XACCH2_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2483 #define FTFA_XACCH2_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2484 #define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
AnnaBridge 171:3a7713b1edbc 2485
AnnaBridge 171:3a7713b1edbc 2486 /*! @name XACCH1 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2487 #define FTFA_XACCH1_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2488 #define FTFA_XACCH1_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2489 #define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
AnnaBridge 171:3a7713b1edbc 2490
AnnaBridge 171:3a7713b1edbc 2491 /*! @name XACCH0 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2492 #define FTFA_XACCH0_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2493 #define FTFA_XACCH0_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2494 #define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
AnnaBridge 171:3a7713b1edbc 2495
AnnaBridge 171:3a7713b1edbc 2496 /*! @name XACCL3 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2497 #define FTFA_XACCL3_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2498 #define FTFA_XACCL3_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2499 #define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
AnnaBridge 171:3a7713b1edbc 2500
AnnaBridge 171:3a7713b1edbc 2501 /*! @name XACCL2 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2502 #define FTFA_XACCL2_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2503 #define FTFA_XACCL2_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2504 #define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
AnnaBridge 171:3a7713b1edbc 2505
AnnaBridge 171:3a7713b1edbc 2506 /*! @name XACCL1 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2507 #define FTFA_XACCL1_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2508 #define FTFA_XACCL1_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2509 #define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
AnnaBridge 171:3a7713b1edbc 2510
AnnaBridge 171:3a7713b1edbc 2511 /*! @name XACCL0 - Execute-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2512 #define FTFA_XACCL0_XA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2513 #define FTFA_XACCL0_XA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2514 #define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
AnnaBridge 171:3a7713b1edbc 2515
AnnaBridge 171:3a7713b1edbc 2516 /*! @name SACCH3 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2517 #define FTFA_SACCH3_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2518 #define FTFA_SACCH3_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2519 #define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
AnnaBridge 171:3a7713b1edbc 2520
AnnaBridge 171:3a7713b1edbc 2521 /*! @name SACCH2 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2522 #define FTFA_SACCH2_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2523 #define FTFA_SACCH2_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2524 #define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
AnnaBridge 171:3a7713b1edbc 2525
AnnaBridge 171:3a7713b1edbc 2526 /*! @name SACCH1 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2527 #define FTFA_SACCH1_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2528 #define FTFA_SACCH1_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2529 #define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
AnnaBridge 171:3a7713b1edbc 2530
AnnaBridge 171:3a7713b1edbc 2531 /*! @name SACCH0 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2532 #define FTFA_SACCH0_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2533 #define FTFA_SACCH0_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2534 #define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
AnnaBridge 171:3a7713b1edbc 2535
AnnaBridge 171:3a7713b1edbc 2536 /*! @name SACCL3 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2537 #define FTFA_SACCL3_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2538 #define FTFA_SACCL3_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2539 #define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
AnnaBridge 171:3a7713b1edbc 2540
AnnaBridge 171:3a7713b1edbc 2541 /*! @name SACCL2 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2542 #define FTFA_SACCL2_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2543 #define FTFA_SACCL2_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2544 #define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
AnnaBridge 171:3a7713b1edbc 2545
AnnaBridge 171:3a7713b1edbc 2546 /*! @name SACCL1 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2547 #define FTFA_SACCL1_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2548 #define FTFA_SACCL1_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2549 #define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
AnnaBridge 171:3a7713b1edbc 2550
AnnaBridge 171:3a7713b1edbc 2551 /*! @name SACCL0 - Supervisor-only Access Registers */
AnnaBridge 171:3a7713b1edbc 2552 #define FTFA_SACCL0_SA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2553 #define FTFA_SACCL0_SA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2554 #define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
AnnaBridge 171:3a7713b1edbc 2555
AnnaBridge 171:3a7713b1edbc 2556 /*! @name FACSS - Flash Access Segment Size Register */
AnnaBridge 171:3a7713b1edbc 2557 #define FTFA_FACSS_SGSIZE_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2558 #define FTFA_FACSS_SGSIZE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2559 #define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 2560
AnnaBridge 171:3a7713b1edbc 2561 /*! @name FACSN - Flash Access Segment Number Register */
AnnaBridge 171:3a7713b1edbc 2562 #define FTFA_FACSN_NUMSG_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2563 #define FTFA_FACSN_NUMSG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2564 #define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
AnnaBridge 171:3a7713b1edbc 2565
AnnaBridge 171:3a7713b1edbc 2566
AnnaBridge 171:3a7713b1edbc 2567 /*!
AnnaBridge 171:3a7713b1edbc 2568 * @}
AnnaBridge 171:3a7713b1edbc 2569 */ /* end of group FTFA_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2570
AnnaBridge 171:3a7713b1edbc 2571
AnnaBridge 171:3a7713b1edbc 2572 /* FTFA - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2573 /** Peripheral FTFA base address */
AnnaBridge 171:3a7713b1edbc 2574 #define FTFA_BASE (0x40020000u)
AnnaBridge 171:3a7713b1edbc 2575 /** Peripheral FTFA base pointer */
AnnaBridge 171:3a7713b1edbc 2576 #define FTFA ((FTFA_Type *)FTFA_BASE)
AnnaBridge 171:3a7713b1edbc 2577 /** Array initializer of FTFA peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2578 #define FTFA_BASE_ADDRS { FTFA_BASE }
AnnaBridge 171:3a7713b1edbc 2579 /** Array initializer of FTFA peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2580 #define FTFA_BASE_PTRS { FTFA }
AnnaBridge 171:3a7713b1edbc 2581 /** Interrupt vectors for the FTFA peripheral type */
AnnaBridge 171:3a7713b1edbc 2582 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
AnnaBridge 171:3a7713b1edbc 2583
AnnaBridge 171:3a7713b1edbc 2584 /*!
AnnaBridge 171:3a7713b1edbc 2585 * @}
AnnaBridge 171:3a7713b1edbc 2586 */ /* end of group FTFA_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2587
AnnaBridge 171:3a7713b1edbc 2588
AnnaBridge 171:3a7713b1edbc 2589 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2590 -- GENFSK Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2591 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2592
AnnaBridge 171:3a7713b1edbc 2593 /*!
AnnaBridge 171:3a7713b1edbc 2594 * @addtogroup GENFSK_Peripheral_Access_Layer GENFSK Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2595 * @{
AnnaBridge 171:3a7713b1edbc 2596 */
AnnaBridge 171:3a7713b1edbc 2597
AnnaBridge 171:3a7713b1edbc 2598 /** GENFSK - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2599 typedef struct {
AnnaBridge 171:3a7713b1edbc 2600 __IO uint32_t IRQ_CTRL; /**< IRQ CONTROL, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2601 __IO uint32_t EVENT_TMR; /**< EVENT TIMER, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2602 __IO uint32_t T1_CMP; /**< T1 COMPARE, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2603 __IO uint32_t T2_CMP; /**< T2 COMPARE, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 2604 __I uint32_t TIMESTAMP; /**< TIMESTAMP, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 2605 __IO uint32_t XCVR_CTRL; /**< TRANSCEIVER CONTROL, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 2606 __I uint32_t XCVR_STS; /**< TRANSCEIVER STATUS, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 2607 __IO uint32_t XCVR_CFG; /**< TRANSCEIVER CONFIGURATION, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 2608 __IO uint32_t CHANNEL_NUM; /**< CHANNEL NUMBER, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 2609 __IO uint32_t TX_POWER; /**< TRANSMIT POWER, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 2610 __IO uint32_t NTW_ADR_CTRL; /**< NETWORK ADDRESS CONTROL, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 2611 __IO uint32_t NTW_ADR_0; /**< NETWORK ADDRESS 0, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 2612 __IO uint32_t NTW_ADR_1; /**< NETWORK ADDRESS 1, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 2613 __IO uint32_t NTW_ADR_2; /**< NETWORK ADDRESS 2, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 2614 __IO uint32_t NTW_ADR_3; /**< NETWORK ADDRESS 3, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 2615 __IO uint32_t RX_WATERMARK; /**< RECEIVE WATERMARK, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 2616 __IO uint32_t DSM_CTRL; /**< DSM CONTROL, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 2617 __I uint32_t PART_ID; /**< PART ID, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 2618 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 2619 __IO uint32_t PACKET_CFG; /**< PACKET CONFIGURATION, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 2620 __IO uint32_t H0_CFG; /**< H0 CONFIGURATION, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 2621 __IO uint32_t H1_CFG; /**< H1 CONFIGURATION, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 2622 __IO uint32_t CRC_CFG; /**< CRC CONFIGURATION, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 2623 __IO uint32_t CRC_INIT; /**< CRC INITIALIZATION, offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 2624 __IO uint32_t CRC_POLY; /**< CRC POLYNOMIAL, offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 2625 __IO uint32_t CRC_XOR_OUT; /**< CRC XOR OUT, offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 2626 __IO uint32_t WHITEN_CFG; /**< WHITENER CONFIGURATION, offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 2627 __IO uint32_t WHITEN_POLY; /**< WHITENER POLYNOMIAL, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 2628 __IO uint32_t WHITEN_SZ_THR; /**< WHITENER SIZE THRESHOLD, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 2629 __IO uint32_t BITRATE; /**< BIT RATE, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 2630 __IO uint32_t PB_PARTITION; /**< PACKET BUFFER PARTITION POINT, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 2631 } GENFSK_Type;
AnnaBridge 171:3a7713b1edbc 2632
AnnaBridge 171:3a7713b1edbc 2633 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2634 -- GENFSK Register Masks
AnnaBridge 171:3a7713b1edbc 2635 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2636
AnnaBridge 171:3a7713b1edbc 2637 /*!
AnnaBridge 171:3a7713b1edbc 2638 * @addtogroup GENFSK_Register_Masks GENFSK Register Masks
AnnaBridge 171:3a7713b1edbc 2639 * @{
AnnaBridge 171:3a7713b1edbc 2640 */
AnnaBridge 171:3a7713b1edbc 2641
AnnaBridge 171:3a7713b1edbc 2642 /*! @name IRQ_CTRL - IRQ CONTROL */
AnnaBridge 171:3a7713b1edbc 2643 #define GENFSK_IRQ_CTRL_SEQ_END_IRQ_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2644 #define GENFSK_IRQ_CTRL_SEQ_END_IRQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2645 #define GENFSK_IRQ_CTRL_SEQ_END_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_SEQ_END_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_SEQ_END_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 2646 #define GENFSK_IRQ_CTRL_TX_IRQ_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2647 #define GENFSK_IRQ_CTRL_TX_IRQ_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2648 #define GENFSK_IRQ_CTRL_TX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TX_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_TX_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 2649 #define GENFSK_IRQ_CTRL_RX_IRQ_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2650 #define GENFSK_IRQ_CTRL_RX_IRQ_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2651 #define GENFSK_IRQ_CTRL_RX_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_RX_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 2652 #define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2653 #define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2654 #define GENFSK_IRQ_CTRL_NTW_ADR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_NTW_ADR_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_NTW_ADR_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 2655 #define GENFSK_IRQ_CTRL_T1_IRQ_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2656 #define GENFSK_IRQ_CTRL_T1_IRQ_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2657 #define GENFSK_IRQ_CTRL_T1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T1_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_T1_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 2658 #define GENFSK_IRQ_CTRL_T2_IRQ_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2659 #define GENFSK_IRQ_CTRL_T2_IRQ_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2660 #define GENFSK_IRQ_CTRL_T2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 2661 #define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2662 #define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2663 #define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 2664 #define GENFSK_IRQ_CTRL_WAKE_IRQ_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2665 #define GENFSK_IRQ_CTRL_WAKE_IRQ_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2666 #define GENFSK_IRQ_CTRL_WAKE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_WAKE_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_WAKE_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 2667 #define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 2668 #define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2669 #define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 2670 #define GENFSK_IRQ_CTRL_TSM_IRQ_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 2671 #define GENFSK_IRQ_CTRL_TSM_IRQ_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2672 #define GENFSK_IRQ_CTRL_TSM_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TSM_IRQ_SHIFT)) & GENFSK_IRQ_CTRL_TSM_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 2673 #define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2674 #define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2675 #define GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_SEQ_END_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2676 #define GENFSK_IRQ_CTRL_TX_IRQ_EN_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 2677 #define GENFSK_IRQ_CTRL_TX_IRQ_EN_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2678 #define GENFSK_IRQ_CTRL_TX_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TX_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_TX_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2679 #define GENFSK_IRQ_CTRL_RX_IRQ_EN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 2680 #define GENFSK_IRQ_CTRL_RX_IRQ_EN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 2681 #define GENFSK_IRQ_CTRL_RX_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_RX_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2682 #define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 2683 #define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 2684 #define GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_NTW_ADR_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2685 #define GENFSK_IRQ_CTRL_T1_IRQ_EN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 2686 #define GENFSK_IRQ_CTRL_T1_IRQ_EN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 2687 #define GENFSK_IRQ_CTRL_T1_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T1_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T1_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2688 #define GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 2689 #define GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 2690 #define GENFSK_IRQ_CTRL_T2_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_T2_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_T2_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2691 #define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 2692 #define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 2693 #define GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_PLL_UNLOCK_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2694 #define GENFSK_IRQ_CTRL_WAKE_IRQ_EN_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 2695 #define GENFSK_IRQ_CTRL_WAKE_IRQ_EN_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 2696 #define GENFSK_IRQ_CTRL_WAKE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_WAKE_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_WAKE_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2697 #define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 2698 #define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2699 #define GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_RX_WATERMARK_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2700 #define GENFSK_IRQ_CTRL_TSM_IRQ_EN_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 2701 #define GENFSK_IRQ_CTRL_TSM_IRQ_EN_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 2702 #define GENFSK_IRQ_CTRL_TSM_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_TSM_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_TSM_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2703 #define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 2704 #define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 2705 #define GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_SHIFT)) & GENFSK_IRQ_CTRL_GENERIC_FSK_IRQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2706 #define GENFSK_IRQ_CTRL_CRC_IGNORE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 2707 #define GENFSK_IRQ_CTRL_CRC_IGNORE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 2708 #define GENFSK_IRQ_CTRL_CRC_IGNORE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_IGNORE_SHIFT)) & GENFSK_IRQ_CTRL_CRC_IGNORE_MASK)
AnnaBridge 171:3a7713b1edbc 2709 #define GENFSK_IRQ_CTRL_CRC_VALID_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2710 #define GENFSK_IRQ_CTRL_CRC_VALID_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2711 #define GENFSK_IRQ_CTRL_CRC_VALID(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_IRQ_CTRL_CRC_VALID_SHIFT)) & GENFSK_IRQ_CTRL_CRC_VALID_MASK)
AnnaBridge 171:3a7713b1edbc 2712
AnnaBridge 171:3a7713b1edbc 2713 /*! @name EVENT_TMR - EVENT TIMER */
AnnaBridge 171:3a7713b1edbc 2714 #define GENFSK_EVENT_TMR_EVENT_TMR_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2715 #define GENFSK_EVENT_TMR_EVENT_TMR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2716 #define GENFSK_EVENT_TMR_EVENT_TMR(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_MASK)
AnnaBridge 171:3a7713b1edbc 2717 #define GENFSK_EVENT_TMR_EVENT_TMR_LD_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 2718 #define GENFSK_EVENT_TMR_EVENT_TMR_LD_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2719 #define GENFSK_EVENT_TMR_EVENT_TMR_LD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_LD_MASK)
AnnaBridge 171:3a7713b1edbc 2720 #define GENFSK_EVENT_TMR_EVENT_TMR_ADD_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 2721 #define GENFSK_EVENT_TMR_EVENT_TMR_ADD_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 2722 #define GENFSK_EVENT_TMR_EVENT_TMR_ADD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & GENFSK_EVENT_TMR_EVENT_TMR_ADD_MASK)
AnnaBridge 171:3a7713b1edbc 2723
AnnaBridge 171:3a7713b1edbc 2724 /*! @name T1_CMP - T1 COMPARE */
AnnaBridge 171:3a7713b1edbc 2725 #define GENFSK_T1_CMP_T1_CMP_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2726 #define GENFSK_T1_CMP_T1_CMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2727 #define GENFSK_T1_CMP_T1_CMP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_SHIFT)) & GENFSK_T1_CMP_T1_CMP_MASK)
AnnaBridge 171:3a7713b1edbc 2728 #define GENFSK_T1_CMP_T1_CMP_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 2729 #define GENFSK_T1_CMP_T1_CMP_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2730 #define GENFSK_T1_CMP_T1_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_T1_CMP_T1_CMP_EN_SHIFT)) & GENFSK_T1_CMP_T1_CMP_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2731
AnnaBridge 171:3a7713b1edbc 2732 /*! @name T2_CMP - T2 COMPARE */
AnnaBridge 171:3a7713b1edbc 2733 #define GENFSK_T2_CMP_T2_CMP_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2734 #define GENFSK_T2_CMP_T2_CMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2735 #define GENFSK_T2_CMP_T2_CMP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_T2_CMP_T2_CMP_SHIFT)) & GENFSK_T2_CMP_T2_CMP_MASK)
AnnaBridge 171:3a7713b1edbc 2736 #define GENFSK_T2_CMP_T2_CMP_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 2737 #define GENFSK_T2_CMP_T2_CMP_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2738 #define GENFSK_T2_CMP_T2_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_T2_CMP_T2_CMP_EN_SHIFT)) & GENFSK_T2_CMP_T2_CMP_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2739
AnnaBridge 171:3a7713b1edbc 2740 /*! @name TIMESTAMP - TIMESTAMP */
AnnaBridge 171:3a7713b1edbc 2741 #define GENFSK_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2742 #define GENFSK_TIMESTAMP_TIMESTAMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2743 #define GENFSK_TIMESTAMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_TIMESTAMP_TIMESTAMP_SHIFT)) & GENFSK_TIMESTAMP_TIMESTAMP_MASK)
AnnaBridge 171:3a7713b1edbc 2744
AnnaBridge 171:3a7713b1edbc 2745 /*! @name XCVR_CTRL - TRANSCEIVER CONTROL */
AnnaBridge 171:3a7713b1edbc 2746 #define GENFSK_XCVR_CTRL_SEQCMD_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2747 #define GENFSK_XCVR_CTRL_SEQCMD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2748 #define GENFSK_XCVR_CTRL_SEQCMD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_SEQCMD_SHIFT)) & GENFSK_XCVR_CTRL_SEQCMD_MASK)
AnnaBridge 171:3a7713b1edbc 2749 #define GENFSK_XCVR_CTRL_CMDDEC_CS_MASK (0x7000000U)
AnnaBridge 171:3a7713b1edbc 2750 #define GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2751 #define GENFSK_XCVR_CTRL_CMDDEC_CS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_CMDDEC_CS_SHIFT)) & GENFSK_XCVR_CTRL_CMDDEC_CS_MASK)
AnnaBridge 171:3a7713b1edbc 2752 #define GENFSK_XCVR_CTRL_XCVR_BUSY_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2753 #define GENFSK_XCVR_CTRL_XCVR_BUSY_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2754 #define GENFSK_XCVR_CTRL_XCVR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CTRL_XCVR_BUSY_SHIFT)) & GENFSK_XCVR_CTRL_XCVR_BUSY_MASK)
AnnaBridge 171:3a7713b1edbc 2755
AnnaBridge 171:3a7713b1edbc 2756 /*! @name XCVR_STS - TRANSCEIVER STATUS */
AnnaBridge 171:3a7713b1edbc 2757 #define GENFSK_XCVR_STS_TX_START_T1_PEND_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2758 #define GENFSK_XCVR_STS_TX_START_T1_PEND_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2759 #define GENFSK_XCVR_STS_TX_START_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_START_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_TX_START_T1_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 2760 #define GENFSK_XCVR_STS_TX_START_T2_PEND_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2761 #define GENFSK_XCVR_STS_TX_START_T2_PEND_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2762 #define GENFSK_XCVR_STS_TX_START_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_START_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_TX_START_T2_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 2763 #define GENFSK_XCVR_STS_TX_IN_WARMUP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2764 #define GENFSK_XCVR_STS_TX_IN_WARMUP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2765 #define GENFSK_XCVR_STS_TX_IN_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_WARMUP_SHIFT)) & GENFSK_XCVR_STS_TX_IN_WARMUP_MASK)
AnnaBridge 171:3a7713b1edbc 2766 #define GENFSK_XCVR_STS_TX_IN_PROGRESS_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2767 #define GENFSK_XCVR_STS_TX_IN_PROGRESS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2768 #define GENFSK_XCVR_STS_TX_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_PROGRESS_SHIFT)) & GENFSK_XCVR_STS_TX_IN_PROGRESS_MASK)
AnnaBridge 171:3a7713b1edbc 2769 #define GENFSK_XCVR_STS_TX_IN_WARMDN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2770 #define GENFSK_XCVR_STS_TX_IN_WARMDN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2771 #define GENFSK_XCVR_STS_TX_IN_WARMDN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_TX_IN_WARMDN_SHIFT)) & GENFSK_XCVR_STS_TX_IN_WARMDN_MASK)
AnnaBridge 171:3a7713b1edbc 2772 #define GENFSK_XCVR_STS_RX_START_T1_PEND_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2773 #define GENFSK_XCVR_STS_RX_START_T1_PEND_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2774 #define GENFSK_XCVR_STS_RX_START_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_START_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_START_T1_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 2775 #define GENFSK_XCVR_STS_RX_START_T2_PEND_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2776 #define GENFSK_XCVR_STS_RX_START_T2_PEND_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2777 #define GENFSK_XCVR_STS_RX_START_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_START_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_START_T2_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 2778 #define GENFSK_XCVR_STS_RX_STOP_T1_PEND_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2779 #define GENFSK_XCVR_STS_RX_STOP_T1_PEND_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2780 #define GENFSK_XCVR_STS_RX_STOP_T1_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_STOP_T1_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_STOP_T1_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 2781 #define GENFSK_XCVR_STS_RX_STOP_T2_PEND_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 2782 #define GENFSK_XCVR_STS_RX_STOP_T2_PEND_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2783 #define GENFSK_XCVR_STS_RX_STOP_T2_PEND(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_STOP_T2_PEND_SHIFT)) & GENFSK_XCVR_STS_RX_STOP_T2_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 2784 #define GENFSK_XCVR_STS_RX_IN_WARMUP_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 2785 #define GENFSK_XCVR_STS_RX_IN_WARMUP_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2786 #define GENFSK_XCVR_STS_RX_IN_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_WARMUP_SHIFT)) & GENFSK_XCVR_STS_RX_IN_WARMUP_MASK)
AnnaBridge 171:3a7713b1edbc 2787 #define GENFSK_XCVR_STS_RX_IN_SEARCH_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 2788 #define GENFSK_XCVR_STS_RX_IN_SEARCH_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 2789 #define GENFSK_XCVR_STS_RX_IN_SEARCH(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_SEARCH_SHIFT)) & GENFSK_XCVR_STS_RX_IN_SEARCH_MASK)
AnnaBridge 171:3a7713b1edbc 2790 #define GENFSK_XCVR_STS_RX_IN_PROGRESS_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 2791 #define GENFSK_XCVR_STS_RX_IN_PROGRESS_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 2792 #define GENFSK_XCVR_STS_RX_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_PROGRESS_SHIFT)) & GENFSK_XCVR_STS_RX_IN_PROGRESS_MASK)
AnnaBridge 171:3a7713b1edbc 2793 #define GENFSK_XCVR_STS_RX_IN_WARMDN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 2794 #define GENFSK_XCVR_STS_RX_IN_WARMDN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2795 #define GENFSK_XCVR_STS_RX_IN_WARMDN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RX_IN_WARMDN_SHIFT)) & GENFSK_XCVR_STS_RX_IN_WARMDN_MASK)
AnnaBridge 171:3a7713b1edbc 2796 #define GENFSK_XCVR_STS_LQI_VALID_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2797 #define GENFSK_XCVR_STS_LQI_VALID_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2798 #define GENFSK_XCVR_STS_LQI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_LQI_VALID_SHIFT)) & GENFSK_XCVR_STS_LQI_VALID_MASK)
AnnaBridge 171:3a7713b1edbc 2799 #define GENFSK_XCVR_STS_CRC_VALID_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2800 #define GENFSK_XCVR_STS_CRC_VALID_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2801 #define GENFSK_XCVR_STS_CRC_VALID(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_CRC_VALID_SHIFT)) & GENFSK_XCVR_STS_CRC_VALID_MASK)
AnnaBridge 171:3a7713b1edbc 2802 #define GENFSK_XCVR_STS_RSSI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 2803 #define GENFSK_XCVR_STS_RSSI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2804 #define GENFSK_XCVR_STS_RSSI(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_RSSI_SHIFT)) & GENFSK_XCVR_STS_RSSI_MASK)
AnnaBridge 171:3a7713b1edbc 2805 #define GENFSK_XCVR_STS_LQI_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 2806 #define GENFSK_XCVR_STS_LQI_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2807 #define GENFSK_XCVR_STS_LQI(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_STS_LQI_SHIFT)) & GENFSK_XCVR_STS_LQI_MASK)
AnnaBridge 171:3a7713b1edbc 2808
AnnaBridge 171:3a7713b1edbc 2809 /*! @name XCVR_CFG - TRANSCEIVER CONFIGURATION */
AnnaBridge 171:3a7713b1edbc 2810 #define GENFSK_XCVR_CFG_TX_WHITEN_DIS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2811 #define GENFSK_XCVR_CFG_TX_WHITEN_DIS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2812 #define GENFSK_XCVR_CFG_TX_WHITEN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_TX_WHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_TX_WHITEN_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 2813 #define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2814 #define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2815 #define GENFSK_XCVR_CFG_RX_DEWHITEN_DIS(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_SHIFT)) & GENFSK_XCVR_CFG_RX_DEWHITEN_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 2816 #define GENFSK_XCVR_CFG_SW_CRC_EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2817 #define GENFSK_XCVR_CFG_SW_CRC_EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2818 #define GENFSK_XCVR_CFG_SW_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_SW_CRC_EN_SHIFT)) & GENFSK_XCVR_CFG_SW_CRC_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2819 #define GENFSK_XCVR_CFG_PREAMBLE_SZ_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 2820 #define GENFSK_XCVR_CFG_PREAMBLE_SZ_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2821 #define GENFSK_XCVR_CFG_PREAMBLE_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_PREAMBLE_SZ_SHIFT)) & GENFSK_XCVR_CFG_PREAMBLE_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 2822 #define GENFSK_XCVR_CFG_TX_WARMUP_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 2823 #define GENFSK_XCVR_CFG_TX_WARMUP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2824 #define GENFSK_XCVR_CFG_TX_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_TX_WARMUP_SHIFT)) & GENFSK_XCVR_CFG_TX_WARMUP_MASK)
AnnaBridge 171:3a7713b1edbc 2825 #define GENFSK_XCVR_CFG_RX_WARMUP_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 2826 #define GENFSK_XCVR_CFG_RX_WARMUP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2827 #define GENFSK_XCVR_CFG_RX_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_XCVR_CFG_RX_WARMUP_SHIFT)) & GENFSK_XCVR_CFG_RX_WARMUP_MASK)
AnnaBridge 171:3a7713b1edbc 2828
AnnaBridge 171:3a7713b1edbc 2829 /*! @name CHANNEL_NUM - CHANNEL NUMBER */
AnnaBridge 171:3a7713b1edbc 2830 #define GENFSK_CHANNEL_NUM_CHANNEL_NUM_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 2831 #define GENFSK_CHANNEL_NUM_CHANNEL_NUM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2832 #define GENFSK_CHANNEL_NUM_CHANNEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CHANNEL_NUM_CHANNEL_NUM_SHIFT)) & GENFSK_CHANNEL_NUM_CHANNEL_NUM_MASK)
AnnaBridge 171:3a7713b1edbc 2833
AnnaBridge 171:3a7713b1edbc 2834 /*! @name TX_POWER - TRANSMIT POWER */
AnnaBridge 171:3a7713b1edbc 2835 #define GENFSK_TX_POWER_TX_POWER_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 2836 #define GENFSK_TX_POWER_TX_POWER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2837 #define GENFSK_TX_POWER_TX_POWER(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_TX_POWER_TX_POWER_SHIFT)) & GENFSK_TX_POWER_TX_POWER_MASK)
AnnaBridge 171:3a7713b1edbc 2838
AnnaBridge 171:3a7713b1edbc 2839 /*! @name NTW_ADR_CTRL - NETWORK ADDRESS CONTROL */
AnnaBridge 171:3a7713b1edbc 2840 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 2841 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2842 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2843 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 2844 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2845 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_MCH_MASK)
AnnaBridge 171:3a7713b1edbc 2846 #define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 2847 #define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2848 #define GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR0_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 2849 #define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK (0xC00U)
AnnaBridge 171:3a7713b1edbc 2850 #define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 2851 #define GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR1_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 2852 #define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 2853 #define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2854 #define GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR2_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 2855 #define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 2856 #define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2857 #define GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR3_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 2858 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 2859 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2860 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR0_MASK)
AnnaBridge 171:3a7713b1edbc 2861 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_MASK (0x700000U)
AnnaBridge 171:3a7713b1edbc 2862 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 2863 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR1_MASK)
AnnaBridge 171:3a7713b1edbc 2864 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_MASK (0x7000000U)
AnnaBridge 171:3a7713b1edbc 2865 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2866 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR2_MASK)
AnnaBridge 171:3a7713b1edbc 2867 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_MASK (0x70000000U)
AnnaBridge 171:3a7713b1edbc 2868 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2869 #define GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_SHIFT)) & GENFSK_NTW_ADR_CTRL_NTW_ADR_THR3_MASK)
AnnaBridge 171:3a7713b1edbc 2870
AnnaBridge 171:3a7713b1edbc 2871 /*! @name NTW_ADR_0 - NETWORK ADDRESS 0 */
AnnaBridge 171:3a7713b1edbc 2872 #define GENFSK_NTW_ADR_0_NTW_ADR_0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2873 #define GENFSK_NTW_ADR_0_NTW_ADR_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2874 #define GENFSK_NTW_ADR_0_NTW_ADR_0(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_0_NTW_ADR_0_SHIFT)) & GENFSK_NTW_ADR_0_NTW_ADR_0_MASK)
AnnaBridge 171:3a7713b1edbc 2875
AnnaBridge 171:3a7713b1edbc 2876 /*! @name NTW_ADR_1 - NETWORK ADDRESS 1 */
AnnaBridge 171:3a7713b1edbc 2877 #define GENFSK_NTW_ADR_1_NTW_ADR_1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2878 #define GENFSK_NTW_ADR_1_NTW_ADR_1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2879 #define GENFSK_NTW_ADR_1_NTW_ADR_1(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_1_NTW_ADR_1_SHIFT)) & GENFSK_NTW_ADR_1_NTW_ADR_1_MASK)
AnnaBridge 171:3a7713b1edbc 2880
AnnaBridge 171:3a7713b1edbc 2881 /*! @name NTW_ADR_2 - NETWORK ADDRESS 2 */
AnnaBridge 171:3a7713b1edbc 2882 #define GENFSK_NTW_ADR_2_NTW_ADR_2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2883 #define GENFSK_NTW_ADR_2_NTW_ADR_2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2884 #define GENFSK_NTW_ADR_2_NTW_ADR_2(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_2_NTW_ADR_2_SHIFT)) & GENFSK_NTW_ADR_2_NTW_ADR_2_MASK)
AnnaBridge 171:3a7713b1edbc 2885
AnnaBridge 171:3a7713b1edbc 2886 /*! @name NTW_ADR_3 - NETWORK ADDRESS 3 */
AnnaBridge 171:3a7713b1edbc 2887 #define GENFSK_NTW_ADR_3_NTW_ADR_3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2888 #define GENFSK_NTW_ADR_3_NTW_ADR_3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2889 #define GENFSK_NTW_ADR_3_NTW_ADR_3(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_NTW_ADR_3_NTW_ADR_3_SHIFT)) & GENFSK_NTW_ADR_3_NTW_ADR_3_MASK)
AnnaBridge 171:3a7713b1edbc 2890
AnnaBridge 171:3a7713b1edbc 2891 /*! @name RX_WATERMARK - RECEIVE WATERMARK */
AnnaBridge 171:3a7713b1edbc 2892 #define GENFSK_RX_WATERMARK_RX_WATERMARK_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 2893 #define GENFSK_RX_WATERMARK_RX_WATERMARK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2894 #define GENFSK_RX_WATERMARK_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_WATERMARK_RX_WATERMARK_SHIFT)) & GENFSK_RX_WATERMARK_RX_WATERMARK_MASK)
AnnaBridge 171:3a7713b1edbc 2895 #define GENFSK_RX_WATERMARK_BYTE_COUNTER_MASK (0x1FFF0000U)
AnnaBridge 171:3a7713b1edbc 2896 #define GENFSK_RX_WATERMARK_BYTE_COUNTER_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2897 #define GENFSK_RX_WATERMARK_BYTE_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_RX_WATERMARK_BYTE_COUNTER_SHIFT)) & GENFSK_RX_WATERMARK_BYTE_COUNTER_MASK)
AnnaBridge 171:3a7713b1edbc 2898
AnnaBridge 171:3a7713b1edbc 2899 /*! @name DSM_CTRL - DSM CONTROL */
AnnaBridge 171:3a7713b1edbc 2900 #define GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2901 #define GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2902 #define GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN_SHIFT)) & GENFSK_DSM_CTRL_GENERIC_FSK_SLEEP_EN_MASK)
AnnaBridge 171:3a7713b1edbc 2903
AnnaBridge 171:3a7713b1edbc 2904 /*! @name PART_ID - PART ID */
AnnaBridge 171:3a7713b1edbc 2905 #define GENFSK_PART_ID_PART_ID_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2906 #define GENFSK_PART_ID_PART_ID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2907 #define GENFSK_PART_ID_PART_ID(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PART_ID_PART_ID_SHIFT)) & GENFSK_PART_ID_PART_ID_MASK)
AnnaBridge 171:3a7713b1edbc 2908
AnnaBridge 171:3a7713b1edbc 2909 /*! @name PACKET_CFG - PACKET CONFIGURATION */
AnnaBridge 171:3a7713b1edbc 2910 #define GENFSK_PACKET_CFG_LENGTH_SZ_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 2911 #define GENFSK_PACKET_CFG_LENGTH_SZ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2912 #define GENFSK_PACKET_CFG_LENGTH_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_SZ_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 2913 #define GENFSK_PACKET_CFG_LENGTH_BIT_ORD_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2914 #define GENFSK_PACKET_CFG_LENGTH_BIT_ORD_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2915 #define GENFSK_PACKET_CFG_LENGTH_BIT_ORD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_BIT_ORD_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_BIT_ORD_MASK)
AnnaBridge 171:3a7713b1edbc 2916 #define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 2917 #define GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2918 #define GENFSK_PACKET_CFG_SYNC_ADDR_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_SYNC_ADDR_SZ_SHIFT)) & GENFSK_PACKET_CFG_SYNC_ADDR_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 2919 #define GENFSK_PACKET_CFG_LENGTH_ADJ_MASK (0x3F00U)
AnnaBridge 171:3a7713b1edbc 2920 #define GENFSK_PACKET_CFG_LENGTH_ADJ_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2921 #define GENFSK_PACKET_CFG_LENGTH_ADJ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_ADJ_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 2922 #define GENFSK_PACKET_CFG_LENGTH_FAIL_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2923 #define GENFSK_PACKET_CFG_LENGTH_FAIL_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2924 #define GENFSK_PACKET_CFG_LENGTH_FAIL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_LENGTH_FAIL_SHIFT)) & GENFSK_PACKET_CFG_LENGTH_FAIL_MASK)
AnnaBridge 171:3a7713b1edbc 2925 #define GENFSK_PACKET_CFG_H0_SZ_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 2926 #define GENFSK_PACKET_CFG_H0_SZ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2927 #define GENFSK_PACKET_CFG_H0_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H0_SZ_SHIFT)) & GENFSK_PACKET_CFG_H0_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 2928 #define GENFSK_PACKET_CFG_H0_FAIL_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 2929 #define GENFSK_PACKET_CFG_H0_FAIL_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 2930 #define GENFSK_PACKET_CFG_H0_FAIL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H0_FAIL_SHIFT)) & GENFSK_PACKET_CFG_H0_FAIL_MASK)
AnnaBridge 171:3a7713b1edbc 2931 #define GENFSK_PACKET_CFG_H1_SZ_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 2932 #define GENFSK_PACKET_CFG_H1_SZ_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2933 #define GENFSK_PACKET_CFG_H1_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H1_SZ_SHIFT)) & GENFSK_PACKET_CFG_H1_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 2934 #define GENFSK_PACKET_CFG_H1_FAIL_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2935 #define GENFSK_PACKET_CFG_H1_FAIL_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2936 #define GENFSK_PACKET_CFG_H1_FAIL(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PACKET_CFG_H1_FAIL_SHIFT)) & GENFSK_PACKET_CFG_H1_FAIL_MASK)
AnnaBridge 171:3a7713b1edbc 2937
AnnaBridge 171:3a7713b1edbc 2938 /*! @name H0_CFG - H0 CONFIGURATION */
AnnaBridge 171:3a7713b1edbc 2939 #define GENFSK_H0_CFG_H0_MATCH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 2940 #define GENFSK_H0_CFG_H0_MATCH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2941 #define GENFSK_H0_CFG_H0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_H0_CFG_H0_MATCH_SHIFT)) & GENFSK_H0_CFG_H0_MATCH_MASK)
AnnaBridge 171:3a7713b1edbc 2942 #define GENFSK_H0_CFG_H0_MASK_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 2943 #define GENFSK_H0_CFG_H0_MASK_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2944 #define GENFSK_H0_CFG_H0_MASK(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_H0_CFG_H0_MASK_SHIFT)) & GENFSK_H0_CFG_H0_MASK_MASK)
AnnaBridge 171:3a7713b1edbc 2945
AnnaBridge 171:3a7713b1edbc 2946 /*! @name H1_CFG - H1 CONFIGURATION */
AnnaBridge 171:3a7713b1edbc 2947 #define GENFSK_H1_CFG_H1_MATCH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 2948 #define GENFSK_H1_CFG_H1_MATCH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2949 #define GENFSK_H1_CFG_H1_MATCH(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MATCH_SHIFT)) & GENFSK_H1_CFG_H1_MATCH_MASK)
AnnaBridge 171:3a7713b1edbc 2950 #define GENFSK_H1_CFG_H1_MASK_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 2951 #define GENFSK_H1_CFG_H1_MASK_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2952 #define GENFSK_H1_CFG_H1_MASK(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_H1_CFG_H1_MASK_SHIFT)) & GENFSK_H1_CFG_H1_MASK_MASK)
AnnaBridge 171:3a7713b1edbc 2953
AnnaBridge 171:3a7713b1edbc 2954 /*! @name CRC_CFG - CRC CONFIGURATION */
AnnaBridge 171:3a7713b1edbc 2955 #define GENFSK_CRC_CFG_CRC_SZ_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2956 #define GENFSK_CRC_CFG_CRC_SZ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2957 #define GENFSK_CRC_CFG_CRC_SZ(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_SZ_SHIFT)) & GENFSK_CRC_CFG_CRC_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 2958 #define GENFSK_CRC_CFG_CRC_START_BYTE_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 2959 #define GENFSK_CRC_CFG_CRC_START_BYTE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2960 #define GENFSK_CRC_CFG_CRC_START_BYTE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_START_BYTE_SHIFT)) & GENFSK_CRC_CFG_CRC_START_BYTE_MASK)
AnnaBridge 171:3a7713b1edbc 2961 #define GENFSK_CRC_CFG_CRC_REF_IN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2962 #define GENFSK_CRC_CFG_CRC_REF_IN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2963 #define GENFSK_CRC_CFG_CRC_REF_IN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_REF_IN_SHIFT)) & GENFSK_CRC_CFG_CRC_REF_IN_MASK)
AnnaBridge 171:3a7713b1edbc 2964 #define GENFSK_CRC_CFG_CRC_REF_OUT_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 2965 #define GENFSK_CRC_CFG_CRC_REF_OUT_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2966 #define GENFSK_CRC_CFG_CRC_REF_OUT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_REF_OUT_SHIFT)) & GENFSK_CRC_CFG_CRC_REF_OUT_MASK)
AnnaBridge 171:3a7713b1edbc 2967 #define GENFSK_CRC_CFG_CRC_BYTE_ORD_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 2968 #define GENFSK_CRC_CFG_CRC_BYTE_ORD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 2969 #define GENFSK_CRC_CFG_CRC_BYTE_ORD(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_CFG_CRC_BYTE_ORD_SHIFT)) & GENFSK_CRC_CFG_CRC_BYTE_ORD_MASK)
AnnaBridge 171:3a7713b1edbc 2970
AnnaBridge 171:3a7713b1edbc 2971 /*! @name CRC_INIT - CRC INITIALIZATION */
AnnaBridge 171:3a7713b1edbc 2972 #define GENFSK_CRC_INIT_CRC_SEED_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2973 #define GENFSK_CRC_INIT_CRC_SEED_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2974 #define GENFSK_CRC_INIT_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_INIT_CRC_SEED_SHIFT)) & GENFSK_CRC_INIT_CRC_SEED_MASK)
AnnaBridge 171:3a7713b1edbc 2975
AnnaBridge 171:3a7713b1edbc 2976 /*! @name CRC_POLY - CRC POLYNOMIAL */
AnnaBridge 171:3a7713b1edbc 2977 #define GENFSK_CRC_POLY_CRC_POLY_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2978 #define GENFSK_CRC_POLY_CRC_POLY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2979 #define GENFSK_CRC_POLY_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_POLY_CRC_POLY_SHIFT)) & GENFSK_CRC_POLY_CRC_POLY_MASK)
AnnaBridge 171:3a7713b1edbc 2980
AnnaBridge 171:3a7713b1edbc 2981 /*! @name CRC_XOR_OUT - CRC XOR OUT */
AnnaBridge 171:3a7713b1edbc 2982 #define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2983 #define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2984 #define GENFSK_CRC_XOR_OUT_CRC_XOR_OUT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_SHIFT)) & GENFSK_CRC_XOR_OUT_CRC_XOR_OUT_MASK)
AnnaBridge 171:3a7713b1edbc 2985
AnnaBridge 171:3a7713b1edbc 2986 /*! @name WHITEN_CFG - WHITENER CONFIGURATION */
AnnaBridge 171:3a7713b1edbc 2987 #define GENFSK_WHITEN_CFG_WHITEN_START_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 2988 #define GENFSK_WHITEN_CFG_WHITEN_START_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2989 #define GENFSK_WHITEN_CFG_WHITEN_START(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_START_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_START_MASK)
AnnaBridge 171:3a7713b1edbc 2990 #define GENFSK_WHITEN_CFG_WHITEN_END_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2991 #define GENFSK_WHITEN_CFG_WHITEN_END_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2992 #define GENFSK_WHITEN_CFG_WHITEN_END(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_END_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_END_MASK)
AnnaBridge 171:3a7713b1edbc 2993 #define GENFSK_WHITEN_CFG_WHITEN_B4_CRC_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2994 #define GENFSK_WHITEN_CFG_WHITEN_B4_CRC_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2995 #define GENFSK_WHITEN_CFG_WHITEN_B4_CRC(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_B4_CRC_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_B4_CRC_MASK)
AnnaBridge 171:3a7713b1edbc 2996 #define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2997 #define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2998 #define GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_POLY_TYPE_MASK)
AnnaBridge 171:3a7713b1edbc 2999 #define GENFSK_WHITEN_CFG_WHITEN_REF_IN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3000 #define GENFSK_WHITEN_CFG_WHITEN_REF_IN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3001 #define GENFSK_WHITEN_CFG_WHITEN_REF_IN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_REF_IN_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_REF_IN_MASK)
AnnaBridge 171:3a7713b1edbc 3002 #define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3003 #define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3004 #define GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_PAYLOAD_REINIT_MASK)
AnnaBridge 171:3a7713b1edbc 3005 #define GENFSK_WHITEN_CFG_WHITEN_SIZE_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 3006 #define GENFSK_WHITEN_CFG_WHITEN_SIZE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3007 #define GENFSK_WHITEN_CFG_WHITEN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_SIZE_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_SIZE_MASK)
AnnaBridge 171:3a7713b1edbc 3008 #define GENFSK_WHITEN_CFG_MANCHESTER_EN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 3009 #define GENFSK_WHITEN_CFG_MANCHESTER_EN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 3010 #define GENFSK_WHITEN_CFG_MANCHESTER_EN(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_EN_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_EN_MASK)
AnnaBridge 171:3a7713b1edbc 3011 #define GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 3012 #define GENFSK_WHITEN_CFG_MANCHESTER_INV_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 3013 #define GENFSK_WHITEN_CFG_MANCHESTER_INV(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_INV_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_INV_MASK)
AnnaBridge 171:3a7713b1edbc 3014 #define GENFSK_WHITEN_CFG_MANCHESTER_START_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 3015 #define GENFSK_WHITEN_CFG_MANCHESTER_START_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 3016 #define GENFSK_WHITEN_CFG_MANCHESTER_START(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_MANCHESTER_START_SHIFT)) & GENFSK_WHITEN_CFG_MANCHESTER_START_MASK)
AnnaBridge 171:3a7713b1edbc 3017 #define GENFSK_WHITEN_CFG_WHITEN_INIT_MASK (0x1FF0000U)
AnnaBridge 171:3a7713b1edbc 3018 #define GENFSK_WHITEN_CFG_WHITEN_INIT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3019 #define GENFSK_WHITEN_CFG_WHITEN_INIT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_CFG_WHITEN_INIT_SHIFT)) & GENFSK_WHITEN_CFG_WHITEN_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 3020
AnnaBridge 171:3a7713b1edbc 3021 /*! @name WHITEN_POLY - WHITENER POLYNOMIAL */
AnnaBridge 171:3a7713b1edbc 3022 #define GENFSK_WHITEN_POLY_WHITEN_POLY_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 3023 #define GENFSK_WHITEN_POLY_WHITEN_POLY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3024 #define GENFSK_WHITEN_POLY_WHITEN_POLY(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_POLY_WHITEN_POLY_SHIFT)) & GENFSK_WHITEN_POLY_WHITEN_POLY_MASK)
AnnaBridge 171:3a7713b1edbc 3025
AnnaBridge 171:3a7713b1edbc 3026 /*! @name WHITEN_SZ_THR - WHITENER SIZE THRESHOLD */
AnnaBridge 171:3a7713b1edbc 3027 #define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 3028 #define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3029 #define GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_SHIFT)) & GENFSK_WHITEN_SZ_THR_WHITEN_SZ_THR_MASK)
AnnaBridge 171:3a7713b1edbc 3030 #define GENFSK_WHITEN_SZ_THR_LENGTH_MAX_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 3031 #define GENFSK_WHITEN_SZ_THR_LENGTH_MAX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3032 #define GENFSK_WHITEN_SZ_THR_LENGTH_MAX(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_LENGTH_MAX_SHIFT)) & GENFSK_WHITEN_SZ_THR_LENGTH_MAX_MASK)
AnnaBridge 171:3a7713b1edbc 3033 #define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 3034 #define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 3035 #define GENFSK_WHITEN_SZ_THR_REC_BAD_PKT(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_SHIFT)) & GENFSK_WHITEN_SZ_THR_REC_BAD_PKT_MASK)
AnnaBridge 171:3a7713b1edbc 3036
AnnaBridge 171:3a7713b1edbc 3037 /*! @name BITRATE - BIT RATE */
AnnaBridge 171:3a7713b1edbc 3038 #define GENFSK_BITRATE_BITRATE_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 3039 #define GENFSK_BITRATE_BITRATE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3040 #define GENFSK_BITRATE_BITRATE(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_BITRATE_BITRATE_SHIFT)) & GENFSK_BITRATE_BITRATE_MASK)
AnnaBridge 171:3a7713b1edbc 3041
AnnaBridge 171:3a7713b1edbc 3042 /*! @name PB_PARTITION - PACKET BUFFER PARTITION POINT */
AnnaBridge 171:3a7713b1edbc 3043 #define GENFSK_PB_PARTITION_PB_PARTITION_MASK (0x7FFU)
AnnaBridge 171:3a7713b1edbc 3044 #define GENFSK_PB_PARTITION_PB_PARTITION_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3045 #define GENFSK_PB_PARTITION_PB_PARTITION(x) (((uint32_t)(((uint32_t)(x)) << GENFSK_PB_PARTITION_PB_PARTITION_SHIFT)) & GENFSK_PB_PARTITION_PB_PARTITION_MASK)
AnnaBridge 171:3a7713b1edbc 3046
AnnaBridge 171:3a7713b1edbc 3047
AnnaBridge 171:3a7713b1edbc 3048 /*!
AnnaBridge 171:3a7713b1edbc 3049 * @}
AnnaBridge 171:3a7713b1edbc 3050 */ /* end of group GENFSK_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3051
AnnaBridge 171:3a7713b1edbc 3052
AnnaBridge 171:3a7713b1edbc 3053 /* GENFSK - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3054 /** Peripheral GENFSK base address */
AnnaBridge 171:3a7713b1edbc 3055 #define GENFSK_BASE (0x4005F000u)
AnnaBridge 171:3a7713b1edbc 3056 /** Peripheral GENFSK base pointer */
AnnaBridge 171:3a7713b1edbc 3057 #define GENFSK ((GENFSK_Type *)GENFSK_BASE)
AnnaBridge 171:3a7713b1edbc 3058 /** Array initializer of GENFSK peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3059 #define GENFSK_BASE_ADDRS { GENFSK_BASE }
AnnaBridge 171:3a7713b1edbc 3060 /** Array initializer of GENFSK peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3061 #define GENFSK_BASE_PTRS { GENFSK }
AnnaBridge 171:3a7713b1edbc 3062
AnnaBridge 171:3a7713b1edbc 3063 /*!
AnnaBridge 171:3a7713b1edbc 3064 * @}
AnnaBridge 171:3a7713b1edbc 3065 */ /* end of group GENFSK_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3066
AnnaBridge 171:3a7713b1edbc 3067
AnnaBridge 171:3a7713b1edbc 3068 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3069 -- GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3070 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3071
AnnaBridge 171:3a7713b1edbc 3072 /*!
AnnaBridge 171:3a7713b1edbc 3073 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3074 * @{
AnnaBridge 171:3a7713b1edbc 3075 */
AnnaBridge 171:3a7713b1edbc 3076
AnnaBridge 171:3a7713b1edbc 3077 /** GPIO - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3078 typedef struct {
AnnaBridge 171:3a7713b1edbc 3079 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3080 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3081 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3082 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3083 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 3084 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 3085 } GPIO_Type;
AnnaBridge 171:3a7713b1edbc 3086
AnnaBridge 171:3a7713b1edbc 3087 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3088 -- GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 3089 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3090
AnnaBridge 171:3a7713b1edbc 3091 /*!
AnnaBridge 171:3a7713b1edbc 3092 * @addtogroup GPIO_Register_Masks GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 3093 * @{
AnnaBridge 171:3a7713b1edbc 3094 */
AnnaBridge 171:3a7713b1edbc 3095
AnnaBridge 171:3a7713b1edbc 3096 /*! @name PDOR - Port Data Output Register */
AnnaBridge 171:3a7713b1edbc 3097 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3098 #define GPIO_PDOR_PDO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3099 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
AnnaBridge 171:3a7713b1edbc 3100
AnnaBridge 171:3a7713b1edbc 3101 /*! @name PSOR - Port Set Output Register */
AnnaBridge 171:3a7713b1edbc 3102 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3103 #define GPIO_PSOR_PTSO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3104 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
AnnaBridge 171:3a7713b1edbc 3105
AnnaBridge 171:3a7713b1edbc 3106 /*! @name PCOR - Port Clear Output Register */
AnnaBridge 171:3a7713b1edbc 3107 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3108 #define GPIO_PCOR_PTCO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3109 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
AnnaBridge 171:3a7713b1edbc 3110
AnnaBridge 171:3a7713b1edbc 3111 /*! @name PTOR - Port Toggle Output Register */
AnnaBridge 171:3a7713b1edbc 3112 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3113 #define GPIO_PTOR_PTTO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3114 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
AnnaBridge 171:3a7713b1edbc 3115
AnnaBridge 171:3a7713b1edbc 3116 /*! @name PDIR - Port Data Input Register */
AnnaBridge 171:3a7713b1edbc 3117 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3118 #define GPIO_PDIR_PDI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3119 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
AnnaBridge 171:3a7713b1edbc 3120
AnnaBridge 171:3a7713b1edbc 3121 /*! @name PDDR - Port Data Direction Register */
AnnaBridge 171:3a7713b1edbc 3122 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3123 #define GPIO_PDDR_PDD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3124 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
AnnaBridge 171:3a7713b1edbc 3125
AnnaBridge 171:3a7713b1edbc 3126
AnnaBridge 171:3a7713b1edbc 3127 /*!
AnnaBridge 171:3a7713b1edbc 3128 * @}
AnnaBridge 171:3a7713b1edbc 3129 */ /* end of group GPIO_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3130
AnnaBridge 171:3a7713b1edbc 3131
AnnaBridge 171:3a7713b1edbc 3132 /* GPIO - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3133 /** Peripheral GPIOA base address */
AnnaBridge 171:3a7713b1edbc 3134 #define GPIOA_BASE (0x400FF000u)
AnnaBridge 171:3a7713b1edbc 3135 /** Peripheral GPIOA base pointer */
AnnaBridge 171:3a7713b1edbc 3136 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 3137 /** Peripheral GPIOB base address */
AnnaBridge 171:3a7713b1edbc 3138 #define GPIOB_BASE (0x400FF040u)
AnnaBridge 171:3a7713b1edbc 3139 /** Peripheral GPIOB base pointer */
AnnaBridge 171:3a7713b1edbc 3140 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 3141 /** Peripheral GPIOC base address */
AnnaBridge 171:3a7713b1edbc 3142 #define GPIOC_BASE (0x400FF080u)
AnnaBridge 171:3a7713b1edbc 3143 /** Peripheral GPIOC base pointer */
AnnaBridge 171:3a7713b1edbc 3144 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 3145 /** Array initializer of GPIO peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3146 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE }
AnnaBridge 171:3a7713b1edbc 3147 /** Array initializer of GPIO peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3148 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC }
AnnaBridge 171:3a7713b1edbc 3149
AnnaBridge 171:3a7713b1edbc 3150 /*!
AnnaBridge 171:3a7713b1edbc 3151 * @}
AnnaBridge 171:3a7713b1edbc 3152 */ /* end of group GPIO_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3153
AnnaBridge 171:3a7713b1edbc 3154
AnnaBridge 171:3a7713b1edbc 3155 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3156 -- I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3157 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3158
AnnaBridge 171:3a7713b1edbc 3159 /*!
AnnaBridge 171:3a7713b1edbc 3160 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3161 * @{
AnnaBridge 171:3a7713b1edbc 3162 */
AnnaBridge 171:3a7713b1edbc 3163
AnnaBridge 171:3a7713b1edbc 3164 /** I2C - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3165 typedef struct {
AnnaBridge 171:3a7713b1edbc 3166 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3167 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3168 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3169 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3170 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3171 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3172 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3173 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3174 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3175 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 3176 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 3177 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 3178 __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3179 } I2C_Type;
AnnaBridge 171:3a7713b1edbc 3180
AnnaBridge 171:3a7713b1edbc 3181 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3182 -- I2C Register Masks
AnnaBridge 171:3a7713b1edbc 3183 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3184
AnnaBridge 171:3a7713b1edbc 3185 /*!
AnnaBridge 171:3a7713b1edbc 3186 * @addtogroup I2C_Register_Masks I2C Register Masks
AnnaBridge 171:3a7713b1edbc 3187 * @{
AnnaBridge 171:3a7713b1edbc 3188 */
AnnaBridge 171:3a7713b1edbc 3189
AnnaBridge 171:3a7713b1edbc 3190 /*! @name A1 - I2C Address Register 1 */
AnnaBridge 171:3a7713b1edbc 3191 #define I2C_A1_AD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 3192 #define I2C_A1_AD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3193 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
AnnaBridge 171:3a7713b1edbc 3194
AnnaBridge 171:3a7713b1edbc 3195 /*! @name F - I2C Frequency Divider register */
AnnaBridge 171:3a7713b1edbc 3196 #define I2C_F_ICR_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 3197 #define I2C_F_ICR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3198 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
AnnaBridge 171:3a7713b1edbc 3199 #define I2C_F_MULT_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 3200 #define I2C_F_MULT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3201 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
AnnaBridge 171:3a7713b1edbc 3202
AnnaBridge 171:3a7713b1edbc 3203 /*! @name C1 - I2C Control Register 1 */
AnnaBridge 171:3a7713b1edbc 3204 #define I2C_C1_DMAEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3205 #define I2C_C1_DMAEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3206 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 3207 #define I2C_C1_WUEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3208 #define I2C_C1_WUEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3209 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
AnnaBridge 171:3a7713b1edbc 3210 #define I2C_C1_RSTA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3211 #define I2C_C1_RSTA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3212 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
AnnaBridge 171:3a7713b1edbc 3213 #define I2C_C1_TXAK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3214 #define I2C_C1_TXAK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3215 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
AnnaBridge 171:3a7713b1edbc 3216 #define I2C_C1_TX_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3217 #define I2C_C1_TX_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3218 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
AnnaBridge 171:3a7713b1edbc 3219 #define I2C_C1_MST_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3220 #define I2C_C1_MST_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3221 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
AnnaBridge 171:3a7713b1edbc 3222 #define I2C_C1_IICIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3223 #define I2C_C1_IICIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3224 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
AnnaBridge 171:3a7713b1edbc 3225 #define I2C_C1_IICEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3226 #define I2C_C1_IICEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3227 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
AnnaBridge 171:3a7713b1edbc 3228
AnnaBridge 171:3a7713b1edbc 3229 /*! @name S - I2C Status register */
AnnaBridge 171:3a7713b1edbc 3230 #define I2C_S_RXAK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3231 #define I2C_S_RXAK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3232 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
AnnaBridge 171:3a7713b1edbc 3233 #define I2C_S_IICIF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3234 #define I2C_S_IICIF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3235 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
AnnaBridge 171:3a7713b1edbc 3236 #define I2C_S_SRW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3237 #define I2C_S_SRW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3238 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
AnnaBridge 171:3a7713b1edbc 3239 #define I2C_S_RAM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3240 #define I2C_S_RAM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3241 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
AnnaBridge 171:3a7713b1edbc 3242 #define I2C_S_ARBL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3243 #define I2C_S_ARBL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3244 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
AnnaBridge 171:3a7713b1edbc 3245 #define I2C_S_BUSY_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3246 #define I2C_S_BUSY_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3247 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
AnnaBridge 171:3a7713b1edbc 3248 #define I2C_S_IAAS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3249 #define I2C_S_IAAS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3250 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
AnnaBridge 171:3a7713b1edbc 3251 #define I2C_S_TCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3252 #define I2C_S_TCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3253 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 3254
AnnaBridge 171:3a7713b1edbc 3255 /*! @name D - I2C Data I/O register */
AnnaBridge 171:3a7713b1edbc 3256 #define I2C_D_DATA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3257 #define I2C_D_DATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3258 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
AnnaBridge 171:3a7713b1edbc 3259
AnnaBridge 171:3a7713b1edbc 3260 /*! @name C2 - I2C Control Register 2 */
AnnaBridge 171:3a7713b1edbc 3261 #define I2C_C2_AD_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 3262 #define I2C_C2_AD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3263 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
AnnaBridge 171:3a7713b1edbc 3264 #define I2C_C2_RMEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3265 #define I2C_C2_RMEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3266 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
AnnaBridge 171:3a7713b1edbc 3267 #define I2C_C2_SBRC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3268 #define I2C_C2_SBRC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3269 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
AnnaBridge 171:3a7713b1edbc 3270 #define I2C_C2_HDRS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3271 #define I2C_C2_HDRS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3272 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
AnnaBridge 171:3a7713b1edbc 3273 #define I2C_C2_ADEXT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3274 #define I2C_C2_ADEXT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3275 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
AnnaBridge 171:3a7713b1edbc 3276 #define I2C_C2_GCAEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3277 #define I2C_C2_GCAEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3278 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
AnnaBridge 171:3a7713b1edbc 3279
AnnaBridge 171:3a7713b1edbc 3280 /*! @name FLT - I2C Programmable Input Glitch Filter Register */
AnnaBridge 171:3a7713b1edbc 3281 #define I2C_FLT_FLT_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3282 #define I2C_FLT_FLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3283 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
AnnaBridge 171:3a7713b1edbc 3284 #define I2C_FLT_STARTF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3285 #define I2C_FLT_STARTF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3286 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
AnnaBridge 171:3a7713b1edbc 3287 #define I2C_FLT_SSIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3288 #define I2C_FLT_SSIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3289 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
AnnaBridge 171:3a7713b1edbc 3290 #define I2C_FLT_STOPF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3291 #define I2C_FLT_STOPF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3292 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
AnnaBridge 171:3a7713b1edbc 3293 #define I2C_FLT_SHEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3294 #define I2C_FLT_SHEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3295 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
AnnaBridge 171:3a7713b1edbc 3296
AnnaBridge 171:3a7713b1edbc 3297 /*! @name RA - I2C Range Address register */
AnnaBridge 171:3a7713b1edbc 3298 #define I2C_RA_RAD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 3299 #define I2C_RA_RAD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3300 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
AnnaBridge 171:3a7713b1edbc 3301
AnnaBridge 171:3a7713b1edbc 3302 /*! @name SMB - I2C SMBus Control and Status register */
AnnaBridge 171:3a7713b1edbc 3303 #define I2C_SMB_SHTF2IE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3304 #define I2C_SMB_SHTF2IE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3305 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
AnnaBridge 171:3a7713b1edbc 3306 #define I2C_SMB_SHTF2_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3307 #define I2C_SMB_SHTF2_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3308 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
AnnaBridge 171:3a7713b1edbc 3309 #define I2C_SMB_SHTF1_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3310 #define I2C_SMB_SHTF1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3311 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
AnnaBridge 171:3a7713b1edbc 3312 #define I2C_SMB_SLTF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3313 #define I2C_SMB_SLTF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3314 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
AnnaBridge 171:3a7713b1edbc 3315 #define I2C_SMB_TCKSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3316 #define I2C_SMB_TCKSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3317 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3318 #define I2C_SMB_SIICAEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3319 #define I2C_SMB_SIICAEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3320 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
AnnaBridge 171:3a7713b1edbc 3321 #define I2C_SMB_ALERTEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3322 #define I2C_SMB_ALERTEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3323 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
AnnaBridge 171:3a7713b1edbc 3324 #define I2C_SMB_FACK_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3325 #define I2C_SMB_FACK_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3326 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
AnnaBridge 171:3a7713b1edbc 3327
AnnaBridge 171:3a7713b1edbc 3328 /*! @name A2 - I2C Address Register 2 */
AnnaBridge 171:3a7713b1edbc 3329 #define I2C_A2_SAD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 3330 #define I2C_A2_SAD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3331 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
AnnaBridge 171:3a7713b1edbc 3332
AnnaBridge 171:3a7713b1edbc 3333 /*! @name SLTH - I2C SCL Low Timeout Register High */
AnnaBridge 171:3a7713b1edbc 3334 #define I2C_SLTH_SSLT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3335 #define I2C_SLTH_SSLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3336 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 3337
AnnaBridge 171:3a7713b1edbc 3338 /*! @name SLTL - I2C SCL Low Timeout Register Low */
AnnaBridge 171:3a7713b1edbc 3339 #define I2C_SLTL_SSLT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3340 #define I2C_SLTL_SSLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3341 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 3342
AnnaBridge 171:3a7713b1edbc 3343 /*! @name S2 - I2C Status register 2 */
AnnaBridge 171:3a7713b1edbc 3344 #define I2C_S2_EMPTY_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3345 #define I2C_S2_EMPTY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3346 #define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK)
AnnaBridge 171:3a7713b1edbc 3347 #define I2C_S2_ERROR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3348 #define I2C_S2_ERROR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3349 #define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK)
AnnaBridge 171:3a7713b1edbc 3350 #define I2C_S2_DFEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3351 #define I2C_S2_DFEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3352 #define I2C_S2_DFEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_DFEN_SHIFT)) & I2C_S2_DFEN_MASK)
AnnaBridge 171:3a7713b1edbc 3353
AnnaBridge 171:3a7713b1edbc 3354
AnnaBridge 171:3a7713b1edbc 3355 /*!
AnnaBridge 171:3a7713b1edbc 3356 * @}
AnnaBridge 171:3a7713b1edbc 3357 */ /* end of group I2C_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3358
AnnaBridge 171:3a7713b1edbc 3359
AnnaBridge 171:3a7713b1edbc 3360 /* I2C - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3361 /** Peripheral I2C0 base address */
AnnaBridge 171:3a7713b1edbc 3362 #define I2C0_BASE (0x40066000u)
AnnaBridge 171:3a7713b1edbc 3363 /** Peripheral I2C0 base pointer */
AnnaBridge 171:3a7713b1edbc 3364 #define I2C0 ((I2C_Type *)I2C0_BASE)
AnnaBridge 171:3a7713b1edbc 3365 /** Peripheral I2C1 base address */
AnnaBridge 171:3a7713b1edbc 3366 #define I2C1_BASE (0x40067000u)
AnnaBridge 171:3a7713b1edbc 3367 /** Peripheral I2C1 base pointer */
AnnaBridge 171:3a7713b1edbc 3368 #define I2C1 ((I2C_Type *)I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 3369 /** Array initializer of I2C peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3370 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
AnnaBridge 171:3a7713b1edbc 3371 /** Array initializer of I2C peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3372 #define I2C_BASE_PTRS { I2C0, I2C1 }
AnnaBridge 171:3a7713b1edbc 3373 /** Interrupt vectors for the I2C peripheral type */
AnnaBridge 171:3a7713b1edbc 3374 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
AnnaBridge 171:3a7713b1edbc 3375
AnnaBridge 171:3a7713b1edbc 3376 /*!
AnnaBridge 171:3a7713b1edbc 3377 * @}
AnnaBridge 171:3a7713b1edbc 3378 */ /* end of group I2C_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3379
AnnaBridge 171:3a7713b1edbc 3380
AnnaBridge 171:3a7713b1edbc 3381 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3382 -- LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3383 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3384
AnnaBridge 171:3a7713b1edbc 3385 /*!
AnnaBridge 171:3a7713b1edbc 3386 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3387 * @{
AnnaBridge 171:3a7713b1edbc 3388 */
AnnaBridge 171:3a7713b1edbc 3389
AnnaBridge 171:3a7713b1edbc 3390 /** LLWU - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3391 typedef struct {
AnnaBridge 171:3a7713b1edbc 3392 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3393 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3394 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3395 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3396 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3397 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3398 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3399 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3400 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3401 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 3402 } LLWU_Type;
AnnaBridge 171:3a7713b1edbc 3403
AnnaBridge 171:3a7713b1edbc 3404 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3405 -- LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 3406 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3407
AnnaBridge 171:3a7713b1edbc 3408 /*!
AnnaBridge 171:3a7713b1edbc 3409 * @addtogroup LLWU_Register_Masks LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 3410 * @{
AnnaBridge 171:3a7713b1edbc 3411 */
AnnaBridge 171:3a7713b1edbc 3412
AnnaBridge 171:3a7713b1edbc 3413 /*! @name PE1 - LLWU Pin Enable 1 register */
AnnaBridge 171:3a7713b1edbc 3414 #define LLWU_PE1_WUPE0_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 3415 #define LLWU_PE1_WUPE0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3416 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
AnnaBridge 171:3a7713b1edbc 3417 #define LLWU_PE1_WUPE1_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 3418 #define LLWU_PE1_WUPE1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3419 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
AnnaBridge 171:3a7713b1edbc 3420 #define LLWU_PE1_WUPE2_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 3421 #define LLWU_PE1_WUPE2_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3422 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
AnnaBridge 171:3a7713b1edbc 3423 #define LLWU_PE1_WUPE3_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 3424 #define LLWU_PE1_WUPE3_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3425 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
AnnaBridge 171:3a7713b1edbc 3426
AnnaBridge 171:3a7713b1edbc 3427 /*! @name PE2 - LLWU Pin Enable 2 register */
AnnaBridge 171:3a7713b1edbc 3428 #define LLWU_PE2_WUPE4_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 3429 #define LLWU_PE2_WUPE4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3430 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
AnnaBridge 171:3a7713b1edbc 3431 #define LLWU_PE2_WUPE5_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 3432 #define LLWU_PE2_WUPE5_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3433 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
AnnaBridge 171:3a7713b1edbc 3434 #define LLWU_PE2_WUPE6_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 3435 #define LLWU_PE2_WUPE6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3436 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
AnnaBridge 171:3a7713b1edbc 3437 #define LLWU_PE2_WUPE7_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 3438 #define LLWU_PE2_WUPE7_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3439 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
AnnaBridge 171:3a7713b1edbc 3440
AnnaBridge 171:3a7713b1edbc 3441 /*! @name PE3 - LLWU Pin Enable 3 register */
AnnaBridge 171:3a7713b1edbc 3442 #define LLWU_PE3_WUPE8_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 3443 #define LLWU_PE3_WUPE8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3444 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
AnnaBridge 171:3a7713b1edbc 3445 #define LLWU_PE3_WUPE9_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 3446 #define LLWU_PE3_WUPE9_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3447 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
AnnaBridge 171:3a7713b1edbc 3448 #define LLWU_PE3_WUPE10_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 3449 #define LLWU_PE3_WUPE10_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3450 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
AnnaBridge 171:3a7713b1edbc 3451 #define LLWU_PE3_WUPE11_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 3452 #define LLWU_PE3_WUPE11_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3453 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
AnnaBridge 171:3a7713b1edbc 3454
AnnaBridge 171:3a7713b1edbc 3455 /*! @name PE4 - LLWU Pin Enable 4 register */
AnnaBridge 171:3a7713b1edbc 3456 #define LLWU_PE4_WUPE12_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 3457 #define LLWU_PE4_WUPE12_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3458 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
AnnaBridge 171:3a7713b1edbc 3459 #define LLWU_PE4_WUPE13_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 3460 #define LLWU_PE4_WUPE13_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3461 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
AnnaBridge 171:3a7713b1edbc 3462 #define LLWU_PE4_WUPE14_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 3463 #define LLWU_PE4_WUPE14_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3464 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
AnnaBridge 171:3a7713b1edbc 3465 #define LLWU_PE4_WUPE15_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 3466 #define LLWU_PE4_WUPE15_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3467 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
AnnaBridge 171:3a7713b1edbc 3468
AnnaBridge 171:3a7713b1edbc 3469 /*! @name ME - LLWU Module Enable register */
AnnaBridge 171:3a7713b1edbc 3470 #define LLWU_ME_WUME0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3471 #define LLWU_ME_WUME0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3472 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
AnnaBridge 171:3a7713b1edbc 3473 #define LLWU_ME_WUME1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3474 #define LLWU_ME_WUME1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3475 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
AnnaBridge 171:3a7713b1edbc 3476 #define LLWU_ME_WUME2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3477 #define LLWU_ME_WUME2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3478 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
AnnaBridge 171:3a7713b1edbc 3479 #define LLWU_ME_WUME3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3480 #define LLWU_ME_WUME3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3481 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
AnnaBridge 171:3a7713b1edbc 3482 #define LLWU_ME_WUME4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3483 #define LLWU_ME_WUME4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3484 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
AnnaBridge 171:3a7713b1edbc 3485 #define LLWU_ME_WUME5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3486 #define LLWU_ME_WUME5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3487 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
AnnaBridge 171:3a7713b1edbc 3488 #define LLWU_ME_WUME6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3489 #define LLWU_ME_WUME6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3490 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
AnnaBridge 171:3a7713b1edbc 3491 #define LLWU_ME_WUME7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3492 #define LLWU_ME_WUME7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3493 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
AnnaBridge 171:3a7713b1edbc 3494
AnnaBridge 171:3a7713b1edbc 3495 /*! @name F1 - LLWU Flag 1 register */
AnnaBridge 171:3a7713b1edbc 3496 #define LLWU_F1_WUF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3497 #define LLWU_F1_WUF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3498 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
AnnaBridge 171:3a7713b1edbc 3499 #define LLWU_F1_WUF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3500 #define LLWU_F1_WUF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3501 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
AnnaBridge 171:3a7713b1edbc 3502 #define LLWU_F1_WUF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3503 #define LLWU_F1_WUF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3504 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
AnnaBridge 171:3a7713b1edbc 3505 #define LLWU_F1_WUF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3506 #define LLWU_F1_WUF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3507 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
AnnaBridge 171:3a7713b1edbc 3508 #define LLWU_F1_WUF4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3509 #define LLWU_F1_WUF4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3510 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
AnnaBridge 171:3a7713b1edbc 3511 #define LLWU_F1_WUF5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3512 #define LLWU_F1_WUF5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3513 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
AnnaBridge 171:3a7713b1edbc 3514 #define LLWU_F1_WUF6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3515 #define LLWU_F1_WUF6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3516 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
AnnaBridge 171:3a7713b1edbc 3517 #define LLWU_F1_WUF7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3518 #define LLWU_F1_WUF7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3519 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
AnnaBridge 171:3a7713b1edbc 3520
AnnaBridge 171:3a7713b1edbc 3521 /*! @name F2 - LLWU Flag 2 register */
AnnaBridge 171:3a7713b1edbc 3522 #define LLWU_F2_WUF8_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3523 #define LLWU_F2_WUF8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3524 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
AnnaBridge 171:3a7713b1edbc 3525 #define LLWU_F2_WUF9_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3526 #define LLWU_F2_WUF9_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3527 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
AnnaBridge 171:3a7713b1edbc 3528 #define LLWU_F2_WUF10_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3529 #define LLWU_F2_WUF10_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3530 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
AnnaBridge 171:3a7713b1edbc 3531 #define LLWU_F2_WUF11_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3532 #define LLWU_F2_WUF11_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3533 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
AnnaBridge 171:3a7713b1edbc 3534 #define LLWU_F2_WUF12_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3535 #define LLWU_F2_WUF12_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3536 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
AnnaBridge 171:3a7713b1edbc 3537 #define LLWU_F2_WUF13_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3538 #define LLWU_F2_WUF13_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3539 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
AnnaBridge 171:3a7713b1edbc 3540 #define LLWU_F2_WUF14_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3541 #define LLWU_F2_WUF14_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3542 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
AnnaBridge 171:3a7713b1edbc 3543 #define LLWU_F2_WUF15_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3544 #define LLWU_F2_WUF15_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3545 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
AnnaBridge 171:3a7713b1edbc 3546
AnnaBridge 171:3a7713b1edbc 3547 /*! @name F3 - LLWU Flag 3 register */
AnnaBridge 171:3a7713b1edbc 3548 #define LLWU_F3_MWUF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3549 #define LLWU_F3_MWUF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3550 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
AnnaBridge 171:3a7713b1edbc 3551 #define LLWU_F3_MWUF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3552 #define LLWU_F3_MWUF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3553 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
AnnaBridge 171:3a7713b1edbc 3554 #define LLWU_F3_MWUF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3555 #define LLWU_F3_MWUF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3556 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
AnnaBridge 171:3a7713b1edbc 3557 #define LLWU_F3_MWUF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3558 #define LLWU_F3_MWUF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3559 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
AnnaBridge 171:3a7713b1edbc 3560 #define LLWU_F3_MWUF4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3561 #define LLWU_F3_MWUF4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3562 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
AnnaBridge 171:3a7713b1edbc 3563 #define LLWU_F3_MWUF5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3564 #define LLWU_F3_MWUF5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3565 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
AnnaBridge 171:3a7713b1edbc 3566 #define LLWU_F3_MWUF6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3567 #define LLWU_F3_MWUF6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3568 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
AnnaBridge 171:3a7713b1edbc 3569 #define LLWU_F3_MWUF7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3570 #define LLWU_F3_MWUF7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3571 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
AnnaBridge 171:3a7713b1edbc 3572
AnnaBridge 171:3a7713b1edbc 3573 /*! @name FILT1 - LLWU Pin Filter 1 register */
AnnaBridge 171:3a7713b1edbc 3574 #define LLWU_FILT1_FILTSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3575 #define LLWU_FILT1_FILTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3576 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3577 #define LLWU_FILT1_FILTE_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 3578 #define LLWU_FILT1_FILTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3579 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 3580 #define LLWU_FILT1_FILTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3581 #define LLWU_FILT1_FILTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3582 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
AnnaBridge 171:3a7713b1edbc 3583
AnnaBridge 171:3a7713b1edbc 3584 /*! @name FILT2 - LLWU Pin Filter 2 register */
AnnaBridge 171:3a7713b1edbc 3585 #define LLWU_FILT2_FILTSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3586 #define LLWU_FILT2_FILTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3587 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3588 #define LLWU_FILT2_FILTE_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 3589 #define LLWU_FILT2_FILTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3590 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 3591 #define LLWU_FILT2_FILTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3592 #define LLWU_FILT2_FILTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3593 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
AnnaBridge 171:3a7713b1edbc 3594
AnnaBridge 171:3a7713b1edbc 3595
AnnaBridge 171:3a7713b1edbc 3596 /*!
AnnaBridge 171:3a7713b1edbc 3597 * @}
AnnaBridge 171:3a7713b1edbc 3598 */ /* end of group LLWU_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3599
AnnaBridge 171:3a7713b1edbc 3600
AnnaBridge 171:3a7713b1edbc 3601 /* LLWU - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3602 /** Peripheral LLWU base address */
AnnaBridge 171:3a7713b1edbc 3603 #define LLWU_BASE (0x4007C000u)
AnnaBridge 171:3a7713b1edbc 3604 /** Peripheral LLWU base pointer */
AnnaBridge 171:3a7713b1edbc 3605 #define LLWU ((LLWU_Type *)LLWU_BASE)
AnnaBridge 171:3a7713b1edbc 3606 /** Array initializer of LLWU peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3607 #define LLWU_BASE_ADDRS { LLWU_BASE }
AnnaBridge 171:3a7713b1edbc 3608 /** Array initializer of LLWU peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3609 #define LLWU_BASE_PTRS { LLWU }
AnnaBridge 171:3a7713b1edbc 3610 /** Interrupt vectors for the LLWU peripheral type */
AnnaBridge 171:3a7713b1edbc 3611 #define LLWU_IRQS { LLWU_IRQn }
AnnaBridge 171:3a7713b1edbc 3612
AnnaBridge 171:3a7713b1edbc 3613 /*!
AnnaBridge 171:3a7713b1edbc 3614 * @}
AnnaBridge 171:3a7713b1edbc 3615 */ /* end of group LLWU_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3616
AnnaBridge 171:3a7713b1edbc 3617
AnnaBridge 171:3a7713b1edbc 3618 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3619 -- LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3620 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3621
AnnaBridge 171:3a7713b1edbc 3622 /*!
AnnaBridge 171:3a7713b1edbc 3623 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3624 * @{
AnnaBridge 171:3a7713b1edbc 3625 */
AnnaBridge 171:3a7713b1edbc 3626
AnnaBridge 171:3a7713b1edbc 3627 /** LPTMR - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3628 typedef struct {
AnnaBridge 171:3a7713b1edbc 3629 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3630 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3631 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3632 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3633 } LPTMR_Type;
AnnaBridge 171:3a7713b1edbc 3634
AnnaBridge 171:3a7713b1edbc 3635 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3636 -- LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 3637 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3638
AnnaBridge 171:3a7713b1edbc 3639 /*!
AnnaBridge 171:3a7713b1edbc 3640 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 3641 * @{
AnnaBridge 171:3a7713b1edbc 3642 */
AnnaBridge 171:3a7713b1edbc 3643
AnnaBridge 171:3a7713b1edbc 3644 /*! @name CSR - Low Power Timer Control Status Register */
AnnaBridge 171:3a7713b1edbc 3645 #define LPTMR_CSR_TEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3646 #define LPTMR_CSR_TEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3647 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
AnnaBridge 171:3a7713b1edbc 3648 #define LPTMR_CSR_TMS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3649 #define LPTMR_CSR_TMS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3650 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
AnnaBridge 171:3a7713b1edbc 3651 #define LPTMR_CSR_TFC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3652 #define LPTMR_CSR_TFC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3653 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
AnnaBridge 171:3a7713b1edbc 3654 #define LPTMR_CSR_TPP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3655 #define LPTMR_CSR_TPP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3656 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
AnnaBridge 171:3a7713b1edbc 3657 #define LPTMR_CSR_TPS_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 3658 #define LPTMR_CSR_TPS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3659 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
AnnaBridge 171:3a7713b1edbc 3660 #define LPTMR_CSR_TIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3661 #define LPTMR_CSR_TIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3662 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 3663 #define LPTMR_CSR_TCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3664 #define LPTMR_CSR_TCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3665 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 3666
AnnaBridge 171:3a7713b1edbc 3667 /*! @name PSR - Low Power Timer Prescale Register */
AnnaBridge 171:3a7713b1edbc 3668 #define LPTMR_PSR_PCS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 3669 #define LPTMR_PSR_PCS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3670 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
AnnaBridge 171:3a7713b1edbc 3671 #define LPTMR_PSR_PBYP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3672 #define LPTMR_PSR_PBYP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3673 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
AnnaBridge 171:3a7713b1edbc 3674 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
AnnaBridge 171:3a7713b1edbc 3675 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3676 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
AnnaBridge 171:3a7713b1edbc 3677
AnnaBridge 171:3a7713b1edbc 3678 /*! @name CMR - Low Power Timer Compare Register */
AnnaBridge 171:3a7713b1edbc 3679 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3680 #define LPTMR_CMR_COMPARE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3681 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
AnnaBridge 171:3a7713b1edbc 3682
AnnaBridge 171:3a7713b1edbc 3683 /*! @name CNR - Low Power Timer Counter Register */
AnnaBridge 171:3a7713b1edbc 3684 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3685 #define LPTMR_CNR_COUNTER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3686 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
AnnaBridge 171:3a7713b1edbc 3687
AnnaBridge 171:3a7713b1edbc 3688
AnnaBridge 171:3a7713b1edbc 3689 /*!
AnnaBridge 171:3a7713b1edbc 3690 * @}
AnnaBridge 171:3a7713b1edbc 3691 */ /* end of group LPTMR_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3692
AnnaBridge 171:3a7713b1edbc 3693
AnnaBridge 171:3a7713b1edbc 3694 /* LPTMR - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3695 /** Peripheral LPTMR0 base address */
AnnaBridge 171:3a7713b1edbc 3696 #define LPTMR0_BASE (0x40040000u)
AnnaBridge 171:3a7713b1edbc 3697 /** Peripheral LPTMR0 base pointer */
AnnaBridge 171:3a7713b1edbc 3698 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
AnnaBridge 171:3a7713b1edbc 3699 /** Array initializer of LPTMR peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3700 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
AnnaBridge 171:3a7713b1edbc 3701 /** Array initializer of LPTMR peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3702 #define LPTMR_BASE_PTRS { LPTMR0 }
AnnaBridge 171:3a7713b1edbc 3703 /** Interrupt vectors for the LPTMR peripheral type */
AnnaBridge 171:3a7713b1edbc 3704 #define LPTMR_IRQS { LPTMR0_IRQn }
AnnaBridge 171:3a7713b1edbc 3705
AnnaBridge 171:3a7713b1edbc 3706 /*!
AnnaBridge 171:3a7713b1edbc 3707 * @}
AnnaBridge 171:3a7713b1edbc 3708 */ /* end of group LPTMR_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3709
AnnaBridge 171:3a7713b1edbc 3710
AnnaBridge 171:3a7713b1edbc 3711 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3712 -- LPUART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3713 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3714
AnnaBridge 171:3a7713b1edbc 3715 /*!
AnnaBridge 171:3a7713b1edbc 3716 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3717 * @{
AnnaBridge 171:3a7713b1edbc 3718 */
AnnaBridge 171:3a7713b1edbc 3719
AnnaBridge 171:3a7713b1edbc 3720 /** LPUART - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3721 typedef struct {
AnnaBridge 171:3a7713b1edbc 3722 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3723 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3724 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3725 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3726 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 3727 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 3728 } LPUART_Type;
AnnaBridge 171:3a7713b1edbc 3729
AnnaBridge 171:3a7713b1edbc 3730 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3731 -- LPUART Register Masks
AnnaBridge 171:3a7713b1edbc 3732 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3733
AnnaBridge 171:3a7713b1edbc 3734 /*!
AnnaBridge 171:3a7713b1edbc 3735 * @addtogroup LPUART_Register_Masks LPUART Register Masks
AnnaBridge 171:3a7713b1edbc 3736 * @{
AnnaBridge 171:3a7713b1edbc 3737 */
AnnaBridge 171:3a7713b1edbc 3738
AnnaBridge 171:3a7713b1edbc 3739 /*! @name BAUD - LPUART Baud Rate Register */
AnnaBridge 171:3a7713b1edbc 3740 #define LPUART_BAUD_SBR_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 3741 #define LPUART_BAUD_SBR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3742 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 3743 #define LPUART_BAUD_SBNS_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 3744 #define LPUART_BAUD_SBNS_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 3745 #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
AnnaBridge 171:3a7713b1edbc 3746 #define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 3747 #define LPUART_BAUD_RXEDGIE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 3748 #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
AnnaBridge 171:3a7713b1edbc 3749 #define LPUART_BAUD_LBKDIE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 3750 #define LPUART_BAUD_LBKDIE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 3751 #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
AnnaBridge 171:3a7713b1edbc 3752 #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 3753 #define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3754 #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
AnnaBridge 171:3a7713b1edbc 3755 #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 3756 #define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 3757 #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
AnnaBridge 171:3a7713b1edbc 3758 #define LPUART_BAUD_MATCFG_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 3759 #define LPUART_BAUD_MATCFG_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 3760 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
AnnaBridge 171:3a7713b1edbc 3761 #define LPUART_BAUD_RDMAE_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 3762 #define LPUART_BAUD_RDMAE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 3763 #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
AnnaBridge 171:3a7713b1edbc 3764 #define LPUART_BAUD_TDMAE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 3765 #define LPUART_BAUD_TDMAE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 3766 #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
AnnaBridge 171:3a7713b1edbc 3767 #define LPUART_BAUD_OSR_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 3768 #define LPUART_BAUD_OSR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 3769 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
AnnaBridge 171:3a7713b1edbc 3770 #define LPUART_BAUD_M10_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 3771 #define LPUART_BAUD_M10_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 3772 #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
AnnaBridge 171:3a7713b1edbc 3773 #define LPUART_BAUD_MAEN2_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 3774 #define LPUART_BAUD_MAEN2_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 3775 #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
AnnaBridge 171:3a7713b1edbc 3776 #define LPUART_BAUD_MAEN1_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 3777 #define LPUART_BAUD_MAEN1_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 3778 #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
AnnaBridge 171:3a7713b1edbc 3779
AnnaBridge 171:3a7713b1edbc 3780 /*! @name STAT - LPUART Status Register */
AnnaBridge 171:3a7713b1edbc 3781 #define LPUART_STAT_MA2F_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 3782 #define LPUART_STAT_MA2F_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 3783 #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
AnnaBridge 171:3a7713b1edbc 3784 #define LPUART_STAT_MA1F_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 3785 #define LPUART_STAT_MA1F_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 3786 #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
AnnaBridge 171:3a7713b1edbc 3787 #define LPUART_STAT_PF_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 3788 #define LPUART_STAT_PF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3789 #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
AnnaBridge 171:3a7713b1edbc 3790 #define LPUART_STAT_FE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 3791 #define LPUART_STAT_FE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 3792 #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
AnnaBridge 171:3a7713b1edbc 3793 #define LPUART_STAT_NF_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 3794 #define LPUART_STAT_NF_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 3795 #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
AnnaBridge 171:3a7713b1edbc 3796 #define LPUART_STAT_OR_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 3797 #define LPUART_STAT_OR_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 3798 #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
AnnaBridge 171:3a7713b1edbc 3799 #define LPUART_STAT_IDLE_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 3800 #define LPUART_STAT_IDLE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 3801 #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 3802 #define LPUART_STAT_RDRF_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 3803 #define LPUART_STAT_RDRF_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 3804 #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
AnnaBridge 171:3a7713b1edbc 3805 #define LPUART_STAT_TC_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 3806 #define LPUART_STAT_TC_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 3807 #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
AnnaBridge 171:3a7713b1edbc 3808 #define LPUART_STAT_TDRE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 3809 #define LPUART_STAT_TDRE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 3810 #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
AnnaBridge 171:3a7713b1edbc 3811 #define LPUART_STAT_RAF_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 3812 #define LPUART_STAT_RAF_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 3813 #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
AnnaBridge 171:3a7713b1edbc 3814 #define LPUART_STAT_LBKDE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 3815 #define LPUART_STAT_LBKDE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 3816 #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
AnnaBridge 171:3a7713b1edbc 3817 #define LPUART_STAT_BRK13_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 3818 #define LPUART_STAT_BRK13_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 3819 #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
AnnaBridge 171:3a7713b1edbc 3820 #define LPUART_STAT_RWUID_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 3821 #define LPUART_STAT_RWUID_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 3822 #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
AnnaBridge 171:3a7713b1edbc 3823 #define LPUART_STAT_RXINV_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 3824 #define LPUART_STAT_RXINV_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 3825 #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
AnnaBridge 171:3a7713b1edbc 3826 #define LPUART_STAT_MSBF_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 3827 #define LPUART_STAT_MSBF_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 3828 #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
AnnaBridge 171:3a7713b1edbc 3829 #define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 3830 #define LPUART_STAT_RXEDGIF_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 3831 #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
AnnaBridge 171:3a7713b1edbc 3832 #define LPUART_STAT_LBKDIF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 3833 #define LPUART_STAT_LBKDIF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 3834 #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
AnnaBridge 171:3a7713b1edbc 3835
AnnaBridge 171:3a7713b1edbc 3836 /*! @name CTRL - LPUART Control Register */
AnnaBridge 171:3a7713b1edbc 3837 #define LPUART_CTRL_PT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3838 #define LPUART_CTRL_PT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3839 #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
AnnaBridge 171:3a7713b1edbc 3840 #define LPUART_CTRL_PE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3841 #define LPUART_CTRL_PE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3842 #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
AnnaBridge 171:3a7713b1edbc 3843 #define LPUART_CTRL_ILT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3844 #define LPUART_CTRL_ILT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3845 #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
AnnaBridge 171:3a7713b1edbc 3846 #define LPUART_CTRL_WAKE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3847 #define LPUART_CTRL_WAKE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3848 #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
AnnaBridge 171:3a7713b1edbc 3849 #define LPUART_CTRL_M_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3850 #define LPUART_CTRL_M_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3851 #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
AnnaBridge 171:3a7713b1edbc 3852 #define LPUART_CTRL_RSRC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3853 #define LPUART_CTRL_RSRC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3854 #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
AnnaBridge 171:3a7713b1edbc 3855 #define LPUART_CTRL_DOZEEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3856 #define LPUART_CTRL_DOZEEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3857 #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
AnnaBridge 171:3a7713b1edbc 3858 #define LPUART_CTRL_LOOPS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3859 #define LPUART_CTRL_LOOPS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3860 #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
AnnaBridge 171:3a7713b1edbc 3861 #define LPUART_CTRL_IDLECFG_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 3862 #define LPUART_CTRL_IDLECFG_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3863 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
AnnaBridge 171:3a7713b1edbc 3864 #define LPUART_CTRL_MA2IE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 3865 #define LPUART_CTRL_MA2IE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 3866 #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
AnnaBridge 171:3a7713b1edbc 3867 #define LPUART_CTRL_MA1IE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 3868 #define LPUART_CTRL_MA1IE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 3869 #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
AnnaBridge 171:3a7713b1edbc 3870 #define LPUART_CTRL_SBK_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 3871 #define LPUART_CTRL_SBK_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3872 #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
AnnaBridge 171:3a7713b1edbc 3873 #define LPUART_CTRL_RWU_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 3874 #define LPUART_CTRL_RWU_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 3875 #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
AnnaBridge 171:3a7713b1edbc 3876 #define LPUART_CTRL_RE_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 3877 #define LPUART_CTRL_RE_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 3878 #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
AnnaBridge 171:3a7713b1edbc 3879 #define LPUART_CTRL_TE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 3880 #define LPUART_CTRL_TE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 3881 #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
AnnaBridge 171:3a7713b1edbc 3882 #define LPUART_CTRL_ILIE_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 3883 #define LPUART_CTRL_ILIE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 3884 #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
AnnaBridge 171:3a7713b1edbc 3885 #define LPUART_CTRL_RIE_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 3886 #define LPUART_CTRL_RIE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 3887 #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
AnnaBridge 171:3a7713b1edbc 3888 #define LPUART_CTRL_TCIE_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 3889 #define LPUART_CTRL_TCIE_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 3890 #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
AnnaBridge 171:3a7713b1edbc 3891 #define LPUART_CTRL_TIE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 3892 #define LPUART_CTRL_TIE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 3893 #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 3894 #define LPUART_CTRL_PEIE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 3895 #define LPUART_CTRL_PEIE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 3896 #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
AnnaBridge 171:3a7713b1edbc 3897 #define LPUART_CTRL_FEIE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 3898 #define LPUART_CTRL_FEIE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 3899 #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 3900 #define LPUART_CTRL_NEIE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 3901 #define LPUART_CTRL_NEIE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 3902 #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
AnnaBridge 171:3a7713b1edbc 3903 #define LPUART_CTRL_ORIE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 3904 #define LPUART_CTRL_ORIE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 3905 #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
AnnaBridge 171:3a7713b1edbc 3906 #define LPUART_CTRL_TXINV_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 3907 #define LPUART_CTRL_TXINV_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 3908 #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
AnnaBridge 171:3a7713b1edbc 3909 #define LPUART_CTRL_TXDIR_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 3910 #define LPUART_CTRL_TXDIR_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 3911 #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
AnnaBridge 171:3a7713b1edbc 3912 #define LPUART_CTRL_R9T8_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 3913 #define LPUART_CTRL_R9T8_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 3914 #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
AnnaBridge 171:3a7713b1edbc 3915 #define LPUART_CTRL_R8T9_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 3916 #define LPUART_CTRL_R8T9_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 3917 #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
AnnaBridge 171:3a7713b1edbc 3918
AnnaBridge 171:3a7713b1edbc 3919 /*! @name DATA - LPUART Data Register */
AnnaBridge 171:3a7713b1edbc 3920 #define LPUART_DATA_R0T0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3921 #define LPUART_DATA_R0T0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3922 #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
AnnaBridge 171:3a7713b1edbc 3923 #define LPUART_DATA_R1T1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3924 #define LPUART_DATA_R1T1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3925 #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
AnnaBridge 171:3a7713b1edbc 3926 #define LPUART_DATA_R2T2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3927 #define LPUART_DATA_R2T2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3928 #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
AnnaBridge 171:3a7713b1edbc 3929 #define LPUART_DATA_R3T3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3930 #define LPUART_DATA_R3T3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3931 #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
AnnaBridge 171:3a7713b1edbc 3932 #define LPUART_DATA_R4T4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3933 #define LPUART_DATA_R4T4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3934 #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
AnnaBridge 171:3a7713b1edbc 3935 #define LPUART_DATA_R5T5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3936 #define LPUART_DATA_R5T5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3937 #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
AnnaBridge 171:3a7713b1edbc 3938 #define LPUART_DATA_R6T6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3939 #define LPUART_DATA_R6T6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3940 #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
AnnaBridge 171:3a7713b1edbc 3941 #define LPUART_DATA_R7T7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3942 #define LPUART_DATA_R7T7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3943 #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
AnnaBridge 171:3a7713b1edbc 3944 #define LPUART_DATA_R8T8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 3945 #define LPUART_DATA_R8T8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3946 #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
AnnaBridge 171:3a7713b1edbc 3947 #define LPUART_DATA_R9T9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 3948 #define LPUART_DATA_R9T9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 3949 #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
AnnaBridge 171:3a7713b1edbc 3950 #define LPUART_DATA_IDLINE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 3951 #define LPUART_DATA_IDLINE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 3952 #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
AnnaBridge 171:3a7713b1edbc 3953 #define LPUART_DATA_RXEMPT_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 3954 #define LPUART_DATA_RXEMPT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 3955 #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
AnnaBridge 171:3a7713b1edbc 3956 #define LPUART_DATA_FRETSC_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 3957 #define LPUART_DATA_FRETSC_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 3958 #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
AnnaBridge 171:3a7713b1edbc 3959 #define LPUART_DATA_PARITYE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 3960 #define LPUART_DATA_PARITYE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 3961 #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
AnnaBridge 171:3a7713b1edbc 3962 #define LPUART_DATA_NOISY_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 3963 #define LPUART_DATA_NOISY_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 3964 #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
AnnaBridge 171:3a7713b1edbc 3965
AnnaBridge 171:3a7713b1edbc 3966 /*! @name MATCH - LPUART Match Address Register */
AnnaBridge 171:3a7713b1edbc 3967 #define LPUART_MATCH_MA1_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 3968 #define LPUART_MATCH_MA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3969 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
AnnaBridge 171:3a7713b1edbc 3970 #define LPUART_MATCH_MA2_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 3971 #define LPUART_MATCH_MA2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3972 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
AnnaBridge 171:3a7713b1edbc 3973
AnnaBridge 171:3a7713b1edbc 3974 /*! @name MODIR - LPUART Modem IrDA Register */
AnnaBridge 171:3a7713b1edbc 3975 #define LPUART_MODIR_TXCTSE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3976 #define LPUART_MODIR_TXCTSE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3977 #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
AnnaBridge 171:3a7713b1edbc 3978 #define LPUART_MODIR_TXRTSE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3979 #define LPUART_MODIR_TXRTSE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3980 #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
AnnaBridge 171:3a7713b1edbc 3981 #define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3982 #define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3983 #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
AnnaBridge 171:3a7713b1edbc 3984 #define LPUART_MODIR_RXRTSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3985 #define LPUART_MODIR_RXRTSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3986 #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
AnnaBridge 171:3a7713b1edbc 3987 #define LPUART_MODIR_TXCTSC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3988 #define LPUART_MODIR_TXCTSC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3989 #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
AnnaBridge 171:3a7713b1edbc 3990 #define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3991 #define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3992 #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
AnnaBridge 171:3a7713b1edbc 3993 #define LPUART_MODIR_TNP_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 3994 #define LPUART_MODIR_TNP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3995 #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
AnnaBridge 171:3a7713b1edbc 3996 #define LPUART_MODIR_IREN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 3997 #define LPUART_MODIR_IREN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 3998 #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
AnnaBridge 171:3a7713b1edbc 3999
AnnaBridge 171:3a7713b1edbc 4000
AnnaBridge 171:3a7713b1edbc 4001 /*!
AnnaBridge 171:3a7713b1edbc 4002 * @}
AnnaBridge 171:3a7713b1edbc 4003 */ /* end of group LPUART_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4004
AnnaBridge 171:3a7713b1edbc 4005
AnnaBridge 171:3a7713b1edbc 4006 /* LPUART - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4007 /** Peripheral LPUART0 base address */
AnnaBridge 171:3a7713b1edbc 4008 #define LPUART0_BASE (0x40054000u)
AnnaBridge 171:3a7713b1edbc 4009 /** Peripheral LPUART0 base pointer */
AnnaBridge 171:3a7713b1edbc 4010 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
AnnaBridge 171:3a7713b1edbc 4011 /** Array initializer of LPUART peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4012 #define LPUART_BASE_ADDRS { LPUART0_BASE }
AnnaBridge 171:3a7713b1edbc 4013 /** Array initializer of LPUART peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4014 #define LPUART_BASE_PTRS { LPUART0 }
AnnaBridge 171:3a7713b1edbc 4015 /** Interrupt vectors for the LPUART peripheral type */
AnnaBridge 171:3a7713b1edbc 4016 #define LPUART_RX_TX_IRQS { LPUART0_IRQn }
AnnaBridge 171:3a7713b1edbc 4017 #define LPUART_ERR_IRQS { LPUART0_IRQn }
AnnaBridge 171:3a7713b1edbc 4018
AnnaBridge 171:3a7713b1edbc 4019 /*!
AnnaBridge 171:3a7713b1edbc 4020 * @}
AnnaBridge 171:3a7713b1edbc 4021 */ /* end of group LPUART_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4022
AnnaBridge 171:3a7713b1edbc 4023
AnnaBridge 171:3a7713b1edbc 4024 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4025 -- LTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4026 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4027
AnnaBridge 171:3a7713b1edbc 4028 /*!
AnnaBridge 171:3a7713b1edbc 4029 * @addtogroup LTC_Peripheral_Access_Layer LTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4030 * @{
AnnaBridge 171:3a7713b1edbc 4031 */
AnnaBridge 171:3a7713b1edbc 4032
AnnaBridge 171:3a7713b1edbc 4033 /** LTC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4034 typedef struct {
AnnaBridge 171:3a7713b1edbc 4035 __IO uint32_t MD; /**< Mode Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4036 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 4037 __IO uint32_t KS; /**< Key Size Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4038 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 4039 __IO uint32_t DS; /**< Data Size Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 4040 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 4041 __IO uint32_t ICVS; /**< ICV Size Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 4042 uint8_t RESERVED_3[20];
AnnaBridge 171:3a7713b1edbc 4043 __IO uint32_t COM; /**< Command Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 4044 __IO uint32_t CTL; /**< Control Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 4045 uint8_t RESERVED_4[8];
AnnaBridge 171:3a7713b1edbc 4046 __IO uint32_t CW; /**< Clear Written Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 4047 uint8_t RESERVED_5[4];
AnnaBridge 171:3a7713b1edbc 4048 __IO uint32_t STA; /**< Status Register, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 4049 __I uint32_t ESTA; /**< Error Status Register, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 4050 uint8_t RESERVED_6[8];
AnnaBridge 171:3a7713b1edbc 4051 __IO uint32_t AADSZ; /**< AAD Size Register, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 4052 uint8_t RESERVED_7[164];
AnnaBridge 171:3a7713b1edbc 4053 __IO uint32_t CTX[14]; /**< Context Register, array offset: 0x100, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 4054 uint8_t RESERVED_8[200];
AnnaBridge 171:3a7713b1edbc 4055 __IO uint32_t KEY[4]; /**< Key Registers, array offset: 0x200, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 4056 uint8_t RESERVED_9[736];
AnnaBridge 171:3a7713b1edbc 4057 __I uint32_t VID1; /**< Version ID Register, offset: 0x4F0 */
AnnaBridge 171:3a7713b1edbc 4058 __I uint32_t VID2; /**< Version ID 2 Register, offset: 0x4F4 */
AnnaBridge 171:3a7713b1edbc 4059 __I uint32_t CHAVID; /**< CHA Version ID Register, offset: 0x4F8 */
AnnaBridge 171:3a7713b1edbc 4060 uint8_t RESERVED_10[708];
AnnaBridge 171:3a7713b1edbc 4061 __I uint32_t FIFOSTA; /**< FIFO Status Register, offset: 0x7C0 */
AnnaBridge 171:3a7713b1edbc 4062 uint8_t RESERVED_11[28];
AnnaBridge 171:3a7713b1edbc 4063 __O uint32_t IFIFO; /**< Input Data FIFO, offset: 0x7E0 */
AnnaBridge 171:3a7713b1edbc 4064 uint8_t RESERVED_12[12];
AnnaBridge 171:3a7713b1edbc 4065 __I uint32_t OFIFO; /**< Output Data FIFO, offset: 0x7F0 */
AnnaBridge 171:3a7713b1edbc 4066 } LTC_Type;
AnnaBridge 171:3a7713b1edbc 4067
AnnaBridge 171:3a7713b1edbc 4068 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4069 -- LTC Register Masks
AnnaBridge 171:3a7713b1edbc 4070 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4071
AnnaBridge 171:3a7713b1edbc 4072 /*!
AnnaBridge 171:3a7713b1edbc 4073 * @addtogroup LTC_Register_Masks LTC Register Masks
AnnaBridge 171:3a7713b1edbc 4074 * @{
AnnaBridge 171:3a7713b1edbc 4075 */
AnnaBridge 171:3a7713b1edbc 4076
AnnaBridge 171:3a7713b1edbc 4077 /*! @name MD - Mode Register */
AnnaBridge 171:3a7713b1edbc 4078 #define LTC_MD_ENC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4079 #define LTC_MD_ENC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4080 #define LTC_MD_ENC(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ENC_SHIFT)) & LTC_MD_ENC_MASK)
AnnaBridge 171:3a7713b1edbc 4081 #define LTC_MD_ICV_TEST_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4082 #define LTC_MD_ICV_TEST_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4083 #define LTC_MD_ICV_TEST(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
AnnaBridge 171:3a7713b1edbc 4084 #define LTC_MD_AS_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 4085 #define LTC_MD_AS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4086 #define LTC_MD_AS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AS_SHIFT)) & LTC_MD_AS_MASK)
AnnaBridge 171:3a7713b1edbc 4087 #define LTC_MD_AAI_MASK (0x1FF0U)
AnnaBridge 171:3a7713b1edbc 4088 #define LTC_MD_AAI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4089 #define LTC_MD_AAI(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AAI_SHIFT)) & LTC_MD_AAI_MASK)
AnnaBridge 171:3a7713b1edbc 4090 #define LTC_MD_ALG_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 4091 #define LTC_MD_ALG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4092 #define LTC_MD_ALG(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ALG_SHIFT)) & LTC_MD_ALG_MASK)
AnnaBridge 171:3a7713b1edbc 4093
AnnaBridge 171:3a7713b1edbc 4094 /*! @name KS - Key Size Register */
AnnaBridge 171:3a7713b1edbc 4095 #define LTC_KS_KS_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4096 #define LTC_KS_KS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4097 #define LTC_KS_KS(x) (((uint32_t)(((uint32_t)(x)) << LTC_KS_KS_SHIFT)) & LTC_KS_KS_MASK)
AnnaBridge 171:3a7713b1edbc 4098
AnnaBridge 171:3a7713b1edbc 4099 /*! @name DS - Data Size Register */
AnnaBridge 171:3a7713b1edbc 4100 #define LTC_DS_DS_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 4101 #define LTC_DS_DS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4102 #define LTC_DS_DS(x) (((uint32_t)(((uint32_t)(x)) << LTC_DS_DS_SHIFT)) & LTC_DS_DS_MASK)
AnnaBridge 171:3a7713b1edbc 4103
AnnaBridge 171:3a7713b1edbc 4104 /*! @name ICVS - ICV Size Register */
AnnaBridge 171:3a7713b1edbc 4105 #define LTC_ICVS_ICVS_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4106 #define LTC_ICVS_ICVS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4107 #define LTC_ICVS_ICVS(x) (((uint32_t)(((uint32_t)(x)) << LTC_ICVS_ICVS_SHIFT)) & LTC_ICVS_ICVS_MASK)
AnnaBridge 171:3a7713b1edbc 4108
AnnaBridge 171:3a7713b1edbc 4109 /*! @name COM - Command Register */
AnnaBridge 171:3a7713b1edbc 4110 #define LTC_COM_ALL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4111 #define LTC_COM_ALL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4112 #define LTC_COM_ALL(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_ALL_SHIFT)) & LTC_COM_ALL_MASK)
AnnaBridge 171:3a7713b1edbc 4113 #define LTC_COM_AES_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4114 #define LTC_COM_AES_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4115 #define LTC_COM_AES(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_AES_SHIFT)) & LTC_COM_AES_MASK)
AnnaBridge 171:3a7713b1edbc 4116
AnnaBridge 171:3a7713b1edbc 4117 /*! @name CTL - Control Register */
AnnaBridge 171:3a7713b1edbc 4118 #define LTC_CTL_IM_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4119 #define LTC_CTL_IM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4120 #define LTC_CTL_IM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IM_SHIFT)) & LTC_CTL_IM_MASK)
AnnaBridge 171:3a7713b1edbc 4121 #define LTC_CTL_IFE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4122 #define LTC_CTL_IFE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4123 #define LTC_CTL_IFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFE_SHIFT)) & LTC_CTL_IFE_MASK)
AnnaBridge 171:3a7713b1edbc 4124 #define LTC_CTL_IFR_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4125 #define LTC_CTL_IFR_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4126 #define LTC_CTL_IFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
AnnaBridge 171:3a7713b1edbc 4127 #define LTC_CTL_OFE_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4128 #define LTC_CTL_OFE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4129 #define LTC_CTL_OFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFE_SHIFT)) & LTC_CTL_OFE_MASK)
AnnaBridge 171:3a7713b1edbc 4130 #define LTC_CTL_OFR_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4131 #define LTC_CTL_OFR_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4132 #define LTC_CTL_OFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFR_SHIFT)) & LTC_CTL_OFR_MASK)
AnnaBridge 171:3a7713b1edbc 4133 #define LTC_CTL_IFS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4134 #define LTC_CTL_IFS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4135 #define LTC_CTL_IFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFS_SHIFT)) & LTC_CTL_IFS_MASK)
AnnaBridge 171:3a7713b1edbc 4136 #define LTC_CTL_OFS_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 4137 #define LTC_CTL_OFS_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 4138 #define LTC_CTL_OFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFS_SHIFT)) & LTC_CTL_OFS_MASK)
AnnaBridge 171:3a7713b1edbc 4139 #define LTC_CTL_KIS_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4140 #define LTC_CTL_KIS_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4141 #define LTC_CTL_KIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KIS_SHIFT)) & LTC_CTL_KIS_MASK)
AnnaBridge 171:3a7713b1edbc 4142 #define LTC_CTL_KOS_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 4143 #define LTC_CTL_KOS_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 4144 #define LTC_CTL_KOS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KOS_SHIFT)) & LTC_CTL_KOS_MASK)
AnnaBridge 171:3a7713b1edbc 4145 #define LTC_CTL_CIS_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 4146 #define LTC_CTL_CIS_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 4147 #define LTC_CTL_CIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_CIS_SHIFT)) & LTC_CTL_CIS_MASK)
AnnaBridge 171:3a7713b1edbc 4148 #define LTC_CTL_COS_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 4149 #define LTC_CTL_COS_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 4150 #define LTC_CTL_COS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_COS_SHIFT)) & LTC_CTL_COS_MASK)
AnnaBridge 171:3a7713b1edbc 4151 #define LTC_CTL_KAL_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4152 #define LTC_CTL_KAL_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4153 #define LTC_CTL_KAL(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KAL_SHIFT)) & LTC_CTL_KAL_MASK)
AnnaBridge 171:3a7713b1edbc 4154
AnnaBridge 171:3a7713b1edbc 4155 /*! @name CW - Clear Written Register */
AnnaBridge 171:3a7713b1edbc 4156 #define LTC_CW_CM_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4157 #define LTC_CW_CM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4158 #define LTC_CW_CM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CM_SHIFT)) & LTC_CW_CM_MASK)
AnnaBridge 171:3a7713b1edbc 4159 #define LTC_CW_CDS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4160 #define LTC_CW_CDS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4161 #define LTC_CW_CDS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CDS_SHIFT)) & LTC_CW_CDS_MASK)
AnnaBridge 171:3a7713b1edbc 4162 #define LTC_CW_CICV_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4163 #define LTC_CW_CICV_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4164 #define LTC_CW_CICV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CICV_SHIFT)) & LTC_CW_CICV_MASK)
AnnaBridge 171:3a7713b1edbc 4165 #define LTC_CW_CCR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4166 #define LTC_CW_CCR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4167 #define LTC_CW_CCR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CCR_SHIFT)) & LTC_CW_CCR_MASK)
AnnaBridge 171:3a7713b1edbc 4168 #define LTC_CW_CKR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4169 #define LTC_CW_CKR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4170 #define LTC_CW_CKR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CKR_SHIFT)) & LTC_CW_CKR_MASK)
AnnaBridge 171:3a7713b1edbc 4171 #define LTC_CW_COF_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4172 #define LTC_CW_COF_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4173 #define LTC_CW_COF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_COF_SHIFT)) & LTC_CW_COF_MASK)
AnnaBridge 171:3a7713b1edbc 4174 #define LTC_CW_CIF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4175 #define LTC_CW_CIF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4176 #define LTC_CW_CIF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CIF_SHIFT)) & LTC_CW_CIF_MASK)
AnnaBridge 171:3a7713b1edbc 4177
AnnaBridge 171:3a7713b1edbc 4178 /*! @name STA - Status Register */
AnnaBridge 171:3a7713b1edbc 4179 #define LTC_STA_AB_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4180 #define LTC_STA_AB_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4181 #define LTC_STA_AB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_AB_SHIFT)) & LTC_STA_AB_MASK)
AnnaBridge 171:3a7713b1edbc 4182 #define LTC_STA_DI_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4183 #define LTC_STA_DI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4184 #define LTC_STA_DI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_DI_SHIFT)) & LTC_STA_DI_MASK)
AnnaBridge 171:3a7713b1edbc 4185 #define LTC_STA_EI_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4186 #define LTC_STA_EI_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4187 #define LTC_STA_EI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_EI_SHIFT)) & LTC_STA_EI_MASK)
AnnaBridge 171:3a7713b1edbc 4188
AnnaBridge 171:3a7713b1edbc 4189 /*! @name ESTA - Error Status Register */
AnnaBridge 171:3a7713b1edbc 4190 #define LTC_ESTA_ERRID1_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4191 #define LTC_ESTA_ERRID1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4192 #define LTC_ESTA_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_ERRID1_SHIFT)) & LTC_ESTA_ERRID1_MASK)
AnnaBridge 171:3a7713b1edbc 4193 #define LTC_ESTA_CL1_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 4194 #define LTC_ESTA_CL1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4195 #define LTC_ESTA_CL1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_CL1_SHIFT)) & LTC_ESTA_CL1_MASK)
AnnaBridge 171:3a7713b1edbc 4196
AnnaBridge 171:3a7713b1edbc 4197 /*! @name AADSZ - AAD Size Register */
AnnaBridge 171:3a7713b1edbc 4198 #define LTC_AADSZ_AADSZ_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4199 #define LTC_AADSZ_AADSZ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4200 #define LTC_AADSZ_AADSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AADSZ_SHIFT)) & LTC_AADSZ_AADSZ_MASK)
AnnaBridge 171:3a7713b1edbc 4201 #define LTC_AADSZ_AL_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4202 #define LTC_AADSZ_AL_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4203 #define LTC_AADSZ_AL(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AL_SHIFT)) & LTC_AADSZ_AL_MASK)
AnnaBridge 171:3a7713b1edbc 4204
AnnaBridge 171:3a7713b1edbc 4205 /*! @name CTX - Context Register */
AnnaBridge 171:3a7713b1edbc 4206 #define LTC_CTX_CTX_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4207 #define LTC_CTX_CTX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4208 #define LTC_CTX_CTX(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTX_CTX_SHIFT)) & LTC_CTX_CTX_MASK)
AnnaBridge 171:3a7713b1edbc 4209
AnnaBridge 171:3a7713b1edbc 4210 /* The count of LTC_CTX */
AnnaBridge 171:3a7713b1edbc 4211 #define LTC_CTX_COUNT (14U)
AnnaBridge 171:3a7713b1edbc 4212
AnnaBridge 171:3a7713b1edbc 4213 /*! @name KEY - Key Registers */
AnnaBridge 171:3a7713b1edbc 4214 #define LTC_KEY_KEY_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4215 #define LTC_KEY_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4216 #define LTC_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << LTC_KEY_KEY_SHIFT)) & LTC_KEY_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 4217
AnnaBridge 171:3a7713b1edbc 4218 /* The count of LTC_KEY */
AnnaBridge 171:3a7713b1edbc 4219 #define LTC_KEY_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 4220
AnnaBridge 171:3a7713b1edbc 4221 /*! @name VID1 - Version ID Register */
AnnaBridge 171:3a7713b1edbc 4222 #define LTC_VID1_MIN_REV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4223 #define LTC_VID1_MIN_REV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4224 #define LTC_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MIN_REV_SHIFT)) & LTC_VID1_MIN_REV_MASK)
AnnaBridge 171:3a7713b1edbc 4225 #define LTC_VID1_MAJ_REV_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 4226 #define LTC_VID1_MAJ_REV_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4227 #define LTC_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MAJ_REV_SHIFT)) & LTC_VID1_MAJ_REV_MASK)
AnnaBridge 171:3a7713b1edbc 4228 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 4229 #define LTC_VID1_IP_ID_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4230 #define LTC_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
AnnaBridge 171:3a7713b1edbc 4231
AnnaBridge 171:3a7713b1edbc 4232 /*! @name VID2 - Version ID 2 Register */
AnnaBridge 171:3a7713b1edbc 4233 #define LTC_VID2_ECO_REV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4234 #define LTC_VID2_ECO_REV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4235 #define LTC_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ECO_REV_SHIFT)) & LTC_VID2_ECO_REV_MASK)
AnnaBridge 171:3a7713b1edbc 4236 #define LTC_VID2_ARCH_ERA_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 4237 #define LTC_VID2_ARCH_ERA_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4238 #define LTC_VID2_ARCH_ERA(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ARCH_ERA_SHIFT)) & LTC_VID2_ARCH_ERA_MASK)
AnnaBridge 171:3a7713b1edbc 4239
AnnaBridge 171:3a7713b1edbc 4240 /*! @name CHAVID - CHA Version ID Register */
AnnaBridge 171:3a7713b1edbc 4241 #define LTC_CHAVID_AESREV_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4242 #define LTC_CHAVID_AESREV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4243 #define LTC_CHAVID_AESREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESREV_SHIFT)) & LTC_CHAVID_AESREV_MASK)
AnnaBridge 171:3a7713b1edbc 4244 #define LTC_CHAVID_AESVID_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 4245 #define LTC_CHAVID_AESVID_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4246 #define LTC_CHAVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
AnnaBridge 171:3a7713b1edbc 4247
AnnaBridge 171:3a7713b1edbc 4248 /*! @name FIFOSTA - FIFO Status Register */
AnnaBridge 171:3a7713b1edbc 4249 #define LTC_FIFOSTA_IFL_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 4250 #define LTC_FIFOSTA_IFL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4251 #define LTC_FIFOSTA_IFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFL_SHIFT)) & LTC_FIFOSTA_IFL_MASK)
AnnaBridge 171:3a7713b1edbc 4252 #define LTC_FIFOSTA_IFF_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4253 #define LTC_FIFOSTA_IFF_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4254 #define LTC_FIFOSTA_IFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFF_SHIFT)) & LTC_FIFOSTA_IFF_MASK)
AnnaBridge 171:3a7713b1edbc 4255 #define LTC_FIFOSTA_OFL_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 4256 #define LTC_FIFOSTA_OFL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4257 #define LTC_FIFOSTA_OFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFL_SHIFT)) & LTC_FIFOSTA_OFL_MASK)
AnnaBridge 171:3a7713b1edbc 4258 #define LTC_FIFOSTA_OFF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4259 #define LTC_FIFOSTA_OFF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4260 #define LTC_FIFOSTA_OFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFF_SHIFT)) & LTC_FIFOSTA_OFF_MASK)
AnnaBridge 171:3a7713b1edbc 4261
AnnaBridge 171:3a7713b1edbc 4262 /*! @name IFIFO - Input Data FIFO */
AnnaBridge 171:3a7713b1edbc 4263 #define LTC_IFIFO_IFIFO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4264 #define LTC_IFIFO_IFIFO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4265 #define LTC_IFIFO_IFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_IFIFO_IFIFO_SHIFT)) & LTC_IFIFO_IFIFO_MASK)
AnnaBridge 171:3a7713b1edbc 4266
AnnaBridge 171:3a7713b1edbc 4267 /*! @name OFIFO - Output Data FIFO */
AnnaBridge 171:3a7713b1edbc 4268 #define LTC_OFIFO_OFIFO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4269 #define LTC_OFIFO_OFIFO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4270 #define LTC_OFIFO_OFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_OFIFO_OFIFO_SHIFT)) & LTC_OFIFO_OFIFO_MASK)
AnnaBridge 171:3a7713b1edbc 4271
AnnaBridge 171:3a7713b1edbc 4272
AnnaBridge 171:3a7713b1edbc 4273 /*!
AnnaBridge 171:3a7713b1edbc 4274 * @}
AnnaBridge 171:3a7713b1edbc 4275 */ /* end of group LTC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4276
AnnaBridge 171:3a7713b1edbc 4277
AnnaBridge 171:3a7713b1edbc 4278 /* LTC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4279 /** Peripheral LTC0 base address */
AnnaBridge 171:3a7713b1edbc 4280 #define LTC0_BASE (0x40058000u)
AnnaBridge 171:3a7713b1edbc 4281 /** Peripheral LTC0 base pointer */
AnnaBridge 171:3a7713b1edbc 4282 #define LTC0 ((LTC_Type *)LTC0_BASE)
AnnaBridge 171:3a7713b1edbc 4283 /** Array initializer of LTC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4284 #define LTC_BASE_ADDRS { LTC0_BASE }
AnnaBridge 171:3a7713b1edbc 4285 /** Array initializer of LTC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4286 #define LTC_BASE_PTRS { LTC0 }
AnnaBridge 171:3a7713b1edbc 4287 /** Interrupt vectors for the LTC peripheral type */
AnnaBridge 171:3a7713b1edbc 4288 #define LTC_IRQS { LTC0_IRQn }
AnnaBridge 171:3a7713b1edbc 4289
AnnaBridge 171:3a7713b1edbc 4290 /*!
AnnaBridge 171:3a7713b1edbc 4291 * @}
AnnaBridge 171:3a7713b1edbc 4292 */ /* end of group LTC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4293
AnnaBridge 171:3a7713b1edbc 4294
AnnaBridge 171:3a7713b1edbc 4295 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4296 -- MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4297 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4298
AnnaBridge 171:3a7713b1edbc 4299 /*!
AnnaBridge 171:3a7713b1edbc 4300 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4301 * @{
AnnaBridge 171:3a7713b1edbc 4302 */
AnnaBridge 171:3a7713b1edbc 4303
AnnaBridge 171:3a7713b1edbc 4304 /** MCG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4305 typedef struct {
AnnaBridge 171:3a7713b1edbc 4306 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4307 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 4308 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 4309 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 4310 __I uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4311 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 4312 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 4313 uint8_t RESERVED_0[1];
AnnaBridge 171:3a7713b1edbc 4314 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4315 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 4316 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 4317 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 4318 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 4319 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 4320 } MCG_Type;
AnnaBridge 171:3a7713b1edbc 4321
AnnaBridge 171:3a7713b1edbc 4322 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4323 -- MCG Register Masks
AnnaBridge 171:3a7713b1edbc 4324 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4325
AnnaBridge 171:3a7713b1edbc 4326 /*!
AnnaBridge 171:3a7713b1edbc 4327 * @addtogroup MCG_Register_Masks MCG Register Masks
AnnaBridge 171:3a7713b1edbc 4328 * @{
AnnaBridge 171:3a7713b1edbc 4329 */
AnnaBridge 171:3a7713b1edbc 4330
AnnaBridge 171:3a7713b1edbc 4331 /*! @name C1 - MCG Control 1 Register */
AnnaBridge 171:3a7713b1edbc 4332 #define MCG_C1_IREFSTEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4333 #define MCG_C1_IREFSTEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4334 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 4335 #define MCG_C1_IRCLKEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4336 #define MCG_C1_IRCLKEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4337 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 4338 #define MCG_C1_IREFS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4339 #define MCG_C1_IREFS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4340 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
AnnaBridge 171:3a7713b1edbc 4341 #define MCG_C1_FRDIV_MASK (0x38U)
AnnaBridge 171:3a7713b1edbc 4342 #define MCG_C1_FRDIV_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4343 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 4344 #define MCG_C1_CLKS_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 4345 #define MCG_C1_CLKS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4346 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 4347
AnnaBridge 171:3a7713b1edbc 4348 /*! @name C2 - MCG Control 2 Register */
AnnaBridge 171:3a7713b1edbc 4349 #define MCG_C2_IRCS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4350 #define MCG_C2_IRCS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4351 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
AnnaBridge 171:3a7713b1edbc 4352 #define MCG_C2_LP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4353 #define MCG_C2_LP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4354 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
AnnaBridge 171:3a7713b1edbc 4355 #define MCG_C2_EREFS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4356 #define MCG_C2_EREFS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4357 #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
AnnaBridge 171:3a7713b1edbc 4358 #define MCG_C2_HGO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4359 #define MCG_C2_HGO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4360 #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
AnnaBridge 171:3a7713b1edbc 4361 #define MCG_C2_RANGE_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 4362 #define MCG_C2_RANGE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4363 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
AnnaBridge 171:3a7713b1edbc 4364 #define MCG_C2_FCFTRIM_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4365 #define MCG_C2_FCFTRIM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4366 #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 4367 #define MCG_C2_LOCRE0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4368 #define MCG_C2_LOCRE0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4369 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
AnnaBridge 171:3a7713b1edbc 4370
AnnaBridge 171:3a7713b1edbc 4371 /*! @name C3 - MCG Control 3 Register */
AnnaBridge 171:3a7713b1edbc 4372 #define MCG_C3_SCTRIM_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4373 #define MCG_C3_SCTRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4374 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 4375
AnnaBridge 171:3a7713b1edbc 4376 /*! @name C4 - MCG Control 4 Register */
AnnaBridge 171:3a7713b1edbc 4377 #define MCG_C4_SCFTRIM_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4378 #define MCG_C4_SCFTRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4379 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 4380 #define MCG_C4_FCTRIM_MASK (0x1EU)
AnnaBridge 171:3a7713b1edbc 4381 #define MCG_C4_FCTRIM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4382 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 4383 #define MCG_C4_DRST_DRS_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 4384 #define MCG_C4_DRST_DRS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4385 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
AnnaBridge 171:3a7713b1edbc 4386 #define MCG_C4_DMX32_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4387 #define MCG_C4_DMX32_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4388 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
AnnaBridge 171:3a7713b1edbc 4389
AnnaBridge 171:3a7713b1edbc 4390 /*! @name C6 - MCG Control 6 Register */
AnnaBridge 171:3a7713b1edbc 4391 #define MCG_C6_CME0_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4392 #define MCG_C6_CME0_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4393 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
AnnaBridge 171:3a7713b1edbc 4394
AnnaBridge 171:3a7713b1edbc 4395 /*! @name S - MCG Status Register */
AnnaBridge 171:3a7713b1edbc 4396 #define MCG_S_IRCST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4397 #define MCG_S_IRCST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4398 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
AnnaBridge 171:3a7713b1edbc 4399 #define MCG_S_OSCINIT0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4400 #define MCG_S_OSCINIT0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4401 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
AnnaBridge 171:3a7713b1edbc 4402 #define MCG_S_CLKST_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 4403 #define MCG_S_CLKST_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4404 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
AnnaBridge 171:3a7713b1edbc 4405 #define MCG_S_IREFST_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4406 #define MCG_S_IREFST_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4407 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
AnnaBridge 171:3a7713b1edbc 4408
AnnaBridge 171:3a7713b1edbc 4409 /*! @name SC - MCG Status and Control Register */
AnnaBridge 171:3a7713b1edbc 4410 #define MCG_SC_LOCS0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4411 #define MCG_SC_LOCS0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4412 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
AnnaBridge 171:3a7713b1edbc 4413 #define MCG_SC_FCRDIV_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 4414 #define MCG_SC_FCRDIV_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4415 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 4416 #define MCG_SC_FLTPRSRV_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4417 #define MCG_SC_FLTPRSRV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4418 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
AnnaBridge 171:3a7713b1edbc 4419 #define MCG_SC_ATMF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4420 #define MCG_SC_ATMF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4421 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
AnnaBridge 171:3a7713b1edbc 4422 #define MCG_SC_ATMS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4423 #define MCG_SC_ATMS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4424 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
AnnaBridge 171:3a7713b1edbc 4425 #define MCG_SC_ATME_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4426 #define MCG_SC_ATME_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4427 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
AnnaBridge 171:3a7713b1edbc 4428
AnnaBridge 171:3a7713b1edbc 4429 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
AnnaBridge 171:3a7713b1edbc 4430 #define MCG_ATCVH_ATCVH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4431 #define MCG_ATCVH_ATCVH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4432 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
AnnaBridge 171:3a7713b1edbc 4433
AnnaBridge 171:3a7713b1edbc 4434 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
AnnaBridge 171:3a7713b1edbc 4435 #define MCG_ATCVL_ATCVL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4436 #define MCG_ATCVL_ATCVL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4437 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
AnnaBridge 171:3a7713b1edbc 4438
AnnaBridge 171:3a7713b1edbc 4439 /*! @name C7 - MCG Control 7 Register */
AnnaBridge 171:3a7713b1edbc 4440 #define MCG_C7_OSCSEL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4441 #define MCG_C7_OSCSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4442 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
AnnaBridge 171:3a7713b1edbc 4443
AnnaBridge 171:3a7713b1edbc 4444 /*! @name C8 - MCG Control 8 Register */
AnnaBridge 171:3a7713b1edbc 4445 #define MCG_C8_LOCS1_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4446 #define MCG_C8_LOCS1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4447 #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
AnnaBridge 171:3a7713b1edbc 4448 #define MCG_C8_CME1_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4449 #define MCG_C8_CME1_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4450 #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
AnnaBridge 171:3a7713b1edbc 4451 #define MCG_C8_LOCRE1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4452 #define MCG_C8_LOCRE1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4453 #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
AnnaBridge 171:3a7713b1edbc 4454
AnnaBridge 171:3a7713b1edbc 4455
AnnaBridge 171:3a7713b1edbc 4456 /*!
AnnaBridge 171:3a7713b1edbc 4457 * @}
AnnaBridge 171:3a7713b1edbc 4458 */ /* end of group MCG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4459
AnnaBridge 171:3a7713b1edbc 4460
AnnaBridge 171:3a7713b1edbc 4461 /* MCG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4462 /** Peripheral MCG base address */
AnnaBridge 171:3a7713b1edbc 4463 #define MCG_BASE (0x40064000u)
AnnaBridge 171:3a7713b1edbc 4464 /** Peripheral MCG base pointer */
AnnaBridge 171:3a7713b1edbc 4465 #define MCG ((MCG_Type *)MCG_BASE)
AnnaBridge 171:3a7713b1edbc 4466 /** Array initializer of MCG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4467 #define MCG_BASE_ADDRS { MCG_BASE }
AnnaBridge 171:3a7713b1edbc 4468 /** Array initializer of MCG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4469 #define MCG_BASE_PTRS { MCG }
AnnaBridge 171:3a7713b1edbc 4470 /** Interrupt vectors for the MCG peripheral type */
AnnaBridge 171:3a7713b1edbc 4471 #define MCG_IRQS { MCG_IRQn }
AnnaBridge 171:3a7713b1edbc 4472
AnnaBridge 171:3a7713b1edbc 4473 /*!
AnnaBridge 171:3a7713b1edbc 4474 * @}
AnnaBridge 171:3a7713b1edbc 4475 */ /* end of group MCG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4476
AnnaBridge 171:3a7713b1edbc 4477
AnnaBridge 171:3a7713b1edbc 4478 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4479 -- MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4480 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4481
AnnaBridge 171:3a7713b1edbc 4482 /*!
AnnaBridge 171:3a7713b1edbc 4483 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4484 * @{
AnnaBridge 171:3a7713b1edbc 4485 */
AnnaBridge 171:3a7713b1edbc 4486
AnnaBridge 171:3a7713b1edbc 4487 /** MCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4488 typedef struct {
AnnaBridge 171:3a7713b1edbc 4489 uint8_t RESERVED_0[8];
AnnaBridge 171:3a7713b1edbc 4490 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4491 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 4492 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 4493 uint8_t RESERVED_1[48];
AnnaBridge 171:3a7713b1edbc 4494 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 4495 } MCM_Type;
AnnaBridge 171:3a7713b1edbc 4496
AnnaBridge 171:3a7713b1edbc 4497 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4498 -- MCM Register Masks
AnnaBridge 171:3a7713b1edbc 4499 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4500
AnnaBridge 171:3a7713b1edbc 4501 /*!
AnnaBridge 171:3a7713b1edbc 4502 * @addtogroup MCM_Register_Masks MCM Register Masks
AnnaBridge 171:3a7713b1edbc 4503 * @{
AnnaBridge 171:3a7713b1edbc 4504 */
AnnaBridge 171:3a7713b1edbc 4505
AnnaBridge 171:3a7713b1edbc 4506 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
AnnaBridge 171:3a7713b1edbc 4507 #define MCM_PLASC_ASC_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4508 #define MCM_PLASC_ASC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4509 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
AnnaBridge 171:3a7713b1edbc 4510
AnnaBridge 171:3a7713b1edbc 4511 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
AnnaBridge 171:3a7713b1edbc 4512 #define MCM_PLAMC_AMC_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 4513 #define MCM_PLAMC_AMC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4514 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
AnnaBridge 171:3a7713b1edbc 4515
AnnaBridge 171:3a7713b1edbc 4516 /*! @name PLACR - Platform Control Register */
AnnaBridge 171:3a7713b1edbc 4517 #define MCM_PLACR_ARB_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4518 #define MCM_PLACR_ARB_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4519 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
AnnaBridge 171:3a7713b1edbc 4520 #define MCM_PLACR_CFCC_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 4521 #define MCM_PLACR_CFCC_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4522 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK)
AnnaBridge 171:3a7713b1edbc 4523 #define MCM_PLACR_DFCDA_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 4524 #define MCM_PLACR_DFCDA_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4525 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK)
AnnaBridge 171:3a7713b1edbc 4526 #define MCM_PLACR_DFCIC_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4527 #define MCM_PLACR_DFCIC_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4528 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK)
AnnaBridge 171:3a7713b1edbc 4529 #define MCM_PLACR_DFCC_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4530 #define MCM_PLACR_DFCC_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4531 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK)
AnnaBridge 171:3a7713b1edbc 4532 #define MCM_PLACR_EFDS_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 4533 #define MCM_PLACR_EFDS_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 4534 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK)
AnnaBridge 171:3a7713b1edbc 4535 #define MCM_PLACR_DFCS_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4536 #define MCM_PLACR_DFCS_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4537 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK)
AnnaBridge 171:3a7713b1edbc 4538 #define MCM_PLACR_ESFC_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4539 #define MCM_PLACR_ESFC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4540 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK)
AnnaBridge 171:3a7713b1edbc 4541
AnnaBridge 171:3a7713b1edbc 4542 /*! @name CPO - Compute Operation Control Register */
AnnaBridge 171:3a7713b1edbc 4543 #define MCM_CPO_CPOREQ_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4544 #define MCM_CPO_CPOREQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4545 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
AnnaBridge 171:3a7713b1edbc 4546 #define MCM_CPO_CPOACK_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4547 #define MCM_CPO_CPOACK_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4548 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
AnnaBridge 171:3a7713b1edbc 4549 #define MCM_CPO_CPOWOI_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4550 #define MCM_CPO_CPOWOI_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4551 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
AnnaBridge 171:3a7713b1edbc 4552
AnnaBridge 171:3a7713b1edbc 4553
AnnaBridge 171:3a7713b1edbc 4554 /*!
AnnaBridge 171:3a7713b1edbc 4555 * @}
AnnaBridge 171:3a7713b1edbc 4556 */ /* end of group MCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4557
AnnaBridge 171:3a7713b1edbc 4558
AnnaBridge 171:3a7713b1edbc 4559 /* MCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4560 /** Peripheral MCM base address */
AnnaBridge 171:3a7713b1edbc 4561 #define MCM_BASE (0xF0003000u)
AnnaBridge 171:3a7713b1edbc 4562 /** Peripheral MCM base pointer */
AnnaBridge 171:3a7713b1edbc 4563 #define MCM ((MCM_Type *)MCM_BASE)
AnnaBridge 171:3a7713b1edbc 4564 /** Array initializer of MCM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4565 #define MCM_BASE_ADDRS { MCM_BASE }
AnnaBridge 171:3a7713b1edbc 4566 /** Array initializer of MCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4567 #define MCM_BASE_PTRS { MCM }
AnnaBridge 171:3a7713b1edbc 4568
AnnaBridge 171:3a7713b1edbc 4569 /*!
AnnaBridge 171:3a7713b1edbc 4570 * @}
AnnaBridge 171:3a7713b1edbc 4571 */ /* end of group MCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4572
AnnaBridge 171:3a7713b1edbc 4573
AnnaBridge 171:3a7713b1edbc 4574 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4575 -- MTB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4576 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4577
AnnaBridge 171:3a7713b1edbc 4578 /*!
AnnaBridge 171:3a7713b1edbc 4579 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4580 * @{
AnnaBridge 171:3a7713b1edbc 4581 */
AnnaBridge 171:3a7713b1edbc 4582
AnnaBridge 171:3a7713b1edbc 4583 /** MTB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4584 typedef struct {
AnnaBridge 171:3a7713b1edbc 4585 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4586 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4587 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4588 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 4589 uint8_t RESERVED_0[3824];
AnnaBridge 171:3a7713b1edbc 4590 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
AnnaBridge 171:3a7713b1edbc 4591 uint8_t RESERVED_1[156];
AnnaBridge 171:3a7713b1edbc 4592 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
AnnaBridge 171:3a7713b1edbc 4593 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
AnnaBridge 171:3a7713b1edbc 4594 uint8_t RESERVED_2[8];
AnnaBridge 171:3a7713b1edbc 4595 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
AnnaBridge 171:3a7713b1edbc 4596 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
AnnaBridge 171:3a7713b1edbc 4597 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
AnnaBridge 171:3a7713b1edbc 4598 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
AnnaBridge 171:3a7713b1edbc 4599 uint8_t RESERVED_3[8];
AnnaBridge 171:3a7713b1edbc 4600 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
AnnaBridge 171:3a7713b1edbc 4601 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
AnnaBridge 171:3a7713b1edbc 4602 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
AnnaBridge 171:3a7713b1edbc 4603 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
AnnaBridge 171:3a7713b1edbc 4604 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
AnnaBridge 171:3a7713b1edbc 4605 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
AnnaBridge 171:3a7713b1edbc 4606 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
AnnaBridge 171:3a7713b1edbc 4607 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
AnnaBridge 171:3a7713b1edbc 4608 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
AnnaBridge 171:3a7713b1edbc 4609 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
AnnaBridge 171:3a7713b1edbc 4610 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 4611 } MTB_Type;
AnnaBridge 171:3a7713b1edbc 4612
AnnaBridge 171:3a7713b1edbc 4613 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4614 -- MTB Register Masks
AnnaBridge 171:3a7713b1edbc 4615 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4616
AnnaBridge 171:3a7713b1edbc 4617 /*!
AnnaBridge 171:3a7713b1edbc 4618 * @addtogroup MTB_Register_Masks MTB Register Masks
AnnaBridge 171:3a7713b1edbc 4619 * @{
AnnaBridge 171:3a7713b1edbc 4620 */
AnnaBridge 171:3a7713b1edbc 4621
AnnaBridge 171:3a7713b1edbc 4622 /*! @name POSITION - MTB Position Register */
AnnaBridge 171:3a7713b1edbc 4623 #define MTB_POSITION_WRAP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4624 #define MTB_POSITION_WRAP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4625 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK)
AnnaBridge 171:3a7713b1edbc 4626 #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U)
AnnaBridge 171:3a7713b1edbc 4627 #define MTB_POSITION_POINTER_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4628 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK)
AnnaBridge 171:3a7713b1edbc 4629
AnnaBridge 171:3a7713b1edbc 4630 /*! @name MASTER - MTB Master Register */
AnnaBridge 171:3a7713b1edbc 4631 #define MTB_MASTER_MASK_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4632 #define MTB_MASTER_MASK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4633 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK)
AnnaBridge 171:3a7713b1edbc 4634 #define MTB_MASTER_TSTARTEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4635 #define MTB_MASTER_TSTARTEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4636 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK)
AnnaBridge 171:3a7713b1edbc 4637 #define MTB_MASTER_TSTOPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4638 #define MTB_MASTER_TSTOPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4639 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK)
AnnaBridge 171:3a7713b1edbc 4640 #define MTB_MASTER_SFRWPRIV_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4641 #define MTB_MASTER_SFRWPRIV_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4642 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK)
AnnaBridge 171:3a7713b1edbc 4643 #define MTB_MASTER_RAMPRIV_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4644 #define MTB_MASTER_RAMPRIV_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4645 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK)
AnnaBridge 171:3a7713b1edbc 4646 #define MTB_MASTER_HALTREQ_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4647 #define MTB_MASTER_HALTREQ_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4648 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK)
AnnaBridge 171:3a7713b1edbc 4649 #define MTB_MASTER_EN_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4650 #define MTB_MASTER_EN_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4651 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK)
AnnaBridge 171:3a7713b1edbc 4652
AnnaBridge 171:3a7713b1edbc 4653 /*! @name FLOW - MTB Flow Register */
AnnaBridge 171:3a7713b1edbc 4654 #define MTB_FLOW_AUTOSTOP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4655 #define MTB_FLOW_AUTOSTOP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4656 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK)
AnnaBridge 171:3a7713b1edbc 4657 #define MTB_FLOW_AUTOHALT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4658 #define MTB_FLOW_AUTOHALT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4659 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK)
AnnaBridge 171:3a7713b1edbc 4660 #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U)
AnnaBridge 171:3a7713b1edbc 4661 #define MTB_FLOW_WATERMARK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4662 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK)
AnnaBridge 171:3a7713b1edbc 4663
AnnaBridge 171:3a7713b1edbc 4664 /*! @name BASE - MTB Base Register */
AnnaBridge 171:3a7713b1edbc 4665 #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4666 #define MTB_BASE_BASEADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4667 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK)
AnnaBridge 171:3a7713b1edbc 4668
AnnaBridge 171:3a7713b1edbc 4669 /*! @name MODECTRL - Integration Mode Control Register */
AnnaBridge 171:3a7713b1edbc 4670 #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4671 #define MTB_MODECTRL_MODECTRL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4672 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK)
AnnaBridge 171:3a7713b1edbc 4673
AnnaBridge 171:3a7713b1edbc 4674 /*! @name TAGSET - Claim TAG Set Register */
AnnaBridge 171:3a7713b1edbc 4675 #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4676 #define MTB_TAGSET_TAGSET_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4677 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK)
AnnaBridge 171:3a7713b1edbc 4678
AnnaBridge 171:3a7713b1edbc 4679 /*! @name TAGCLEAR - Claim TAG Clear Register */
AnnaBridge 171:3a7713b1edbc 4680 #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4681 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4682 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK)
AnnaBridge 171:3a7713b1edbc 4683
AnnaBridge 171:3a7713b1edbc 4684 /*! @name LOCKACCESS - Lock Access Register */
AnnaBridge 171:3a7713b1edbc 4685 #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4686 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4687 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK)
AnnaBridge 171:3a7713b1edbc 4688
AnnaBridge 171:3a7713b1edbc 4689 /*! @name LOCKSTAT - Lock Status Register */
AnnaBridge 171:3a7713b1edbc 4690 #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4691 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4692 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK)
AnnaBridge 171:3a7713b1edbc 4693
AnnaBridge 171:3a7713b1edbc 4694 /*! @name AUTHSTAT - Authentication Status Register */
AnnaBridge 171:3a7713b1edbc 4695 #define MTB_AUTHSTAT_BIT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4696 #define MTB_AUTHSTAT_BIT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4697 #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK)
AnnaBridge 171:3a7713b1edbc 4698 #define MTB_AUTHSTAT_BIT1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4699 #define MTB_AUTHSTAT_BIT1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4700 #define MTB_AUTHSTAT_BIT1(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT1_SHIFT)) & MTB_AUTHSTAT_BIT1_MASK)
AnnaBridge 171:3a7713b1edbc 4701 #define MTB_AUTHSTAT_BIT2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4702 #define MTB_AUTHSTAT_BIT2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4703 #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK)
AnnaBridge 171:3a7713b1edbc 4704 #define MTB_AUTHSTAT_BIT3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4705 #define MTB_AUTHSTAT_BIT3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4706 #define MTB_AUTHSTAT_BIT3(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT3_SHIFT)) & MTB_AUTHSTAT_BIT3_MASK)
AnnaBridge 171:3a7713b1edbc 4707
AnnaBridge 171:3a7713b1edbc 4708 /*! @name DEVICEARCH - Device Architecture Register */
AnnaBridge 171:3a7713b1edbc 4709 #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4710 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4711 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK)
AnnaBridge 171:3a7713b1edbc 4712
AnnaBridge 171:3a7713b1edbc 4713 /*! @name DEVICECFG - Device Configuration Register */
AnnaBridge 171:3a7713b1edbc 4714 #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4715 #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4716 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK)
AnnaBridge 171:3a7713b1edbc 4717
AnnaBridge 171:3a7713b1edbc 4718 /*! @name DEVICETYPID - Device Type Identifier Register */
AnnaBridge 171:3a7713b1edbc 4719 #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4720 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4721 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK)
AnnaBridge 171:3a7713b1edbc 4722
AnnaBridge 171:3a7713b1edbc 4723 /*! @name PERIPHID4 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4724 #define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4725 #define MTB_PERIPHID4_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4726 #define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4727
AnnaBridge 171:3a7713b1edbc 4728 /*! @name PERIPHID5 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4729 #define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4730 #define MTB_PERIPHID5_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4731 #define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4732
AnnaBridge 171:3a7713b1edbc 4733 /*! @name PERIPHID6 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4734 #define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4735 #define MTB_PERIPHID6_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4736 #define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4737
AnnaBridge 171:3a7713b1edbc 4738 /*! @name PERIPHID7 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4739 #define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4740 #define MTB_PERIPHID7_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4741 #define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4742
AnnaBridge 171:3a7713b1edbc 4743 /*! @name PERIPHID0 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4744 #define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4745 #define MTB_PERIPHID0_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4746 #define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4747
AnnaBridge 171:3a7713b1edbc 4748 /*! @name PERIPHID1 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4749 #define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4750 #define MTB_PERIPHID1_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4751 #define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4752
AnnaBridge 171:3a7713b1edbc 4753 /*! @name PERIPHID2 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4754 #define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4755 #define MTB_PERIPHID2_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4756 #define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4757
AnnaBridge 171:3a7713b1edbc 4758 /*! @name PERIPHID3 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4759 #define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4760 #define MTB_PERIPHID3_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4761 #define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4762
AnnaBridge 171:3a7713b1edbc 4763 /*! @name COMPID - Component ID Register */
AnnaBridge 171:3a7713b1edbc 4764 #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4765 #define MTB_COMPID_COMPID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4766 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK)
AnnaBridge 171:3a7713b1edbc 4767
AnnaBridge 171:3a7713b1edbc 4768 /* The count of MTB_COMPID */
AnnaBridge 171:3a7713b1edbc 4769 #define MTB_COMPID_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 4770
AnnaBridge 171:3a7713b1edbc 4771
AnnaBridge 171:3a7713b1edbc 4772 /*!
AnnaBridge 171:3a7713b1edbc 4773 * @}
AnnaBridge 171:3a7713b1edbc 4774 */ /* end of group MTB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4775
AnnaBridge 171:3a7713b1edbc 4776
AnnaBridge 171:3a7713b1edbc 4777 /* MTB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4778 /** Peripheral MTB base address */
AnnaBridge 171:3a7713b1edbc 4779 #define MTB_BASE (0xF0000000u)
AnnaBridge 171:3a7713b1edbc 4780 /** Peripheral MTB base pointer */
AnnaBridge 171:3a7713b1edbc 4781 #define MTB ((MTB_Type *)MTB_BASE)
AnnaBridge 171:3a7713b1edbc 4782 /** Array initializer of MTB peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4783 #define MTB_BASE_ADDRS { MTB_BASE }
AnnaBridge 171:3a7713b1edbc 4784 /** Array initializer of MTB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4785 #define MTB_BASE_PTRS { MTB }
AnnaBridge 171:3a7713b1edbc 4786
AnnaBridge 171:3a7713b1edbc 4787 /*!
AnnaBridge 171:3a7713b1edbc 4788 * @}
AnnaBridge 171:3a7713b1edbc 4789 */ /* end of group MTB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4790
AnnaBridge 171:3a7713b1edbc 4791
AnnaBridge 171:3a7713b1edbc 4792 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4793 -- MTBDWT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4794 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4795
AnnaBridge 171:3a7713b1edbc 4796 /*!
AnnaBridge 171:3a7713b1edbc 4797 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4798 * @{
AnnaBridge 171:3a7713b1edbc 4799 */
AnnaBridge 171:3a7713b1edbc 4800
AnnaBridge 171:3a7713b1edbc 4801 /** MTBDWT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4802 typedef struct {
AnnaBridge 171:3a7713b1edbc 4803 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4804 uint8_t RESERVED_0[28];
AnnaBridge 171:3a7713b1edbc 4805 struct { /* offset: 0x20, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 4806 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 4807 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 4808 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 4809 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 4810 } COMPARATOR[2];
AnnaBridge 171:3a7713b1edbc 4811 uint8_t RESERVED_1[448];
AnnaBridge 171:3a7713b1edbc 4812 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
AnnaBridge 171:3a7713b1edbc 4813 uint8_t RESERVED_2[3524];
AnnaBridge 171:3a7713b1edbc 4814 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
AnnaBridge 171:3a7713b1edbc 4815 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
AnnaBridge 171:3a7713b1edbc 4816 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
AnnaBridge 171:3a7713b1edbc 4817 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
AnnaBridge 171:3a7713b1edbc 4818 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
AnnaBridge 171:3a7713b1edbc 4819 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
AnnaBridge 171:3a7713b1edbc 4820 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
AnnaBridge 171:3a7713b1edbc 4821 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
AnnaBridge 171:3a7713b1edbc 4822 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
AnnaBridge 171:3a7713b1edbc 4823 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
AnnaBridge 171:3a7713b1edbc 4824 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 4825 } MTBDWT_Type;
AnnaBridge 171:3a7713b1edbc 4826
AnnaBridge 171:3a7713b1edbc 4827 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4828 -- MTBDWT Register Masks
AnnaBridge 171:3a7713b1edbc 4829 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4830
AnnaBridge 171:3a7713b1edbc 4831 /*!
AnnaBridge 171:3a7713b1edbc 4832 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
AnnaBridge 171:3a7713b1edbc 4833 * @{
AnnaBridge 171:3a7713b1edbc 4834 */
AnnaBridge 171:3a7713b1edbc 4835
AnnaBridge 171:3a7713b1edbc 4836 /*! @name CTRL - MTB DWT Control Register */
AnnaBridge 171:3a7713b1edbc 4837 #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4838 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4839 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK)
AnnaBridge 171:3a7713b1edbc 4840 #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 4841 #define MTBDWT_CTRL_NUMCMP_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4842 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK)
AnnaBridge 171:3a7713b1edbc 4843
AnnaBridge 171:3a7713b1edbc 4844 /*! @name COMP - MTB_DWT Comparator Register */
AnnaBridge 171:3a7713b1edbc 4845 #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4846 #define MTBDWT_COMP_COMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4847 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK)
AnnaBridge 171:3a7713b1edbc 4848
AnnaBridge 171:3a7713b1edbc 4849 /* The count of MTBDWT_COMP */
AnnaBridge 171:3a7713b1edbc 4850 #define MTBDWT_COMP_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 4851
AnnaBridge 171:3a7713b1edbc 4852 /*! @name MASK - MTB_DWT Comparator Mask Register */
AnnaBridge 171:3a7713b1edbc 4853 #define MTBDWT_MASK_MASK_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 4854 #define MTBDWT_MASK_MASK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4855 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK)
AnnaBridge 171:3a7713b1edbc 4856
AnnaBridge 171:3a7713b1edbc 4857 /* The count of MTBDWT_MASK */
AnnaBridge 171:3a7713b1edbc 4858 #define MTBDWT_MASK_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 4859
AnnaBridge 171:3a7713b1edbc 4860 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */
AnnaBridge 171:3a7713b1edbc 4861 #define MTBDWT_FCT_FUNCTION_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4862 #define MTBDWT_FCT_FUNCTION_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4863 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK)
AnnaBridge 171:3a7713b1edbc 4864 #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4865 #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4866 #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK)
AnnaBridge 171:3a7713b1edbc 4867 #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U)
AnnaBridge 171:3a7713b1edbc 4868 #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4869 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 4870 #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 4871 #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4872 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK)
AnnaBridge 171:3a7713b1edbc 4873 #define MTBDWT_FCT_MATCHED_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4874 #define MTBDWT_FCT_MATCHED_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4875 #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK)
AnnaBridge 171:3a7713b1edbc 4876
AnnaBridge 171:3a7713b1edbc 4877 /* The count of MTBDWT_FCT */
AnnaBridge 171:3a7713b1edbc 4878 #define MTBDWT_FCT_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 4879
AnnaBridge 171:3a7713b1edbc 4880 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */
AnnaBridge 171:3a7713b1edbc 4881 #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4882 #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4883 #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK)
AnnaBridge 171:3a7713b1edbc 4884 #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4885 #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4886 #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK)
AnnaBridge 171:3a7713b1edbc 4887 #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 4888 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4889 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK)
AnnaBridge 171:3a7713b1edbc 4890
AnnaBridge 171:3a7713b1edbc 4891 /*! @name DEVICECFG - Device Configuration Register */
AnnaBridge 171:3a7713b1edbc 4892 #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4893 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4894 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK)
AnnaBridge 171:3a7713b1edbc 4895
AnnaBridge 171:3a7713b1edbc 4896 /*! @name DEVICETYPID - Device Type Identifier Register */
AnnaBridge 171:3a7713b1edbc 4897 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4898 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4899 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
AnnaBridge 171:3a7713b1edbc 4900
AnnaBridge 171:3a7713b1edbc 4901 /*! @name PERIPHID4 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4902 #define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4903 #define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4904 #define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4905
AnnaBridge 171:3a7713b1edbc 4906 /*! @name PERIPHID5 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4907 #define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4908 #define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4909 #define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4910
AnnaBridge 171:3a7713b1edbc 4911 /*! @name PERIPHID6 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4912 #define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4913 #define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4914 #define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4915
AnnaBridge 171:3a7713b1edbc 4916 /*! @name PERIPHID7 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4917 #define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4918 #define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4919 #define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4920
AnnaBridge 171:3a7713b1edbc 4921 /*! @name PERIPHID0 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4922 #define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4923 #define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4924 #define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4925
AnnaBridge 171:3a7713b1edbc 4926 /*! @name PERIPHID1 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4927 #define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4928 #define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4929 #define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4930
AnnaBridge 171:3a7713b1edbc 4931 /*! @name PERIPHID2 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4932 #define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4933 #define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4934 #define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4935
AnnaBridge 171:3a7713b1edbc 4936 /*! @name PERIPHID3 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 4937 #define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4938 #define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4939 #define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 4940
AnnaBridge 171:3a7713b1edbc 4941 /*! @name COMPID - Component ID Register */
AnnaBridge 171:3a7713b1edbc 4942 #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4943 #define MTBDWT_COMPID_COMPID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4944 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK)
AnnaBridge 171:3a7713b1edbc 4945
AnnaBridge 171:3a7713b1edbc 4946 /* The count of MTBDWT_COMPID */
AnnaBridge 171:3a7713b1edbc 4947 #define MTBDWT_COMPID_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 4948
AnnaBridge 171:3a7713b1edbc 4949
AnnaBridge 171:3a7713b1edbc 4950 /*!
AnnaBridge 171:3a7713b1edbc 4951 * @}
AnnaBridge 171:3a7713b1edbc 4952 */ /* end of group MTBDWT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4953
AnnaBridge 171:3a7713b1edbc 4954
AnnaBridge 171:3a7713b1edbc 4955 /* MTBDWT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4956 /** Peripheral MTBDWT base address */
AnnaBridge 171:3a7713b1edbc 4957 #define MTBDWT_BASE (0xF0001000u)
AnnaBridge 171:3a7713b1edbc 4958 /** Peripheral MTBDWT base pointer */
AnnaBridge 171:3a7713b1edbc 4959 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
AnnaBridge 171:3a7713b1edbc 4960 /** Array initializer of MTBDWT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4961 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
AnnaBridge 171:3a7713b1edbc 4962 /** Array initializer of MTBDWT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4963 #define MTBDWT_BASE_PTRS { MTBDWT }
AnnaBridge 171:3a7713b1edbc 4964
AnnaBridge 171:3a7713b1edbc 4965 /*!
AnnaBridge 171:3a7713b1edbc 4966 * @}
AnnaBridge 171:3a7713b1edbc 4967 */ /* end of group MTBDWT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4968
AnnaBridge 171:3a7713b1edbc 4969
AnnaBridge 171:3a7713b1edbc 4970 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4971 -- NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4972 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4973
AnnaBridge 171:3a7713b1edbc 4974 /*!
AnnaBridge 171:3a7713b1edbc 4975 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4976 * @{
AnnaBridge 171:3a7713b1edbc 4977 */
AnnaBridge 171:3a7713b1edbc 4978
AnnaBridge 171:3a7713b1edbc 4979 /** NV - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4980 typedef struct {
AnnaBridge 171:3a7713b1edbc 4981 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 4982 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 4983 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 4984 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 4985 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4986 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 4987 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 4988 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 4989 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4990 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 4991 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 4992 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 4993 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 4994 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 4995 } NV_Type;
AnnaBridge 171:3a7713b1edbc 4996
AnnaBridge 171:3a7713b1edbc 4997 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4998 -- NV Register Masks
AnnaBridge 171:3a7713b1edbc 4999 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5000
AnnaBridge 171:3a7713b1edbc 5001 /*!
AnnaBridge 171:3a7713b1edbc 5002 * @addtogroup NV_Register_Masks NV Register Masks
AnnaBridge 171:3a7713b1edbc 5003 * @{
AnnaBridge 171:3a7713b1edbc 5004 */
AnnaBridge 171:3a7713b1edbc 5005
AnnaBridge 171:3a7713b1edbc 5006 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
AnnaBridge 171:3a7713b1edbc 5007 #define NV_BACKKEY3_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5008 #define NV_BACKKEY3_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5009 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5010
AnnaBridge 171:3a7713b1edbc 5011 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
AnnaBridge 171:3a7713b1edbc 5012 #define NV_BACKKEY2_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5013 #define NV_BACKKEY2_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5014 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5015
AnnaBridge 171:3a7713b1edbc 5016 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
AnnaBridge 171:3a7713b1edbc 5017 #define NV_BACKKEY1_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5018 #define NV_BACKKEY1_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5019 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5020
AnnaBridge 171:3a7713b1edbc 5021 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
AnnaBridge 171:3a7713b1edbc 5022 #define NV_BACKKEY0_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5023 #define NV_BACKKEY0_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5024 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5025
AnnaBridge 171:3a7713b1edbc 5026 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
AnnaBridge 171:3a7713b1edbc 5027 #define NV_BACKKEY7_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5028 #define NV_BACKKEY7_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5029 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5030
AnnaBridge 171:3a7713b1edbc 5031 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
AnnaBridge 171:3a7713b1edbc 5032 #define NV_BACKKEY6_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5033 #define NV_BACKKEY6_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5034 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5035
AnnaBridge 171:3a7713b1edbc 5036 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
AnnaBridge 171:3a7713b1edbc 5037 #define NV_BACKKEY5_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5038 #define NV_BACKKEY5_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5039 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5040
AnnaBridge 171:3a7713b1edbc 5041 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
AnnaBridge 171:3a7713b1edbc 5042 #define NV_BACKKEY4_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5043 #define NV_BACKKEY4_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5044 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 5045
AnnaBridge 171:3a7713b1edbc 5046 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
AnnaBridge 171:3a7713b1edbc 5047 #define NV_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5048 #define NV_FPROT3_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5049 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 5050
AnnaBridge 171:3a7713b1edbc 5051 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
AnnaBridge 171:3a7713b1edbc 5052 #define NV_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5053 #define NV_FPROT2_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5054 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 5055
AnnaBridge 171:3a7713b1edbc 5056 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
AnnaBridge 171:3a7713b1edbc 5057 #define NV_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5058 #define NV_FPROT1_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5059 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 5060
AnnaBridge 171:3a7713b1edbc 5061 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
AnnaBridge 171:3a7713b1edbc 5062 #define NV_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5063 #define NV_FPROT0_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5064 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 5065
AnnaBridge 171:3a7713b1edbc 5066 /*! @name FSEC - Non-volatile Flash Security Register */
AnnaBridge 171:3a7713b1edbc 5067 #define NV_FSEC_SEC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 5068 #define NV_FSEC_SEC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5069 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 5070 #define NV_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 5071 #define NV_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5072 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 5073 #define NV_FSEC_MEEN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 5074 #define NV_FSEC_MEEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5075 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 5076 #define NV_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 5077 #define NV_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5078 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 5079
AnnaBridge 171:3a7713b1edbc 5080 /*! @name FOPT - Non-volatile Flash Option Register */
AnnaBridge 171:3a7713b1edbc 5081 #define NV_FOPT_LPBOOT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5082 #define NV_FOPT_LPBOOT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5083 #define NV_FOPT_LPBOOT0(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT0_SHIFT)) & NV_FOPT_LPBOOT0_MASK)
AnnaBridge 171:3a7713b1edbc 5084 #define NV_FOPT_NMI_DIS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5085 #define NV_FOPT_NMI_DIS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5086 #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 5087 #define NV_FOPT_RESET_PIN_CFG_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5088 #define NV_FOPT_RESET_PIN_CFG_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5089 #define NV_FOPT_RESET_PIN_CFG(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_RESET_PIN_CFG_SHIFT)) & NV_FOPT_RESET_PIN_CFG_MASK)
AnnaBridge 171:3a7713b1edbc 5090 #define NV_FOPT_LPBOOT1_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5091 #define NV_FOPT_LPBOOT1_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5092 #define NV_FOPT_LPBOOT1(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT1_SHIFT)) & NV_FOPT_LPBOOT1_MASK)
AnnaBridge 171:3a7713b1edbc 5093 #define NV_FOPT_FAST_INIT_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5094 #define NV_FOPT_FAST_INIT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5095 #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 5096
AnnaBridge 171:3a7713b1edbc 5097
AnnaBridge 171:3a7713b1edbc 5098 /*!
AnnaBridge 171:3a7713b1edbc 5099 * @}
AnnaBridge 171:3a7713b1edbc 5100 */ /* end of group NV_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5101
AnnaBridge 171:3a7713b1edbc 5102
AnnaBridge 171:3a7713b1edbc 5103 /* NV - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5104 /** Peripheral FTFA_FlashConfig base address */
AnnaBridge 171:3a7713b1edbc 5105 #define FTFA_FlashConfig_BASE (0x400u)
AnnaBridge 171:3a7713b1edbc 5106 /** Peripheral FTFA_FlashConfig base pointer */
AnnaBridge 171:3a7713b1edbc 5107 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
AnnaBridge 171:3a7713b1edbc 5108 /** Array initializer of NV peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5109 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
AnnaBridge 171:3a7713b1edbc 5110 /** Array initializer of NV peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5111 #define NV_BASE_PTRS { FTFA_FlashConfig }
AnnaBridge 171:3a7713b1edbc 5112
AnnaBridge 171:3a7713b1edbc 5113 /*!
AnnaBridge 171:3a7713b1edbc 5114 * @}
AnnaBridge 171:3a7713b1edbc 5115 */ /* end of group NV_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5116
AnnaBridge 171:3a7713b1edbc 5117
AnnaBridge 171:3a7713b1edbc 5118 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5119 -- PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5120 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5121
AnnaBridge 171:3a7713b1edbc 5122 /*!
AnnaBridge 171:3a7713b1edbc 5123 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5124 * @{
AnnaBridge 171:3a7713b1edbc 5125 */
AnnaBridge 171:3a7713b1edbc 5126
AnnaBridge 171:3a7713b1edbc 5127 /** PIT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5128 typedef struct {
AnnaBridge 171:3a7713b1edbc 5129 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5130 uint8_t RESERVED_0[220];
AnnaBridge 171:3a7713b1edbc 5131 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
AnnaBridge 171:3a7713b1edbc 5132 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
AnnaBridge 171:3a7713b1edbc 5133 uint8_t RESERVED_1[24];
AnnaBridge 171:3a7713b1edbc 5134 struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 5135 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 5136 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 5137 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 5138 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 5139 } CHANNEL[2];
AnnaBridge 171:3a7713b1edbc 5140 } PIT_Type;
AnnaBridge 171:3a7713b1edbc 5141
AnnaBridge 171:3a7713b1edbc 5142 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5143 -- PIT Register Masks
AnnaBridge 171:3a7713b1edbc 5144 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5145
AnnaBridge 171:3a7713b1edbc 5146 /*!
AnnaBridge 171:3a7713b1edbc 5147 * @addtogroup PIT_Register_Masks PIT Register Masks
AnnaBridge 171:3a7713b1edbc 5148 * @{
AnnaBridge 171:3a7713b1edbc 5149 */
AnnaBridge 171:3a7713b1edbc 5150
AnnaBridge 171:3a7713b1edbc 5151 /*! @name MCR - PIT Module Control Register */
AnnaBridge 171:3a7713b1edbc 5152 #define PIT_MCR_FRZ_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5153 #define PIT_MCR_FRZ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5154 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
AnnaBridge 171:3a7713b1edbc 5155 #define PIT_MCR_MDIS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5156 #define PIT_MCR_MDIS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5157 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
AnnaBridge 171:3a7713b1edbc 5158
AnnaBridge 171:3a7713b1edbc 5159 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */
AnnaBridge 171:3a7713b1edbc 5160 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5161 #define PIT_LTMR64H_LTH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5162 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
AnnaBridge 171:3a7713b1edbc 5163
AnnaBridge 171:3a7713b1edbc 5164 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */
AnnaBridge 171:3a7713b1edbc 5165 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5166 #define PIT_LTMR64L_LTL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5167 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
AnnaBridge 171:3a7713b1edbc 5168
AnnaBridge 171:3a7713b1edbc 5169 /*! @name LDVAL - Timer Load Value Register */
AnnaBridge 171:3a7713b1edbc 5170 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5171 #define PIT_LDVAL_TSV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5172 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
AnnaBridge 171:3a7713b1edbc 5173
AnnaBridge 171:3a7713b1edbc 5174 /* The count of PIT_LDVAL */
AnnaBridge 171:3a7713b1edbc 5175 #define PIT_LDVAL_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 5176
AnnaBridge 171:3a7713b1edbc 5177 /*! @name CVAL - Current Timer Value Register */
AnnaBridge 171:3a7713b1edbc 5178 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5179 #define PIT_CVAL_TVL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5180 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
AnnaBridge 171:3a7713b1edbc 5181
AnnaBridge 171:3a7713b1edbc 5182 /* The count of PIT_CVAL */
AnnaBridge 171:3a7713b1edbc 5183 #define PIT_CVAL_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 5184
AnnaBridge 171:3a7713b1edbc 5185 /*! @name TCTRL - Timer Control Register */
AnnaBridge 171:3a7713b1edbc 5186 #define PIT_TCTRL_TEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5187 #define PIT_TCTRL_TEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5188 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
AnnaBridge 171:3a7713b1edbc 5189 #define PIT_TCTRL_TIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5190 #define PIT_TCTRL_TIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5191 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 5192 #define PIT_TCTRL_CHN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5193 #define PIT_TCTRL_CHN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5194 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
AnnaBridge 171:3a7713b1edbc 5195
AnnaBridge 171:3a7713b1edbc 5196 /* The count of PIT_TCTRL */
AnnaBridge 171:3a7713b1edbc 5197 #define PIT_TCTRL_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 5198
AnnaBridge 171:3a7713b1edbc 5199 /*! @name TFLG - Timer Flag Register */
AnnaBridge 171:3a7713b1edbc 5200 #define PIT_TFLG_TIF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5201 #define PIT_TFLG_TIF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5202 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
AnnaBridge 171:3a7713b1edbc 5203
AnnaBridge 171:3a7713b1edbc 5204 /* The count of PIT_TFLG */
AnnaBridge 171:3a7713b1edbc 5205 #define PIT_TFLG_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 5206
AnnaBridge 171:3a7713b1edbc 5207
AnnaBridge 171:3a7713b1edbc 5208 /*!
AnnaBridge 171:3a7713b1edbc 5209 * @}
AnnaBridge 171:3a7713b1edbc 5210 */ /* end of group PIT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5211
AnnaBridge 171:3a7713b1edbc 5212
AnnaBridge 171:3a7713b1edbc 5213 /* PIT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5214 /** Peripheral PIT base address */
AnnaBridge 171:3a7713b1edbc 5215 #define PIT_BASE (0x40037000u)
AnnaBridge 171:3a7713b1edbc 5216 /** Peripheral PIT base pointer */
AnnaBridge 171:3a7713b1edbc 5217 #define PIT ((PIT_Type *)PIT_BASE)
AnnaBridge 171:3a7713b1edbc 5218 /** Array initializer of PIT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5219 #define PIT_BASE_ADDRS { PIT_BASE }
AnnaBridge 171:3a7713b1edbc 5220 /** Array initializer of PIT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5221 #define PIT_BASE_PTRS { PIT }
AnnaBridge 171:3a7713b1edbc 5222 /** Interrupt vectors for the PIT peripheral type */
AnnaBridge 171:3a7713b1edbc 5223 #define PIT_IRQS { PIT_IRQn, PIT_IRQn }
AnnaBridge 171:3a7713b1edbc 5224
AnnaBridge 171:3a7713b1edbc 5225 /*!
AnnaBridge 171:3a7713b1edbc 5226 * @}
AnnaBridge 171:3a7713b1edbc 5227 */ /* end of group PIT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5228
AnnaBridge 171:3a7713b1edbc 5229
AnnaBridge 171:3a7713b1edbc 5230 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5231 -- PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5232 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5233
AnnaBridge 171:3a7713b1edbc 5234 /*!
AnnaBridge 171:3a7713b1edbc 5235 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5236 * @{
AnnaBridge 171:3a7713b1edbc 5237 */
AnnaBridge 171:3a7713b1edbc 5238
AnnaBridge 171:3a7713b1edbc 5239 /** PMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5240 typedef struct {
AnnaBridge 171:3a7713b1edbc 5241 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5242 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 5243 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 5244 } PMC_Type;
AnnaBridge 171:3a7713b1edbc 5245
AnnaBridge 171:3a7713b1edbc 5246 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5247 -- PMC Register Masks
AnnaBridge 171:3a7713b1edbc 5248 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5249
AnnaBridge 171:3a7713b1edbc 5250 /*!
AnnaBridge 171:3a7713b1edbc 5251 * @addtogroup PMC_Register_Masks PMC Register Masks
AnnaBridge 171:3a7713b1edbc 5252 * @{
AnnaBridge 171:3a7713b1edbc 5253 */
AnnaBridge 171:3a7713b1edbc 5254
AnnaBridge 171:3a7713b1edbc 5255 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
AnnaBridge 171:3a7713b1edbc 5256 #define PMC_LVDSC1_LVDV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 5257 #define PMC_LVDSC1_LVDV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5258 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
AnnaBridge 171:3a7713b1edbc 5259 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5260 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5261 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
AnnaBridge 171:3a7713b1edbc 5262 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5263 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5264 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
AnnaBridge 171:3a7713b1edbc 5265 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5266 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5267 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
AnnaBridge 171:3a7713b1edbc 5268 #define PMC_LVDSC1_LVDF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5269 #define PMC_LVDSC1_LVDF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5270 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
AnnaBridge 171:3a7713b1edbc 5271
AnnaBridge 171:3a7713b1edbc 5272 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
AnnaBridge 171:3a7713b1edbc 5273 #define PMC_LVDSC2_LVWV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 5274 #define PMC_LVDSC2_LVWV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5275 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
AnnaBridge 171:3a7713b1edbc 5276 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5277 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5278 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
AnnaBridge 171:3a7713b1edbc 5279 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5280 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5281 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
AnnaBridge 171:3a7713b1edbc 5282 #define PMC_LVDSC2_LVWF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5283 #define PMC_LVDSC2_LVWF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5284 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
AnnaBridge 171:3a7713b1edbc 5285
AnnaBridge 171:3a7713b1edbc 5286 /*! @name REGSC - Regulator Status And Control register */
AnnaBridge 171:3a7713b1edbc 5287 #define PMC_REGSC_BGBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5288 #define PMC_REGSC_BGBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5289 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
AnnaBridge 171:3a7713b1edbc 5290 #define PMC_REGSC_REGONS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5291 #define PMC_REGSC_REGONS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5292 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
AnnaBridge 171:3a7713b1edbc 5293 #define PMC_REGSC_ACKISO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5294 #define PMC_REGSC_ACKISO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5295 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
AnnaBridge 171:3a7713b1edbc 5296 #define PMC_REGSC_VLPO_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5297 #define PMC_REGSC_VLPO_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5298 #define PMC_REGSC_VLPO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_VLPO_SHIFT)) & PMC_REGSC_VLPO_MASK)
AnnaBridge 171:3a7713b1edbc 5299
AnnaBridge 171:3a7713b1edbc 5300
AnnaBridge 171:3a7713b1edbc 5301 /*!
AnnaBridge 171:3a7713b1edbc 5302 * @}
AnnaBridge 171:3a7713b1edbc 5303 */ /* end of group PMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5304
AnnaBridge 171:3a7713b1edbc 5305
AnnaBridge 171:3a7713b1edbc 5306 /* PMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5307 /** Peripheral PMC base address */
AnnaBridge 171:3a7713b1edbc 5308 #define PMC_BASE (0x4007D000u)
AnnaBridge 171:3a7713b1edbc 5309 /** Peripheral PMC base pointer */
AnnaBridge 171:3a7713b1edbc 5310 #define PMC ((PMC_Type *)PMC_BASE)
AnnaBridge 171:3a7713b1edbc 5311 /** Array initializer of PMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5312 #define PMC_BASE_ADDRS { PMC_BASE }
AnnaBridge 171:3a7713b1edbc 5313 /** Array initializer of PMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5314 #define PMC_BASE_PTRS { PMC }
AnnaBridge 171:3a7713b1edbc 5315 /** Interrupt vectors for the PMC peripheral type */
AnnaBridge 171:3a7713b1edbc 5316 #define PMC_IRQS { LVD_LVW_DCDC_IRQn }
AnnaBridge 171:3a7713b1edbc 5317
AnnaBridge 171:3a7713b1edbc 5318 /*!
AnnaBridge 171:3a7713b1edbc 5319 * @}
AnnaBridge 171:3a7713b1edbc 5320 */ /* end of group PMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5321
AnnaBridge 171:3a7713b1edbc 5322
AnnaBridge 171:3a7713b1edbc 5323 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5324 -- PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5325 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5326
AnnaBridge 171:3a7713b1edbc 5327 /*!
AnnaBridge 171:3a7713b1edbc 5328 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5329 * @{
AnnaBridge 171:3a7713b1edbc 5330 */
AnnaBridge 171:3a7713b1edbc 5331
AnnaBridge 171:3a7713b1edbc 5332 /** PORT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5333 typedef struct {
AnnaBridge 171:3a7713b1edbc 5334 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5335 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 5336 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 5337 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 5338 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 5339 } PORT_Type;
AnnaBridge 171:3a7713b1edbc 5340
AnnaBridge 171:3a7713b1edbc 5341 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5342 -- PORT Register Masks
AnnaBridge 171:3a7713b1edbc 5343 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5344
AnnaBridge 171:3a7713b1edbc 5345 /*!
AnnaBridge 171:3a7713b1edbc 5346 * @addtogroup PORT_Register_Masks PORT Register Masks
AnnaBridge 171:3a7713b1edbc 5347 * @{
AnnaBridge 171:3a7713b1edbc 5348 */
AnnaBridge 171:3a7713b1edbc 5349
AnnaBridge 171:3a7713b1edbc 5350 /*! @name PCR - Pin Control Register n */
AnnaBridge 171:3a7713b1edbc 5351 #define PORT_PCR_PS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5352 #define PORT_PCR_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5353 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
AnnaBridge 171:3a7713b1edbc 5354 #define PORT_PCR_PE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5355 #define PORT_PCR_PE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5356 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
AnnaBridge 171:3a7713b1edbc 5357 #define PORT_PCR_SRE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5358 #define PORT_PCR_SRE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5359 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
AnnaBridge 171:3a7713b1edbc 5360 #define PORT_PCR_PFE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5361 #define PORT_PCR_PFE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5362 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
AnnaBridge 171:3a7713b1edbc 5363 #define PORT_PCR_DSE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5364 #define PORT_PCR_DSE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5365 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
AnnaBridge 171:3a7713b1edbc 5366 #define PORT_PCR_MUX_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 5367 #define PORT_PCR_MUX_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5368 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
AnnaBridge 171:3a7713b1edbc 5369 #define PORT_PCR_IRQC_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 5370 #define PORT_PCR_IRQC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5371 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
AnnaBridge 171:3a7713b1edbc 5372 #define PORT_PCR_ISF_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 5373 #define PORT_PCR_ISF_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5374 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
AnnaBridge 171:3a7713b1edbc 5375
AnnaBridge 171:3a7713b1edbc 5376 /* The count of PORT_PCR */
AnnaBridge 171:3a7713b1edbc 5377 #define PORT_PCR_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 5378
AnnaBridge 171:3a7713b1edbc 5379 /*! @name GPCLR - Global Pin Control Low Register */
AnnaBridge 171:3a7713b1edbc 5380 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5381 #define PORT_GPCLR_GPWD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5382 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 5383 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 5384 #define PORT_GPCLR_GPWE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5385 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 5386
AnnaBridge 171:3a7713b1edbc 5387 /*! @name GPCHR - Global Pin Control High Register */
AnnaBridge 171:3a7713b1edbc 5388 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5389 #define PORT_GPCHR_GPWD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5390 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 5391 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 5392 #define PORT_GPCHR_GPWE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5393 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 5394
AnnaBridge 171:3a7713b1edbc 5395 /*! @name ISFR - Interrupt Status Flag Register */
AnnaBridge 171:3a7713b1edbc 5396 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5397 #define PORT_ISFR_ISF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5398 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
AnnaBridge 171:3a7713b1edbc 5399
AnnaBridge 171:3a7713b1edbc 5400
AnnaBridge 171:3a7713b1edbc 5401 /*!
AnnaBridge 171:3a7713b1edbc 5402 * @}
AnnaBridge 171:3a7713b1edbc 5403 */ /* end of group PORT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5404
AnnaBridge 171:3a7713b1edbc 5405
AnnaBridge 171:3a7713b1edbc 5406 /* PORT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5407 /** Peripheral PORTA base address */
AnnaBridge 171:3a7713b1edbc 5408 #define PORTA_BASE (0x40049000u)
AnnaBridge 171:3a7713b1edbc 5409 /** Peripheral PORTA base pointer */
AnnaBridge 171:3a7713b1edbc 5410 #define PORTA ((PORT_Type *)PORTA_BASE)
AnnaBridge 171:3a7713b1edbc 5411 /** Peripheral PORTB base address */
AnnaBridge 171:3a7713b1edbc 5412 #define PORTB_BASE (0x4004A000u)
AnnaBridge 171:3a7713b1edbc 5413 /** Peripheral PORTB base pointer */
AnnaBridge 171:3a7713b1edbc 5414 #define PORTB ((PORT_Type *)PORTB_BASE)
AnnaBridge 171:3a7713b1edbc 5415 /** Peripheral PORTC base address */
AnnaBridge 171:3a7713b1edbc 5416 #define PORTC_BASE (0x4004B000u)
AnnaBridge 171:3a7713b1edbc 5417 /** Peripheral PORTC base pointer */
AnnaBridge 171:3a7713b1edbc 5418 #define PORTC ((PORT_Type *)PORTC_BASE)
AnnaBridge 171:3a7713b1edbc 5419 /** Array initializer of PORT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5420 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE }
AnnaBridge 171:3a7713b1edbc 5421 /** Array initializer of PORT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5422 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC }
AnnaBridge 171:3a7713b1edbc 5423 /** Interrupt vectors for the PORT peripheral type */
AnnaBridge 171:3a7713b1edbc 5424 #define PORT_IRQS { PORTA_IRQn, PORTB_PORTC_IRQn, PORTB_PORTC_IRQn }
AnnaBridge 171:3a7713b1edbc 5425
AnnaBridge 171:3a7713b1edbc 5426 /*!
AnnaBridge 171:3a7713b1edbc 5427 * @}
AnnaBridge 171:3a7713b1edbc 5428 */ /* end of group PORT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5429
AnnaBridge 171:3a7713b1edbc 5430
AnnaBridge 171:3a7713b1edbc 5431 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5432 -- RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5433 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5434
AnnaBridge 171:3a7713b1edbc 5435 /*!
AnnaBridge 171:3a7713b1edbc 5436 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5437 * @{
AnnaBridge 171:3a7713b1edbc 5438 */
AnnaBridge 171:3a7713b1edbc 5439
AnnaBridge 171:3a7713b1edbc 5440 /** RCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5441 typedef struct {
AnnaBridge 171:3a7713b1edbc 5442 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5443 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 5444 uint8_t RESERVED_0[2];
AnnaBridge 171:3a7713b1edbc 5445 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 5446 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 5447 } RCM_Type;
AnnaBridge 171:3a7713b1edbc 5448
AnnaBridge 171:3a7713b1edbc 5449 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5450 -- RCM Register Masks
AnnaBridge 171:3a7713b1edbc 5451 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5452
AnnaBridge 171:3a7713b1edbc 5453 /*!
AnnaBridge 171:3a7713b1edbc 5454 * @addtogroup RCM_Register_Masks RCM Register Masks
AnnaBridge 171:3a7713b1edbc 5455 * @{
AnnaBridge 171:3a7713b1edbc 5456 */
AnnaBridge 171:3a7713b1edbc 5457
AnnaBridge 171:3a7713b1edbc 5458 /*! @name SRS0 - System Reset Status Register 0 */
AnnaBridge 171:3a7713b1edbc 5459 #define RCM_SRS0_WAKEUP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5460 #define RCM_SRS0_WAKEUP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5461 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
AnnaBridge 171:3a7713b1edbc 5462 #define RCM_SRS0_LVD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5463 #define RCM_SRS0_LVD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5464 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
AnnaBridge 171:3a7713b1edbc 5465 #define RCM_SRS0_LOC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5466 #define RCM_SRS0_LOC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5467 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
AnnaBridge 171:3a7713b1edbc 5468 #define RCM_SRS0_WDOG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5469 #define RCM_SRS0_WDOG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5470 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
AnnaBridge 171:3a7713b1edbc 5471 #define RCM_SRS0_PIN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5472 #define RCM_SRS0_PIN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5473 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
AnnaBridge 171:3a7713b1edbc 5474 #define RCM_SRS0_POR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5475 #define RCM_SRS0_POR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5476 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
AnnaBridge 171:3a7713b1edbc 5477
AnnaBridge 171:3a7713b1edbc 5478 /*! @name SRS1 - System Reset Status Register 1 */
AnnaBridge 171:3a7713b1edbc 5479 #define RCM_SRS1_LOCKUP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5480 #define RCM_SRS1_LOCKUP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5481 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
AnnaBridge 171:3a7713b1edbc 5482 #define RCM_SRS1_SW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5483 #define RCM_SRS1_SW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5484 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
AnnaBridge 171:3a7713b1edbc 5485 #define RCM_SRS1_MDM_AP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5486 #define RCM_SRS1_MDM_AP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5487 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
AnnaBridge 171:3a7713b1edbc 5488 #define RCM_SRS1_SACKERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5489 #define RCM_SRS1_SACKERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5490 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
AnnaBridge 171:3a7713b1edbc 5491
AnnaBridge 171:3a7713b1edbc 5492 /*! @name RPFC - Reset Pin Filter Control register */
AnnaBridge 171:3a7713b1edbc 5493 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 5494 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5495 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
AnnaBridge 171:3a7713b1edbc 5496 #define RCM_RPFC_RSTFLTSS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5497 #define RCM_RPFC_RSTFLTSS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5498 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
AnnaBridge 171:3a7713b1edbc 5499
AnnaBridge 171:3a7713b1edbc 5500 /*! @name RPFW - Reset Pin Filter Width register */
AnnaBridge 171:3a7713b1edbc 5501 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 5502 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5503 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 5504
AnnaBridge 171:3a7713b1edbc 5505
AnnaBridge 171:3a7713b1edbc 5506 /*!
AnnaBridge 171:3a7713b1edbc 5507 * @}
AnnaBridge 171:3a7713b1edbc 5508 */ /* end of group RCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5509
AnnaBridge 171:3a7713b1edbc 5510
AnnaBridge 171:3a7713b1edbc 5511 /* RCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5512 /** Peripheral RCM base address */
AnnaBridge 171:3a7713b1edbc 5513 #define RCM_BASE (0x4007F000u)
AnnaBridge 171:3a7713b1edbc 5514 /** Peripheral RCM base pointer */
AnnaBridge 171:3a7713b1edbc 5515 #define RCM ((RCM_Type *)RCM_BASE)
AnnaBridge 171:3a7713b1edbc 5516 /** Array initializer of RCM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5517 #define RCM_BASE_ADDRS { RCM_BASE }
AnnaBridge 171:3a7713b1edbc 5518 /** Array initializer of RCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5519 #define RCM_BASE_PTRS { RCM }
AnnaBridge 171:3a7713b1edbc 5520
AnnaBridge 171:3a7713b1edbc 5521 /*!
AnnaBridge 171:3a7713b1edbc 5522 * @}
AnnaBridge 171:3a7713b1edbc 5523 */ /* end of group RCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5524
AnnaBridge 171:3a7713b1edbc 5525
AnnaBridge 171:3a7713b1edbc 5526 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5527 -- RFSYS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5528 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5529
AnnaBridge 171:3a7713b1edbc 5530 /*!
AnnaBridge 171:3a7713b1edbc 5531 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5532 * @{
AnnaBridge 171:3a7713b1edbc 5533 */
AnnaBridge 171:3a7713b1edbc 5534
AnnaBridge 171:3a7713b1edbc 5535 /** RFSYS - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5536 typedef struct {
AnnaBridge 171:3a7713b1edbc 5537 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5538 } RFSYS_Type;
AnnaBridge 171:3a7713b1edbc 5539
AnnaBridge 171:3a7713b1edbc 5540 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5541 -- RFSYS Register Masks
AnnaBridge 171:3a7713b1edbc 5542 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5543
AnnaBridge 171:3a7713b1edbc 5544 /*!
AnnaBridge 171:3a7713b1edbc 5545 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
AnnaBridge 171:3a7713b1edbc 5546 * @{
AnnaBridge 171:3a7713b1edbc 5547 */
AnnaBridge 171:3a7713b1edbc 5548
AnnaBridge 171:3a7713b1edbc 5549 /*! @name REG - Register file register */
AnnaBridge 171:3a7713b1edbc 5550 #define RFSYS_REG_LL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5551 #define RFSYS_REG_LL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5552 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
AnnaBridge 171:3a7713b1edbc 5553 #define RFSYS_REG_LH_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 5554 #define RFSYS_REG_LH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5555 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
AnnaBridge 171:3a7713b1edbc 5556 #define RFSYS_REG_HL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 5557 #define RFSYS_REG_HL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5558 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
AnnaBridge 171:3a7713b1edbc 5559 #define RFSYS_REG_HH_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 5560 #define RFSYS_REG_HH_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5561 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
AnnaBridge 171:3a7713b1edbc 5562
AnnaBridge 171:3a7713b1edbc 5563 /* The count of RFSYS_REG */
AnnaBridge 171:3a7713b1edbc 5564 #define RFSYS_REG_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 5565
AnnaBridge 171:3a7713b1edbc 5566
AnnaBridge 171:3a7713b1edbc 5567 /*!
AnnaBridge 171:3a7713b1edbc 5568 * @}
AnnaBridge 171:3a7713b1edbc 5569 */ /* end of group RFSYS_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5570
AnnaBridge 171:3a7713b1edbc 5571
AnnaBridge 171:3a7713b1edbc 5572 /* RFSYS - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5573 /** Peripheral RFSYS base address */
AnnaBridge 171:3a7713b1edbc 5574 #define RFSYS_BASE (0x40041000u)
AnnaBridge 171:3a7713b1edbc 5575 /** Peripheral RFSYS base pointer */
AnnaBridge 171:3a7713b1edbc 5576 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
AnnaBridge 171:3a7713b1edbc 5577 /** Array initializer of RFSYS peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5578 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
AnnaBridge 171:3a7713b1edbc 5579 /** Array initializer of RFSYS peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5580 #define RFSYS_BASE_PTRS { RFSYS }
AnnaBridge 171:3a7713b1edbc 5581
AnnaBridge 171:3a7713b1edbc 5582 /*!
AnnaBridge 171:3a7713b1edbc 5583 * @}
AnnaBridge 171:3a7713b1edbc 5584 */ /* end of group RFSYS_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5585
AnnaBridge 171:3a7713b1edbc 5586
AnnaBridge 171:3a7713b1edbc 5587 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5588 -- ROM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5589 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5590
AnnaBridge 171:3a7713b1edbc 5591 /*!
AnnaBridge 171:3a7713b1edbc 5592 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5593 * @{
AnnaBridge 171:3a7713b1edbc 5594 */
AnnaBridge 171:3a7713b1edbc 5595
AnnaBridge 171:3a7713b1edbc 5596 /** ROM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5597 typedef struct {
AnnaBridge 171:3a7713b1edbc 5598 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5599 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 5600 uint8_t RESERVED_0[4028];
AnnaBridge 171:3a7713b1edbc 5601 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
AnnaBridge 171:3a7713b1edbc 5602 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
AnnaBridge 171:3a7713b1edbc 5603 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
AnnaBridge 171:3a7713b1edbc 5604 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
AnnaBridge 171:3a7713b1edbc 5605 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
AnnaBridge 171:3a7713b1edbc 5606 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
AnnaBridge 171:3a7713b1edbc 5607 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
AnnaBridge 171:3a7713b1edbc 5608 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
AnnaBridge 171:3a7713b1edbc 5609 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
AnnaBridge 171:3a7713b1edbc 5610 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5611 } ROM_Type;
AnnaBridge 171:3a7713b1edbc 5612
AnnaBridge 171:3a7713b1edbc 5613 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5614 -- ROM Register Masks
AnnaBridge 171:3a7713b1edbc 5615 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5616
AnnaBridge 171:3a7713b1edbc 5617 /*!
AnnaBridge 171:3a7713b1edbc 5618 * @addtogroup ROM_Register_Masks ROM Register Masks
AnnaBridge 171:3a7713b1edbc 5619 * @{
AnnaBridge 171:3a7713b1edbc 5620 */
AnnaBridge 171:3a7713b1edbc 5621
AnnaBridge 171:3a7713b1edbc 5622 /*! @name ENTRY - Entry */
AnnaBridge 171:3a7713b1edbc 5623 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5624 #define ROM_ENTRY_ENTRY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5625 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK)
AnnaBridge 171:3a7713b1edbc 5626
AnnaBridge 171:3a7713b1edbc 5627 /* The count of ROM_ENTRY */
AnnaBridge 171:3a7713b1edbc 5628 #define ROM_ENTRY_COUNT (3U)
AnnaBridge 171:3a7713b1edbc 5629
AnnaBridge 171:3a7713b1edbc 5630 /*! @name TABLEMARK - End of Table Marker Register */
AnnaBridge 171:3a7713b1edbc 5631 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5632 #define ROM_TABLEMARK_MARK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5633 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK)
AnnaBridge 171:3a7713b1edbc 5634
AnnaBridge 171:3a7713b1edbc 5635 /*! @name SYSACCESS - System Access Register */
AnnaBridge 171:3a7713b1edbc 5636 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5637 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5638 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK)
AnnaBridge 171:3a7713b1edbc 5639
AnnaBridge 171:3a7713b1edbc 5640 /*! @name PERIPHID4 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 5641 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5642 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5643 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 5644
AnnaBridge 171:3a7713b1edbc 5645 /*! @name PERIPHID5 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 5646 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5647 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5648 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 5649
AnnaBridge 171:3a7713b1edbc 5650 /*! @name PERIPHID6 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 5651 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5652 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5653 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 5654
AnnaBridge 171:3a7713b1edbc 5655 /*! @name PERIPHID7 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 5656 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5657 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5658 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 5659
AnnaBridge 171:3a7713b1edbc 5660 /*! @name PERIPHID0 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 5661 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5662 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5663 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 5664
AnnaBridge 171:3a7713b1edbc 5665 /*! @name PERIPHID1 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 5666 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5667 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5668 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 5669
AnnaBridge 171:3a7713b1edbc 5670 /*! @name PERIPHID2 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 5671 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5672 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5673 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 5674
AnnaBridge 171:3a7713b1edbc 5675 /*! @name PERIPHID3 - Peripheral ID Register */
AnnaBridge 171:3a7713b1edbc 5676 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5677 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5678 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK)
AnnaBridge 171:3a7713b1edbc 5679
AnnaBridge 171:3a7713b1edbc 5680 /*! @name COMPID - Component ID Register */
AnnaBridge 171:3a7713b1edbc 5681 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5682 #define ROM_COMPID_COMPID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5683 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK)
AnnaBridge 171:3a7713b1edbc 5684
AnnaBridge 171:3a7713b1edbc 5685 /* The count of ROM_COMPID */
AnnaBridge 171:3a7713b1edbc 5686 #define ROM_COMPID_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5687
AnnaBridge 171:3a7713b1edbc 5688
AnnaBridge 171:3a7713b1edbc 5689 /*!
AnnaBridge 171:3a7713b1edbc 5690 * @}
AnnaBridge 171:3a7713b1edbc 5691 */ /* end of group ROM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5692
AnnaBridge 171:3a7713b1edbc 5693
AnnaBridge 171:3a7713b1edbc 5694 /* ROM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5695 /** Peripheral ROM base address */
AnnaBridge 171:3a7713b1edbc 5696 #define ROM_BASE (0xF0002000u)
AnnaBridge 171:3a7713b1edbc 5697 /** Peripheral ROM base pointer */
AnnaBridge 171:3a7713b1edbc 5698 #define ROM ((ROM_Type *)ROM_BASE)
AnnaBridge 171:3a7713b1edbc 5699 /** Array initializer of ROM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5700 #define ROM_BASE_ADDRS { ROM_BASE }
AnnaBridge 171:3a7713b1edbc 5701 /** Array initializer of ROM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5702 #define ROM_BASE_PTRS { ROM }
AnnaBridge 171:3a7713b1edbc 5703
AnnaBridge 171:3a7713b1edbc 5704 /*!
AnnaBridge 171:3a7713b1edbc 5705 * @}
AnnaBridge 171:3a7713b1edbc 5706 */ /* end of group ROM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5707
AnnaBridge 171:3a7713b1edbc 5708
AnnaBridge 171:3a7713b1edbc 5709 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5710 -- RSIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5711 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5712
AnnaBridge 171:3a7713b1edbc 5713 /*!
AnnaBridge 171:3a7713b1edbc 5714 * @addtogroup RSIM_Peripheral_Access_Layer RSIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5715 * @{
AnnaBridge 171:3a7713b1edbc 5716 */
AnnaBridge 171:3a7713b1edbc 5717
AnnaBridge 171:3a7713b1edbc 5718 /** RSIM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5719 typedef struct {
AnnaBridge 171:3a7713b1edbc 5720 __IO uint32_t CONTROL; /**< Radio System Control, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5721 __IO uint32_t ACTIVE_DELAY; /**< Radio Active Early Warning, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 5722 __I uint32_t MAC_MSB; /**< Radio MAC Address, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 5723 __I uint32_t MAC_LSB; /**< Radio MAC Address, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 5724 __IO uint32_t MISC; /**< Radio Miscellaneous, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 5725 uint8_t RESERVED_0[236];
AnnaBridge 171:3a7713b1edbc 5726 __I uint32_t DSM_TIMER; /**< Deep Sleep Timer, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 5727 __IO uint32_t DSM_CONTROL; /**< Deep Sleep Timer Control, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 5728 __IO uint32_t DSM_OSC_OFFSET; /**< Deep Sleep Wakeup Time Offset, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 5729 __IO uint32_t ANT_SLEEP; /**< ANT Link Layer Sleep Time, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 5730 __IO uint32_t ANT_WAKE; /**< ANT Link Layer Wake Time, offset: 0x110 */
AnnaBridge 171:3a7713b1edbc 5731 __IO uint32_t ZIG_SLEEP; /**< 802.15.4 Link Layer Sleep Time, offset: 0x114 */
AnnaBridge 171:3a7713b1edbc 5732 __IO uint32_t ZIG_WAKE; /**< 802.15.4 Link Layer Wake Time, offset: 0x118 */
AnnaBridge 171:3a7713b1edbc 5733 __IO uint32_t GEN_SLEEP; /**< Generic FSK Link Layer Sleep Time, offset: 0x11C */
AnnaBridge 171:3a7713b1edbc 5734 __IO uint32_t GEN_WAKE; /**< Generic FSK Link Layer Wake Time, offset: 0x120 */
AnnaBridge 171:3a7713b1edbc 5735 __IO uint32_t RF_OSC_CTRL; /**< Radio Oscillator Control, offset: 0x124 */
AnnaBridge 171:3a7713b1edbc 5736 __IO uint32_t ANA_TEST; /**< Radio Analog Test Registers, offset: 0x128 */
AnnaBridge 171:3a7713b1edbc 5737 __IO uint32_t ANA_TRIM; /**< Radio Analog Trim Registers, offset: 0x12C */
AnnaBridge 171:3a7713b1edbc 5738 } RSIM_Type;
AnnaBridge 171:3a7713b1edbc 5739
AnnaBridge 171:3a7713b1edbc 5740 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5741 -- RSIM Register Masks
AnnaBridge 171:3a7713b1edbc 5742 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5743
AnnaBridge 171:3a7713b1edbc 5744 /*!
AnnaBridge 171:3a7713b1edbc 5745 * @addtogroup RSIM_Register_Masks RSIM Register Masks
AnnaBridge 171:3a7713b1edbc 5746 * @{
AnnaBridge 171:3a7713b1edbc 5747 */
AnnaBridge 171:3a7713b1edbc 5748
AnnaBridge 171:3a7713b1edbc 5749 /*! @name CONTROL - Radio System Control */
AnnaBridge 171:3a7713b1edbc 5750 #define RSIM_CONTROL_BLE_RF_OSC_REQ_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5751 #define RSIM_CONTROL_BLE_RF_OSC_REQ_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5752 #define RSIM_CONTROL_BLE_RF_OSC_REQ_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_OSC_REQ_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_OSC_REQ_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5753 #define RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5754 #define RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5755 #define RSIM_CONTROL_BLE_RF_OSC_REQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_SHIFT)) & RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_MASK)
AnnaBridge 171:3a7713b1edbc 5756 #define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5757 #define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5758 #define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_SHIFT)) & RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5759 #define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5760 #define RSIM_CONTROL_BLE_RF_OSC_REQ_INT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5761 #define RSIM_CONTROL_BLE_RF_OSC_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLE_RF_OSC_REQ_INT_SHIFT)) & RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK)
AnnaBridge 171:3a7713b1edbc 5762 #define RSIM_CONTROL_RF_OSC_EN_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 5763 #define RSIM_CONTROL_RF_OSC_EN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5764 #define RSIM_CONTROL_RF_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5765 #define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 5766 #define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 5767 #define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5768 #define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 5769 #define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 5770 #define RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_SHIFT)) & RSIM_CONTROL_RADIO_GASKET_BYPASS_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 5771 #define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 5772 #define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5773 #define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1_SHIFT)) & RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_1_MASK)
AnnaBridge 171:3a7713b1edbc 5774 #define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 5775 #define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 5776 #define RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2_SHIFT)) & RSIM_CONTROL_IPP_OBE_3V_BLE_ACTIVE_2_MASK)
AnnaBridge 171:3a7713b1edbc 5777 #define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 5778 #define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 5779 #define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN_SHIFT)) & RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5780 #define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 5781 #define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 5782 #define RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_SHIFT)) & RSIM_CONTROL_RADIO_RAM_ACCESS_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 5783 #define RSIM_CONTROL_RSIM_DSM_EXIT_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 5784 #define RSIM_CONTROL_RSIM_DSM_EXIT_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 5785 #define RSIM_CONTROL_RSIM_DSM_EXIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_DSM_EXIT_SHIFT)) & RSIM_CONTROL_RSIM_DSM_EXIT_MASK)
AnnaBridge 171:3a7713b1edbc 5786 #define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 5787 #define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 5788 #define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN_SHIFT)) & RSIM_CONTROL_RSIM_STOP_ACK_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5789 #define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 5790 #define RSIM_CONTROL_RSIM_STOP_ACK_OVRD_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 5791 #define RSIM_CONTROL_RSIM_STOP_ACK_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RSIM_STOP_ACK_OVRD_SHIFT)) & RSIM_CONTROL_RSIM_STOP_ACK_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 5792 #define RSIM_CONTROL_RF_OSC_READY_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 5793 #define RSIM_CONTROL_RF_OSC_READY_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5794 #define RSIM_CONTROL_RF_OSC_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_MASK)
AnnaBridge 171:3a7713b1edbc 5795 #define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 5796 #define RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 5797 #define RSIM_CONTROL_RF_OSC_READY_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5798 #define RSIM_CONTROL_RF_OSC_READY_OVRD_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 5799 #define RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 5800 #define RSIM_CONTROL_RF_OSC_READY_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT)) & RSIM_CONTROL_RF_OSC_READY_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 5801 #define RSIM_CONTROL_BLOCK_SOC_RESETS_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 5802 #define RSIM_CONTROL_BLOCK_SOC_RESETS_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 5803 #define RSIM_CONTROL_BLOCK_SOC_RESETS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLOCK_SOC_RESETS_SHIFT)) & RSIM_CONTROL_BLOCK_SOC_RESETS_MASK)
AnnaBridge 171:3a7713b1edbc 5804 #define RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 5805 #define RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 5806 #define RSIM_CONTROL_BLOCK_RADIO_OUTPUTS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_SHIFT)) & RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_MASK)
AnnaBridge 171:3a7713b1edbc 5807 #define RSIM_CONTROL_ALLOW_DFT_RESETS_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 5808 #define RSIM_CONTROL_ALLOW_DFT_RESETS_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 5809 #define RSIM_CONTROL_ALLOW_DFT_RESETS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_ALLOW_DFT_RESETS_SHIFT)) & RSIM_CONTROL_ALLOW_DFT_RESETS_MASK)
AnnaBridge 171:3a7713b1edbc 5810 #define RSIM_CONTROL_RADIO_RESET_BIT_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 5811 #define RSIM_CONTROL_RADIO_RESET_BIT_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 5812 #define RSIM_CONTROL_RADIO_RESET_BIT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_CONTROL_RADIO_RESET_BIT_SHIFT)) & RSIM_CONTROL_RADIO_RESET_BIT_MASK)
AnnaBridge 171:3a7713b1edbc 5813
AnnaBridge 171:3a7713b1edbc 5814 /*! @name ACTIVE_DELAY - Radio Active Early Warning */
AnnaBridge 171:3a7713b1edbc 5815 #define RSIM_ACTIVE_DELAY_BLE_FINE_DELAY_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 5816 #define RSIM_ACTIVE_DELAY_BLE_FINE_DELAY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5817 #define RSIM_ACTIVE_DELAY_BLE_FINE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ACTIVE_DELAY_BLE_FINE_DELAY_SHIFT)) & RSIM_ACTIVE_DELAY_BLE_FINE_DELAY_MASK)
AnnaBridge 171:3a7713b1edbc 5818 #define RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 5819 #define RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5820 #define RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY_SHIFT)) & RSIM_ACTIVE_DELAY_BLE_COARSE_DELAY_MASK)
AnnaBridge 171:3a7713b1edbc 5821
AnnaBridge 171:3a7713b1edbc 5822 /*! @name MAC_MSB - Radio MAC Address */
AnnaBridge 171:3a7713b1edbc 5823 #define RSIM_MAC_MSB_MAC_ADDR_MSB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5824 #define RSIM_MAC_MSB_MAC_ADDR_MSB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5825 #define RSIM_MAC_MSB_MAC_ADDR_MSB(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MAC_MSB_MAC_ADDR_MSB_SHIFT)) & RSIM_MAC_MSB_MAC_ADDR_MSB_MASK)
AnnaBridge 171:3a7713b1edbc 5826
AnnaBridge 171:3a7713b1edbc 5827 /*! @name MAC_LSB - Radio MAC Address */
AnnaBridge 171:3a7713b1edbc 5828 #define RSIM_MAC_LSB_MAC_ADDR_LSB_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5829 #define RSIM_MAC_LSB_MAC_ADDR_LSB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5830 #define RSIM_MAC_LSB_MAC_ADDR_LSB(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MAC_LSB_MAC_ADDR_LSB_SHIFT)) & RSIM_MAC_LSB_MAC_ADDR_LSB_MASK)
AnnaBridge 171:3a7713b1edbc 5831
AnnaBridge 171:3a7713b1edbc 5832 /*! @name MISC - Radio Miscellaneous */
AnnaBridge 171:3a7713b1edbc 5833 #define RSIM_MISC_ANALOG_TEST_EN_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 5834 #define RSIM_MISC_ANALOG_TEST_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5835 #define RSIM_MISC_ANALOG_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MISC_ANALOG_TEST_EN_SHIFT)) & RSIM_MISC_ANALOG_TEST_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5836 #define RSIM_MISC_RADIO_VERSION_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 5837 #define RSIM_MISC_RADIO_VERSION_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5838 #define RSIM_MISC_RADIO_VERSION(x) (((uint32_t)(((uint32_t)(x)) << RSIM_MISC_RADIO_VERSION_SHIFT)) & RSIM_MISC_RADIO_VERSION_MASK)
AnnaBridge 171:3a7713b1edbc 5839
AnnaBridge 171:3a7713b1edbc 5840 /*! @name DSM_TIMER - Deep Sleep Timer */
AnnaBridge 171:3a7713b1edbc 5841 #define RSIM_DSM_TIMER_DSM_TIMER_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5842 #define RSIM_DSM_TIMER_DSM_TIMER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5843 #define RSIM_DSM_TIMER_DSM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_TIMER_DSM_TIMER_SHIFT)) & RSIM_DSM_TIMER_DSM_TIMER_MASK)
AnnaBridge 171:3a7713b1edbc 5844
AnnaBridge 171:3a7713b1edbc 5845 /*! @name DSM_CONTROL - Deep Sleep Timer Control */
AnnaBridge 171:3a7713b1edbc 5846 #define RSIM_DSM_CONTROL_DSM_ANT_READY_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5847 #define RSIM_DSM_CONTROL_DSM_ANT_READY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5848 #define RSIM_DSM_CONTROL_DSM_ANT_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_ANT_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_ANT_READY_MASK)
AnnaBridge 171:3a7713b1edbc 5849 #define RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5850 #define RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5851 #define RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_ANT_DEEP_SLEEP_STATUS_MASK)
AnnaBridge 171:3a7713b1edbc 5852 #define RSIM_DSM_CONTROL_DSM_ANT_FINISHED_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5853 #define RSIM_DSM_CONTROL_DSM_ANT_FINISHED_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5854 #define RSIM_DSM_CONTROL_DSM_ANT_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_ANT_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_ANT_FINISHED_MASK)
AnnaBridge 171:3a7713b1edbc 5855 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5856 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5857 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_ANT_SYSCLK_REQUEST_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5858 #define RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5859 #define RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5860 #define RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_ANT_SLEEP_REQUEST_MASK)
AnnaBridge 171:3a7713b1edbc 5861 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5862 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5863 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_SHIFT)) & RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_MASK)
AnnaBridge 171:3a7713b1edbc 5864 #define RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5865 #define RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5866 #define RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_ANT_SYSCLK_INTERRUPT_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5867 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5868 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5869 #define RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_ANT_SYSCLK_REQ_INT_MASK)
AnnaBridge 171:3a7713b1edbc 5870 #define RSIM_DSM_CONTROL_DSM_GEN_READY_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 5871 #define RSIM_DSM_CONTROL_DSM_GEN_READY_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5872 #define RSIM_DSM_CONTROL_DSM_GEN_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_GEN_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_GEN_READY_MASK)
AnnaBridge 171:3a7713b1edbc 5873 #define RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 5874 #define RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 5875 #define RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_GEN_DEEP_SLEEP_STATUS_MASK)
AnnaBridge 171:3a7713b1edbc 5876 #define RSIM_DSM_CONTROL_DSM_GEN_FINISHED_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 5877 #define RSIM_DSM_CONTROL_DSM_GEN_FINISHED_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 5878 #define RSIM_DSM_CONTROL_DSM_GEN_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_GEN_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_GEN_FINISHED_MASK)
AnnaBridge 171:3a7713b1edbc 5879 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 5880 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 5881 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_GEN_SYSCLK_REQUEST_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5882 #define RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 5883 #define RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 5884 #define RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_GEN_SLEEP_REQUEST_MASK)
AnnaBridge 171:3a7713b1edbc 5885 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 5886 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 5887 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_SHIFT)) & RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_MASK)
AnnaBridge 171:3a7713b1edbc 5888 #define RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 5889 #define RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 5890 #define RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_GEN_SYSCLK_INTERRUPT_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5891 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 5892 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 5893 #define RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_GEN_SYSCLK_REQ_INT_MASK)
AnnaBridge 171:3a7713b1edbc 5894 #define RSIM_DSM_CONTROL_DSM_ZIG_READY_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 5895 #define RSIM_DSM_CONTROL_DSM_ZIG_READY_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5896 #define RSIM_DSM_CONTROL_DSM_ZIG_READY(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_ZIG_READY_SHIFT)) & RSIM_DSM_CONTROL_DSM_ZIG_READY_MASK)
AnnaBridge 171:3a7713b1edbc 5897 #define RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 5898 #define RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 5899 #define RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_SHIFT)) & RSIM_DSM_CONTROL_ZIG_DEEP_SLEEP_STATUS_MASK)
AnnaBridge 171:3a7713b1edbc 5900 #define RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 5901 #define RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 5902 #define RSIM_DSM_CONTROL_DSM_ZIG_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_SHIFT)) & RSIM_DSM_CONTROL_DSM_ZIG_FINISHED_MASK)
AnnaBridge 171:3a7713b1edbc 5903 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 5904 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 5905 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SYSCLK_REQUEST_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5906 #define RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 5907 #define RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 5908 #define RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SLEEP_REQUEST_MASK)
AnnaBridge 171:3a7713b1edbc 5909 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 5910 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 5911 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_MASK)
AnnaBridge 171:3a7713b1edbc 5912 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 5913 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 5914 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SYSCLK_INTERRUPT_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5915 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 5916 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 5917 #define RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT_SHIFT)) & RSIM_DSM_CONTROL_ZIG_SYSCLK_REQ_INT_MASK)
AnnaBridge 171:3a7713b1edbc 5918 #define RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 5919 #define RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 5920 #define RSIM_DSM_CONTROL_DSM_TIMER_CLR(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_CLR_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_CLR_MASK)
AnnaBridge 171:3a7713b1edbc 5921 #define RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 5922 #define RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 5923 #define RSIM_DSM_CONTROL_DSM_TIMER_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_CONTROL_DSM_TIMER_EN_SHIFT)) & RSIM_DSM_CONTROL_DSM_TIMER_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5924
AnnaBridge 171:3a7713b1edbc 5925 /*! @name DSM_OSC_OFFSET - Deep Sleep Wakeup Time Offset */
AnnaBridge 171:3a7713b1edbc 5926 #define RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 5927 #define RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5928 #define RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME_SHIFT)) & RSIM_DSM_OSC_OFFSET_DSM_OSC_STABILIZE_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 5929
AnnaBridge 171:3a7713b1edbc 5930 /*! @name ANT_SLEEP - ANT Link Layer Sleep Time */
AnnaBridge 171:3a7713b1edbc 5931 #define RSIM_ANT_SLEEP_ANT_SLEEP_TIME_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5932 #define RSIM_ANT_SLEEP_ANT_SLEEP_TIME_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5933 #define RSIM_ANT_SLEEP_ANT_SLEEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANT_SLEEP_ANT_SLEEP_TIME_SHIFT)) & RSIM_ANT_SLEEP_ANT_SLEEP_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 5934
AnnaBridge 171:3a7713b1edbc 5935 /*! @name ANT_WAKE - ANT Link Layer Wake Time */
AnnaBridge 171:3a7713b1edbc 5936 #define RSIM_ANT_WAKE_ANT_WAKE_TIME_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5937 #define RSIM_ANT_WAKE_ANT_WAKE_TIME_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5938 #define RSIM_ANT_WAKE_ANT_WAKE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANT_WAKE_ANT_WAKE_TIME_SHIFT)) & RSIM_ANT_WAKE_ANT_WAKE_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 5939
AnnaBridge 171:3a7713b1edbc 5940 /*! @name ZIG_SLEEP - 802.15.4 Link Layer Sleep Time */
AnnaBridge 171:3a7713b1edbc 5941 #define RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5942 #define RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5943 #define RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME_SHIFT)) & RSIM_ZIG_SLEEP_ZIG_SLEEP_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 5944
AnnaBridge 171:3a7713b1edbc 5945 /*! @name ZIG_WAKE - 802.15.4 Link Layer Wake Time */
AnnaBridge 171:3a7713b1edbc 5946 #define RSIM_ZIG_WAKE_ZIG_WAKE_TIME_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5947 #define RSIM_ZIG_WAKE_ZIG_WAKE_TIME_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5948 #define RSIM_ZIG_WAKE_ZIG_WAKE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ZIG_WAKE_ZIG_WAKE_TIME_SHIFT)) & RSIM_ZIG_WAKE_ZIG_WAKE_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 5949
AnnaBridge 171:3a7713b1edbc 5950 /*! @name GEN_SLEEP - Generic FSK Link Layer Sleep Time */
AnnaBridge 171:3a7713b1edbc 5951 #define RSIM_GEN_SLEEP_GEN_SLEEP_TIME_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5952 #define RSIM_GEN_SLEEP_GEN_SLEEP_TIME_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5953 #define RSIM_GEN_SLEEP_GEN_SLEEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_GEN_SLEEP_GEN_SLEEP_TIME_SHIFT)) & RSIM_GEN_SLEEP_GEN_SLEEP_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 5954
AnnaBridge 171:3a7713b1edbc 5955 /*! @name GEN_WAKE - Generic FSK Link Layer Wake Time */
AnnaBridge 171:3a7713b1edbc 5956 #define RSIM_GEN_WAKE_GEN_WAKE_TIME_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5957 #define RSIM_GEN_WAKE_GEN_WAKE_TIME_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5958 #define RSIM_GEN_WAKE_GEN_WAKE_TIME(x) (((uint32_t)(((uint32_t)(x)) << RSIM_GEN_WAKE_GEN_WAKE_TIME_SHIFT)) & RSIM_GEN_WAKE_GEN_WAKE_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 5959
AnnaBridge 171:3a7713b1edbc 5960 /*! @name RF_OSC_CTRL - Radio Oscillator Control */
AnnaBridge 171:3a7713b1edbc 5961 #define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 5962 #define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5963 #define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_COUNT_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 5964 #define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5965 #define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5966 #define RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ALC_ON_MASK)
AnnaBridge 171:3a7713b1edbc 5967 #define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5968 #define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5969 #define RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5970 #define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK (0x1F0U)
AnnaBridge 171:3a7713b1edbc 5971 #define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5972 #define RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_COMP_BIAS_MASK)
AnnaBridge 171:3a7713b1edbc 5973 #define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 5974 #define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 5975 #define RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DC_COUP_MODE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5976 #define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 5977 #define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 5978 #define RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 5979 #define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 5980 #define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 5981 #define RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_DIG_CLK_ON_MASK)
AnnaBridge 171:3a7713b1edbc 5982 #define RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK (0x1F000U)
AnnaBridge 171:3a7713b1edbc 5983 #define RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 5984 #define RSIM_RF_OSC_CTRL_BB_XTAL_GM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_GM_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_GM_MASK)
AnnaBridge 171:3a7713b1edbc 5985 #define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 5986 #define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 5987 #define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 5988 #define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 5989 #define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 5990 #define RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_ON_OVRD_ON_MASK)
AnnaBridge 171:3a7713b1edbc 5991 #define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 5992 #define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 5993 #define RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_BB_XTAL_READY_COUNT_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 5994 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 5995 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 5996 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_RF_EN_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 5997 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 5998 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 5999 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 6000 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 6001 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 6002 #define RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 6003 #define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 6004 #define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 6005 #define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 6006 #define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 6007 #define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 6008 #define RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN_SHIFT)) & RSIM_RF_OSC_CTRL_RADIO_RF_ABORT_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 6009
AnnaBridge 171:3a7713b1edbc 6010 /*! @name ANA_TEST - Radio Analog Test Registers */
AnnaBridge 171:3a7713b1edbc 6011 #define RSIM_ANA_TEST_BB_LDO_LS_BYP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6012 #define RSIM_ANA_TEST_BB_LDO_LS_BYP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6013 #define RSIM_ANA_TEST_BB_LDO_LS_BYP(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_LDO_LS_BYP_SHIFT)) & RSIM_ANA_TEST_BB_LDO_LS_BYP_MASK)
AnnaBridge 171:3a7713b1edbc 6014 #define RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6015 #define RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6016 #define RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL_SHIFT)) & RSIM_ANA_TEST_BB_LDO_LS_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6017 #define RSIM_ANA_TEST_BB_LDO_XO_BYP_ON_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6018 #define RSIM_ANA_TEST_BB_LDO_XO_BYP_ON_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6019 #define RSIM_ANA_TEST_BB_LDO_XO_BYP_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_LDO_XO_BYP_ON_SHIFT)) & RSIM_ANA_TEST_BB_LDO_XO_BYP_ON_MASK)
AnnaBridge 171:3a7713b1edbc 6020 #define RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6021 #define RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6022 #define RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL_SHIFT)) & RSIM_ANA_TEST_BB_LDO_XO_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6023 #define RSIM_ANA_TEST_BB_XTAL_TEST_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6024 #define RSIM_ANA_TEST_BB_XTAL_TEST_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6025 #define RSIM_ANA_TEST_BB_XTAL_TEST(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BB_XTAL_TEST_SHIFT)) & RSIM_ANA_TEST_BB_XTAL_TEST_MASK)
AnnaBridge 171:3a7713b1edbc 6026 #define RSIM_ANA_TEST_BG_DIAGBUF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6027 #define RSIM_ANA_TEST_BG_DIAGBUF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6028 #define RSIM_ANA_TEST_BG_DIAGBUF(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BG_DIAGBUF_SHIFT)) & RSIM_ANA_TEST_BG_DIAGBUF_MASK)
AnnaBridge 171:3a7713b1edbc 6029 #define RSIM_ANA_TEST_BG_DIAGSEL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6030 #define RSIM_ANA_TEST_BG_DIAGSEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6031 #define RSIM_ANA_TEST_BG_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BG_DIAGSEL_SHIFT)) & RSIM_ANA_TEST_BG_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6032 #define RSIM_ANA_TEST_BG_STARTUPFORCE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6033 #define RSIM_ANA_TEST_BG_STARTUPFORCE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6034 #define RSIM_ANA_TEST_BG_STARTUPFORCE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_BG_STARTUPFORCE_SHIFT)) & RSIM_ANA_TEST_BG_STARTUPFORCE_MASK)
AnnaBridge 171:3a7713b1edbc 6035 #define RSIM_ANA_TEST_DIAG_1234_ON_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6036 #define RSIM_ANA_TEST_DIAG_1234_ON_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6037 #define RSIM_ANA_TEST_DIAG_1234_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_DIAG_1234_ON_SHIFT)) & RSIM_ANA_TEST_DIAG_1234_ON_MASK)
AnnaBridge 171:3a7713b1edbc 6038 #define RSIM_ANA_TEST_DIAG2SOCADC_DEC_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 6039 #define RSIM_ANA_TEST_DIAG2SOCADC_DEC_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6040 #define RSIM_ANA_TEST_DIAG2SOCADC_DEC(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_DIAG2SOCADC_DEC_SHIFT)) & RSIM_ANA_TEST_DIAG2SOCADC_DEC_MASK)
AnnaBridge 171:3a7713b1edbc 6041 #define RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6042 #define RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6043 #define RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON_SHIFT)) & RSIM_ANA_TEST_DIAG2SOCADC_DEC_ON_MASK)
AnnaBridge 171:3a7713b1edbc 6044 #define RSIM_ANA_TEST_DIAGCODE_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 6045 #define RSIM_ANA_TEST_DIAGCODE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6046 #define RSIM_ANA_TEST_DIAGCODE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TEST_DIAGCODE_SHIFT)) & RSIM_ANA_TEST_DIAGCODE_MASK)
AnnaBridge 171:3a7713b1edbc 6047
AnnaBridge 171:3a7713b1edbc 6048 /*! @name ANA_TRIM - Radio Analog Trim Registers */
AnnaBridge 171:3a7713b1edbc 6049 #define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 6050 #define RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6051 #define RSIM_ANA_TRIM_BB_LDO_LS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 6052 #define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK (0x38U)
AnnaBridge 171:3a7713b1edbc 6053 #define RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6054 #define RSIM_ANA_TRIM_BB_LDO_LS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_LS_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_LS_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 6055 #define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 6056 #define RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6057 #define RSIM_ANA_TRIM_BB_LDO_XO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 6058 #define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 6059 #define RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6060 #define RSIM_ANA_TRIM_BB_LDO_XO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_LDO_XO_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_LDO_XO_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 6061 #define RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK (0xF800U)
AnnaBridge 171:3a7713b1edbc 6062 #define RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6063 #define RSIM_ANA_TRIM_BB_XTAL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_SPARE_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 6064 #define RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 6065 #define RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6066 #define RSIM_ANA_TRIM_BB_XTAL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT)) & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 6067 #define RSIM_ANA_TRIM_BG_1V_TRIM_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 6068 #define RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6069 #define RSIM_ANA_TRIM_BG_1V_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_1V_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_1V_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 6070 #define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 6071 #define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6072 #define RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM(x) (((uint32_t)(((uint32_t)(x)) << RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_SHIFT)) & RSIM_ANA_TRIM_BG_IBIAS_5U_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 6073
AnnaBridge 171:3a7713b1edbc 6074
AnnaBridge 171:3a7713b1edbc 6075 /*!
AnnaBridge 171:3a7713b1edbc 6076 * @}
AnnaBridge 171:3a7713b1edbc 6077 */ /* end of group RSIM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6078
AnnaBridge 171:3a7713b1edbc 6079
AnnaBridge 171:3a7713b1edbc 6080 /* RSIM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6081 /** Peripheral RSIM base address */
AnnaBridge 171:3a7713b1edbc 6082 #define RSIM_BASE (0x40059000u)
AnnaBridge 171:3a7713b1edbc 6083 /** Peripheral RSIM base pointer */
AnnaBridge 171:3a7713b1edbc 6084 #define RSIM ((RSIM_Type *)RSIM_BASE)
AnnaBridge 171:3a7713b1edbc 6085 /** Array initializer of RSIM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6086 #define RSIM_BASE_ADDRS { RSIM_BASE }
AnnaBridge 171:3a7713b1edbc 6087 /** Array initializer of RSIM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6088 #define RSIM_BASE_PTRS { RSIM }
AnnaBridge 171:3a7713b1edbc 6089
AnnaBridge 171:3a7713b1edbc 6090 /*!
AnnaBridge 171:3a7713b1edbc 6091 * @}
AnnaBridge 171:3a7713b1edbc 6092 */ /* end of group RSIM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6093
AnnaBridge 171:3a7713b1edbc 6094
AnnaBridge 171:3a7713b1edbc 6095 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6096 -- RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6097 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6098
AnnaBridge 171:3a7713b1edbc 6099 /*!
AnnaBridge 171:3a7713b1edbc 6100 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6101 * @{
AnnaBridge 171:3a7713b1edbc 6102 */
AnnaBridge 171:3a7713b1edbc 6103
AnnaBridge 171:3a7713b1edbc 6104 /** RTC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6105 typedef struct {
AnnaBridge 171:3a7713b1edbc 6106 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6107 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 6108 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 6109 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 6110 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 6111 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 6112 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 6113 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 6114 } RTC_Type;
AnnaBridge 171:3a7713b1edbc 6115
AnnaBridge 171:3a7713b1edbc 6116 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6117 -- RTC Register Masks
AnnaBridge 171:3a7713b1edbc 6118 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6119
AnnaBridge 171:3a7713b1edbc 6120 /*!
AnnaBridge 171:3a7713b1edbc 6121 * @addtogroup RTC_Register_Masks RTC Register Masks
AnnaBridge 171:3a7713b1edbc 6122 * @{
AnnaBridge 171:3a7713b1edbc 6123 */
AnnaBridge 171:3a7713b1edbc 6124
AnnaBridge 171:3a7713b1edbc 6125 /*! @name TSR - RTC Time Seconds Register */
AnnaBridge 171:3a7713b1edbc 6126 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6127 #define RTC_TSR_TSR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6128 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
AnnaBridge 171:3a7713b1edbc 6129
AnnaBridge 171:3a7713b1edbc 6130 /*! @name TPR - RTC Time Prescaler Register */
AnnaBridge 171:3a7713b1edbc 6131 #define RTC_TPR_TPR_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6132 #define RTC_TPR_TPR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6133 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
AnnaBridge 171:3a7713b1edbc 6134
AnnaBridge 171:3a7713b1edbc 6135 /*! @name TAR - RTC Time Alarm Register */
AnnaBridge 171:3a7713b1edbc 6136 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6137 #define RTC_TAR_TAR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6138 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
AnnaBridge 171:3a7713b1edbc 6139
AnnaBridge 171:3a7713b1edbc 6140 /*! @name TCR - RTC Time Compensation Register */
AnnaBridge 171:3a7713b1edbc 6141 #define RTC_TCR_TCR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6142 #define RTC_TCR_TCR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6143 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
AnnaBridge 171:3a7713b1edbc 6144 #define RTC_TCR_CIR_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 6145 #define RTC_TCR_CIR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6146 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
AnnaBridge 171:3a7713b1edbc 6147 #define RTC_TCR_TCV_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 6148 #define RTC_TCR_TCV_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6149 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
AnnaBridge 171:3a7713b1edbc 6150 #define RTC_TCR_CIC_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 6151 #define RTC_TCR_CIC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6152 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
AnnaBridge 171:3a7713b1edbc 6153
AnnaBridge 171:3a7713b1edbc 6154 /*! @name CR - RTC Control Register */
AnnaBridge 171:3a7713b1edbc 6155 #define RTC_CR_SWR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6156 #define RTC_CR_SWR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6157 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
AnnaBridge 171:3a7713b1edbc 6158 #define RTC_CR_WPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6159 #define RTC_CR_WPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6160 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
AnnaBridge 171:3a7713b1edbc 6161 #define RTC_CR_SUP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6162 #define RTC_CR_SUP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6163 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
AnnaBridge 171:3a7713b1edbc 6164 #define RTC_CR_UM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6165 #define RTC_CR_UM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6166 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
AnnaBridge 171:3a7713b1edbc 6167 #define RTC_CR_WPS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6168 #define RTC_CR_WPS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6169 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
AnnaBridge 171:3a7713b1edbc 6170 #define RTC_CR_OSCE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6171 #define RTC_CR_OSCE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6172 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
AnnaBridge 171:3a7713b1edbc 6173 #define RTC_CR_CLKO_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6174 #define RTC_CR_CLKO_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6175 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
AnnaBridge 171:3a7713b1edbc 6176 #define RTC_CR_SC16P_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6177 #define RTC_CR_SC16P_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6178 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
AnnaBridge 171:3a7713b1edbc 6179 #define RTC_CR_SC8P_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6180 #define RTC_CR_SC8P_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6181 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
AnnaBridge 171:3a7713b1edbc 6182 #define RTC_CR_SC4P_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 6183 #define RTC_CR_SC4P_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6184 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
AnnaBridge 171:3a7713b1edbc 6185 #define RTC_CR_SC2P_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 6186 #define RTC_CR_SC2P_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 6187 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
AnnaBridge 171:3a7713b1edbc 6188
AnnaBridge 171:3a7713b1edbc 6189 /*! @name SR - RTC Status Register */
AnnaBridge 171:3a7713b1edbc 6190 #define RTC_SR_TIF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6191 #define RTC_SR_TIF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6192 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
AnnaBridge 171:3a7713b1edbc 6193 #define RTC_SR_TOF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6194 #define RTC_SR_TOF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6195 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 6196 #define RTC_SR_TAF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6197 #define RTC_SR_TAF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6198 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
AnnaBridge 171:3a7713b1edbc 6199 #define RTC_SR_TCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6200 #define RTC_SR_TCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6201 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
AnnaBridge 171:3a7713b1edbc 6202
AnnaBridge 171:3a7713b1edbc 6203 /*! @name LR - RTC Lock Register */
AnnaBridge 171:3a7713b1edbc 6204 #define RTC_LR_TCL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6205 #define RTC_LR_TCL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6206 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
AnnaBridge 171:3a7713b1edbc 6207 #define RTC_LR_CRL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6208 #define RTC_LR_CRL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6209 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
AnnaBridge 171:3a7713b1edbc 6210 #define RTC_LR_SRL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6211 #define RTC_LR_SRL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6212 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
AnnaBridge 171:3a7713b1edbc 6213 #define RTC_LR_LRL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6214 #define RTC_LR_LRL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6215 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
AnnaBridge 171:3a7713b1edbc 6216
AnnaBridge 171:3a7713b1edbc 6217 /*! @name IER - RTC Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 6218 #define RTC_IER_TIIE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6219 #define RTC_IER_TIIE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6220 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
AnnaBridge 171:3a7713b1edbc 6221 #define RTC_IER_TOIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6222 #define RTC_IER_TOIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6223 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
AnnaBridge 171:3a7713b1edbc 6224 #define RTC_IER_TAIE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6225 #define RTC_IER_TAIE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6226 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
AnnaBridge 171:3a7713b1edbc 6227 #define RTC_IER_TSIE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6228 #define RTC_IER_TSIE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6229 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
AnnaBridge 171:3a7713b1edbc 6230 #define RTC_IER_WPON_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6231 #define RTC_IER_WPON_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6232 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
AnnaBridge 171:3a7713b1edbc 6233
AnnaBridge 171:3a7713b1edbc 6234
AnnaBridge 171:3a7713b1edbc 6235 /*!
AnnaBridge 171:3a7713b1edbc 6236 * @}
AnnaBridge 171:3a7713b1edbc 6237 */ /* end of group RTC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6238
AnnaBridge 171:3a7713b1edbc 6239
AnnaBridge 171:3a7713b1edbc 6240 /* RTC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6241 /** Peripheral RTC base address */
AnnaBridge 171:3a7713b1edbc 6242 #define RTC_BASE (0x4003D000u)
AnnaBridge 171:3a7713b1edbc 6243 /** Peripheral RTC base pointer */
AnnaBridge 171:3a7713b1edbc 6244 #define RTC ((RTC_Type *)RTC_BASE)
AnnaBridge 171:3a7713b1edbc 6245 /** Array initializer of RTC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6246 #define RTC_BASE_ADDRS { RTC_BASE }
AnnaBridge 171:3a7713b1edbc 6247 /** Array initializer of RTC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6248 #define RTC_BASE_PTRS { RTC }
AnnaBridge 171:3a7713b1edbc 6249 /** Interrupt vectors for the RTC peripheral type */
AnnaBridge 171:3a7713b1edbc 6250 #define RTC_IRQS { RTC_IRQn }
AnnaBridge 171:3a7713b1edbc 6251 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
AnnaBridge 171:3a7713b1edbc 6252
AnnaBridge 171:3a7713b1edbc 6253 /*!
AnnaBridge 171:3a7713b1edbc 6254 * @}
AnnaBridge 171:3a7713b1edbc 6255 */ /* end of group RTC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6256
AnnaBridge 171:3a7713b1edbc 6257
AnnaBridge 171:3a7713b1edbc 6258 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6259 -- SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6260 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6261
AnnaBridge 171:3a7713b1edbc 6262 /*!
AnnaBridge 171:3a7713b1edbc 6263 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6264 * @{
AnnaBridge 171:3a7713b1edbc 6265 */
AnnaBridge 171:3a7713b1edbc 6266
AnnaBridge 171:3a7713b1edbc 6267 /** SIM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6268 typedef struct {
AnnaBridge 171:3a7713b1edbc 6269 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6270 uint8_t RESERVED_0[4096];
AnnaBridge 171:3a7713b1edbc 6271 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
AnnaBridge 171:3a7713b1edbc 6272 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 6273 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
AnnaBridge 171:3a7713b1edbc 6274 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
AnnaBridge 171:3a7713b1edbc 6275 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 6276 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
AnnaBridge 171:3a7713b1edbc 6277 uint8_t RESERVED_3[8];
AnnaBridge 171:3a7713b1edbc 6278 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
AnnaBridge 171:3a7713b1edbc 6279 uint8_t RESERVED_4[12];
AnnaBridge 171:3a7713b1edbc 6280 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
AnnaBridge 171:3a7713b1edbc 6281 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
AnnaBridge 171:3a7713b1edbc 6282 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
AnnaBridge 171:3a7713b1edbc 6283 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
AnnaBridge 171:3a7713b1edbc 6284 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
AnnaBridge 171:3a7713b1edbc 6285 uint8_t RESERVED_5[4];
AnnaBridge 171:3a7713b1edbc 6286 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
AnnaBridge 171:3a7713b1edbc 6287 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
AnnaBridge 171:3a7713b1edbc 6288 uint8_t RESERVED_6[4];
AnnaBridge 171:3a7713b1edbc 6289 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
AnnaBridge 171:3a7713b1edbc 6290 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
AnnaBridge 171:3a7713b1edbc 6291 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
AnnaBridge 171:3a7713b1edbc 6292 uint8_t RESERVED_7[156];
AnnaBridge 171:3a7713b1edbc 6293 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
AnnaBridge 171:3a7713b1edbc 6294 __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
AnnaBridge 171:3a7713b1edbc 6295 } SIM_Type;
AnnaBridge 171:3a7713b1edbc 6296
AnnaBridge 171:3a7713b1edbc 6297 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6298 -- SIM Register Masks
AnnaBridge 171:3a7713b1edbc 6299 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6300
AnnaBridge 171:3a7713b1edbc 6301 /*!
AnnaBridge 171:3a7713b1edbc 6302 * @addtogroup SIM_Register_Masks SIM Register Masks
AnnaBridge 171:3a7713b1edbc 6303 * @{
AnnaBridge 171:3a7713b1edbc 6304 */
AnnaBridge 171:3a7713b1edbc 6305
AnnaBridge 171:3a7713b1edbc 6306 /*! @name SOPT1 - System Options Register 1 */
AnnaBridge 171:3a7713b1edbc 6307 #define SIM_SOPT1_OSC32KOUT_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 6308 #define SIM_SOPT1_OSC32KOUT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6309 #define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK)
AnnaBridge 171:3a7713b1edbc 6310 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 6311 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6312 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6313
AnnaBridge 171:3a7713b1edbc 6314 /*! @name SOPT2 - System Options Register 2 */
AnnaBridge 171:3a7713b1edbc 6315 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
AnnaBridge 171:3a7713b1edbc 6316 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6317 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6318 #define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 6319 #define SIM_SOPT2_TPMSRC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6320 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
AnnaBridge 171:3a7713b1edbc 6321 #define SIM_SOPT2_LPUART0SRC_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 6322 #define SIM_SOPT2_LPUART0SRC_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6323 #define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUART0SRC_SHIFT)) & SIM_SOPT2_LPUART0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 6324
AnnaBridge 171:3a7713b1edbc 6325 /*! @name SOPT4 - System Options Register 4 */
AnnaBridge 171:3a7713b1edbc 6326 #define SIM_SOPT4_TPM1CH0SRC_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 6327 #define SIM_SOPT4_TPM1CH0SRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6328 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CH0SRC_SHIFT)) & SIM_SOPT4_TPM1CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 6329 #define SIM_SOPT4_TPM2CH0SRC_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 6330 #define SIM_SOPT4_TPM2CH0SRC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6331 #define SIM_SOPT4_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CH0SRC_SHIFT)) & SIM_SOPT4_TPM2CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 6332 #define SIM_SOPT4_TPM0CLKSEL_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 6333 #define SIM_SOPT4_TPM0CLKSEL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6334 #define SIM_SOPT4_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM0CLKSEL_SHIFT)) & SIM_SOPT4_TPM0CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6335 #define SIM_SOPT4_TPM1CLKSEL_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6336 #define SIM_SOPT4_TPM1CLKSEL_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6337 #define SIM_SOPT4_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM1CLKSEL_SHIFT)) & SIM_SOPT4_TPM1CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6338 #define SIM_SOPT4_TPM2CLKSEL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6339 #define SIM_SOPT4_TPM2CLKSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6340 #define SIM_SOPT4_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_TPM2CLKSEL_SHIFT)) & SIM_SOPT4_TPM2CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6341
AnnaBridge 171:3a7713b1edbc 6342 /*! @name SOPT5 - System Options Register 5 */
AnnaBridge 171:3a7713b1edbc 6343 #define SIM_SOPT5_LPUART0TXSRC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 6344 #define SIM_SOPT5_LPUART0TXSRC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6345 #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 6346 #define SIM_SOPT5_LPUART0RXSRC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6347 #define SIM_SOPT5_LPUART0RXSRC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6348 #define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 6349 #define SIM_SOPT5_LPUART0ODE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 6350 #define SIM_SOPT5_LPUART0ODE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6351 #define SIM_SOPT5_LPUART0ODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0ODE_SHIFT)) & SIM_SOPT5_LPUART0ODE_MASK)
AnnaBridge 171:3a7713b1edbc 6352
AnnaBridge 171:3a7713b1edbc 6353 /*! @name SOPT7 - System Options Register 7 */
AnnaBridge 171:3a7713b1edbc 6354 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 6355 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6356 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6357 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6358 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6359 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6360 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6361 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6362 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
AnnaBridge 171:3a7713b1edbc 6363
AnnaBridge 171:3a7713b1edbc 6364 /*! @name SDID - System Device Identification Register */
AnnaBridge 171:3a7713b1edbc 6365 #define SIM_SDID_PINID_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 6366 #define SIM_SDID_PINID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6367 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
AnnaBridge 171:3a7713b1edbc 6368 #define SIM_SDID_DIEID_MASK (0xF80U)
AnnaBridge 171:3a7713b1edbc 6369 #define SIM_SDID_DIEID_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6370 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
AnnaBridge 171:3a7713b1edbc 6371 #define SIM_SDID_REVID_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 6372 #define SIM_SDID_REVID_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6373 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
AnnaBridge 171:3a7713b1edbc 6374 #define SIM_SDID_SRAMSIZE_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 6375 #define SIM_SDID_SRAMSIZE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6376 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 6377 #define SIM_SDID_SERIESID_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 6378 #define SIM_SDID_SERIESID_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6379 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
AnnaBridge 171:3a7713b1edbc 6380 #define SIM_SDID_SUBFAMID_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 6381 #define SIM_SDID_SUBFAMID_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6382 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
AnnaBridge 171:3a7713b1edbc 6383 #define SIM_SDID_FAMID_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 6384 #define SIM_SDID_FAMID_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6385 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
AnnaBridge 171:3a7713b1edbc 6386
AnnaBridge 171:3a7713b1edbc 6387 /*! @name SCGC4 - System Clock Gating Control Register 4 */
AnnaBridge 171:3a7713b1edbc 6388 #define SIM_SCGC4_CMT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6389 #define SIM_SCGC4_CMT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6390 #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
AnnaBridge 171:3a7713b1edbc 6391 #define SIM_SCGC4_I2C0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6392 #define SIM_SCGC4_I2C0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6393 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
AnnaBridge 171:3a7713b1edbc 6394 #define SIM_SCGC4_I2C1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6395 #define SIM_SCGC4_I2C1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6396 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
AnnaBridge 171:3a7713b1edbc 6397 #define SIM_SCGC4_CMP_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 6398 #define SIM_SCGC4_CMP_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 6399 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
AnnaBridge 171:3a7713b1edbc 6400 #define SIM_SCGC4_VREF_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 6401 #define SIM_SCGC4_VREF_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6402 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
AnnaBridge 171:3a7713b1edbc 6403
AnnaBridge 171:3a7713b1edbc 6404 /*! @name SCGC5 - System Clock Gating Control Register 5 */
AnnaBridge 171:3a7713b1edbc 6405 #define SIM_SCGC5_LPTMR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6406 #define SIM_SCGC5_LPTMR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6407 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
AnnaBridge 171:3a7713b1edbc 6408 #define SIM_SCGC5_TSI_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6409 #define SIM_SCGC5_TSI_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6410 #define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
AnnaBridge 171:3a7713b1edbc 6411 #define SIM_SCGC5_PORTA_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6412 #define SIM_SCGC5_PORTA_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6413 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
AnnaBridge 171:3a7713b1edbc 6414 #define SIM_SCGC5_PORTB_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6415 #define SIM_SCGC5_PORTB_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6416 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
AnnaBridge 171:3a7713b1edbc 6417 #define SIM_SCGC5_PORTC_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6418 #define SIM_SCGC5_PORTC_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6419 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
AnnaBridge 171:3a7713b1edbc 6420 #define SIM_SCGC5_LPUART0_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 6421 #define SIM_SCGC5_LPUART0_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6422 #define SIM_SCGC5_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART0_SHIFT)) & SIM_SCGC5_LPUART0_MASK)
AnnaBridge 171:3a7713b1edbc 6423 #define SIM_SCGC5_LTC_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 6424 #define SIM_SCGC5_LTC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6425 #define SIM_SCGC5_LTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LTC_SHIFT)) & SIM_SCGC5_LTC_MASK)
AnnaBridge 171:3a7713b1edbc 6426 #define SIM_SCGC5_RSIM_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6427 #define SIM_SCGC5_RSIM_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6428 #define SIM_SCGC5_RSIM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_RSIM_SHIFT)) & SIM_SCGC5_RSIM_MASK)
AnnaBridge 171:3a7713b1edbc 6429 #define SIM_SCGC5_DCDC_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6430 #define SIM_SCGC5_DCDC_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6431 #define SIM_SCGC5_DCDC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_DCDC_SHIFT)) & SIM_SCGC5_DCDC_MASK)
AnnaBridge 171:3a7713b1edbc 6432 #define SIM_SCGC5_BTLL_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 6433 #define SIM_SCGC5_BTLL_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6434 #define SIM_SCGC5_BTLL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_BTLL_SHIFT)) & SIM_SCGC5_BTLL_MASK)
AnnaBridge 171:3a7713b1edbc 6435 #define SIM_SCGC5_PHYDIG_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 6436 #define SIM_SCGC5_PHYDIG_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6437 #define SIM_SCGC5_PHYDIG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PHYDIG_SHIFT)) & SIM_SCGC5_PHYDIG_MASK)
AnnaBridge 171:3a7713b1edbc 6438 #define SIM_SCGC5_ZigBee_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 6439 #define SIM_SCGC5_ZigBee_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 6440 #define SIM_SCGC5_ZigBee(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_ZigBee_SHIFT)) & SIM_SCGC5_ZigBee_MASK)
AnnaBridge 171:3a7713b1edbc 6441 #define SIM_SCGC5_ANT_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 6442 #define SIM_SCGC5_ANT_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 6443 #define SIM_SCGC5_ANT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_ANT_SHIFT)) & SIM_SCGC5_ANT_MASK)
AnnaBridge 171:3a7713b1edbc 6444 #define SIM_SCGC5_GEN_FSK_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 6445 #define SIM_SCGC5_GEN_FSK_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 6446 #define SIM_SCGC5_GEN_FSK(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_GEN_FSK_SHIFT)) & SIM_SCGC5_GEN_FSK_MASK)
AnnaBridge 171:3a7713b1edbc 6447
AnnaBridge 171:3a7713b1edbc 6448 /*! @name SCGC6 - System Clock Gating Control Register 6 */
AnnaBridge 171:3a7713b1edbc 6449 #define SIM_SCGC6_FTF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6450 #define SIM_SCGC6_FTF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6451 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
AnnaBridge 171:3a7713b1edbc 6452 #define SIM_SCGC6_DMAMUX_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6453 #define SIM_SCGC6_DMAMUX_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6454 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
AnnaBridge 171:3a7713b1edbc 6455 #define SIM_SCGC6_TRNG_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6456 #define SIM_SCGC6_TRNG_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6457 #define SIM_SCGC6_TRNG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TRNG_SHIFT)) & SIM_SCGC6_TRNG_MASK)
AnnaBridge 171:3a7713b1edbc 6458 #define SIM_SCGC6_SPI0_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 6459 #define SIM_SCGC6_SPI0_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6460 #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
AnnaBridge 171:3a7713b1edbc 6461 #define SIM_SCGC6_SPI1_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 6462 #define SIM_SCGC6_SPI1_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 6463 #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
AnnaBridge 171:3a7713b1edbc 6464 #define SIM_SCGC6_PIT_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 6465 #define SIM_SCGC6_PIT_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 6466 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
AnnaBridge 171:3a7713b1edbc 6467 #define SIM_SCGC6_TPM0_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 6468 #define SIM_SCGC6_TPM0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6469 #define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK)
AnnaBridge 171:3a7713b1edbc 6470 #define SIM_SCGC6_TPM1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6471 #define SIM_SCGC6_TPM1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6472 #define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK)
AnnaBridge 171:3a7713b1edbc 6473 #define SIM_SCGC6_TPM2_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6474 #define SIM_SCGC6_TPM2_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6475 #define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK)
AnnaBridge 171:3a7713b1edbc 6476 #define SIM_SCGC6_ADC0_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 6477 #define SIM_SCGC6_ADC0_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6478 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
AnnaBridge 171:3a7713b1edbc 6479 #define SIM_SCGC6_RTC_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 6480 #define SIM_SCGC6_RTC_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 6481 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
AnnaBridge 171:3a7713b1edbc 6482 #define SIM_SCGC6_DAC0_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 6483 #define SIM_SCGC6_DAC0_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 6484 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
AnnaBridge 171:3a7713b1edbc 6485
AnnaBridge 171:3a7713b1edbc 6486 /*! @name SCGC7 - System Clock Gating Control Register 7 */
AnnaBridge 171:3a7713b1edbc 6487 #define SIM_SCGC7_DMA_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6488 #define SIM_SCGC7_DMA_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6489 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 6490
AnnaBridge 171:3a7713b1edbc 6491 /*! @name CLKDIV1 - System Clock Divider Register 1 */
AnnaBridge 171:3a7713b1edbc 6492 #define SIM_CLKDIV1_OUTDIV4_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 6493 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6494 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
AnnaBridge 171:3a7713b1edbc 6495 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 6496 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6497 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
AnnaBridge 171:3a7713b1edbc 6498
AnnaBridge 171:3a7713b1edbc 6499 /*! @name FCFG1 - Flash Configuration Register 1 */
AnnaBridge 171:3a7713b1edbc 6500 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6501 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6502 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
AnnaBridge 171:3a7713b1edbc 6503 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6504 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6505 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
AnnaBridge 171:3a7713b1edbc 6506 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 6507 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6508 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 6509
AnnaBridge 171:3a7713b1edbc 6510 /*! @name FCFG2 - Flash Configuration Register 2 */
AnnaBridge 171:3a7713b1edbc 6511 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 6512 #define SIM_FCFG2_MAXADDR1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6513 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
AnnaBridge 171:3a7713b1edbc 6514 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
AnnaBridge 171:3a7713b1edbc 6515 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6516 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
AnnaBridge 171:3a7713b1edbc 6517
AnnaBridge 171:3a7713b1edbc 6518 /*! @name UIDMH - Unique Identification Register Mid-High */
AnnaBridge 171:3a7713b1edbc 6519 #define SIM_UIDMH_UID_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6520 #define SIM_UIDMH_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6521 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
AnnaBridge 171:3a7713b1edbc 6522
AnnaBridge 171:3a7713b1edbc 6523 /*! @name UIDML - Unique Identification Register Mid Low */
AnnaBridge 171:3a7713b1edbc 6524 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6525 #define SIM_UIDML_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6526 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
AnnaBridge 171:3a7713b1edbc 6527
AnnaBridge 171:3a7713b1edbc 6528 /*! @name UIDL - Unique Identification Register Low */
AnnaBridge 171:3a7713b1edbc 6529 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6530 #define SIM_UIDL_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6531 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
AnnaBridge 171:3a7713b1edbc 6532
AnnaBridge 171:3a7713b1edbc 6533 /*! @name COPC - COP Control Register */
AnnaBridge 171:3a7713b1edbc 6534 #define SIM_COPC_COPW_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6535 #define SIM_COPC_COPW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6536 #define SIM_COPC_COPW(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPW_SHIFT)) & SIM_COPC_COPW_MASK)
AnnaBridge 171:3a7713b1edbc 6537 #define SIM_COPC_COPCLKS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6538 #define SIM_COPC_COPCLKS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6539 #define SIM_COPC_COPCLKS(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKS_SHIFT)) & SIM_COPC_COPCLKS_MASK)
AnnaBridge 171:3a7713b1edbc 6540 #define SIM_COPC_COPT_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 6541 #define SIM_COPC_COPT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6542 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPT_SHIFT)) & SIM_COPC_COPT_MASK)
AnnaBridge 171:3a7713b1edbc 6543 #define SIM_COPC_COPSTPEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6544 #define SIM_COPC_COPSTPEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6545 #define SIM_COPC_COPSTPEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPSTPEN_SHIFT)) & SIM_COPC_COPSTPEN_MASK)
AnnaBridge 171:3a7713b1edbc 6546 #define SIM_COPC_COPDBGEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6547 #define SIM_COPC_COPDBGEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6548 #define SIM_COPC_COPDBGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPDBGEN_SHIFT)) & SIM_COPC_COPDBGEN_MASK)
AnnaBridge 171:3a7713b1edbc 6549 #define SIM_COPC_COPCLKSEL_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 6550 #define SIM_COPC_COPCLKSEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6551 #define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_COPC_COPCLKSEL_SHIFT)) & SIM_COPC_COPCLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 6552
AnnaBridge 171:3a7713b1edbc 6553 /*! @name SRVCOP - Service COP */
AnnaBridge 171:3a7713b1edbc 6554 #define SIM_SRVCOP_SRVCOP_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6555 #define SIM_SRVCOP_SRVCOP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6556 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRVCOP_SRVCOP_SHIFT)) & SIM_SRVCOP_SRVCOP_MASK)
AnnaBridge 171:3a7713b1edbc 6557
AnnaBridge 171:3a7713b1edbc 6558
AnnaBridge 171:3a7713b1edbc 6559 /*!
AnnaBridge 171:3a7713b1edbc 6560 * @}
AnnaBridge 171:3a7713b1edbc 6561 */ /* end of group SIM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6562
AnnaBridge 171:3a7713b1edbc 6563
AnnaBridge 171:3a7713b1edbc 6564 /* SIM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6565 /** Peripheral SIM base address */
AnnaBridge 171:3a7713b1edbc 6566 #define SIM_BASE (0x40047000u)
AnnaBridge 171:3a7713b1edbc 6567 /** Peripheral SIM base pointer */
AnnaBridge 171:3a7713b1edbc 6568 #define SIM ((SIM_Type *)SIM_BASE)
AnnaBridge 171:3a7713b1edbc 6569 /** Array initializer of SIM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6570 #define SIM_BASE_ADDRS { SIM_BASE }
AnnaBridge 171:3a7713b1edbc 6571 /** Array initializer of SIM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6572 #define SIM_BASE_PTRS { SIM }
AnnaBridge 171:3a7713b1edbc 6573
AnnaBridge 171:3a7713b1edbc 6574 /*!
AnnaBridge 171:3a7713b1edbc 6575 * @}
AnnaBridge 171:3a7713b1edbc 6576 */ /* end of group SIM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6577
AnnaBridge 171:3a7713b1edbc 6578
AnnaBridge 171:3a7713b1edbc 6579 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6580 -- SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6581 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6582
AnnaBridge 171:3a7713b1edbc 6583 /*!
AnnaBridge 171:3a7713b1edbc 6584 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6585 * @{
AnnaBridge 171:3a7713b1edbc 6586 */
AnnaBridge 171:3a7713b1edbc 6587
AnnaBridge 171:3a7713b1edbc 6588 /** SMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6589 typedef struct {
AnnaBridge 171:3a7713b1edbc 6590 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6591 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 6592 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 6593 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 6594 } SMC_Type;
AnnaBridge 171:3a7713b1edbc 6595
AnnaBridge 171:3a7713b1edbc 6596 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6597 -- SMC Register Masks
AnnaBridge 171:3a7713b1edbc 6598 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6599
AnnaBridge 171:3a7713b1edbc 6600 /*!
AnnaBridge 171:3a7713b1edbc 6601 * @addtogroup SMC_Register_Masks SMC Register Masks
AnnaBridge 171:3a7713b1edbc 6602 * @{
AnnaBridge 171:3a7713b1edbc 6603 */
AnnaBridge 171:3a7713b1edbc 6604
AnnaBridge 171:3a7713b1edbc 6605 /*! @name PMPROT - Power Mode Protection register */
AnnaBridge 171:3a7713b1edbc 6606 #define SMC_PMPROT_AVLLS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6607 #define SMC_PMPROT_AVLLS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6608 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
AnnaBridge 171:3a7713b1edbc 6609 #define SMC_PMPROT_ALLS_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6610 #define SMC_PMPROT_ALLS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6611 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
AnnaBridge 171:3a7713b1edbc 6612 #define SMC_PMPROT_AVLP_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6613 #define SMC_PMPROT_AVLP_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6614 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
AnnaBridge 171:3a7713b1edbc 6615
AnnaBridge 171:3a7713b1edbc 6616 /*! @name PMCTRL - Power Mode Control register */
AnnaBridge 171:3a7713b1edbc 6617 #define SMC_PMCTRL_STOPM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 6618 #define SMC_PMCTRL_STOPM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6619 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
AnnaBridge 171:3a7713b1edbc 6620 #define SMC_PMCTRL_STOPA_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6621 #define SMC_PMCTRL_STOPA_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6622 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
AnnaBridge 171:3a7713b1edbc 6623 #define SMC_PMCTRL_RUNM_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 6624 #define SMC_PMCTRL_RUNM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6625 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
AnnaBridge 171:3a7713b1edbc 6626
AnnaBridge 171:3a7713b1edbc 6627 /*! @name STOPCTRL - Stop Control Register */
AnnaBridge 171:3a7713b1edbc 6628 #define SMC_STOPCTRL_LLSM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 6629 #define SMC_STOPCTRL_LLSM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6630 #define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
AnnaBridge 171:3a7713b1edbc 6631 #define SMC_STOPCTRL_RAM2PO_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6632 #define SMC_STOPCTRL_RAM2PO_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6633 #define SMC_STOPCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
AnnaBridge 171:3a7713b1edbc 6634 #define SMC_STOPCTRL_PORPO_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6635 #define SMC_STOPCTRL_PORPO_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6636 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
AnnaBridge 171:3a7713b1edbc 6637 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 6638 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6639 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
AnnaBridge 171:3a7713b1edbc 6640
AnnaBridge 171:3a7713b1edbc 6641 /*! @name PMSTAT - Power Mode Status register */
AnnaBridge 171:3a7713b1edbc 6642 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6643 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6644 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
AnnaBridge 171:3a7713b1edbc 6645
AnnaBridge 171:3a7713b1edbc 6646
AnnaBridge 171:3a7713b1edbc 6647 /*!
AnnaBridge 171:3a7713b1edbc 6648 * @}
AnnaBridge 171:3a7713b1edbc 6649 */ /* end of group SMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6650
AnnaBridge 171:3a7713b1edbc 6651
AnnaBridge 171:3a7713b1edbc 6652 /* SMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6653 /** Peripheral SMC base address */
AnnaBridge 171:3a7713b1edbc 6654 #define SMC_BASE (0x4007E000u)
AnnaBridge 171:3a7713b1edbc 6655 /** Peripheral SMC base pointer */
AnnaBridge 171:3a7713b1edbc 6656 #define SMC ((SMC_Type *)SMC_BASE)
AnnaBridge 171:3a7713b1edbc 6657 /** Array initializer of SMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6658 #define SMC_BASE_ADDRS { SMC_BASE }
AnnaBridge 171:3a7713b1edbc 6659 /** Array initializer of SMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6660 #define SMC_BASE_PTRS { SMC }
AnnaBridge 171:3a7713b1edbc 6661
AnnaBridge 171:3a7713b1edbc 6662 /*!
AnnaBridge 171:3a7713b1edbc 6663 * @}
AnnaBridge 171:3a7713b1edbc 6664 */ /* end of group SMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6665
AnnaBridge 171:3a7713b1edbc 6666
AnnaBridge 171:3a7713b1edbc 6667 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6668 -- SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6669 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6670
AnnaBridge 171:3a7713b1edbc 6671 /*!
AnnaBridge 171:3a7713b1edbc 6672 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6673 * @{
AnnaBridge 171:3a7713b1edbc 6674 */
AnnaBridge 171:3a7713b1edbc 6675
AnnaBridge 171:3a7713b1edbc 6676 /** SPI - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6677 typedef struct {
AnnaBridge 171:3a7713b1edbc 6678 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6679 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 6680 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 6681 union { /* offset: 0xC */
AnnaBridge 171:3a7713b1edbc 6682 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 6683 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 6684 };
AnnaBridge 171:3a7713b1edbc 6685 uint8_t RESERVED_1[24];
AnnaBridge 171:3a7713b1edbc 6686 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 6687 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 6688 union { /* offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 6689 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 6690 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 6691 };
AnnaBridge 171:3a7713b1edbc 6692 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 6693 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 6694 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 6695 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 6696 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 6697 uint8_t RESERVED_2[48];
AnnaBridge 171:3a7713b1edbc 6698 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 6699 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 6700 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 6701 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 6702 } SPI_Type;
AnnaBridge 171:3a7713b1edbc 6703
AnnaBridge 171:3a7713b1edbc 6704 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6705 -- SPI Register Masks
AnnaBridge 171:3a7713b1edbc 6706 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6707
AnnaBridge 171:3a7713b1edbc 6708 /*!
AnnaBridge 171:3a7713b1edbc 6709 * @addtogroup SPI_Register_Masks SPI Register Masks
AnnaBridge 171:3a7713b1edbc 6710 * @{
AnnaBridge 171:3a7713b1edbc 6711 */
AnnaBridge 171:3a7713b1edbc 6712
AnnaBridge 171:3a7713b1edbc 6713 /*! @name MCR - Module Configuration Register */
AnnaBridge 171:3a7713b1edbc 6714 #define SPI_MCR_HALT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6715 #define SPI_MCR_HALT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6716 #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
AnnaBridge 171:3a7713b1edbc 6717 #define SPI_MCR_SMPL_PT_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 6718 #define SPI_MCR_SMPL_PT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6719 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
AnnaBridge 171:3a7713b1edbc 6720 #define SPI_MCR_CLR_RXF_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6721 #define SPI_MCR_CLR_RXF_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6722 #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
AnnaBridge 171:3a7713b1edbc 6723 #define SPI_MCR_CLR_TXF_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6724 #define SPI_MCR_CLR_TXF_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6725 #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
AnnaBridge 171:3a7713b1edbc 6726 #define SPI_MCR_DIS_RXF_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 6727 #define SPI_MCR_DIS_RXF_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6728 #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
AnnaBridge 171:3a7713b1edbc 6729 #define SPI_MCR_DIS_TXF_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 6730 #define SPI_MCR_DIS_TXF_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 6731 #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
AnnaBridge 171:3a7713b1edbc 6732 #define SPI_MCR_MDIS_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 6733 #define SPI_MCR_MDIS_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 6734 #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
AnnaBridge 171:3a7713b1edbc 6735 #define SPI_MCR_DOZE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 6736 #define SPI_MCR_DOZE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 6737 #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
AnnaBridge 171:3a7713b1edbc 6738 #define SPI_MCR_PCSIS_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 6739 #define SPI_MCR_PCSIS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6740 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
AnnaBridge 171:3a7713b1edbc 6741 #define SPI_MCR_ROOE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 6742 #define SPI_MCR_ROOE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6743 #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
AnnaBridge 171:3a7713b1edbc 6744 #define SPI_MCR_MTFE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6745 #define SPI_MCR_MTFE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6746 #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
AnnaBridge 171:3a7713b1edbc 6747 #define SPI_MCR_FRZ_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 6748 #define SPI_MCR_FRZ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6749 #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
AnnaBridge 171:3a7713b1edbc 6750 #define SPI_MCR_DCONF_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 6751 #define SPI_MCR_DCONF_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6752 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
AnnaBridge 171:3a7713b1edbc 6753 #define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 6754 #define SPI_MCR_CONT_SCKE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 6755 #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
AnnaBridge 171:3a7713b1edbc 6756 #define SPI_MCR_MSTR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 6757 #define SPI_MCR_MSTR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 6758 #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
AnnaBridge 171:3a7713b1edbc 6759
AnnaBridge 171:3a7713b1edbc 6760 /*! @name TCR - Transfer Count Register */
AnnaBridge 171:3a7713b1edbc 6761 #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 6762 #define SPI_TCR_SPI_TCNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6763 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
AnnaBridge 171:3a7713b1edbc 6764
AnnaBridge 171:3a7713b1edbc 6765 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
AnnaBridge 171:3a7713b1edbc 6766 #define SPI_CTAR_BR_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 6767 #define SPI_CTAR_BR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6768 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
AnnaBridge 171:3a7713b1edbc 6769 #define SPI_CTAR_DT_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 6770 #define SPI_CTAR_DT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6771 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
AnnaBridge 171:3a7713b1edbc 6772 #define SPI_CTAR_ASC_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 6773 #define SPI_CTAR_ASC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6774 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
AnnaBridge 171:3a7713b1edbc 6775 #define SPI_CTAR_CSSCK_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 6776 #define SPI_CTAR_CSSCK_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6777 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
AnnaBridge 171:3a7713b1edbc 6778 #define SPI_CTAR_PBR_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 6779 #define SPI_CTAR_PBR_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6780 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
AnnaBridge 171:3a7713b1edbc 6781 #define SPI_CTAR_PDT_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 6782 #define SPI_CTAR_PDT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6783 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
AnnaBridge 171:3a7713b1edbc 6784 #define SPI_CTAR_PASC_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 6785 #define SPI_CTAR_PASC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6786 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
AnnaBridge 171:3a7713b1edbc 6787 #define SPI_CTAR_PCSSCK_MASK (0xC00000U)
AnnaBridge 171:3a7713b1edbc 6788 #define SPI_CTAR_PCSSCK_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 6789 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
AnnaBridge 171:3a7713b1edbc 6790 #define SPI_CTAR_LSBFE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 6791 #define SPI_CTAR_LSBFE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6792 #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
AnnaBridge 171:3a7713b1edbc 6793 #define SPI_CTAR_CPHA_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6794 #define SPI_CTAR_CPHA_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6795 #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
AnnaBridge 171:3a7713b1edbc 6796 #define SPI_CTAR_CPOL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6797 #define SPI_CTAR_CPOL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6798 #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
AnnaBridge 171:3a7713b1edbc 6799 #define SPI_CTAR_FMSZ_MASK (0x78000000U)
AnnaBridge 171:3a7713b1edbc 6800 #define SPI_CTAR_FMSZ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6801 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
AnnaBridge 171:3a7713b1edbc 6802 #define SPI_CTAR_DBR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 6803 #define SPI_CTAR_DBR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 6804 #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
AnnaBridge 171:3a7713b1edbc 6805
AnnaBridge 171:3a7713b1edbc 6806 /* The count of SPI_CTAR */
AnnaBridge 171:3a7713b1edbc 6807 #define SPI_CTAR_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 6808
AnnaBridge 171:3a7713b1edbc 6809 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
AnnaBridge 171:3a7713b1edbc 6810 #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6811 #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6812 #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
AnnaBridge 171:3a7713b1edbc 6813 #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6814 #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6815 #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
AnnaBridge 171:3a7713b1edbc 6816 #define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U)
AnnaBridge 171:3a7713b1edbc 6817 #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6818 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
AnnaBridge 171:3a7713b1edbc 6819
AnnaBridge 171:3a7713b1edbc 6820 /* The count of SPI_CTAR_SLAVE */
AnnaBridge 171:3a7713b1edbc 6821 #define SPI_CTAR_SLAVE_COUNT (1U)
AnnaBridge 171:3a7713b1edbc 6822
AnnaBridge 171:3a7713b1edbc 6823 /*! @name SR - Status Register */
AnnaBridge 171:3a7713b1edbc 6824 #define SPI_SR_POPNXTPTR_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 6825 #define SPI_SR_POPNXTPTR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6826 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
AnnaBridge 171:3a7713b1edbc 6827 #define SPI_SR_RXCTR_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 6828 #define SPI_SR_RXCTR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6829 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
AnnaBridge 171:3a7713b1edbc 6830 #define SPI_SR_TXNXTPTR_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 6831 #define SPI_SR_TXNXTPTR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6832 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
AnnaBridge 171:3a7713b1edbc 6833 #define SPI_SR_TXCTR_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 6834 #define SPI_SR_TXCTR_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6835 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
AnnaBridge 171:3a7713b1edbc 6836 #define SPI_SR_RFDF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 6837 #define SPI_SR_RFDF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 6838 #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
AnnaBridge 171:3a7713b1edbc 6839 #define SPI_SR_RFOF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 6840 #define SPI_SR_RFOF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 6841 #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
AnnaBridge 171:3a7713b1edbc 6842 #define SPI_SR_TFFF_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6843 #define SPI_SR_TFFF_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6844 #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
AnnaBridge 171:3a7713b1edbc 6845 #define SPI_SR_TFUF_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 6846 #define SPI_SR_TFUF_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6847 #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
AnnaBridge 171:3a7713b1edbc 6848 #define SPI_SR_EOQF_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 6849 #define SPI_SR_EOQF_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6850 #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
AnnaBridge 171:3a7713b1edbc 6851 #define SPI_SR_TXRXS_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 6852 #define SPI_SR_TXRXS_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 6853 #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
AnnaBridge 171:3a7713b1edbc 6854 #define SPI_SR_TCF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 6855 #define SPI_SR_TCF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 6856 #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 6857
AnnaBridge 171:3a7713b1edbc 6858 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */
AnnaBridge 171:3a7713b1edbc 6859 #define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 6860 #define SPI_RSER_RFDF_DIRS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6861 #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
AnnaBridge 171:3a7713b1edbc 6862 #define SPI_RSER_RFDF_RE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 6863 #define SPI_RSER_RFDF_RE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 6864 #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 6865 #define SPI_RSER_RFOF_RE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 6866 #define SPI_RSER_RFOF_RE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 6867 #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 6868 #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 6869 #define SPI_RSER_TFFF_DIRS_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6870 #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
AnnaBridge 171:3a7713b1edbc 6871 #define SPI_RSER_TFFF_RE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6872 #define SPI_RSER_TFFF_RE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6873 #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 6874 #define SPI_RSER_TFUF_RE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 6875 #define SPI_RSER_TFUF_RE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6876 #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 6877 #define SPI_RSER_EOQF_RE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 6878 #define SPI_RSER_EOQF_RE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6879 #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 6880 #define SPI_RSER_TCF_RE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 6881 #define SPI_RSER_TCF_RE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 6882 #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 6883
AnnaBridge 171:3a7713b1edbc 6884 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
AnnaBridge 171:3a7713b1edbc 6885 #define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6886 #define SPI_PUSHR_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6887 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6888 #define SPI_PUSHR_PCS_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 6889 #define SPI_PUSHR_PCS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6890 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
AnnaBridge 171:3a7713b1edbc 6891 #define SPI_PUSHR_CTCNT_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6892 #define SPI_PUSHR_CTCNT_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6893 #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 6894 #define SPI_PUSHR_EOQ_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 6895 #define SPI_PUSHR_EOQ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6896 #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
AnnaBridge 171:3a7713b1edbc 6897 #define SPI_PUSHR_CTAS_MASK (0x70000000U)
AnnaBridge 171:3a7713b1edbc 6898 #define SPI_PUSHR_CTAS_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6899 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
AnnaBridge 171:3a7713b1edbc 6900 #define SPI_PUSHR_CONT_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 6901 #define SPI_PUSHR_CONT_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 6902 #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
AnnaBridge 171:3a7713b1edbc 6903
AnnaBridge 171:3a7713b1edbc 6904 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
AnnaBridge 171:3a7713b1edbc 6905 #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6906 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6907 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6908
AnnaBridge 171:3a7713b1edbc 6909 /*! @name POPR - POP RX FIFO Register */
AnnaBridge 171:3a7713b1edbc 6910 #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6911 #define SPI_POPR_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6912 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6913
AnnaBridge 171:3a7713b1edbc 6914 /*! @name TXFR0 - Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 6915 #define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6916 #define SPI_TXFR0_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6917 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6918 #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 6919 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6920 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6921
AnnaBridge 171:3a7713b1edbc 6922 /*! @name TXFR1 - Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 6923 #define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6924 #define SPI_TXFR1_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6925 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6926 #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 6927 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6928 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6929
AnnaBridge 171:3a7713b1edbc 6930 /*! @name TXFR2 - Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 6931 #define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6932 #define SPI_TXFR2_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6933 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6934 #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 6935 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6936 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6937
AnnaBridge 171:3a7713b1edbc 6938 /*! @name TXFR3 - Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 6939 #define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6940 #define SPI_TXFR3_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6941 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6942 #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 6943 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6944 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6945
AnnaBridge 171:3a7713b1edbc 6946 /*! @name RXFR0 - Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 6947 #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6948 #define SPI_RXFR0_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6949 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6950
AnnaBridge 171:3a7713b1edbc 6951 /*! @name RXFR1 - Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 6952 #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6953 #define SPI_RXFR1_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6954 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6955
AnnaBridge 171:3a7713b1edbc 6956 /*! @name RXFR2 - Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 6957 #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6958 #define SPI_RXFR2_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6959 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6960
AnnaBridge 171:3a7713b1edbc 6961 /*! @name RXFR3 - Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 6962 #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6963 #define SPI_RXFR3_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6964 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 6965
AnnaBridge 171:3a7713b1edbc 6966
AnnaBridge 171:3a7713b1edbc 6967 /*!
AnnaBridge 171:3a7713b1edbc 6968 * @}
AnnaBridge 171:3a7713b1edbc 6969 */ /* end of group SPI_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6970
AnnaBridge 171:3a7713b1edbc 6971
AnnaBridge 171:3a7713b1edbc 6972 /* SPI - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6973 /** Peripheral SPI0 base address */
AnnaBridge 171:3a7713b1edbc 6974 #define SPI0_BASE (0x4002C000u)
AnnaBridge 171:3a7713b1edbc 6975 /** Peripheral SPI0 base pointer */
AnnaBridge 171:3a7713b1edbc 6976 #define SPI0 ((SPI_Type *)SPI0_BASE)
AnnaBridge 171:3a7713b1edbc 6977 /** Peripheral SPI1 base address */
AnnaBridge 171:3a7713b1edbc 6978 #define SPI1_BASE (0x4002D000u)
AnnaBridge 171:3a7713b1edbc 6979 /** Peripheral SPI1 base pointer */
AnnaBridge 171:3a7713b1edbc 6980 #define SPI1 ((SPI_Type *)SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 6981 /** Array initializer of SPI peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6982 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
AnnaBridge 171:3a7713b1edbc 6983 /** Array initializer of SPI peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6984 #define SPI_BASE_PTRS { SPI0, SPI1 }
AnnaBridge 171:3a7713b1edbc 6985 /** Interrupt vectors for the SPI peripheral type */
AnnaBridge 171:3a7713b1edbc 6986 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
AnnaBridge 171:3a7713b1edbc 6987
AnnaBridge 171:3a7713b1edbc 6988 /*!
AnnaBridge 171:3a7713b1edbc 6989 * @}
AnnaBridge 171:3a7713b1edbc 6990 */ /* end of group SPI_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6991
AnnaBridge 171:3a7713b1edbc 6992
AnnaBridge 171:3a7713b1edbc 6993 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6994 -- TPM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6995 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6996
AnnaBridge 171:3a7713b1edbc 6997 /*!
AnnaBridge 171:3a7713b1edbc 6998 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6999 * @{
AnnaBridge 171:3a7713b1edbc 7000 */
AnnaBridge 171:3a7713b1edbc 7001
AnnaBridge 171:3a7713b1edbc 7002 /** TPM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7003 typedef struct {
AnnaBridge 171:3a7713b1edbc 7004 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7005 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7006 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7007 struct { /* offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 7008 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 7009 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 7010 } CONTROLS[4];
AnnaBridge 171:3a7713b1edbc 7011 uint8_t RESERVED_0[36];
AnnaBridge 171:3a7713b1edbc 7012 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 7013 uint8_t RESERVED_1[16];
AnnaBridge 171:3a7713b1edbc 7014 __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 7015 uint8_t RESERVED_2[8];
AnnaBridge 171:3a7713b1edbc 7016 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 7017 uint8_t RESERVED_3[4];
AnnaBridge 171:3a7713b1edbc 7018 __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 7019 uint8_t RESERVED_4[4];
AnnaBridge 171:3a7713b1edbc 7020 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 7021 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 7022 } TPM_Type;
AnnaBridge 171:3a7713b1edbc 7023
AnnaBridge 171:3a7713b1edbc 7024 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7025 -- TPM Register Masks
AnnaBridge 171:3a7713b1edbc 7026 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7027
AnnaBridge 171:3a7713b1edbc 7028 /*!
AnnaBridge 171:3a7713b1edbc 7029 * @addtogroup TPM_Register_Masks TPM Register Masks
AnnaBridge 171:3a7713b1edbc 7030 * @{
AnnaBridge 171:3a7713b1edbc 7031 */
AnnaBridge 171:3a7713b1edbc 7032
AnnaBridge 171:3a7713b1edbc 7033 /*! @name SC - Status and Control */
AnnaBridge 171:3a7713b1edbc 7034 #define TPM_SC_PS_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 7035 #define TPM_SC_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7036 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
AnnaBridge 171:3a7713b1edbc 7037 #define TPM_SC_CMOD_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 7038 #define TPM_SC_CMOD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7039 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
AnnaBridge 171:3a7713b1edbc 7040 #define TPM_SC_CPWMS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7041 #define TPM_SC_CPWMS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7042 #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
AnnaBridge 171:3a7713b1edbc 7043 #define TPM_SC_TOIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7044 #define TPM_SC_TOIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7045 #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
AnnaBridge 171:3a7713b1edbc 7046 #define TPM_SC_TOF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7047 #define TPM_SC_TOF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7048 #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 7049 #define TPM_SC_DMA_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 7050 #define TPM_SC_DMA_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7051 #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 7052
AnnaBridge 171:3a7713b1edbc 7053 /*! @name CNT - Counter */
AnnaBridge 171:3a7713b1edbc 7054 #define TPM_CNT_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7055 #define TPM_CNT_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7056 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 7057
AnnaBridge 171:3a7713b1edbc 7058 /*! @name MOD - Modulo */
AnnaBridge 171:3a7713b1edbc 7059 #define TPM_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7060 #define TPM_MOD_MOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7061 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
AnnaBridge 171:3a7713b1edbc 7062
AnnaBridge 171:3a7713b1edbc 7063 /*! @name CnSC - Channel (n) Status and Control */
AnnaBridge 171:3a7713b1edbc 7064 #define TPM_CnSC_DMA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7065 #define TPM_CnSC_DMA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7066 #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 7067 #define TPM_CnSC_ELSA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7068 #define TPM_CnSC_ELSA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7069 #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
AnnaBridge 171:3a7713b1edbc 7070 #define TPM_CnSC_ELSB_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7071 #define TPM_CnSC_ELSB_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7072 #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
AnnaBridge 171:3a7713b1edbc 7073 #define TPM_CnSC_MSA_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7074 #define TPM_CnSC_MSA_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7075 #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
AnnaBridge 171:3a7713b1edbc 7076 #define TPM_CnSC_MSB_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7077 #define TPM_CnSC_MSB_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7078 #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
AnnaBridge 171:3a7713b1edbc 7079 #define TPM_CnSC_CHIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7080 #define TPM_CnSC_CHIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7081 #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
AnnaBridge 171:3a7713b1edbc 7082 #define TPM_CnSC_CHF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7083 #define TPM_CnSC_CHF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7084 #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
AnnaBridge 171:3a7713b1edbc 7085
AnnaBridge 171:3a7713b1edbc 7086 /* The count of TPM_CnSC */
AnnaBridge 171:3a7713b1edbc 7087 #define TPM_CnSC_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 7088
AnnaBridge 171:3a7713b1edbc 7089 /*! @name CnV - Channel (n) Value */
AnnaBridge 171:3a7713b1edbc 7090 #define TPM_CnV_VAL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7091 #define TPM_CnV_VAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7092 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 7093
AnnaBridge 171:3a7713b1edbc 7094 /* The count of TPM_CnV */
AnnaBridge 171:3a7713b1edbc 7095 #define TPM_CnV_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 7096
AnnaBridge 171:3a7713b1edbc 7097 /*! @name STATUS - Capture and Compare Status */
AnnaBridge 171:3a7713b1edbc 7098 #define TPM_STATUS_CH0F_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7099 #define TPM_STATUS_CH0F_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7100 #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
AnnaBridge 171:3a7713b1edbc 7101 #define TPM_STATUS_CH1F_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7102 #define TPM_STATUS_CH1F_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7103 #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
AnnaBridge 171:3a7713b1edbc 7104 #define TPM_STATUS_CH2F_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7105 #define TPM_STATUS_CH2F_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7106 #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK)
AnnaBridge 171:3a7713b1edbc 7107 #define TPM_STATUS_CH3F_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7108 #define TPM_STATUS_CH3F_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7109 #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK)
AnnaBridge 171:3a7713b1edbc 7110 #define TPM_STATUS_TOF_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 7111 #define TPM_STATUS_TOF_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7112 #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 7113
AnnaBridge 171:3a7713b1edbc 7114 /*! @name COMBINE - Combine Channel Register */
AnnaBridge 171:3a7713b1edbc 7115 #define TPM_COMBINE_COMBINE0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7116 #define TPM_COMBINE_COMBINE0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7117 #define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
AnnaBridge 171:3a7713b1edbc 7118 #define TPM_COMBINE_COMSWAP0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7119 #define TPM_COMBINE_COMSWAP0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7120 #define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
AnnaBridge 171:3a7713b1edbc 7121 #define TPM_COMBINE_COMBINE1_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 7122 #define TPM_COMBINE_COMBINE1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7123 #define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK)
AnnaBridge 171:3a7713b1edbc 7124 #define TPM_COMBINE_COMSWAP1_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 7125 #define TPM_COMBINE_COMSWAP1_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 7126 #define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK)
AnnaBridge 171:3a7713b1edbc 7127
AnnaBridge 171:3a7713b1edbc 7128 /*! @name POL - Channel Polarity */
AnnaBridge 171:3a7713b1edbc 7129 #define TPM_POL_POL0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7130 #define TPM_POL_POL0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7131 #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
AnnaBridge 171:3a7713b1edbc 7132 #define TPM_POL_POL1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7133 #define TPM_POL_POL1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7134 #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
AnnaBridge 171:3a7713b1edbc 7135 #define TPM_POL_POL2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7136 #define TPM_POL_POL2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7137 #define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK)
AnnaBridge 171:3a7713b1edbc 7138 #define TPM_POL_POL3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7139 #define TPM_POL_POL3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7140 #define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK)
AnnaBridge 171:3a7713b1edbc 7141
AnnaBridge 171:3a7713b1edbc 7142 /*! @name FILTER - Filter Control */
AnnaBridge 171:3a7713b1edbc 7143 #define TPM_FILTER_CH0FVAL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 7144 #define TPM_FILTER_CH0FVAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7145 #define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 7146 #define TPM_FILTER_CH1FVAL_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 7147 #define TPM_FILTER_CH1FVAL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7148 #define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 7149 #define TPM_FILTER_CH2FVAL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 7150 #define TPM_FILTER_CH2FVAL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7151 #define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 7152 #define TPM_FILTER_CH3FVAL_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 7153 #define TPM_FILTER_CH3FVAL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 7154 #define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 7155
AnnaBridge 171:3a7713b1edbc 7156 /*! @name QDCTRL - Quadrature Decoder Control and Status */
AnnaBridge 171:3a7713b1edbc 7157 #define TPM_QDCTRL_QUADEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7158 #define TPM_QDCTRL_QUADEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7159 #define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
AnnaBridge 171:3a7713b1edbc 7160 #define TPM_QDCTRL_TOFDIR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7161 #define TPM_QDCTRL_TOFDIR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7162 #define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
AnnaBridge 171:3a7713b1edbc 7163 #define TPM_QDCTRL_QUADIR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7164 #define TPM_QDCTRL_QUADIR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7165 #define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
AnnaBridge 171:3a7713b1edbc 7166 #define TPM_QDCTRL_QUADMODE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7167 #define TPM_QDCTRL_QUADMODE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7168 #define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
AnnaBridge 171:3a7713b1edbc 7169
AnnaBridge 171:3a7713b1edbc 7170 /*! @name CONF - Configuration */
AnnaBridge 171:3a7713b1edbc 7171 #define TPM_CONF_DOZEEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7172 #define TPM_CONF_DOZEEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7173 #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
AnnaBridge 171:3a7713b1edbc 7174 #define TPM_CONF_DBGMODE_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 7175 #define TPM_CONF_DBGMODE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7176 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
AnnaBridge 171:3a7713b1edbc 7177 #define TPM_CONF_GTBSYNC_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 7178 #define TPM_CONF_GTBSYNC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7179 #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
AnnaBridge 171:3a7713b1edbc 7180 #define TPM_CONF_GTBEEN_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 7181 #define TPM_CONF_GTBEEN_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 7182 #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
AnnaBridge 171:3a7713b1edbc 7183 #define TPM_CONF_CSOT_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 7184 #define TPM_CONF_CSOT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7185 #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
AnnaBridge 171:3a7713b1edbc 7186 #define TPM_CONF_CSOO_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 7187 #define TPM_CONF_CSOO_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 7188 #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
AnnaBridge 171:3a7713b1edbc 7189 #define TPM_CONF_CROT_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 7190 #define TPM_CONF_CROT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 7191 #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
AnnaBridge 171:3a7713b1edbc 7192 #define TPM_CONF_CPOT_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 7193 #define TPM_CONF_CPOT_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 7194 #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
AnnaBridge 171:3a7713b1edbc 7195 #define TPM_CONF_TRGPOL_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 7196 #define TPM_CONF_TRGPOL_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 7197 #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
AnnaBridge 171:3a7713b1edbc 7198 #define TPM_CONF_TRGSRC_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 7199 #define TPM_CONF_TRGSRC_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 7200 #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
AnnaBridge 171:3a7713b1edbc 7201 #define TPM_CONF_TRGSEL_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 7202 #define TPM_CONF_TRGSEL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 7203 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 7204
AnnaBridge 171:3a7713b1edbc 7205
AnnaBridge 171:3a7713b1edbc 7206 /*!
AnnaBridge 171:3a7713b1edbc 7207 * @}
AnnaBridge 171:3a7713b1edbc 7208 */ /* end of group TPM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7209
AnnaBridge 171:3a7713b1edbc 7210
AnnaBridge 171:3a7713b1edbc 7211 /* TPM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7212 /** Peripheral TPM0 base address */
AnnaBridge 171:3a7713b1edbc 7213 #define TPM0_BASE (0x40038000u)
AnnaBridge 171:3a7713b1edbc 7214 /** Peripheral TPM0 base pointer */
AnnaBridge 171:3a7713b1edbc 7215 #define TPM0 ((TPM_Type *)TPM0_BASE)
AnnaBridge 171:3a7713b1edbc 7216 /** Peripheral TPM1 base address */
AnnaBridge 171:3a7713b1edbc 7217 #define TPM1_BASE (0x40039000u)
AnnaBridge 171:3a7713b1edbc 7218 /** Peripheral TPM1 base pointer */
AnnaBridge 171:3a7713b1edbc 7219 #define TPM1 ((TPM_Type *)TPM1_BASE)
AnnaBridge 171:3a7713b1edbc 7220 /** Peripheral TPM2 base address */
AnnaBridge 171:3a7713b1edbc 7221 #define TPM2_BASE (0x4003A000u)
AnnaBridge 171:3a7713b1edbc 7222 /** Peripheral TPM2 base pointer */
AnnaBridge 171:3a7713b1edbc 7223 #define TPM2 ((TPM_Type *)TPM2_BASE)
AnnaBridge 171:3a7713b1edbc 7224 /** Array initializer of TPM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7225 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
AnnaBridge 171:3a7713b1edbc 7226 /** Array initializer of TPM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7227 #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
AnnaBridge 171:3a7713b1edbc 7228 /** Interrupt vectors for the TPM peripheral type */
AnnaBridge 171:3a7713b1edbc 7229 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
AnnaBridge 171:3a7713b1edbc 7230
AnnaBridge 171:3a7713b1edbc 7231 /*!
AnnaBridge 171:3a7713b1edbc 7232 * @}
AnnaBridge 171:3a7713b1edbc 7233 */ /* end of group TPM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7234
AnnaBridge 171:3a7713b1edbc 7235
AnnaBridge 171:3a7713b1edbc 7236 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7237 -- TRNG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7238 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7239
AnnaBridge 171:3a7713b1edbc 7240 /*!
AnnaBridge 171:3a7713b1edbc 7241 * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7242 * @{
AnnaBridge 171:3a7713b1edbc 7243 */
AnnaBridge 171:3a7713b1edbc 7244
AnnaBridge 171:3a7713b1edbc 7245 /** TRNG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7246 typedef struct {
AnnaBridge 171:3a7713b1edbc 7247 __IO uint32_t MCTL; /**< Miscellaneous Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7248 __IO uint32_t SCMISC; /**< Statistical Check Miscellaneous Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7249 __IO uint32_t PKRRNG; /**< Poker Range Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7250 union { /* offset: 0xC */
AnnaBridge 171:3a7713b1edbc 7251 __IO uint32_t PKRMAX; /**< Poker Maximum Limit Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 7252 __I uint32_t PKRSQ; /**< Poker Square Calculation Result Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 7253 };
AnnaBridge 171:3a7713b1edbc 7254 __IO uint32_t SDCTL; /**< Seed Control Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 7255 union { /* offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 7256 __IO uint32_t SBLIM; /**< Sparse Bit Limit Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 7257 __I uint32_t TOTSAM; /**< Total Samples Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 7258 };
AnnaBridge 171:3a7713b1edbc 7259 __IO uint32_t FRQMIN; /**< Frequency Count Minimum Limit Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 7260 union { /* offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 7261 __I uint32_t FRQCNT; /**< Frequency Count Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 7262 __IO uint32_t FRQMAX; /**< Frequency Count Maximum Limit Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 7263 };
AnnaBridge 171:3a7713b1edbc 7264 union { /* offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 7265 __I uint32_t SCMC; /**< Statistical Check Monobit Count Register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 7266 __IO uint32_t SCML; /**< Statistical Check Monobit Limit Register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 7267 };
AnnaBridge 171:3a7713b1edbc 7268 union { /* offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 7269 __I uint32_t SCR1C; /**< Statistical Check Run Length 1 Count Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 7270 __IO uint32_t SCR1L; /**< Statistical Check Run Length 1 Limit Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 7271 };
AnnaBridge 171:3a7713b1edbc 7272 union { /* offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 7273 __I uint32_t SCR2C; /**< Statistical Check Run Length 2 Count Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 7274 __IO uint32_t SCR2L; /**< Statistical Check Run Length 2 Limit Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 7275 };
AnnaBridge 171:3a7713b1edbc 7276 union { /* offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 7277 __I uint32_t SCR3C; /**< Statistical Check Run Length 3 Count Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 7278 __IO uint32_t SCR3L; /**< Statistical Check Run Length 3 Limit Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 7279 };
AnnaBridge 171:3a7713b1edbc 7280 union { /* offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 7281 __I uint32_t SCR4C; /**< Statistical Check Run Length 4 Count Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 7282 __IO uint32_t SCR4L; /**< Statistical Check Run Length 4 Limit Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 7283 };
AnnaBridge 171:3a7713b1edbc 7284 union { /* offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 7285 __I uint32_t SCR5C; /**< Statistical Check Run Length 5 Count Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 7286 __IO uint32_t SCR5L; /**< Statistical Check Run Length 5 Limit Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 7287 };
AnnaBridge 171:3a7713b1edbc 7288 union { /* offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 7289 __I uint32_t SCR6PC; /**< Statistical Check Run Length 6+ Count Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 7290 __IO uint32_t SCR6PL; /**< Statistical Check Run Length 6+ Limit Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 7291 };
AnnaBridge 171:3a7713b1edbc 7292 __I uint32_t STATUS; /**< Status Register, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 7293 __I uint32_t ENT[16]; /**< Entropy Read Register, array offset: 0x40, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 7294 __I uint32_t PKRCNT10; /**< Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 7295 __I uint32_t PKRCNT32; /**< Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 7296 __I uint32_t PKRCNT54; /**< Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 7297 __I uint32_t PKRCNT76; /**< Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 7298 __I uint32_t PKRCNT98; /**< Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 7299 __I uint32_t PKRCNTBA; /**< Statistical Check Poker Count B and A Register, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 7300 __I uint32_t PKRCNTDC; /**< Statistical Check Poker Count D and C Register, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 7301 __I uint32_t PKRCNTFE; /**< Statistical Check Poker Count F and E Register, offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 7302 uint8_t RESERVED_0[16];
AnnaBridge 171:3a7713b1edbc 7303 __IO uint32_t SEC_CFG; /**< Security Configuration Register, offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 7304 __IO uint32_t INT_CTRL; /**< Interrupt Control Register, offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 7305 __IO uint32_t INT_MASK; /**< Mask Register, offset: 0xB8 */
AnnaBridge 171:3a7713b1edbc 7306 __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0xBC */
AnnaBridge 171:3a7713b1edbc 7307 uint8_t RESERVED_1[48];
AnnaBridge 171:3a7713b1edbc 7308 __I uint32_t VID1; /**< Version ID Register (MS), offset: 0xF0 */
AnnaBridge 171:3a7713b1edbc 7309 __I uint32_t VID2; /**< Version ID Register (LS), offset: 0xF4 */
AnnaBridge 171:3a7713b1edbc 7310 } TRNG_Type;
AnnaBridge 171:3a7713b1edbc 7311
AnnaBridge 171:3a7713b1edbc 7312 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7313 -- TRNG Register Masks
AnnaBridge 171:3a7713b1edbc 7314 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7315
AnnaBridge 171:3a7713b1edbc 7316 /*!
AnnaBridge 171:3a7713b1edbc 7317 * @addtogroup TRNG_Register_Masks TRNG Register Masks
AnnaBridge 171:3a7713b1edbc 7318 * @{
AnnaBridge 171:3a7713b1edbc 7319 */
AnnaBridge 171:3a7713b1edbc 7320
AnnaBridge 171:3a7713b1edbc 7321 /*! @name MCTL - Miscellaneous Control Register */
AnnaBridge 171:3a7713b1edbc 7322 #define TRNG_MCTL_SAMP_MODE_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 7323 #define TRNG_MCTL_SAMP_MODE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7324 #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 7325 #define TRNG_MCTL_OSC_DIV_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 7326 #define TRNG_MCTL_OSC_DIV_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7327 #define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK)
AnnaBridge 171:3a7713b1edbc 7328 #define TRNG_MCTL_UNUSED_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7329 #define TRNG_MCTL_UNUSED_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7330 #define TRNG_MCTL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED_SHIFT)) & TRNG_MCTL_UNUSED_MASK)
AnnaBridge 171:3a7713b1edbc 7331 #define TRNG_MCTL_TRNG_ACC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7332 #define TRNG_MCTL_TRNG_ACC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7333 #define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 7334 #define TRNG_MCTL_RST_DEF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7335 #define TRNG_MCTL_RST_DEF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7336 #define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK)
AnnaBridge 171:3a7713b1edbc 7337 #define TRNG_MCTL_FOR_SCLK_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7338 #define TRNG_MCTL_FOR_SCLK_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7339 #define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK)
AnnaBridge 171:3a7713b1edbc 7340 #define TRNG_MCTL_FCT_FAIL_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 7341 #define TRNG_MCTL_FCT_FAIL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7342 #define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK)
AnnaBridge 171:3a7713b1edbc 7343 #define TRNG_MCTL_FCT_VAL_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 7344 #define TRNG_MCTL_FCT_VAL_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 7345 #define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 7346 #define TRNG_MCTL_ENT_VAL_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 7347 #define TRNG_MCTL_ENT_VAL_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 7348 #define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 7349 #define TRNG_MCTL_TST_OUT_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 7350 #define TRNG_MCTL_TST_OUT_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 7351 #define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK)
AnnaBridge 171:3a7713b1edbc 7352 #define TRNG_MCTL_ERR_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 7353 #define TRNG_MCTL_ERR_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 7354 #define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK)
AnnaBridge 171:3a7713b1edbc 7355 #define TRNG_MCTL_TSTOP_OK_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 7356 #define TRNG_MCTL_TSTOP_OK_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 7357 #define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK)
AnnaBridge 171:3a7713b1edbc 7358 #define TRNG_MCTL_PRGM_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 7359 #define TRNG_MCTL_PRGM_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7360 #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK)
AnnaBridge 171:3a7713b1edbc 7361
AnnaBridge 171:3a7713b1edbc 7362 /*! @name SCMISC - Statistical Check Miscellaneous Register */
AnnaBridge 171:3a7713b1edbc 7363 #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7364 #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7365 #define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK)
AnnaBridge 171:3a7713b1edbc 7366 #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 7367 #define TRNG_SCMISC_RTY_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7368 #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7369
AnnaBridge 171:3a7713b1edbc 7370 /*! @name PKRRNG - Poker Range Register */
AnnaBridge 171:3a7713b1edbc 7371 #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7372 #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7373 #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK)
AnnaBridge 171:3a7713b1edbc 7374
AnnaBridge 171:3a7713b1edbc 7375 /*! @name PKRMAX - Poker Maximum Limit Register */
AnnaBridge 171:3a7713b1edbc 7376 #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7377 #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7378 #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK)
AnnaBridge 171:3a7713b1edbc 7379
AnnaBridge 171:3a7713b1edbc 7380 /*! @name PKRSQ - Poker Square Calculation Result Register */
AnnaBridge 171:3a7713b1edbc 7381 #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7382 #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7383 #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK)
AnnaBridge 171:3a7713b1edbc 7384
AnnaBridge 171:3a7713b1edbc 7385 /*! @name SDCTL - Seed Control Register */
AnnaBridge 171:3a7713b1edbc 7386 #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7387 #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7388 #define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK)
AnnaBridge 171:3a7713b1edbc 7389 #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7390 #define TRNG_SDCTL_ENT_DLY_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7391 #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK)
AnnaBridge 171:3a7713b1edbc 7392
AnnaBridge 171:3a7713b1edbc 7393 /*! @name SBLIM - Sparse Bit Limit Register */
AnnaBridge 171:3a7713b1edbc 7394 #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 7395 #define TRNG_SBLIM_SB_LIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7396 #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK)
AnnaBridge 171:3a7713b1edbc 7397
AnnaBridge 171:3a7713b1edbc 7398 /*! @name TOTSAM - Total Samples Register */
AnnaBridge 171:3a7713b1edbc 7399 #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU)
AnnaBridge 171:3a7713b1edbc 7400 #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7401 #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK)
AnnaBridge 171:3a7713b1edbc 7402
AnnaBridge 171:3a7713b1edbc 7403 /*! @name FRQMIN - Frequency Count Minimum Limit Register */
AnnaBridge 171:3a7713b1edbc 7404 #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
AnnaBridge 171:3a7713b1edbc 7405 #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7406 #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK)
AnnaBridge 171:3a7713b1edbc 7407
AnnaBridge 171:3a7713b1edbc 7408 /*! @name FRQCNT - Frequency Count Register */
AnnaBridge 171:3a7713b1edbc 7409 #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU)
AnnaBridge 171:3a7713b1edbc 7410 #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7411 #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7412
AnnaBridge 171:3a7713b1edbc 7413 /*! @name FRQMAX - Frequency Count Maximum Limit Register */
AnnaBridge 171:3a7713b1edbc 7414 #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
AnnaBridge 171:3a7713b1edbc 7415 #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7416 #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK)
AnnaBridge 171:3a7713b1edbc 7417
AnnaBridge 171:3a7713b1edbc 7418 /*! @name SCMC - Statistical Check Monobit Count Register */
AnnaBridge 171:3a7713b1edbc 7419 #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7420 #define TRNG_SCMC_MONO_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7421 #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7422
AnnaBridge 171:3a7713b1edbc 7423 /*! @name SCML - Statistical Check Monobit Limit Register */
AnnaBridge 171:3a7713b1edbc 7424 #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7425 #define TRNG_SCML_MONO_MAX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7426 #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK)
AnnaBridge 171:3a7713b1edbc 7427 #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7428 #define TRNG_SCML_MONO_RNG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7429 #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK)
AnnaBridge 171:3a7713b1edbc 7430
AnnaBridge 171:3a7713b1edbc 7431 /*! @name SCR1C - Statistical Check Run Length 1 Count Register */
AnnaBridge 171:3a7713b1edbc 7432 #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU)
AnnaBridge 171:3a7713b1edbc 7433 #define TRNG_SCR1C_R1_0_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7434 #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7435 #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U)
AnnaBridge 171:3a7713b1edbc 7436 #define TRNG_SCR1C_R1_1_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7437 #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7438
AnnaBridge 171:3a7713b1edbc 7439 /*! @name SCR1L - Statistical Check Run Length 1 Limit Register */
AnnaBridge 171:3a7713b1edbc 7440 #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU)
AnnaBridge 171:3a7713b1edbc 7441 #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7442 #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK)
AnnaBridge 171:3a7713b1edbc 7443 #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U)
AnnaBridge 171:3a7713b1edbc 7444 #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7445 #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK)
AnnaBridge 171:3a7713b1edbc 7446
AnnaBridge 171:3a7713b1edbc 7447 /*! @name SCR2C - Statistical Check Run Length 2 Count Register */
AnnaBridge 171:3a7713b1edbc 7448 #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU)
AnnaBridge 171:3a7713b1edbc 7449 #define TRNG_SCR2C_R2_0_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7450 #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7451 #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U)
AnnaBridge 171:3a7713b1edbc 7452 #define TRNG_SCR2C_R2_1_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7453 #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7454
AnnaBridge 171:3a7713b1edbc 7455 /*! @name SCR2L - Statistical Check Run Length 2 Limit Register */
AnnaBridge 171:3a7713b1edbc 7456 #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU)
AnnaBridge 171:3a7713b1edbc 7457 #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7458 #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK)
AnnaBridge 171:3a7713b1edbc 7459 #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U)
AnnaBridge 171:3a7713b1edbc 7460 #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7461 #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK)
AnnaBridge 171:3a7713b1edbc 7462
AnnaBridge 171:3a7713b1edbc 7463 /*! @name SCR3C - Statistical Check Run Length 3 Count Register */
AnnaBridge 171:3a7713b1edbc 7464 #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 7465 #define TRNG_SCR3C_R3_0_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7466 #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7467 #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U)
AnnaBridge 171:3a7713b1edbc 7468 #define TRNG_SCR3C_R3_1_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7469 #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7470
AnnaBridge 171:3a7713b1edbc 7471 /*! @name SCR3L - Statistical Check Run Length 3 Limit Register */
AnnaBridge 171:3a7713b1edbc 7472 #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 7473 #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7474 #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK)
AnnaBridge 171:3a7713b1edbc 7475 #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U)
AnnaBridge 171:3a7713b1edbc 7476 #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7477 #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK)
AnnaBridge 171:3a7713b1edbc 7478
AnnaBridge 171:3a7713b1edbc 7479 /*! @name SCR4C - Statistical Check Run Length 4 Count Register */
AnnaBridge 171:3a7713b1edbc 7480 #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 7481 #define TRNG_SCR4C_R4_0_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7482 #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7483 #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 7484 #define TRNG_SCR4C_R4_1_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7485 #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7486
AnnaBridge 171:3a7713b1edbc 7487 /*! @name SCR4L - Statistical Check Run Length 4 Limit Register */
AnnaBridge 171:3a7713b1edbc 7488 #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 7489 #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7490 #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK)
AnnaBridge 171:3a7713b1edbc 7491 #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 7492 #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7493 #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK)
AnnaBridge 171:3a7713b1edbc 7494
AnnaBridge 171:3a7713b1edbc 7495 /*! @name SCR5C - Statistical Check Run Length 5 Count Register */
AnnaBridge 171:3a7713b1edbc 7496 #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU)
AnnaBridge 171:3a7713b1edbc 7497 #define TRNG_SCR5C_R5_0_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7498 #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7499 #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U)
AnnaBridge 171:3a7713b1edbc 7500 #define TRNG_SCR5C_R5_1_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7501 #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7502
AnnaBridge 171:3a7713b1edbc 7503 /*! @name SCR5L - Statistical Check Run Length 5 Limit Register */
AnnaBridge 171:3a7713b1edbc 7504 #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU)
AnnaBridge 171:3a7713b1edbc 7505 #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7506 #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK)
AnnaBridge 171:3a7713b1edbc 7507 #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U)
AnnaBridge 171:3a7713b1edbc 7508 #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7509 #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK)
AnnaBridge 171:3a7713b1edbc 7510
AnnaBridge 171:3a7713b1edbc 7511 /*! @name SCR6PC - Statistical Check Run Length 6+ Count Register */
AnnaBridge 171:3a7713b1edbc 7512 #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU)
AnnaBridge 171:3a7713b1edbc 7513 #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7514 #define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7515 #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U)
AnnaBridge 171:3a7713b1edbc 7516 #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7517 #define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7518
AnnaBridge 171:3a7713b1edbc 7519 /*! @name SCR6PL - Statistical Check Run Length 6+ Limit Register */
AnnaBridge 171:3a7713b1edbc 7520 #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU)
AnnaBridge 171:3a7713b1edbc 7521 #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7522 #define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK)
AnnaBridge 171:3a7713b1edbc 7523 #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
AnnaBridge 171:3a7713b1edbc 7524 #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7525 #define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK)
AnnaBridge 171:3a7713b1edbc 7526
AnnaBridge 171:3a7713b1edbc 7527 /*! @name STATUS - Status Register */
AnnaBridge 171:3a7713b1edbc 7528 #define TRNG_STATUS_TF1BR0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7529 #define TRNG_STATUS_TF1BR0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7530 #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK)
AnnaBridge 171:3a7713b1edbc 7531 #define TRNG_STATUS_TF1BR1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7532 #define TRNG_STATUS_TF1BR1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7533 #define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK)
AnnaBridge 171:3a7713b1edbc 7534 #define TRNG_STATUS_TF2BR0_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7535 #define TRNG_STATUS_TF2BR0_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7536 #define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK)
AnnaBridge 171:3a7713b1edbc 7537 #define TRNG_STATUS_TF2BR1_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7538 #define TRNG_STATUS_TF2BR1_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7539 #define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK)
AnnaBridge 171:3a7713b1edbc 7540 #define TRNG_STATUS_TF3BR0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7541 #define TRNG_STATUS_TF3BR0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7542 #define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK)
AnnaBridge 171:3a7713b1edbc 7543 #define TRNG_STATUS_TF3BR1_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7544 #define TRNG_STATUS_TF3BR1_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7545 #define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK)
AnnaBridge 171:3a7713b1edbc 7546 #define TRNG_STATUS_TF4BR0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7547 #define TRNG_STATUS_TF4BR0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7548 #define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK)
AnnaBridge 171:3a7713b1edbc 7549 #define TRNG_STATUS_TF4BR1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7550 #define TRNG_STATUS_TF4BR1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7551 #define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK)
AnnaBridge 171:3a7713b1edbc 7552 #define TRNG_STATUS_TF5BR0_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 7553 #define TRNG_STATUS_TF5BR0_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7554 #define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK)
AnnaBridge 171:3a7713b1edbc 7555 #define TRNG_STATUS_TF5BR1_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 7556 #define TRNG_STATUS_TF5BR1_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 7557 #define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK)
AnnaBridge 171:3a7713b1edbc 7558 #define TRNG_STATUS_TF6PBR0_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 7559 #define TRNG_STATUS_TF6PBR0_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 7560 #define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK)
AnnaBridge 171:3a7713b1edbc 7561 #define TRNG_STATUS_TF6PBR1_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 7562 #define TRNG_STATUS_TF6PBR1_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 7563 #define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK)
AnnaBridge 171:3a7713b1edbc 7564 #define TRNG_STATUS_TFSB_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 7565 #define TRNG_STATUS_TFSB_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 7566 #define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK)
AnnaBridge 171:3a7713b1edbc 7567 #define TRNG_STATUS_TFLR_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 7568 #define TRNG_STATUS_TFLR_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 7569 #define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK)
AnnaBridge 171:3a7713b1edbc 7570 #define TRNG_STATUS_TFP_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 7571 #define TRNG_STATUS_TFP_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 7572 #define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK)
AnnaBridge 171:3a7713b1edbc 7573 #define TRNG_STATUS_TFMB_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 7574 #define TRNG_STATUS_TFMB_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 7575 #define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK)
AnnaBridge 171:3a7713b1edbc 7576 #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 7577 #define TRNG_STATUS_RETRY_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7578 #define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7579
AnnaBridge 171:3a7713b1edbc 7580 /*! @name ENT - Entropy Read Register */
AnnaBridge 171:3a7713b1edbc 7581 #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7582 #define TRNG_ENT_ENT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7583 #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK)
AnnaBridge 171:3a7713b1edbc 7584
AnnaBridge 171:3a7713b1edbc 7585 /* The count of TRNG_ENT */
AnnaBridge 171:3a7713b1edbc 7586 #define TRNG_ENT_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 7587
AnnaBridge 171:3a7713b1edbc 7588 /*! @name PKRCNT10 - Statistical Check Poker Count 1 and 0 Register */
AnnaBridge 171:3a7713b1edbc 7589 #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7590 #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7591 #define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7592 #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7593 #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7594 #define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7595
AnnaBridge 171:3a7713b1edbc 7596 /*! @name PKRCNT32 - Statistical Check Poker Count 3 and 2 Register */
AnnaBridge 171:3a7713b1edbc 7597 #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7598 #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7599 #define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7600 #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7601 #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7602 #define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7603
AnnaBridge 171:3a7713b1edbc 7604 /*! @name PKRCNT54 - Statistical Check Poker Count 5 and 4 Register */
AnnaBridge 171:3a7713b1edbc 7605 #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7606 #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7607 #define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7608 #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7609 #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7610 #define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7611
AnnaBridge 171:3a7713b1edbc 7612 /*! @name PKRCNT76 - Statistical Check Poker Count 7 and 6 Register */
AnnaBridge 171:3a7713b1edbc 7613 #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7614 #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7615 #define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7616 #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7617 #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7618 #define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7619
AnnaBridge 171:3a7713b1edbc 7620 /*! @name PKRCNT98 - Statistical Check Poker Count 9 and 8 Register */
AnnaBridge 171:3a7713b1edbc 7621 #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7622 #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7623 #define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7624 #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7625 #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7626 #define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7627
AnnaBridge 171:3a7713b1edbc 7628 /*! @name PKRCNTBA - Statistical Check Poker Count B and A Register */
AnnaBridge 171:3a7713b1edbc 7629 #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7630 #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7631 #define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7632 #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7633 #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7634 #define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7635
AnnaBridge 171:3a7713b1edbc 7636 /*! @name PKRCNTDC - Statistical Check Poker Count D and C Register */
AnnaBridge 171:3a7713b1edbc 7637 #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7638 #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7639 #define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7640 #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7641 #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7642 #define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7643
AnnaBridge 171:3a7713b1edbc 7644 /*! @name PKRCNTFE - Statistical Check Poker Count F and E Register */
AnnaBridge 171:3a7713b1edbc 7645 #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7646 #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7647 #define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7648 #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7649 #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7650 #define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK)
AnnaBridge 171:3a7713b1edbc 7651
AnnaBridge 171:3a7713b1edbc 7652 /*! @name SEC_CFG - Security Configuration Register */
AnnaBridge 171:3a7713b1edbc 7653 #define TRNG_SEC_CFG_SH0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7654 #define TRNG_SEC_CFG_SH0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7655 #define TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK)
AnnaBridge 171:3a7713b1edbc 7656 #define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7657 #define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7658 #define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK)
AnnaBridge 171:3a7713b1edbc 7659 #define TRNG_SEC_CFG_SK_VAL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7660 #define TRNG_SEC_CFG_SK_VAL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7661 #define TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 7662
AnnaBridge 171:3a7713b1edbc 7663 /*! @name INT_CTRL - Interrupt Control Register */
AnnaBridge 171:3a7713b1edbc 7664 #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7665 #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7666 #define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK)
AnnaBridge 171:3a7713b1edbc 7667 #define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7668 #define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7669 #define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 7670 #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7671 #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7672 #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK)
AnnaBridge 171:3a7713b1edbc 7673 #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U)
AnnaBridge 171:3a7713b1edbc 7674 #define TRNG_INT_CTRL_UNUSED_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7675 #define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK)
AnnaBridge 171:3a7713b1edbc 7676
AnnaBridge 171:3a7713b1edbc 7677 /*! @name INT_MASK - Mask Register */
AnnaBridge 171:3a7713b1edbc 7678 #define TRNG_INT_MASK_HW_ERR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7679 #define TRNG_INT_MASK_HW_ERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7680 #define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK)
AnnaBridge 171:3a7713b1edbc 7681 #define TRNG_INT_MASK_ENT_VAL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7682 #define TRNG_INT_MASK_ENT_VAL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7683 #define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 7684 #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7685 #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7686 #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK)
AnnaBridge 171:3a7713b1edbc 7687
AnnaBridge 171:3a7713b1edbc 7688 /*! @name INT_STATUS - Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 7689 #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7690 #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7691 #define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK)
AnnaBridge 171:3a7713b1edbc 7692 #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7693 #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7694 #define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 7695 #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7696 #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7697 #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK)
AnnaBridge 171:3a7713b1edbc 7698
AnnaBridge 171:3a7713b1edbc 7699 /*! @name VID1 - Version ID Register (MS) */
AnnaBridge 171:3a7713b1edbc 7700 #define TRNG_VID1_MIN_REV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7701 #define TRNG_VID1_MIN_REV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7702 #define TRNG_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MIN_REV_SHIFT)) & TRNG_VID1_MIN_REV_MASK)
AnnaBridge 171:3a7713b1edbc 7703 #define TRNG_VID1_MAJ_REV_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 7704 #define TRNG_VID1_MAJ_REV_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7705 #define TRNG_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_MAJ_REV_SHIFT)) & TRNG_VID1_MAJ_REV_MASK)
AnnaBridge 171:3a7713b1edbc 7706 #define TRNG_VID1_IP_ID_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7707 #define TRNG_VID1_IP_ID_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7708 #define TRNG_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_IP_ID_SHIFT)) & TRNG_VID1_IP_ID_MASK)
AnnaBridge 171:3a7713b1edbc 7709
AnnaBridge 171:3a7713b1edbc 7710 /*! @name VID2 - Version ID Register (LS) */
AnnaBridge 171:3a7713b1edbc 7711 #define TRNG_VID2_CONFIG_OPT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7712 #define TRNG_VID2_CONFIG_OPT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7713 #define TRNG_VID2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_CONFIG_OPT_SHIFT)) & TRNG_VID2_CONFIG_OPT_MASK)
AnnaBridge 171:3a7713b1edbc 7714 #define TRNG_VID2_ECO_REV_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 7715 #define TRNG_VID2_ECO_REV_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7716 #define TRNG_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ECO_REV_SHIFT)) & TRNG_VID2_ECO_REV_MASK)
AnnaBridge 171:3a7713b1edbc 7717 #define TRNG_VID2_INTG_OPT_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 7718 #define TRNG_VID2_INTG_OPT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7719 #define TRNG_VID2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_INTG_OPT_SHIFT)) & TRNG_VID2_INTG_OPT_MASK)
AnnaBridge 171:3a7713b1edbc 7720 #define TRNG_VID2_ERA_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 7721 #define TRNG_VID2_ERA_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 7722 #define TRNG_VID2_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_ERA_SHIFT)) & TRNG_VID2_ERA_MASK)
AnnaBridge 171:3a7713b1edbc 7723
AnnaBridge 171:3a7713b1edbc 7724
AnnaBridge 171:3a7713b1edbc 7725 /*!
AnnaBridge 171:3a7713b1edbc 7726 * @}
AnnaBridge 171:3a7713b1edbc 7727 */ /* end of group TRNG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7728
AnnaBridge 171:3a7713b1edbc 7729
AnnaBridge 171:3a7713b1edbc 7730 /* TRNG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7731 /** Peripheral TRNG0 base address */
AnnaBridge 171:3a7713b1edbc 7732 #define TRNG0_BASE (0x40029000u)
AnnaBridge 171:3a7713b1edbc 7733 /** Peripheral TRNG0 base pointer */
AnnaBridge 171:3a7713b1edbc 7734 #define TRNG0 ((TRNG_Type *)TRNG0_BASE)
AnnaBridge 171:3a7713b1edbc 7735 /** Array initializer of TRNG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7736 #define TRNG_BASE_ADDRS { TRNG0_BASE }
AnnaBridge 171:3a7713b1edbc 7737 /** Array initializer of TRNG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7738 #define TRNG_BASE_PTRS { TRNG0 }
AnnaBridge 171:3a7713b1edbc 7739 /** Interrupt vectors for the TRNG peripheral type */
AnnaBridge 171:3a7713b1edbc 7740 #define TRNG_IRQS { TRNG0_IRQn }
AnnaBridge 171:3a7713b1edbc 7741
AnnaBridge 171:3a7713b1edbc 7742 /*!
AnnaBridge 171:3a7713b1edbc 7743 * @}
AnnaBridge 171:3a7713b1edbc 7744 */ /* end of group TRNG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7745
AnnaBridge 171:3a7713b1edbc 7746
AnnaBridge 171:3a7713b1edbc 7747 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7748 -- TSI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7749 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7750
AnnaBridge 171:3a7713b1edbc 7751 /*!
AnnaBridge 171:3a7713b1edbc 7752 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7753 * @{
AnnaBridge 171:3a7713b1edbc 7754 */
AnnaBridge 171:3a7713b1edbc 7755
AnnaBridge 171:3a7713b1edbc 7756 /** TSI - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7757 typedef struct {
AnnaBridge 171:3a7713b1edbc 7758 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7759 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7760 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7761 } TSI_Type;
AnnaBridge 171:3a7713b1edbc 7762
AnnaBridge 171:3a7713b1edbc 7763 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7764 -- TSI Register Masks
AnnaBridge 171:3a7713b1edbc 7765 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7766
AnnaBridge 171:3a7713b1edbc 7767 /*!
AnnaBridge 171:3a7713b1edbc 7768 * @addtogroup TSI_Register_Masks TSI Register Masks
AnnaBridge 171:3a7713b1edbc 7769 * @{
AnnaBridge 171:3a7713b1edbc 7770 */
AnnaBridge 171:3a7713b1edbc 7771
AnnaBridge 171:3a7713b1edbc 7772 /*! @name GENCS - TSI General Control and Status Register */
AnnaBridge 171:3a7713b1edbc 7773 #define TSI_GENCS_CURSW_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7774 #define TSI_GENCS_CURSW_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7775 #define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
AnnaBridge 171:3a7713b1edbc 7776 #define TSI_GENCS_EOSF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7777 #define TSI_GENCS_EOSF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7778 #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
AnnaBridge 171:3a7713b1edbc 7779 #define TSI_GENCS_SCNIP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7780 #define TSI_GENCS_SCNIP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7781 #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
AnnaBridge 171:3a7713b1edbc 7782 #define TSI_GENCS_STM_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7783 #define TSI_GENCS_STM_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7784 #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
AnnaBridge 171:3a7713b1edbc 7785 #define TSI_GENCS_STPE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7786 #define TSI_GENCS_STPE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7787 #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
AnnaBridge 171:3a7713b1edbc 7788 #define TSI_GENCS_TSIIEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7789 #define TSI_GENCS_TSIIEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7790 #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
AnnaBridge 171:3a7713b1edbc 7791 #define TSI_GENCS_TSIEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7792 #define TSI_GENCS_TSIEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7793 #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
AnnaBridge 171:3a7713b1edbc 7794 #define TSI_GENCS_NSCN_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 7795 #define TSI_GENCS_NSCN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7796 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
AnnaBridge 171:3a7713b1edbc 7797 #define TSI_GENCS_PS_MASK (0xE000U)
AnnaBridge 171:3a7713b1edbc 7798 #define TSI_GENCS_PS_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 7799 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
AnnaBridge 171:3a7713b1edbc 7800 #define TSI_GENCS_EXTCHRG_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 7801 #define TSI_GENCS_EXTCHRG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7802 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
AnnaBridge 171:3a7713b1edbc 7803 #define TSI_GENCS_DVOLT_MASK (0x180000U)
AnnaBridge 171:3a7713b1edbc 7804 #define TSI_GENCS_DVOLT_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 7805 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
AnnaBridge 171:3a7713b1edbc 7806 #define TSI_GENCS_REFCHRG_MASK (0xE00000U)
AnnaBridge 171:3a7713b1edbc 7807 #define TSI_GENCS_REFCHRG_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 7808 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
AnnaBridge 171:3a7713b1edbc 7809 #define TSI_GENCS_MODE_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 7810 #define TSI_GENCS_MODE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 7811 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 7812 #define TSI_GENCS_ESOR_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 7813 #define TSI_GENCS_ESOR_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 7814 #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
AnnaBridge 171:3a7713b1edbc 7815 #define TSI_GENCS_OUTRGF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 7816 #define TSI_GENCS_OUTRGF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 7817 #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
AnnaBridge 171:3a7713b1edbc 7818
AnnaBridge 171:3a7713b1edbc 7819 /*! @name DATA - TSI DATA Register */
AnnaBridge 171:3a7713b1edbc 7820 #define TSI_DATA_TSICNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7821 #define TSI_DATA_TSICNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7822 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
AnnaBridge 171:3a7713b1edbc 7823 #define TSI_DATA_SWTS_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 7824 #define TSI_DATA_SWTS_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 7825 #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
AnnaBridge 171:3a7713b1edbc 7826 #define TSI_DATA_DMAEN_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 7827 #define TSI_DATA_DMAEN_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 7828 #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 7829 #define TSI_DATA_TSICH_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 7830 #define TSI_DATA_TSICH_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 7831 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
AnnaBridge 171:3a7713b1edbc 7832
AnnaBridge 171:3a7713b1edbc 7833 /*! @name TSHD - TSI Threshold Register */
AnnaBridge 171:3a7713b1edbc 7834 #define TSI_TSHD_THRESL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7835 #define TSI_TSHD_THRESL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7836 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
AnnaBridge 171:3a7713b1edbc 7837 #define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 7838 #define TSI_TSHD_THRESH_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7839 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 7840
AnnaBridge 171:3a7713b1edbc 7841
AnnaBridge 171:3a7713b1edbc 7842 /*!
AnnaBridge 171:3a7713b1edbc 7843 * @}
AnnaBridge 171:3a7713b1edbc 7844 */ /* end of group TSI_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7845
AnnaBridge 171:3a7713b1edbc 7846
AnnaBridge 171:3a7713b1edbc 7847 /* TSI - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7848 /** Peripheral TSI0 base address */
AnnaBridge 171:3a7713b1edbc 7849 #define TSI0_BASE (0x40045000u)
AnnaBridge 171:3a7713b1edbc 7850 /** Peripheral TSI0 base pointer */
AnnaBridge 171:3a7713b1edbc 7851 #define TSI0 ((TSI_Type *)TSI0_BASE)
AnnaBridge 171:3a7713b1edbc 7852 /** Array initializer of TSI peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7853 #define TSI_BASE_ADDRS { TSI0_BASE }
AnnaBridge 171:3a7713b1edbc 7854 /** Array initializer of TSI peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7855 #define TSI_BASE_PTRS { TSI0 }
AnnaBridge 171:3a7713b1edbc 7856 /** Interrupt vectors for the TSI peripheral type */
AnnaBridge 171:3a7713b1edbc 7857 #define TSI_IRQS { TSI0_IRQn }
AnnaBridge 171:3a7713b1edbc 7858
AnnaBridge 171:3a7713b1edbc 7859 /*!
AnnaBridge 171:3a7713b1edbc 7860 * @}
AnnaBridge 171:3a7713b1edbc 7861 */ /* end of group TSI_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7862
AnnaBridge 171:3a7713b1edbc 7863
AnnaBridge 171:3a7713b1edbc 7864 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7865 -- VREF Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7866 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7867
AnnaBridge 171:3a7713b1edbc 7868 /*!
AnnaBridge 171:3a7713b1edbc 7869 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7870 * @{
AnnaBridge 171:3a7713b1edbc 7871 */
AnnaBridge 171:3a7713b1edbc 7872
AnnaBridge 171:3a7713b1edbc 7873 /** VREF - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7874 typedef struct {
AnnaBridge 171:3a7713b1edbc 7875 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7876 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 7877 } VREF_Type;
AnnaBridge 171:3a7713b1edbc 7878
AnnaBridge 171:3a7713b1edbc 7879 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7880 -- VREF Register Masks
AnnaBridge 171:3a7713b1edbc 7881 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7882
AnnaBridge 171:3a7713b1edbc 7883 /*!
AnnaBridge 171:3a7713b1edbc 7884 * @addtogroup VREF_Register_Masks VREF Register Masks
AnnaBridge 171:3a7713b1edbc 7885 * @{
AnnaBridge 171:3a7713b1edbc 7886 */
AnnaBridge 171:3a7713b1edbc 7887
AnnaBridge 171:3a7713b1edbc 7888 /*! @name TRM - VREF Trim Register */
AnnaBridge 171:3a7713b1edbc 7889 #define VREF_TRM_TRIM_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 7890 #define VREF_TRM_TRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7891 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 7892 #define VREF_TRM_CHOPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7893 #define VREF_TRM_CHOPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7894 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
AnnaBridge 171:3a7713b1edbc 7895
AnnaBridge 171:3a7713b1edbc 7896 /*! @name SC - VREF Status and Control Register */
AnnaBridge 171:3a7713b1edbc 7897 #define VREF_SC_MODE_LV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 7898 #define VREF_SC_MODE_LV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7899 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
AnnaBridge 171:3a7713b1edbc 7900 #define VREF_SC_VREFST_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7901 #define VREF_SC_VREFST_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7902 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
AnnaBridge 171:3a7713b1edbc 7903 #define VREF_SC_ICOMPEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7904 #define VREF_SC_ICOMPEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7905 #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
AnnaBridge 171:3a7713b1edbc 7906 #define VREF_SC_REGEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7907 #define VREF_SC_REGEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7908 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
AnnaBridge 171:3a7713b1edbc 7909 #define VREF_SC_VREFEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7910 #define VREF_SC_VREFEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7911 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
AnnaBridge 171:3a7713b1edbc 7912
AnnaBridge 171:3a7713b1edbc 7913
AnnaBridge 171:3a7713b1edbc 7914 /*!
AnnaBridge 171:3a7713b1edbc 7915 * @}
AnnaBridge 171:3a7713b1edbc 7916 */ /* end of group VREF_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7917
AnnaBridge 171:3a7713b1edbc 7918
AnnaBridge 171:3a7713b1edbc 7919 /* VREF - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7920 /** Peripheral VREF base address */
AnnaBridge 171:3a7713b1edbc 7921 #define VREF_BASE (0x40074000u)
AnnaBridge 171:3a7713b1edbc 7922 /** Peripheral VREF base pointer */
AnnaBridge 171:3a7713b1edbc 7923 #define VREF ((VREF_Type *)VREF_BASE)
AnnaBridge 171:3a7713b1edbc 7924 /** Array initializer of VREF peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7925 #define VREF_BASE_ADDRS { VREF_BASE }
AnnaBridge 171:3a7713b1edbc 7926 /** Array initializer of VREF peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7927 #define VREF_BASE_PTRS { VREF }
AnnaBridge 171:3a7713b1edbc 7928
AnnaBridge 171:3a7713b1edbc 7929 /*!
AnnaBridge 171:3a7713b1edbc 7930 * @}
AnnaBridge 171:3a7713b1edbc 7931 */ /* end of group VREF_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7932
AnnaBridge 171:3a7713b1edbc 7933
AnnaBridge 171:3a7713b1edbc 7934 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7935 -- XCVR_ANALOG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7936 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7937
AnnaBridge 171:3a7713b1edbc 7938 /*!
AnnaBridge 171:3a7713b1edbc 7939 * @addtogroup XCVR_ANALOG_Peripheral_Access_Layer XCVR_ANALOG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7940 * @{
AnnaBridge 171:3a7713b1edbc 7941 */
AnnaBridge 171:3a7713b1edbc 7942
AnnaBridge 171:3a7713b1edbc 7943 /** XCVR_ANALOG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7944 typedef struct {
AnnaBridge 171:3a7713b1edbc 7945 __IO uint32_t BB_LDO_1; /**< RF Analog Baseband LDO Control 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7946 __IO uint32_t BB_LDO_2; /**< RF Analog Baseband LDO Control 2, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7947 __IO uint32_t RX_ADC; /**< RF Analog ADC Control, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7948 __IO uint32_t RX_BBA; /**< RF Analog BBA Control, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 7949 __IO uint32_t RX_LNA; /**< RF Analog LNA Control, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 7950 __IO uint32_t RX_TZA; /**< RF Analog TZA Control, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 7951 __IO uint32_t RX_AUXPLL; /**< RF Analog Aux PLL Control, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 7952 __IO uint32_t SY_CTRL_1; /**< RF Analog Synthesizer Control 1, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 7953 __IO uint32_t SY_CTRL_2; /**< RF Analog Synthesizer Control 2, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 7954 __IO uint32_t TX_DAC_PA; /**< RF Analog TX HPM DAC and PA Control, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 7955 __IO uint32_t BALUN_TX; /**< RF Analog Balun TX Mode Control, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 7956 __IO uint32_t BALUN_RX; /**< RF Analog Balun RX Mode Control, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 7957 __I uint32_t DFT_OBSV_1; /**< RF Analog DFT Observation Register 1, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 7958 __IO uint32_t DFT_OBSV_2; /**< RF Analog DFT Observation Register 2, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 7959 } XCVR_ANALOG_Type;
AnnaBridge 171:3a7713b1edbc 7960
AnnaBridge 171:3a7713b1edbc 7961 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7962 -- XCVR_ANALOG Register Masks
AnnaBridge 171:3a7713b1edbc 7963 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7964
AnnaBridge 171:3a7713b1edbc 7965 /*!
AnnaBridge 171:3a7713b1edbc 7966 * @addtogroup XCVR_ANALOG_Register_Masks XCVR_ANALOG Register Masks
AnnaBridge 171:3a7713b1edbc 7967 * @{
AnnaBridge 171:3a7713b1edbc 7968 */
AnnaBridge 171:3a7713b1edbc 7969
AnnaBridge 171:3a7713b1edbc 7970 /*! @name BB_LDO_1 - RF Analog Baseband LDO Control 1 */
AnnaBridge 171:3a7713b1edbc 7971 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7972 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7973 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_BYP_MASK)
AnnaBridge 171:3a7713b1edbc 7974 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7975 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7976 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 7977 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 7978 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7979 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 7980 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 7981 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7982 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_ADCDAC_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 7983 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 7984 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7985 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_BYP_MASK)
AnnaBridge 171:3a7713b1edbc 7986 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 7987 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 7988 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 7989 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_MASK (0xC00U)
AnnaBridge 171:3a7713b1edbc 7990 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 7991 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 7992 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 7993 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 7994 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_BBA_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 7995 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 7996 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7997 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_BYP_MASK)
AnnaBridge 171:3a7713b1edbc 7998 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 7999 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 8000 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8001 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 8002 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 8003 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8004 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK (0x700000U)
AnnaBridge 171:3a7713b1edbc 8005 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8006 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 8007 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8008 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8009 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_BYP_MASK)
AnnaBridge 171:3a7713b1edbc 8010 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 8011 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 8012 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8013 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 8014 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 8015 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8016 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_MASK (0x70000000U)
AnnaBridge 171:3a7713b1edbc 8017 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8018 #define XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_1_BB_LDO_HF_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 8019
AnnaBridge 171:3a7713b1edbc 8020 /*! @name BB_LDO_2 - RF Analog Baseband LDO Control 2 */
AnnaBridge 171:3a7713b1edbc 8021 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8022 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8023 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_BYP_MASK)
AnnaBridge 171:3a7713b1edbc 8024 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8025 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8026 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8027 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8028 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8029 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8030 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 8031 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8032 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_PD_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 8033 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 8034 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8035 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCO_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8036 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 8037 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 8038 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_BYP_MASK)
AnnaBridge 171:3a7713b1edbc 8039 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 8040 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 8041 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8042 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 8043 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8044 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 8045 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 8046 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8047 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8048 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_MASK (0x60000U)
AnnaBridge 171:3a7713b1edbc 8049 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 8050 #define XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_SHIFT)) & XCVR_ANALOG_BB_LDO_2_BB_LDO_VTREF_TC_MASK)
AnnaBridge 171:3a7713b1edbc 8051
AnnaBridge 171:3a7713b1edbc 8052 /*! @name RX_ADC - RF Analog ADC Control */
AnnaBridge 171:3a7713b1edbc 8053 #define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8054 #define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8055 #define XCVR_ANALOG_RX_ADC_RX_ADC_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_BUMP_MASK)
AnnaBridge 171:3a7713b1edbc 8056 #define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 8057 #define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8058 #define XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_FS_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 8059 #define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 8060 #define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 8061 #define XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_I_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8062 #define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 8063 #define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 8064 #define XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_Q_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8065 #define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 8066 #define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8067 #define XCVR_ANALOG_RX_ADC_RX_ADC_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_SHIFT)) & XCVR_ANALOG_RX_ADC_RX_ADC_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8068
AnnaBridge 171:3a7713b1edbc 8069 /*! @name RX_BBA - RF Analog BBA Control */
AnnaBridge 171:3a7713b1edbc 8070 #define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 8071 #define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8072 #define XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 8073 #define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8074 #define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8075 #define XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_CUR_BUMP_MASK)
AnnaBridge 171:3a7713b1edbc 8076 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8077 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8078 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL1_MASK)
AnnaBridge 171:3a7713b1edbc 8079 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8080 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8081 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL2_MASK)
AnnaBridge 171:3a7713b1edbc 8082 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8083 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8084 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL3_MASK)
AnnaBridge 171:3a7713b1edbc 8085 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8086 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8087 #define XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_DIAGSEL4_MASK)
AnnaBridge 171:3a7713b1edbc 8088 #define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 8089 #define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8090 #define XCVR_ANALOG_RX_BBA_RX_BBA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8091 #define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK (0x7000000U)
AnnaBridge 171:3a7713b1edbc 8092 #define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8093 #define XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 8094 #define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_MASK (0x70000000U)
AnnaBridge 171:3a7713b1edbc 8095 #define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8096 #define XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_SHIFT)) & XCVR_ANALOG_RX_BBA_RX_BBA2_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8097
AnnaBridge 171:3a7713b1edbc 8098 /*! @name RX_LNA - RF Analog LNA Control */
AnnaBridge 171:3a7713b1edbc 8099 #define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 8100 #define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8101 #define XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK)
AnnaBridge 171:3a7713b1edbc 8102 #define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8103 #define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8104 #define XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_HG_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8105 #define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8106 #define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8107 #define XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_HIZ_ENABLE_MASK)
AnnaBridge 171:3a7713b1edbc 8108 #define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8109 #define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8110 #define XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_LG_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8111 #define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 8112 #define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8113 #define XCVR_ANALOG_RX_LNA_RX_LNA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_LNA_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8114 #define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 8115 #define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8116 #define XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_MIXER_BUMP_MASK)
AnnaBridge 171:3a7713b1edbc 8117 #define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 8118 #define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8119 #define XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_SHIFT)) & XCVR_ANALOG_RX_LNA_RX_MIXER_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8120
AnnaBridge 171:3a7713b1edbc 8121 /*! @name RX_TZA - RF Analog TZA Control */
AnnaBridge 171:3a7713b1edbc 8122 #define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 8123 #define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8124 #define XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 8125 #define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8126 #define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8127 #define XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_CUR_BUMP_MASK)
AnnaBridge 171:3a7713b1edbc 8128 #define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8129 #define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8130 #define XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_GAIN_BUMP_MASK)
AnnaBridge 171:3a7713b1edbc 8131 #define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 8132 #define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8133 #define XCVR_ANALOG_RX_TZA_RX_TZA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8134 #define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8135 #define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8136 #define XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA1_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8137 #define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 8138 #define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 8139 #define XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA2_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8140 #define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 8141 #define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 8142 #define XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA3_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8143 #define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 8144 #define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 8145 #define XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_TZA_RX_TZA4_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8146
AnnaBridge 171:3a7713b1edbc 8147 /*! @name RX_AUXPLL - RF Analog Aux PLL Control */
AnnaBridge 171:3a7713b1edbc 8148 #define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 8149 #define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8150 #define XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_BIAS_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 8151 #define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8152 #define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8153 #define XCVR_ANALOG_RX_AUXPLL_DIAGSEL1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_DIAGSEL1_MASK)
AnnaBridge 171:3a7713b1edbc 8154 #define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8155 #define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8156 #define XCVR_ANALOG_RX_AUXPLL_DIAGSEL2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_DIAGSEL2_MASK)
AnnaBridge 171:3a7713b1edbc 8157 #define XCVR_ANALOG_RX_AUXPLL_LF_CNTL_MASK (0xE0U)
AnnaBridge 171:3a7713b1edbc 8158 #define XCVR_ANALOG_RX_AUXPLL_LF_CNTL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8159 #define XCVR_ANALOG_RX_AUXPLL_LF_CNTL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_LF_CNTL_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_LF_CNTL_MASK)
AnnaBridge 171:3a7713b1edbc 8160 #define XCVR_ANALOG_RX_AUXPLL_SPARE_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 8161 #define XCVR_ANALOG_RX_AUXPLL_SPARE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8162 #define XCVR_ANALOG_RX_AUXPLL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_SPARE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8163 #define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 8164 #define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8165 #define XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK)
AnnaBridge 171:3a7713b1edbc 8166 #define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 8167 #define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8168 #define XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_VTUNE_TESTMODE_MASK)
AnnaBridge 171:3a7713b1edbc 8169 #define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 8170 #define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8171 #define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_BIAST_MASK)
AnnaBridge 171:3a7713b1edbc 8172 #define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_MASK (0x7000000U)
AnnaBridge 171:3a7713b1edbc 8173 #define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8174 #define XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_BAL_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8175 #define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 8176 #define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8177 #define XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_SHIFT)) & XCVR_ANALOG_RX_AUXPLL_RXTX_RCCAL_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8178
AnnaBridge 171:3a7713b1edbc 8179 /*! @name SY_CTRL_1 - RF Analog Synthesizer Control 1 */
AnnaBridge 171:3a7713b1edbc 8180 #define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8181 #define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8182 #define XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_DIVN_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8183 #define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8184 #define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8185 #define XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_FCAL_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8186 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 8187 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8188 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_FDBK_MASK)
AnnaBridge 171:3a7713b1edbc 8189 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8190 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8191 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_RX_MASK)
AnnaBridge 171:3a7713b1edbc 8192 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 8193 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8194 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_BUMP_RTLO_TX_MASK)
AnnaBridge 171:3a7713b1edbc 8195 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 8196 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 8197 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8198 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 8199 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8200 #define XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LO_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8201 #define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 8202 #define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8203 #define XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK)
AnnaBridge 171:3a7713b1edbc 8204 #define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 8205 #define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 8206 #define XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_LPF_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8207 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 8208 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8209 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8210 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_MASK (0x600000U)
AnnaBridge 171:3a7713b1edbc 8211 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 8212 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_TUNE_MASK)
AnnaBridge 171:3a7713b1edbc 8213 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 8214 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 8215 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_PCH_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 8216 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 8217 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8218 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8219 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 8220 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8221 #define XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE_SHIFT)) & XCVR_ANALOG_SY_CTRL_1_SY_PD_VTUNE_OVERRIDE_TEST_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 8222
AnnaBridge 171:3a7713b1edbc 8223 /*! @name SY_CTRL_2 - RF Analog Synthesizer Control 2 */
AnnaBridge 171:3a7713b1edbc 8224 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 8225 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8226 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_BIAS_MASK)
AnnaBridge 171:3a7713b1edbc 8227 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8228 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8229 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8230 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 8231 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8232 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_KV_MASK)
AnnaBridge 171:3a7713b1edbc 8233 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 8234 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8235 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK)
AnnaBridge 171:3a7713b1edbc 8236 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 8237 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8238 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_PK_DET_ON_MASK)
AnnaBridge 171:3a7713b1edbc 8239 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_MASK (0x1C000U)
AnnaBridge 171:3a7713b1edbc 8240 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 8241 #define XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_SHIFT)) & XCVR_ANALOG_SY_CTRL_2_SY_VCO_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8242
AnnaBridge 171:3a7713b1edbc 8243 /*! @name TX_DAC_PA - RF Analog TX HPM DAC and PA Control */
AnnaBridge 171:3a7713b1edbc 8244 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8245 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8246 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_CAP_MASK)
AnnaBridge 171:3a7713b1edbc 8247 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 8248 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8249 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_IDAC_MASK)
AnnaBridge 171:3a7713b1edbc 8250 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8251 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8252 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_BUMP_RLOAD_MASK)
AnnaBridge 171:3a7713b1edbc 8253 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 8254 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 8255 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8256 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 8257 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 8258 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_INVERT_CLK_MASK)
AnnaBridge 171:3a7713b1edbc 8259 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 8260 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 8261 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_OPAMP_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8262 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_MASK (0xE000U)
AnnaBridge 171:3a7713b1edbc 8263 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 8264 #define XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_DAC_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8265 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK (0xE0000U)
AnnaBridge 171:3a7713b1edbc 8266 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 8267 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK)
AnnaBridge 171:3a7713b1edbc 8268 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 8269 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 8270 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_DIAGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8271 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_MASK (0x3800000U)
AnnaBridge 171:3a7713b1edbc 8272 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 8273 #define XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_SHIFT)) & XCVR_ANALOG_TX_DAC_PA_TX_PA_SPARE_MASK)
AnnaBridge 171:3a7713b1edbc 8274
AnnaBridge 171:3a7713b1edbc 8275 /*! @name BALUN_TX - RF Analog Balun TX Mode Control */
AnnaBridge 171:3a7713b1edbc 8276 #define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8277 #define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8278 #define XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_SHIFT)) & XCVR_ANALOG_BALUN_TX_RXTX_BAL_TX_CODE_MASK)
AnnaBridge 171:3a7713b1edbc 8279
AnnaBridge 171:3a7713b1edbc 8280 /*! @name BALUN_RX - RF Analog Balun RX Mode Control */
AnnaBridge 171:3a7713b1edbc 8281 #define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8282 #define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8283 #define XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_SHIFT)) & XCVR_ANALOG_BALUN_RX_RXTX_BAL_RX_CODE_MASK)
AnnaBridge 171:3a7713b1edbc 8284
AnnaBridge 171:3a7713b1edbc 8285 /*! @name DFT_OBSV_1 - RF Analog DFT Observation Register 1 */
AnnaBridge 171:3a7713b1edbc 8286 #define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_MASK (0x7FFFFU)
AnnaBridge 171:3a7713b1edbc 8287 #define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8288 #define XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_SHIFT)) & XCVR_ANALOG_DFT_OBSV_1_DFT_FREQ_COUNTER_MASK)
AnnaBridge 171:3a7713b1edbc 8289 #define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_MASK (0xFF00000U)
AnnaBridge 171:3a7713b1edbc 8290 #define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8291 #define XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_SHIFT)) & XCVR_ANALOG_DFT_OBSV_1_CTUNE_MAX_DIFF_MASK)
AnnaBridge 171:3a7713b1edbc 8292
AnnaBridge 171:3a7713b1edbc 8293 /*! @name DFT_OBSV_2 - RF Analog DFT Observation Register 2 */
AnnaBridge 171:3a7713b1edbc 8294 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_MASK (0x1FFFFU)
AnnaBridge 171:3a7713b1edbc 8295 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8296 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_MASK)
AnnaBridge 171:3a7713b1edbc 8297 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_MASK (0x7F000000U)
AnnaBridge 171:3a7713b1edbc 8298 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8299 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_MAX_DIFF_CH_MASK)
AnnaBridge 171:3a7713b1edbc 8300 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 8301 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 8302 #define XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_SHIFT)) & XCVR_ANALOG_DFT_OBSV_2_SYN_BIST_IGNORE_FAILS_MASK)
AnnaBridge 171:3a7713b1edbc 8303
AnnaBridge 171:3a7713b1edbc 8304
AnnaBridge 171:3a7713b1edbc 8305 /*!
AnnaBridge 171:3a7713b1edbc 8306 * @}
AnnaBridge 171:3a7713b1edbc 8307 */ /* end of group XCVR_ANALOG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8308
AnnaBridge 171:3a7713b1edbc 8309
AnnaBridge 171:3a7713b1edbc 8310 /* XCVR_ANALOG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8311 /** Peripheral XCVR_ANA base address */
AnnaBridge 171:3a7713b1edbc 8312 #define XCVR_ANA_BASE (0x4005C500u)
AnnaBridge 171:3a7713b1edbc 8313 /** Peripheral XCVR_ANA base pointer */
AnnaBridge 171:3a7713b1edbc 8314 #define XCVR_ANA ((XCVR_ANALOG_Type *)XCVR_ANA_BASE)
AnnaBridge 171:3a7713b1edbc 8315 /** Array initializer of XCVR_ANALOG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8316 #define XCVR_ANALOG_BASE_ADDRS { XCVR_ANA_BASE }
AnnaBridge 171:3a7713b1edbc 8317 /** Array initializer of XCVR_ANALOG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8318 #define XCVR_ANALOG_BASE_PTRS { XCVR_ANA }
AnnaBridge 171:3a7713b1edbc 8319
AnnaBridge 171:3a7713b1edbc 8320 /*!
AnnaBridge 171:3a7713b1edbc 8321 * @}
AnnaBridge 171:3a7713b1edbc 8322 */ /* end of group XCVR_ANALOG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8323
AnnaBridge 171:3a7713b1edbc 8324
AnnaBridge 171:3a7713b1edbc 8325 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8326 -- XCVR_CTRL Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8327 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8328
AnnaBridge 171:3a7713b1edbc 8329 /*!
AnnaBridge 171:3a7713b1edbc 8330 * @addtogroup XCVR_CTRL_Peripheral_Access_Layer XCVR_CTRL Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8331 * @{
AnnaBridge 171:3a7713b1edbc 8332 */
AnnaBridge 171:3a7713b1edbc 8333
AnnaBridge 171:3a7713b1edbc 8334 /** XCVR_CTRL - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8335 typedef struct {
AnnaBridge 171:3a7713b1edbc 8336 __IO uint32_t XCVR_CTRL; /**< TRANSCEIVER CONTROL, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8337 __IO uint32_t XCVR_STATUS; /**< TRANSCEIVER STATUS, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 8338 __IO uint32_t BLE_ARB_CTRL; /**< BLE ARBITRATION CONTROL, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 8339 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 8340 __IO uint32_t OVERWRITE_VER; /**< OVERWRITE VERSION, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 8341 __IO uint32_t DMA_CTRL; /**< TRANSCEIVER DMA CONTROL, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 8342 __I uint32_t DMA_DATA; /**< TRANSCEIVER DMA DATA, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 8343 __IO uint32_t DTEST_CTRL; /**< DIGITAL TEST MUX CONTROL, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 8344 __IO uint32_t PACKET_RAM_CTRL; /**< PACKET RAM CONTROL, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 8345 __IO uint32_t FAD_CTRL; /**< FAD CONTROL, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 8346 __IO uint32_t LPPS_CTRL; /**< LOW POWER PREAMBLE SEARCH CONTROL, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 8347 __IO uint32_t RF_NOT_ALLOWED_CTRL; /**< WIFI COEXISTENCE CONTROL, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 8348 __IO uint32_t CRCW_CFG; /**< CRC/WHITENER CONTROL, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 8349 __I uint32_t CRC_EC_MASK; /**< CRC ERROR CORRECTION MASK, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 8350 __I uint32_t CRC_RES_OUT; /**< CRC RESULT, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 8351 } XCVR_CTRL_Type;
AnnaBridge 171:3a7713b1edbc 8352
AnnaBridge 171:3a7713b1edbc 8353 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8354 -- XCVR_CTRL Register Masks
AnnaBridge 171:3a7713b1edbc 8355 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8356
AnnaBridge 171:3a7713b1edbc 8357 /*!
AnnaBridge 171:3a7713b1edbc 8358 * @addtogroup XCVR_CTRL_Register_Masks XCVR_CTRL Register Masks
AnnaBridge 171:3a7713b1edbc 8359 * @{
AnnaBridge 171:3a7713b1edbc 8360 */
AnnaBridge 171:3a7713b1edbc 8361
AnnaBridge 171:3a7713b1edbc 8362 /*! @name XCVR_CTRL - TRANSCEIVER CONTROL */
AnnaBridge 171:3a7713b1edbc 8363 #define XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 8364 #define XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8365 #define XCVR_CTRL_XCVR_CTRL_PROTOCOL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK)
AnnaBridge 171:3a7713b1edbc 8366 #define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 8367 #define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8368 #define XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_SHIFT)) & XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK)
AnnaBridge 171:3a7713b1edbc 8369 #define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 8370 #define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8371 #define XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_SHIFT)) & XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK)
AnnaBridge 171:3a7713b1edbc 8372 #define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 8373 #define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 8374 #define XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_SHIFT)) & XCVR_CTRL_XCVR_CTRL_SOC_RF_OSC_CLK_GATE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 8375 #define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 8376 #define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8377 #define XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 8378 #define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 8379 #define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8380 #define XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 8381 #define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK (0x700000U)
AnnaBridge 171:3a7713b1edbc 8382 #define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8383 #define XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT)) & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 8384
AnnaBridge 171:3a7713b1edbc 8385 /*! @name XCVR_STATUS - TRANSCEIVER STATUS */
AnnaBridge 171:3a7713b1edbc 8386 #define XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8387 #define XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8388 #define XCVR_CTRL_XCVR_STATUS_TSM_COUNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 8389 #define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 8390 #define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8391 #define XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_PLL_SEQ_STATE_MASK)
AnnaBridge 171:3a7713b1edbc 8392 #define XCVR_CTRL_XCVR_STATUS_RX_MODE_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 8393 #define XCVR_CTRL_XCVR_STATUS_RX_MODE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8394 #define XCVR_CTRL_XCVR_STATUS_RX_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_RX_MODE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_RX_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 8395 #define XCVR_CTRL_XCVR_STATUS_TX_MODE_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 8396 #define XCVR_CTRL_XCVR_STATUS_TX_MODE_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 8397 #define XCVR_CTRL_XCVR_STATUS_TX_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TX_MODE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TX_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 8398 #define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 8399 #define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8400 #define XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_SHIFT)) & XCVR_CTRL_XCVR_STATUS_BTLE_SYSCLK_REQ_MASK)
AnnaBridge 171:3a7713b1edbc 8401 #define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 8402 #define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 8403 #define XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_SHIFT)) & XCVR_CTRL_XCVR_STATUS_RIF_LL_ACTIVE_MASK)
AnnaBridge 171:3a7713b1edbc 8404 #define XCVR_CTRL_XCVR_STATUS_XTAL_READY_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 8405 #define XCVR_CTRL_XCVR_STATUS_XTAL_READY_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 8406 #define XCVR_CTRL_XCVR_STATUS_XTAL_READY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_XTAL_READY_SHIFT)) & XCVR_CTRL_XCVR_STATUS_XTAL_READY_MASK)
AnnaBridge 171:3a7713b1edbc 8407 #define XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 8408 #define XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 8409 #define XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK_SHIFT)) & XCVR_CTRL_XCVR_STATUS_SOC_USING_RF_OSC_CLK_MASK)
AnnaBridge 171:3a7713b1edbc 8410 #define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8411 #define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8412 #define XCVR_CTRL_XCVR_STATUS_TSM_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_IRQ0_MASK)
AnnaBridge 171:3a7713b1edbc 8413 #define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 8414 #define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 8415 #define XCVR_CTRL_XCVR_STATUS_TSM_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_SHIFT)) & XCVR_CTRL_XCVR_STATUS_TSM_IRQ1_MASK)
AnnaBridge 171:3a7713b1edbc 8416
AnnaBridge 171:3a7713b1edbc 8417 /*! @name BLE_ARB_CTRL - BLE ARBITRATION CONTROL */
AnnaBridge 171:3a7713b1edbc 8418 #define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8419 #define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8420 #define XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_SHIFT)) & XCVR_CTRL_BLE_ARB_CTRL_BLE_RELINQUISH_MASK)
AnnaBridge 171:3a7713b1edbc 8421 #define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8422 #define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8423 #define XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_SHIFT)) & XCVR_CTRL_BLE_ARB_CTRL_XCVR_BUSY_MASK)
AnnaBridge 171:3a7713b1edbc 8424
AnnaBridge 171:3a7713b1edbc 8425 /*! @name OVERWRITE_VER - OVERWRITE VERSION */
AnnaBridge 171:3a7713b1edbc 8426 #define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8427 #define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8428 #define XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_SHIFT)) & XCVR_CTRL_OVERWRITE_VER_OVERWRITE_VER_MASK)
AnnaBridge 171:3a7713b1edbc 8429
AnnaBridge 171:3a7713b1edbc 8430 /*! @name DMA_CTRL - TRANSCEIVER DMA CONTROL */
AnnaBridge 171:3a7713b1edbc 8431 #define XCVR_CTRL_DMA_CTRL_DMA_PAGE_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 8432 #define XCVR_CTRL_DMA_CTRL_DMA_PAGE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8433 #define XCVR_CTRL_DMA_CTRL_DMA_PAGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_PAGE_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_PAGE_MASK)
AnnaBridge 171:3a7713b1edbc 8434 #define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8435 #define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8436 #define XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_SHIFT)) & XCVR_CTRL_DMA_CTRL_SINGLE_REQ_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 8437 #define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8438 #define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8439 #define XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_SHIFT)) & XCVR_CTRL_DMA_CTRL_BYPASS_DMA_SYNC_MASK)
AnnaBridge 171:3a7713b1edbc 8440 #define XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8441 #define XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8442 #define XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TRIGGERRED_MASK)
AnnaBridge 171:3a7713b1edbc 8443 #define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8444 #define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8445 #define XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TIMED_OUT_MASK)
AnnaBridge 171:3a7713b1edbc 8446 #define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 8447 #define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8448 #define XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_SHIFT)) & XCVR_CTRL_DMA_CTRL_DMA_TIMEOUT_MASK)
AnnaBridge 171:3a7713b1edbc 8449
AnnaBridge 171:3a7713b1edbc 8450 /*! @name DMA_DATA - TRANSCEIVER DMA DATA */
AnnaBridge 171:3a7713b1edbc 8451 #define XCVR_CTRL_DMA_DATA_DMA_DATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8452 #define XCVR_CTRL_DMA_DATA_DMA_DATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8453 #define XCVR_CTRL_DMA_DATA_DMA_DATA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DMA_DATA_DMA_DATA_SHIFT)) & XCVR_CTRL_DMA_DATA_DMA_DATA_MASK)
AnnaBridge 171:3a7713b1edbc 8454
AnnaBridge 171:3a7713b1edbc 8455 /*! @name DTEST_CTRL - DIGITAL TEST MUX CONTROL */
AnnaBridge 171:3a7713b1edbc 8456 #define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 8457 #define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8458 #define XCVR_CTRL_DTEST_CTRL_DTEST_PAGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_PAGE_MASK)
AnnaBridge 171:3a7713b1edbc 8459 #define XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8460 #define XCVR_CTRL_DTEST_CTRL_DTEST_EN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8461 #define XCVR_CTRL_DTEST_CTRL_DTEST_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_EN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK)
AnnaBridge 171:3a7713b1edbc 8462 #define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 8463 #define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8464 #define XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_GPIO0_OVLAY_PIN_MASK)
AnnaBridge 171:3a7713b1edbc 8465 #define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 8466 #define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8467 #define XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT)) & XCVR_CTRL_DTEST_CTRL_GPIO1_OVLAY_PIN_MASK)
AnnaBridge 171:3a7713b1edbc 8468 #define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 8469 #define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8470 #define XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_SHIFT)) & XCVR_CTRL_DTEST_CTRL_TSM_GPIO_OVLAY_MASK)
AnnaBridge 171:3a7713b1edbc 8471 #define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_MASK (0x7000000U)
AnnaBridge 171:3a7713b1edbc 8472 #define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8473 #define XCVR_CTRL_DTEST_CTRL_DTEST_SHFT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_SHIFT)) & XCVR_CTRL_DTEST_CTRL_DTEST_SHFT_MASK)
AnnaBridge 171:3a7713b1edbc 8474 #define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 8475 #define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8476 #define XCVR_CTRL_DTEST_CTRL_RAW_MODE_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_SHIFT)) & XCVR_CTRL_DTEST_CTRL_RAW_MODE_I_MASK)
AnnaBridge 171:3a7713b1edbc 8477 #define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 8478 #define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 8479 #define XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_SHIFT)) & XCVR_CTRL_DTEST_CTRL_RAW_MODE_Q_MASK)
AnnaBridge 171:3a7713b1edbc 8480
AnnaBridge 171:3a7713b1edbc 8481 /*! @name PACKET_RAM_CTRL - PACKET RAM CONTROL */
AnnaBridge 171:3a7713b1edbc 8482 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 8483 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8484 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK)
AnnaBridge 171:3a7713b1edbc 8485 #define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8486 #define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8487 #define XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_PB_PROTECT_MASK)
AnnaBridge 171:3a7713b1edbc 8488 #define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8489 #define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8490 #define XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8491 #define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8492 #define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8493 #define XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_ALL_PROTOCOLS_ALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8494 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8495 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8496 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_TRIGGERRED_MASK)
AnnaBridge 171:3a7713b1edbc 8497 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 8498 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8499 #define XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL_MASK)
AnnaBridge 171:3a7713b1edbc 8500 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 8501 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 8502 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 8503 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 8504 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 8505 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CLK_ON_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 8506 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 8507 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8508 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 8509 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 8510 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 8511 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CLK_ON_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 8512 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 8513 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 8514 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 8515 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 8516 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 8517 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM0_CE_ON_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 8518 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 8519 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8520 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 8521 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 8522 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 8523 #define XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_SHIFT)) & XCVR_CTRL_PACKET_RAM_CTRL_RAM1_CE_ON_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 8524
AnnaBridge 171:3a7713b1edbc 8525 /*! @name FAD_CTRL - FAD CONTROL */
AnnaBridge 171:3a7713b1edbc 8526 #define XCVR_CTRL_FAD_CTRL_FAD_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8527 #define XCVR_CTRL_FAD_CTRL_FAD_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8528 #define XCVR_CTRL_FAD_CTRL_FAD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_FAD_EN_SHIFT)) & XCVR_CTRL_FAD_CTRL_FAD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 8529 #define XCVR_CTRL_FAD_CTRL_ANTX_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8530 #define XCVR_CTRL_FAD_CTRL_ANTX_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8531 #define XCVR_CTRL_FAD_CTRL_ANTX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_MASK)
AnnaBridge 171:3a7713b1edbc 8532 #define XCVR_CTRL_FAD_CTRL_ANTX_EN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 8533 #define XCVR_CTRL_FAD_CTRL_ANTX_EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8534 #define XCVR_CTRL_FAD_CTRL_ANTX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_EN_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_EN_MASK)
AnnaBridge 171:3a7713b1edbc 8535 #define XCVR_CTRL_FAD_CTRL_ANTX_HZ_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8536 #define XCVR_CTRL_FAD_CTRL_ANTX_HZ_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8537 #define XCVR_CTRL_FAD_CTRL_ANTX_HZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_HZ_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_HZ_MASK)
AnnaBridge 171:3a7713b1edbc 8538 #define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8539 #define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8540 #define XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_CTRLMODE_MASK)
AnnaBridge 171:3a7713b1edbc 8541 #define XCVR_CTRL_FAD_CTRL_ANTX_POL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 8542 #define XCVR_CTRL_FAD_CTRL_ANTX_POL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8543 #define XCVR_CTRL_FAD_CTRL_ANTX_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_ANTX_POL_SHIFT)) & XCVR_CTRL_FAD_CTRL_ANTX_POL_MASK)
AnnaBridge 171:3a7713b1edbc 8544 #define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 8545 #define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8546 #define XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_SHIFT)) & XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK)
AnnaBridge 171:3a7713b1edbc 8547
AnnaBridge 171:3a7713b1edbc 8548 /*! @name LPPS_CTRL - LOW POWER PREAMBLE SEARCH CONTROL */
AnnaBridge 171:3a7713b1edbc 8549 #define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8550 #define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8551 #define XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_ENABLE_MASK)
AnnaBridge 171:3a7713b1edbc 8552 #define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8553 #define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8554 #define XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_TZA_ALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8555 #define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8556 #define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8557 #define XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_BBA_ALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8558 #define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8559 #define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8560 #define XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_ADC_ALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8561 #define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8562 #define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8563 #define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_ALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8564 #define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8565 #define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8566 #define XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_PDET_ALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8567 #define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8568 #define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8569 #define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_ALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8570 #define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8571 #define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8572 #define XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_SY_LO_BUF_ALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8573 #define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 8574 #define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8575 #define XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_RX_DIG_ALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8576 #define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 8577 #define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 8578 #define XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DCOC_DIG_ALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 8579 #define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 8580 #define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8581 #define XCVR_CTRL_LPPS_CTRL_LPPS_START_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_START_RX_MASK)
AnnaBridge 171:3a7713b1edbc 8582 #define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 8583 #define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8584 #define XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_SHIFT)) & XCVR_CTRL_LPPS_CTRL_LPPS_DEST_RX_MASK)
AnnaBridge 171:3a7713b1edbc 8585
AnnaBridge 171:3a7713b1edbc 8586 /*! @name RF_NOT_ALLOWED_CTRL - WIFI COEXISTENCE CONTROL */
AnnaBridge 171:3a7713b1edbc 8587 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8588 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8589 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_TX_MASK)
AnnaBridge 171:3a7713b1edbc 8590 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8591 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8592 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_NO_RX_MASK)
AnnaBridge 171:3a7713b1edbc 8593 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8594 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8595 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_ASSERTED_MASK)
AnnaBridge 171:3a7713b1edbc 8596 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8597 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8598 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_TX_ABORT_MASK)
AnnaBridge 171:3a7713b1edbc 8599 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8600 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8601 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_RX_ABORT_MASK)
AnnaBridge 171:3a7713b1edbc 8602 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8603 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8604 #define XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_SHIFT)) & XCVR_CTRL_RF_NOT_ALLOWED_CTRL_RF_NOT_ALLOWED_MASK)
AnnaBridge 171:3a7713b1edbc 8605
AnnaBridge 171:3a7713b1edbc 8606 /*! @name CRCW_CFG - CRC/WHITENER CONTROL */
AnnaBridge 171:3a7713b1edbc 8607 #define XCVR_CTRL_CRCW_CFG_CRCW_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8608 #define XCVR_CTRL_CRCW_CFG_CRCW_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8609 #define XCVR_CTRL_CRCW_CFG_CRCW_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRCW_EN_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRCW_EN_MASK)
AnnaBridge 171:3a7713b1edbc 8610 #define XCVR_CTRL_CRCW_CFG_CRC_ZERO_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8611 #define XCVR_CTRL_CRCW_CFG_CRC_ZERO_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8612 #define XCVR_CTRL_CRCW_CFG_CRC_ZERO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_ZERO_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_ZERO_MASK)
AnnaBridge 171:3a7713b1edbc 8613 #define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8614 #define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8615 #define XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EARLY_FAIL_MASK)
AnnaBridge 171:3a7713b1edbc 8616 #define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8617 #define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8618 #define XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_RES_OUT_VLD_MASK)
AnnaBridge 171:3a7713b1edbc 8619 #define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_MASK (0x7FF0000U)
AnnaBridge 171:3a7713b1edbc 8620 #define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8621 #define XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_OFFSET_MASK)
AnnaBridge 171:3a7713b1edbc 8622 #define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 8623 #define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8624 #define XCVR_CTRL_CRCW_CFG_CRC_EC_DONE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_DONE_MASK)
AnnaBridge 171:3a7713b1edbc 8625 #define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 8626 #define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 8627 #define XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_SHIFT)) & XCVR_CTRL_CRCW_CFG_CRC_EC_FAIL_MASK)
AnnaBridge 171:3a7713b1edbc 8628
AnnaBridge 171:3a7713b1edbc 8629 /*! @name CRC_EC_MASK - CRC ERROR CORRECTION MASK */
AnnaBridge 171:3a7713b1edbc 8630 #define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8631 #define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8632 #define XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_SHIFT)) & XCVR_CTRL_CRC_EC_MASK_CRC_EC_MASK_MASK)
AnnaBridge 171:3a7713b1edbc 8633
AnnaBridge 171:3a7713b1edbc 8634 /*! @name CRC_RES_OUT - CRC RESULT */
AnnaBridge 171:3a7713b1edbc 8635 #define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8636 #define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8637 #define XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_SHIFT)) & XCVR_CTRL_CRC_RES_OUT_CRC_RES_OUT_MASK)
AnnaBridge 171:3a7713b1edbc 8638
AnnaBridge 171:3a7713b1edbc 8639
AnnaBridge 171:3a7713b1edbc 8640 /*!
AnnaBridge 171:3a7713b1edbc 8641 * @}
AnnaBridge 171:3a7713b1edbc 8642 */ /* end of group XCVR_CTRL_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8643
AnnaBridge 171:3a7713b1edbc 8644
AnnaBridge 171:3a7713b1edbc 8645 /* XCVR_CTRL - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8646 /** Peripheral XCVR_MISC base address */
AnnaBridge 171:3a7713b1edbc 8647 #define XCVR_MISC_BASE (0x4005C280u)
AnnaBridge 171:3a7713b1edbc 8648 /** Peripheral XCVR_MISC base pointer */
AnnaBridge 171:3a7713b1edbc 8649 #define XCVR_MISC ((XCVR_CTRL_Type *)XCVR_MISC_BASE)
AnnaBridge 171:3a7713b1edbc 8650 /** Array initializer of XCVR_CTRL peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8651 #define XCVR_CTRL_BASE_ADDRS { XCVR_MISC_BASE }
AnnaBridge 171:3a7713b1edbc 8652 /** Array initializer of XCVR_CTRL peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8653 #define XCVR_CTRL_BASE_PTRS { XCVR_MISC }
AnnaBridge 171:3a7713b1edbc 8654
AnnaBridge 171:3a7713b1edbc 8655 /*!
AnnaBridge 171:3a7713b1edbc 8656 * @}
AnnaBridge 171:3a7713b1edbc 8657 */ /* end of group XCVR_CTRL_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8658
AnnaBridge 171:3a7713b1edbc 8659
AnnaBridge 171:3a7713b1edbc 8660 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8661 -- XCVR_PHY Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8662 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8663
AnnaBridge 171:3a7713b1edbc 8664 /*!
AnnaBridge 171:3a7713b1edbc 8665 * @addtogroup XCVR_PHY_Peripheral_Access_Layer XCVR_PHY Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8666 * @{
AnnaBridge 171:3a7713b1edbc 8667 */
AnnaBridge 171:3a7713b1edbc 8668
AnnaBridge 171:3a7713b1edbc 8669 /** XCVR_PHY - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8670 typedef struct {
AnnaBridge 171:3a7713b1edbc 8671 __IO uint32_t PHY_PRE_REF0; /**< PREAMBLE REFERENCE WAVEFORM 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8672 __IO uint32_t PRE_REF1; /**< PREAMBLE REFERENCE WAVEFORM 1, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 8673 __IO uint32_t PRE_REF2; /**< PREAMBLE REFERENCE WAVEFORM 2, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 8674 uint8_t RESERVED_0[20];
AnnaBridge 171:3a7713b1edbc 8675 __IO uint32_t CFG1; /**< PHY CONFIGURATION REGISTER 1, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 8676 __IO uint32_t CFG2; /**< PHY CONFIGURATION REGISTER 2, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 8677 __IO uint32_t EL_CFG; /**< PHY EARLY/LATE CONFIGURATION REGISTER, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 8678 __IO uint32_t NTW_ADR_BSM; /**< PHY NETWORK ADDRESS FOR BSM, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 8679 __I uint32_t STATUS; /**< PHY STATUS REGISTER, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 8680 } XCVR_PHY_Type;
AnnaBridge 171:3a7713b1edbc 8681
AnnaBridge 171:3a7713b1edbc 8682 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8683 -- XCVR_PHY Register Masks
AnnaBridge 171:3a7713b1edbc 8684 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8685
AnnaBridge 171:3a7713b1edbc 8686 /*!
AnnaBridge 171:3a7713b1edbc 8687 * @addtogroup XCVR_PHY_Register_Masks XCVR_PHY Register Masks
AnnaBridge 171:3a7713b1edbc 8688 * @{
AnnaBridge 171:3a7713b1edbc 8689 */
AnnaBridge 171:3a7713b1edbc 8690
AnnaBridge 171:3a7713b1edbc 8691 /*! @name PHY_PRE_REF0 - PREAMBLE REFERENCE WAVEFORM 0 */
AnnaBridge 171:3a7713b1edbc 8692 #define XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8693 #define XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8694 #define XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0_SHIFT)) & XCVR_PHY_PHY_PRE_REF0_FSK_PREAMBLE_REF0_MASK)
AnnaBridge 171:3a7713b1edbc 8695
AnnaBridge 171:3a7713b1edbc 8696 /*! @name PRE_REF1 - PREAMBLE REFERENCE WAVEFORM 1 */
AnnaBridge 171:3a7713b1edbc 8697 #define XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8698 #define XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8699 #define XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1_SHIFT)) & XCVR_PHY_PRE_REF1_FSK_PREAMBLE_REF1_MASK)
AnnaBridge 171:3a7713b1edbc 8700
AnnaBridge 171:3a7713b1edbc 8701 /*! @name PRE_REF2 - PREAMBLE REFERENCE WAVEFORM 2 */
AnnaBridge 171:3a7713b1edbc 8702 #define XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8703 #define XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8704 #define XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2_SHIFT)) & XCVR_PHY_PRE_REF2_FSK_PREAMBLE_REF2_MASK)
AnnaBridge 171:3a7713b1edbc 8705
AnnaBridge 171:3a7713b1edbc 8706 /*! @name CFG1 - PHY CONFIGURATION REGISTER 1 */
AnnaBridge 171:3a7713b1edbc 8707 #define XCVR_PHY_CFG1_AA_PLAYBACK_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8708 #define XCVR_PHY_CFG1_AA_PLAYBACK_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8709 #define XCVR_PHY_CFG1_AA_PLAYBACK(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_AA_PLAYBACK_SHIFT)) & XCVR_PHY_CFG1_AA_PLAYBACK_MASK)
AnnaBridge 171:3a7713b1edbc 8710 #define XCVR_PHY_CFG1_AA_OUTPUT_SEL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8711 #define XCVR_PHY_CFG1_AA_OUTPUT_SEL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8712 #define XCVR_PHY_CFG1_AA_OUTPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_AA_OUTPUT_SEL_SHIFT)) & XCVR_PHY_CFG1_AA_OUTPUT_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 8713 #define XCVR_PHY_CFG1_FSK_BIT_INVERT_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8714 #define XCVR_PHY_CFG1_FSK_BIT_INVERT_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8715 #define XCVR_PHY_CFG1_FSK_BIT_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_FSK_BIT_INVERT_SHIFT)) & XCVR_PHY_CFG1_FSK_BIT_INVERT_MASK)
AnnaBridge 171:3a7713b1edbc 8716 #define XCVR_PHY_CFG1_RFU00_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8717 #define XCVR_PHY_CFG1_RFU00_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8718 #define XCVR_PHY_CFG1_RFU00(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_RFU00_SHIFT)) & XCVR_PHY_CFG1_RFU00_MASK)
AnnaBridge 171:3a7713b1edbc 8719 #define XCVR_PHY_CFG1_BSM_EN_BLE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8720 #define XCVR_PHY_CFG1_BSM_EN_BLE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8721 #define XCVR_PHY_CFG1_BSM_EN_BLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_BSM_EN_BLE_SHIFT)) & XCVR_PHY_CFG1_BSM_EN_BLE_MASK)
AnnaBridge 171:3a7713b1edbc 8722 #define XCVR_PHY_CFG1_DEMOD_CLK_MODE_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8723 #define XCVR_PHY_CFG1_DEMOD_CLK_MODE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8724 #define XCVR_PHY_CFG1_DEMOD_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_DEMOD_CLK_MODE_SHIFT)) & XCVR_PHY_CFG1_DEMOD_CLK_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 8725 #define XCVR_PHY_CFG1_CTS_THRESH_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 8726 #define XCVR_PHY_CFG1_CTS_THRESH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8727 #define XCVR_PHY_CFG1_CTS_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_CTS_THRESH_SHIFT)) & XCVR_PHY_CFG1_CTS_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 8728 #define XCVR_PHY_CFG1_FSK_FTS_TIMEOUT_MASK (0x700000U)
AnnaBridge 171:3a7713b1edbc 8729 #define XCVR_PHY_CFG1_FSK_FTS_TIMEOUT_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8730 #define XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_FSK_FTS_TIMEOUT_SHIFT)) & XCVR_PHY_CFG1_FSK_FTS_TIMEOUT_MASK)
AnnaBridge 171:3a7713b1edbc 8731 #define XCVR_PHY_CFG1_RFU01_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8732 #define XCVR_PHY_CFG1_RFU01_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8733 #define XCVR_PHY_CFG1_RFU01(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_RFU01_SHIFT)) & XCVR_PHY_CFG1_RFU01_MASK)
AnnaBridge 171:3a7713b1edbc 8734 #define XCVR_PHY_CFG1_RFU02_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 8735 #define XCVR_PHY_CFG1_RFU02_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 8736 #define XCVR_PHY_CFG1_RFU02(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_RFU02_SHIFT)) & XCVR_PHY_CFG1_RFU02_MASK)
AnnaBridge 171:3a7713b1edbc 8737 #define XCVR_PHY_CFG1_BLE_NTW_ADR_THR_MASK (0x70000000U)
AnnaBridge 171:3a7713b1edbc 8738 #define XCVR_PHY_CFG1_BLE_NTW_ADR_THR_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8739 #define XCVR_PHY_CFG1_BLE_NTW_ADR_THR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG1_BLE_NTW_ADR_THR_SHIFT)) & XCVR_PHY_CFG1_BLE_NTW_ADR_THR_MASK)
AnnaBridge 171:3a7713b1edbc 8740
AnnaBridge 171:3a7713b1edbc 8741 /*! @name CFG2 - PHY CONFIGURATION REGISTER 2 */
AnnaBridge 171:3a7713b1edbc 8742 #define XCVR_PHY_CFG2_PHY_FIFO_PRECHG_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 8743 #define XCVR_PHY_CFG2_PHY_FIFO_PRECHG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8744 #define XCVR_PHY_CFG2_PHY_FIFO_PRECHG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_PHY_FIFO_PRECHG_SHIFT)) & XCVR_PHY_CFG2_PHY_FIFO_PRECHG_MASK)
AnnaBridge 171:3a7713b1edbc 8745 #define XCVR_PHY_CFG2_RFU03_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8746 #define XCVR_PHY_CFG2_RFU03_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8747 #define XCVR_PHY_CFG2_RFU03(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU03_SHIFT)) & XCVR_PHY_CFG2_RFU03_MASK)
AnnaBridge 171:3a7713b1edbc 8748 #define XCVR_PHY_CFG2_RFU04_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8749 #define XCVR_PHY_CFG2_RFU04_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8750 #define XCVR_PHY_CFG2_RFU04(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU04_SHIFT)) & XCVR_PHY_CFG2_RFU04_MASK)
AnnaBridge 171:3a7713b1edbc 8751 #define XCVR_PHY_CFG2_RFU05_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8752 #define XCVR_PHY_CFG2_RFU05_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8753 #define XCVR_PHY_CFG2_RFU05(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU05_SHIFT)) & XCVR_PHY_CFG2_RFU05_MASK)
AnnaBridge 171:3a7713b1edbc 8754 #define XCVR_PHY_CFG2_RFU06_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8755 #define XCVR_PHY_CFG2_RFU06_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8756 #define XCVR_PHY_CFG2_RFU06(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU06_SHIFT)) & XCVR_PHY_CFG2_RFU06_MASK)
AnnaBridge 171:3a7713b1edbc 8757 #define XCVR_PHY_CFG2_X2_DEMOD_GAIN_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 8758 #define XCVR_PHY_CFG2_X2_DEMOD_GAIN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8759 #define XCVR_PHY_CFG2_X2_DEMOD_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_X2_DEMOD_GAIN_SHIFT)) & XCVR_PHY_CFG2_X2_DEMOD_GAIN_MASK)
AnnaBridge 171:3a7713b1edbc 8760 #define XCVR_PHY_CFG2_RFU07_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 8761 #define XCVR_PHY_CFG2_RFU07_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8762 #define XCVR_PHY_CFG2_RFU07(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU07_SHIFT)) & XCVR_PHY_CFG2_RFU07_MASK)
AnnaBridge 171:3a7713b1edbc 8763 #define XCVR_PHY_CFG2_RFU08_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 8764 #define XCVR_PHY_CFG2_RFU08_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 8765 #define XCVR_PHY_CFG2_RFU08(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU08_SHIFT)) & XCVR_PHY_CFG2_RFU08_MASK)
AnnaBridge 171:3a7713b1edbc 8766 #define XCVR_PHY_CFG2_RFU09_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 8767 #define XCVR_PHY_CFG2_RFU09_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 8768 #define XCVR_PHY_CFG2_RFU09(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU09_SHIFT)) & XCVR_PHY_CFG2_RFU09_MASK)
AnnaBridge 171:3a7713b1edbc 8769 #define XCVR_PHY_CFG2_RFU10_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 8770 #define XCVR_PHY_CFG2_RFU10_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 8771 #define XCVR_PHY_CFG2_RFU10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU10_SHIFT)) & XCVR_PHY_CFG2_RFU10_MASK)
AnnaBridge 171:3a7713b1edbc 8772 #define XCVR_PHY_CFG2_RFU11_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 8773 #define XCVR_PHY_CFG2_RFU11_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 8774 #define XCVR_PHY_CFG2_RFU11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU11_SHIFT)) & XCVR_PHY_CFG2_RFU11_MASK)
AnnaBridge 171:3a7713b1edbc 8775 #define XCVR_PHY_CFG2_RFU12_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 8776 #define XCVR_PHY_CFG2_RFU12_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 8777 #define XCVR_PHY_CFG2_RFU12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU12_SHIFT)) & XCVR_PHY_CFG2_RFU12_MASK)
AnnaBridge 171:3a7713b1edbc 8778 #define XCVR_PHY_CFG2_RFU13_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 8779 #define XCVR_PHY_CFG2_RFU13_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 8780 #define XCVR_PHY_CFG2_RFU13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU13_SHIFT)) & XCVR_PHY_CFG2_RFU13_MASK)
AnnaBridge 171:3a7713b1edbc 8781 #define XCVR_PHY_CFG2_RFU14_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 8782 #define XCVR_PHY_CFG2_RFU14_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 8783 #define XCVR_PHY_CFG2_RFU14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU14_SHIFT)) & XCVR_PHY_CFG2_RFU14_MASK)
AnnaBridge 171:3a7713b1edbc 8784 #define XCVR_PHY_CFG2_RFU15_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8785 #define XCVR_PHY_CFG2_RFU15_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8786 #define XCVR_PHY_CFG2_RFU15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU15_SHIFT)) & XCVR_PHY_CFG2_RFU15_MASK)
AnnaBridge 171:3a7713b1edbc 8787 #define XCVR_PHY_CFG2_RFU16_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 8788 #define XCVR_PHY_CFG2_RFU16_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 8789 #define XCVR_PHY_CFG2_RFU16(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_RFU16_SHIFT)) & XCVR_PHY_CFG2_RFU16_MASK)
AnnaBridge 171:3a7713b1edbc 8790 #define XCVR_PHY_CFG2_PHY_CLK_ON_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 8791 #define XCVR_PHY_CFG2_PHY_CLK_ON_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 8792 #define XCVR_PHY_CFG2_PHY_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_CFG2_PHY_CLK_ON_SHIFT)) & XCVR_PHY_CFG2_PHY_CLK_ON_MASK)
AnnaBridge 171:3a7713b1edbc 8793
AnnaBridge 171:3a7713b1edbc 8794 /*! @name EL_CFG - PHY EARLY/LATE CONFIGURATION REGISTER */
AnnaBridge 171:3a7713b1edbc 8795 #define XCVR_PHY_EL_CFG_EL_ENABLE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8796 #define XCVR_PHY_EL_CFG_EL_ENABLE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8797 #define XCVR_PHY_EL_CFG_EL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_ENABLE_SHIFT)) & XCVR_PHY_EL_CFG_EL_ENABLE_MASK)
AnnaBridge 171:3a7713b1edbc 8798 #define XCVR_PHY_EL_CFG_EL_ZB_ENABLE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8799 #define XCVR_PHY_EL_CFG_EL_ZB_ENABLE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8800 #define XCVR_PHY_EL_CFG_EL_ZB_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_ZB_ENABLE_SHIFT)) & XCVR_PHY_EL_CFG_EL_ZB_ENABLE_MASK)
AnnaBridge 171:3a7713b1edbc 8801 #define XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8802 #define XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8803 #define XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE_SHIFT)) & XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE_MASK)
AnnaBridge 171:3a7713b1edbc 8804 #define XCVR_PHY_EL_CFG_EL_WIN_SIZE_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 8805 #define XCVR_PHY_EL_CFG_EL_WIN_SIZE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8806 #define XCVR_PHY_EL_CFG_EL_WIN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_WIN_SIZE_SHIFT)) & XCVR_PHY_EL_CFG_EL_WIN_SIZE_MASK)
AnnaBridge 171:3a7713b1edbc 8807 #define XCVR_PHY_EL_CFG_EL_INTERVAL_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 8808 #define XCVR_PHY_EL_CFG_EL_INTERVAL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8809 #define XCVR_PHY_EL_CFG_EL_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_EL_CFG_EL_INTERVAL_SHIFT)) & XCVR_PHY_EL_CFG_EL_INTERVAL_MASK)
AnnaBridge 171:3a7713b1edbc 8810
AnnaBridge 171:3a7713b1edbc 8811 /*! @name NTW_ADR_BSM - PHY NETWORK ADDRESS FOR BSM */
AnnaBridge 171:3a7713b1edbc 8812 #define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8813 #define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8814 #define XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_SHIFT)) & XCVR_PHY_NTW_ADR_BSM_NTW_ADR_BSM_MASK)
AnnaBridge 171:3a7713b1edbc 8815
AnnaBridge 171:3a7713b1edbc 8816 /*! @name STATUS - PHY STATUS REGISTER */
AnnaBridge 171:3a7713b1edbc 8817 #define XCVR_PHY_STATUS_PREAMBLE_FOUND_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8818 #define XCVR_PHY_STATUS_PREAMBLE_FOUND_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8819 #define XCVR_PHY_STATUS_PREAMBLE_FOUND(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_PREAMBLE_FOUND_SHIFT)) & XCVR_PHY_STATUS_PREAMBLE_FOUND_MASK)
AnnaBridge 171:3a7713b1edbc 8820 #define XCVR_PHY_STATUS_AA_SFD_MATCHED_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8821 #define XCVR_PHY_STATUS_AA_SFD_MATCHED_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8822 #define XCVR_PHY_STATUS_AA_SFD_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_AA_SFD_MATCHED_SHIFT)) & XCVR_PHY_STATUS_AA_SFD_MATCHED_MASK)
AnnaBridge 171:3a7713b1edbc 8823 #define XCVR_PHY_STATUS_AA_MATCHED_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 8824 #define XCVR_PHY_STATUS_AA_MATCHED_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8825 #define XCVR_PHY_STATUS_AA_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_AA_MATCHED_SHIFT)) & XCVR_PHY_STATUS_AA_MATCHED_MASK)
AnnaBridge 171:3a7713b1edbc 8826 #define XCVR_PHY_STATUS_HAMMING_DISTANCE_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 8827 #define XCVR_PHY_STATUS_HAMMING_DISTANCE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8828 #define XCVR_PHY_STATUS_HAMMING_DISTANCE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_HAMMING_DISTANCE_SHIFT)) & XCVR_PHY_STATUS_HAMMING_DISTANCE_MASK)
AnnaBridge 171:3a7713b1edbc 8829 #define XCVR_PHY_STATUS_DATA_FIFO_DEPTH_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 8830 #define XCVR_PHY_STATUS_DATA_FIFO_DEPTH_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8831 #define XCVR_PHY_STATUS_DATA_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_DATA_FIFO_DEPTH_SHIFT)) & XCVR_PHY_STATUS_DATA_FIFO_DEPTH_MASK)
AnnaBridge 171:3a7713b1edbc 8832 #define XCVR_PHY_STATUS_CFO_ESTIMATE_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 8833 #define XCVR_PHY_STATUS_CFO_ESTIMATE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8834 #define XCVR_PHY_STATUS_CFO_ESTIMATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PHY_STATUS_CFO_ESTIMATE_SHIFT)) & XCVR_PHY_STATUS_CFO_ESTIMATE_MASK)
AnnaBridge 171:3a7713b1edbc 8835
AnnaBridge 171:3a7713b1edbc 8836
AnnaBridge 171:3a7713b1edbc 8837 /*!
AnnaBridge 171:3a7713b1edbc 8838 * @}
AnnaBridge 171:3a7713b1edbc 8839 */ /* end of group XCVR_PHY_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8840
AnnaBridge 171:3a7713b1edbc 8841
AnnaBridge 171:3a7713b1edbc 8842 /* XCVR_PHY - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8843 /** Peripheral XCVR_PHY base address */
AnnaBridge 171:3a7713b1edbc 8844 #define XCVR_PHY_BASE (0x4005C400u)
AnnaBridge 171:3a7713b1edbc 8845 /** Peripheral XCVR_PHY base pointer */
AnnaBridge 171:3a7713b1edbc 8846 #define XCVR_PHY ((XCVR_PHY_Type *)XCVR_PHY_BASE)
AnnaBridge 171:3a7713b1edbc 8847 /** Array initializer of XCVR_PHY peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8848 #define XCVR_PHY_BASE_ADDRS { XCVR_PHY_BASE }
AnnaBridge 171:3a7713b1edbc 8849 /** Array initializer of XCVR_PHY peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8850 #define XCVR_PHY_BASE_PTRS { XCVR_PHY }
AnnaBridge 171:3a7713b1edbc 8851
AnnaBridge 171:3a7713b1edbc 8852 /*!
AnnaBridge 171:3a7713b1edbc 8853 * @}
AnnaBridge 171:3a7713b1edbc 8854 */ /* end of group XCVR_PHY_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8855
AnnaBridge 171:3a7713b1edbc 8856
AnnaBridge 171:3a7713b1edbc 8857 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8858 -- XCVR_PKT_RAM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8859 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8860
AnnaBridge 171:3a7713b1edbc 8861 /*!
AnnaBridge 171:3a7713b1edbc 8862 * @addtogroup XCVR_PKT_RAM_Peripheral_Access_Layer XCVR_PKT_RAM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8863 * @{
AnnaBridge 171:3a7713b1edbc 8864 */
AnnaBridge 171:3a7713b1edbc 8865
AnnaBridge 171:3a7713b1edbc 8866 /** XCVR_PKT_RAM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8867 typedef struct {
AnnaBridge 171:3a7713b1edbc 8868 __IO uint16_t PACKET_RAM_0[544]; /**< Shared Packet RAM for multiple Link Layer usage., array offset: 0x0, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 8869 __IO uint16_t PACKET_RAM_1[544]; /**< Shared Packet RAM for multiple Link Layer usage., array offset: 0x440, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 8870 } XCVR_PKT_RAM_Type;
AnnaBridge 171:3a7713b1edbc 8871
AnnaBridge 171:3a7713b1edbc 8872 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8873 -- XCVR_PKT_RAM Register Masks
AnnaBridge 171:3a7713b1edbc 8874 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8875
AnnaBridge 171:3a7713b1edbc 8876 /*!
AnnaBridge 171:3a7713b1edbc 8877 * @addtogroup XCVR_PKT_RAM_Register_Masks XCVR_PKT_RAM Register Masks
AnnaBridge 171:3a7713b1edbc 8878 * @{
AnnaBridge 171:3a7713b1edbc 8879 */
AnnaBridge 171:3a7713b1edbc 8880
AnnaBridge 171:3a7713b1edbc 8881 /*! @name PACKET_RAM_0 - Shared Packet RAM for multiple Link Layer usage. */
AnnaBridge 171:3a7713b1edbc 8882 #define XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8883 #define XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8884 #define XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE(x) (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_0_LSBYTE_MASK)
AnnaBridge 171:3a7713b1edbc 8885 #define XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 8886 #define XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8887 #define XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE(x) (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_0_MSBYTE_MASK)
AnnaBridge 171:3a7713b1edbc 8888
AnnaBridge 171:3a7713b1edbc 8889 /* The count of XCVR_PKT_RAM_PACKET_RAM_0 */
AnnaBridge 171:3a7713b1edbc 8890 #define XCVR_PKT_RAM_PACKET_RAM_0_COUNT (544U)
AnnaBridge 171:3a7713b1edbc 8891
AnnaBridge 171:3a7713b1edbc 8892 /*! @name PACKET_RAM_1 - Shared Packet RAM for multiple Link Layer usage. */
AnnaBridge 171:3a7713b1edbc 8893 #define XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8894 #define XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8895 #define XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE(x) (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_1_LSBYTE_MASK)
AnnaBridge 171:3a7713b1edbc 8896 #define XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 8897 #define XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8898 #define XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE(x) (((uint16_t)(((uint16_t)(x)) << XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE_SHIFT)) & XCVR_PKT_RAM_PACKET_RAM_1_MSBYTE_MASK)
AnnaBridge 171:3a7713b1edbc 8899
AnnaBridge 171:3a7713b1edbc 8900 /* The count of XCVR_PKT_RAM_PACKET_RAM_1 */
AnnaBridge 171:3a7713b1edbc 8901 #define XCVR_PKT_RAM_PACKET_RAM_1_COUNT (544U)
AnnaBridge 171:3a7713b1edbc 8902
AnnaBridge 171:3a7713b1edbc 8903
AnnaBridge 171:3a7713b1edbc 8904 /*!
AnnaBridge 171:3a7713b1edbc 8905 * @}
AnnaBridge 171:3a7713b1edbc 8906 */ /* end of group XCVR_PKT_RAM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8907
AnnaBridge 171:3a7713b1edbc 8908
AnnaBridge 171:3a7713b1edbc 8909 /* XCVR_PKT_RAM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8910 /** Peripheral XCVR_PKT_RAM base address */
AnnaBridge 171:3a7713b1edbc 8911 #define XCVR_PKT_RAM_BASE (0x4005C700u)
AnnaBridge 171:3a7713b1edbc 8912 /** Peripheral XCVR_PKT_RAM base pointer */
AnnaBridge 171:3a7713b1edbc 8913 #define XCVR_PKT_RAM ((XCVR_PKT_RAM_Type *)XCVR_PKT_RAM_BASE)
AnnaBridge 171:3a7713b1edbc 8914 /** Array initializer of XCVR_PKT_RAM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8915 #define XCVR_PKT_RAM_BASE_ADDRS { XCVR_PKT_RAM_BASE }
AnnaBridge 171:3a7713b1edbc 8916 /** Array initializer of XCVR_PKT_RAM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8917 #define XCVR_PKT_RAM_BASE_PTRS { XCVR_PKT_RAM }
AnnaBridge 171:3a7713b1edbc 8918
AnnaBridge 171:3a7713b1edbc 8919 /*!
AnnaBridge 171:3a7713b1edbc 8920 * @}
AnnaBridge 171:3a7713b1edbc 8921 */ /* end of group XCVR_PKT_RAM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8922
AnnaBridge 171:3a7713b1edbc 8923
AnnaBridge 171:3a7713b1edbc 8924 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8925 -- XCVR_PLL_DIG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8926 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8927
AnnaBridge 171:3a7713b1edbc 8928 /*!
AnnaBridge 171:3a7713b1edbc 8929 * @addtogroup XCVR_PLL_DIG_Peripheral_Access_Layer XCVR_PLL_DIG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8930 * @{
AnnaBridge 171:3a7713b1edbc 8931 */
AnnaBridge 171:3a7713b1edbc 8932
AnnaBridge 171:3a7713b1edbc 8933 /** XCVR_PLL_DIG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8934 typedef struct {
AnnaBridge 171:3a7713b1edbc 8935 __IO uint32_t HPM_BUMP; /**< PLL HPM Analog Bump Control, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8936 __IO uint32_t MOD_CTRL; /**< PLL Modulation Control, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 8937 __IO uint32_t CHAN_MAP; /**< PLL Channel Mapping, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 8938 __IO uint32_t LOCK_DETECT; /**< PLL Lock Detect Control, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 8939 __IO uint32_t HPM_CTRL; /**< PLL High Port Modulator Control, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 8940 __IO uint32_t HPMCAL_CTRL; /**< PLL High Port Calibration Control, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 8941 __IO uint32_t HPM_CAL1; /**< PLL High Port Calibration Result 1, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 8942 __IO uint32_t HPM_CAL2; /**< PLL High Port Calibration Result 2, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 8943 __IO uint32_t HPM_SDM_RES; /**< PLL High Port Sigma Delta Results, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 8944 __IO uint32_t LPM_CTRL; /**< PLL Low Port Modulator Control, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 8945 __IO uint32_t LPM_SDM_CTRL1; /**< PLL Low Port Sigma Delta Control 1, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 8946 __IO uint32_t LPM_SDM_CTRL2; /**< PLL Low Port Sigma Delta Control 2, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 8947 __IO uint32_t LPM_SDM_CTRL3; /**< PLL Low Port Sigma Delta Control 3, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 8948 __I uint32_t LPM_SDM_RES1; /**< PLL Low Port Sigma Delta Result 1, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 8949 __I uint32_t LPM_SDM_RES2; /**< PLL Low Port Sigma Delta Result 2, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 8950 __IO uint32_t DELAY_MATCH; /**< PLL Delay Matching, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 8951 __IO uint32_t CTUNE_CTRL; /**< PLL Coarse Tune Control, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 8952 __I uint32_t CTUNE_CNT6; /**< PLL Coarse Tune Count 6, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 8953 __I uint32_t CTUNE_CNT5_4; /**< PLL Coarse Tune Counts 5 and 4, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 8954 __I uint32_t CTUNE_CNT3_2; /**< PLL Coarse Tune Counts 3 and 2, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 8955 __I uint32_t CTUNE_CNT1_0; /**< PLL Coarse Tune Counts 1 and 0, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 8956 __I uint32_t CTUNE_RES; /**< PLL Coarse Tune Results, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 8957 } XCVR_PLL_DIG_Type;
AnnaBridge 171:3a7713b1edbc 8958
AnnaBridge 171:3a7713b1edbc 8959 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8960 -- XCVR_PLL_DIG Register Masks
AnnaBridge 171:3a7713b1edbc 8961 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8962
AnnaBridge 171:3a7713b1edbc 8963 /*!
AnnaBridge 171:3a7713b1edbc 8964 * @addtogroup XCVR_PLL_DIG_Register_Masks XCVR_PLL_DIG Register Masks
AnnaBridge 171:3a7713b1edbc 8965 * @{
AnnaBridge 171:3a7713b1edbc 8966 */
AnnaBridge 171:3a7713b1edbc 8967
AnnaBridge 171:3a7713b1edbc 8968 /*! @name HPM_BUMP - PLL HPM Analog Bump Control */
AnnaBridge 171:3a7713b1edbc 8969 #define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 8970 #define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8971 #define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX_MASK)
AnnaBridge 171:3a7713b1edbc 8972 #define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 8973 #define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8974 #define XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 8975 #define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 8976 #define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8977 #define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX_MASK)
AnnaBridge 171:3a7713b1edbc 8978 #define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 8979 #define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8980 #define XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_SHIFT)) & XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 8981
AnnaBridge 171:3a7713b1edbc 8982 /*! @name MOD_CTRL - PLL Modulation Control */
AnnaBridge 171:3a7713b1edbc 8983 #define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 8984 #define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8985 #define XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 8986 #define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 8987 #define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 8988 #define XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 8989 #define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 8990 #define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8991 #define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 8992 #define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 8993 #define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 8994 #define XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 8995 #define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 8996 #define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8997 #define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 8998 #define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 8999 #define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9000 #define XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_SHIFT)) & XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 9001
AnnaBridge 171:3a7713b1edbc 9002 /*! @name CHAN_MAP - PLL Channel Mapping */
AnnaBridge 171:3a7713b1edbc 9003 #define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 9004 #define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9005 #define XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK)
AnnaBridge 171:3a7713b1edbc 9006 #define XCVR_PLL_DIG_CHAN_MAP_BOC_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 9007 #define XCVR_PLL_DIG_CHAN_MAP_BOC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9008 #define XCVR_PLL_DIG_CHAN_MAP_BOC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_BOC_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_BOC_MASK)
AnnaBridge 171:3a7713b1edbc 9009 #define XCVR_PLL_DIG_CHAN_MAP_BMR_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 9010 #define XCVR_PLL_DIG_CHAN_MAP_BMR_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 9011 #define XCVR_PLL_DIG_CHAN_MAP_BMR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_BMR_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_BMR_MASK)
AnnaBridge 171:3a7713b1edbc 9012 #define XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 9013 #define XCVR_PLL_DIG_CHAN_MAP_ZOC_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 9014 #define XCVR_PLL_DIG_CHAN_MAP_ZOC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CHAN_MAP_ZOC_SHIFT)) & XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK)
AnnaBridge 171:3a7713b1edbc 9015
AnnaBridge 171:3a7713b1edbc 9016 /*! @name LOCK_DETECT - PLL Lock Detect Control */
AnnaBridge 171:3a7713b1edbc 9017 #define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9018 #define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9019 #define XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CT_FAIL_MASK)
AnnaBridge 171:3a7713b1edbc 9020 #define XCVR_PLL_DIG_LOCK_DETECT_CTFF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9021 #define XCVR_PLL_DIG_LOCK_DETECT_CTFF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9022 #define XCVR_PLL_DIG_LOCK_DETECT_CTFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CTFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CTFF_MASK)
AnnaBridge 171:3a7713b1edbc 9023 #define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9024 #define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9025 #define XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CS_FAIL_MASK)
AnnaBridge 171:3a7713b1edbc 9026 #define XCVR_PLL_DIG_LOCK_DETECT_CSFF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9027 #define XCVR_PLL_DIG_LOCK_DETECT_CSFF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9028 #define XCVR_PLL_DIG_LOCK_DETECT_CSFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CSFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CSFF_MASK)
AnnaBridge 171:3a7713b1edbc 9029 #define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9030 #define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9031 #define XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FT_FAIL_MASK)
AnnaBridge 171:3a7713b1edbc 9032 #define XCVR_PLL_DIG_LOCK_DETECT_FTFF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9033 #define XCVR_PLL_DIG_LOCK_DETECT_FTFF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9034 #define XCVR_PLL_DIG_LOCK_DETECT_FTFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTFF_MASK)
AnnaBridge 171:3a7713b1edbc 9035 #define XCVR_PLL_DIG_LOCK_DETECT_TAFF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9036 #define XCVR_PLL_DIG_LOCK_DETECT_TAFF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9037 #define XCVR_PLL_DIG_LOCK_DETECT_TAFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_TAFF_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_TAFF_MASK)
AnnaBridge 171:3a7713b1edbc 9038 #define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 9039 #define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9040 #define XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV_MASK)
AnnaBridge 171:3a7713b1edbc 9041 #define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_MASK (0x3F000U)
AnnaBridge 171:3a7713b1edbc 9042 #define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 9043 #define XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH_MASK)
AnnaBridge 171:3a7713b1edbc 9044 #define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 9045 #define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 9046 #define XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTW_RX_MASK)
AnnaBridge 171:3a7713b1edbc 9047 #define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_MASK (0x3F00000U)
AnnaBridge 171:3a7713b1edbc 9048 #define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9049 #define XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH_MASK)
AnnaBridge 171:3a7713b1edbc 9050 #define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 9051 #define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 9052 #define XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FTW_TX_MASK)
AnnaBridge 171:3a7713b1edbc 9053 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 9054 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9055 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO_MASK)
AnnaBridge 171:3a7713b1edbc 9056 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 9057 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 9058 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_FINISHED_MASK)
AnnaBridge 171:3a7713b1edbc 9059 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 9060 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 9061 #define XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_SHIFT)) & XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 9062
AnnaBridge 171:3a7713b1edbc 9063 /*! @name HPM_CTRL - PLL High Port Modulator Control */
AnnaBridge 171:3a7713b1edbc 9064 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 9065 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9066 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 9067 #define XCVR_PLL_DIG_HPM_CTRL_HPFF_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 9068 #define XCVR_PLL_DIG_HPM_CTRL_HPFF_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 9069 #define XCVR_PLL_DIG_HPM_CTRL_HPFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPFF_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPFF_MASK)
AnnaBridge 171:3a7713b1edbc 9070 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 9071 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 9072 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT_MASK)
AnnaBridge 171:3a7713b1edbc 9073 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 9074 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 9075 #define XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 9076 #define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 9077 #define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9078 #define XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE_MASK)
AnnaBridge 171:3a7713b1edbc 9079 #define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 9080 #define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9081 #define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL_MASK)
AnnaBridge 171:3a7713b1edbc 9082 #define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 9083 #define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 9084 #define XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9085 #define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 9086 #define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9087 #define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE_MASK)
AnnaBridge 171:3a7713b1edbc 9088 #define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 9089 #define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 9090 #define XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT_MASK)
AnnaBridge 171:3a7713b1edbc 9091 #define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 9092 #define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9093 #define XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT_MASK)
AnnaBridge 171:3a7713b1edbc 9094 #define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 9095 #define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9096 #define XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_SHIFT)) & XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT_MASK)
AnnaBridge 171:3a7713b1edbc 9097
AnnaBridge 171:3a7713b1edbc 9098 /*! @name HPMCAL_CTRL - PLL High Port Calibration Control */
AnnaBridge 171:3a7713b1edbc 9099 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 9100 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9101 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MASK)
AnnaBridge 171:3a7713b1edbc 9102 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 9103 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 9104 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED_MASK)
AnnaBridge 171:3a7713b1edbc 9105 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 9106 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 9107 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE_MASK)
AnnaBridge 171:3a7713b1edbc 9108 #define XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 9109 #define XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 9110 #define XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 9111 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_MASK (0x1FFF0000U)
AnnaBridge 171:3a7713b1edbc 9112 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9113 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 9114 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 9115 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 9116 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE_MASK)
AnnaBridge 171:3a7713b1edbc 9117 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 9118 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9119 #define XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME_SHIFT)) & XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 9120
AnnaBridge 171:3a7713b1edbc 9121 /*! @name HPM_CAL1 - PLL High Port Calibration Result 1 */
AnnaBridge 171:3a7713b1edbc 9122 #define XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_MASK (0x7FFFFU)
AnnaBridge 171:3a7713b1edbc 9123 #define XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9124 #define XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_HPM_COUNT_1_MASK)
AnnaBridge 171:3a7713b1edbc 9125 #define XCVR_PLL_DIG_HPM_CAL1_CS_WT_MASK (0x700000U)
AnnaBridge 171:3a7713b1edbc 9126 #define XCVR_PLL_DIG_HPM_CAL1_CS_WT_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9127 #define XCVR_PLL_DIG_HPM_CAL1_CS_WT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_CS_WT_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_CS_WT_MASK)
AnnaBridge 171:3a7713b1edbc 9128 #define XCVR_PLL_DIG_HPM_CAL1_CS_FW_MASK (0x7000000U)
AnnaBridge 171:3a7713b1edbc 9129 #define XCVR_PLL_DIG_HPM_CAL1_CS_FW_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9130 #define XCVR_PLL_DIG_HPM_CAL1_CS_FW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_CS_FW_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_CS_FW_MASK)
AnnaBridge 171:3a7713b1edbc 9131 #define XCVR_PLL_DIG_HPM_CAL1_CS_FCNT_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 9132 #define XCVR_PLL_DIG_HPM_CAL1_CS_FCNT_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9133 #define XCVR_PLL_DIG_HPM_CAL1_CS_FCNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL1_CS_FCNT_SHIFT)) & XCVR_PLL_DIG_HPM_CAL1_CS_FCNT_MASK)
AnnaBridge 171:3a7713b1edbc 9134
AnnaBridge 171:3a7713b1edbc 9135 /*! @name HPM_CAL2 - PLL High Port Calibration Result 2 */
AnnaBridge 171:3a7713b1edbc 9136 #define XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_MASK (0x7FFFFU)
AnnaBridge 171:3a7713b1edbc 9137 #define XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9138 #define XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_SHIFT)) & XCVR_PLL_DIG_HPM_CAL2_HPM_COUNT_2_MASK)
AnnaBridge 171:3a7713b1edbc 9139 #define XCVR_PLL_DIG_HPM_CAL2_CS_RC_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 9140 #define XCVR_PLL_DIG_HPM_CAL2_CS_RC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9141 #define XCVR_PLL_DIG_HPM_CAL2_CS_RC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL2_CS_RC_SHIFT)) & XCVR_PLL_DIG_HPM_CAL2_CS_RC_MASK)
AnnaBridge 171:3a7713b1edbc 9142 #define XCVR_PLL_DIG_HPM_CAL2_CS_FT_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 9143 #define XCVR_PLL_DIG_HPM_CAL2_CS_FT_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9144 #define XCVR_PLL_DIG_HPM_CAL2_CS_FT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_CAL2_CS_FT_SHIFT)) & XCVR_PLL_DIG_HPM_CAL2_CS_FT_MASK)
AnnaBridge 171:3a7713b1edbc 9145
AnnaBridge 171:3a7713b1edbc 9146 /*! @name HPM_SDM_RES - PLL High Port Sigma Delta Results */
AnnaBridge 171:3a7713b1edbc 9147 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 9148 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9149 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_NUM_SELECTED_MASK)
AnnaBridge 171:3a7713b1edbc 9150 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 9151 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9152 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM_MASK)
AnnaBridge 171:3a7713b1edbc 9153 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 9154 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9155 #define XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_SHIFT)) & XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST_MASK)
AnnaBridge 171:3a7713b1edbc 9156
AnnaBridge 171:3a7713b1edbc 9157 /*! @name LPM_CTRL - PLL Low Port Modulator Control */
AnnaBridge 171:3a7713b1edbc 9158 #define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 9159 #define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9160 #define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 9161 #define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 9162 #define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 9163 #define XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 9164 #define XCVR_PLL_DIG_LPM_CTRL_LPFF_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 9165 #define XCVR_PLL_DIG_LPM_CTRL_LPFF_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 9166 #define XCVR_PLL_DIG_LPM_CTRL_LPFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPFF_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPFF_MASK)
AnnaBridge 171:3a7713b1edbc 9167 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 9168 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 9169 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV_MASK)
AnnaBridge 171:3a7713b1edbc 9170 #define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 9171 #define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 9172 #define XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 9173 #define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 9174 #define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9175 #define XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL_MASK)
AnnaBridge 171:3a7713b1edbc 9176 #define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 9177 #define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 9178 #define XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL_MASK)
AnnaBridge 171:3a7713b1edbc 9179 #define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 9180 #define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 9181 #define XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 9182 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 9183 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9184 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE_MASK)
AnnaBridge 171:3a7713b1edbc 9185 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 9186 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9187 #define XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_SHIFT)) & XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG_MASK)
AnnaBridge 171:3a7713b1edbc 9188
AnnaBridge 171:3a7713b1edbc 9189 /*! @name LPM_SDM_CTRL1 - PLL Low Port Sigma Delta Control 1 */
AnnaBridge 171:3a7713b1edbc 9190 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 9191 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9192 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK)
AnnaBridge 171:3a7713b1edbc 9193 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_MASK (0x7F00U)
AnnaBridge 171:3a7713b1edbc 9194 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9195 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS_MASK)
AnnaBridge 171:3a7713b1edbc 9196 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 9197 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9198 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK)
AnnaBridge 171:3a7713b1edbc 9199 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 9200 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9201 #define XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 9202
AnnaBridge 171:3a7713b1edbc 9203 /*! @name LPM_SDM_CTRL2 - PLL Low Port Sigma Delta Control 2 */
AnnaBridge 171:3a7713b1edbc 9204 #define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_MASK (0xFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9205 #define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9206 #define XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM_MASK)
AnnaBridge 171:3a7713b1edbc 9207
AnnaBridge 171:3a7713b1edbc 9208 /*! @name LPM_SDM_CTRL3 - PLL Low Port Sigma Delta Control 3 */
AnnaBridge 171:3a7713b1edbc 9209 #define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_MASK (0xFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9210 #define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9211 #define XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM_MASK)
AnnaBridge 171:3a7713b1edbc 9212
AnnaBridge 171:3a7713b1edbc 9213 /*! @name LPM_SDM_RES1 - PLL Low Port Sigma Delta Result 1 */
AnnaBridge 171:3a7713b1edbc 9214 #define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_MASK (0xFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9215 #define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9216 #define XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_RES1_LPM_NUM_SELECTED_MASK)
AnnaBridge 171:3a7713b1edbc 9217
AnnaBridge 171:3a7713b1edbc 9218 /*! @name LPM_SDM_RES2 - PLL Low Port Sigma Delta Result 2 */
AnnaBridge 171:3a7713b1edbc 9219 #define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_MASK (0xFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9220 #define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9221 #define XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_SHIFT)) & XCVR_PLL_DIG_LPM_SDM_RES2_LPM_DENOM_SELECTED_MASK)
AnnaBridge 171:3a7713b1edbc 9222
AnnaBridge 171:3a7713b1edbc 9223 /*! @name DELAY_MATCH - PLL Delay Matching */
AnnaBridge 171:3a7713b1edbc 9224 #define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 9225 #define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9226 #define XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY_MASK)
AnnaBridge 171:3a7713b1edbc 9227 #define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 9228 #define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9229 #define XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY_MASK)
AnnaBridge 171:3a7713b1edbc 9230 #define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 9231 #define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9232 #define XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_SHIFT)) & XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY_MASK)
AnnaBridge 171:3a7713b1edbc 9233
AnnaBridge 171:3a7713b1edbc 9234 /*! @name CTUNE_CTRL - PLL Coarse Tune Control */
AnnaBridge 171:3a7713b1edbc 9235 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 9236 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9237 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 9238 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 9239 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 9240 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 9241 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 9242 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9243 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST_MASK)
AnnaBridge 171:3a7713b1edbc 9244 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_MASK (0x7F000000U)
AnnaBridge 171:3a7713b1edbc 9245 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9246 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 9247 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 9248 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9249 #define XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_SHIFT)) & XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE_MASK)
AnnaBridge 171:3a7713b1edbc 9250
AnnaBridge 171:3a7713b1edbc 9251 /*! @name CTUNE_CNT6 - PLL Coarse Tune Count 6 */
AnnaBridge 171:3a7713b1edbc 9252 #define XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 9253 #define XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9254 #define XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT6_CTUNE_COUNT_6_MASK)
AnnaBridge 171:3a7713b1edbc 9255
AnnaBridge 171:3a7713b1edbc 9256 /*! @name CTUNE_CNT5_4 - PLL Coarse Tune Counts 5 and 4 */
AnnaBridge 171:3a7713b1edbc 9257 #define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 9258 #define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9259 #define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_4_MASK)
AnnaBridge 171:3a7713b1edbc 9260 #define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5_MASK (0x1FFF0000U)
AnnaBridge 171:3a7713b1edbc 9261 #define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9262 #define XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT5_4_CTUNE_COUNT_5_MASK)
AnnaBridge 171:3a7713b1edbc 9263
AnnaBridge 171:3a7713b1edbc 9264 /*! @name CTUNE_CNT3_2 - PLL Coarse Tune Counts 3 and 2 */
AnnaBridge 171:3a7713b1edbc 9265 #define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 9266 #define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9267 #define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_2_MASK)
AnnaBridge 171:3a7713b1edbc 9268 #define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3_MASK (0x1FFF0000U)
AnnaBridge 171:3a7713b1edbc 9269 #define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9270 #define XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT3_2_CTUNE_COUNT_3_MASK)
AnnaBridge 171:3a7713b1edbc 9271
AnnaBridge 171:3a7713b1edbc 9272 /*! @name CTUNE_CNT1_0 - PLL Coarse Tune Counts 1 and 0 */
AnnaBridge 171:3a7713b1edbc 9273 #define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 9274 #define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9275 #define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_0_MASK)
AnnaBridge 171:3a7713b1edbc 9276 #define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1_MASK (0x1FFF0000U)
AnnaBridge 171:3a7713b1edbc 9277 #define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9278 #define XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1_SHIFT)) & XCVR_PLL_DIG_CTUNE_CNT1_0_CTUNE_COUNT_1_MASK)
AnnaBridge 171:3a7713b1edbc 9279
AnnaBridge 171:3a7713b1edbc 9280 /*! @name CTUNE_RES - PLL Coarse Tune Results */
AnnaBridge 171:3a7713b1edbc 9281 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 9282 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9283 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_SELECTED_MASK)
AnnaBridge 171:3a7713b1edbc 9284 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 9285 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9286 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_BEST_DIFF_MASK)
AnnaBridge 171:3a7713b1edbc 9287 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 9288 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9289 #define XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_SHIFT)) & XCVR_PLL_DIG_CTUNE_RES_CTUNE_FREQ_SELECTED_MASK)
AnnaBridge 171:3a7713b1edbc 9290
AnnaBridge 171:3a7713b1edbc 9291
AnnaBridge 171:3a7713b1edbc 9292 /*!
AnnaBridge 171:3a7713b1edbc 9293 * @}
AnnaBridge 171:3a7713b1edbc 9294 */ /* end of group XCVR_PLL_DIG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 9295
AnnaBridge 171:3a7713b1edbc 9296
AnnaBridge 171:3a7713b1edbc 9297 /* XCVR_PLL_DIG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 9298 /** Peripheral XCVR_PLL_DIG base address */
AnnaBridge 171:3a7713b1edbc 9299 #define XCVR_PLL_DIG_BASE (0x4005C224u)
AnnaBridge 171:3a7713b1edbc 9300 /** Peripheral XCVR_PLL_DIG base pointer */
AnnaBridge 171:3a7713b1edbc 9301 #define XCVR_PLL_DIG ((XCVR_PLL_DIG_Type *)XCVR_PLL_DIG_BASE)
AnnaBridge 171:3a7713b1edbc 9302 /** Array initializer of XCVR_PLL_DIG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 9303 #define XCVR_PLL_DIG_BASE_ADDRS { XCVR_PLL_DIG_BASE }
AnnaBridge 171:3a7713b1edbc 9304 /** Array initializer of XCVR_PLL_DIG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 9305 #define XCVR_PLL_DIG_BASE_PTRS { XCVR_PLL_DIG }
AnnaBridge 171:3a7713b1edbc 9306
AnnaBridge 171:3a7713b1edbc 9307 /*!
AnnaBridge 171:3a7713b1edbc 9308 * @}
AnnaBridge 171:3a7713b1edbc 9309 */ /* end of group XCVR_PLL_DIG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 9310
AnnaBridge 171:3a7713b1edbc 9311
AnnaBridge 171:3a7713b1edbc 9312 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9313 -- XCVR_RX_DIG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9314 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9315
AnnaBridge 171:3a7713b1edbc 9316 /*!
AnnaBridge 171:3a7713b1edbc 9317 * @addtogroup XCVR_RX_DIG_Peripheral_Access_Layer XCVR_RX_DIG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9318 * @{
AnnaBridge 171:3a7713b1edbc 9319 */
AnnaBridge 171:3a7713b1edbc 9320
AnnaBridge 171:3a7713b1edbc 9321 /** XCVR_RX_DIG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 9322 typedef struct {
AnnaBridge 171:3a7713b1edbc 9323 __IO uint32_t RX_DIG_CTRL; /**< RX Digital Control, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 9324 __IO uint32_t AGC_CTRL_0; /**< AGC Control 0, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 9325 __IO uint32_t AGC_CTRL_1; /**< AGC Control 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 9326 __IO uint32_t AGC_CTRL_2; /**< AGC Control 2, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 9327 __IO uint32_t AGC_CTRL_3; /**< AGC Control 3, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 9328 __I uint32_t AGC_STAT; /**< AGC Status, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 9329 __IO uint32_t RSSI_CTRL_0; /**< RSSI Control 0, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 9330 __I uint32_t RSSI_CTRL_1; /**< RSSI Control 1, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 9331 __I uint32_t RSSI_DFT; /**< RSSI DFT, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 9332 __IO uint32_t DCOC_CTRL_0; /**< DCOC Control 0, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 9333 __IO uint32_t DCOC_CTRL_1; /**< DCOC Control 1, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 9334 __IO uint32_t DCOC_DAC_INIT; /**< DCOC DAC Initialization, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 9335 __IO uint32_t DCOC_DIG_MAN; /**< DCOC Digital Correction Manual Override, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 9336 __IO uint32_t DCOC_CAL_GAIN; /**< DCOC Calibration Gain, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 9337 __I uint32_t DCOC_STAT; /**< DCOC Status, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 9338 __I uint32_t DCOC_DC_EST; /**< DCOC DC Estimate, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 9339 __IO uint32_t DCOC_CAL_RCP; /**< DCOC Calibration Reciprocals, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 9340 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 9341 __IO uint32_t IQMC_CTRL; /**< IQMC Control, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 9342 __IO uint32_t IQMC_CAL; /**< IQMC Calibration, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 9343 __IO uint32_t LNA_GAIN_VAL_3_0; /**< LNA_GAIN Step Values 3..0, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 9344 __IO uint32_t LNA_GAIN_VAL_7_4; /**< LNA_GAIN Step Values 7..4, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 9345 __IO uint32_t LNA_GAIN_VAL_8; /**< LNA_GAIN Step Values 8, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 9346 __IO uint32_t BBA_RES_TUNE_VAL_7_0; /**< BBA Resistor Tune Values 7..0, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 9347 __IO uint32_t BBA_RES_TUNE_VAL_10_8; /**< BBA Resistor Tune Values 10..8, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 9348 __IO uint32_t LNA_GAIN_LIN_VAL_2_0; /**< LNA Linear Gain Values 2..0, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 9349 __IO uint32_t LNA_GAIN_LIN_VAL_5_3; /**< LNA Linear Gain Values 5..3, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 9350 __IO uint32_t LNA_GAIN_LIN_VAL_8_6; /**< LNA Linear Gain Values 8..6, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 9351 __IO uint32_t LNA_GAIN_LIN_VAL_9; /**< LNA Linear Gain Values 9, offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 9352 __IO uint32_t BBA_RES_TUNE_LIN_VAL_3_0; /**< BBA Resistor Tune Values 3..0, offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 9353 __IO uint32_t BBA_RES_TUNE_LIN_VAL_7_4; /**< BBA Resistor Tune Values 7..4, offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 9354 __IO uint32_t BBA_RES_TUNE_LIN_VAL_10_8; /**< BBA Resistor Tune Values 10..8, offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 9355 __IO uint32_t AGC_GAIN_TBL_03_00; /**< AGC Gain Tables Step 03..00, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 9356 __IO uint32_t AGC_GAIN_TBL_07_04; /**< AGC Gain Tables Step 07..04, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 9357 __IO uint32_t AGC_GAIN_TBL_11_08; /**< AGC Gain Tables Step 11..08, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 9358 __IO uint32_t AGC_GAIN_TBL_15_12; /**< AGC Gain Tables Step 15..12, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 9359 __IO uint32_t AGC_GAIN_TBL_19_16; /**< AGC Gain Tables Step 19..16, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 9360 __IO uint32_t AGC_GAIN_TBL_23_20; /**< AGC Gain Tables Step 23..20, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 9361 __IO uint32_t AGC_GAIN_TBL_26_24; /**< AGC Gain Tables Step 26..24, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 9362 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 9363 __IO uint32_t DCOC_OFFSET[27]; /**< DCOC Offset, array offset: 0xA0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 9364 __IO uint32_t DCOC_BBA_STEP; /**< DCOC BBA DAC Step, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 9365 __IO uint32_t DCOC_TZA_STEP_0; /**< DCOC TZA DAC Step 0, offset: 0x110 */
AnnaBridge 171:3a7713b1edbc 9366 __IO uint32_t DCOC_TZA_STEP_1; /**< DCOC TZA DAC Step 1, offset: 0x114 */
AnnaBridge 171:3a7713b1edbc 9367 __IO uint32_t DCOC_TZA_STEP_2; /**< DCOC TZA DAC Step 2, offset: 0x118 */
AnnaBridge 171:3a7713b1edbc 9368 __IO uint32_t DCOC_TZA_STEP_3; /**< DCOC TZA DAC Step 3, offset: 0x11C */
AnnaBridge 171:3a7713b1edbc 9369 __IO uint32_t DCOC_TZA_STEP_4; /**< DCOC TZA DAC Step 4, offset: 0x120 */
AnnaBridge 171:3a7713b1edbc 9370 __IO uint32_t DCOC_TZA_STEP_5; /**< DCOC TZA DAC Step 5, offset: 0x124 */
AnnaBridge 171:3a7713b1edbc 9371 __IO uint32_t DCOC_TZA_STEP_6; /**< DCOC TZA DAC Step 6, offset: 0x128 */
AnnaBridge 171:3a7713b1edbc 9372 __IO uint32_t DCOC_TZA_STEP_7; /**< DCOC TZA DAC Step 7, offset: 0x12C */
AnnaBridge 171:3a7713b1edbc 9373 __IO uint32_t DCOC_TZA_STEP_8; /**< DCOC TZA DAC Step 5, offset: 0x130 */
AnnaBridge 171:3a7713b1edbc 9374 __IO uint32_t DCOC_TZA_STEP_9; /**< DCOC TZA DAC Step 9, offset: 0x134 */
AnnaBridge 171:3a7713b1edbc 9375 __IO uint32_t DCOC_TZA_STEP_10; /**< DCOC TZA DAC Step 10, offset: 0x138 */
AnnaBridge 171:3a7713b1edbc 9376 uint8_t RESERVED_2[44];
AnnaBridge 171:3a7713b1edbc 9377 __I uint32_t DCOC_CAL_ALPHA; /**< DCOC Calibration Alpha, offset: 0x168 */
AnnaBridge 171:3a7713b1edbc 9378 __I uint32_t DCOC_CAL_BETA_Q; /**< DCOC Calibration Beta Q, offset: 0x16C */
AnnaBridge 171:3a7713b1edbc 9379 __I uint32_t DCOC_CAL_BETA_I; /**< DCOC Calibration Beta I, offset: 0x170 */
AnnaBridge 171:3a7713b1edbc 9380 __I uint32_t DCOC_CAL_GAMMA; /**< DCOC Calibration Gamma, offset: 0x174 */
AnnaBridge 171:3a7713b1edbc 9381 __IO uint32_t DCOC_CAL_IIR; /**< DCOC Calibration IIR, offset: 0x178 */
AnnaBridge 171:3a7713b1edbc 9382 uint8_t RESERVED_3[4];
AnnaBridge 171:3a7713b1edbc 9383 __I uint32_t DCOC_CAL[3]; /**< DCOC Calibration Result, array offset: 0x180, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 9384 uint8_t RESERVED_4[4];
AnnaBridge 171:3a7713b1edbc 9385 __IO uint32_t CCA_ED_LQI_CTRL_0; /**< RX_DIG CCA ED LQI Control Register 0, offset: 0x190 */
AnnaBridge 171:3a7713b1edbc 9386 __IO uint32_t CCA_ED_LQI_CTRL_1; /**< RX_DIG CCA ED LQI Control Register 1, offset: 0x194 */
AnnaBridge 171:3a7713b1edbc 9387 __I uint32_t CCA_ED_LQI_STAT_0; /**< RX_DIG CCA ED LQI Status Register 0, offset: 0x198 */
AnnaBridge 171:3a7713b1edbc 9388 uint8_t RESERVED_5[4];
AnnaBridge 171:3a7713b1edbc 9389 __IO uint32_t RX_CHF_COEF_0; /**< Receive Channel Filter Coefficient 0, offset: 0x1A0 */
AnnaBridge 171:3a7713b1edbc 9390 __IO uint32_t RX_CHF_COEF_1; /**< Receive Channel Filter Coefficient 1, offset: 0x1A4 */
AnnaBridge 171:3a7713b1edbc 9391 __IO uint32_t RX_CHF_COEF_2; /**< Receive Channel Filter Coefficient 2, offset: 0x1A8 */
AnnaBridge 171:3a7713b1edbc 9392 __IO uint32_t RX_CHF_COEF_3; /**< Receive Channel Filter Coefficient 3, offset: 0x1AC */
AnnaBridge 171:3a7713b1edbc 9393 __IO uint32_t RX_CHF_COEF_4; /**< Receive Channel Filter Coefficient 4, offset: 0x1B0 */
AnnaBridge 171:3a7713b1edbc 9394 __IO uint32_t RX_CHF_COEF_5; /**< Receive Channel Filter Coefficient 5, offset: 0x1B4 */
AnnaBridge 171:3a7713b1edbc 9395 __IO uint32_t RX_CHF_COEF_6; /**< Receive Channel Filter Coefficient 6, offset: 0x1B8 */
AnnaBridge 171:3a7713b1edbc 9396 __IO uint32_t RX_CHF_COEF_7; /**< Receive Channel Filter Coefficient 7, offset: 0x1BC */
AnnaBridge 171:3a7713b1edbc 9397 __IO uint32_t RX_CHF_COEF_8; /**< Receive Channel Filter Coefficient 8, offset: 0x1C0 */
AnnaBridge 171:3a7713b1edbc 9398 __IO uint32_t RX_CHF_COEF_9; /**< Receive Channel Filter Coefficient 9, offset: 0x1C4 */
AnnaBridge 171:3a7713b1edbc 9399 __IO uint32_t RX_CHF_COEF_10; /**< Receive Channel Filter Coefficient 10, offset: 0x1C8 */
AnnaBridge 171:3a7713b1edbc 9400 __IO uint32_t RX_CHF_COEF_11; /**< Receive Channel Filter Coefficient 11, offset: 0x1CC */
AnnaBridge 171:3a7713b1edbc 9401 __IO uint32_t AGC_MAN_AGC_IDX; /**< AGC Manual AGC Index, offset: 0x1D0 */
AnnaBridge 171:3a7713b1edbc 9402 __IO uint32_t DC_RESID_CTRL; /**< DC Residual Control, offset: 0x1D4 */
AnnaBridge 171:3a7713b1edbc 9403 __I uint32_t DC_RESID_EST; /**< DC Residual Estimate, offset: 0x1D8 */
AnnaBridge 171:3a7713b1edbc 9404 __IO uint32_t RX_RCCAL_CTRL0; /**< RX RC Calibration Control0, offset: 0x1DC */
AnnaBridge 171:3a7713b1edbc 9405 __IO uint32_t RX_RCCAL_CTRL1; /**< RX RC Calibration Control1, offset: 0x1E0 */
AnnaBridge 171:3a7713b1edbc 9406 __I uint32_t RX_RCCAL_STAT; /**< RX RC Calibration Status, offset: 0x1E4 */
AnnaBridge 171:3a7713b1edbc 9407 __IO uint32_t AUXPLL_FCAL_CTRL; /**< Aux PLL Frequency Calibration Control, offset: 0x1E8 */
AnnaBridge 171:3a7713b1edbc 9408 __I uint32_t AUXPLL_FCAL_CNT6; /**< Aux PLL Frequency Calibration Count 6, offset: 0x1EC */
AnnaBridge 171:3a7713b1edbc 9409 __I uint32_t AUXPLL_FCAL_CNT5_4; /**< Aux PLL Frequency Calibration Count 5 and 4, offset: 0x1F0 */
AnnaBridge 171:3a7713b1edbc 9410 __I uint32_t AUXPLL_FCAL_CNT3_2; /**< Aux PLL Frequency Calibration Count 3 and 2, offset: 0x1F4 */
AnnaBridge 171:3a7713b1edbc 9411 __I uint32_t AUXPLL_FCAL_CNT1_0; /**< Aux PLL Frequency Calibration Count 1 and 0, offset: 0x1F8 */
AnnaBridge 171:3a7713b1edbc 9412 __IO uint32_t RXDIG_DFT; /**< RXDIG DFT, offset: 0x1FC */
AnnaBridge 171:3a7713b1edbc 9413 } XCVR_RX_DIG_Type;
AnnaBridge 171:3a7713b1edbc 9414
AnnaBridge 171:3a7713b1edbc 9415 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9416 -- XCVR_RX_DIG Register Masks
AnnaBridge 171:3a7713b1edbc 9417 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9418
AnnaBridge 171:3a7713b1edbc 9419 /*!
AnnaBridge 171:3a7713b1edbc 9420 * @addtogroup XCVR_RX_DIG_Register_Masks XCVR_RX_DIG Register Masks
AnnaBridge 171:3a7713b1edbc 9421 * @{
AnnaBridge 171:3a7713b1edbc 9422 */
AnnaBridge 171:3a7713b1edbc 9423
AnnaBridge 171:3a7713b1edbc 9424 /*! @name RX_DIG_CTRL - RX Digital Control */
AnnaBridge 171:3a7713b1edbc 9425 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9426 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9427 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE_MASK)
AnnaBridge 171:3a7713b1edbc 9428 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9429 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9430 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK)
AnnaBridge 171:3a7713b1edbc 9431 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9432 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9433 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9434 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9435 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9436 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL_MASK)
AnnaBridge 171:3a7713b1edbc 9437 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 9438 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9439 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK)
AnnaBridge 171:3a7713b1edbc 9440 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 9441 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9442 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 9443 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 9444 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 9445 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9446 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 9447 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 9448 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9449 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 9450 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 9451 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9452 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 9453 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 9454 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9455 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 9456 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 9457 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9458 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 9459 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 9460 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP_MASK)
AnnaBridge 171:3a7713b1edbc 9461 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 9462 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 9463 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9464 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 9465 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9466 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9467 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 9468 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 9469 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE_MASK)
AnnaBridge 171:3a7713b1edbc 9470 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 9471 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 9472 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9473 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_MASK (0x1F00000U)
AnnaBridge 171:3a7713b1edbc 9474 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9475 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN_MASK)
AnnaBridge 171:3a7713b1edbc 9476 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 9477 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 9478 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 9479 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 9480 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9481 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HAZARD_MASK)
AnnaBridge 171:3a7713b1edbc 9482 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 9483 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 9484 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_FILT_HAZARD_MASK)
AnnaBridge 171:3a7713b1edbc 9485 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 9486 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 9487 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_I_MASK)
AnnaBridge 171:3a7713b1edbc 9488 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 9489 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9490 #define XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_SHIFT)) & XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_SAT_Q_MASK)
AnnaBridge 171:3a7713b1edbc 9491
AnnaBridge 171:3a7713b1edbc 9492 /*! @name AGC_CTRL_0 - AGC Control 0 */
AnnaBridge 171:3a7713b1edbc 9493 #define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9494 #define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9495 #define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9496 #define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_MASK (0x6U)
AnnaBridge 171:3a7713b1edbc 9497 #define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9498 #define XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC_MASK)
AnnaBridge 171:3a7713b1edbc 9499 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9500 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9501 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9502 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9503 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9504 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA_MASK)
AnnaBridge 171:3a7713b1edbc 9505 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9506 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9507 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9508 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9509 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9510 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC_MASK)
AnnaBridge 171:3a7713b1edbc 9511 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 9512 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9513 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 9514 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 9515 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 9516 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 9517 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 9518 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9519 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 9520 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9521 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9522 #define XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 9523
AnnaBridge 171:3a7713b1edbc 9524 /*! @name AGC_CTRL_1 - AGC Control 1 */
AnnaBridge 171:3a7713b1edbc 9525 #define XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 9526 #define XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9527 #define XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_BBA_ALT_CODE_MASK)
AnnaBridge 171:3a7713b1edbc 9528 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE_MASK (0xFF0U)
AnnaBridge 171:3a7713b1edbc 9529 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9530 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_ALT_CODE_MASK)
AnnaBridge 171:3a7713b1edbc 9531 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 9532 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 9533 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN_MASK)
AnnaBridge 171:3a7713b1edbc 9534 #define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 9535 #define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9536 #define XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN_MASK)
AnnaBridge 171:3a7713b1edbc 9537 #define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 9538 #define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9539 #define XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9540 #define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 9541 #define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 9542 #define XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9543 #define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 9544 #define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 9545 #define XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9546 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9547 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9548 #define XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 9549
AnnaBridge 171:3a7713b1edbc 9550 /*! @name AGC_CTRL_2 - AGC Control 2 */
AnnaBridge 171:3a7713b1edbc 9551 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9552 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9553 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_RST_MASK)
AnnaBridge 171:3a7713b1edbc 9554 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9555 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9556 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_RST_MASK)
AnnaBridge 171:3a7713b1edbc 9557 #define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9558 #define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9559 #define XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_MAN_PDET_RST_MASK)
AnnaBridge 171:3a7713b1edbc 9560 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_MASK (0xFF0U)
AnnaBridge 171:3a7713b1edbc 9561 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9562 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 9563 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 9564 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 9565 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO_MASK)
AnnaBridge 171:3a7713b1edbc 9566 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_MASK (0x38000U)
AnnaBridge 171:3a7713b1edbc 9567 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 9568 #define XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI_MASK)
AnnaBridge 171:3a7713b1edbc 9569 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_MASK (0x1C0000U)
AnnaBridge 171:3a7713b1edbc 9570 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 9571 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO_MASK)
AnnaBridge 171:3a7713b1edbc 9572 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_MASK (0xE00000U)
AnnaBridge 171:3a7713b1edbc 9573 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 9574 #define XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI_MASK)
AnnaBridge 171:3a7713b1edbc 9575 #define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK (0x3F000000U)
AnnaBridge 171:3a7713b1edbc 9576 #define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9577 #define XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK)
AnnaBridge 171:3a7713b1edbc 9578 #define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 9579 #define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 9580 #define XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_LNA_LG_ON_OVR_MASK)
AnnaBridge 171:3a7713b1edbc 9581 #define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 9582 #define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 9583 #define XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_2_LNA_HG_ON_OVR_MASK)
AnnaBridge 171:3a7713b1edbc 9584
AnnaBridge 171:3a7713b1edbc 9585 /*! @name AGC_CTRL_3 - AGC Control 3 */
AnnaBridge 171:3a7713b1edbc 9586 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 9587 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9588 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 9589 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK (0xE000U)
AnnaBridge 171:3a7713b1edbc 9590 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 9591 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK)
AnnaBridge 171:3a7713b1edbc 9592 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 9593 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9594 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK)
AnnaBridge 171:3a7713b1edbc 9595 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK (0xF800000U)
AnnaBridge 171:3a7713b1edbc 9596 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 9597 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 9598 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 9599 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9600 #define XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT)) & XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK)
AnnaBridge 171:3a7713b1edbc 9601
AnnaBridge 171:3a7713b1edbc 9602 /*! @name AGC_STAT - AGC Status */
AnnaBridge 171:3a7713b1edbc 9603 #define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9604 #define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9605 #define XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_BBA_PDET_LO_STAT_MASK)
AnnaBridge 171:3a7713b1edbc 9606 #define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9607 #define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9608 #define XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_BBA_PDET_HI_STAT_MASK)
AnnaBridge 171:3a7713b1edbc 9609 #define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9610 #define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9611 #define XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_TZA_PDET_LO_STAT_MASK)
AnnaBridge 171:3a7713b1edbc 9612 #define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9613 #define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9614 #define XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_SHIFT)) & XCVR_RX_DIG_AGC_STAT_TZA_PDET_HI_STAT_MASK)
AnnaBridge 171:3a7713b1edbc 9615 #define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_MASK (0x1F0U)
AnnaBridge 171:3a7713b1edbc 9616 #define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9617 #define XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_SHIFT)) & XCVR_RX_DIG_AGC_STAT_CURR_AGC_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 9618 #define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 9619 #define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 9620 #define XCVR_RX_DIG_AGC_STAT_AGC_FROZEN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_SHIFT)) & XCVR_RX_DIG_AGC_STAT_AGC_FROZEN_MASK)
AnnaBridge 171:3a7713b1edbc 9621 #define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 9622 #define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9623 #define XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_SHIFT)) & XCVR_RX_DIG_AGC_STAT_RSSI_ADC_RAW_MASK)
AnnaBridge 171:3a7713b1edbc 9624
AnnaBridge 171:3a7713b1edbc 9625 /*! @name RSSI_CTRL_0 - RSSI Control 0 */
AnnaBridge 171:3a7713b1edbc 9626 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9627 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9628 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS_MASK)
AnnaBridge 171:3a7713b1edbc 9629 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_MASK (0x6U)
AnnaBridge 171:3a7713b1edbc 9630 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9631 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC_MASK)
AnnaBridge 171:3a7713b1edbc 9632 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9633 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9634 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9635 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 9636 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9637 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK)
AnnaBridge 171:3a7713b1edbc 9638 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 9639 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9640 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK)
AnnaBridge 171:3a7713b1edbc 9641 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_MASK (0xFC00U)
AnnaBridge 171:3a7713b1edbc 9642 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 9643 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY_MASK)
AnnaBridge 171:3a7713b1edbc 9644 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 9645 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9646 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK)
AnnaBridge 171:3a7713b1edbc 9647 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_MASK (0x700000U)
AnnaBridge 171:3a7713b1edbc 9648 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9649 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE_MASK)
AnnaBridge 171:3a7713b1edbc 9650 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9651 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9652 #define XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 9653
AnnaBridge 171:3a7713b1edbc 9654 /*! @name RSSI_CTRL_1 - RSSI Control 1 */
AnnaBridge 171:3a7713b1edbc 9655 #define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9656 #define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9657 #define XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT)) & XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK)
AnnaBridge 171:3a7713b1edbc 9658
AnnaBridge 171:3a7713b1edbc 9659 /*! @name RSSI_DFT - RSSI DFT */
AnnaBridge 171:3a7713b1edbc 9660 #define XCVR_RX_DIG_RSSI_DFT_DFT_MAG_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 9661 #define XCVR_RX_DIG_RSSI_DFT_DFT_MAG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9662 #define XCVR_RX_DIG_RSSI_DFT_DFT_MAG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_DFT_DFT_MAG_SHIFT)) & XCVR_RX_DIG_RSSI_DFT_DFT_MAG_MASK)
AnnaBridge 171:3a7713b1edbc 9663 #define XCVR_RX_DIG_RSSI_DFT_DFT_NOISE_MASK (0x1FFF0000U)
AnnaBridge 171:3a7713b1edbc 9664 #define XCVR_RX_DIG_RSSI_DFT_DFT_NOISE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9665 #define XCVR_RX_DIG_RSSI_DFT_DFT_NOISE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RSSI_DFT_DFT_NOISE_SHIFT)) & XCVR_RX_DIG_RSSI_DFT_DFT_NOISE_MASK)
AnnaBridge 171:3a7713b1edbc 9666
AnnaBridge 171:3a7713b1edbc 9667 /*! @name DCOC_CTRL_0 - DCOC Control 0 */
AnnaBridge 171:3a7713b1edbc 9668 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9669 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9670 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MIDPWR_TRK_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 9671 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9672 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9673 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK)
AnnaBridge 171:3a7713b1edbc 9674 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9675 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9676 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR_MASK)
AnnaBridge 171:3a7713b1edbc 9677 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9678 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9679 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK)
AnnaBridge 171:3a7713b1edbc 9680 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9681 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9682 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9683 #define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9684 #define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9685 #define XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO_MASK)
AnnaBridge 171:3a7713b1edbc 9686 #define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9687 #define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9688 #define XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL_MASK)
AnnaBridge 171:3a7713b1edbc 9689 #define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9690 #define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9691 #define XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL_MASK)
AnnaBridge 171:3a7713b1edbc 9692 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 9693 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9694 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION_MASK)
AnnaBridge 171:3a7713b1edbc 9695 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 9696 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9697 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY_MASK)
AnnaBridge 171:3a7713b1edbc 9698 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK (0x7F000000U)
AnnaBridge 171:3a7713b1edbc 9699 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9700 #define XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK)
AnnaBridge 171:3a7713b1edbc 9701
AnnaBridge 171:3a7713b1edbc 9702 /*! @name DCOC_CTRL_1 - DCOC Control 1 */
AnnaBridge 171:3a7713b1edbc 9703 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 9704 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9705 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 9706 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_MASK (0x1CU)
AnnaBridge 171:3a7713b1edbc 9707 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9708 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 9709 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_MASK (0xE0U)
AnnaBridge 171:3a7713b1edbc 9710 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9711 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 9712 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 9713 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 9714 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 9715 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 9716 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9717 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 9718 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_MASK (0x1C0000U)
AnnaBridge 171:3a7713b1edbc 9719 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 9720 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 9721 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_MASK (0xE00000U)
AnnaBridge 171:3a7713b1edbc 9722 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 9723 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 9724 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 9725 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9726 #define XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 9727
AnnaBridge 171:3a7713b1edbc 9728 /*! @name DCOC_DAC_INIT - DCOC DAC Initialization */
AnnaBridge 171:3a7713b1edbc 9729 #define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 9730 #define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9731 #define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK)
AnnaBridge 171:3a7713b1edbc 9732 #define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK (0x3F00U)
AnnaBridge 171:3a7713b1edbc 9733 #define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9734 #define XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK)
AnnaBridge 171:3a7713b1edbc 9735 #define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 9736 #define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9737 #define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I_MASK)
AnnaBridge 171:3a7713b1edbc 9738 #define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9739 #define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9740 #define XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q_MASK)
AnnaBridge 171:3a7713b1edbc 9741
AnnaBridge 171:3a7713b1edbc 9742 /*! @name DCOC_DIG_MAN - DCOC Digital Correction Manual Override */
AnnaBridge 171:3a7713b1edbc 9743 #define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 9744 #define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9745 #define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_SHIFT)) & XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_I_MASK)
AnnaBridge 171:3a7713b1edbc 9746 #define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 9747 #define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9748 #define XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DIG_MAN_DIG_DCOC_INIT_Q_MASK)
AnnaBridge 171:3a7713b1edbc 9749
AnnaBridge 171:3a7713b1edbc 9750 /*! @name DCOC_CAL_GAIN - DCOC Calibration Gain */
AnnaBridge 171:3a7713b1edbc 9751 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 9752 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9753 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1_MASK)
AnnaBridge 171:3a7713b1edbc 9754 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 9755 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 9756 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1_MASK)
AnnaBridge 171:3a7713b1edbc 9757 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 9758 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9759 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2_MASK)
AnnaBridge 171:3a7713b1edbc 9760 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 9761 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9762 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2_MASK)
AnnaBridge 171:3a7713b1edbc 9763 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 9764 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9765 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3_MASK)
AnnaBridge 171:3a7713b1edbc 9766 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 9767 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9768 #define XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3_MASK)
AnnaBridge 171:3a7713b1edbc 9769
AnnaBridge 171:3a7713b1edbc 9770 /*! @name DCOC_STAT - DCOC Status */
AnnaBridge 171:3a7713b1edbc 9771 #define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 9772 #define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9773 #define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_I_MASK)
AnnaBridge 171:3a7713b1edbc 9774 #define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_MASK (0x3F00U)
AnnaBridge 171:3a7713b1edbc 9775 #define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9776 #define XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_BBA_DCOC_Q_MASK)
AnnaBridge 171:3a7713b1edbc 9777 #define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 9778 #define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9779 #define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_I_MASK)
AnnaBridge 171:3a7713b1edbc 9780 #define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9781 #define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9782 #define XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_SHIFT)) & XCVR_RX_DIG_DCOC_STAT_TZA_DCOC_Q_MASK)
AnnaBridge 171:3a7713b1edbc 9783
AnnaBridge 171:3a7713b1edbc 9784 /*! @name DCOC_DC_EST - DCOC DC Estimate */
AnnaBridge 171:3a7713b1edbc 9785 #define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 9786 #define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9787 #define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_SHIFT)) & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK)
AnnaBridge 171:3a7713b1edbc 9788 #define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 9789 #define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9790 #define XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT)) & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK)
AnnaBridge 171:3a7713b1edbc 9791
AnnaBridge 171:3a7713b1edbc 9792 /*! @name DCOC_CAL_RCP - DCOC Calibration Reciprocals */
AnnaBridge 171:3a7713b1edbc 9793 #define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK (0x7FFU)
AnnaBridge 171:3a7713b1edbc 9794 #define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9795 #define XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK)
AnnaBridge 171:3a7713b1edbc 9796 #define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK (0x7FF0000U)
AnnaBridge 171:3a7713b1edbc 9797 #define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9798 #define XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK)
AnnaBridge 171:3a7713b1edbc 9799
AnnaBridge 171:3a7713b1edbc 9800 /*! @name IQMC_CTRL - IQMC Control */
AnnaBridge 171:3a7713b1edbc 9801 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9802 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9803 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_CAL_EN_MASK)
AnnaBridge 171:3a7713b1edbc 9804 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 9805 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9806 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_NUM_ITER_MASK)
AnnaBridge 171:3a7713b1edbc 9807 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_MASK (0x7FF0000U)
AnnaBridge 171:3a7713b1edbc 9808 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9809 #define XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CTRL_IQMC_DC_GAIN_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 9810
AnnaBridge 171:3a7713b1edbc 9811 /*! @name IQMC_CAL - IQMC Calibration */
AnnaBridge 171:3a7713b1edbc 9812 #define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_MASK (0x7FFU)
AnnaBridge 171:3a7713b1edbc 9813 #define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9814 #define XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CAL_IQMC_GAIN_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 9815 #define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 9816 #define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9817 #define XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT)) & XCVR_RX_DIG_IQMC_CAL_IQMC_PHASE_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 9818
AnnaBridge 171:3a7713b1edbc 9819 /*! @name LNA_GAIN_VAL_3_0 - LNA_GAIN Step Values 3..0 */
AnnaBridge 171:3a7713b1edbc 9820 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9821 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9822 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0_MASK)
AnnaBridge 171:3a7713b1edbc 9823 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 9824 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9825 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1_MASK)
AnnaBridge 171:3a7713b1edbc 9826 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 9827 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9828 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2_MASK)
AnnaBridge 171:3a7713b1edbc 9829 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9830 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9831 #define XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3_MASK)
AnnaBridge 171:3a7713b1edbc 9832
AnnaBridge 171:3a7713b1edbc 9833 /*! @name LNA_GAIN_VAL_7_4 - LNA_GAIN Step Values 7..4 */
AnnaBridge 171:3a7713b1edbc 9834 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9835 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9836 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4_MASK)
AnnaBridge 171:3a7713b1edbc 9837 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 9838 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9839 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5_MASK)
AnnaBridge 171:3a7713b1edbc 9840 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 9841 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9842 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6_MASK)
AnnaBridge 171:3a7713b1edbc 9843 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9844 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9845 #define XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7_MASK)
AnnaBridge 171:3a7713b1edbc 9846
AnnaBridge 171:3a7713b1edbc 9847 /*! @name LNA_GAIN_VAL_8 - LNA_GAIN Step Values 8 */
AnnaBridge 171:3a7713b1edbc 9848 #define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9849 #define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9850 #define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8_MASK)
AnnaBridge 171:3a7713b1edbc 9851 #define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 9852 #define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9853 #define XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9_MASK)
AnnaBridge 171:3a7713b1edbc 9854
AnnaBridge 171:3a7713b1edbc 9855 /*! @name BBA_RES_TUNE_VAL_7_0 - BBA Resistor Tune Values 7..0 */
AnnaBridge 171:3a7713b1edbc 9856 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 9857 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9858 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0_MASK)
AnnaBridge 171:3a7713b1edbc 9859 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 9860 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9861 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1_MASK)
AnnaBridge 171:3a7713b1edbc 9862 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 9863 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9864 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2_MASK)
AnnaBridge 171:3a7713b1edbc 9865 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 9866 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 9867 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3_MASK)
AnnaBridge 171:3a7713b1edbc 9868 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 9869 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9870 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4_MASK)
AnnaBridge 171:3a7713b1edbc 9871 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 9872 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9873 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5_MASK)
AnnaBridge 171:3a7713b1edbc 9874 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 9875 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9876 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6_MASK)
AnnaBridge 171:3a7713b1edbc 9877 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 9878 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9879 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7_MASK)
AnnaBridge 171:3a7713b1edbc 9880
AnnaBridge 171:3a7713b1edbc 9881 /*! @name BBA_RES_TUNE_VAL_10_8 - BBA Resistor Tune Values 10..8 */
AnnaBridge 171:3a7713b1edbc 9882 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 9883 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9884 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8_MASK)
AnnaBridge 171:3a7713b1edbc 9885 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 9886 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9887 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9_MASK)
AnnaBridge 171:3a7713b1edbc 9888 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 9889 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9890 #define XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10_MASK)
AnnaBridge 171:3a7713b1edbc 9891
AnnaBridge 171:3a7713b1edbc 9892 /*! @name LNA_GAIN_LIN_VAL_2_0 - LNA Linear Gain Values 2..0 */
AnnaBridge 171:3a7713b1edbc 9893 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 9894 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9895 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0_MASK)
AnnaBridge 171:3a7713b1edbc 9896 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_MASK (0xFFC00U)
AnnaBridge 171:3a7713b1edbc 9897 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 9898 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1_MASK)
AnnaBridge 171:3a7713b1edbc 9899 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_MASK (0x3FF00000U)
AnnaBridge 171:3a7713b1edbc 9900 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9901 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2_MASK)
AnnaBridge 171:3a7713b1edbc 9902
AnnaBridge 171:3a7713b1edbc 9903 /*! @name LNA_GAIN_LIN_VAL_5_3 - LNA Linear Gain Values 5..3 */
AnnaBridge 171:3a7713b1edbc 9904 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 9905 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9906 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3_MASK)
AnnaBridge 171:3a7713b1edbc 9907 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_MASK (0xFFC00U)
AnnaBridge 171:3a7713b1edbc 9908 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 9909 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4_MASK)
AnnaBridge 171:3a7713b1edbc 9910 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_MASK (0x3FF00000U)
AnnaBridge 171:3a7713b1edbc 9911 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9912 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5_MASK)
AnnaBridge 171:3a7713b1edbc 9913
AnnaBridge 171:3a7713b1edbc 9914 /*! @name LNA_GAIN_LIN_VAL_8_6 - LNA Linear Gain Values 8..6 */
AnnaBridge 171:3a7713b1edbc 9915 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 9916 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9917 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6_MASK)
AnnaBridge 171:3a7713b1edbc 9918 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_MASK (0xFFC00U)
AnnaBridge 171:3a7713b1edbc 9919 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 9920 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7_MASK)
AnnaBridge 171:3a7713b1edbc 9921 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_MASK (0x3FF00000U)
AnnaBridge 171:3a7713b1edbc 9922 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9923 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8_MASK)
AnnaBridge 171:3a7713b1edbc 9924
AnnaBridge 171:3a7713b1edbc 9925 /*! @name LNA_GAIN_LIN_VAL_9 - LNA Linear Gain Values 9 */
AnnaBridge 171:3a7713b1edbc 9926 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 9927 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9928 #define XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_SHIFT)) & XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9_MASK)
AnnaBridge 171:3a7713b1edbc 9929
AnnaBridge 171:3a7713b1edbc 9930 /*! @name BBA_RES_TUNE_LIN_VAL_3_0 - BBA Resistor Tune Values 3..0 */
AnnaBridge 171:3a7713b1edbc 9931 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9932 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9933 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0_MASK)
AnnaBridge 171:3a7713b1edbc 9934 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 9935 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9936 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1_MASK)
AnnaBridge 171:3a7713b1edbc 9937 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 9938 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9939 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2_MASK)
AnnaBridge 171:3a7713b1edbc 9940 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9941 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9942 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3_MASK)
AnnaBridge 171:3a7713b1edbc 9943
AnnaBridge 171:3a7713b1edbc 9944 /*! @name BBA_RES_TUNE_LIN_VAL_7_4 - BBA Resistor Tune Values 7..4 */
AnnaBridge 171:3a7713b1edbc 9945 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9946 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9947 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4_MASK)
AnnaBridge 171:3a7713b1edbc 9948 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 9949 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9950 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5_MASK)
AnnaBridge 171:3a7713b1edbc 9951 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 9952 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9953 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6_MASK)
AnnaBridge 171:3a7713b1edbc 9954 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9955 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9956 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7_MASK)
AnnaBridge 171:3a7713b1edbc 9957
AnnaBridge 171:3a7713b1edbc 9958 /*! @name BBA_RES_TUNE_LIN_VAL_10_8 - BBA Resistor Tune Values 10..8 */
AnnaBridge 171:3a7713b1edbc 9959 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 9960 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9961 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8_MASK)
AnnaBridge 171:3a7713b1edbc 9962 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_MASK (0xFFC00U)
AnnaBridge 171:3a7713b1edbc 9963 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 9964 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9_MASK)
AnnaBridge 171:3a7713b1edbc 9965 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_MASK (0x3FF00000U)
AnnaBridge 171:3a7713b1edbc 9966 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9967 #define XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_SHIFT)) & XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10_MASK)
AnnaBridge 171:3a7713b1edbc 9968
AnnaBridge 171:3a7713b1edbc 9969 /*! @name AGC_GAIN_TBL_03_00 - AGC Gain Tables Step 03..00 */
AnnaBridge 171:3a7713b1edbc 9970 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 9971 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9972 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00_MASK)
AnnaBridge 171:3a7713b1edbc 9973 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 9974 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9975 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00_MASK)
AnnaBridge 171:3a7713b1edbc 9976 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 9977 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9978 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01_MASK)
AnnaBridge 171:3a7713b1edbc 9979 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 9980 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 9981 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01_MASK)
AnnaBridge 171:3a7713b1edbc 9982 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 9983 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9984 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02_MASK)
AnnaBridge 171:3a7713b1edbc 9985 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 9986 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9987 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02_MASK)
AnnaBridge 171:3a7713b1edbc 9988 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 9989 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9990 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03_MASK)
AnnaBridge 171:3a7713b1edbc 9991 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 9992 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9993 #define XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03_MASK)
AnnaBridge 171:3a7713b1edbc 9994
AnnaBridge 171:3a7713b1edbc 9995 /*! @name AGC_GAIN_TBL_07_04 - AGC Gain Tables Step 07..04 */
AnnaBridge 171:3a7713b1edbc 9996 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 9997 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9998 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04_MASK)
AnnaBridge 171:3a7713b1edbc 9999 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 10000 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10001 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04_MASK)
AnnaBridge 171:3a7713b1edbc 10002 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 10003 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10004 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05_MASK)
AnnaBridge 171:3a7713b1edbc 10005 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 10006 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10007 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05_MASK)
AnnaBridge 171:3a7713b1edbc 10008 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 10009 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10010 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06_MASK)
AnnaBridge 171:3a7713b1edbc 10011 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 10012 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10013 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06_MASK)
AnnaBridge 171:3a7713b1edbc 10014 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 10015 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10016 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07_MASK)
AnnaBridge 171:3a7713b1edbc 10017 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 10018 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10019 #define XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07_MASK)
AnnaBridge 171:3a7713b1edbc 10020
AnnaBridge 171:3a7713b1edbc 10021 /*! @name AGC_GAIN_TBL_11_08 - AGC Gain Tables Step 11..08 */
AnnaBridge 171:3a7713b1edbc 10022 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 10023 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10024 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08_MASK)
AnnaBridge 171:3a7713b1edbc 10025 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 10026 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10027 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08_MASK)
AnnaBridge 171:3a7713b1edbc 10028 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 10029 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10030 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09_MASK)
AnnaBridge 171:3a7713b1edbc 10031 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 10032 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10033 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09_MASK)
AnnaBridge 171:3a7713b1edbc 10034 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 10035 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10036 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10_MASK)
AnnaBridge 171:3a7713b1edbc 10037 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 10038 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10039 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10_MASK)
AnnaBridge 171:3a7713b1edbc 10040 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 10041 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10042 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11_MASK)
AnnaBridge 171:3a7713b1edbc 10043 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 10044 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10045 #define XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11_MASK)
AnnaBridge 171:3a7713b1edbc 10046
AnnaBridge 171:3a7713b1edbc 10047 /*! @name AGC_GAIN_TBL_15_12 - AGC Gain Tables Step 15..12 */
AnnaBridge 171:3a7713b1edbc 10048 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 10049 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10050 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12_MASK)
AnnaBridge 171:3a7713b1edbc 10051 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 10052 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10053 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12_MASK)
AnnaBridge 171:3a7713b1edbc 10054 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 10055 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10056 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13_MASK)
AnnaBridge 171:3a7713b1edbc 10057 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 10058 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10059 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13_MASK)
AnnaBridge 171:3a7713b1edbc 10060 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 10061 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10062 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14_MASK)
AnnaBridge 171:3a7713b1edbc 10063 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 10064 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10065 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14_MASK)
AnnaBridge 171:3a7713b1edbc 10066 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 10067 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10068 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15_MASK)
AnnaBridge 171:3a7713b1edbc 10069 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 10070 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10071 #define XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15_MASK)
AnnaBridge 171:3a7713b1edbc 10072
AnnaBridge 171:3a7713b1edbc 10073 /*! @name AGC_GAIN_TBL_19_16 - AGC Gain Tables Step 19..16 */
AnnaBridge 171:3a7713b1edbc 10074 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 10075 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10076 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16_MASK)
AnnaBridge 171:3a7713b1edbc 10077 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 10078 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10079 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16_MASK)
AnnaBridge 171:3a7713b1edbc 10080 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 10081 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10082 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17_MASK)
AnnaBridge 171:3a7713b1edbc 10083 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 10084 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10085 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17_MASK)
AnnaBridge 171:3a7713b1edbc 10086 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 10087 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10088 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18_MASK)
AnnaBridge 171:3a7713b1edbc 10089 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 10090 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10091 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18_MASK)
AnnaBridge 171:3a7713b1edbc 10092 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 10093 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10094 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19_MASK)
AnnaBridge 171:3a7713b1edbc 10095 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 10096 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10097 #define XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19_MASK)
AnnaBridge 171:3a7713b1edbc 10098
AnnaBridge 171:3a7713b1edbc 10099 /*! @name AGC_GAIN_TBL_23_20 - AGC Gain Tables Step 23..20 */
AnnaBridge 171:3a7713b1edbc 10100 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 10101 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10102 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20_MASK)
AnnaBridge 171:3a7713b1edbc 10103 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 10104 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10105 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20_MASK)
AnnaBridge 171:3a7713b1edbc 10106 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 10107 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10108 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21_MASK)
AnnaBridge 171:3a7713b1edbc 10109 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 10110 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10111 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21_MASK)
AnnaBridge 171:3a7713b1edbc 10112 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 10113 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10114 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22_MASK)
AnnaBridge 171:3a7713b1edbc 10115 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 10116 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10117 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22_MASK)
AnnaBridge 171:3a7713b1edbc 10118 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 10119 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10120 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23_MASK)
AnnaBridge 171:3a7713b1edbc 10121 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 10122 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10123 #define XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23_MASK)
AnnaBridge 171:3a7713b1edbc 10124
AnnaBridge 171:3a7713b1edbc 10125 /*! @name AGC_GAIN_TBL_26_24 - AGC Gain Tables Step 26..24 */
AnnaBridge 171:3a7713b1edbc 10126 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 10127 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10128 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24_MASK)
AnnaBridge 171:3a7713b1edbc 10129 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 10130 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10131 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24_MASK)
AnnaBridge 171:3a7713b1edbc 10132 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 10133 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10134 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25_MASK)
AnnaBridge 171:3a7713b1edbc 10135 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 10136 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10137 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25_MASK)
AnnaBridge 171:3a7713b1edbc 10138 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 10139 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10140 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26_MASK)
AnnaBridge 171:3a7713b1edbc 10141 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 10142 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10143 #define XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_SHIFT)) & XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26_MASK)
AnnaBridge 171:3a7713b1edbc 10144
AnnaBridge 171:3a7713b1edbc 10145 /*! @name DCOC_OFFSET - DCOC Offset */
AnnaBridge 171:3a7713b1edbc 10146 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 10147 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10148 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_I_MASK)
AnnaBridge 171:3a7713b1edbc 10149 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_MASK (0x3F00U)
AnnaBridge 171:3a7713b1edbc 10150 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10151 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_BBA_OFFSET_Q_MASK)
AnnaBridge 171:3a7713b1edbc 10152 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 10153 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10154 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_I_MASK)
AnnaBridge 171:3a7713b1edbc 10155 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 10156 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10157 #define XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DCOC_OFFSET_DCOC_TZA_OFFSET_Q_MASK)
AnnaBridge 171:3a7713b1edbc 10158
AnnaBridge 171:3a7713b1edbc 10159 /* The count of XCVR_RX_DIG_DCOC_OFFSET */
AnnaBridge 171:3a7713b1edbc 10160 #define XCVR_RX_DIG_DCOC_OFFSET_COUNT (27U)
AnnaBridge 171:3a7713b1edbc 10161
AnnaBridge 171:3a7713b1edbc 10162 /*! @name DCOC_BBA_STEP - DCOC BBA DAC Step */
AnnaBridge 171:3a7713b1edbc 10163 #define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10164 #define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10165 #define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_SHIFT)) & XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP_MASK)
AnnaBridge 171:3a7713b1edbc 10166 #define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK (0x1FF0000U)
AnnaBridge 171:3a7713b1edbc 10167 #define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10168 #define XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_SHIFT)) & XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_MASK)
AnnaBridge 171:3a7713b1edbc 10169
AnnaBridge 171:3a7713b1edbc 10170 /*! @name DCOC_TZA_STEP_0 - DCOC TZA DAC Step 0 */
AnnaBridge 171:3a7713b1edbc 10171 #define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10172 #define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10173 #define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0_MASK)
AnnaBridge 171:3a7713b1edbc 10174 #define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 10175 #define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10176 #define XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0_MASK)
AnnaBridge 171:3a7713b1edbc 10177
AnnaBridge 171:3a7713b1edbc 10178 /*! @name DCOC_TZA_STEP_1 - DCOC TZA DAC Step 1 */
AnnaBridge 171:3a7713b1edbc 10179 #define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10180 #define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10181 #define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1_MASK)
AnnaBridge 171:3a7713b1edbc 10182 #define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 10183 #define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10184 #define XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1_MASK)
AnnaBridge 171:3a7713b1edbc 10185
AnnaBridge 171:3a7713b1edbc 10186 /*! @name DCOC_TZA_STEP_2 - DCOC TZA DAC Step 2 */
AnnaBridge 171:3a7713b1edbc 10187 #define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10188 #define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10189 #define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2_MASK)
AnnaBridge 171:3a7713b1edbc 10190 #define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 10191 #define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10192 #define XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2_MASK)
AnnaBridge 171:3a7713b1edbc 10193
AnnaBridge 171:3a7713b1edbc 10194 /*! @name DCOC_TZA_STEP_3 - DCOC TZA DAC Step 3 */
AnnaBridge 171:3a7713b1edbc 10195 #define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10196 #define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10197 #define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3_MASK)
AnnaBridge 171:3a7713b1edbc 10198 #define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 10199 #define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10200 #define XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3_MASK)
AnnaBridge 171:3a7713b1edbc 10201
AnnaBridge 171:3a7713b1edbc 10202 /*! @name DCOC_TZA_STEP_4 - DCOC TZA DAC Step 4 */
AnnaBridge 171:3a7713b1edbc 10203 #define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10204 #define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10205 #define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4_MASK)
AnnaBridge 171:3a7713b1edbc 10206 #define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 10207 #define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10208 #define XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4_MASK)
AnnaBridge 171:3a7713b1edbc 10209
AnnaBridge 171:3a7713b1edbc 10210 /*! @name DCOC_TZA_STEP_5 - DCOC TZA DAC Step 5 */
AnnaBridge 171:3a7713b1edbc 10211 #define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10212 #define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10213 #define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5_MASK)
AnnaBridge 171:3a7713b1edbc 10214 #define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 10215 #define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10216 #define XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5_MASK)
AnnaBridge 171:3a7713b1edbc 10217
AnnaBridge 171:3a7713b1edbc 10218 /*! @name DCOC_TZA_STEP_6 - DCOC TZA DAC Step 6 */
AnnaBridge 171:3a7713b1edbc 10219 #define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10220 #define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10221 #define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6_MASK)
AnnaBridge 171:3a7713b1edbc 10222 #define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 10223 #define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10224 #define XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6_MASK)
AnnaBridge 171:3a7713b1edbc 10225
AnnaBridge 171:3a7713b1edbc 10226 /*! @name DCOC_TZA_STEP_7 - DCOC TZA DAC Step 7 */
AnnaBridge 171:3a7713b1edbc 10227 #define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10228 #define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10229 #define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7_MASK)
AnnaBridge 171:3a7713b1edbc 10230 #define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_MASK (0x1FFF0000U)
AnnaBridge 171:3a7713b1edbc 10231 #define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10232 #define XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7_MASK)
AnnaBridge 171:3a7713b1edbc 10233
AnnaBridge 171:3a7713b1edbc 10234 /*! @name DCOC_TZA_STEP_8 - DCOC TZA DAC Step 5 */
AnnaBridge 171:3a7713b1edbc 10235 #define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10236 #define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10237 #define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8_MASK)
AnnaBridge 171:3a7713b1edbc 10238 #define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_MASK (0x1FFF0000U)
AnnaBridge 171:3a7713b1edbc 10239 #define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10240 #define XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8_MASK)
AnnaBridge 171:3a7713b1edbc 10241
AnnaBridge 171:3a7713b1edbc 10242 /*! @name DCOC_TZA_STEP_9 - DCOC TZA DAC Step 9 */
AnnaBridge 171:3a7713b1edbc 10243 #define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10244 #define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10245 #define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9_MASK)
AnnaBridge 171:3a7713b1edbc 10246 #define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_MASK (0x3FFF0000U)
AnnaBridge 171:3a7713b1edbc 10247 #define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10248 #define XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9_MASK)
AnnaBridge 171:3a7713b1edbc 10249
AnnaBridge 171:3a7713b1edbc 10250 /*! @name DCOC_TZA_STEP_10 - DCOC TZA DAC Step 10 */
AnnaBridge 171:3a7713b1edbc 10251 #define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10252 #define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10253 #define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10_MASK)
AnnaBridge 171:3a7713b1edbc 10254 #define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_MASK (0x3FFF0000U)
AnnaBridge 171:3a7713b1edbc 10255 #define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10256 #define XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_SHIFT)) & XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10_MASK)
AnnaBridge 171:3a7713b1edbc 10257
AnnaBridge 171:3a7713b1edbc 10258 /*! @name DCOC_CAL_ALPHA - DCOC Calibration Alpha */
AnnaBridge 171:3a7713b1edbc 10259 #define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_MASK (0x7FFU)
AnnaBridge 171:3a7713b1edbc 10260 #define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10261 #define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_MASK)
AnnaBridge 171:3a7713b1edbc 10262 #define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_MASK (0x7FF0000U)
AnnaBridge 171:3a7713b1edbc 10263 #define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10264 #define XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_MASK)
AnnaBridge 171:3a7713b1edbc 10265
AnnaBridge 171:3a7713b1edbc 10266 /*! @name DCOC_CAL_BETA_Q - DCOC Calibration Beta Q */
AnnaBridge 171:3a7713b1edbc 10267 #define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_MASK (0x1FFFFU)
AnnaBridge 171:3a7713b1edbc 10268 #define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10269 #define XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_BETA_Q_DCOC_CAL_BETA_Q_MASK)
AnnaBridge 171:3a7713b1edbc 10270
AnnaBridge 171:3a7713b1edbc 10271 /*! @name DCOC_CAL_BETA_I - DCOC Calibration Beta I */
AnnaBridge 171:3a7713b1edbc 10272 #define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_MASK (0x1FFFFU)
AnnaBridge 171:3a7713b1edbc 10273 #define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10274 #define XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_BETA_I_DCOC_CAL_BETA_I_MASK)
AnnaBridge 171:3a7713b1edbc 10275
AnnaBridge 171:3a7713b1edbc 10276 /*! @name DCOC_CAL_GAMMA - DCOC Calibration Gamma */
AnnaBridge 171:3a7713b1edbc 10277 #define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10278 #define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10279 #define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_MASK)
AnnaBridge 171:3a7713b1edbc 10280 #define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 10281 #define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10282 #define XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_MASK)
AnnaBridge 171:3a7713b1edbc 10283
AnnaBridge 171:3a7713b1edbc 10284 /*! @name DCOC_CAL_IIR - DCOC Calibration IIR */
AnnaBridge 171:3a7713b1edbc 10285 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 10286 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10287 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 10288 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 10289 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10290 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 10291 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 10292 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10293 #define XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 10294
AnnaBridge 171:3a7713b1edbc 10295 /*! @name DCOC_CAL - DCOC Calibration Result */
AnnaBridge 171:3a7713b1edbc 10296 #define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 10297 #define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10298 #define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_I_MASK)
AnnaBridge 171:3a7713b1edbc 10299 #define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_MASK (0xFFF0000U)
AnnaBridge 171:3a7713b1edbc 10300 #define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10301 #define XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_SHIFT)) & XCVR_RX_DIG_DCOC_CAL_DCOC_CAL_RES_Q_MASK)
AnnaBridge 171:3a7713b1edbc 10302
AnnaBridge 171:3a7713b1edbc 10303 /* The count of XCVR_RX_DIG_DCOC_CAL */
AnnaBridge 171:3a7713b1edbc 10304 #define XCVR_RX_DIG_DCOC_CAL_COUNT (3U)
AnnaBridge 171:3a7713b1edbc 10305
AnnaBridge 171:3a7713b1edbc 10306 /*! @name CCA_ED_LQI_CTRL_0 - RX_DIG CCA ED LQI Control Register 0 */
AnnaBridge 171:3a7713b1edbc 10307 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 10308 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10309 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 10310 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 10311 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10312 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 10313 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 10314 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10315 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR_MASK)
AnnaBridge 171:3a7713b1edbc 10316 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_MASK (0x3F000000U)
AnnaBridge 171:3a7713b1edbc 10317 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10318 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 10319
AnnaBridge 171:3a7713b1edbc 10320 /*! @name CCA_ED_LQI_CTRL_1 - RX_DIG CCA ED LQI Control Register 1 */
AnnaBridge 171:3a7713b1edbc 10321 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 10322 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10323 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY_MASK)
AnnaBridge 171:3a7713b1edbc 10324 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_MASK (0x1C0U)
AnnaBridge 171:3a7713b1edbc 10325 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10326 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR_MASK)
AnnaBridge 171:3a7713b1edbc 10327 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_MASK (0xE00U)
AnnaBridge 171:3a7713b1edbc 10328 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 10329 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT_MASK)
AnnaBridge 171:3a7713b1edbc 10330 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 10331 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10332 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS_MASK)
AnnaBridge 171:3a7713b1edbc 10333 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 10334 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10335 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 10336 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 10337 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 10338 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 10339 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 10340 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 10341 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 10342 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 10343 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 10344 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 10345 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 10346 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10347 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE_MASK)
AnnaBridge 171:3a7713b1edbc 10348 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 10349 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 10350 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH_MASK)
AnnaBridge 171:3a7713b1edbc 10351 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 10352 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10353 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT_MASK)
AnnaBridge 171:3a7713b1edbc 10354 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 10355 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10356 #define XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS_MASK)
AnnaBridge 171:3a7713b1edbc 10357
AnnaBridge 171:3a7713b1edbc 10358 /*! @name CCA_ED_LQI_STAT_0 - RX_DIG CCA ED LQI Status Register 0 */
AnnaBridge 171:3a7713b1edbc 10359 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 10360 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10361 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_LQI_OUT_MASK)
AnnaBridge 171:3a7713b1edbc 10362 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 10363 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10364 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_ED_OUT_MASK)
AnnaBridge 171:3a7713b1edbc 10365 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 10366 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10367 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_SNR_OUT_MASK)
AnnaBridge 171:3a7713b1edbc 10368 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10369 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10370 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_CCA1_STATE_MASK)
AnnaBridge 171:3a7713b1edbc 10371 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10372 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10373 #define XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_SHIFT)) & XCVR_RX_DIG_CCA_ED_LQI_STAT_0_MEAS_COMPLETE_MASK)
AnnaBridge 171:3a7713b1edbc 10374
AnnaBridge 171:3a7713b1edbc 10375 /*! @name RX_CHF_COEF_0 - Receive Channel Filter Coefficient 0 */
AnnaBridge 171:3a7713b1edbc 10376 #define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 10377 #define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10378 #define XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_0_RX_CH_FILT_H0_MASK)
AnnaBridge 171:3a7713b1edbc 10379
AnnaBridge 171:3a7713b1edbc 10380 /*! @name RX_CHF_COEF_1 - Receive Channel Filter Coefficient 1 */
AnnaBridge 171:3a7713b1edbc 10381 #define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 10382 #define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10383 #define XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_1_RX_CH_FILT_H1_MASK)
AnnaBridge 171:3a7713b1edbc 10384
AnnaBridge 171:3a7713b1edbc 10385 /*! @name RX_CHF_COEF_2 - Receive Channel Filter Coefficient 2 */
AnnaBridge 171:3a7713b1edbc 10386 #define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 10387 #define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10388 #define XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_2_RX_CH_FILT_H2_MASK)
AnnaBridge 171:3a7713b1edbc 10389
AnnaBridge 171:3a7713b1edbc 10390 /*! @name RX_CHF_COEF_3 - Receive Channel Filter Coefficient 3 */
AnnaBridge 171:3a7713b1edbc 10391 #define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 10392 #define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10393 #define XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_3_RX_CH_FILT_H3_MASK)
AnnaBridge 171:3a7713b1edbc 10394
AnnaBridge 171:3a7713b1edbc 10395 /*! @name RX_CHF_COEF_4 - Receive Channel Filter Coefficient 4 */
AnnaBridge 171:3a7713b1edbc 10396 #define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 10397 #define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10398 #define XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_4_RX_CH_FILT_H4_MASK)
AnnaBridge 171:3a7713b1edbc 10399
AnnaBridge 171:3a7713b1edbc 10400 /*! @name RX_CHF_COEF_5 - Receive Channel Filter Coefficient 5 */
AnnaBridge 171:3a7713b1edbc 10401 #define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 10402 #define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10403 #define XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_5_RX_CH_FILT_H5_MASK)
AnnaBridge 171:3a7713b1edbc 10404
AnnaBridge 171:3a7713b1edbc 10405 /*! @name RX_CHF_COEF_6 - Receive Channel Filter Coefficient 6 */
AnnaBridge 171:3a7713b1edbc 10406 #define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 10407 #define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10408 #define XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_6_RX_CH_FILT_H6_MASK)
AnnaBridge 171:3a7713b1edbc 10409
AnnaBridge 171:3a7713b1edbc 10410 /*! @name RX_CHF_COEF_7 - Receive Channel Filter Coefficient 7 */
AnnaBridge 171:3a7713b1edbc 10411 #define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 10412 #define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10413 #define XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_7_RX_CH_FILT_H7_MASK)
AnnaBridge 171:3a7713b1edbc 10414
AnnaBridge 171:3a7713b1edbc 10415 /*! @name RX_CHF_COEF_8 - Receive Channel Filter Coefficient 8 */
AnnaBridge 171:3a7713b1edbc 10416 #define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 10417 #define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10418 #define XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_8_RX_CH_FILT_H8_MASK)
AnnaBridge 171:3a7713b1edbc 10419
AnnaBridge 171:3a7713b1edbc 10420 /*! @name RX_CHF_COEF_9 - Receive Channel Filter Coefficient 9 */
AnnaBridge 171:3a7713b1edbc 10421 #define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 10422 #define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10423 #define XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_9_RX_CH_FILT_H9_MASK)
AnnaBridge 171:3a7713b1edbc 10424
AnnaBridge 171:3a7713b1edbc 10425 /*! @name RX_CHF_COEF_10 - Receive Channel Filter Coefficient 10 */
AnnaBridge 171:3a7713b1edbc 10426 #define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 10427 #define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10428 #define XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_10_RX_CH_FILT_H10_MASK)
AnnaBridge 171:3a7713b1edbc 10429
AnnaBridge 171:3a7713b1edbc 10430 /*! @name RX_CHF_COEF_11 - Receive Channel Filter Coefficient 11 */
AnnaBridge 171:3a7713b1edbc 10431 #define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 10432 #define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10433 #define XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_SHIFT)) & XCVR_RX_DIG_RX_CHF_COEF_11_RX_CH_FILT_H11_MASK)
AnnaBridge 171:3a7713b1edbc 10434
AnnaBridge 171:3a7713b1edbc 10435 /*! @name AGC_MAN_AGC_IDX - AGC Manual AGC Index */
AnnaBridge 171:3a7713b1edbc 10436 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 10437 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10438 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 10439 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10440 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10441 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_MAN_IDX_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10442 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10443 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10444 #define XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_SHIFT)) & XCVR_RX_DIG_AGC_MAN_AGC_IDX_AGC_DCOC_START_PT_MASK)
AnnaBridge 171:3a7713b1edbc 10445
AnnaBridge 171:3a7713b1edbc 10446 /*! @name DC_RESID_CTRL - DC Residual Control */
AnnaBridge 171:3a7713b1edbc 10447 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 10448 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10449 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN_MASK)
AnnaBridge 171:3a7713b1edbc 10450 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 10451 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10452 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE_MASK)
AnnaBridge 171:3a7713b1edbc 10453 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 10454 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10455 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA_MASK)
AnnaBridge 171:3a7713b1edbc 10456 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 10457 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10458 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY_MASK)
AnnaBridge 171:3a7713b1edbc 10459 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 10460 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10461 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10462 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 10463 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10464 #define XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_SHIFT)) & XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 10465
AnnaBridge 171:3a7713b1edbc 10466 /*! @name DC_RESID_EST - DC Residual Estimate */
AnnaBridge 171:3a7713b1edbc 10467 #define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 10468 #define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10469 #define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_SHIFT)) & XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_I_MASK)
AnnaBridge 171:3a7713b1edbc 10470 #define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_MASK (0x1FFF0000U)
AnnaBridge 171:3a7713b1edbc 10471 #define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10472 #define XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_SHIFT)) & XCVR_RX_DIG_DC_RESID_EST_DC_RESID_OFFSET_Q_MASK)
AnnaBridge 171:3a7713b1edbc 10473
AnnaBridge 171:3a7713b1edbc 10474 /*! @name RX_RCCAL_CTRL0 - RX RC Calibration Control0 */
AnnaBridge 171:3a7713b1edbc 10475 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 10476 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10477 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET_MASK)
AnnaBridge 171:3a7713b1edbc 10478 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_MASK (0x1F0U)
AnnaBridge 171:3a7713b1edbc 10479 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10480 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 10481 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 10482 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 10483 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 10484 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 10485 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10486 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY_MASK)
AnnaBridge 171:3a7713b1edbc 10487 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 10488 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 10489 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV_MASK)
AnnaBridge 171:3a7713b1edbc 10490 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 10491 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10492 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET_MASK)
AnnaBridge 171:3a7713b1edbc 10493 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_MASK (0x1F00000U)
AnnaBridge 171:3a7713b1edbc 10494 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10495 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 10496 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10497 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10498 #define XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 10499
AnnaBridge 171:3a7713b1edbc 10500 /*! @name RX_RCCAL_CTRL1 - RX RC Calibration Control1 */
AnnaBridge 171:3a7713b1edbc 10501 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 10502 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10503 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET_MASK)
AnnaBridge 171:3a7713b1edbc 10504 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_MASK (0x1F0U)
AnnaBridge 171:3a7713b1edbc 10505 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10506 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 10507 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 10508 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 10509 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 10510 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 10511 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10512 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET_MASK)
AnnaBridge 171:3a7713b1edbc 10513 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_MASK (0x1F00000U)
AnnaBridge 171:3a7713b1edbc 10514 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10515 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 10516 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10517 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10518 #define XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 10519
AnnaBridge 171:3a7713b1edbc 10520 /*! @name RX_RCCAL_STAT - RX RC Calibration Status */
AnnaBridge 171:3a7713b1edbc 10521 #define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 10522 #define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10523 #define XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_RCCAL_CODE_MASK)
AnnaBridge 171:3a7713b1edbc 10524 #define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_MASK (0x3E0U)
AnnaBridge 171:3a7713b1edbc 10525 #define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10526 #define XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_ADC_RCCAL_MASK)
AnnaBridge 171:3a7713b1edbc 10527 #define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_MASK (0x7C00U)
AnnaBridge 171:3a7713b1edbc 10528 #define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 10529 #define XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_BBA2_RCCAL_MASK)
AnnaBridge 171:3a7713b1edbc 10530 #define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 10531 #define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10532 #define XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_BBA_RCCAL_MASK)
AnnaBridge 171:3a7713b1edbc 10533 #define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_MASK (0x3E00000U)
AnnaBridge 171:3a7713b1edbc 10534 #define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 10535 #define XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_SHIFT)) & XCVR_RX_DIG_RX_RCCAL_STAT_TZA_RCCAL_MASK)
AnnaBridge 171:3a7713b1edbc 10536
AnnaBridge 171:3a7713b1edbc 10537 /*! @name AUXPLL_FCAL_CTRL - Aux PLL Frequency Calibration Control */
AnnaBridge 171:3a7713b1edbc 10538 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 10539 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10540 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 10541 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10542 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10543 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_AUXPLL_DAC_CAL_ADJUST_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 10544 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 10545 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10546 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_RUN_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 10547 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 10548 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 10549 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_COMP_INV_MASK)
AnnaBridge 171:3a7713b1edbc 10550 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_MASK (0xC00U)
AnnaBridge 171:3a7713b1edbc 10551 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 10552 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_FCAL_SMP_DLY_MASK)
AnnaBridge 171:3a7713b1edbc 10553 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 10554 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10555 #define XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CTRL_DAC_CAL_ADJUST_MASK)
AnnaBridge 171:3a7713b1edbc 10556
AnnaBridge 171:3a7713b1edbc 10557 /*! @name AUXPLL_FCAL_CNT6 - Aux PLL Frequency Calibration Count 6 */
AnnaBridge 171:3a7713b1edbc 10558 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 10559 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10560 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_COUNT_6_MASK)
AnnaBridge 171:3a7713b1edbc 10561 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 10562 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10563 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT6_FCAL_BESTDIFF_MASK)
AnnaBridge 171:3a7713b1edbc 10564
AnnaBridge 171:3a7713b1edbc 10565 /*! @name AUXPLL_FCAL_CNT5_4 - Aux PLL Frequency Calibration Count 5 and 4 */
AnnaBridge 171:3a7713b1edbc 10566 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 10567 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10568 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_4_MASK)
AnnaBridge 171:3a7713b1edbc 10569 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 10570 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10571 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT5_4_FCAL_COUNT_5_MASK)
AnnaBridge 171:3a7713b1edbc 10572
AnnaBridge 171:3a7713b1edbc 10573 /*! @name AUXPLL_FCAL_CNT3_2 - Aux PLL Frequency Calibration Count 3 and 2 */
AnnaBridge 171:3a7713b1edbc 10574 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 10575 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10576 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_2_MASK)
AnnaBridge 171:3a7713b1edbc 10577 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 10578 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10579 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT3_2_FCAL_COUNT_3_MASK)
AnnaBridge 171:3a7713b1edbc 10580
AnnaBridge 171:3a7713b1edbc 10581 /*! @name AUXPLL_FCAL_CNT1_0 - Aux PLL Frequency Calibration Count 1 and 0 */
AnnaBridge 171:3a7713b1edbc 10582 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 10583 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10584 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_0_MASK)
AnnaBridge 171:3a7713b1edbc 10585 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 10586 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10587 #define XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_SHIFT)) & XCVR_RX_DIG_AUXPLL_FCAL_CNT1_0_FCAL_COUNT_1_MASK)
AnnaBridge 171:3a7713b1edbc 10588
AnnaBridge 171:3a7713b1edbc 10589 /*! @name RXDIG_DFT - RXDIG DFT */
AnnaBridge 171:3a7713b1edbc 10590 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 10591 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10592 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ_SHIFT)) & XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_FREQ_MASK)
AnnaBridge 171:3a7713b1edbc 10593 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10594 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10595 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE_SHIFT)) & XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_SCALE_MASK)
AnnaBridge 171:3a7713b1edbc 10596 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10597 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10598 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN_SHIFT)) & XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_TZA_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10599 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10600 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10601 #define XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN_SHIFT)) & XCVR_RX_DIG_RXDIG_DFT_DFT_TONE_BBA_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10602
AnnaBridge 171:3a7713b1edbc 10603
AnnaBridge 171:3a7713b1edbc 10604 /*!
AnnaBridge 171:3a7713b1edbc 10605 * @}
AnnaBridge 171:3a7713b1edbc 10606 */ /* end of group XCVR_RX_DIG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10607
AnnaBridge 171:3a7713b1edbc 10608
AnnaBridge 171:3a7713b1edbc 10609 /* XCVR_RX_DIG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10610 /** Peripheral XCVR_RX_DIG base address */
AnnaBridge 171:3a7713b1edbc 10611 #define XCVR_RX_DIG_BASE (0x4005C000u)
AnnaBridge 171:3a7713b1edbc 10612 /** Peripheral XCVR_RX_DIG base pointer */
AnnaBridge 171:3a7713b1edbc 10613 #define XCVR_RX_DIG ((XCVR_RX_DIG_Type *)XCVR_RX_DIG_BASE)
AnnaBridge 171:3a7713b1edbc 10614 /** Array initializer of XCVR_RX_DIG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10615 #define XCVR_RX_DIG_BASE_ADDRS { XCVR_RX_DIG_BASE }
AnnaBridge 171:3a7713b1edbc 10616 /** Array initializer of XCVR_RX_DIG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10617 #define XCVR_RX_DIG_BASE_PTRS { XCVR_RX_DIG }
AnnaBridge 171:3a7713b1edbc 10618
AnnaBridge 171:3a7713b1edbc 10619 /*!
AnnaBridge 171:3a7713b1edbc 10620 * @}
AnnaBridge 171:3a7713b1edbc 10621 */ /* end of group XCVR_RX_DIG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10622
AnnaBridge 171:3a7713b1edbc 10623
AnnaBridge 171:3a7713b1edbc 10624 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10625 -- XCVR_TSM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10626 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10627
AnnaBridge 171:3a7713b1edbc 10628 /*!
AnnaBridge 171:3a7713b1edbc 10629 * @addtogroup XCVR_TSM_Peripheral_Access_Layer XCVR_TSM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10630 * @{
AnnaBridge 171:3a7713b1edbc 10631 */
AnnaBridge 171:3a7713b1edbc 10632
AnnaBridge 171:3a7713b1edbc 10633 /** XCVR_TSM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10634 typedef struct {
AnnaBridge 171:3a7713b1edbc 10635 __IO uint32_t CTRL; /**< TRANSCEIVER SEQUENCE MANAGER CONTROL, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 10636 __IO uint32_t END_OF_SEQ; /**< TSM END OF SEQUENCE, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 10637 __IO uint32_t OVRD0; /**< TSM OVERRIDE REGISTER 0, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 10638 __IO uint32_t OVRD1; /**< TSM OVERRIDE REGISTER 1, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 10639 __IO uint32_t OVRD2; /**< TSM OVERRIDE REGISTER 2, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 10640 __IO uint32_t OVRD3; /**< TSM OVERRIDE REGISTER 3, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 10641 __IO uint32_t PA_POWER; /**< PA POWER, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 10642 __IO uint32_t PA_RAMP_TBL0; /**< PA RAMP TABLE 0, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 10643 __IO uint32_t PA_RAMP_TBL1; /**< PA RAMP TABLE 1, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 10644 __IO uint32_t RECYCLE_COUNT; /**< TSM RECYCLE COUNT, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 10645 __IO uint32_t FAST_CTRL1; /**< TSM FAST WARMUP CONTROL REGISTER 1, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 10646 __IO uint32_t FAST_CTRL2; /**< TSM FAST WARMUP CONTROL REGISTER 2, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 10647 __IO uint32_t TIMING00; /**< TSM_TIMING00, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 10648 __IO uint32_t TIMING01; /**< TSM_TIMING01, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 10649 __IO uint32_t TIMING02; /**< TSM_TIMING02, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 10650 __IO uint32_t TIMING03; /**< TSM_TIMING03, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 10651 __IO uint32_t TIMING04; /**< TSM_TIMING04, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 10652 __IO uint32_t TIMING05; /**< TSM_TIMING05, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 10653 __IO uint32_t TIMING06; /**< TSM_TIMING06, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 10654 __IO uint32_t TIMING07; /**< TSM_TIMING07, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 10655 __IO uint32_t TIMING08; /**< TSM_TIMING08, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 10656 __IO uint32_t TIMING09; /**< TSM_TIMING09, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 10657 __IO uint32_t TIMING10; /**< TSM_TIMING10, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 10658 __IO uint32_t TIMING11; /**< TSM_TIMING11, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 10659 __IO uint32_t TIMING12; /**< TSM_TIMING12, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 10660 __IO uint32_t TIMING13; /**< TSM_TIMING13, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 10661 __IO uint32_t TIMING14; /**< TSM_TIMING14, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 10662 __IO uint32_t TIMING15; /**< TSM_TIMING15, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 10663 __IO uint32_t TIMING16; /**< TSM_TIMING16, offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 10664 __IO uint32_t TIMING17; /**< TSM_TIMING17, offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 10665 __IO uint32_t TIMING18; /**< TSM_TIMING18, offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 10666 __IO uint32_t TIMING19; /**< TSM_TIMING19, offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 10667 __IO uint32_t TIMING20; /**< TSM_TIMING20, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 10668 __IO uint32_t TIMING21; /**< TSM_TIMING21, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 10669 __IO uint32_t TIMING22; /**< TSM_TIMING22, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 10670 __IO uint32_t TIMING23; /**< TSM_TIMING23, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 10671 __IO uint32_t TIMING24; /**< TSM_TIMING24, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 10672 __IO uint32_t TIMING25; /**< TSM_TIMING25, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 10673 __IO uint32_t TIMING26; /**< TSM_TIMING26, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 10674 __IO uint32_t TIMING27; /**< TSM_TIMING27, offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 10675 __IO uint32_t TIMING28; /**< TSM_TIMING28, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 10676 __IO uint32_t TIMING29; /**< TSM_TIMING29, offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 10677 __IO uint32_t TIMING30; /**< TSM_TIMING30, offset: 0xA8 */
AnnaBridge 171:3a7713b1edbc 10678 __IO uint32_t TIMING31; /**< TSM_TIMING31, offset: 0xAC */
AnnaBridge 171:3a7713b1edbc 10679 __IO uint32_t TIMING32; /**< TSM_TIMING32, offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 10680 __IO uint32_t TIMING33; /**< TSM_TIMING33, offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 10681 __IO uint32_t TIMING34; /**< TSM_TIMING34, offset: 0xB8 */
AnnaBridge 171:3a7713b1edbc 10682 __IO uint32_t TIMING35; /**< TSM_TIMING35, offset: 0xBC */
AnnaBridge 171:3a7713b1edbc 10683 __IO uint32_t TIMING36; /**< TSM_TIMING36, offset: 0xC0 */
AnnaBridge 171:3a7713b1edbc 10684 __IO uint32_t TIMING37; /**< TSM_TIMING37, offset: 0xC4 */
AnnaBridge 171:3a7713b1edbc 10685 __IO uint32_t TIMING38; /**< TSM_TIMING38, offset: 0xC8 */
AnnaBridge 171:3a7713b1edbc 10686 __IO uint32_t TIMING39; /**< TSM_TIMING39, offset: 0xCC */
AnnaBridge 171:3a7713b1edbc 10687 __IO uint32_t TIMING40; /**< TSM_TIMING40, offset: 0xD0 */
AnnaBridge 171:3a7713b1edbc 10688 __IO uint32_t TIMING41; /**< TSM_TIMING41, offset: 0xD4 */
AnnaBridge 171:3a7713b1edbc 10689 __IO uint32_t TIMING42; /**< TSM_TIMING42, offset: 0xD8 */
AnnaBridge 171:3a7713b1edbc 10690 __IO uint32_t TIMING43; /**< TSM_TIMING43, offset: 0xDC */
AnnaBridge 171:3a7713b1edbc 10691 __IO uint32_t TIMING44; /**< TSM_TIMING44, offset: 0xE0 */
AnnaBridge 171:3a7713b1edbc 10692 __IO uint32_t TIMING45; /**< TSM_TIMING45, offset: 0xE4 */
AnnaBridge 171:3a7713b1edbc 10693 __IO uint32_t TIMING46; /**< TSM_TIMING46, offset: 0xE8 */
AnnaBridge 171:3a7713b1edbc 10694 __IO uint32_t TIMING47; /**< TSM_TIMING47, offset: 0xEC */
AnnaBridge 171:3a7713b1edbc 10695 __IO uint32_t TIMING48; /**< TSM_TIMING48, offset: 0xF0 */
AnnaBridge 171:3a7713b1edbc 10696 __IO uint32_t TIMING49; /**< TSM_TIMING49, offset: 0xF4 */
AnnaBridge 171:3a7713b1edbc 10697 __IO uint32_t TIMING50; /**< TSM_TIMING50, offset: 0xF8 */
AnnaBridge 171:3a7713b1edbc 10698 __IO uint32_t TIMING51; /**< TSM_TIMING51, offset: 0xFC */
AnnaBridge 171:3a7713b1edbc 10699 __IO uint32_t TIMING52; /**< TSM_TIMING52, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 10700 __IO uint32_t TIMING53; /**< TSM_TIMING53, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 10701 __IO uint32_t TIMING54; /**< TSM_TIMING54, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 10702 __IO uint32_t TIMING55; /**< TSM_TIMING55, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 10703 __IO uint32_t TIMING56; /**< TSM_TIMING56, offset: 0x110 */
AnnaBridge 171:3a7713b1edbc 10704 __IO uint32_t TIMING57; /**< TSM_TIMING57, offset: 0x114 */
AnnaBridge 171:3a7713b1edbc 10705 __IO uint32_t TIMING58; /**< TSM_TIMING58, offset: 0x118 */
AnnaBridge 171:3a7713b1edbc 10706 } XCVR_TSM_Type;
AnnaBridge 171:3a7713b1edbc 10707
AnnaBridge 171:3a7713b1edbc 10708 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10709 -- XCVR_TSM Register Masks
AnnaBridge 171:3a7713b1edbc 10710 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10711
AnnaBridge 171:3a7713b1edbc 10712 /*!
AnnaBridge 171:3a7713b1edbc 10713 * @addtogroup XCVR_TSM_Register_Masks XCVR_TSM Register Masks
AnnaBridge 171:3a7713b1edbc 10714 * @{
AnnaBridge 171:3a7713b1edbc 10715 */
AnnaBridge 171:3a7713b1edbc 10716
AnnaBridge 171:3a7713b1edbc 10717 /*! @name CTRL - TRANSCEIVER SEQUENCE MANAGER CONTROL */
AnnaBridge 171:3a7713b1edbc 10718 #define XCVR_TSM_CTRL_FORCE_TX_EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10719 #define XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10720 #define XCVR_TSM_CTRL_FORCE_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_TX_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10721 #define XCVR_TSM_CTRL_FORCE_RX_EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10722 #define XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10723 #define XCVR_TSM_CTRL_FORCE_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT)) & XCVR_TSM_CTRL_FORCE_RX_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10724 #define XCVR_TSM_CTRL_PA_RAMP_SEL_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 10725 #define XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10726 #define XCVR_TSM_CTRL_PA_RAMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT)) & XCVR_TSM_CTRL_PA_RAMP_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 10727 #define XCVR_TSM_CTRL_DATA_PADDING_EN_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 10728 #define XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10729 #define XCVR_TSM_CTRL_DATA_PADDING_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT)) & XCVR_TSM_CTRL_DATA_PADDING_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10730 #define XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 10731 #define XCVR_TSM_CTRL_TSM_IRQ0_EN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10732 #define XCVR_TSM_CTRL_TSM_IRQ0_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_IRQ0_EN_SHIFT)) & XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10733 #define XCVR_TSM_CTRL_TSM_IRQ1_EN_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 10734 #define XCVR_TSM_CTRL_TSM_IRQ1_EN_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 10735 #define XCVR_TSM_CTRL_TSM_IRQ1_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TSM_IRQ1_EN_SHIFT)) & XCVR_TSM_CTRL_TSM_IRQ1_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10736 #define XCVR_TSM_CTRL_RAMP_DN_DELAY_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 10737 #define XCVR_TSM_CTRL_RAMP_DN_DELAY_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10738 #define XCVR_TSM_CTRL_RAMP_DN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_RAMP_DN_DELAY_SHIFT)) & XCVR_TSM_CTRL_RAMP_DN_DELAY_MASK)
AnnaBridge 171:3a7713b1edbc 10739 #define XCVR_TSM_CTRL_TX_ABORT_DIS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 10740 #define XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10741 #define XCVR_TSM_CTRL_TX_ABORT_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT)) & XCVR_TSM_CTRL_TX_ABORT_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 10742 #define XCVR_TSM_CTRL_RX_ABORT_DIS_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 10743 #define XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 10744 #define XCVR_TSM_CTRL_RX_ABORT_DIS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT)) & XCVR_TSM_CTRL_RX_ABORT_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 10745 #define XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 10746 #define XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 10747 #define XCVR_TSM_CTRL_ABORT_ON_CTUNE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK)
AnnaBridge 171:3a7713b1edbc 10748 #define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 10749 #define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 10750 #define XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK)
AnnaBridge 171:3a7713b1edbc 10751 #define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 10752 #define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10753 #define XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT)) & XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK)
AnnaBridge 171:3a7713b1edbc 10754 #define XCVR_TSM_CTRL_BKPT_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 10755 #define XCVR_TSM_CTRL_BKPT_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10756 #define XCVR_TSM_CTRL_BKPT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_CTRL_BKPT_SHIFT)) & XCVR_TSM_CTRL_BKPT_MASK)
AnnaBridge 171:3a7713b1edbc 10757
AnnaBridge 171:3a7713b1edbc 10758 /*! @name END_OF_SEQ - TSM END OF SEQUENCE */
AnnaBridge 171:3a7713b1edbc 10759 #define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 10760 #define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10761 #define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK)
AnnaBridge 171:3a7713b1edbc 10762 #define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 10763 #define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10764 #define XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_TX_WD_MASK)
AnnaBridge 171:3a7713b1edbc 10765 #define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 10766 #define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10767 #define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK)
AnnaBridge 171:3a7713b1edbc 10768 #define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 10769 #define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10770 #define XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_SHIFT)) & XCVR_TSM_END_OF_SEQ_END_OF_RX_WD_MASK)
AnnaBridge 171:3a7713b1edbc 10771
AnnaBridge 171:3a7713b1edbc 10772 /*! @name OVRD0 - TSM OVERRIDE REGISTER 0 */
AnnaBridge 171:3a7713b1edbc 10773 #define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10774 #define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10775 #define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10776 #define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10777 #define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10778 #define XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_HF_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10779 #define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10780 #define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10781 #define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10782 #define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10783 #define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10784 #define XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_ADCDAC_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10785 #define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10786 #define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10787 #define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10788 #define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10789 #define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10790 #define XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_BBA_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10791 #define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 10792 #define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10793 #define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10794 #define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10795 #define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10796 #define XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_PD_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10797 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 10798 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10799 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10800 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 10801 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 10802 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10803 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 10804 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 10805 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10806 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 10807 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 10808 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10809 #define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 10810 #define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10811 #define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10812 #define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 10813 #define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 10814 #define XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VTREF_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10815 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 10816 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 10817 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10818 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 10819 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 10820 #define XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_FDBK_BLEED_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10821 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 10822 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10823 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10824 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 10825 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 10826 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_BLEED_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10827 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 10828 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 10829 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10830 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 10831 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 10832 #define XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_LDO_VCOLO_FASTCHARGE_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10833 #define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 10834 #define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10835 #define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10836 #define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 10837 #define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 10838 #define XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_PLL_REF_CLK_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10839 #define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 10840 #define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 10841 #define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10842 #define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 10843 #define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 10844 #define XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_DAC_REF_CLK_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10845 #define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10846 #define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10847 #define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10848 #define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10849 #define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10850 #define XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_BB_XTAL_AUXPLL_REF_CLK_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10851 #define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 10852 #define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 10853 #define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10854 #define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 10855 #define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 10856 #define XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_AUTOTUNE_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10857 #define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 10858 #define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10859 #define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10860 #define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 10861 #define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 10862 #define XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_PD_CYCLE_SLIP_LD_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10863 #define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 10864 #define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 10865 #define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10866 #define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 10867 #define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 10868 #define XCVR_TSM_OVRD0_SY_VCO_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD0_SY_VCO_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10869
AnnaBridge 171:3a7713b1edbc 10870 /*! @name OVRD1 - TSM OVERRIDE REGISTER 1 */
AnnaBridge 171:3a7713b1edbc 10871 #define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10872 #define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10873 #define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10874 #define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10875 #define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10876 #define XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_BUF_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10877 #define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10878 #define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10879 #define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10880 #define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10881 #define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10882 #define XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_BUF_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10883 #define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10884 #define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10885 #define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10886 #define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10887 #define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10888 #define XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10889 #define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 10890 #define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10891 #define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10892 #define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10893 #define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10894 #define XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_FILTER_CHARGE_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10895 #define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 10896 #define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10897 #define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10898 #define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 10899 #define XCVR_TSM_OVRD1_SY_PD_EN_OVRD_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 10900 #define XCVR_TSM_OVRD1_SY_PD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_PD_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10901 #define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 10902 #define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 10903 #define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10904 #define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 10905 #define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 10906 #define XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_DIVN_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10907 #define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 10908 #define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10909 #define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10910 #define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 10911 #define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 10912 #define XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_RX_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10913 #define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 10914 #define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 10915 #define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10916 #define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 10917 #define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 10918 #define XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_LO_TX_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10919 #define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 10920 #define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10921 #define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10922 #define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 10923 #define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 10924 #define XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_SY_DIVN_CAL_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10925 #define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 10926 #define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 10927 #define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10928 #define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 10929 #define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 10930 #define XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_MIXER_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10931 #define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 10932 #define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10933 #define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_TX_PA_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10934 #define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 10935 #define XCVR_TSM_OVRD1_TX_PA_EN_OVRD_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 10936 #define XCVR_TSM_OVRD1_TX_PA_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_TX_PA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_TX_PA_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10937 #define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 10938 #define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 10939 #define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10940 #define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 10941 #define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 10942 #define XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_I_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10943 #define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10944 #define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10945 #define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10946 #define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10947 #define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10948 #define XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_Q_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10949 #define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 10950 #define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 10951 #define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10952 #define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 10953 #define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 10954 #define XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_ADC_RESET_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10955 #define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 10956 #define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10957 #define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10958 #define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 10959 #define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 10960 #define XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_I_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10961 #define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 10962 #define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 10963 #define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10964 #define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 10965 #define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 10966 #define XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD1_RX_BBA_Q_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10967
AnnaBridge 171:3a7713b1edbc 10968 /*! @name OVRD2 - TSM OVERRIDE REGISTER 2 */
AnnaBridge 171:3a7713b1edbc 10969 #define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10970 #define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10971 #define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10972 #define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10973 #define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10974 #define XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_PDET_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10975 #define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10976 #define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10977 #define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10978 #define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10979 #define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10980 #define XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_BBA_DCOC_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10981 #define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10982 #define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10983 #define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10984 #define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10985 #define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10986 #define XCVR_TSM_OVRD2_RX_LNA_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_LNA_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10987 #define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 10988 #define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10989 #define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10990 #define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10991 #define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10992 #define XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_I_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10993 #define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 10994 #define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10995 #define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 10996 #define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 10997 #define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 10998 #define XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_Q_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 10999 #define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 11000 #define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 11001 #define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11002 #define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 11003 #define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 11004 #define XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_PDET_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11005 #define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 11006 #define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 11007 #define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11008 #define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 11009 #define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 11010 #define XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_TZA_DCOC_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11011 #define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 11012 #define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 11013 #define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11014 #define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 11015 #define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 11016 #define XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11017 #define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 11018 #define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11019 #define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11020 #define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 11021 #define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 11022 #define XCVR_TSM_OVRD2_TX_DIG_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11023 #define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 11024 #define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 11025 #define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11026 #define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 11027 #define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 11028 #define XCVR_TSM_OVRD2_RX_DIG_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11029 #define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 11030 #define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 11031 #define XCVR_TSM_OVRD2_RX_INIT_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11032 #define XCVR_TSM_OVRD2_RX_INIT_OVRD_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 11033 #define XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 11034 #define XCVR_TSM_OVRD2_RX_INIT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_INIT_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11035 #define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 11036 #define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 11037 #define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11038 #define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 11039 #define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 11040 #define XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11041 #define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 11042 #define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11043 #define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11044 #define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 11045 #define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 11046 #define XCVR_TSM_OVRD2_RX_PHY_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_RX_PHY_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11047 #define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 11048 #define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 11049 #define XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11050 #define XCVR_TSM_OVRD2_DCOC_EN_OVRD_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 11051 #define XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 11052 #define XCVR_TSM_OVRD2_DCOC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_DCOC_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11053 #define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 11054 #define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 11055 #define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11056 #define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 11057 #define XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 11058 #define XCVR_TSM_OVRD2_DCOC_INIT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT)) & XCVR_TSM_OVRD2_DCOC_INIT_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11059 #define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 11060 #define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 11061 #define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11062 #define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 11063 #define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 11064 #define XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11065
AnnaBridge 171:3a7713b1edbc 11066 /*! @name OVRD3 - TSM OVERRIDE REGISTER 3 */
AnnaBridge 171:3a7713b1edbc 11067 #define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11068 #define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11069 #define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11070 #define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11071 #define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11072 #define XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11073 #define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11074 #define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11075 #define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11076 #define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11077 #define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11078 #define XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11079 #define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11080 #define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11081 #define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11082 #define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11083 #define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11084 #define XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11085 #define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11086 #define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11087 #define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11088 #define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11089 #define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11090 #define XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11091 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 11092 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11093 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11094 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 11095 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 11096 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_BIAS_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11097 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 11098 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 11099 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11100 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 11101 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 11102 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_VCO_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11103 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 11104 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 11105 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11106 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 11107 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 11108 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_FCAL_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11109 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 11110 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 11111 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11112 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 11113 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 11114 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_LF_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11115 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 11116 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11117 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11118 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 11119 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 11120 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11121 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 11122 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 11123 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11124 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 11125 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 11126 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11127 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 11128 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 11129 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11130 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 11131 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 11132 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_ADC_BUF_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11133 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 11134 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 11135 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11136 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 11137 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 11138 #define XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_AUXPLL_DIG_BUF_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11139 #define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 11140 #define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11141 #define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11142 #define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 11143 #define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 11144 #define XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RXTX_RCCAL_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11145 #define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 11146 #define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 11147 #define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11148 #define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 11149 #define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 11150 #define XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TX_HPM_DAC_EN_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11151 #define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 11152 #define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 11153 #define XCVR_TSM_OVRD3_TX_MODE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11154 #define XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 11155 #define XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 11156 #define XCVR_TSM_OVRD3_TX_MODE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT)) & XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11157 #define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 11158 #define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 11159 #define XCVR_TSM_OVRD3_RX_MODE_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT)) & XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11160 #define XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 11161 #define XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 11162 #define XCVR_TSM_OVRD3_RX_MODE_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT)) & XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11163
AnnaBridge 171:3a7713b1edbc 11164 /*! @name PA_POWER - PA POWER */
AnnaBridge 171:3a7713b1edbc 11165 #define XCVR_TSM_PA_POWER_PA_POWER_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 11166 #define XCVR_TSM_PA_POWER_PA_POWER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11167 #define XCVR_TSM_PA_POWER_PA_POWER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_POWER_PA_POWER_SHIFT)) & XCVR_TSM_PA_POWER_PA_POWER_MASK)
AnnaBridge 171:3a7713b1edbc 11168
AnnaBridge 171:3a7713b1edbc 11169 /*! @name PA_RAMP_TBL0 - PA RAMP TABLE 0 */
AnnaBridge 171:3a7713b1edbc 11170 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 11171 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11172 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0_MASK)
AnnaBridge 171:3a7713b1edbc 11173 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_MASK (0x3F00U)
AnnaBridge 171:3a7713b1edbc 11174 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11175 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1_MASK)
AnnaBridge 171:3a7713b1edbc 11176 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 11177 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11178 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2_MASK)
AnnaBridge 171:3a7713b1edbc 11179 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_MASK (0x3F000000U)
AnnaBridge 171:3a7713b1edbc 11180 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11181 #define XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_SHIFT)) & XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3_MASK)
AnnaBridge 171:3a7713b1edbc 11182
AnnaBridge 171:3a7713b1edbc 11183 /*! @name PA_RAMP_TBL1 - PA RAMP TABLE 1 */
AnnaBridge 171:3a7713b1edbc 11184 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 11185 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11186 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4_MASK)
AnnaBridge 171:3a7713b1edbc 11187 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_MASK (0x3F00U)
AnnaBridge 171:3a7713b1edbc 11188 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11189 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5_MASK)
AnnaBridge 171:3a7713b1edbc 11190 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 11191 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11192 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6_MASK)
AnnaBridge 171:3a7713b1edbc 11193 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_MASK (0x3F000000U)
AnnaBridge 171:3a7713b1edbc 11194 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11195 #define XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_SHIFT)) & XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7_MASK)
AnnaBridge 171:3a7713b1edbc 11196
AnnaBridge 171:3a7713b1edbc 11197 /*! @name RECYCLE_COUNT - TSM RECYCLE COUNT */
AnnaBridge 171:3a7713b1edbc 11198 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11199 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11200 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT0_MASK)
AnnaBridge 171:3a7713b1edbc 11201 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11202 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11203 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT1_MASK)
AnnaBridge 171:3a7713b1edbc 11204 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11205 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11206 #define XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_SHIFT)) & XCVR_TSM_RECYCLE_COUNT_RECYCLE_COUNT2_MASK)
AnnaBridge 171:3a7713b1edbc 11207
AnnaBridge 171:3a7713b1edbc 11208 /*! @name FAST_CTRL1 - TSM FAST WARMUP CONTROL REGISTER 1 */
AnnaBridge 171:3a7713b1edbc 11209 #define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11210 #define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11211 #define XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_TX_WU_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11212 #define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11213 #define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11214 #define XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX_WU_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11215 #define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11216 #define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11217 #define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX2TX_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11218 #define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11219 #define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11220 #define XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_WU_CLEAR_MASK)
AnnaBridge 171:3a7713b1edbc 11221 #define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11222 #define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11223 #define XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_SHIFT)) & XCVR_TSM_FAST_CTRL1_FAST_RX2TX_START_MASK)
AnnaBridge 171:3a7713b1edbc 11224
AnnaBridge 171:3a7713b1edbc 11225 /*! @name FAST_CTRL2 - TSM FAST WARMUP CONTROL REGISTER 2 */
AnnaBridge 171:3a7713b1edbc 11226 #define XCVR_TSM_FAST_CTRL2_FAST_START_TX_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11227 #define XCVR_TSM_FAST_CTRL2_FAST_START_TX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11228 #define XCVR_TSM_FAST_CTRL2_FAST_START_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_START_TX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_START_TX_MASK)
AnnaBridge 171:3a7713b1edbc 11229 #define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11230 #define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11231 #define XCVR_TSM_FAST_CTRL2_FAST_DEST_TX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_DEST_TX_MASK)
AnnaBridge 171:3a7713b1edbc 11232 #define XCVR_TSM_FAST_CTRL2_FAST_START_RX_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11233 #define XCVR_TSM_FAST_CTRL2_FAST_START_RX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11234 #define XCVR_TSM_FAST_CTRL2_FAST_START_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_START_RX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_START_RX_MASK)
AnnaBridge 171:3a7713b1edbc 11235 #define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11236 #define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11237 #define XCVR_TSM_FAST_CTRL2_FAST_DEST_RX(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_SHIFT)) & XCVR_TSM_FAST_CTRL2_FAST_DEST_RX_MASK)
AnnaBridge 171:3a7713b1edbc 11238
AnnaBridge 171:3a7713b1edbc 11239 /*! @name TIMING00 - TSM_TIMING00 */
AnnaBridge 171:3a7713b1edbc 11240 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11241 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11242 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11243 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11244 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11245 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11246 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11247 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11248 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11249 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11250 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11251 #define XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING00_BB_LDO_HF_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11252
AnnaBridge 171:3a7713b1edbc 11253 /*! @name TIMING01 - TSM_TIMING01 */
AnnaBridge 171:3a7713b1edbc 11254 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11255 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11256 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11257 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11258 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11259 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11260 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11261 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11262 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11263 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11264 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11265 #define XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING01_BB_LDO_ADCDAC_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11266
AnnaBridge 171:3a7713b1edbc 11267 /*! @name TIMING02 - TSM_TIMING02 */
AnnaBridge 171:3a7713b1edbc 11268 #define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11269 #define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11270 #define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11271 #define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11272 #define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11273 #define XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING02_BB_LDO_BBA_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11274
AnnaBridge 171:3a7713b1edbc 11275 /*! @name TIMING03 - TSM_TIMING03 */
AnnaBridge 171:3a7713b1edbc 11276 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11277 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11278 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11279 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11280 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11281 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11282 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11283 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11284 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11285 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11286 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11287 #define XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING03_BB_LDO_PD_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11288
AnnaBridge 171:3a7713b1edbc 11289 /*! @name TIMING04 - TSM_TIMING04 */
AnnaBridge 171:3a7713b1edbc 11290 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11291 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11292 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11293 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11294 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11295 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11296 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11297 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11298 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11299 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11300 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11301 #define XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING04_BB_LDO_FDBK_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11302
AnnaBridge 171:3a7713b1edbc 11303 /*! @name TIMING05 - TSM_TIMING05 */
AnnaBridge 171:3a7713b1edbc 11304 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11305 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11306 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11307 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11308 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11309 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11310 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11311 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11312 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11313 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11314 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11315 #define XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING05_BB_LDO_VCOLO_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11316
AnnaBridge 171:3a7713b1edbc 11317 /*! @name TIMING06 - TSM_TIMING06 */
AnnaBridge 171:3a7713b1edbc 11318 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11319 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11320 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11321 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11322 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11323 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11324 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11325 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11326 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11327 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11328 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11329 #define XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING06_BB_LDO_VTREF_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11330
AnnaBridge 171:3a7713b1edbc 11331 /*! @name TIMING07 - TSM_TIMING07 */
AnnaBridge 171:3a7713b1edbc 11332 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11333 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11334 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11335 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11336 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11337 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11338 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11339 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11340 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11341 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11342 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11343 #define XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING07_BB_LDO_FDBK_BLEED_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11344
AnnaBridge 171:3a7713b1edbc 11345 /*! @name TIMING08 - TSM_TIMING08 */
AnnaBridge 171:3a7713b1edbc 11346 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11347 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11348 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11349 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11350 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11351 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11352 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11353 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11354 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11355 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11356 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11357 #define XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING08_BB_LDO_VCOLO_BLEED_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11358
AnnaBridge 171:3a7713b1edbc 11359 /*! @name TIMING09 - TSM_TIMING09 */
AnnaBridge 171:3a7713b1edbc 11360 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11361 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11362 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11363 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11364 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11365 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11366 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11367 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11368 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11369 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11370 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11371 #define XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING09_BB_LDO_VCOLO_FASTCHARGE_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11372
AnnaBridge 171:3a7713b1edbc 11373 /*! @name TIMING10 - TSM_TIMING10 */
AnnaBridge 171:3a7713b1edbc 11374 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11375 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11376 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11377 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11378 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11379 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11380 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11381 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11382 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11383 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11384 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11385 #define XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING10_BB_XTAL_PLL_REF_CLK_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11386
AnnaBridge 171:3a7713b1edbc 11387 /*! @name TIMING11 - TSM_TIMING11 */
AnnaBridge 171:3a7713b1edbc 11388 #define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11389 #define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11390 #define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11391 #define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11392 #define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11393 #define XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING11_BB_XTAL_DAC_REF_CLK_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11394
AnnaBridge 171:3a7713b1edbc 11395 /*! @name TIMING12 - TSM_TIMING12 */
AnnaBridge 171:3a7713b1edbc 11396 #define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11397 #define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11398 #define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11399 #define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11400 #define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11401 #define XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING12_RXTX_AUXPLL_VCO_REF_CLK_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11402
AnnaBridge 171:3a7713b1edbc 11403 /*! @name TIMING13 - TSM_TIMING13 */
AnnaBridge 171:3a7713b1edbc 11404 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11405 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11406 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11407 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11408 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11409 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11410 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11411 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11412 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11413 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11414 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11415 #define XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING13_SY_VCO_AUTOTUNE_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11416
AnnaBridge 171:3a7713b1edbc 11417 /*! @name TIMING14 - TSM_TIMING14 */
AnnaBridge 171:3a7713b1edbc 11418 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11419 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11420 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11421 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11422 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11423 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11424 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11425 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11426 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11427 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11428 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11429 #define XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING14_SY_PD_CYCLE_SLIP_LD_FT_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11430
AnnaBridge 171:3a7713b1edbc 11431 /*! @name TIMING15 - TSM_TIMING15 */
AnnaBridge 171:3a7713b1edbc 11432 #define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11433 #define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11434 #define XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11435 #define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11436 #define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11437 #define XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11438 #define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11439 #define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11440 #define XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11441 #define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11442 #define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11443 #define XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING15_SY_VCO_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11444
AnnaBridge 171:3a7713b1edbc 11445 /*! @name TIMING16 - TSM_TIMING16 */
AnnaBridge 171:3a7713b1edbc 11446 #define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11447 #define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11448 #define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11449 #define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11450 #define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11451 #define XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING16_SY_LO_RX_BUF_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11452
AnnaBridge 171:3a7713b1edbc 11453 /*! @name TIMING17 - TSM_TIMING17 */
AnnaBridge 171:3a7713b1edbc 11454 #define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11455 #define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11456 #define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11457 #define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11458 #define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11459 #define XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING17_SY_LO_TX_BUF_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11460
AnnaBridge 171:3a7713b1edbc 11461 /*! @name TIMING18 - TSM_TIMING18 */
AnnaBridge 171:3a7713b1edbc 11462 #define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11463 #define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11464 #define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11465 #define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11466 #define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11467 #define XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11468 #define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11469 #define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11470 #define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11471 #define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11472 #define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11473 #define XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING18_SY_DIVN_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11474
AnnaBridge 171:3a7713b1edbc 11475 /*! @name TIMING19 - TSM_TIMING19 */
AnnaBridge 171:3a7713b1edbc 11476 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11477 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11478 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11479 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11480 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11481 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11482 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11483 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11484 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11485 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11486 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11487 #define XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING19_SY_PD_FILTER_CHARGE_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11488
AnnaBridge 171:3a7713b1edbc 11489 /*! @name TIMING20 - TSM_TIMING20 */
AnnaBridge 171:3a7713b1edbc 11490 #define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11491 #define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11492 #define XCVR_TSM_TIMING20_SY_PD_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11493 #define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11494 #define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11495 #define XCVR_TSM_TIMING20_SY_PD_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11496 #define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11497 #define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11498 #define XCVR_TSM_TIMING20_SY_PD_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11499 #define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11500 #define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11501 #define XCVR_TSM_TIMING20_SY_PD_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING20_SY_PD_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11502
AnnaBridge 171:3a7713b1edbc 11503 /*! @name TIMING21 - TSM_TIMING21 */
AnnaBridge 171:3a7713b1edbc 11504 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11505 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11506 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11507 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11508 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11509 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11510 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11511 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11512 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11513 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11514 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11515 #define XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING21_SY_LO_DIVN_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11516
AnnaBridge 171:3a7713b1edbc 11517 /*! @name TIMING22 - TSM_TIMING22 */
AnnaBridge 171:3a7713b1edbc 11518 #define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11519 #define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11520 #define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11521 #define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11522 #define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11523 #define XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING22_SY_LO_RX_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11524
AnnaBridge 171:3a7713b1edbc 11525 /*! @name TIMING23 - TSM_TIMING23 */
AnnaBridge 171:3a7713b1edbc 11526 #define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11527 #define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11528 #define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11529 #define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11530 #define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11531 #define XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING23_SY_LO_TX_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11532
AnnaBridge 171:3a7713b1edbc 11533 /*! @name TIMING24 - TSM_TIMING24 */
AnnaBridge 171:3a7713b1edbc 11534 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11535 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11536 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11537 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11538 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11539 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11540 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11541 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11542 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11543 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11544 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11545 #define XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING24_SY_DIVN_CAL_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11546
AnnaBridge 171:3a7713b1edbc 11547 /*! @name TIMING25 - TSM_TIMING25 */
AnnaBridge 171:3a7713b1edbc 11548 #define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11549 #define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11550 #define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11551 #define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11552 #define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11553 #define XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING25_RX_LNA_MIXER_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11554
AnnaBridge 171:3a7713b1edbc 11555 /*! @name TIMING26 - TSM_TIMING26 */
AnnaBridge 171:3a7713b1edbc 11556 #define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11557 #define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11558 #define XCVR_TSM_TIMING26_TX_PA_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING26_TX_PA_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11559 #define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11560 #define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11561 #define XCVR_TSM_TIMING26_TX_PA_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING26_TX_PA_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11562
AnnaBridge 171:3a7713b1edbc 11563 /*! @name TIMING27 - TSM_TIMING27 */
AnnaBridge 171:3a7713b1edbc 11564 #define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11565 #define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11566 #define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11567 #define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11568 #define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11569 #define XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING27_RX_ADC_I_Q_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11570
AnnaBridge 171:3a7713b1edbc 11571 /*! @name TIMING28 - TSM_TIMING28 */
AnnaBridge 171:3a7713b1edbc 11572 #define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11573 #define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11574 #define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11575 #define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11576 #define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11577 #define XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING28_RX_ADC_RESET_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11578
AnnaBridge 171:3a7713b1edbc 11579 /*! @name TIMING29 - TSM_TIMING29 */
AnnaBridge 171:3a7713b1edbc 11580 #define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11581 #define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11582 #define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11583 #define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11584 #define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11585 #define XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING29_RX_BBA_I_Q_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11586
AnnaBridge 171:3a7713b1edbc 11587 /*! @name TIMING30 - TSM_TIMING30 */
AnnaBridge 171:3a7713b1edbc 11588 #define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11589 #define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11590 #define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11591 #define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11592 #define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11593 #define XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING30_RX_BBA_PDET_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11594
AnnaBridge 171:3a7713b1edbc 11595 /*! @name TIMING31 - TSM_TIMING31 */
AnnaBridge 171:3a7713b1edbc 11596 #define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11597 #define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11598 #define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11599 #define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11600 #define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11601 #define XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING31_RX_BBA_TZA_DCOC_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11602
AnnaBridge 171:3a7713b1edbc 11603 /*! @name TIMING32 - TSM_TIMING32 */
AnnaBridge 171:3a7713b1edbc 11604 #define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11605 #define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11606 #define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11607 #define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11608 #define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11609 #define XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING32_RX_TZA_I_Q_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11610
AnnaBridge 171:3a7713b1edbc 11611 /*! @name TIMING33 - TSM_TIMING33 */
AnnaBridge 171:3a7713b1edbc 11612 #define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11613 #define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11614 #define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11615 #define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11616 #define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11617 #define XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING33_RX_TZA_PDET_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11618
AnnaBridge 171:3a7713b1edbc 11619 /*! @name TIMING34 - TSM_TIMING34 */
AnnaBridge 171:3a7713b1edbc 11620 #define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11621 #define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11622 #define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11623 #define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11624 #define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11625 #define XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11626 #define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11627 #define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11628 #define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11629 #define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11630 #define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11631 #define XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING34_PLL_DIG_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11632
AnnaBridge 171:3a7713b1edbc 11633 /*! @name TIMING35 - TSM_TIMING35 */
AnnaBridge 171:3a7713b1edbc 11634 #define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11635 #define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11636 #define XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING35_TX_DIG_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11637 #define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11638 #define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11639 #define XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING35_TX_DIG_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11640
AnnaBridge 171:3a7713b1edbc 11641 /*! @name TIMING36 - TSM_TIMING36 */
AnnaBridge 171:3a7713b1edbc 11642 #define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11643 #define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11644 #define XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING36_RX_DIG_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11645 #define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11646 #define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11647 #define XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING36_RX_DIG_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11648
AnnaBridge 171:3a7713b1edbc 11649 /*! @name TIMING37 - TSM_TIMING37 */
AnnaBridge 171:3a7713b1edbc 11650 #define XCVR_TSM_TIMING37_RX_INIT_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11651 #define XCVR_TSM_TIMING37_RX_INIT_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11652 #define XCVR_TSM_TIMING37_RX_INIT_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_RX_INIT_RX_HI_SHIFT)) & XCVR_TSM_TIMING37_RX_INIT_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11653 #define XCVR_TSM_TIMING37_RX_INIT_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11654 #define XCVR_TSM_TIMING37_RX_INIT_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11655 #define XCVR_TSM_TIMING37_RX_INIT_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING37_RX_INIT_RX_LO_SHIFT)) & XCVR_TSM_TIMING37_RX_INIT_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11656
AnnaBridge 171:3a7713b1edbc 11657 /*! @name TIMING38 - TSM_TIMING38 */
AnnaBridge 171:3a7713b1edbc 11658 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11659 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11660 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11661 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11662 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11663 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11664 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11665 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11666 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11667 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11668 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11669 #define XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING38_SIGMA_DELTA_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11670
AnnaBridge 171:3a7713b1edbc 11671 /*! @name TIMING39 - TSM_TIMING39 */
AnnaBridge 171:3a7713b1edbc 11672 #define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11673 #define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11674 #define XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING39_RX_PHY_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11675 #define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11676 #define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11677 #define XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING39_RX_PHY_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11678
AnnaBridge 171:3a7713b1edbc 11679 /*! @name TIMING40 - TSM_TIMING40 */
AnnaBridge 171:3a7713b1edbc 11680 #define XCVR_TSM_TIMING40_DCOC_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11681 #define XCVR_TSM_TIMING40_DCOC_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11682 #define XCVR_TSM_TIMING40_DCOC_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_DCOC_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING40_DCOC_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11683 #define XCVR_TSM_TIMING40_DCOC_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11684 #define XCVR_TSM_TIMING40_DCOC_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11685 #define XCVR_TSM_TIMING40_DCOC_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING40_DCOC_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING40_DCOC_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11686
AnnaBridge 171:3a7713b1edbc 11687 /*! @name TIMING41 - TSM_TIMING41 */
AnnaBridge 171:3a7713b1edbc 11688 #define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11689 #define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11690 #define XCVR_TSM_TIMING41_DCOC_INIT_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_SHIFT)) & XCVR_TSM_TIMING41_DCOC_INIT_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11691 #define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11692 #define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11693 #define XCVR_TSM_TIMING41_DCOC_INIT_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_SHIFT)) & XCVR_TSM_TIMING41_DCOC_INIT_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11694
AnnaBridge 171:3a7713b1edbc 11695 /*! @name TIMING42 - TSM_TIMING42 */
AnnaBridge 171:3a7713b1edbc 11696 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11697 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11698 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11699 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11700 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11701 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11702 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11703 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11704 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11705 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11706 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11707 #define XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING42_SAR_ADC_TRIG_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11708
AnnaBridge 171:3a7713b1edbc 11709 /*! @name TIMING43 - TSM_TIMING43 */
AnnaBridge 171:3a7713b1edbc 11710 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11711 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11712 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11713 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11714 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11715 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11716 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11717 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11718 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11719 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11720 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11721 #define XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11722
AnnaBridge 171:3a7713b1edbc 11723 /*! @name TIMING44 - TSM_TIMING44 */
AnnaBridge 171:3a7713b1edbc 11724 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11725 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11726 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11727 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11728 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11729 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11730 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11731 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11732 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11733 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11734 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11735 #define XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING44_TSM_SPARE1_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11736
AnnaBridge 171:3a7713b1edbc 11737 /*! @name TIMING45 - TSM_TIMING45 */
AnnaBridge 171:3a7713b1edbc 11738 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11739 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11740 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11741 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11742 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11743 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11744 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11745 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11746 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11747 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11748 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11749 #define XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING45_TSM_SPARE2_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11750
AnnaBridge 171:3a7713b1edbc 11751 /*! @name TIMING46 - TSM_TIMING46 */
AnnaBridge 171:3a7713b1edbc 11752 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11753 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11754 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11755 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11756 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11757 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11758 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11759 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11760 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11761 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11762 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11763 #define XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING46_TSM_SPARE3_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11764
AnnaBridge 171:3a7713b1edbc 11765 /*! @name TIMING47 - TSM_TIMING47 */
AnnaBridge 171:3a7713b1edbc 11766 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11767 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11768 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11769 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11770 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11771 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11772 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11773 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11774 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11775 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11776 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11777 #define XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11778
AnnaBridge 171:3a7713b1edbc 11779 /*! @name TIMING48 - TSM_TIMING48 */
AnnaBridge 171:3a7713b1edbc 11780 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11781 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11782 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11783 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11784 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11785 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11786 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11787 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11788 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11789 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11790 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11791 #define XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11792
AnnaBridge 171:3a7713b1edbc 11793 /*! @name TIMING49 - TSM_TIMING49 */
AnnaBridge 171:3a7713b1edbc 11794 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11795 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11796 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11797 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11798 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11799 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11800 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11801 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11802 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11803 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11804 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11805 #define XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING49_GPIO2_TRIG_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11806
AnnaBridge 171:3a7713b1edbc 11807 /*! @name TIMING50 - TSM_TIMING50 */
AnnaBridge 171:3a7713b1edbc 11808 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11809 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11810 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11811 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11812 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11813 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11814 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11815 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11816 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11817 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11818 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11819 #define XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11820
AnnaBridge 171:3a7713b1edbc 11821 /*! @name TIMING51 - TSM_TIMING51 */
AnnaBridge 171:3a7713b1edbc 11822 #define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11823 #define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11824 #define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11825 #define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11826 #define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11827 #define XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING51_RXTX_AUXPLL_BIAS_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11828
AnnaBridge 171:3a7713b1edbc 11829 /*! @name TIMING52 - TSM_TIMING52 */
AnnaBridge 171:3a7713b1edbc 11830 #define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11831 #define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11832 #define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11833 #define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11834 #define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11835 #define XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING52_RXTX_AUXPLL_FCAL_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11836
AnnaBridge 171:3a7713b1edbc 11837 /*! @name TIMING53 - TSM_TIMING53 */
AnnaBridge 171:3a7713b1edbc 11838 #define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11839 #define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11840 #define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11841 #define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11842 #define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11843 #define XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING53_RXTX_AUXPLL_LF_PD_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11844
AnnaBridge 171:3a7713b1edbc 11845 /*! @name TIMING54 - TSM_TIMING54 */
AnnaBridge 171:3a7713b1edbc 11846 #define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11847 #define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11848 #define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11849 #define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11850 #define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11851 #define XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING54_RXTX_AUXPLL_PD_LF_FILTER_CHARGE_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11852
AnnaBridge 171:3a7713b1edbc 11853 /*! @name TIMING55 - TSM_TIMING55 */
AnnaBridge 171:3a7713b1edbc 11854 #define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11855 #define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11856 #define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11857 #define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11858 #define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11859 #define XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING55_RXTX_AUXPLL_ADC_BUF_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11860
AnnaBridge 171:3a7713b1edbc 11861 /*! @name TIMING56 - TSM_TIMING56 */
AnnaBridge 171:3a7713b1edbc 11862 #define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11863 #define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11864 #define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11865 #define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11866 #define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11867 #define XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING56_RXTX_AUXPLL_DIG_BUF_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11868
AnnaBridge 171:3a7713b1edbc 11869 /*! @name TIMING57 - TSM_TIMING57 */
AnnaBridge 171:3a7713b1edbc 11870 #define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11871 #define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11872 #define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_SHIFT)) & XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11873 #define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11874 #define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11875 #define XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_SHIFT)) & XCVR_TSM_TIMING57_RXTX_RCCAL_EN_RX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11876
AnnaBridge 171:3a7713b1edbc 11877 /*! @name TIMING58 - TSM_TIMING58 */
AnnaBridge 171:3a7713b1edbc 11878 #define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11879 #define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11880 #define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_SHIFT)) & XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_HI_MASK)
AnnaBridge 171:3a7713b1edbc 11881 #define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11882 #define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11883 #define XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_SHIFT)) & XCVR_TSM_TIMING58_TX_HPM_DAC_EN_TX_LO_MASK)
AnnaBridge 171:3a7713b1edbc 11884
AnnaBridge 171:3a7713b1edbc 11885
AnnaBridge 171:3a7713b1edbc 11886 /*!
AnnaBridge 171:3a7713b1edbc 11887 * @}
AnnaBridge 171:3a7713b1edbc 11888 */ /* end of group XCVR_TSM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 11889
AnnaBridge 171:3a7713b1edbc 11890
AnnaBridge 171:3a7713b1edbc 11891 /* XCVR_TSM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 11892 /** Peripheral XCVR_TSM base address */
AnnaBridge 171:3a7713b1edbc 11893 #define XCVR_TSM_BASE (0x4005C2C0u)
AnnaBridge 171:3a7713b1edbc 11894 /** Peripheral XCVR_TSM base pointer */
AnnaBridge 171:3a7713b1edbc 11895 #define XCVR_TSM ((XCVR_TSM_Type *)XCVR_TSM_BASE)
AnnaBridge 171:3a7713b1edbc 11896 /** Array initializer of XCVR_TSM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 11897 #define XCVR_TSM_BASE_ADDRS { XCVR_TSM_BASE }
AnnaBridge 171:3a7713b1edbc 11898 /** Array initializer of XCVR_TSM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 11899 #define XCVR_TSM_BASE_PTRS { XCVR_TSM }
AnnaBridge 171:3a7713b1edbc 11900
AnnaBridge 171:3a7713b1edbc 11901 /*!
AnnaBridge 171:3a7713b1edbc 11902 * @}
AnnaBridge 171:3a7713b1edbc 11903 */ /* end of group XCVR_TSM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 11904
AnnaBridge 171:3a7713b1edbc 11905
AnnaBridge 171:3a7713b1edbc 11906 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11907 -- XCVR_TX_DIG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11908 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11909
AnnaBridge 171:3a7713b1edbc 11910 /*!
AnnaBridge 171:3a7713b1edbc 11911 * @addtogroup XCVR_TX_DIG_Peripheral_Access_Layer XCVR_TX_DIG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11912 * @{
AnnaBridge 171:3a7713b1edbc 11913 */
AnnaBridge 171:3a7713b1edbc 11914
AnnaBridge 171:3a7713b1edbc 11915 /** XCVR_TX_DIG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 11916 typedef struct {
AnnaBridge 171:3a7713b1edbc 11917 __IO uint32_t CTRL; /**< TX Digital Control, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 11918 __IO uint32_t DATA_PADDING; /**< TX Data Padding, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 11919 __IO uint32_t GFSK_CTRL; /**< TX GFSK Modulator Control, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 11920 __IO uint32_t GFSK_COEFF2; /**< TX GFSK Filter Coefficients 2, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 11921 __IO uint32_t GFSK_COEFF1; /**< TX GFSK Filter Coefficients 1, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 11922 __IO uint32_t FSK_SCALE; /**< TX FSK Modulation Levels, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 11923 __IO uint32_t DFT_PATTERN; /**< TX DFT Modulation Pattern, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 11924 __IO uint32_t RF_DFT_BIST_1; /**< TX DFT Control 1, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 11925 __IO uint32_t RF_DFT_BIST_2; /**< TX DFT Control 2, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 11926 } XCVR_TX_DIG_Type;
AnnaBridge 171:3a7713b1edbc 11927
AnnaBridge 171:3a7713b1edbc 11928 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11929 -- XCVR_TX_DIG Register Masks
AnnaBridge 171:3a7713b1edbc 11930 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11931
AnnaBridge 171:3a7713b1edbc 11932 /*!
AnnaBridge 171:3a7713b1edbc 11933 * @addtogroup XCVR_TX_DIG_Register_Masks XCVR_TX_DIG Register Masks
AnnaBridge 171:3a7713b1edbc 11934 * @{
AnnaBridge 171:3a7713b1edbc 11935 */
AnnaBridge 171:3a7713b1edbc 11936
AnnaBridge 171:3a7713b1edbc 11937 /*! @name CTRL - TX Digital Control */
AnnaBridge 171:3a7713b1edbc 11938 #define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 11939 #define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11940 #define XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_SHIFT)) & XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 11941 #define XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 11942 #define XCVR_TX_DIG_CTRL_LFSR_LENGTH_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11943 #define XCVR_TX_DIG_CTRL_LFSR_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_LFSR_LENGTH_SHIFT)) & XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK)
AnnaBridge 171:3a7713b1edbc 11944 #define XCVR_TX_DIG_CTRL_LFSR_EN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11945 #define XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11946 #define XCVR_TX_DIG_CTRL_LFSR_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT)) & XCVR_TX_DIG_CTRL_LFSR_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11947 #define XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 11948 #define XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11949 #define XCVR_TX_DIG_CTRL_DFT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT)) & XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 11950 #define XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 11951 #define XCVR_TX_DIG_CTRL_TX_DFT_EN_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 11952 #define XCVR_TX_DIG_CTRL_TX_DFT_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_TX_DFT_EN_SHIFT)) & XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11953 #define XCVR_TX_DIG_CTRL_SOC_TEST_SEL_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 11954 #define XCVR_TX_DIG_CTRL_SOC_TEST_SEL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 11955 #define XCVR_TX_DIG_CTRL_SOC_TEST_SEL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_SOC_TEST_SEL_SHIFT)) & XCVR_TX_DIG_CTRL_SOC_TEST_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 11956 #define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 11957 #define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11958 #define XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_SHIFT)) & XCVR_TX_DIG_CTRL_TX_CAPTURE_POL_MASK)
AnnaBridge 171:3a7713b1edbc 11959 #define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_MASK (0xFFC00000U)
AnnaBridge 171:3a7713b1edbc 11960 #define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 11961 #define XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT)) & XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 11962
AnnaBridge 171:3a7713b1edbc 11963 /*! @name DATA_PADDING - TX Data Padding */
AnnaBridge 171:3a7713b1edbc 11964 #define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11965 #define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11966 #define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0_MASK)
AnnaBridge 171:3a7713b1edbc 11967 #define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11968 #define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11969 #define XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1_MASK)
AnnaBridge 171:3a7713b1edbc 11970 #define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_MASK (0x7FFF0000U)
AnnaBridge 171:3a7713b1edbc 11971 #define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11972 #define XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_DFT_LFSR_OUT_MASK)
AnnaBridge 171:3a7713b1edbc 11973 #define XCVR_TX_DIG_DATA_PADDING_LRM_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 11974 #define XCVR_TX_DIG_DATA_PADDING_LRM_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 11975 #define XCVR_TX_DIG_DATA_PADDING_LRM(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DATA_PADDING_LRM_SHIFT)) & XCVR_TX_DIG_DATA_PADDING_LRM_MASK)
AnnaBridge 171:3a7713b1edbc 11976
AnnaBridge 171:3a7713b1edbc 11977 /*! @name GFSK_CTRL - TX GFSK Modulator Control */
AnnaBridge 171:3a7713b1edbc 11978 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 11979 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11980 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_MASK)
AnnaBridge 171:3a7713b1edbc 11981 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 11982 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11983 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MI_MASK)
AnnaBridge 171:3a7713b1edbc 11984 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 11985 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 11986 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD_MASK)
AnnaBridge 171:3a7713b1edbc 11987 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 11988 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 11989 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD_MASK)
AnnaBridge 171:3a7713b1edbc 11990 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_MASK (0x7000000U)
AnnaBridge 171:3a7713b1edbc 11991 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11992 #define XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING_MASK)
AnnaBridge 171:3a7713b1edbc 11993 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 11994 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 11995 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 11996 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 11997 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 11998 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 11999 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 12000 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 12001 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 12002 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12003 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12004 #define XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_SHIFT)) & XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD_MASK)
AnnaBridge 171:3a7713b1edbc 12005
AnnaBridge 171:3a7713b1edbc 12006 /*! @name GFSK_COEFF2 - TX GFSK Filter Coefficients 2 */
AnnaBridge 171:3a7713b1edbc 12007 #define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12008 #define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12009 #define XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF2_GFSK_FILTER_COEFF_MANUAL2_MASK)
AnnaBridge 171:3a7713b1edbc 12010
AnnaBridge 171:3a7713b1edbc 12011 /*! @name GFSK_COEFF1 - TX GFSK Filter Coefficients 1 */
AnnaBridge 171:3a7713b1edbc 12012 #define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12013 #define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12014 #define XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_SHIFT)) & XCVR_TX_DIG_GFSK_COEFF1_GFSK_FILTER_COEFF_MANUAL1_MASK)
AnnaBridge 171:3a7713b1edbc 12015
AnnaBridge 171:3a7713b1edbc 12016 /*! @name FSK_SCALE - TX FSK Modulation Levels */
AnnaBridge 171:3a7713b1edbc 12017 #define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 12018 #define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12019 #define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_SHIFT)) & XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0_MASK)
AnnaBridge 171:3a7713b1edbc 12020 #define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_MASK (0x1FFF0000U)
AnnaBridge 171:3a7713b1edbc 12021 #define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12022 #define XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_SHIFT)) & XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1_MASK)
AnnaBridge 171:3a7713b1edbc 12023
AnnaBridge 171:3a7713b1edbc 12024 /*! @name DFT_PATTERN - TX DFT Modulation Pattern */
AnnaBridge 171:3a7713b1edbc 12025 #define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12026 #define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12027 #define XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_SHIFT)) & XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN_MASK)
AnnaBridge 171:3a7713b1edbc 12028
AnnaBridge 171:3a7713b1edbc 12029 /*! @name RF_DFT_BIST_1 - TX DFT Control 1 */
AnnaBridge 171:3a7713b1edbc 12030 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12031 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12032 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO_MASK)
AnnaBridge 171:3a7713b1edbc 12033 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12034 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12035 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_FINISHED_MASK)
AnnaBridge 171:3a7713b1edbc 12036 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12037 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12038 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_RESULT_MASK)
AnnaBridge 171:3a7713b1edbc 12039 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 12040 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12041 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD_MASK)
AnnaBridge 171:3a7713b1edbc 12042 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 12043 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12044 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_MASK)
AnnaBridge 171:3a7713b1edbc 12045 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 12046 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12047 #define XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_MAX_DIFF_CH_MASK)
AnnaBridge 171:3a7713b1edbc 12048 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ_MASK (0x7000000U)
AnnaBridge 171:3a7713b1edbc 12049 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12050 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ_MASK)
AnnaBridge 171:3a7713b1edbc 12051 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES_MASK (0x70000000U)
AnnaBridge 171:3a7713b1edbc 12052 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 12053 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES_MASK)
AnnaBridge 171:3a7713b1edbc 12054 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12055 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12056 #define XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12057
AnnaBridge 171:3a7713b1edbc 12058 /*! @name RF_DFT_BIST_2 - TX DFT Control 2 */
AnnaBridge 171:3a7713b1edbc 12059 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12060 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12061 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO_MASK)
AnnaBridge 171:3a7713b1edbc 12062 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12063 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12064 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_FINISHED_MASK)
AnnaBridge 171:3a7713b1edbc 12065 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12066 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12067 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_RESULT_MASK)
AnnaBridge 171:3a7713b1edbc 12068 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12069 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12070 #define XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS_MASK)
AnnaBridge 171:3a7713b1edbc 12071 #define XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD_MASK (0xFF0U)
AnnaBridge 171:3a7713b1edbc 12072 #define XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12073 #define XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD_MASK)
AnnaBridge 171:3a7713b1edbc 12074 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12075 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12076 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO_MASK)
AnnaBridge 171:3a7713b1edbc 12077 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 12078 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 12079 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_FINISHED_MASK)
AnnaBridge 171:3a7713b1edbc 12080 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 12081 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 12082 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_RESULT_MASK)
AnnaBridge 171:3a7713b1edbc 12083 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 12084 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12085 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO_MASK)
AnnaBridge 171:3a7713b1edbc 12086 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 12087 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 12088 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_FINISHED_MASK)
AnnaBridge 171:3a7713b1edbc 12089 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 12090 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12091 #define XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_RESULT_MASK)
AnnaBridge 171:3a7713b1edbc 12092 #define XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE_MASK (0x1FF00000U)
AnnaBridge 171:3a7713b1edbc 12093 #define XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12094 #define XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE_SHIFT)) & XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE_MASK)
AnnaBridge 171:3a7713b1edbc 12095
AnnaBridge 171:3a7713b1edbc 12096
AnnaBridge 171:3a7713b1edbc 12097 /*!
AnnaBridge 171:3a7713b1edbc 12098 * @}
AnnaBridge 171:3a7713b1edbc 12099 */ /* end of group XCVR_TX_DIG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 12100
AnnaBridge 171:3a7713b1edbc 12101
AnnaBridge 171:3a7713b1edbc 12102 /* XCVR_TX_DIG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 12103 /** Peripheral XCVR_TX_DIG base address */
AnnaBridge 171:3a7713b1edbc 12104 #define XCVR_TX_DIG_BASE (0x4005C200u)
AnnaBridge 171:3a7713b1edbc 12105 /** Peripheral XCVR_TX_DIG base pointer */
AnnaBridge 171:3a7713b1edbc 12106 #define XCVR_TX_DIG ((XCVR_TX_DIG_Type *)XCVR_TX_DIG_BASE)
AnnaBridge 171:3a7713b1edbc 12107 /** Array initializer of XCVR_TX_DIG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 12108 #define XCVR_TX_DIG_BASE_ADDRS { XCVR_TX_DIG_BASE }
AnnaBridge 171:3a7713b1edbc 12109 /** Array initializer of XCVR_TX_DIG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 12110 #define XCVR_TX_DIG_BASE_PTRS { XCVR_TX_DIG }
AnnaBridge 171:3a7713b1edbc 12111
AnnaBridge 171:3a7713b1edbc 12112 /*!
AnnaBridge 171:3a7713b1edbc 12113 * @}
AnnaBridge 171:3a7713b1edbc 12114 */ /* end of group XCVR_TX_DIG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 12115
AnnaBridge 171:3a7713b1edbc 12116
AnnaBridge 171:3a7713b1edbc 12117 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12118 -- XCVR_ZBDEM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12119 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12120
AnnaBridge 171:3a7713b1edbc 12121 /*!
AnnaBridge 171:3a7713b1edbc 12122 * @addtogroup XCVR_ZBDEM_Peripheral_Access_Layer XCVR_ZBDEM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12123 * @{
AnnaBridge 171:3a7713b1edbc 12124 */
AnnaBridge 171:3a7713b1edbc 12125
AnnaBridge 171:3a7713b1edbc 12126 /** XCVR_ZBDEM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 12127 typedef struct {
AnnaBridge 171:3a7713b1edbc 12128 __IO uint32_t CORR_CTRL; /**< 802.15.4 DEMOD CORRELLATOR CONTROL, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 12129 __IO uint32_t PN_TYPE; /**< 802.15.4 DEMOD PN TYPE, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 12130 __IO uint32_t PN_CODE; /**< 802.15.4 DEMOD PN CODE, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 12131 __IO uint32_t SYNC_CTRL; /**< 802.15.4 DEMOD SYMBOL SYNC CONTROL, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 12132 __IO uint32_t CCA_LQI_SRC; /**< 802.15.4 CCA/LQI SOURCE, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 12133 __IO uint32_t FAD_THR; /**< FAD CORRELATOR THRESHOLD, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 12134 __IO uint32_t ZBDEM_AFC; /**< 802.15.4 AFC STATUS, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 12135 } XCVR_ZBDEM_Type;
AnnaBridge 171:3a7713b1edbc 12136
AnnaBridge 171:3a7713b1edbc 12137 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12138 -- XCVR_ZBDEM Register Masks
AnnaBridge 171:3a7713b1edbc 12139 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12140
AnnaBridge 171:3a7713b1edbc 12141 /*!
AnnaBridge 171:3a7713b1edbc 12142 * @addtogroup XCVR_ZBDEM_Register_Masks XCVR_ZBDEM Register Masks
AnnaBridge 171:3a7713b1edbc 12143 * @{
AnnaBridge 171:3a7713b1edbc 12144 */
AnnaBridge 171:3a7713b1edbc 12145
AnnaBridge 171:3a7713b1edbc 12146 /*! @name CORR_CTRL - 802.15.4 DEMOD CORRELLATOR CONTROL */
AnnaBridge 171:3a7713b1edbc 12147 #define XCVR_ZBDEM_CORR_CTRL_CORR_VT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12148 #define XCVR_ZBDEM_CORR_CTRL_CORR_VT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12149 #define XCVR_ZBDEM_CORR_CTRL_CORR_VT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_CORR_VT_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_CORR_VT_MASK)
AnnaBridge 171:3a7713b1edbc 12150 #define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 12151 #define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12152 #define XCVR_ZBDEM_CORR_CTRL_CORR_NVAL(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_CORR_NVAL_MASK)
AnnaBridge 171:3a7713b1edbc 12153 #define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 12154 #define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 12155 #define XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_MAX_CORR_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12156 #define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 12157 #define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 12158 #define XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_ZBDEM_CLK_ON_MASK)
AnnaBridge 171:3a7713b1edbc 12159 #define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 12160 #define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12161 #define XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_RX_MAX_CORR_MASK)
AnnaBridge 171:3a7713b1edbc 12162 #define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 12163 #define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12164 #define XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_SHIFT)) & XCVR_ZBDEM_CORR_CTRL_RX_MAX_PREAMBLE_MASK)
AnnaBridge 171:3a7713b1edbc 12165
AnnaBridge 171:3a7713b1edbc 12166 /*! @name PN_TYPE - 802.15.4 DEMOD PN TYPE */
AnnaBridge 171:3a7713b1edbc 12167 #define XCVR_ZBDEM_PN_TYPE_PN_TYPE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12168 #define XCVR_ZBDEM_PN_TYPE_PN_TYPE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12169 #define XCVR_ZBDEM_PN_TYPE_PN_TYPE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_TYPE_PN_TYPE_SHIFT)) & XCVR_ZBDEM_PN_TYPE_PN_TYPE_MASK)
AnnaBridge 171:3a7713b1edbc 12170 #define XCVR_ZBDEM_PN_TYPE_TX_INV_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12171 #define XCVR_ZBDEM_PN_TYPE_TX_INV_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12172 #define XCVR_ZBDEM_PN_TYPE_TX_INV(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_TYPE_TX_INV_SHIFT)) & XCVR_ZBDEM_PN_TYPE_TX_INV_MASK)
AnnaBridge 171:3a7713b1edbc 12173
AnnaBridge 171:3a7713b1edbc 12174 /*! @name PN_CODE - 802.15.4 DEMOD PN CODE */
AnnaBridge 171:3a7713b1edbc 12175 #define XCVR_ZBDEM_PN_CODE_PN_LSB_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12176 #define XCVR_ZBDEM_PN_CODE_PN_LSB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12177 #define XCVR_ZBDEM_PN_CODE_PN_LSB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_CODE_PN_LSB_SHIFT)) & XCVR_ZBDEM_PN_CODE_PN_LSB_MASK)
AnnaBridge 171:3a7713b1edbc 12178 #define XCVR_ZBDEM_PN_CODE_PN_MSB_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 12179 #define XCVR_ZBDEM_PN_CODE_PN_MSB_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12180 #define XCVR_ZBDEM_PN_CODE_PN_MSB(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_PN_CODE_PN_MSB_SHIFT)) & XCVR_ZBDEM_PN_CODE_PN_MSB_MASK)
AnnaBridge 171:3a7713b1edbc 12181
AnnaBridge 171:3a7713b1edbc 12182 /*! @name SYNC_CTRL - 802.15.4 DEMOD SYMBOL SYNC CONTROL */
AnnaBridge 171:3a7713b1edbc 12183 #define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 12184 #define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12185 #define XCVR_ZBDEM_SYNC_CTRL_SYNC_PER(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_SHIFT)) & XCVR_ZBDEM_SYNC_CTRL_SYNC_PER_MASK)
AnnaBridge 171:3a7713b1edbc 12186 #define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12187 #define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12188 #define XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_SHIFT)) & XCVR_ZBDEM_SYNC_CTRL_TRACK_ENABLE_MASK)
AnnaBridge 171:3a7713b1edbc 12189
AnnaBridge 171:3a7713b1edbc 12190 /*! @name CCA_LQI_SRC - 802.15.4 CCA/LQI SOURCE */
AnnaBridge 171:3a7713b1edbc 12191 #define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12192 #define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12193 #define XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_CCA1_FROM_RX_DIG_MASK)
AnnaBridge 171:3a7713b1edbc 12194 #define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12195 #define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12196 #define XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_LQI_FROM_RX_DIG_MASK)
AnnaBridge 171:3a7713b1edbc 12197 #define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12198 #define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12199 #define XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_SHIFT)) & XCVR_ZBDEM_CCA_LQI_SRC_LQI_START_AT_SFD_MASK)
AnnaBridge 171:3a7713b1edbc 12200
AnnaBridge 171:3a7713b1edbc 12201 /*! @name FAD_THR - FAD CORRELATOR THRESHOLD */
AnnaBridge 171:3a7713b1edbc 12202 #define XCVR_ZBDEM_FAD_THR_FAD_THR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12203 #define XCVR_ZBDEM_FAD_THR_FAD_THR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12204 #define XCVR_ZBDEM_FAD_THR_FAD_THR(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_FAD_THR_FAD_THR_SHIFT)) & XCVR_ZBDEM_FAD_THR_FAD_THR_MASK)
AnnaBridge 171:3a7713b1edbc 12205
AnnaBridge 171:3a7713b1edbc 12206 /*! @name ZBDEM_AFC - 802.15.4 AFC STATUS */
AnnaBridge 171:3a7713b1edbc 12207 #define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12208 #define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12209 #define XCVR_ZBDEM_ZBDEM_AFC_AFC_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_AFC_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12210 #define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12211 #define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12212 #define XCVR_ZBDEM_ZBDEM_AFC_DCD_EN(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_DCD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12213 #define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 12214 #define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12215 #define XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT(x) (((uint32_t)(((uint32_t)(x)) << XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_SHIFT)) & XCVR_ZBDEM_ZBDEM_AFC_AFC_OUT_MASK)
AnnaBridge 171:3a7713b1edbc 12216
AnnaBridge 171:3a7713b1edbc 12217
AnnaBridge 171:3a7713b1edbc 12218 /*!
AnnaBridge 171:3a7713b1edbc 12219 * @}
AnnaBridge 171:3a7713b1edbc 12220 */ /* end of group XCVR_ZBDEM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 12221
AnnaBridge 171:3a7713b1edbc 12222
AnnaBridge 171:3a7713b1edbc 12223 /* XCVR_ZBDEM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 12224 /** Peripheral XCVR_ZBDEM base address */
AnnaBridge 171:3a7713b1edbc 12225 #define XCVR_ZBDEM_BASE (0x4005C480u)
AnnaBridge 171:3a7713b1edbc 12226 /** Peripheral XCVR_ZBDEM base pointer */
AnnaBridge 171:3a7713b1edbc 12227 #define XCVR_ZBDEM ((XCVR_ZBDEM_Type *)XCVR_ZBDEM_BASE)
AnnaBridge 171:3a7713b1edbc 12228 /** Array initializer of XCVR_ZBDEM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 12229 #define XCVR_ZBDEM_BASE_ADDRS { XCVR_ZBDEM_BASE }
AnnaBridge 171:3a7713b1edbc 12230 /** Array initializer of XCVR_ZBDEM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 12231 #define XCVR_ZBDEM_BASE_PTRS { XCVR_ZBDEM }
AnnaBridge 171:3a7713b1edbc 12232
AnnaBridge 171:3a7713b1edbc 12233 /*!
AnnaBridge 171:3a7713b1edbc 12234 * @}
AnnaBridge 171:3a7713b1edbc 12235 */ /* end of group XCVR_ZBDEM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 12236
AnnaBridge 171:3a7713b1edbc 12237
AnnaBridge 171:3a7713b1edbc 12238 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12239 -- ZLL Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12240 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12241
AnnaBridge 171:3a7713b1edbc 12242 /*!
AnnaBridge 171:3a7713b1edbc 12243 * @addtogroup ZLL_Peripheral_Access_Layer ZLL Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12244 * @{
AnnaBridge 171:3a7713b1edbc 12245 */
AnnaBridge 171:3a7713b1edbc 12246
AnnaBridge 171:3a7713b1edbc 12247 /** ZLL - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 12248 typedef struct {
AnnaBridge 171:3a7713b1edbc 12249 __IO uint32_t IRQSTS; /**< INTERRUPT REQUEST STATUS, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 12250 __IO uint32_t PHY_CTRL; /**< PHY CONTROL, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 12251 __IO uint32_t EVENT_TMR; /**< EVENT TIMER, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 12252 __I uint32_t TIMESTAMP; /**< TIMESTAMP, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 12253 __IO uint32_t T1CMP; /**< T1 COMPARE, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 12254 __IO uint32_t T2CMP; /**< T2 COMPARE, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 12255 __IO uint32_t T2PRIMECMP; /**< T2 PRIME COMPARE, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 12256 __IO uint32_t T3CMP; /**< T3 COMPARE, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 12257 __IO uint32_t T4CMP; /**< T4 COMPARE, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 12258 __IO uint32_t PA_PWR; /**< PA POWER, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 12259 __IO uint32_t CHANNEL_NUM0; /**< CHANNEL NUMBER 0, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 12260 __I uint32_t LQI_AND_RSSI; /**< LQI AND RSSI, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 12261 __IO uint32_t MACSHORTADDRS0; /**< MAC SHORT ADDRESS 0, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 12262 __IO uint32_t MACLONGADDRS0_LSB; /**< MAC LONG ADDRESS 0 LSB, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 12263 __IO uint32_t MACLONGADDRS0_MSB; /**< MAC LONG ADDRESS 0 MSB, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 12264 __IO uint32_t RX_FRAME_FILTER; /**< RECEIVE FRAME FILTER, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 12265 __IO uint32_t CCA_LQI_CTRL; /**< CCA AND LQI CONTROL, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 12266 __IO uint32_t CCA2_CTRL; /**< CCA2 CONTROL, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 12267 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 12268 __IO uint32_t DSM_CTRL; /**< DSM CONTROL, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 12269 __IO uint32_t BSM_CTRL; /**< BSM CONTROL, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 12270 __IO uint32_t MACSHORTADDRS1; /**< MAC SHORT ADDRESS FOR PAN1, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 12271 __IO uint32_t MACLONGADDRS1_LSB; /**< MAC LONG ADDRESS 1 LSB, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 12272 __IO uint32_t MACLONGADDRS1_MSB; /**< MAC LONG ADDRESS 1 MSB, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 12273 __IO uint32_t DUAL_PAN_CTRL; /**< DUAL PAN CONTROL, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 12274 __IO uint32_t CHANNEL_NUM1; /**< CHANNEL NUMBER 1, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 12275 __IO uint32_t SAM_CTRL; /**< SAM CONTROL, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 12276 __IO uint32_t SAM_TABLE; /**< SOURCE ADDRESS MANAGEMENT TABLE, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 12277 __I uint32_t SAM_MATCH; /**< SOURCE ADDRESS MANAGEMENT MATCH, offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 12278 __I uint32_t SAM_FREE_IDX; /**< SAM FREE INDEX, offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 12279 __IO uint32_t SEQ_CTRL_STS; /**< SEQUENCE CONTROL AND STATUS, offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 12280 __IO uint32_t ACKDELAY; /**< ACK DELAY, offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 12281 __IO uint32_t FILTERFAIL_CODE; /**< FILTER FAIL CODE, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 12282 __IO uint32_t RX_WTR_MARK; /**< RECEIVE WATER MARK, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 12283 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 12284 __IO uint32_t SLOT_PRELOAD; /**< SLOT PRELOAD, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 12285 __I uint32_t SEQ_STATE; /**< 802.15.4 SEQUENCE STATE, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 12286 __IO uint32_t TMR_PRESCALE; /**< TIMER PRESCALER, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 12287 __IO uint32_t LENIENCY_LSB; /**< LENIENCY LSB, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 12288 __IO uint32_t LENIENCY_MSB; /**< LENIENCY MSB, offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 12289 __I uint32_t PART_ID; /**< PART ID, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 12290 uint8_t RESERVED_2[92];
AnnaBridge 171:3a7713b1edbc 12291 __IO uint16_t PKT_BUFFER_TX[64]; /**< Packet Buffer TX, array offset: 0x100, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 12292 __IO uint16_t PKT_BUFFER_RX[64]; /**< Packet Buffer RX, array offset: 0x180, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 12293 } ZLL_Type;
AnnaBridge 171:3a7713b1edbc 12294
AnnaBridge 171:3a7713b1edbc 12295 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12296 -- ZLL Register Masks
AnnaBridge 171:3a7713b1edbc 12297 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12298
AnnaBridge 171:3a7713b1edbc 12299 /*!
AnnaBridge 171:3a7713b1edbc 12300 * @addtogroup ZLL_Register_Masks ZLL Register Masks
AnnaBridge 171:3a7713b1edbc 12301 * @{
AnnaBridge 171:3a7713b1edbc 12302 */
AnnaBridge 171:3a7713b1edbc 12303
AnnaBridge 171:3a7713b1edbc 12304 /*! @name IRQSTS - INTERRUPT REQUEST STATUS */
AnnaBridge 171:3a7713b1edbc 12305 #define ZLL_IRQSTS_SEQIRQ_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12306 #define ZLL_IRQSTS_SEQIRQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12307 #define ZLL_IRQSTS_SEQIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SEQIRQ_SHIFT)) & ZLL_IRQSTS_SEQIRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12308 #define ZLL_IRQSTS_TXIRQ_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12309 #define ZLL_IRQSTS_TXIRQ_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12310 #define ZLL_IRQSTS_TXIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TXIRQ_SHIFT)) & ZLL_IRQSTS_TXIRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12311 #define ZLL_IRQSTS_RXIRQ_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12312 #define ZLL_IRQSTS_RXIRQ_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12313 #define ZLL_IRQSTS_RXIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RXIRQ_SHIFT)) & ZLL_IRQSTS_RXIRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12314 #define ZLL_IRQSTS_CCAIRQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12315 #define ZLL_IRQSTS_CCAIRQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12316 #define ZLL_IRQSTS_CCAIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CCAIRQ_SHIFT)) & ZLL_IRQSTS_CCAIRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12317 #define ZLL_IRQSTS_RXWTRMRKIRQ_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12318 #define ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12319 #define ZLL_IRQSTS_RXWTRMRKIRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT)) & ZLL_IRQSTS_RXWTRMRKIRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12320 #define ZLL_IRQSTS_FILTERFAIL_IRQ_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12321 #define ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12322 #define ZLL_IRQSTS_FILTERFAIL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT)) & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12323 #define ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12324 #define ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12325 #define ZLL_IRQSTS_PLL_UNLOCK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT)) & ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12326 #define ZLL_IRQSTS_RX_FRM_PEND_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12327 #define ZLL_IRQSTS_RX_FRM_PEND_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12328 #define ZLL_IRQSTS_RX_FRM_PEND(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RX_FRM_PEND_SHIFT)) & ZLL_IRQSTS_RX_FRM_PEND_MASK)
AnnaBridge 171:3a7713b1edbc 12329 #define ZLL_IRQSTS_WAKE_IRQ_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 12330 #define ZLL_IRQSTS_WAKE_IRQ_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12331 #define ZLL_IRQSTS_WAKE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_WAKE_IRQ_SHIFT)) & ZLL_IRQSTS_WAKE_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12332 #define ZLL_IRQSTS_TSM_IRQ_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 12333 #define ZLL_IRQSTS_TSM_IRQ_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 12334 #define ZLL_IRQSTS_TSM_IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TSM_IRQ_SHIFT)) & ZLL_IRQSTS_TSM_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12335 #define ZLL_IRQSTS_ENH_PKT_STATUS_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 12336 #define ZLL_IRQSTS_ENH_PKT_STATUS_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 12337 #define ZLL_IRQSTS_ENH_PKT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_ENH_PKT_STATUS_SHIFT)) & ZLL_IRQSTS_ENH_PKT_STATUS_MASK)
AnnaBridge 171:3a7713b1edbc 12338 #define ZLL_IRQSTS_PI_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12339 #define ZLL_IRQSTS_PI_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12340 #define ZLL_IRQSTS_PI(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_PI_SHIFT)) & ZLL_IRQSTS_PI_MASK)
AnnaBridge 171:3a7713b1edbc 12341 #define ZLL_IRQSTS_SRCADDR_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 12342 #define ZLL_IRQSTS_SRCADDR_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 12343 #define ZLL_IRQSTS_SRCADDR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_SRCADDR_SHIFT)) & ZLL_IRQSTS_SRCADDR_MASK)
AnnaBridge 171:3a7713b1edbc 12344 #define ZLL_IRQSTS_CCA_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 12345 #define ZLL_IRQSTS_CCA_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 12346 #define ZLL_IRQSTS_CCA(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CCA_SHIFT)) & ZLL_IRQSTS_CCA_MASK)
AnnaBridge 171:3a7713b1edbc 12347 #define ZLL_IRQSTS_CRCVALID_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 12348 #define ZLL_IRQSTS_CRCVALID_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 12349 #define ZLL_IRQSTS_CRCVALID(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_CRCVALID_SHIFT)) & ZLL_IRQSTS_CRCVALID_MASK)
AnnaBridge 171:3a7713b1edbc 12350 #define ZLL_IRQSTS_TMR1IRQ_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 12351 #define ZLL_IRQSTS_TMR1IRQ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12352 #define ZLL_IRQSTS_TMR1IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR1IRQ_SHIFT)) & ZLL_IRQSTS_TMR1IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12353 #define ZLL_IRQSTS_TMR2IRQ_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 12354 #define ZLL_IRQSTS_TMR2IRQ_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 12355 #define ZLL_IRQSTS_TMR2IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR2IRQ_SHIFT)) & ZLL_IRQSTS_TMR2IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12356 #define ZLL_IRQSTS_TMR3IRQ_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 12357 #define ZLL_IRQSTS_TMR3IRQ_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12358 #define ZLL_IRQSTS_TMR3IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR3IRQ_SHIFT)) & ZLL_IRQSTS_TMR3IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12359 #define ZLL_IRQSTS_TMR4IRQ_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 12360 #define ZLL_IRQSTS_TMR4IRQ_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 12361 #define ZLL_IRQSTS_TMR4IRQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR4IRQ_SHIFT)) & ZLL_IRQSTS_TMR4IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 12362 #define ZLL_IRQSTS_TMR1MSK_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 12363 #define ZLL_IRQSTS_TMR1MSK_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12364 #define ZLL_IRQSTS_TMR1MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR1MSK_SHIFT)) & ZLL_IRQSTS_TMR1MSK_MASK)
AnnaBridge 171:3a7713b1edbc 12365 #define ZLL_IRQSTS_TMR2MSK_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 12366 #define ZLL_IRQSTS_TMR2MSK_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 12367 #define ZLL_IRQSTS_TMR2MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR2MSK_SHIFT)) & ZLL_IRQSTS_TMR2MSK_MASK)
AnnaBridge 171:3a7713b1edbc 12368 #define ZLL_IRQSTS_TMR3MSK_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 12369 #define ZLL_IRQSTS_TMR3MSK_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 12370 #define ZLL_IRQSTS_TMR3MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR3MSK_SHIFT)) & ZLL_IRQSTS_TMR3MSK_MASK)
AnnaBridge 171:3a7713b1edbc 12371 #define ZLL_IRQSTS_TMR4MSK_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 12372 #define ZLL_IRQSTS_TMR4MSK_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 12373 #define ZLL_IRQSTS_TMR4MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_TMR4MSK_SHIFT)) & ZLL_IRQSTS_TMR4MSK_MASK)
AnnaBridge 171:3a7713b1edbc 12374 #define ZLL_IRQSTS_RX_FRAME_LENGTH_MASK (0x7F000000U)
AnnaBridge 171:3a7713b1edbc 12375 #define ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12376 #define ZLL_IRQSTS_RX_FRAME_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT)) & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK)
AnnaBridge 171:3a7713b1edbc 12377
AnnaBridge 171:3a7713b1edbc 12378 /*! @name PHY_CTRL - PHY CONTROL */
AnnaBridge 171:3a7713b1edbc 12379 #define ZLL_PHY_CTRL_XCVSEQ_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 12380 #define ZLL_PHY_CTRL_XCVSEQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12381 #define ZLL_PHY_CTRL_XCVSEQ(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_XCVSEQ_SHIFT)) & ZLL_PHY_CTRL_XCVSEQ_MASK)
AnnaBridge 171:3a7713b1edbc 12382 #define ZLL_PHY_CTRL_AUTOACK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12383 #define ZLL_PHY_CTRL_AUTOACK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12384 #define ZLL_PHY_CTRL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_AUTOACK_SHIFT)) & ZLL_PHY_CTRL_AUTOACK_MASK)
AnnaBridge 171:3a7713b1edbc 12385 #define ZLL_PHY_CTRL_RXACKRQD_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12386 #define ZLL_PHY_CTRL_RXACKRQD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12387 #define ZLL_PHY_CTRL_RXACKRQD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RXACKRQD_SHIFT)) & ZLL_PHY_CTRL_RXACKRQD_MASK)
AnnaBridge 171:3a7713b1edbc 12388 #define ZLL_PHY_CTRL_CCABFRTX_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12389 #define ZLL_PHY_CTRL_CCABFRTX_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12390 #define ZLL_PHY_CTRL_CCABFRTX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCABFRTX_SHIFT)) & ZLL_PHY_CTRL_CCABFRTX_MASK)
AnnaBridge 171:3a7713b1edbc 12391 #define ZLL_PHY_CTRL_SLOTTED_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12392 #define ZLL_PHY_CTRL_SLOTTED_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12393 #define ZLL_PHY_CTRL_SLOTTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_SLOTTED_SHIFT)) & ZLL_PHY_CTRL_SLOTTED_MASK)
AnnaBridge 171:3a7713b1edbc 12394 #define ZLL_PHY_CTRL_TMRTRIGEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12395 #define ZLL_PHY_CTRL_TMRTRIGEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12396 #define ZLL_PHY_CTRL_TMRTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMRTRIGEN_SHIFT)) & ZLL_PHY_CTRL_TMRTRIGEN_MASK)
AnnaBridge 171:3a7713b1edbc 12397 #define ZLL_PHY_CTRL_SEQMSK_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 12398 #define ZLL_PHY_CTRL_SEQMSK_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12399 #define ZLL_PHY_CTRL_SEQMSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_SEQMSK_SHIFT)) & ZLL_PHY_CTRL_SEQMSK_MASK)
AnnaBridge 171:3a7713b1edbc 12400 #define ZLL_PHY_CTRL_TXMSK_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 12401 #define ZLL_PHY_CTRL_TXMSK_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 12402 #define ZLL_PHY_CTRL_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TXMSK_SHIFT)) & ZLL_PHY_CTRL_TXMSK_MASK)
AnnaBridge 171:3a7713b1edbc 12403 #define ZLL_PHY_CTRL_RXMSK_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 12404 #define ZLL_PHY_CTRL_RXMSK_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 12405 #define ZLL_PHY_CTRL_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RXMSK_SHIFT)) & ZLL_PHY_CTRL_RXMSK_MASK)
AnnaBridge 171:3a7713b1edbc 12406 #define ZLL_PHY_CTRL_CCAMSK_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 12407 #define ZLL_PHY_CTRL_CCAMSK_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 12408 #define ZLL_PHY_CTRL_CCAMSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCAMSK_SHIFT)) & ZLL_PHY_CTRL_CCAMSK_MASK)
AnnaBridge 171:3a7713b1edbc 12409 #define ZLL_PHY_CTRL_RX_WMRK_MSK_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12410 #define ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12411 #define ZLL_PHY_CTRL_RX_WMRK_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT)) & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK)
AnnaBridge 171:3a7713b1edbc 12412 #define ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 12413 #define ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 12414 #define ZLL_PHY_CTRL_FILTERFAIL_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT)) & ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK)
AnnaBridge 171:3a7713b1edbc 12415 #define ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 12416 #define ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 12417 #define ZLL_PHY_CTRL_PLL_UNLOCK_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT)) & ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK)
AnnaBridge 171:3a7713b1edbc 12418 #define ZLL_PHY_CTRL_CRC_MSK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 12419 #define ZLL_PHY_CTRL_CRC_MSK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 12420 #define ZLL_PHY_CTRL_CRC_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CRC_MSK_SHIFT)) & ZLL_PHY_CTRL_CRC_MSK_MASK)
AnnaBridge 171:3a7713b1edbc 12421 #define ZLL_PHY_CTRL_WAKE_MSK_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 12422 #define ZLL_PHY_CTRL_WAKE_MSK_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12423 #define ZLL_PHY_CTRL_WAKE_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_WAKE_MSK_SHIFT)) & ZLL_PHY_CTRL_WAKE_MSK_MASK)
AnnaBridge 171:3a7713b1edbc 12424 #define ZLL_PHY_CTRL_TSM_MSK_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 12425 #define ZLL_PHY_CTRL_TSM_MSK_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12426 #define ZLL_PHY_CTRL_TSM_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TSM_MSK_SHIFT)) & ZLL_PHY_CTRL_TSM_MSK_MASK)
AnnaBridge 171:3a7713b1edbc 12427 #define ZLL_PHY_CTRL_TMR1CMP_EN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 12428 #define ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12429 #define ZLL_PHY_CTRL_TMR1CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR1CMP_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12430 #define ZLL_PHY_CTRL_TMR2CMP_EN_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 12431 #define ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 12432 #define ZLL_PHY_CTRL_TMR2CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR2CMP_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12433 #define ZLL_PHY_CTRL_TMR3CMP_EN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 12434 #define ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 12435 #define ZLL_PHY_CTRL_TMR3CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR3CMP_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12436 #define ZLL_PHY_CTRL_TMR4CMP_EN_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 12437 #define ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 12438 #define ZLL_PHY_CTRL_TMR4CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT)) & ZLL_PHY_CTRL_TMR4CMP_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12439 #define ZLL_PHY_CTRL_TC2PRIME_EN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 12440 #define ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12441 #define ZLL_PHY_CTRL_TC2PRIME_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT)) & ZLL_PHY_CTRL_TC2PRIME_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12442 #define ZLL_PHY_CTRL_PROMISCUOUS_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12443 #define ZLL_PHY_CTRL_PROMISCUOUS_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12444 #define ZLL_PHY_CTRL_PROMISCUOUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PROMISCUOUS_SHIFT)) & ZLL_PHY_CTRL_PROMISCUOUS_MASK)
AnnaBridge 171:3a7713b1edbc 12445 #define ZLL_PHY_CTRL_CCATYPE_MASK (0x18000000U)
AnnaBridge 171:3a7713b1edbc 12446 #define ZLL_PHY_CTRL_CCATYPE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12447 #define ZLL_PHY_CTRL_CCATYPE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_CCATYPE_SHIFT)) & ZLL_PHY_CTRL_CCATYPE_MASK)
AnnaBridge 171:3a7713b1edbc 12448 #define ZLL_PHY_CTRL_PANCORDNTR0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 12449 #define ZLL_PHY_CTRL_PANCORDNTR0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 12450 #define ZLL_PHY_CTRL_PANCORDNTR0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_PANCORDNTR0_SHIFT)) & ZLL_PHY_CTRL_PANCORDNTR0_MASK)
AnnaBridge 171:3a7713b1edbc 12451 #define ZLL_PHY_CTRL_TC3TMOUT_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 12452 #define ZLL_PHY_CTRL_TC3TMOUT_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 12453 #define ZLL_PHY_CTRL_TC3TMOUT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TC3TMOUT_SHIFT)) & ZLL_PHY_CTRL_TC3TMOUT_MASK)
AnnaBridge 171:3a7713b1edbc 12454 #define ZLL_PHY_CTRL_TRCV_MSK_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12455 #define ZLL_PHY_CTRL_TRCV_MSK_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12456 #define ZLL_PHY_CTRL_TRCV_MSK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PHY_CTRL_TRCV_MSK_SHIFT)) & ZLL_PHY_CTRL_TRCV_MSK_MASK)
AnnaBridge 171:3a7713b1edbc 12457
AnnaBridge 171:3a7713b1edbc 12458 /*! @name EVENT_TMR - EVENT TIMER */
AnnaBridge 171:3a7713b1edbc 12459 #define ZLL_EVENT_TMR_EVENT_TMR_LD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12460 #define ZLL_EVENT_TMR_EVENT_TMR_LD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12461 #define ZLL_EVENT_TMR_EVENT_TMR_LD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_LD_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_LD_MASK)
AnnaBridge 171:3a7713b1edbc 12462 #define ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12463 #define ZLL_EVENT_TMR_EVENT_TMR_ADD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12464 #define ZLL_EVENT_TMR_EVENT_TMR_ADD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_ADD_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_ADD_MASK)
AnnaBridge 171:3a7713b1edbc 12465 #define ZLL_EVENT_TMR_EVENT_TMR_FRAC_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 12466 #define ZLL_EVENT_TMR_EVENT_TMR_FRAC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12467 #define ZLL_EVENT_TMR_EVENT_TMR_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_FRAC_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_FRAC_MASK)
AnnaBridge 171:3a7713b1edbc 12468 #define ZLL_EVENT_TMR_EVENT_TMR_MASK (0xFFFFFF00U)
AnnaBridge 171:3a7713b1edbc 12469 #define ZLL_EVENT_TMR_EVENT_TMR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12470 #define ZLL_EVENT_TMR_EVENT_TMR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_EVENT_TMR_EVENT_TMR_SHIFT)) & ZLL_EVENT_TMR_EVENT_TMR_MASK)
AnnaBridge 171:3a7713b1edbc 12471
AnnaBridge 171:3a7713b1edbc 12472 /*! @name TIMESTAMP - TIMESTAMP */
AnnaBridge 171:3a7713b1edbc 12473 #define ZLL_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12474 #define ZLL_TIMESTAMP_TIMESTAMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12475 #define ZLL_TIMESTAMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_TIMESTAMP_TIMESTAMP_SHIFT)) & ZLL_TIMESTAMP_TIMESTAMP_MASK)
AnnaBridge 171:3a7713b1edbc 12476
AnnaBridge 171:3a7713b1edbc 12477 /*! @name T1CMP - T1 COMPARE */
AnnaBridge 171:3a7713b1edbc 12478 #define ZLL_T1CMP_T1CMP_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12479 #define ZLL_T1CMP_T1CMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12480 #define ZLL_T1CMP_T1CMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T1CMP_T1CMP_SHIFT)) & ZLL_T1CMP_T1CMP_MASK)
AnnaBridge 171:3a7713b1edbc 12481
AnnaBridge 171:3a7713b1edbc 12482 /*! @name T2CMP - T2 COMPARE */
AnnaBridge 171:3a7713b1edbc 12483 #define ZLL_T2CMP_T2CMP_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12484 #define ZLL_T2CMP_T2CMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12485 #define ZLL_T2CMP_T2CMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T2CMP_T2CMP_SHIFT)) & ZLL_T2CMP_T2CMP_MASK)
AnnaBridge 171:3a7713b1edbc 12486
AnnaBridge 171:3a7713b1edbc 12487 /*! @name T2PRIMECMP - T2 PRIME COMPARE */
AnnaBridge 171:3a7713b1edbc 12488 #define ZLL_T2PRIMECMP_T2PRIMECMP_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12489 #define ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12490 #define ZLL_T2PRIMECMP_T2PRIMECMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT)) & ZLL_T2PRIMECMP_T2PRIMECMP_MASK)
AnnaBridge 171:3a7713b1edbc 12491
AnnaBridge 171:3a7713b1edbc 12492 /*! @name T3CMP - T3 COMPARE */
AnnaBridge 171:3a7713b1edbc 12493 #define ZLL_T3CMP_T3CMP_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12494 #define ZLL_T3CMP_T3CMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12495 #define ZLL_T3CMP_T3CMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T3CMP_T3CMP_SHIFT)) & ZLL_T3CMP_T3CMP_MASK)
AnnaBridge 171:3a7713b1edbc 12496
AnnaBridge 171:3a7713b1edbc 12497 /*! @name T4CMP - T4 COMPARE */
AnnaBridge 171:3a7713b1edbc 12498 #define ZLL_T4CMP_T4CMP_MASK (0xFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12499 #define ZLL_T4CMP_T4CMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12500 #define ZLL_T4CMP_T4CMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_T4CMP_T4CMP_SHIFT)) & ZLL_T4CMP_T4CMP_MASK)
AnnaBridge 171:3a7713b1edbc 12501
AnnaBridge 171:3a7713b1edbc 12502 /*! @name PA_PWR - PA POWER */
AnnaBridge 171:3a7713b1edbc 12503 #define ZLL_PA_PWR_PA_PWR_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 12504 #define ZLL_PA_PWR_PA_PWR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12505 #define ZLL_PA_PWR_PA_PWR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PA_PWR_PA_PWR_SHIFT)) & ZLL_PA_PWR_PA_PWR_MASK)
AnnaBridge 171:3a7713b1edbc 12506
AnnaBridge 171:3a7713b1edbc 12507 /*! @name CHANNEL_NUM0 - CHANNEL NUMBER 0 */
AnnaBridge 171:3a7713b1edbc 12508 #define ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 12509 #define ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12510 #define ZLL_CHANNEL_NUM0_CHANNEL_NUM0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT)) & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK)
AnnaBridge 171:3a7713b1edbc 12511
AnnaBridge 171:3a7713b1edbc 12512 /*! @name LQI_AND_RSSI - LQI AND RSSI */
AnnaBridge 171:3a7713b1edbc 12513 #define ZLL_LQI_AND_RSSI_LQI_VALUE_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12514 #define ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12515 #define ZLL_LQI_AND_RSSI_LQI_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT)) & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK)
AnnaBridge 171:3a7713b1edbc 12516 #define ZLL_LQI_AND_RSSI_RSSI_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 12517 #define ZLL_LQI_AND_RSSI_RSSI_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12518 #define ZLL_LQI_AND_RSSI_RSSI(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_RSSI_SHIFT)) & ZLL_LQI_AND_RSSI_RSSI_MASK)
AnnaBridge 171:3a7713b1edbc 12519 #define ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 12520 #define ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12521 #define ZLL_LQI_AND_RSSI_CCA1_ED_FNL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT)) & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK)
AnnaBridge 171:3a7713b1edbc 12522
AnnaBridge 171:3a7713b1edbc 12523 /*! @name MACSHORTADDRS0 - MAC SHORT ADDRESS 0 */
AnnaBridge 171:3a7713b1edbc 12524 #define ZLL_MACSHORTADDRS0_MACPANID0_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12525 #define ZLL_MACSHORTADDRS0_MACPANID0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12526 #define ZLL_MACSHORTADDRS0_MACPANID0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS0_MACPANID0_SHIFT)) & ZLL_MACSHORTADDRS0_MACPANID0_MASK)
AnnaBridge 171:3a7713b1edbc 12527 #define ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 12528 #define ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12529 #define ZLL_MACSHORTADDRS0_MACSHORTADDRS0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT)) & ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK)
AnnaBridge 171:3a7713b1edbc 12530
AnnaBridge 171:3a7713b1edbc 12531 /*! @name MACLONGADDRS0_LSB - MAC LONG ADDRESS 0 LSB */
AnnaBridge 171:3a7713b1edbc 12532 #define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12533 #define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12534 #define ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_SHIFT)) & ZLL_MACLONGADDRS0_LSB_MACLONGADDRS0_LSB_MASK)
AnnaBridge 171:3a7713b1edbc 12535
AnnaBridge 171:3a7713b1edbc 12536 /*! @name MACLONGADDRS0_MSB - MAC LONG ADDRESS 0 MSB */
AnnaBridge 171:3a7713b1edbc 12537 #define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12538 #define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12539 #define ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_SHIFT)) & ZLL_MACLONGADDRS0_MSB_MACLONGADDRS0_MSB_MASK)
AnnaBridge 171:3a7713b1edbc 12540
AnnaBridge 171:3a7713b1edbc 12541 /*! @name RX_FRAME_FILTER - RECEIVE FRAME FILTER */
AnnaBridge 171:3a7713b1edbc 12542 #define ZLL_RX_FRAME_FILTER_BEACON_FT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12543 #define ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12544 #define ZLL_RX_FRAME_FILTER_BEACON_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_BEACON_FT_MASK)
AnnaBridge 171:3a7713b1edbc 12545 #define ZLL_RX_FRAME_FILTER_DATA_FT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12546 #define ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12547 #define ZLL_RX_FRAME_FILTER_DATA_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_DATA_FT_MASK)
AnnaBridge 171:3a7713b1edbc 12548 #define ZLL_RX_FRAME_FILTER_ACK_FT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12549 #define ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12550 #define ZLL_RX_FRAME_FILTER_ACK_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_ACK_FT_MASK)
AnnaBridge 171:3a7713b1edbc 12551 #define ZLL_RX_FRAME_FILTER_CMD_FT_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12552 #define ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12553 #define ZLL_RX_FRAME_FILTER_CMD_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_CMD_FT_MASK)
AnnaBridge 171:3a7713b1edbc 12554 #define ZLL_RX_FRAME_FILTER_LLDN_FT_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12555 #define ZLL_RX_FRAME_FILTER_LLDN_FT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12556 #define ZLL_RX_FRAME_FILTER_LLDN_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_LLDN_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_LLDN_FT_MASK)
AnnaBridge 171:3a7713b1edbc 12557 #define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12558 #define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12559 #define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_MULTIPURPOSE_FT_MASK)
AnnaBridge 171:3a7713b1edbc 12560 #define ZLL_RX_FRAME_FILTER_NS_FT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12561 #define ZLL_RX_FRAME_FILTER_NS_FT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12562 #define ZLL_RX_FRAME_FILTER_NS_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_NS_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_NS_FT_MASK)
AnnaBridge 171:3a7713b1edbc 12563 #define ZLL_RX_FRAME_FILTER_EXTENDED_FT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12564 #define ZLL_RX_FRAME_FILTER_EXTENDED_FT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12565 #define ZLL_RX_FRAME_FILTER_EXTENDED_FT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_FT_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_FT_MASK)
AnnaBridge 171:3a7713b1edbc 12566 #define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 12567 #define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12568 #define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_SHIFT)) & ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK)
AnnaBridge 171:3a7713b1edbc 12569 #define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 12570 #define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 12571 #define ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT)) & ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK)
AnnaBridge 171:3a7713b1edbc 12572 #define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 12573 #define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 12574 #define ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_FCS_CHK_MASK)
AnnaBridge 171:3a7713b1edbc 12575 #define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 12576 #define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12577 #define ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_BEACON_RECD_MASK)
AnnaBridge 171:3a7713b1edbc 12578 #define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 12579 #define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 12580 #define ZLL_RX_FRAME_FILTER_FV2_DATA_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_DATA_RECD_MASK)
AnnaBridge 171:3a7713b1edbc 12581 #define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 12582 #define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12583 #define ZLL_RX_FRAME_FILTER_FV2_ACK_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_ACK_RECD_MASK)
AnnaBridge 171:3a7713b1edbc 12584 #define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 12585 #define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 12586 #define ZLL_RX_FRAME_FILTER_FV2_CMD_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_FV2_CMD_RECD_MASK)
AnnaBridge 171:3a7713b1edbc 12587 #define ZLL_RX_FRAME_FILTER_LLDN_RECD_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 12588 #define ZLL_RX_FRAME_FILTER_LLDN_RECD_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12589 #define ZLL_RX_FRAME_FILTER_LLDN_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_LLDN_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_LLDN_RECD_MASK)
AnnaBridge 171:3a7713b1edbc 12590 #define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 12591 #define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 12592 #define ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_MULTIPURPOSE_RECD_MASK)
AnnaBridge 171:3a7713b1edbc 12593 #define ZLL_RX_FRAME_FILTER_EXTENDED_RECD_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 12594 #define ZLL_RX_FRAME_FILTER_EXTENDED_RECD_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 12595 #define ZLL_RX_FRAME_FILTER_EXTENDED_RECD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_FRAME_FILTER_EXTENDED_RECD_SHIFT)) & ZLL_RX_FRAME_FILTER_EXTENDED_RECD_MASK)
AnnaBridge 171:3a7713b1edbc 12596
AnnaBridge 171:3a7713b1edbc 12597 /*! @name CCA_LQI_CTRL - CCA AND LQI CONTROL */
AnnaBridge 171:3a7713b1edbc 12598 #define ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12599 #define ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12600 #define ZLL_CCA_LQI_CTRL_CCA1_THRESH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT)) & ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 12601 #define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 12602 #define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12603 #define ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT)) & ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK)
AnnaBridge 171:3a7713b1edbc 12604 #define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 12605 #define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12606 #define ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT)) & ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_MASK)
AnnaBridge 171:3a7713b1edbc 12607
AnnaBridge 171:3a7713b1edbc 12608 /*! @name CCA2_CTRL - CCA2 CONTROL */
AnnaBridge 171:3a7713b1edbc 12609 #define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 12610 #define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12611 #define ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_SHIFT)) & ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_MASK)
AnnaBridge 171:3a7713b1edbc 12612 #define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 12613 #define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12614 #define ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT)) & ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_MASK)
AnnaBridge 171:3a7713b1edbc 12615 #define ZLL_CCA2_CTRL_CCA2_CORR_THRESH_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 12616 #define ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12617 #define ZLL_CCA2_CTRL_CCA2_CORR_THRESH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT)) & ZLL_CCA2_CTRL_CCA2_CORR_THRESH_MASK)
AnnaBridge 171:3a7713b1edbc 12618
AnnaBridge 171:3a7713b1edbc 12619 /*! @name DSM_CTRL - DSM CONTROL */
AnnaBridge 171:3a7713b1edbc 12620 #define ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12621 #define ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12622 #define ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_SHIFT)) & ZLL_DSM_CTRL_ZIGBEE_SLEEP_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12623
AnnaBridge 171:3a7713b1edbc 12624 /*! @name BSM_CTRL - BSM CONTROL */
AnnaBridge 171:3a7713b1edbc 12625 #define ZLL_BSM_CTRL_BSM_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12626 #define ZLL_BSM_CTRL_BSM_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12627 #define ZLL_BSM_CTRL_BSM_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_BSM_CTRL_BSM_EN_SHIFT)) & ZLL_BSM_CTRL_BSM_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12628
AnnaBridge 171:3a7713b1edbc 12629 /*! @name MACSHORTADDRS1 - MAC SHORT ADDRESS FOR PAN1 */
AnnaBridge 171:3a7713b1edbc 12630 #define ZLL_MACSHORTADDRS1_MACPANID1_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12631 #define ZLL_MACSHORTADDRS1_MACPANID1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12632 #define ZLL_MACSHORTADDRS1_MACPANID1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS1_MACPANID1_SHIFT)) & ZLL_MACSHORTADDRS1_MACPANID1_MASK)
AnnaBridge 171:3a7713b1edbc 12633 #define ZLL_MACSHORTADDRS1_MACSHORTADDRS1_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 12634 #define ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12635 #define ZLL_MACSHORTADDRS1_MACSHORTADDRS1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT)) & ZLL_MACSHORTADDRS1_MACSHORTADDRS1_MASK)
AnnaBridge 171:3a7713b1edbc 12636
AnnaBridge 171:3a7713b1edbc 12637 /*! @name MACLONGADDRS1_LSB - MAC LONG ADDRESS 1 LSB */
AnnaBridge 171:3a7713b1edbc 12638 #define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12639 #define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12640 #define ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_SHIFT)) & ZLL_MACLONGADDRS1_LSB_MACLONGADDRS1_LSB_MASK)
AnnaBridge 171:3a7713b1edbc 12641
AnnaBridge 171:3a7713b1edbc 12642 /*! @name MACLONGADDRS1_MSB - MAC LONG ADDRESS 1 MSB */
AnnaBridge 171:3a7713b1edbc 12643 #define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12644 #define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12645 #define ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_SHIFT)) & ZLL_MACLONGADDRS1_MSB_MACLONGADDRS1_MSB_MASK)
AnnaBridge 171:3a7713b1edbc 12646
AnnaBridge 171:3a7713b1edbc 12647 /*! @name DUAL_PAN_CTRL - DUAL PAN CONTROL */
AnnaBridge 171:3a7713b1edbc 12648 #define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12649 #define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12650 #define ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT)) & ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK)
AnnaBridge 171:3a7713b1edbc 12651 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12652 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12653 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK)
AnnaBridge 171:3a7713b1edbc 12654 #define ZLL_DUAL_PAN_CTRL_PANCORDNTR1_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12655 #define ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12656 #define ZLL_DUAL_PAN_CTRL_PANCORDNTR1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT)) & ZLL_DUAL_PAN_CTRL_PANCORDNTR1_MASK)
AnnaBridge 171:3a7713b1edbc 12657 #define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12658 #define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12659 #define ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT)) & ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK)
AnnaBridge 171:3a7713b1edbc 12660 #define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12661 #define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12662 #define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT)) & ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12663 #define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12664 #define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12665 #define ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT)) & ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 12666 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 12667 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12668 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK)
AnnaBridge 171:3a7713b1edbc 12669 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 12670 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12671 #define ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT)) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK)
AnnaBridge 171:3a7713b1edbc 12672 #define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 12673 #define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 12674 #define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT)) & ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK)
AnnaBridge 171:3a7713b1edbc 12675 #define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 12676 #define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 12677 #define ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT)) & ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK)
AnnaBridge 171:3a7713b1edbc 12678
AnnaBridge 171:3a7713b1edbc 12679 /*! @name CHANNEL_NUM1 - CHANNEL NUMBER 1 */
AnnaBridge 171:3a7713b1edbc 12680 #define ZLL_CHANNEL_NUM1_CHANNEL_NUM1_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 12681 #define ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12682 #define ZLL_CHANNEL_NUM1_CHANNEL_NUM1(x) (((uint32_t)(((uint32_t)(x)) << ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT)) & ZLL_CHANNEL_NUM1_CHANNEL_NUM1_MASK)
AnnaBridge 171:3a7713b1edbc 12683
AnnaBridge 171:3a7713b1edbc 12684 /*! @name SAM_CTRL - SAM CONTROL */
AnnaBridge 171:3a7713b1edbc 12685 #define ZLL_SAM_CTRL_SAP0_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12686 #define ZLL_SAM_CTRL_SAP0_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12687 #define ZLL_SAM_CTRL_SAP0_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP0_EN_SHIFT)) & ZLL_SAM_CTRL_SAP0_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12688 #define ZLL_SAM_CTRL_SAA0_EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12689 #define ZLL_SAM_CTRL_SAA0_EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12690 #define ZLL_SAM_CTRL_SAA0_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA0_EN_SHIFT)) & ZLL_SAM_CTRL_SAA0_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12691 #define ZLL_SAM_CTRL_SAP1_EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12692 #define ZLL_SAM_CTRL_SAP1_EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12693 #define ZLL_SAM_CTRL_SAP1_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP1_EN_SHIFT)) & ZLL_SAM_CTRL_SAP1_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12694 #define ZLL_SAM_CTRL_SAA1_EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12695 #define ZLL_SAM_CTRL_SAA1_EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12696 #define ZLL_SAM_CTRL_SAA1_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA1_EN_SHIFT)) & ZLL_SAM_CTRL_SAA1_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12697 #define ZLL_SAM_CTRL_SAA0_START_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 12698 #define ZLL_SAM_CTRL_SAA0_START_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12699 #define ZLL_SAM_CTRL_SAA0_START(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA0_START_SHIFT)) & ZLL_SAM_CTRL_SAA0_START_MASK)
AnnaBridge 171:3a7713b1edbc 12700 #define ZLL_SAM_CTRL_SAP1_START_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 12701 #define ZLL_SAM_CTRL_SAP1_START_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12702 #define ZLL_SAM_CTRL_SAP1_START(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAP1_START_SHIFT)) & ZLL_SAM_CTRL_SAP1_START_MASK)
AnnaBridge 171:3a7713b1edbc 12703 #define ZLL_SAM_CTRL_SAA1_START_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 12704 #define ZLL_SAM_CTRL_SAA1_START_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12705 #define ZLL_SAM_CTRL_SAA1_START(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_CTRL_SAA1_START_SHIFT)) & ZLL_SAM_CTRL_SAA1_START_MASK)
AnnaBridge 171:3a7713b1edbc 12706
AnnaBridge 171:3a7713b1edbc 12707 /*! @name SAM_TABLE - SOURCE ADDRESS MANAGEMENT TABLE */
AnnaBridge 171:3a7713b1edbc 12708 #define ZLL_SAM_TABLE_SAM_INDEX_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 12709 #define ZLL_SAM_TABLE_SAM_INDEX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12710 #define ZLL_SAM_TABLE_SAM_INDEX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_MASK)
AnnaBridge 171:3a7713b1edbc 12711 #define ZLL_SAM_TABLE_SAM_INDEX_WR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12712 #define ZLL_SAM_TABLE_SAM_INDEX_WR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12713 #define ZLL_SAM_TABLE_SAM_INDEX_WR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_WR_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_WR_MASK)
AnnaBridge 171:3a7713b1edbc 12714 #define ZLL_SAM_TABLE_SAM_CHECKSUM_MASK (0xFFFF00U)
AnnaBridge 171:3a7713b1edbc 12715 #define ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12716 #define ZLL_SAM_TABLE_SAM_CHECKSUM(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT)) & ZLL_SAM_TABLE_SAM_CHECKSUM_MASK)
AnnaBridge 171:3a7713b1edbc 12717 #define ZLL_SAM_TABLE_SAM_INDEX_INV_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 12718 #define ZLL_SAM_TABLE_SAM_INDEX_INV_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12719 #define ZLL_SAM_TABLE_SAM_INDEX_INV(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_INV_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_INV_MASK)
AnnaBridge 171:3a7713b1edbc 12720 #define ZLL_SAM_TABLE_SAM_INDEX_EN_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12721 #define ZLL_SAM_TABLE_SAM_INDEX_EN_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12722 #define ZLL_SAM_TABLE_SAM_INDEX_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_INDEX_EN_SHIFT)) & ZLL_SAM_TABLE_SAM_INDEX_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12723 #define ZLL_SAM_TABLE_ACK_FRM_PND_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 12724 #define ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 12725 #define ZLL_SAM_TABLE_ACK_FRM_PND(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT)) & ZLL_SAM_TABLE_ACK_FRM_PND_MASK)
AnnaBridge 171:3a7713b1edbc 12726 #define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 12727 #define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 12728 #define ZLL_SAM_TABLE_ACK_FRM_PND_CTRL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT)) & ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_MASK)
AnnaBridge 171:3a7713b1edbc 12729 #define ZLL_SAM_TABLE_FIND_FREE_IDX_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 12730 #define ZLL_SAM_TABLE_FIND_FREE_IDX_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 12731 #define ZLL_SAM_TABLE_FIND_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_FIND_FREE_IDX_SHIFT)) & ZLL_SAM_TABLE_FIND_FREE_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 12732 #define ZLL_SAM_TABLE_INVALIDATE_ALL_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 12733 #define ZLL_SAM_TABLE_INVALIDATE_ALL_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 12734 #define ZLL_SAM_TABLE_INVALIDATE_ALL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_INVALIDATE_ALL_SHIFT)) & ZLL_SAM_TABLE_INVALIDATE_ALL_MASK)
AnnaBridge 171:3a7713b1edbc 12735 #define ZLL_SAM_TABLE_SAM_BUSY_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12736 #define ZLL_SAM_TABLE_SAM_BUSY_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12737 #define ZLL_SAM_TABLE_SAM_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_TABLE_SAM_BUSY_SHIFT)) & ZLL_SAM_TABLE_SAM_BUSY_MASK)
AnnaBridge 171:3a7713b1edbc 12738
AnnaBridge 171:3a7713b1edbc 12739 /*! @name SAM_MATCH - SOURCE ADDRESS MANAGEMENT MATCH */
AnnaBridge 171:3a7713b1edbc 12740 #define ZLL_SAM_MATCH_SAP0_MATCH_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 12741 #define ZLL_SAM_MATCH_SAP0_MATCH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12742 #define ZLL_SAM_MATCH_SAP0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP0_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAP0_MATCH_MASK)
AnnaBridge 171:3a7713b1edbc 12743 #define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12744 #define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12745 #define ZLL_SAM_MATCH_SAP0_ADDR_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT)) & ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_MASK)
AnnaBridge 171:3a7713b1edbc 12746 #define ZLL_SAM_MATCH_SAA0_MATCH_MASK (0x7F00U)
AnnaBridge 171:3a7713b1edbc 12747 #define ZLL_SAM_MATCH_SAA0_MATCH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12748 #define ZLL_SAM_MATCH_SAA0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA0_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAA0_MATCH_MASK)
AnnaBridge 171:3a7713b1edbc 12749 #define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 12750 #define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 12751 #define ZLL_SAM_MATCH_SAA0_ADDR_ABSENT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT)) & ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_MASK)
AnnaBridge 171:3a7713b1edbc 12752 #define ZLL_SAM_MATCH_SAP1_MATCH_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 12753 #define ZLL_SAM_MATCH_SAP1_MATCH_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12754 #define ZLL_SAM_MATCH_SAP1_MATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP1_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAP1_MATCH_MASK)
AnnaBridge 171:3a7713b1edbc 12755 #define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 12756 #define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 12757 #define ZLL_SAM_MATCH_SAP1_ADDR_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT)) & ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_MASK)
AnnaBridge 171:3a7713b1edbc 12758 #define ZLL_SAM_MATCH_SAA1_MATCH_MASK (0x7F000000U)
AnnaBridge 171:3a7713b1edbc 12759 #define ZLL_SAM_MATCH_SAA1_MATCH_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12760 #define ZLL_SAM_MATCH_SAA1_MATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA1_MATCH_SHIFT)) & ZLL_SAM_MATCH_SAA1_MATCH_MASK)
AnnaBridge 171:3a7713b1edbc 12761 #define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 12762 #define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 12763 #define ZLL_SAM_MATCH_SAA1_ADDR_ABSENT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT)) & ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK)
AnnaBridge 171:3a7713b1edbc 12764
AnnaBridge 171:3a7713b1edbc 12765 /*! @name SAM_FREE_IDX - SAM FREE INDEX */
AnnaBridge 171:3a7713b1edbc 12766 #define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12767 #define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12768 #define ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 12769 #define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 12770 #define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12771 #define ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 12772 #define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 12773 #define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12774 #define ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 12775 #define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 12776 #define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12777 #define ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT)) & ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK)
AnnaBridge 171:3a7713b1edbc 12778
AnnaBridge 171:3a7713b1edbc 12779 /*! @name SEQ_CTRL_STS - SEQUENCE CONTROL AND STATUS */
AnnaBridge 171:3a7713b1edbc 12780 #define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12781 #define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12782 #define ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT)) & ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_MASK)
AnnaBridge 171:3a7713b1edbc 12783 #define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12784 #define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12785 #define ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT)) & ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK)
AnnaBridge 171:3a7713b1edbc 12786 #define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12787 #define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12788 #define ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT)) & ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_MASK)
AnnaBridge 171:3a7713b1edbc 12789 #define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12790 #define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12791 #define ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT)) & ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_MASK)
AnnaBridge 171:3a7713b1edbc 12792 #define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12793 #define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12794 #define ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT)) & ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_MASK)
AnnaBridge 171:3a7713b1edbc 12795 #define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12796 #define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12797 #define ZLL_SEQ_CTRL_STS_CONTINUOUS_EN(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT)) & ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12798 #define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 12799 #define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12800 #define ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT)) & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK)
AnnaBridge 171:3a7713b1edbc 12801 #define ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 12802 #define ZLL_SEQ_CTRL_STS_SEQ_IDLE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 12803 #define ZLL_SEQ_CTRL_STS_SEQ_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SEQ_IDLE_SHIFT)) & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 12804 #define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12805 #define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12806 #define ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_SHIFT)) & ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_MASK)
AnnaBridge 171:3a7713b1edbc 12807 #define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 12808 #define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 12809 #define ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_SHIFT)) & ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_MASK)
AnnaBridge 171:3a7713b1edbc 12810 #define ZLL_SEQ_CTRL_STS_RX_MODE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 12811 #define ZLL_SEQ_CTRL_STS_RX_MODE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 12812 #define ZLL_SEQ_CTRL_STS_RX_MODE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_RX_MODE_SHIFT)) & ZLL_SEQ_CTRL_STS_RX_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 12813 #define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 12814 #define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 12815 #define ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_SHIFT)) & ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_MASK)
AnnaBridge 171:3a7713b1edbc 12816 #define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 12817 #define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12818 #define ZLL_SEQ_CTRL_STS_SEQ_T_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_SHIFT)) & ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_MASK)
AnnaBridge 171:3a7713b1edbc 12819 #define ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 12820 #define ZLL_SEQ_CTRL_STS_SW_ABORTED_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12821 #define ZLL_SEQ_CTRL_STS_SW_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_SW_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK)
AnnaBridge 171:3a7713b1edbc 12822 #define ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12823 #define ZLL_SEQ_CTRL_STS_TC3_ABORTED_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12824 #define ZLL_SEQ_CTRL_STS_TC3_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_TC3_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK)
AnnaBridge 171:3a7713b1edbc 12825 #define ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 12826 #define ZLL_SEQ_CTRL_STS_PLL_ABORTED_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 12827 #define ZLL_SEQ_CTRL_STS_PLL_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_CTRL_STS_PLL_ABORTED_SHIFT)) & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK)
AnnaBridge 171:3a7713b1edbc 12828
AnnaBridge 171:3a7713b1edbc 12829 /*! @name ACKDELAY - ACK DELAY */
AnnaBridge 171:3a7713b1edbc 12830 #define ZLL_ACKDELAY_ACKDELAY_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 12831 #define ZLL_ACKDELAY_ACKDELAY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12832 #define ZLL_ACKDELAY_ACKDELAY(x) (((uint32_t)(((uint32_t)(x)) << ZLL_ACKDELAY_ACKDELAY_SHIFT)) & ZLL_ACKDELAY_ACKDELAY_MASK)
AnnaBridge 171:3a7713b1edbc 12833 #define ZLL_ACKDELAY_TXDELAY_MASK (0x3F00U)
AnnaBridge 171:3a7713b1edbc 12834 #define ZLL_ACKDELAY_TXDELAY_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12835 #define ZLL_ACKDELAY_TXDELAY(x) (((uint32_t)(((uint32_t)(x)) << ZLL_ACKDELAY_TXDELAY_SHIFT)) & ZLL_ACKDELAY_TXDELAY_MASK)
AnnaBridge 171:3a7713b1edbc 12836
AnnaBridge 171:3a7713b1edbc 12837 /*! @name FILTERFAIL_CODE - FILTER FAIL CODE */
AnnaBridge 171:3a7713b1edbc 12838 #define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 12839 #define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12840 #define ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_SHIFT)) & ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_MASK)
AnnaBridge 171:3a7713b1edbc 12841 #define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 12842 #define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 12843 #define ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT)) & ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 12844
AnnaBridge 171:3a7713b1edbc 12845 /*! @name RX_WTR_MARK - RECEIVE WATER MARK */
AnnaBridge 171:3a7713b1edbc 12846 #define ZLL_RX_WTR_MARK_RX_WTR_MARK_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12847 #define ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12848 #define ZLL_RX_WTR_MARK_RX_WTR_MARK(x) (((uint32_t)(((uint32_t)(x)) << ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT)) & ZLL_RX_WTR_MARK_RX_WTR_MARK_MASK)
AnnaBridge 171:3a7713b1edbc 12849
AnnaBridge 171:3a7713b1edbc 12850 /*! @name SLOT_PRELOAD - SLOT PRELOAD */
AnnaBridge 171:3a7713b1edbc 12851 #define ZLL_SLOT_PRELOAD_SLOT_PRELOAD_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12852 #define ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12853 #define ZLL_SLOT_PRELOAD_SLOT_PRELOAD(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT)) & ZLL_SLOT_PRELOAD_SLOT_PRELOAD_MASK)
AnnaBridge 171:3a7713b1edbc 12854
AnnaBridge 171:3a7713b1edbc 12855 /*! @name SEQ_STATE - 802.15.4 SEQUENCE STATE */
AnnaBridge 171:3a7713b1edbc 12856 #define ZLL_SEQ_STATE_SEQ_STATE_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 12857 #define ZLL_SEQ_STATE_SEQ_STATE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12858 #define ZLL_SEQ_STATE_SEQ_STATE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_SEQ_STATE_SHIFT)) & ZLL_SEQ_STATE_SEQ_STATE_MASK)
AnnaBridge 171:3a7713b1edbc 12859 #define ZLL_SEQ_STATE_PREAMBLE_DET_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 12860 #define ZLL_SEQ_STATE_PREAMBLE_DET_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12861 #define ZLL_SEQ_STATE_PREAMBLE_DET(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PREAMBLE_DET_SHIFT)) & ZLL_SEQ_STATE_PREAMBLE_DET_MASK)
AnnaBridge 171:3a7713b1edbc 12862 #define ZLL_SEQ_STATE_SFD_DET_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 12863 #define ZLL_SEQ_STATE_SFD_DET_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 12864 #define ZLL_SEQ_STATE_SFD_DET(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_SFD_DET_SHIFT)) & ZLL_SEQ_STATE_SFD_DET_MASK)
AnnaBridge 171:3a7713b1edbc 12865 #define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 12866 #define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 12867 #define ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_SHIFT)) & ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_MASK)
AnnaBridge 171:3a7713b1edbc 12868 #define ZLL_SEQ_STATE_CRCVALID_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 12869 #define ZLL_SEQ_STATE_CRCVALID_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 12870 #define ZLL_SEQ_STATE_CRCVALID(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_CRCVALID_SHIFT)) & ZLL_SEQ_STATE_CRCVALID_MASK)
AnnaBridge 171:3a7713b1edbc 12871 #define ZLL_SEQ_STATE_PLL_ABORT_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 12872 #define ZLL_SEQ_STATE_PLL_ABORT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12873 #define ZLL_SEQ_STATE_PLL_ABORT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PLL_ABORT_SHIFT)) & ZLL_SEQ_STATE_PLL_ABORT_MASK)
AnnaBridge 171:3a7713b1edbc 12874 #define ZLL_SEQ_STATE_PLL_ABORTED_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 12875 #define ZLL_SEQ_STATE_PLL_ABORTED_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 12876 #define ZLL_SEQ_STATE_PLL_ABORTED(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_PLL_ABORTED_SHIFT)) & ZLL_SEQ_STATE_PLL_ABORTED_MASK)
AnnaBridge 171:3a7713b1edbc 12877 #define ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 12878 #define ZLL_SEQ_STATE_RX_BYTE_COUNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12879 #define ZLL_SEQ_STATE_RX_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_RX_BYTE_COUNT_SHIFT)) & ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 12880 #define ZLL_SEQ_STATE_CCCA_BUSY_CNT_MASK (0x3F000000U)
AnnaBridge 171:3a7713b1edbc 12881 #define ZLL_SEQ_STATE_CCCA_BUSY_CNT_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12882 #define ZLL_SEQ_STATE_CCCA_BUSY_CNT(x) (((uint32_t)(((uint32_t)(x)) << ZLL_SEQ_STATE_CCCA_BUSY_CNT_SHIFT)) & ZLL_SEQ_STATE_CCCA_BUSY_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 12883
AnnaBridge 171:3a7713b1edbc 12884 /*! @name TMR_PRESCALE - TIMER PRESCALER */
AnnaBridge 171:3a7713b1edbc 12885 #define ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 12886 #define ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12887 #define ZLL_TMR_PRESCALE_TMR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT)) & ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK)
AnnaBridge 171:3a7713b1edbc 12888
AnnaBridge 171:3a7713b1edbc 12889 /*! @name LENIENCY_LSB - LENIENCY LSB */
AnnaBridge 171:3a7713b1edbc 12890 #define ZLL_LENIENCY_LSB_LENIENCY_LSB_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 12891 #define ZLL_LENIENCY_LSB_LENIENCY_LSB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12892 #define ZLL_LENIENCY_LSB_LENIENCY_LSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LENIENCY_LSB_LENIENCY_LSB_SHIFT)) & ZLL_LENIENCY_LSB_LENIENCY_LSB_MASK)
AnnaBridge 171:3a7713b1edbc 12893
AnnaBridge 171:3a7713b1edbc 12894 /*! @name LENIENCY_MSB - LENIENCY MSB */
AnnaBridge 171:3a7713b1edbc 12895 #define ZLL_LENIENCY_MSB_LENIENCY_MSB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12896 #define ZLL_LENIENCY_MSB_LENIENCY_MSB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12897 #define ZLL_LENIENCY_MSB_LENIENCY_MSB(x) (((uint32_t)(((uint32_t)(x)) << ZLL_LENIENCY_MSB_LENIENCY_MSB_SHIFT)) & ZLL_LENIENCY_MSB_LENIENCY_MSB_MASK)
AnnaBridge 171:3a7713b1edbc 12898
AnnaBridge 171:3a7713b1edbc 12899 /*! @name PART_ID - PART ID */
AnnaBridge 171:3a7713b1edbc 12900 #define ZLL_PART_ID_PART_ID_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12901 #define ZLL_PART_ID_PART_ID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12902 #define ZLL_PART_ID_PART_ID(x) (((uint32_t)(((uint32_t)(x)) << ZLL_PART_ID_PART_ID_SHIFT)) & ZLL_PART_ID_PART_ID_MASK)
AnnaBridge 171:3a7713b1edbc 12903
AnnaBridge 171:3a7713b1edbc 12904 /*! @name PKT_BUFFER_TX - Packet Buffer TX */
AnnaBridge 171:3a7713b1edbc 12905 #define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12906 #define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12907 #define ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX(x) (((uint16_t)(((uint16_t)(x)) << ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_SHIFT)) & ZLL_PKT_BUFFER_TX_PKT_BUFFER_TX_MASK)
AnnaBridge 171:3a7713b1edbc 12908
AnnaBridge 171:3a7713b1edbc 12909 /* The count of ZLL_PKT_BUFFER_TX */
AnnaBridge 171:3a7713b1edbc 12910 #define ZLL_PKT_BUFFER_TX_COUNT (64U)
AnnaBridge 171:3a7713b1edbc 12911
AnnaBridge 171:3a7713b1edbc 12912 /*! @name PKT_BUFFER_RX - Packet Buffer RX */
AnnaBridge 171:3a7713b1edbc 12913 #define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12914 #define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12915 #define ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX(x) (((uint16_t)(((uint16_t)(x)) << ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_SHIFT)) & ZLL_PKT_BUFFER_RX_PKT_BUFFER_RX_MASK)
AnnaBridge 171:3a7713b1edbc 12916
AnnaBridge 171:3a7713b1edbc 12917 /* The count of ZLL_PKT_BUFFER_RX */
AnnaBridge 171:3a7713b1edbc 12918 #define ZLL_PKT_BUFFER_RX_COUNT (64U)
AnnaBridge 171:3a7713b1edbc 12919
AnnaBridge 171:3a7713b1edbc 12920
AnnaBridge 171:3a7713b1edbc 12921 /*!
AnnaBridge 171:3a7713b1edbc 12922 * @}
AnnaBridge 171:3a7713b1edbc 12923 */ /* end of group ZLL_Register_Masks */
AnnaBridge 171:3a7713b1edbc 12924
AnnaBridge 171:3a7713b1edbc 12925
AnnaBridge 171:3a7713b1edbc 12926 /* ZLL - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 12927 /** Peripheral ZLL base address */
AnnaBridge 171:3a7713b1edbc 12928 #define ZLL_BASE (0x4005D000u)
AnnaBridge 171:3a7713b1edbc 12929 /** Peripheral ZLL base pointer */
AnnaBridge 171:3a7713b1edbc 12930 #define ZLL ((ZLL_Type *)ZLL_BASE)
AnnaBridge 171:3a7713b1edbc 12931 /** Array initializer of ZLL peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 12932 #define ZLL_BASE_ADDRS { ZLL_BASE }
AnnaBridge 171:3a7713b1edbc 12933 /** Array initializer of ZLL peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 12934 #define ZLL_BASE_PTRS { ZLL }
AnnaBridge 171:3a7713b1edbc 12935
AnnaBridge 171:3a7713b1edbc 12936 /*!
AnnaBridge 171:3a7713b1edbc 12937 * @}
AnnaBridge 171:3a7713b1edbc 12938 */ /* end of group ZLL_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 12939
AnnaBridge 171:3a7713b1edbc 12940
AnnaBridge 171:3a7713b1edbc 12941 /*
AnnaBridge 171:3a7713b1edbc 12942 ** End of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 12943 */
AnnaBridge 171:3a7713b1edbc 12944
AnnaBridge 171:3a7713b1edbc 12945 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 12946 #pragma pop
AnnaBridge 171:3a7713b1edbc 12947 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 12948 /* leave anonymous unions enabled */
AnnaBridge 171:3a7713b1edbc 12949 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 12950 #pragma language=default
AnnaBridge 171:3a7713b1edbc 12951 #else
AnnaBridge 171:3a7713b1edbc 12952 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 12953 #endif
AnnaBridge 171:3a7713b1edbc 12954
AnnaBridge 171:3a7713b1edbc 12955 /*!
AnnaBridge 171:3a7713b1edbc 12956 * @}
AnnaBridge 171:3a7713b1edbc 12957 */ /* end of group Peripheral_access_layer */
AnnaBridge 171:3a7713b1edbc 12958
AnnaBridge 171:3a7713b1edbc 12959
AnnaBridge 171:3a7713b1edbc 12960 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12961 -- SDK Compatibility
AnnaBridge 171:3a7713b1edbc 12962 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12963
AnnaBridge 171:3a7713b1edbc 12964 /*!
AnnaBridge 171:3a7713b1edbc 12965 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
AnnaBridge 171:3a7713b1edbc 12966 * @{
AnnaBridge 171:3a7713b1edbc 12967 */
AnnaBridge 171:3a7713b1edbc 12968
AnnaBridge 171:3a7713b1edbc 12969 #define DSPI0 SPI0
AnnaBridge 171:3a7713b1edbc 12970 #define DSPI1 SPI1
AnnaBridge 171:3a7713b1edbc 12971
AnnaBridge 171:3a7713b1edbc 12972 /*!
AnnaBridge 171:3a7713b1edbc 12973 * @}
AnnaBridge 171:3a7713b1edbc 12974 */ /* end of group SDK_Compatibility_Symbols */
AnnaBridge 171:3a7713b1edbc 12975
AnnaBridge 171:3a7713b1edbc 12976
AnnaBridge 171:3a7713b1edbc 12977 #endif /* _MKW41Z4_H_ */
AnnaBridge 171:3a7713b1edbc 12978