mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_KL43Z/TOOLCHAIN_GCC_ARM/fsl_slcd.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 3 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 6 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 9 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 13 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 171:3a7713b1edbc 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 17 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 29 */
AnnaBridge 171:3a7713b1edbc 30
AnnaBridge 171:3a7713b1edbc 31 #ifndef _FSL_SLCD_H_
AnnaBridge 171:3a7713b1edbc 32 #define _FSL_SLCD_H_
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #include "fsl_common.h"
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /*!
AnnaBridge 171:3a7713b1edbc 37 * @addtogroup slcd
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 */
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 /*! @file */
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 44 * Definitions
AnnaBridge 171:3a7713b1edbc 45 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 48 /*@{*/
AnnaBridge 171:3a7713b1edbc 49 /*! @brief SLCD driver version 2.0.0. */
AnnaBridge 171:3a7713b1edbc 50 #define FSL_SLCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
AnnaBridge 171:3a7713b1edbc 51 /*@}*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /*! @brief SLCD power supply option. */
AnnaBridge 171:3a7713b1edbc 54 typedef enum _slcd_power_supply_option
AnnaBridge 171:3a7713b1edbc 55 {
AnnaBridge 171:3a7713b1edbc 56 kSLCD_InternalVll3UseChargePump =
AnnaBridge 171:3a7713b1edbc 57 2U, /*!< VLL3 connected to VDD internally, charge pump is used to generate VLL1 and VLL2. */
AnnaBridge 171:3a7713b1edbc 58 kSLCD_ExternalVll3UseResistorBiasNetwork =
AnnaBridge 171:3a7713b1edbc 59 4U, /*!< VLL3 is driven externally and resistor bias network is used to generate VLL1 and VLL2. */
AnnaBridge 171:3a7713b1edbc 60 kSLCD_ExteranlVll3UseChargePump =
AnnaBridge 171:3a7713b1edbc 61 6U, /*!< VLL3 is driven externally and charge pump is used to generate VLL1 and VLL2. */
AnnaBridge 171:3a7713b1edbc 62 kSLCD_InternalVll1UseChargePump =
AnnaBridge 171:3a7713b1edbc 63 7U /*!< VIREG is connected to VLL1 internally and charge pump is used to generate VLL2 and VLL3. */
AnnaBridge 171:3a7713b1edbc 64 } slcd_power_supply_option_t;
AnnaBridge 171:3a7713b1edbc 65
AnnaBridge 171:3a7713b1edbc 66 /*! @brief SLCD regulated voltage trim parameter, be used to meet the desired contrast. */
AnnaBridge 171:3a7713b1edbc 67 typedef enum _slcd_regulated_voltage_trim
AnnaBridge 171:3a7713b1edbc 68 {
AnnaBridge 171:3a7713b1edbc 69 kSLCD_RegulatedVolatgeTrim00 = 0U, /*!< Increase the voltage to 0.91 V. */
AnnaBridge 171:3a7713b1edbc 70 kSLCD_RegulatedVolatgeTrim01, /*!< Increase the voltage to 1.01 V. */
AnnaBridge 171:3a7713b1edbc 71 kSLCD_RegulatedVolatgeTrim02, /*!< Increase the voltage to 0.96 V. */
AnnaBridge 171:3a7713b1edbc 72 kSLCD_RegulatedVolatgeTrim03, /*!< Increase the voltage to 1.06 V. */
AnnaBridge 171:3a7713b1edbc 73 kSLCD_RegulatedVolatgeTrim04, /*!< Increase the voltage to 0.93 V. */
AnnaBridge 171:3a7713b1edbc 74 kSLCD_RegulatedVolatgeTrim05, /*!< Increase the voltage to 1.02 V. */
AnnaBridge 171:3a7713b1edbc 75 kSLCD_RegulatedVolatgeTrim06, /*!< Increase the voltage to 0.98 V. */
AnnaBridge 171:3a7713b1edbc 76 kSLCD_RegulatedVolatgeTrim07, /*!< Increase the voltage to 1.08 V. */
AnnaBridge 171:3a7713b1edbc 77 kSLCD_RegulatedVolatgeTrim08, /*!< Increase the voltage to 0.92 V. */
AnnaBridge 171:3a7713b1edbc 78 kSLCD_RegulatedVolatgeTrim09, /*!< Increase the voltage to 1.02 V. */
AnnaBridge 171:3a7713b1edbc 79 kSLCD_RegulatedVolatgeTrim10, /*!< Increase the voltage to 0.97 V. */
AnnaBridge 171:3a7713b1edbc 80 kSLCD_RegulatedVolatgeTrim11, /*!< Increase the voltage to 1.07 V. */
AnnaBridge 171:3a7713b1edbc 81 kSLCD_RegulatedVolatgeTrim12, /*!< Increase the voltage to 0.94 V. */
AnnaBridge 171:3a7713b1edbc 82 kSLCD_RegulatedVolatgeTrim13, /*!< Increase the voltage to 1.05 V. */
AnnaBridge 171:3a7713b1edbc 83 kSLCD_RegulatedVolatgeTrim14, /*!< Increase the voltage to 0.99 V. */
AnnaBridge 171:3a7713b1edbc 84 kSLCD_RegulatedVolatgeTrim15 /*!< Increase the voltage to 1.09 V. */
AnnaBridge 171:3a7713b1edbc 85 } slcd_regulated_voltage_trim_t;
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 /*! @brief SLCD load adjust to handle different LCD glass capacitance or
AnnaBridge 171:3a7713b1edbc 88 * configure the LCD charge pump clock source.
AnnaBridge 171:3a7713b1edbc 89 * Adjust the LCD glass capacitance if resistor bias network is enabled:
AnnaBridge 171:3a7713b1edbc 90 * kSLCD_LowLoadOrFastestClkSrc - Low load (LCD glass capacitance 2000pF or lower.
AnnaBridge 171:3a7713b1edbc 91 * LCD or GPIO function can be used on VLL1,VLL2,Vcap1 and Vcap2 pins)
AnnaBridge 171:3a7713b1edbc 92 * kSLCD_LowLoadOrIntermediateClkSrc - low load (LCD glass capacitance 2000pF or lower.
AnnaBridge 171:3a7713b1edbc 93 * LCD or GPIO function can be used on VLL1,VLL2,Vcap1 and Vcap2 pins)
AnnaBridge 171:3a7713b1edbc 94 * kSLCD_HighLoadOrIntermediateClkSrc - high load (LCD glass capacitance 8000pF or lower.
AnnaBridge 171:3a7713b1edbc 95 * LCD or GPIO function can be used on Vcap1 and Vcap2 pins)
AnnaBridge 171:3a7713b1edbc 96 * kSLCD_HighLoadOrSlowestClkSrc - high load (LCD glass capacitance 8000pF or lower
AnnaBridge 171:3a7713b1edbc 97 * LCD or GPIO function can be used on Vcap1 and Vcap2 pins)
AnnaBridge 171:3a7713b1edbc 98 * Adjust clock for charge pump if charge pump is enabled:
AnnaBridge 171:3a7713b1edbc 99 * kSLCD_LowLoadOrFastestClkSrc - Fasten clock source (LCD glass capacitance
AnnaBridge 171:3a7713b1edbc 100 * 8000pF or 4000pF or lower if Fast Frame Rate is set)
AnnaBridge 171:3a7713b1edbc 101 * kSLCD_LowLoadOrIntermediateClkSrc - Intermediate clock source (LCD glass
AnnaBridge 171:3a7713b1edbc 102 * capacitance 4000pF or 2000pF or lower if Fast Frame Rate is set)
AnnaBridge 171:3a7713b1edbc 103 * kSLCD_HighLoadOrIntermediateClkSrc - Intermediate clock source (LCD glass
AnnaBridge 171:3a7713b1edbc 104 * capacitance 2000pF or 1000pF or lower if Fast Frame Rate is set)
AnnaBridge 171:3a7713b1edbc 105 * kSLCD_HighLoadOrSlowestClkSrc - slowest clock source (LCD glass capacitance
AnnaBridge 171:3a7713b1edbc 106 * 1000pF or 500pF or lower if Fast Frame Rate is set)
AnnaBridge 171:3a7713b1edbc 107 */
AnnaBridge 171:3a7713b1edbc 108 typedef enum _slcd_load_adjust
AnnaBridge 171:3a7713b1edbc 109 {
AnnaBridge 171:3a7713b1edbc 110 kSLCD_LowLoadOrFastestClkSrc = 0U, /*!< Adjust in low load or selects fastest clock. */
AnnaBridge 171:3a7713b1edbc 111 kSLCD_LowLoadOrIntermediateClkSrc, /*!< Adjust in low load or selects intermediate clock. */
AnnaBridge 171:3a7713b1edbc 112 kSLCD_HighLoadOrIntermediateClkSrc, /*!< Adjust in high load or selects intermediate clock. */
AnnaBridge 171:3a7713b1edbc 113 kSLCD_HighLoadOrSlowestClkSrc /*!< Adjust in high load or selects slowest clock. */
AnnaBridge 171:3a7713b1edbc 114 } slcd_load_adjust_t;
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 /*! @brief SLCD clock source. */
AnnaBridge 171:3a7713b1edbc 117 typedef enum _slcd_clock_src
AnnaBridge 171:3a7713b1edbc 118 {
AnnaBridge 171:3a7713b1edbc 119 kSLCD_DefaultClk = 0U, /*!< Select default clock ERCLK32K. */
AnnaBridge 171:3a7713b1edbc 120 kSLCD_AlternateClk1 = 1U, /*!< Select alternate clock source 1 : MCGIRCLK. */
AnnaBridge 171:3a7713b1edbc 121 #if FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE
AnnaBridge 171:3a7713b1edbc 122 kSLCD_AlternateClk2 = 3U /*!< Select alternate clock source 2 : OSCERCLK. */
AnnaBridge 171:3a7713b1edbc 123 #endif /* FSL_FEATURE_SLCD_HAS_MULTI_ALTERNATE_CLOCK_SOURCE */
AnnaBridge 171:3a7713b1edbc 124 } slcd_clock_src_t;
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 /*! @brief SLCD alternate clock divider. */
AnnaBridge 171:3a7713b1edbc 127 typedef enum _slcd_alt_clock_div
AnnaBridge 171:3a7713b1edbc 128 {
AnnaBridge 171:3a7713b1edbc 129 kSLCD_AltClkDivFactor1 = 0U, /*!< No divide for alternate clock. */
AnnaBridge 171:3a7713b1edbc 130 kSLCD_AltClkDivFactor64, /*!< Divide alternate clock with factor 64. */
AnnaBridge 171:3a7713b1edbc 131 kSLCD_AltClkDivFactor256, /*!< Divide alternate clock with factor 256. */
AnnaBridge 171:3a7713b1edbc 132 kSLCD_AltClkDivFactor512 /*!< Divide alternate clock with factor 512. */
AnnaBridge 171:3a7713b1edbc 133 } slcd_alt_clock_div_t;
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 /*! @brief SLCD clock prescaler to generate frame frequency. */
AnnaBridge 171:3a7713b1edbc 136 typedef enum _slcd_clock_prescaler
AnnaBridge 171:3a7713b1edbc 137 {
AnnaBridge 171:3a7713b1edbc 138 kSLCD_ClkPrescaler00 = 0U, /*!< Prescaler 0. */
AnnaBridge 171:3a7713b1edbc 139 kSLCD_ClkPrescaler01, /*!< Prescaler 1. */
AnnaBridge 171:3a7713b1edbc 140 kSLCD_ClkPrescaler02, /*!< Prescaler 2. */
AnnaBridge 171:3a7713b1edbc 141 kSLCD_ClkPrescaler03, /*!< Prescaler 3. */
AnnaBridge 171:3a7713b1edbc 142 kSLCD_ClkPrescaler04, /*!< Prescaler 4. */
AnnaBridge 171:3a7713b1edbc 143 kSLCD_ClkPrescaler05, /*!< Prescaler 5. */
AnnaBridge 171:3a7713b1edbc 144 kSLCD_ClkPrescaler06, /*!< Prescaler 6. */
AnnaBridge 171:3a7713b1edbc 145 kSLCD_ClkPrescaler07 /*!< Prescaler 7. */
AnnaBridge 171:3a7713b1edbc 146 } slcd_clock_prescaler_t;
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 /*! @brief SLCD duty cycle. */
AnnaBridge 171:3a7713b1edbc 149 typedef enum _slcd_duty_cycle
AnnaBridge 171:3a7713b1edbc 150 {
AnnaBridge 171:3a7713b1edbc 151 kSLCD_1Div1DutyCycle = 0U, /*!< LCD use 1 BP 1/1 duty cycle. */
AnnaBridge 171:3a7713b1edbc 152 kSLCD_1Div2DutyCycle, /*!< LCD use 2 BP 1/2 duty cycle. */
AnnaBridge 171:3a7713b1edbc 153 kSLCD_1Div3DutyCycle, /*!< LCD use 3 BP 1/3 duty cycle. */
AnnaBridge 171:3a7713b1edbc 154 kSLCD_1Div4DutyCycle, /*!< LCD use 4 BP 1/4 duty cycle. */
AnnaBridge 171:3a7713b1edbc 155 kSLCD_1Div5DutyCycle, /*!< LCD use 5 BP 1/5 duty cycle. */
AnnaBridge 171:3a7713b1edbc 156 kSLCD_1Div6DutyCycle, /*!< LCD use 6 BP 1/6 duty cycle. */
AnnaBridge 171:3a7713b1edbc 157 kSLCD_1Div7DutyCycle, /*!< LCD use 7 BP 1/7 duty cycle. */
AnnaBridge 171:3a7713b1edbc 158 kSLCD_1Div8DutyCycle /*!< LCD use 8 BP 1/8 duty cycle. */
AnnaBridge 171:3a7713b1edbc 159 } slcd_duty_cycle_t;
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 /*! @brief SLCD segment phase type. */
AnnaBridge 171:3a7713b1edbc 162 typedef enum _slcd_phase_type
AnnaBridge 171:3a7713b1edbc 163 {
AnnaBridge 171:3a7713b1edbc 164 kSLCD_NoPhaseActivate = 0x00U, /*!< LCD wareform no phase activates. */
AnnaBridge 171:3a7713b1edbc 165 kSLCD_PhaseAActivate = 0x01U, /*!< LCD waveform phase A activates. */
AnnaBridge 171:3a7713b1edbc 166 kSLCD_PhaseBActivate = 0x02U, /*!< LCD waveform phase B activates. */
AnnaBridge 171:3a7713b1edbc 167 kSLCD_PhaseCActivate = 0x04U, /*!< LCD waveform phase C activates. */
AnnaBridge 171:3a7713b1edbc 168 kSLCD_PhaseDActivate = 0x08U, /*!< LCD waveform phase D activates. */
AnnaBridge 171:3a7713b1edbc 169 kSLCD_PhaseEActivate = 0x10U, /*!< LCD waveform phase E activates. */
AnnaBridge 171:3a7713b1edbc 170 kSLCD_PhaseFActivate = 0x20U, /*!< LCD waveform phase F activates. */
AnnaBridge 171:3a7713b1edbc 171 kSLCD_PhaseGActivate = 0x40U, /*!< LCD waveform phase G activates. */
AnnaBridge 171:3a7713b1edbc 172 kSLCD_PhaseHActivate = 0x80U /*!< LCD waveform phase H activates. */
AnnaBridge 171:3a7713b1edbc 173 } slcd_phase_type_t;
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 /*! @brief SLCD segment phase bit index. */
AnnaBridge 171:3a7713b1edbc 176 typedef enum _slcd_phase_index
AnnaBridge 171:3a7713b1edbc 177 {
AnnaBridge 171:3a7713b1edbc 178 kSLCD_PhaseAIndex = 0x0U, /*!< LCD phase A bit index. */
AnnaBridge 171:3a7713b1edbc 179 kSLCD_PhaseBIndex = 0x1U, /*!< LCD phase B bit index. */
AnnaBridge 171:3a7713b1edbc 180 kSLCD_PhaseCIndex = 0x2U, /*!< LCD phase C bit index. */
AnnaBridge 171:3a7713b1edbc 181 kSLCD_PhaseDIndex = 0x3U, /*!< LCD phase D bit index. */
AnnaBridge 171:3a7713b1edbc 182 kSLCD_PhaseEIndex = 0x4U, /*!< LCD phase E bit index. */
AnnaBridge 171:3a7713b1edbc 183 kSLCD_PhaseFIndex = 0x5U, /*!< LCD phase F bit index. */
AnnaBridge 171:3a7713b1edbc 184 kSLCD_PhaseGIndex = 0x6U, /*!< LCD phase G bit index. */
AnnaBridge 171:3a7713b1edbc 185 kSLCD_PhaseHIndex = 0x7U /*!< LCD phase H bit index. */
AnnaBridge 171:3a7713b1edbc 186 } slcd_phase_index_t;
AnnaBridge 171:3a7713b1edbc 187
AnnaBridge 171:3a7713b1edbc 188 /*! @brief SLCD display mode. */
AnnaBridge 171:3a7713b1edbc 189 typedef enum _slcd_display_mode
AnnaBridge 171:3a7713b1edbc 190 {
AnnaBridge 171:3a7713b1edbc 191 kSLCD_NormalMode = 0U, /*!< LCD Normal display mode. */
AnnaBridge 171:3a7713b1edbc 192 kSLCD_AlternateMode, /*!< LCD Alternate display mode. For four back planes or less. */
AnnaBridge 171:3a7713b1edbc 193 kSLCD_BlankMode /*!< LCD Blank display mode. */
AnnaBridge 171:3a7713b1edbc 194 } slcd_display_mode_t;
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 /*! @brief SLCD blink mode. */
AnnaBridge 171:3a7713b1edbc 197 typedef enum _slcd_blink_mode
AnnaBridge 171:3a7713b1edbc 198 {
AnnaBridge 171:3a7713b1edbc 199 kSLCD_BlankDisplayBlink = 0U, /*!< Display blank during the blink period. */
AnnaBridge 171:3a7713b1edbc 200 kSLCD_AltDisplayBlink /*!< Display alternate display during the blink period if duty cycle is lower than 5. */
AnnaBridge 171:3a7713b1edbc 201 } slcd_blink_mode_t;
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 /*! @brief SLCD blink rate. */
AnnaBridge 171:3a7713b1edbc 204 typedef enum _slcd_blink_rate
AnnaBridge 171:3a7713b1edbc 205 {
AnnaBridge 171:3a7713b1edbc 206 kSLCD_BlinkRate00 = 0U, /*!< SLCD blink rate is LCD clock/((2^12)). */
AnnaBridge 171:3a7713b1edbc 207 kSLCD_BlinkRate01, /*!< SLCD blink rate is LCD clock/((2^13)). */
AnnaBridge 171:3a7713b1edbc 208 kSLCD_BlinkRate02, /*!< SLCD blink rate is LCD clock/((2^14)). */
AnnaBridge 171:3a7713b1edbc 209 kSLCD_BlinkRate03, /*!< SLCD blink rate is LCD clock/((2^15)). */
AnnaBridge 171:3a7713b1edbc 210 kSLCD_BlinkRate04, /*!< SLCD blink rate is LCD clock/((2^16)). */
AnnaBridge 171:3a7713b1edbc 211 kSLCD_BlinkRate05, /*!< SLCD blink rate is LCD clock/((2^17)). */
AnnaBridge 171:3a7713b1edbc 212 kSLCD_BlinkRate06, /*!< SLCD blink rate is LCD clock/((2^18)). */
AnnaBridge 171:3a7713b1edbc 213 kSLCD_BlinkRate07 /*!< SLCD blink rate is LCD clock/((2^19)). */
AnnaBridge 171:3a7713b1edbc 214 } slcd_blink_rate_t;
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 /*! @brief SLCD fault detect clock prescaler. */
AnnaBridge 171:3a7713b1edbc 217 typedef enum _slcd_fault_detect_clock_prescaler
AnnaBridge 171:3a7713b1edbc 218 {
AnnaBridge 171:3a7713b1edbc 219 kSLCD_FaultSampleFreqDivider1 = 0U, /*!< Fault detect sample clock frequency is 1/1 bus clock. */
AnnaBridge 171:3a7713b1edbc 220 kSLCD_FaultSampleFreqDivider2, /*!< Fault detect sample clock frequency is 1/2 bus clock. */
AnnaBridge 171:3a7713b1edbc 221 kSLCD_FaultSampleFreqDivider4, /*!< Fault detect sample clock frequency is 1/4 bus clock. */
AnnaBridge 171:3a7713b1edbc 222 kSLCD_FaultSampleFreqDivider8, /*!< Fault detect sample clock frequency is 1/8 bus clock. */
AnnaBridge 171:3a7713b1edbc 223 kSLCD_FaultSampleFreqDivider16, /*!< Fault detect sample clock frequency is 1/16 bus clock. */
AnnaBridge 171:3a7713b1edbc 224 kSLCD_FaultSampleFreqDivider32, /*!< Fault detect sample clock frequency is 1/32 bus clock. */
AnnaBridge 171:3a7713b1edbc 225 kSLCD_FaultSampleFreqDivider64, /*!< Fault detect sample clock frequency is 1/64 bus clock. */
AnnaBridge 171:3a7713b1edbc 226 kSLCD_FaultSampleFreqDivider128 /*!< Fault detect sample clock frequency is 1/128 bus clock. */
AnnaBridge 171:3a7713b1edbc 227 } slcd_fault_detect_clock_prescaler_t;
AnnaBridge 171:3a7713b1edbc 228
AnnaBridge 171:3a7713b1edbc 229 /*! @brief SLCD fault detect sample window width. */
AnnaBridge 171:3a7713b1edbc 230 typedef enum _slcd_fault_detect_sample_window_width
AnnaBridge 171:3a7713b1edbc 231 {
AnnaBridge 171:3a7713b1edbc 232 kSLCD_FaultDetectWindowWidth4SampleClk = 0U, /*!< Sample window width is 4 sample clock cycles. */
AnnaBridge 171:3a7713b1edbc 233 kSLCD_FaultDetectWindowWidth8SampleClk, /*!< Sample window width is 8 sample clock cycles. */
AnnaBridge 171:3a7713b1edbc 234 kSLCD_FaultDetectWindowWidth16SampleClk, /*!< Sample window width is 16 sample clock cycles. */
AnnaBridge 171:3a7713b1edbc 235 kSLCD_FaultDetectWindowWidth32SampleClk, /*!< Sample window width is 32 sample clock cycles. */
AnnaBridge 171:3a7713b1edbc 236 kSLCD_FaultDetectWindowWidth64SampleClk, /*!< Sample window width is 64 sample clock cycles. */
AnnaBridge 171:3a7713b1edbc 237 kSLCD_FaultDetectWindowWidth128SampleClk, /*!< Sample window width is 128 sample clock cycles. */
AnnaBridge 171:3a7713b1edbc 238 kSLCD_FaultDetectWindowWidth256SampleClk, /*!< Sample window width is 256 sample clock cycles. */
AnnaBridge 171:3a7713b1edbc 239 kSLCD_FaultDetectWindowWidth512SampleClk /*!< Sample window width is 512 sample clock cycles. */
AnnaBridge 171:3a7713b1edbc 240 } slcd_fault_detect_sample_window_width_t;
AnnaBridge 171:3a7713b1edbc 241
AnnaBridge 171:3a7713b1edbc 242 /*! @brief SLCD interrupt source. */
AnnaBridge 171:3a7713b1edbc 243 typedef enum _slcd_interrupt_enable
AnnaBridge 171:3a7713b1edbc 244 {
AnnaBridge 171:3a7713b1edbc 245 kSLCD_FaultDetectCompleteInterrupt = 1U, /*!< SLCD fault detection complete interrupt source. */
AnnaBridge 171:3a7713b1edbc 246 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
AnnaBridge 171:3a7713b1edbc 247 kSLCD_FrameFreqInterrupt = 2U /*!< SLCD frame frequency interrupt source. Not available in all low-power modes. */
AnnaBridge 171:3a7713b1edbc 248 #endif /* FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT */
AnnaBridge 171:3a7713b1edbc 249 } slcd_interrupt_enable_t;
AnnaBridge 171:3a7713b1edbc 250
AnnaBridge 171:3a7713b1edbc 251 /*! @brief SLCD behavior in low power mode. */
AnnaBridge 171:3a7713b1edbc 252 typedef enum _slcd_lowpower_behavior
AnnaBridge 171:3a7713b1edbc 253 {
AnnaBridge 171:3a7713b1edbc 254 kSLCD_EnabledInWaitStop = 0, /*!< SLCD works in wait and stop mode. */
AnnaBridge 171:3a7713b1edbc 255 kSLCD_EnabledInWaitOnly, /*!< SLCD works in wait mode and is disabled in stop mode. */
AnnaBridge 171:3a7713b1edbc 256 kSLCD_EnabledInStopOnly, /*!< SLCD works in stop mode and is disabled in wait mode. */
AnnaBridge 171:3a7713b1edbc 257 kSLCD_DisabledInWaitStop /*!< SLCD is disabled in stop mode and wait mode. */
AnnaBridge 171:3a7713b1edbc 258 } slcd_lowpower_behavior;
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260 /*! @brief SLCD fault frame detection configure structure. */
AnnaBridge 171:3a7713b1edbc 261 typedef struct _slcd_fault_detect_config
AnnaBridge 171:3a7713b1edbc 262 {
AnnaBridge 171:3a7713b1edbc 263 bool faultDetectIntEnable; /*!< Fault frame detection interrupt enable flag.*/
AnnaBridge 171:3a7713b1edbc 264 bool faultDetectBackPlaneEnable; /*!< True means the pin id fault detected is back plane otherwise front plane. */
AnnaBridge 171:3a7713b1edbc 265 uint8_t faultDetectPinIndex; /*!< Fault detected pin id from 0 to 63. */
AnnaBridge 171:3a7713b1edbc 266 slcd_fault_detect_clock_prescaler_t faultPrescaler; /*!< Fault detect clock prescaler. */
AnnaBridge 171:3a7713b1edbc 267 slcd_fault_detect_sample_window_width_t width; /*!< Fault detect sample window width. */
AnnaBridge 171:3a7713b1edbc 268 } slcd_fault_detect_config_t;
AnnaBridge 171:3a7713b1edbc 269
AnnaBridge 171:3a7713b1edbc 270 /*! @brief SLCD clock configure structure. */
AnnaBridge 171:3a7713b1edbc 271 typedef struct _slcd_clock_config
AnnaBridge 171:3a7713b1edbc 272 {
AnnaBridge 171:3a7713b1edbc 273 slcd_clock_src_t clkSource; /*!< Clock source. "slcd_clock_src_t" is recommended to be used.
AnnaBridge 171:3a7713b1edbc 274 The SLCD is optimized to operate using a 32.768kHz clock input. */
AnnaBridge 171:3a7713b1edbc 275 slcd_alt_clock_div_t
AnnaBridge 171:3a7713b1edbc 276 altClkDivider; /*!< The divider to divide the alternate clock used for alternate clock source. */
AnnaBridge 171:3a7713b1edbc 277 slcd_clock_prescaler_t clkPrescaler; /*!< Clock prescaler. */
AnnaBridge 171:3a7713b1edbc 278 #if FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE
AnnaBridge 171:3a7713b1edbc 279 bool fastFrameRateEnable; /*!< Fast frame rate enable flag. */
AnnaBridge 171:3a7713b1edbc 280 #endif /* FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE */
AnnaBridge 171:3a7713b1edbc 281 } slcd_clock_config_t;
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 /*! @brief SLCD configure structure. */
AnnaBridge 171:3a7713b1edbc 284 typedef struct _slcd_config
AnnaBridge 171:3a7713b1edbc 285 {
AnnaBridge 171:3a7713b1edbc 286 slcd_power_supply_option_t powerSupply; /*!< Power supply option. */
AnnaBridge 171:3a7713b1edbc 287 slcd_regulated_voltage_trim_t voltageTrim; /*!< Regulated voltage trim used for the internal regulator VIREG to
AnnaBridge 171:3a7713b1edbc 288 adjust to facilitate contrast control. */
AnnaBridge 171:3a7713b1edbc 289 slcd_clock_config_t *clkConfig; /*!< Clock configure. */
AnnaBridge 171:3a7713b1edbc 290 slcd_display_mode_t displayMode; /*!< SLCD display mode. */
AnnaBridge 171:3a7713b1edbc 291 slcd_load_adjust_t loadAdjust; /*!< Load adjust to handle glass capacitance. */
AnnaBridge 171:3a7713b1edbc 292 slcd_duty_cycle_t dutyCycle; /*!< Duty cycle. */
AnnaBridge 171:3a7713b1edbc 293 slcd_lowpower_behavior lowPowerBehavior; /*!< SLCD behavior in low power mode. */
AnnaBridge 171:3a7713b1edbc 294 #if FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT
AnnaBridge 171:3a7713b1edbc 295 bool frameFreqIntEnable; /*!< Frame frequency interrupt enable flag.*/
AnnaBridge 171:3a7713b1edbc 296 #endif /* FSL_FEATURE_SLCD_HAS_FAST_FRAME_RATE */
AnnaBridge 171:3a7713b1edbc 297 uint32_t slcdLowPinEnabled; /*!< Setting enabled SLCD pin 0 ~ pin 31. Setting bit n to 1 means enable pin n. */
AnnaBridge 171:3a7713b1edbc 298 uint32_t
AnnaBridge 171:3a7713b1edbc 299 slcdHighPinEnabled; /*!< Setting enabled SLCD pin 32 ~ pin 63. Setting bit n to 1 means enable pin (n + 32). */
AnnaBridge 171:3a7713b1edbc 300 uint32_t backPlaneLowPin; /*!< Setting back plane pin 0 ~ pin 31. Setting bit n to 1 means setting pin n as back
AnnaBridge 171:3a7713b1edbc 301 plane. It should never have the same bit setting as the frontPlane Pin. */
AnnaBridge 171:3a7713b1edbc 302 uint32_t backPlaneHighPin; /*!< Setting back plane pin 32 ~ pin 63. Setting bit n to 1 means setting pin (n + 32) as
AnnaBridge 171:3a7713b1edbc 303 back plane. It should never have the same bit setting as the frontPlane Pin. */
AnnaBridge 171:3a7713b1edbc 304 slcd_fault_detect_config_t *faultConfig; /*!< Fault frame detection configure. If not requirement, set to NULL. */
AnnaBridge 171:3a7713b1edbc 305 } slcd_config_t;
AnnaBridge 171:3a7713b1edbc 306 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 307 * API
AnnaBridge 171:3a7713b1edbc 308 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 311 extern "C" {
AnnaBridge 171:3a7713b1edbc 312 #endif /* __cplusplus*/
AnnaBridge 171:3a7713b1edbc 313
AnnaBridge 171:3a7713b1edbc 314 /*!
AnnaBridge 171:3a7713b1edbc 315 * @name Initialization and deinitialization
AnnaBridge 171:3a7713b1edbc 316 * @{
AnnaBridge 171:3a7713b1edbc 317 */
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319 /*!
AnnaBridge 171:3a7713b1edbc 320 * @brief Initializes the SLCD, ungates the module clock, initializes the power
AnnaBridge 171:3a7713b1edbc 321 * setting, enables all used plane pins, and sets with interrupt and work mode
AnnaBridge 171:3a7713b1edbc 322 * with configuration.
AnnaBridge 171:3a7713b1edbc 323 *
AnnaBridge 171:3a7713b1edbc 324 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 325 * @param configure SLCD configuration pointer.
AnnaBridge 171:3a7713b1edbc 326 * For the configuration structure, many parameters have the default setting
AnnaBridge 171:3a7713b1edbc 327 * and the SLCD_Getdefaultconfig() is provided to get them. Use it
AnnaBridge 171:3a7713b1edbc 328 * verified for their applications.
AnnaBridge 171:3a7713b1edbc 329 * The others have no default settings such as "clkConfig" and must be provided
AnnaBridge 171:3a7713b1edbc 330 * by the application before calling the SLCD_Init() API.
AnnaBridge 171:3a7713b1edbc 331 */
AnnaBridge 171:3a7713b1edbc 332 void SLCD_Init(LCD_Type *base, slcd_config_t *configure);
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334 /*!
AnnaBridge 171:3a7713b1edbc 335 * @brief Deinitializes the SLCD module, gates the module clock, disables an interrupt,
AnnaBridge 171:3a7713b1edbc 336 * and displays the SLCD.
AnnaBridge 171:3a7713b1edbc 337 *
AnnaBridge 171:3a7713b1edbc 338 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 339 */
AnnaBridge 171:3a7713b1edbc 340 void SLCD_Deinit(LCD_Type *base);
AnnaBridge 171:3a7713b1edbc 341
AnnaBridge 171:3a7713b1edbc 342 /*!
AnnaBridge 171:3a7713b1edbc 343 * @brief Gets the SLCD default configuration structure. The
AnnaBridge 171:3a7713b1edbc 344 * purpose of this API is to get default parameters of the configuration structure
AnnaBridge 171:3a7713b1edbc 345 * for the SLCD_Init(). Use these initialized parameters unchanged in SLCD_Init(),
AnnaBridge 171:3a7713b1edbc 346 * or modify some fields of the structure before the calling SLCD_Init().
AnnaBridge 171:3a7713b1edbc 347 * All default parameters of the configure structure are listed:
AnnaBridge 171:3a7713b1edbc 348 * @code
AnnaBridge 171:3a7713b1edbc 349 config.displayMode = kSLCD_NormalMode; // SLCD normal mode
AnnaBridge 171:3a7713b1edbc 350 config.powerSupply = kSLCD_InternalVll3UseChargePump; // Use charge pump internal VLL3
AnnaBridge 171:3a7713b1edbc 351 config.voltageTrim = kSLCD_RegulatedVolatgeTrim00;
AnnaBridge 171:3a7713b1edbc 352 config.lowPowerBehavior = kSLCD_EnabledInWaitStop; // Work on low power mode
AnnaBridge 171:3a7713b1edbc 353 config.interruptSrc = 0; // No interrupt source is enabled
AnnaBridge 171:3a7713b1edbc 354 config.faultConfig = NULL; // Fault detection is disabled
AnnaBridge 171:3a7713b1edbc 355 config.frameFreqIntEnable = false;
AnnaBridge 171:3a7713b1edbc 356 @endcode
AnnaBridge 171:3a7713b1edbc 357 * @param configure The SLCD configuration structure pointer.
AnnaBridge 171:3a7713b1edbc 358 */
AnnaBridge 171:3a7713b1edbc 359 void SLCD_GetDefaultConfig(slcd_config_t *configure);
AnnaBridge 171:3a7713b1edbc 360
AnnaBridge 171:3a7713b1edbc 361 /* @}*/
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363 /*!
AnnaBridge 171:3a7713b1edbc 364 * @name Plane Setting and Display Control
AnnaBridge 171:3a7713b1edbc 365 * @{
AnnaBridge 171:3a7713b1edbc 366 */
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 /*!
AnnaBridge 171:3a7713b1edbc 369 * @brief Enables the SLCD controller, starts generate, and displays the front plane and back plane waveform.
AnnaBridge 171:3a7713b1edbc 370 *
AnnaBridge 171:3a7713b1edbc 371 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 372 */
AnnaBridge 171:3a7713b1edbc 373 static inline void SLCD_StartDisplay(LCD_Type *base)
AnnaBridge 171:3a7713b1edbc 374 {
AnnaBridge 171:3a7713b1edbc 375 base->GCR |= LCD_GCR_LCDEN_MASK;
AnnaBridge 171:3a7713b1edbc 376 }
AnnaBridge 171:3a7713b1edbc 377
AnnaBridge 171:3a7713b1edbc 378 /*!
AnnaBridge 171:3a7713b1edbc 379 * @brief Stops the SLCD controller. There is no waveform generator and all enabled pins
AnnaBridge 171:3a7713b1edbc 380 * only output a low value.
AnnaBridge 171:3a7713b1edbc 381 *
AnnaBridge 171:3a7713b1edbc 382 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 383 */
AnnaBridge 171:3a7713b1edbc 384 static inline void SLCD_StopDisplay(LCD_Type *base)
AnnaBridge 171:3a7713b1edbc 385 {
AnnaBridge 171:3a7713b1edbc 386 base->GCR &= ~LCD_GCR_LCDEN_MASK;
AnnaBridge 171:3a7713b1edbc 387 }
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389 /*!
AnnaBridge 171:3a7713b1edbc 390 * @brief Starts the SLCD blink mode.
AnnaBridge 171:3a7713b1edbc 391 *
AnnaBridge 171:3a7713b1edbc 392 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 393 * @param mode SLCD blink mode.
AnnaBridge 171:3a7713b1edbc 394 * @param rate SLCD blink rate.
AnnaBridge 171:3a7713b1edbc 395 */
AnnaBridge 171:3a7713b1edbc 396 void SLCD_StartBlinkMode(LCD_Type *base, slcd_blink_mode_t mode, slcd_blink_rate_t rate);
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 /*!
AnnaBridge 171:3a7713b1edbc 399 * @brief Stops the SLCD blink mode.
AnnaBridge 171:3a7713b1edbc 400 *
AnnaBridge 171:3a7713b1edbc 401 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 402 */
AnnaBridge 171:3a7713b1edbc 403 static inline void SLCD_StopBlinkMode(LCD_Type *base)
AnnaBridge 171:3a7713b1edbc 404 {
AnnaBridge 171:3a7713b1edbc 405 base->AR &= ~LCD_AR_BLINK_MASK;
AnnaBridge 171:3a7713b1edbc 406 }
AnnaBridge 171:3a7713b1edbc 407
AnnaBridge 171:3a7713b1edbc 408 /*!
AnnaBridge 171:3a7713b1edbc 409 * @brief Sets the SLCD back plane pin phase.
AnnaBridge 171:3a7713b1edbc 410 *
AnnaBridge 171:3a7713b1edbc 411 * This function sets the SLCD back plane pin phase. "kSLCD_PhaseXActivate" setting
AnnaBridge 171:3a7713b1edbc 412 * means the phase X is active for the back plane pin. "kSLCD_NoPhaseActivate" setting
AnnaBridge 171:3a7713b1edbc 413 * means there is no phase active for the back plane pin.
AnnaBridge 171:3a7713b1edbc 414 * register value.
AnnaBridge 171:3a7713b1edbc 415 * For example, set the back plane pin 20 for phase A:
AnnaBridge 171:3a7713b1edbc 416 * @code
AnnaBridge 171:3a7713b1edbc 417 * SLCD_SetBackPlanePhase(LCD, 20, kSLCD_PhaseAActivate);
AnnaBridge 171:3a7713b1edbc 418 * @endcode
AnnaBridge 171:3a7713b1edbc 419 *
AnnaBridge 171:3a7713b1edbc 420 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 421 * @param pinIndx SLCD back plane pin index. Range from 0 to 63.
AnnaBridge 171:3a7713b1edbc 422 * @param phase The phase activates for the back plane pin.
AnnaBridge 171:3a7713b1edbc 423 */
AnnaBridge 171:3a7713b1edbc 424 static inline void SLCD_SetBackPlanePhase(LCD_Type *base, uint32_t pinIndx, slcd_phase_type_t phase)
AnnaBridge 171:3a7713b1edbc 425 {
AnnaBridge 171:3a7713b1edbc 426 base->WF8B[pinIndx] = phase;
AnnaBridge 171:3a7713b1edbc 427 }
AnnaBridge 171:3a7713b1edbc 428
AnnaBridge 171:3a7713b1edbc 429 /*!
AnnaBridge 171:3a7713b1edbc 430 * @brief Sets the SLCD front plane segment operation for a front plane pin.
AnnaBridge 171:3a7713b1edbc 431 *
AnnaBridge 171:3a7713b1edbc 432 * This function sets the SLCD front plane segment on or off operation.
AnnaBridge 171:3a7713b1edbc 433 * Each bit turns on or off the segments associated with the front plane pin in
AnnaBridge 171:3a7713b1edbc 434 * the following pattern: HGFEDCBA (most significant bit controls segment H and
AnnaBridge 171:3a7713b1edbc 435 * least significant bit controls segment A).
AnnaBridge 171:3a7713b1edbc 436 * For example, turn on the front plane pin 20 for phase B and phase C:
AnnaBridge 171:3a7713b1edbc 437 * @code
AnnaBridge 171:3a7713b1edbc 438 * SLCD_SetFrontPlaneSegments(LCD, 20, (kSLCD_PhaseBActivate | kSLCD_PhaseCActivate));
AnnaBridge 171:3a7713b1edbc 439 * @endcode
AnnaBridge 171:3a7713b1edbc 440 *
AnnaBridge 171:3a7713b1edbc 441 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 442 * @param pinIndx SLCD back plane pin index. Range from 0 to 63.
AnnaBridge 171:3a7713b1edbc 443 * @param operation The operation for the segment on the front plane pin.
AnnaBridge 171:3a7713b1edbc 444 * This is a logical OR of the enumeration :: slcd_phase_type_t.
AnnaBridge 171:3a7713b1edbc 445 */
AnnaBridge 171:3a7713b1edbc 446 static inline void SLCD_SetFrontPlaneSegments(LCD_Type *base, uint32_t pinIndx, uint8_t operation)
AnnaBridge 171:3a7713b1edbc 447 {
AnnaBridge 171:3a7713b1edbc 448 base->WF8B[pinIndx] = operation;
AnnaBridge 171:3a7713b1edbc 449 }
AnnaBridge 171:3a7713b1edbc 450
AnnaBridge 171:3a7713b1edbc 451 /*!
AnnaBridge 171:3a7713b1edbc 452 * @brief Sets one SLCD front plane pin for one phase.
AnnaBridge 171:3a7713b1edbc 453 *
AnnaBridge 171:3a7713b1edbc 454 * This function can be used to set one phase on or off for the front plane pin.
AnnaBridge 171:3a7713b1edbc 455 * It can be call many times to set the plane pin for different phase indexes.
AnnaBridge 171:3a7713b1edbc 456 * For example, turn on the front plane pin 20 for phase B and phase C:
AnnaBridge 171:3a7713b1edbc 457 * @code
AnnaBridge 171:3a7713b1edbc 458 * SLCD_SetFrontPlaneOnePhase(LCD, 20, kSLCD_PhaseBIndex, true);
AnnaBridge 171:3a7713b1edbc 459 * SLCD_SetFrontPlaneOnePhase(LCD, 20, kSLCD_PhaseCIndex, true);
AnnaBridge 171:3a7713b1edbc 460 * @endcode
AnnaBridge 171:3a7713b1edbc 461 *
AnnaBridge 171:3a7713b1edbc 462 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 463 * @param pinIndx SLCD back plane pin index. Range from 0 to 63.
AnnaBridge 171:3a7713b1edbc 464 * @param phaseIndx The phase bit index @ref slcd_phase_index_t.
AnnaBridge 171:3a7713b1edbc 465 * @param enable True to turn on the segment for phaseIndx phase
AnnaBridge 171:3a7713b1edbc 466 * false to turn off the segment for phaseIndx phase.
AnnaBridge 171:3a7713b1edbc 467 */
AnnaBridge 171:3a7713b1edbc 468 static inline void SLCD_SetFrontPlaneOnePhase(LCD_Type *base,
AnnaBridge 171:3a7713b1edbc 469 uint32_t pinIndx,
AnnaBridge 171:3a7713b1edbc 470 slcd_phase_index_t phaseIndx,
AnnaBridge 171:3a7713b1edbc 471 bool enable)
AnnaBridge 171:3a7713b1edbc 472 {
AnnaBridge 171:3a7713b1edbc 473 uint8_t reg = base->WF8B[pinIndx];
AnnaBridge 171:3a7713b1edbc 474
AnnaBridge 171:3a7713b1edbc 475 if (enable)
AnnaBridge 171:3a7713b1edbc 476 {
AnnaBridge 171:3a7713b1edbc 477 base->WF8B[pinIndx] = (reg | (1U << phaseIndx));
AnnaBridge 171:3a7713b1edbc 478 }
AnnaBridge 171:3a7713b1edbc 479 else
AnnaBridge 171:3a7713b1edbc 480 {
AnnaBridge 171:3a7713b1edbc 481 base->WF8B[pinIndx] = (reg & ~(1U << phaseIndx));
AnnaBridge 171:3a7713b1edbc 482 }
AnnaBridge 171:3a7713b1edbc 483 }
AnnaBridge 171:3a7713b1edbc 484
AnnaBridge 171:3a7713b1edbc 485 #if FSL_FEATURE_SLCD_HAS_PAD_SAFE
AnnaBridge 171:3a7713b1edbc 486 /*!
AnnaBridge 171:3a7713b1edbc 487 * @brief Enables/disables the SLCD pad safe state.
AnnaBridge 171:3a7713b1edbc 488 *
AnnaBridge 171:3a7713b1edbc 489 * Forces the safe state on the LCD pad controls. All LCD front plane
AnnaBridge 171:3a7713b1edbc 490 * and backplane functions are disabled.
AnnaBridge 171:3a7713b1edbc 491 *
AnnaBridge 171:3a7713b1edbc 492 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 493 * @param enable True enable, false disable.
AnnaBridge 171:3a7713b1edbc 494 */
AnnaBridge 171:3a7713b1edbc 495 static inline void SLCD_EnablePadSafeState(LCD_Type *base, bool enable)
AnnaBridge 171:3a7713b1edbc 496 {
AnnaBridge 171:3a7713b1edbc 497 if (enable)
AnnaBridge 171:3a7713b1edbc 498 { /* Enable. */
AnnaBridge 171:3a7713b1edbc 499 base->GCR |= LCD_GCR_PADSAFE_MASK;
AnnaBridge 171:3a7713b1edbc 500 }
AnnaBridge 171:3a7713b1edbc 501 else
AnnaBridge 171:3a7713b1edbc 502 { /* Disable. */
AnnaBridge 171:3a7713b1edbc 503 base->GCR &= ~LCD_GCR_PADSAFE_MASK;
AnnaBridge 171:3a7713b1edbc 504 }
AnnaBridge 171:3a7713b1edbc 505 }
AnnaBridge 171:3a7713b1edbc 506 #endif /* FSL_FEATURE_SLCD_HAS_PAD_SAFE */
AnnaBridge 171:3a7713b1edbc 507
AnnaBridge 171:3a7713b1edbc 508 /*!
AnnaBridge 171:3a7713b1edbc 509 * @brief Gets the SLCD fault detect counter.
AnnaBridge 171:3a7713b1edbc 510 *
AnnaBridge 171:3a7713b1edbc 511 * This function gets the number of samples inside the
AnnaBridge 171:3a7713b1edbc 512 * fault detection sample window.
AnnaBridge 171:3a7713b1edbc 513 *
AnnaBridge 171:3a7713b1edbc 514 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 515 * @return The fault detect counter. The maximum return value is 255.
AnnaBridge 171:3a7713b1edbc 516 * If the maximum 255 returns, the overflow may happen.
AnnaBridge 171:3a7713b1edbc 517 * Reconfigure the fault detect sample window and fault detect clock prescaler
AnnaBridge 171:3a7713b1edbc 518 * for proper sampling.
AnnaBridge 171:3a7713b1edbc 519 */
AnnaBridge 171:3a7713b1edbc 520 static inline uint32_t SLCD_GetFaultDetectCounter(LCD_Type *base)
AnnaBridge 171:3a7713b1edbc 521 {
AnnaBridge 171:3a7713b1edbc 522 return base->FDSR & LCD_FDSR_FDCNT_MASK;
AnnaBridge 171:3a7713b1edbc 523 }
AnnaBridge 171:3a7713b1edbc 524
AnnaBridge 171:3a7713b1edbc 525 /* @} */
AnnaBridge 171:3a7713b1edbc 526
AnnaBridge 171:3a7713b1edbc 527 /*!
AnnaBridge 171:3a7713b1edbc 528 * @name Interrupts.
AnnaBridge 171:3a7713b1edbc 529 * @{
AnnaBridge 171:3a7713b1edbc 530 */
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 /*!
AnnaBridge 171:3a7713b1edbc 533 * @brief Enables the SLCD interrupt.
AnnaBridge 171:3a7713b1edbc 534 * For example, to enable fault detect complete interrupt and frame frequency interrupt,
AnnaBridge 171:3a7713b1edbc 535 * for FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT enabled case, do the following.
AnnaBridge 171:3a7713b1edbc 536 * @code
AnnaBridge 171:3a7713b1edbc 537 * SLCD_EnableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt);
AnnaBridge 171:3a7713b1edbc 538 * @endcode
AnnaBridge 171:3a7713b1edbc 539 *
AnnaBridge 171:3a7713b1edbc 540 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 541 * @param mask SLCD interrupts to enable. This is a logical OR of the
AnnaBridge 171:3a7713b1edbc 542 * enumeration :: slcd_interrupt_enable_t.
AnnaBridge 171:3a7713b1edbc 543 */
AnnaBridge 171:3a7713b1edbc 544 void SLCD_EnableInterrupts(LCD_Type *base, uint32_t mask);
AnnaBridge 171:3a7713b1edbc 545
AnnaBridge 171:3a7713b1edbc 546 /*!
AnnaBridge 171:3a7713b1edbc 547 * @brief Disables the SLCD interrupt.
AnnaBridge 171:3a7713b1edbc 548 * For example, to disable fault detect complete interrupt and frame frequency interrupt,
AnnaBridge 171:3a7713b1edbc 549 * for FSL_FEATURE_SLCD_HAS_FRAME_FREQUENCY_INTERRUPT enabled case, do the following.
AnnaBridge 171:3a7713b1edbc 550 * @code
AnnaBridge 171:3a7713b1edbc 551 * SLCD_DisableInterrupts(LCD,kSLCD_FaultDetectCompleteInterrupt | kSLCD_FrameFreqInterrupt);
AnnaBridge 171:3a7713b1edbc 552 * @endcode
AnnaBridge 171:3a7713b1edbc 553 *
AnnaBridge 171:3a7713b1edbc 554 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 555 * @param mask SLCD interrupts to disable. This is a logical OR of the
AnnaBridge 171:3a7713b1edbc 556 * enumeration :: slcd_interrupt_enable_t.
AnnaBridge 171:3a7713b1edbc 557 */
AnnaBridge 171:3a7713b1edbc 558 void SLCD_DisableInterrupts(LCD_Type *base, uint32_t mask);
AnnaBridge 171:3a7713b1edbc 559
AnnaBridge 171:3a7713b1edbc 560 /*!
AnnaBridge 171:3a7713b1edbc 561 * @brief Gets the SLCD interrupt status flag.
AnnaBridge 171:3a7713b1edbc 562 *
AnnaBridge 171:3a7713b1edbc 563 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 564 * @return The event status of the interrupt source. This is the logical OR of members
AnnaBridge 171:3a7713b1edbc 565 * of the enumeration :: slcd_interrupt_enable_t.
AnnaBridge 171:3a7713b1edbc 566 */
AnnaBridge 171:3a7713b1edbc 567 uint32_t SLCD_GetInterruptStatus(LCD_Type *base);
AnnaBridge 171:3a7713b1edbc 568
AnnaBridge 171:3a7713b1edbc 569 /*!
AnnaBridge 171:3a7713b1edbc 570 * @brief Clears the SLCD interrupt events status flag.
AnnaBridge 171:3a7713b1edbc 571 *
AnnaBridge 171:3a7713b1edbc 572 * @param base SLCD peripheral base address.
AnnaBridge 171:3a7713b1edbc 573 * @param mask SLCD interrupt source to be cleared.
AnnaBridge 171:3a7713b1edbc 574 * This is the logical OR of members of the enumeration :: slcd_interrupt_enable_t.
AnnaBridge 171:3a7713b1edbc 575 */
AnnaBridge 171:3a7713b1edbc 576 void SLCD_ClearInterruptStatus(LCD_Type *base, uint32_t mask);
AnnaBridge 171:3a7713b1edbc 577
AnnaBridge 171:3a7713b1edbc 578 /* @} */
AnnaBridge 171:3a7713b1edbc 579
AnnaBridge 171:3a7713b1edbc 580 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 581 }
AnnaBridge 171:3a7713b1edbc 582 #endif /* __cplusplus*/
AnnaBridge 171:3a7713b1edbc 583
AnnaBridge 171:3a7713b1edbc 584 /*! @}*/
AnnaBridge 171:3a7713b1edbc 585
AnnaBridge 171:3a7713b1edbc 586 #endif /* _FSL_SLCD_H_*/