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TARGET_KL43Z/TOOLCHAIN_ARM_STD/fsl_clock.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 3 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 6 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 9 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 13 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 171:3a7713b1edbc 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 17 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 29 */
AnnaBridge 171:3a7713b1edbc 30
AnnaBridge 171:3a7713b1edbc 31 #ifndef _FSL_CLOCK_H_
AnnaBridge 171:3a7713b1edbc 32 #define _FSL_CLOCK_H_
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #include "fsl_device_registers.h"
AnnaBridge 171:3a7713b1edbc 35 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 36 #include <stdbool.h>
AnnaBridge 171:3a7713b1edbc 37 #include <assert.h>
AnnaBridge 171:3a7713b1edbc 38
AnnaBridge 171:3a7713b1edbc 39 /*! @addtogroup mcglite */
AnnaBridge 171:3a7713b1edbc 40 /*! @{ */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 43 * Definitions
AnnaBridge 171:3a7713b1edbc 44 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /*! @brief Clock driver version. */
AnnaBridge 171:3a7713b1edbc 47 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /*! @brief External XTAL0 (OSC0) clock frequency.
AnnaBridge 171:3a7713b1edbc 50 *
AnnaBridge 171:3a7713b1edbc 51 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz, when the clock is setup, use the
AnnaBridge 171:3a7713b1edbc 52 * function CLOCK_SetXtal0Freq to set the value in to clock driver. For example,
AnnaBridge 171:3a7713b1edbc 53 * if XTAL0 is 8MHz,
AnnaBridge 171:3a7713b1edbc 54 * @code
AnnaBridge 171:3a7713b1edbc 55 * CLOCK_InitOsc0(...); // Setup the OSC0
AnnaBridge 171:3a7713b1edbc 56 * CLOCK_SetXtal0Freq(80000000); // Set the XTAL0 value to clock driver.
AnnaBridge 171:3a7713b1edbc 57 * @endcode
AnnaBridge 171:3a7713b1edbc 58 *
AnnaBridge 171:3a7713b1edbc 59 * This is important for the multicore platforms, only one core needs to setup
AnnaBridge 171:3a7713b1edbc 60 * OSC0 using CLOCK_InitOsc0, all other cores need to call CLOCK_SetXtal0Freq
AnnaBridge 171:3a7713b1edbc 61 * to get valid clock frequency.
AnnaBridge 171:3a7713b1edbc 62 */
AnnaBridge 171:3a7713b1edbc 63 extern uint32_t g_xtal0Freq;
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 /*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
AnnaBridge 171:3a7713b1edbc 66 *
AnnaBridge 171:3a7713b1edbc 67 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz, when the clock is setup, use the
AnnaBridge 171:3a7713b1edbc 68 * function CLOCK_SetXtal32Freq to set the value in to clock driver.
AnnaBridge 171:3a7713b1edbc 69 *
AnnaBridge 171:3a7713b1edbc 70 * This is important for the multicore platforms, only one core needs to setup
AnnaBridge 171:3a7713b1edbc 71 * the clock, all other cores need to call CLOCK_SetXtal32Freq
AnnaBridge 171:3a7713b1edbc 72 * to get valid clock frequency.
AnnaBridge 171:3a7713b1edbc 73 */
AnnaBridge 171:3a7713b1edbc 74 extern uint32_t g_xtal32Freq;
AnnaBridge 171:3a7713b1edbc 75
AnnaBridge 171:3a7713b1edbc 76 /*! @brief Clock ip name array for DMAMUX. */
AnnaBridge 171:3a7713b1edbc 77 #define DMAMUX_CLOCKS \
AnnaBridge 171:3a7713b1edbc 78 { \
AnnaBridge 171:3a7713b1edbc 79 kCLOCK_Dmamux0 \
AnnaBridge 171:3a7713b1edbc 80 }
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 /*! @brief Clock ip name array for RTC. */
AnnaBridge 171:3a7713b1edbc 83 #define RTC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 84 { \
AnnaBridge 171:3a7713b1edbc 85 kCLOCK_Rtc0 \
AnnaBridge 171:3a7713b1edbc 86 }
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 /*! @brief Clock ip name array for SAI. */
AnnaBridge 171:3a7713b1edbc 89 #define SAI_CLOCKS \
AnnaBridge 171:3a7713b1edbc 90 { \
AnnaBridge 171:3a7713b1edbc 91 kCLOCK_Sai0 \
AnnaBridge 171:3a7713b1edbc 92 }
AnnaBridge 171:3a7713b1edbc 93
AnnaBridge 171:3a7713b1edbc 94 /*! @brief Clock ip name array for SPI. */
AnnaBridge 171:3a7713b1edbc 95 #define SPI_CLOCKS \
AnnaBridge 171:3a7713b1edbc 96 { \
AnnaBridge 171:3a7713b1edbc 97 kCLOCK_Spi0, kCLOCK_Spi1 \
AnnaBridge 171:3a7713b1edbc 98 }
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 /*! @brief Clock ip name array for SLCD. */
AnnaBridge 171:3a7713b1edbc 101 #define SLCD_CLOCKS \
AnnaBridge 171:3a7713b1edbc 102 { \
AnnaBridge 171:3a7713b1edbc 103 kCLOCK_Slcd0 \
AnnaBridge 171:3a7713b1edbc 104 }
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 /*! @brief Clock ip name array for PIT. */
AnnaBridge 171:3a7713b1edbc 107 #define PIT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 108 { \
AnnaBridge 171:3a7713b1edbc 109 kCLOCK_Pit0 \
AnnaBridge 171:3a7713b1edbc 110 }
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 /*! @brief Clock ip name array for PORT. */
AnnaBridge 171:3a7713b1edbc 113 #define PORT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 114 { \
AnnaBridge 171:3a7713b1edbc 115 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
AnnaBridge 171:3a7713b1edbc 116 }
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 /*! @brief Clock ip name array for LPUART. */
AnnaBridge 171:3a7713b1edbc 119 #define LPUART_CLOCKS \
AnnaBridge 171:3a7713b1edbc 120 { \
AnnaBridge 171:3a7713b1edbc 121 kCLOCK_Lpuart0, kCLOCK_Lpuart1 \
AnnaBridge 171:3a7713b1edbc 122 }
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 /*! @brief Clock ip name array for DAC. */
AnnaBridge 171:3a7713b1edbc 125 #define DAC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 126 { \
AnnaBridge 171:3a7713b1edbc 127 kCLOCK_Dac0 \
AnnaBridge 171:3a7713b1edbc 128 }
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /*! @brief Clock ip name array for LPTMR. */
AnnaBridge 171:3a7713b1edbc 131 #define LPTMR_CLOCKS \
AnnaBridge 171:3a7713b1edbc 132 { \
AnnaBridge 171:3a7713b1edbc 133 kCLOCK_Lptmr0 \
AnnaBridge 171:3a7713b1edbc 134 }
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136 /*! @brief Clock ip name array for ADC16. */
AnnaBridge 171:3a7713b1edbc 137 #define ADC16_CLOCKS \
AnnaBridge 171:3a7713b1edbc 138 { \
AnnaBridge 171:3a7713b1edbc 139 kCLOCK_Adc0 \
AnnaBridge 171:3a7713b1edbc 140 }
AnnaBridge 171:3a7713b1edbc 141
AnnaBridge 171:3a7713b1edbc 142 /*! @brief Clock ip name array for FLEXIO. */
AnnaBridge 171:3a7713b1edbc 143 #define FLEXIO_CLOCKS \
AnnaBridge 171:3a7713b1edbc 144 { \
AnnaBridge 171:3a7713b1edbc 145 kCLOCK_Flexio0 \
AnnaBridge 171:3a7713b1edbc 146 }
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 /*! @brief Clock ip name array for VREF. */
AnnaBridge 171:3a7713b1edbc 149 #define VREF_CLOCKS \
AnnaBridge 171:3a7713b1edbc 150 { \
AnnaBridge 171:3a7713b1edbc 151 kCLOCK_Vref0 \
AnnaBridge 171:3a7713b1edbc 152 }
AnnaBridge 171:3a7713b1edbc 153
AnnaBridge 171:3a7713b1edbc 154 /*! @brief Clock ip name array for DMA. */
AnnaBridge 171:3a7713b1edbc 155 #define DMA_CLOCKS \
AnnaBridge 171:3a7713b1edbc 156 { \
AnnaBridge 171:3a7713b1edbc 157 kCLOCK_Dma0 \
AnnaBridge 171:3a7713b1edbc 158 }
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /*! @brief Clock ip name array for UART. */
AnnaBridge 171:3a7713b1edbc 161 #define UART_CLOCKS \
AnnaBridge 171:3a7713b1edbc 162 { \
AnnaBridge 171:3a7713b1edbc 163 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Uart2 \
AnnaBridge 171:3a7713b1edbc 164 }
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 /*! @brief Clock ip name array for TPM. */
AnnaBridge 171:3a7713b1edbc 167 #define TPM_CLOCKS \
AnnaBridge 171:3a7713b1edbc 168 { \
AnnaBridge 171:3a7713b1edbc 169 kCLOCK_Tpm0, kCLOCK_Tpm1, kCLOCK_Tpm2 \
AnnaBridge 171:3a7713b1edbc 170 }
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 /*! @brief Clock ip name array for I2C. */
AnnaBridge 171:3a7713b1edbc 173 #define I2C_CLOCKS \
AnnaBridge 171:3a7713b1edbc 174 { \
AnnaBridge 171:3a7713b1edbc 175 kCLOCK_I2c0, kCLOCK_I2c1 \
AnnaBridge 171:3a7713b1edbc 176 }
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 /*! @brief Clock ip name array for FTF. */
AnnaBridge 171:3a7713b1edbc 179 #define FTF_CLOCKS \
AnnaBridge 171:3a7713b1edbc 180 { \
AnnaBridge 171:3a7713b1edbc 181 kCLOCK_Ftf0 \
AnnaBridge 171:3a7713b1edbc 182 }
AnnaBridge 171:3a7713b1edbc 183
AnnaBridge 171:3a7713b1edbc 184 /*! @brief Clock ip name array for CMP. */
AnnaBridge 171:3a7713b1edbc 185 #define CMP_CLOCKS \
AnnaBridge 171:3a7713b1edbc 186 { \
AnnaBridge 171:3a7713b1edbc 187 kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2 \
AnnaBridge 171:3a7713b1edbc 188 }
AnnaBridge 171:3a7713b1edbc 189
AnnaBridge 171:3a7713b1edbc 190 /*!
AnnaBridge 171:3a7713b1edbc 191 * @brief LPO clock frequency.
AnnaBridge 171:3a7713b1edbc 192 */
AnnaBridge 171:3a7713b1edbc 193 #define LPO_CLK_FREQ 1000U
AnnaBridge 171:3a7713b1edbc 194
AnnaBridge 171:3a7713b1edbc 195 /*! @brief Peripherals clock source definition. */
AnnaBridge 171:3a7713b1edbc 196 #define SYS_CLK kCLOCK_CoreSysClk
AnnaBridge 171:3a7713b1edbc 197 #define BUS_CLK kCLOCK_BusClk
AnnaBridge 171:3a7713b1edbc 198
AnnaBridge 171:3a7713b1edbc 199 #define I2C0_CLK_SRC SYS_CLK
AnnaBridge 171:3a7713b1edbc 200 #define I2C1_CLK_SRC SYS_CLK
AnnaBridge 171:3a7713b1edbc 201 #define SPI0_CLK_SRC BUS_CLK
AnnaBridge 171:3a7713b1edbc 202 #define SPI1_CLK_SRC SYS_CLK
AnnaBridge 171:3a7713b1edbc 203 #define UART2_CLK_SRC BUS_CLK
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 /*! @brief Clock name used to get clock frequency. */
AnnaBridge 171:3a7713b1edbc 206 typedef enum _clock_name
AnnaBridge 171:3a7713b1edbc 207 {
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 /* ----------------------------- System layer clock -------------------------------*/
AnnaBridge 171:3a7713b1edbc 210 kCLOCK_CoreSysClk, /*!< Core/system clock */
AnnaBridge 171:3a7713b1edbc 211 kCLOCK_PlatClk, /*!< Platform clock */
AnnaBridge 171:3a7713b1edbc 212 kCLOCK_BusClk, /*!< Bus clock */
AnnaBridge 171:3a7713b1edbc 213 kCLOCK_FlexBusClk, /*!< FlexBus clock */
AnnaBridge 171:3a7713b1edbc 214 kCLOCK_FlashClk, /*!< Flash clock */
AnnaBridge 171:3a7713b1edbc 215 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
AnnaBridge 171:3a7713b1edbc 216 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /* ---------------------------------- OSC clock -----------------------------------*/
AnnaBridge 171:3a7713b1edbc 219 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
AnnaBridge 171:3a7713b1edbc 220 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
AnnaBridge 171:3a7713b1edbc 221 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
AnnaBridge 171:3a7713b1edbc 222 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
AnnaBridge 171:3a7713b1edbc 223
AnnaBridge 171:3a7713b1edbc 224 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
AnnaBridge 171:3a7713b1edbc 225 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
AnnaBridge 171:3a7713b1edbc 226 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
AnnaBridge 171:3a7713b1edbc 227 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
AnnaBridge 171:3a7713b1edbc 228 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
AnnaBridge 171:3a7713b1edbc 229 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
AnnaBridge 171:3a7713b1edbc 230 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
AnnaBridge 171:3a7713b1edbc 231 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
AnnaBridge 171:3a7713b1edbc 232 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
AnnaBridge 171:3a7713b1edbc 233
AnnaBridge 171:3a7713b1edbc 234 /* --------------------------------- Other clock ----------------------------------*/
AnnaBridge 171:3a7713b1edbc 235 kCLOCK_LpoClk, /*!< LPO clock */
AnnaBridge 171:3a7713b1edbc 236
AnnaBridge 171:3a7713b1edbc 237 } clock_name_t;
AnnaBridge 171:3a7713b1edbc 238
AnnaBridge 171:3a7713b1edbc 239 /*! @brief USB clock source definition. */
AnnaBridge 171:3a7713b1edbc 240 typedef enum _clock_usb_src
AnnaBridge 171:3a7713b1edbc 241 {
AnnaBridge 171:3a7713b1edbc 242 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U), /*!< Use IRC48M. */
AnnaBridge 171:3a7713b1edbc 243 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */
AnnaBridge 171:3a7713b1edbc 244 } clock_usb_src_t;
AnnaBridge 171:3a7713b1edbc 245 /*------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 246
AnnaBridge 171:3a7713b1edbc 247 clock_gate_t definition:
AnnaBridge 171:3a7713b1edbc 248
AnnaBridge 171:3a7713b1edbc 249 31 16 0
AnnaBridge 171:3a7713b1edbc 250 -----------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 251 | SIM_SCGC register offset | control bit offset in SCGC |
AnnaBridge 171:3a7713b1edbc 252 -----------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 253
AnnaBridge 171:3a7713b1edbc 254 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
AnnaBridge 171:3a7713b1edbc 255 SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as
AnnaBridge 171:3a7713b1edbc 256
AnnaBridge 171:3a7713b1edbc 257 kCLOCK_GateSdhc0 = (0x1030 << 16) | 17;
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 ------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 #define CLK_GATE_REG_OFFSET_SHIFT 16U
AnnaBridge 171:3a7713b1edbc 262 #define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
AnnaBridge 171:3a7713b1edbc 263 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
AnnaBridge 171:3a7713b1edbc 264 #define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
AnnaBridge 171:3a7713b1edbc 265
AnnaBridge 171:3a7713b1edbc 266 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
AnnaBridge 171:3a7713b1edbc 267 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
AnnaBridge 171:3a7713b1edbc 268 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
AnnaBridge 171:3a7713b1edbc 269
AnnaBridge 171:3a7713b1edbc 270 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
AnnaBridge 171:3a7713b1edbc 271 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
AnnaBridge 171:3a7713b1edbc 272
AnnaBridge 171:3a7713b1edbc 273 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
AnnaBridge 171:3a7713b1edbc 274 typedef enum _clock_ip_name
AnnaBridge 171:3a7713b1edbc 275 {
AnnaBridge 171:3a7713b1edbc 276 kCLOCK_IpInvalid = 0U,
AnnaBridge 171:3a7713b1edbc 277 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
AnnaBridge 171:3a7713b1edbc 278 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
AnnaBridge 171:3a7713b1edbc 279 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
AnnaBridge 171:3a7713b1edbc 280 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
AnnaBridge 171:3a7713b1edbc 281 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge 171:3a7713b1edbc 282 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge 171:3a7713b1edbc 283 kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
AnnaBridge 171:3a7713b1edbc 284 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
AnnaBridge 171:3a7713b1edbc 285 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x1034U, 22U),
AnnaBridge 171:3a7713b1edbc 286 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x1034U, 23U),
AnnaBridge 171:3a7713b1edbc 287
AnnaBridge 171:3a7713b1edbc 288 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
AnnaBridge 171:3a7713b1edbc 289 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
AnnaBridge 171:3a7713b1edbc 290 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
AnnaBridge 171:3a7713b1edbc 291 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
AnnaBridge 171:3a7713b1edbc 292 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
AnnaBridge 171:3a7713b1edbc 293 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
AnnaBridge 171:3a7713b1edbc 294 kCLOCK_Slcd0 = CLK_GATE_DEFINE(0x1038U, 19U),
AnnaBridge 171:3a7713b1edbc 295 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x1038U, 20U),
AnnaBridge 171:3a7713b1edbc 296 kCLOCK_Lpuart1 = CLK_GATE_DEFINE(0x1038U, 21U),
AnnaBridge 171:3a7713b1edbc 297 kCLOCK_Flexio0 = CLK_GATE_DEFINE(0x1038U, 31U),
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
AnnaBridge 171:3a7713b1edbc 300 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
AnnaBridge 171:3a7713b1edbc 301 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
AnnaBridge 171:3a7713b1edbc 302 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
AnnaBridge 171:3a7713b1edbc 303 kCLOCK_Tpm0 = CLK_GATE_DEFINE(0x103CU, 24U),
AnnaBridge 171:3a7713b1edbc 304 kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x103CU, 25U),
AnnaBridge 171:3a7713b1edbc 305 kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x103CU, 26U),
AnnaBridge 171:3a7713b1edbc 306 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
AnnaBridge 171:3a7713b1edbc 307 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
AnnaBridge 171:3a7713b1edbc 308 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 8U),
AnnaBridge 171:3a7713b1edbc 311 } clock_ip_name_t;
AnnaBridge 171:3a7713b1edbc 312
AnnaBridge 171:3a7713b1edbc 313 /*!@brief SIM configuration structure for clock setting. */
AnnaBridge 171:3a7713b1edbc 314 typedef struct _sim_clock_config
AnnaBridge 171:3a7713b1edbc 315 {
AnnaBridge 171:3a7713b1edbc 316 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
AnnaBridge 171:3a7713b1edbc 317 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
AnnaBridge 171:3a7713b1edbc 318 } sim_clock_config_t;
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 /*! @brief Oscillator capacitor load setting.*/
AnnaBridge 171:3a7713b1edbc 321 enum _osc_cap_load
AnnaBridge 171:3a7713b1edbc 322 {
AnnaBridge 171:3a7713b1edbc 323 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
AnnaBridge 171:3a7713b1edbc 324 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
AnnaBridge 171:3a7713b1edbc 325 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
AnnaBridge 171:3a7713b1edbc 326 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
AnnaBridge 171:3a7713b1edbc 327 };
AnnaBridge 171:3a7713b1edbc 328
AnnaBridge 171:3a7713b1edbc 329 /*! @brief OSCERCLK enable mode. */
AnnaBridge 171:3a7713b1edbc 330 enum _oscer_enable_mode
AnnaBridge 171:3a7713b1edbc 331 {
AnnaBridge 171:3a7713b1edbc 332 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
AnnaBridge 171:3a7713b1edbc 333 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
AnnaBridge 171:3a7713b1edbc 334 };
AnnaBridge 171:3a7713b1edbc 335
AnnaBridge 171:3a7713b1edbc 336 /*! @brief OSC configuration for OSCERCLK. */
AnnaBridge 171:3a7713b1edbc 337 typedef struct _oscer_config
AnnaBridge 171:3a7713b1edbc 338 {
AnnaBridge 171:3a7713b1edbc 339 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of \ref _oscer_enable_mode. */
AnnaBridge 171:3a7713b1edbc 340
AnnaBridge 171:3a7713b1edbc 341 } oscer_config_t;
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 /*! @brief OSC work mode. */
AnnaBridge 171:3a7713b1edbc 344 typedef enum _osc_mode
AnnaBridge 171:3a7713b1edbc 345 {
AnnaBridge 171:3a7713b1edbc 346 kOSC_ModeExt = 0U, /*!< Use external clock. */
AnnaBridge 171:3a7713b1edbc 347 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
AnnaBridge 171:3a7713b1edbc 348 kOSC_ModeOscHighGain = MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
AnnaBridge 171:3a7713b1edbc 349 } osc_mode_t;
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 /*!
AnnaBridge 171:3a7713b1edbc 352 * @brief OSC Initialization Configuration Structure
AnnaBridge 171:3a7713b1edbc 353 *
AnnaBridge 171:3a7713b1edbc 354 * Defines the configuration data structure to initialize the OSC.
AnnaBridge 171:3a7713b1edbc 355 * When porting to a new board, set the following members
AnnaBridge 171:3a7713b1edbc 356 * according to board settings:
AnnaBridge 171:3a7713b1edbc 357 * 1. freq: The external frequency.
AnnaBridge 171:3a7713b1edbc 358 * 2. workMode: The OSC module mode.
AnnaBridge 171:3a7713b1edbc 359 */
AnnaBridge 171:3a7713b1edbc 360 typedef struct _osc_config
AnnaBridge 171:3a7713b1edbc 361 {
AnnaBridge 171:3a7713b1edbc 362 uint32_t freq; /*!< External clock frequency. */
AnnaBridge 171:3a7713b1edbc 363 uint8_t capLoad; /*!< Capacitor load setting. */
AnnaBridge 171:3a7713b1edbc 364 osc_mode_t workMode; /*!< OSC work mode setting. */
AnnaBridge 171:3a7713b1edbc 365 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
AnnaBridge 171:3a7713b1edbc 366 } osc_config_t;
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 /*! @brief MCG_Lite clock source selection. */
AnnaBridge 171:3a7713b1edbc 369 typedef enum _mcglite_clkout_src
AnnaBridge 171:3a7713b1edbc 370 {
AnnaBridge 171:3a7713b1edbc 371 kMCGLITE_ClkSrcHirc, /*!< MCGOUTCLK source is HIRC */
AnnaBridge 171:3a7713b1edbc 372 kMCGLITE_ClkSrcLirc, /*!< MCGOUTCLK source is LIRC */
AnnaBridge 171:3a7713b1edbc 373 kMCGLITE_ClkSrcExt, /*!< MCGOUTCLK source is external clock source */
AnnaBridge 171:3a7713b1edbc 374 kMCGLITE_ClkSrcReserved
AnnaBridge 171:3a7713b1edbc 375 } mcglite_clkout_src_t;
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 /*! @brief MCG_Lite LIRC select. */
AnnaBridge 171:3a7713b1edbc 378 typedef enum _mcglite_lirc_mode
AnnaBridge 171:3a7713b1edbc 379 {
AnnaBridge 171:3a7713b1edbc 380 kMCGLITE_Lirc2M, /*!< Slow internal reference(LIRC) 2MHz clock selected */
AnnaBridge 171:3a7713b1edbc 381 kMCGLITE_Lirc8M, /*!< Slow internal reference(LIRC) 8MHz clock selected */
AnnaBridge 171:3a7713b1edbc 382 } mcglite_lirc_mode_t;
AnnaBridge 171:3a7713b1edbc 383
AnnaBridge 171:3a7713b1edbc 384 /*! @brief MCG_Lite divider factor selection for clock source*/
AnnaBridge 171:3a7713b1edbc 385 typedef enum _mcglite_lirc_div
AnnaBridge 171:3a7713b1edbc 386 {
AnnaBridge 171:3a7713b1edbc 387 kMCGLITE_LircDivBy1 = 0U, /*!< Divider is 1 */
AnnaBridge 171:3a7713b1edbc 388 kMCGLITE_LircDivBy2, /*!< Divider is 2 */
AnnaBridge 171:3a7713b1edbc 389 kMCGLITE_LircDivBy4, /*!< Divider is 4 */
AnnaBridge 171:3a7713b1edbc 390 kMCGLITE_LircDivBy8, /*!< Divider is 8 */
AnnaBridge 171:3a7713b1edbc 391 kMCGLITE_LircDivBy16, /*!< Divider is 16 */
AnnaBridge 171:3a7713b1edbc 392 kMCGLITE_LircDivBy32, /*!< Divider is 32 */
AnnaBridge 171:3a7713b1edbc 393 kMCGLITE_LircDivBy64, /*!< Divider is 64 */
AnnaBridge 171:3a7713b1edbc 394 kMCGLITE_LircDivBy128 /*!< Divider is 128 */
AnnaBridge 171:3a7713b1edbc 395 } mcglite_lirc_div_t;
AnnaBridge 171:3a7713b1edbc 396
AnnaBridge 171:3a7713b1edbc 397 /*! @brief MCG_Lite clock mode definitions */
AnnaBridge 171:3a7713b1edbc 398 typedef enum _mcglite_mode
AnnaBridge 171:3a7713b1edbc 399 {
AnnaBridge 171:3a7713b1edbc 400 kMCGLITE_ModeHirc48M, /*!< Clock mode is HIRC 48 M */
AnnaBridge 171:3a7713b1edbc 401 kMCGLITE_ModeLirc8M, /*!< Clock mode is LIRC 8 M */
AnnaBridge 171:3a7713b1edbc 402 kMCGLITE_ModeLirc2M, /*!< Clock mode is LIRC 2 M */
AnnaBridge 171:3a7713b1edbc 403 kMCGLITE_ModeExt, /*!< Clock mode is EXT */
AnnaBridge 171:3a7713b1edbc 404 kMCGLITE_ModeError /*!< Unknown mode */
AnnaBridge 171:3a7713b1edbc 405 } mcglite_mode_t;
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 /*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
AnnaBridge 171:3a7713b1edbc 408 enum _mcglite_irclk_enable_mode
AnnaBridge 171:3a7713b1edbc 409 {
AnnaBridge 171:3a7713b1edbc 410 kMCGLITE_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
AnnaBridge 171:3a7713b1edbc 411 kMCGLITE_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
AnnaBridge 171:3a7713b1edbc 412 };
AnnaBridge 171:3a7713b1edbc 413
AnnaBridge 171:3a7713b1edbc 414 /*! @brief MCG_Lite configure structure for mode change. */
AnnaBridge 171:3a7713b1edbc 415 typedef struct _mcglite_config
AnnaBridge 171:3a7713b1edbc 416 {
AnnaBridge 171:3a7713b1edbc 417 mcglite_clkout_src_t outSrc; /*!< MCGOUT clock select. */
AnnaBridge 171:3a7713b1edbc 418 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode, OR'ed value of _mcglite_irclk_enable_mode. */
AnnaBridge 171:3a7713b1edbc 419 mcglite_lirc_mode_t ircs; /*!< MCG_C2[IRCS]. */
AnnaBridge 171:3a7713b1edbc 420 mcglite_lirc_div_t fcrdiv; /*!< MCG_SC[FCRDIV]. */
AnnaBridge 171:3a7713b1edbc 421 mcglite_lirc_div_t lircDiv2; /*!< MCG_MC[LIRC_DIV2]. */
AnnaBridge 171:3a7713b1edbc 422 bool hircEnableInNotHircMode; /*!< HIRC enable when not in HIRC mode. */
AnnaBridge 171:3a7713b1edbc 423 } mcglite_config_t;
AnnaBridge 171:3a7713b1edbc 424
AnnaBridge 171:3a7713b1edbc 425 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 426 * API
AnnaBridge 171:3a7713b1edbc 427 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 428
AnnaBridge 171:3a7713b1edbc 429 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 430 extern "C" {
AnnaBridge 171:3a7713b1edbc 431 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 432
AnnaBridge 171:3a7713b1edbc 433 /*!
AnnaBridge 171:3a7713b1edbc 434 * @brief Set the XTAL0 frequency based on board setting.
AnnaBridge 171:3a7713b1edbc 435 *
AnnaBridge 171:3a7713b1edbc 436 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 437 */
AnnaBridge 171:3a7713b1edbc 438 static inline void CLOCK_SetXtal0Freq(uint32_t freq)
AnnaBridge 171:3a7713b1edbc 439 {
AnnaBridge 171:3a7713b1edbc 440 g_xtal0Freq = freq;
AnnaBridge 171:3a7713b1edbc 441 }
AnnaBridge 171:3a7713b1edbc 442
AnnaBridge 171:3a7713b1edbc 443 /*!
AnnaBridge 171:3a7713b1edbc 444 * @brief Set the XTAL32/RTC_CLKIN frequency based on board setting.
AnnaBridge 171:3a7713b1edbc 445 *
AnnaBridge 171:3a7713b1edbc 446 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 447 */
AnnaBridge 171:3a7713b1edbc 448 static inline void CLOCK_SetXtal32Freq(uint32_t freq)
AnnaBridge 171:3a7713b1edbc 449 {
AnnaBridge 171:3a7713b1edbc 450 g_xtal32Freq = freq;
AnnaBridge 171:3a7713b1edbc 451 }
AnnaBridge 171:3a7713b1edbc 452
AnnaBridge 171:3a7713b1edbc 453 /*!
AnnaBridge 171:3a7713b1edbc 454 * @brief Enable the clock for specific IP.
AnnaBridge 171:3a7713b1edbc 455 *
AnnaBridge 171:3a7713b1edbc 456 * @param name Which clock to enable, see \ref clock_ip_name_t.
AnnaBridge 171:3a7713b1edbc 457 */
AnnaBridge 171:3a7713b1edbc 458 static inline void CLOCK_EnableClock(clock_ip_name_t name)
AnnaBridge 171:3a7713b1edbc 459 {
AnnaBridge 171:3a7713b1edbc 460 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge 171:3a7713b1edbc 461 (*(volatile uint32_t *)regAddr) |= (1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge 171:3a7713b1edbc 462 }
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464 /*!
AnnaBridge 171:3a7713b1edbc 465 * @brief Disable the clock for specific IP.
AnnaBridge 171:3a7713b1edbc 466 *
AnnaBridge 171:3a7713b1edbc 467 * @param name Which clock to disable, see \ref clock_ip_name_t.
AnnaBridge 171:3a7713b1edbc 468 */
AnnaBridge 171:3a7713b1edbc 469 static inline void CLOCK_DisableClock(clock_ip_name_t name)
AnnaBridge 171:3a7713b1edbc 470 {
AnnaBridge 171:3a7713b1edbc 471 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
AnnaBridge 171:3a7713b1edbc 472 (*(volatile uint32_t *)regAddr) &= ~(1U << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
AnnaBridge 171:3a7713b1edbc 473 }
AnnaBridge 171:3a7713b1edbc 474
AnnaBridge 171:3a7713b1edbc 475 /*!
AnnaBridge 171:3a7713b1edbc 476 * @brief Set ERCLK32K source.
AnnaBridge 171:3a7713b1edbc 477 *
AnnaBridge 171:3a7713b1edbc 478 * @param src The value to set ERCLK32K clock source.
AnnaBridge 171:3a7713b1edbc 479 */
AnnaBridge 171:3a7713b1edbc 480 static inline void CLOCK_SetEr32kClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 481 {
AnnaBridge 171:3a7713b1edbc 482 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
AnnaBridge 171:3a7713b1edbc 483 }
AnnaBridge 171:3a7713b1edbc 484
AnnaBridge 171:3a7713b1edbc 485 /*!
AnnaBridge 171:3a7713b1edbc 486 * @brief Set LPUART0 clock source.
AnnaBridge 171:3a7713b1edbc 487 *
AnnaBridge 171:3a7713b1edbc 488 * @param src The value to set LPUART0 clock source.
AnnaBridge 171:3a7713b1edbc 489 */
AnnaBridge 171:3a7713b1edbc 490 static inline void CLOCK_SetLpuart0Clock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 491 {
AnnaBridge 171:3a7713b1edbc 492 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART0SRC_MASK) | SIM_SOPT2_LPUART0SRC(src));
AnnaBridge 171:3a7713b1edbc 493 }
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 /*!
AnnaBridge 171:3a7713b1edbc 496 * @brief Set LPUART1 clock source.
AnnaBridge 171:3a7713b1edbc 497 *
AnnaBridge 171:3a7713b1edbc 498 * @param src The value to set LPUART1 clock source.
AnnaBridge 171:3a7713b1edbc 499 */
AnnaBridge 171:3a7713b1edbc 500 static inline void CLOCK_SetLpuart1Clock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 501 {
AnnaBridge 171:3a7713b1edbc 502 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUART1SRC_MASK) | SIM_SOPT2_LPUART1SRC(src));
AnnaBridge 171:3a7713b1edbc 503 }
AnnaBridge 171:3a7713b1edbc 504
AnnaBridge 171:3a7713b1edbc 505 /*!
AnnaBridge 171:3a7713b1edbc 506 * @brief Set TPM clock source.
AnnaBridge 171:3a7713b1edbc 507 *
AnnaBridge 171:3a7713b1edbc 508 * @param src The value to set TPM clock source.
AnnaBridge 171:3a7713b1edbc 509 */
AnnaBridge 171:3a7713b1edbc 510 static inline void CLOCK_SetTpmClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 511 {
AnnaBridge 171:3a7713b1edbc 512 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src));
AnnaBridge 171:3a7713b1edbc 513 }
AnnaBridge 171:3a7713b1edbc 514
AnnaBridge 171:3a7713b1edbc 515 /*!
AnnaBridge 171:3a7713b1edbc 516 * @brief Set FLEXIO clock source.
AnnaBridge 171:3a7713b1edbc 517 *
AnnaBridge 171:3a7713b1edbc 518 * @param src The value to set FLEXIO clock source.
AnnaBridge 171:3a7713b1edbc 519 */
AnnaBridge 171:3a7713b1edbc 520 static inline void CLOCK_SetFlexio0Clock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 521 {
AnnaBridge 171:3a7713b1edbc 522 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_FLEXIOSRC_MASK) | SIM_SOPT2_FLEXIOSRC(src));
AnnaBridge 171:3a7713b1edbc 523 }
AnnaBridge 171:3a7713b1edbc 524
AnnaBridge 171:3a7713b1edbc 525 /*! @brief Enable USB FS clock.
AnnaBridge 171:3a7713b1edbc 526 *
AnnaBridge 171:3a7713b1edbc 527 * @param src USB FS clock source.
AnnaBridge 171:3a7713b1edbc 528 * @param freq The frequency specified by src.
AnnaBridge 171:3a7713b1edbc 529 * @retval true The clock is set successfully.
AnnaBridge 171:3a7713b1edbc 530 * @retval false The clock source is invalid to get proper USB FS clock.
AnnaBridge 171:3a7713b1edbc 531 */
AnnaBridge 171:3a7713b1edbc 532 bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
AnnaBridge 171:3a7713b1edbc 533
AnnaBridge 171:3a7713b1edbc 534 /*! @brief Disable USB FS clock.
AnnaBridge 171:3a7713b1edbc 535 *
AnnaBridge 171:3a7713b1edbc 536 * Disable USB FS clock.
AnnaBridge 171:3a7713b1edbc 537 */
AnnaBridge 171:3a7713b1edbc 538 static inline void CLOCK_DisableUsbfs0Clock(void)
AnnaBridge 171:3a7713b1edbc 539 {
AnnaBridge 171:3a7713b1edbc 540 CLOCK_DisableClock(kCLOCK_Usbfs0);
AnnaBridge 171:3a7713b1edbc 541 }
AnnaBridge 171:3a7713b1edbc 542
AnnaBridge 171:3a7713b1edbc 543 /*!
AnnaBridge 171:3a7713b1edbc 544 * @brief Set CLKOUT source.
AnnaBridge 171:3a7713b1edbc 545 *
AnnaBridge 171:3a7713b1edbc 546 * @param src The value to set CLKOUT source.
AnnaBridge 171:3a7713b1edbc 547 */
AnnaBridge 171:3a7713b1edbc 548 static inline void CLOCK_SetClkOutClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 549 {
AnnaBridge 171:3a7713b1edbc 550 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
AnnaBridge 171:3a7713b1edbc 551 }
AnnaBridge 171:3a7713b1edbc 552
AnnaBridge 171:3a7713b1edbc 553 /*!
AnnaBridge 171:3a7713b1edbc 554 * @brief Set RTC_CLKOUT source.
AnnaBridge 171:3a7713b1edbc 555 *
AnnaBridge 171:3a7713b1edbc 556 * @param src The value to set RTC_CLKOUT source.
AnnaBridge 171:3a7713b1edbc 557 */
AnnaBridge 171:3a7713b1edbc 558 static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
AnnaBridge 171:3a7713b1edbc 559 {
AnnaBridge 171:3a7713b1edbc 560 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
AnnaBridge 171:3a7713b1edbc 561 }
AnnaBridge 171:3a7713b1edbc 562
AnnaBridge 171:3a7713b1edbc 563 /*!
AnnaBridge 171:3a7713b1edbc 564 * @brief System clock divider
AnnaBridge 171:3a7713b1edbc 565 *
AnnaBridge 171:3a7713b1edbc 566 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV4].
AnnaBridge 171:3a7713b1edbc 567 *
AnnaBridge 171:3a7713b1edbc 568 * @param outdiv1 Clock 1 output divider value.
AnnaBridge 171:3a7713b1edbc 569 *
AnnaBridge 171:3a7713b1edbc 570 * @param outdiv4 Clock 4 output divider value.
AnnaBridge 171:3a7713b1edbc 571 */
AnnaBridge 171:3a7713b1edbc 572 static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv4)
AnnaBridge 171:3a7713b1edbc 573 {
AnnaBridge 171:3a7713b1edbc 574 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV4(outdiv4);
AnnaBridge 171:3a7713b1edbc 575 }
AnnaBridge 171:3a7713b1edbc 576
AnnaBridge 171:3a7713b1edbc 577 /*!
AnnaBridge 171:3a7713b1edbc 578 * @brief Gets the clock frequency for a specific clock name.
AnnaBridge 171:3a7713b1edbc 579 *
AnnaBridge 171:3a7713b1edbc 580 * This function checks the current clock configurations and then calculates
AnnaBridge 171:3a7713b1edbc 581 * the clock frequency for a specific clock name defined in clock_name_t.
AnnaBridge 171:3a7713b1edbc 582 * The MCG must be properly configured before using this function.
AnnaBridge 171:3a7713b1edbc 583 *
AnnaBridge 171:3a7713b1edbc 584 * @param clockName Clock names defined in clock_name_t
AnnaBridge 171:3a7713b1edbc 585 * @return Clock frequency value in Hertz
AnnaBridge 171:3a7713b1edbc 586 */
AnnaBridge 171:3a7713b1edbc 587 uint32_t CLOCK_GetFreq(clock_name_t clockName);
AnnaBridge 171:3a7713b1edbc 588
AnnaBridge 171:3a7713b1edbc 589 /*!
AnnaBridge 171:3a7713b1edbc 590 * @brief Get the core clock or system clock frequency.
AnnaBridge 171:3a7713b1edbc 591 *
AnnaBridge 171:3a7713b1edbc 592 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 593 */
AnnaBridge 171:3a7713b1edbc 594 uint32_t CLOCK_GetCoreSysClkFreq(void);
AnnaBridge 171:3a7713b1edbc 595
AnnaBridge 171:3a7713b1edbc 596 /*!
AnnaBridge 171:3a7713b1edbc 597 * @brief Get the platform clock frequency.
AnnaBridge 171:3a7713b1edbc 598 *
AnnaBridge 171:3a7713b1edbc 599 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 600 */
AnnaBridge 171:3a7713b1edbc 601 uint32_t CLOCK_GetPlatClkFreq(void);
AnnaBridge 171:3a7713b1edbc 602
AnnaBridge 171:3a7713b1edbc 603 /*!
AnnaBridge 171:3a7713b1edbc 604 * @brief Get the bus clock frequency.
AnnaBridge 171:3a7713b1edbc 605 *
AnnaBridge 171:3a7713b1edbc 606 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 607 */
AnnaBridge 171:3a7713b1edbc 608 uint32_t CLOCK_GetBusClkFreq(void);
AnnaBridge 171:3a7713b1edbc 609
AnnaBridge 171:3a7713b1edbc 610 /*!
AnnaBridge 171:3a7713b1edbc 611 * @brief Get the flash clock frequency.
AnnaBridge 171:3a7713b1edbc 612 *
AnnaBridge 171:3a7713b1edbc 613 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 614 */
AnnaBridge 171:3a7713b1edbc 615 uint32_t CLOCK_GetFlashClkFreq(void);
AnnaBridge 171:3a7713b1edbc 616
AnnaBridge 171:3a7713b1edbc 617 /*!
AnnaBridge 171:3a7713b1edbc 618 * @brief Get the external reference 32K clock frequency (ERCLK32K).
AnnaBridge 171:3a7713b1edbc 619 *
AnnaBridge 171:3a7713b1edbc 620 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 621 */
AnnaBridge 171:3a7713b1edbc 622 uint32_t CLOCK_GetEr32kClkFreq(void);
AnnaBridge 171:3a7713b1edbc 623
AnnaBridge 171:3a7713b1edbc 624 /*!
AnnaBridge 171:3a7713b1edbc 625 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
AnnaBridge 171:3a7713b1edbc 626 *
AnnaBridge 171:3a7713b1edbc 627 * @return Clock frequency in Hz.
AnnaBridge 171:3a7713b1edbc 628 */
AnnaBridge 171:3a7713b1edbc 629 uint32_t CLOCK_GetOsc0ErClkFreq(void);
AnnaBridge 171:3a7713b1edbc 630
AnnaBridge 171:3a7713b1edbc 631 /*!
AnnaBridge 171:3a7713b1edbc 632 * @brief Set the clock configure in SIM module.
AnnaBridge 171:3a7713b1edbc 633 *
AnnaBridge 171:3a7713b1edbc 634 * This function sets system layer clock settings in SIM module.
AnnaBridge 171:3a7713b1edbc 635 *
AnnaBridge 171:3a7713b1edbc 636 * @param config Pointer to the configure structure.
AnnaBridge 171:3a7713b1edbc 637 */
AnnaBridge 171:3a7713b1edbc 638 void CLOCK_SetSimConfig(sim_clock_config_t const *config);
AnnaBridge 171:3a7713b1edbc 639
AnnaBridge 171:3a7713b1edbc 640 /*!
AnnaBridge 171:3a7713b1edbc 641 * @brief Set the system clock dividers in SIM to safe value.
AnnaBridge 171:3a7713b1edbc 642 *
AnnaBridge 171:3a7713b1edbc 643 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
AnnaBridge 171:3a7713b1edbc 644 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
AnnaBridge 171:3a7713b1edbc 645 * changes then the system level clocks may be out of range. This function could
AnnaBridge 171:3a7713b1edbc 646 * be used before MCG mode change, to make sure system level clocks are in allowed
AnnaBridge 171:3a7713b1edbc 647 * range.
AnnaBridge 171:3a7713b1edbc 648 *
AnnaBridge 171:3a7713b1edbc 649 * @param config Pointer to the configure structure.
AnnaBridge 171:3a7713b1edbc 650 */
AnnaBridge 171:3a7713b1edbc 651 static inline void CLOCK_SetSimSafeDivs(void)
AnnaBridge 171:3a7713b1edbc 652 {
AnnaBridge 171:3a7713b1edbc 653 SIM->CLKDIV1 = 0x10030000U;
AnnaBridge 171:3a7713b1edbc 654 }
AnnaBridge 171:3a7713b1edbc 655
AnnaBridge 171:3a7713b1edbc 656 /*!
AnnaBridge 171:3a7713b1edbc 657 * @name MCG_Lite clock frequency
AnnaBridge 171:3a7713b1edbc 658 * @{
AnnaBridge 171:3a7713b1edbc 659 */
AnnaBridge 171:3a7713b1edbc 660
AnnaBridge 171:3a7713b1edbc 661 /*!
AnnaBridge 171:3a7713b1edbc 662 * @brief Gets the MCG_Lite output clock (MCGOUTCLK) frequency.
AnnaBridge 171:3a7713b1edbc 663 *
AnnaBridge 171:3a7713b1edbc 664 * This function gets the MCG_Lite output clock frequency (Hz) based on the current
AnnaBridge 171:3a7713b1edbc 665 * MCG_Lite register value.
AnnaBridge 171:3a7713b1edbc 666 *
AnnaBridge 171:3a7713b1edbc 667 * @return The frequency of MCGOUTCLK.
AnnaBridge 171:3a7713b1edbc 668 */
AnnaBridge 171:3a7713b1edbc 669 uint32_t CLOCK_GetOutClkFreq(void);
AnnaBridge 171:3a7713b1edbc 670
AnnaBridge 171:3a7713b1edbc 671 /*!
AnnaBridge 171:3a7713b1edbc 672 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
AnnaBridge 171:3a7713b1edbc 673 *
AnnaBridge 171:3a7713b1edbc 674 * This function gets the MCG_Lite internal reference clock frequency (Hz) based
AnnaBridge 171:3a7713b1edbc 675 * on the current MCG register value.
AnnaBridge 171:3a7713b1edbc 676 *
AnnaBridge 171:3a7713b1edbc 677 * @return The frequency of MCGIRCLK.
AnnaBridge 171:3a7713b1edbc 678 */
AnnaBridge 171:3a7713b1edbc 679 uint32_t CLOCK_GetInternalRefClkFreq(void);
AnnaBridge 171:3a7713b1edbc 680
AnnaBridge 171:3a7713b1edbc 681 /*!
AnnaBridge 171:3a7713b1edbc 682 * @brief Gets the current MCGPCLK frequency.
AnnaBridge 171:3a7713b1edbc 683 *
AnnaBridge 171:3a7713b1edbc 684 * This function gets the MCGPCLK frequency (Hertz) based on the current MCG_Lite
AnnaBridge 171:3a7713b1edbc 685 * register settings.
AnnaBridge 171:3a7713b1edbc 686 *
AnnaBridge 171:3a7713b1edbc 687 * @return The frequency of MCGPCLK.
AnnaBridge 171:3a7713b1edbc 688 */
AnnaBridge 171:3a7713b1edbc 689 uint32_t CLOCK_GetPeriphClkFreq(void);
AnnaBridge 171:3a7713b1edbc 690
AnnaBridge 171:3a7713b1edbc 691 /*! @}*/
AnnaBridge 171:3a7713b1edbc 692
AnnaBridge 171:3a7713b1edbc 693 /*!
AnnaBridge 171:3a7713b1edbc 694 * @name MCG_Lite mode.
AnnaBridge 171:3a7713b1edbc 695 * @{
AnnaBridge 171:3a7713b1edbc 696 */
AnnaBridge 171:3a7713b1edbc 697
AnnaBridge 171:3a7713b1edbc 698 /*!
AnnaBridge 171:3a7713b1edbc 699 * @brief Gets the current MCG_Lite mode.
AnnaBridge 171:3a7713b1edbc 700 *
AnnaBridge 171:3a7713b1edbc 701 * This function checks the MCG_Lite registers and determines the current MCG_Lite mode.
AnnaBridge 171:3a7713b1edbc 702 *
AnnaBridge 171:3a7713b1edbc 703 * @return Current MCG_Lite mode or error code.
AnnaBridge 171:3a7713b1edbc 704 */
AnnaBridge 171:3a7713b1edbc 705 mcglite_mode_t CLOCK_GetMode(void);
AnnaBridge 171:3a7713b1edbc 706
AnnaBridge 171:3a7713b1edbc 707 /*!
AnnaBridge 171:3a7713b1edbc 708 * @brief Sets the MCG_Lite configuration.
AnnaBridge 171:3a7713b1edbc 709 *
AnnaBridge 171:3a7713b1edbc 710 * This function configures the MCG_Lite, include output clock source, MCGIRCLK
AnnaBridge 171:3a7713b1edbc 711 * setting, HIRC setting and so on, see @ref mcglite_config_t for details.
AnnaBridge 171:3a7713b1edbc 712 *
AnnaBridge 171:3a7713b1edbc 713 * @param targetConfig Pointer to the target MCG_Lite mode configuration structure.
AnnaBridge 171:3a7713b1edbc 714 * @return Error code.
AnnaBridge 171:3a7713b1edbc 715 */
AnnaBridge 171:3a7713b1edbc 716 status_t CLOCK_SetMcgliteConfig(mcglite_config_t const *targetConfig);
AnnaBridge 171:3a7713b1edbc 717
AnnaBridge 171:3a7713b1edbc 718 /*! @}*/
AnnaBridge 171:3a7713b1edbc 719
AnnaBridge 171:3a7713b1edbc 720 /*!
AnnaBridge 171:3a7713b1edbc 721 * @name OSC configuration
AnnaBridge 171:3a7713b1edbc 722 * @{
AnnaBridge 171:3a7713b1edbc 723 */
AnnaBridge 171:3a7713b1edbc 724
AnnaBridge 171:3a7713b1edbc 725 /*!
AnnaBridge 171:3a7713b1edbc 726 * @brief Configures the OSC external reference clock (OSCERCLK).
AnnaBridge 171:3a7713b1edbc 727 *
AnnaBridge 171:3a7713b1edbc 728 * This function configures the OSC external reference clock (OSCERCLK).
AnnaBridge 171:3a7713b1edbc 729 * For example, to enable the OSCERCLK in normal mode and stop mode, and also set
AnnaBridge 171:3a7713b1edbc 730 * the output divider to 1, as follows:
AnnaBridge 171:3a7713b1edbc 731 *
AnnaBridge 171:3a7713b1edbc 732 @code
AnnaBridge 171:3a7713b1edbc 733 oscer_config_t config =
AnnaBridge 171:3a7713b1edbc 734 {
AnnaBridge 171:3a7713b1edbc 735 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
AnnaBridge 171:3a7713b1edbc 736 .erclkDiv = 1U,
AnnaBridge 171:3a7713b1edbc 737 };
AnnaBridge 171:3a7713b1edbc 738
AnnaBridge 171:3a7713b1edbc 739 OSC_SetExtRefClkConfig(OSC, &config);
AnnaBridge 171:3a7713b1edbc 740 @endcode
AnnaBridge 171:3a7713b1edbc 741 *
AnnaBridge 171:3a7713b1edbc 742 * @param base OSC peripheral address.
AnnaBridge 171:3a7713b1edbc 743 * @param config Pointer to the configuration structure.
AnnaBridge 171:3a7713b1edbc 744 */
AnnaBridge 171:3a7713b1edbc 745 static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
AnnaBridge 171:3a7713b1edbc 746 {
AnnaBridge 171:3a7713b1edbc 747 uint8_t reg = base->CR;
AnnaBridge 171:3a7713b1edbc 748
AnnaBridge 171:3a7713b1edbc 749 reg &= ~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK);
AnnaBridge 171:3a7713b1edbc 750 reg |= config->enableMode;
AnnaBridge 171:3a7713b1edbc 751
AnnaBridge 171:3a7713b1edbc 752 base->CR = reg;
AnnaBridge 171:3a7713b1edbc 753 }
AnnaBridge 171:3a7713b1edbc 754
AnnaBridge 171:3a7713b1edbc 755 /*!
AnnaBridge 171:3a7713b1edbc 756 * @brief Sets the capacitor load configuration for the oscillator.
AnnaBridge 171:3a7713b1edbc 757 *
AnnaBridge 171:3a7713b1edbc 758 * This function sets the specified capacitors configuration for the oscillator.
AnnaBridge 171:3a7713b1edbc 759 * This should be done in the early system level initialization function call
AnnaBridge 171:3a7713b1edbc 760 * based on the system configuration.
AnnaBridge 171:3a7713b1edbc 761 *
AnnaBridge 171:3a7713b1edbc 762 * @param base OSC peripheral address.
AnnaBridge 171:3a7713b1edbc 763 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
AnnaBridge 171:3a7713b1edbc 764 *
AnnaBridge 171:3a7713b1edbc 765 * Example:
AnnaBridge 171:3a7713b1edbc 766 @code
AnnaBridge 171:3a7713b1edbc 767 // To enable only 2 pF and 8 pF capacitor load, please use like this.
AnnaBridge 171:3a7713b1edbc 768 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
AnnaBridge 171:3a7713b1edbc 769 @endcode
AnnaBridge 171:3a7713b1edbc 770 */
AnnaBridge 171:3a7713b1edbc 771
AnnaBridge 171:3a7713b1edbc 772 static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
AnnaBridge 171:3a7713b1edbc 773 {
AnnaBridge 171:3a7713b1edbc 774 uint8_t reg = base->CR;
AnnaBridge 171:3a7713b1edbc 775
AnnaBridge 171:3a7713b1edbc 776 reg &= ~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK);
AnnaBridge 171:3a7713b1edbc 777 reg |= capLoad;
AnnaBridge 171:3a7713b1edbc 778
AnnaBridge 171:3a7713b1edbc 779 base->CR = reg;
AnnaBridge 171:3a7713b1edbc 780 }
AnnaBridge 171:3a7713b1edbc 781
AnnaBridge 171:3a7713b1edbc 782 /*!
AnnaBridge 171:3a7713b1edbc 783 * @brief Initialize OSC0.
AnnaBridge 171:3a7713b1edbc 784 *
AnnaBridge 171:3a7713b1edbc 785 * This function initializes the OSC0 according to the board configuration.
AnnaBridge 171:3a7713b1edbc 786 *
AnnaBridge 171:3a7713b1edbc 787 * @param config Pointer to the OSC0 configuration structure.
AnnaBridge 171:3a7713b1edbc 788 */
AnnaBridge 171:3a7713b1edbc 789 void CLOCK_InitOsc0(osc_config_t const *config);
AnnaBridge 171:3a7713b1edbc 790
AnnaBridge 171:3a7713b1edbc 791 /*!
AnnaBridge 171:3a7713b1edbc 792 * @brief Deinitializes the OSC0.
AnnaBridge 171:3a7713b1edbc 793 *
AnnaBridge 171:3a7713b1edbc 794 * This function deinitializes the OSC0.
AnnaBridge 171:3a7713b1edbc 795 */
AnnaBridge 171:3a7713b1edbc 796 void CLOCK_DeinitOsc0(void);
AnnaBridge 171:3a7713b1edbc 797
AnnaBridge 171:3a7713b1edbc 798 /*! @}*/
AnnaBridge 171:3a7713b1edbc 799
AnnaBridge 171:3a7713b1edbc 800 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 801 }
AnnaBridge 171:3a7713b1edbc 802 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 803
AnnaBridge 171:3a7713b1edbc 804 /*! @} */
AnnaBridge 171:3a7713b1edbc 805
AnnaBridge 171:3a7713b1edbc 806 #endif /* _FSL_CLOCK_H_ */