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TARGET_KL27Z/TOOLCHAIN_ARM_STD/MKL27Z644_features.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/*
AnnaBridge	171:3a7713b1edbc	2	** ###################################################################
AnnaBridge	171:3a7713b1edbc	3	** Version: rev. 1.8, 2015-05-27
AnnaBridge	171:3a7713b1edbc	4	** Build: b151216
AnnaBridge	171:3a7713b1edbc	5	**
AnnaBridge	171:3a7713b1edbc	6	** Abstract:
AnnaBridge	171:3a7713b1edbc	7	** Chip specific module features.
AnnaBridge	171:3a7713b1edbc	8	**
AnnaBridge	171:3a7713b1edbc	9	** Copyright (c) 2015 Freescale Semiconductor, Inc.
AnnaBridge	171:3a7713b1edbc	10	** All rights reserved.
AnnaBridge	171:3a7713b1edbc	11	**
AnnaBridge	171:3a7713b1edbc	12	** Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	13	** are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	14	**
AnnaBridge	171:3a7713b1edbc	15	** o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge	171:3a7713b1edbc	16	** of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	17	**
AnnaBridge	171:3a7713b1edbc	18	** o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge	171:3a7713b1edbc	19	** list of conditions and the following disclaimer in the documentation and/or
AnnaBridge	171:3a7713b1edbc	20	** other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	21	**
AnnaBridge	171:3a7713b1edbc	22	** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge	171:3a7713b1edbc	23	** contributors may be used to endorse or promote products derived from this
AnnaBridge	171:3a7713b1edbc	24	** software without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	25	**
AnnaBridge	171:3a7713b1edbc	26	** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge	171:3a7713b1edbc	27	** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge	171:3a7713b1edbc	28	** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	29	** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge	171:3a7713b1edbc	30	** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge	171:3a7713b1edbc	31	** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge	171:3a7713b1edbc	32	** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge	171:3a7713b1edbc	33	** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge	171:3a7713b1edbc	34	** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge	171:3a7713b1edbc	35	** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	36	**
AnnaBridge	171:3a7713b1edbc	37	** http: www.freescale.com
AnnaBridge	171:3a7713b1edbc	38	** mail: support@freescale.com
AnnaBridge	171:3a7713b1edbc	39	**
AnnaBridge	171:3a7713b1edbc	40	** Revisions:
AnnaBridge	171:3a7713b1edbc	41	** - rev. 1.0 (2014-05-12)
AnnaBridge	171:3a7713b1edbc	42	** Initial version.
AnnaBridge	171:3a7713b1edbc	43	** - rev. 1.1 (2014-07-10)
AnnaBridge	171:3a7713b1edbc	44	** UART0 - UART0 module renamed to UART2.
AnnaBridge	171:3a7713b1edbc	45	** - rev. 1.2 (2014-08-12)
AnnaBridge	171:3a7713b1edbc	46	** CRC - CRC register renamed to DATA.
AnnaBridge	171:3a7713b1edbc	47	** - rev. 1.3 (2014-09-02)
AnnaBridge	171:3a7713b1edbc	48	** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
AnnaBridge	171:3a7713b1edbc	49	** USB - USB0_CTL1 was renamed to USB0_CTL register.
AnnaBridge	171:3a7713b1edbc	50	** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register.
AnnaBridge	171:3a7713b1edbc	51	** - rev. 1.4 (2014-09-22)
AnnaBridge	171:3a7713b1edbc	52	** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers.
AnnaBridge	171:3a7713b1edbc	53	** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
AnnaBridge	171:3a7713b1edbc	54	** SIM - Removed bitfield DIEID in SDID register.
AnnaBridge	171:3a7713b1edbc	55	** UART2 - Removed ED register.
AnnaBridge	171:3a7713b1edbc	56	** UART2 - Removed MODEM register.
AnnaBridge	171:3a7713b1edbc	57	** UART2 - Removed IR register.
AnnaBridge	171:3a7713b1edbc	58	** UART2 - Removed PFIFO register.
AnnaBridge	171:3a7713b1edbc	59	** UART2 - Removed CFIFO register.
AnnaBridge	171:3a7713b1edbc	60	** UART2 - Removed SFIFO register.
AnnaBridge	171:3a7713b1edbc	61	** UART2 - Removed TWFIFO register.
AnnaBridge	171:3a7713b1edbc	62	** UART2 - Removed TCFIFO register.
AnnaBridge	171:3a7713b1edbc	63	** UART2 - Removed RWFIFO register.
AnnaBridge	171:3a7713b1edbc	64	** UART2 - Removed RCFIFO register.
AnnaBridge	171:3a7713b1edbc	65	** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
AnnaBridge	171:3a7713b1edbc	66	** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
AnnaBridge	171:3a7713b1edbc	67	** - rev. 1.5 (2015-01-21)
AnnaBridge	171:3a7713b1edbc	68	** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
AnnaBridge	171:3a7713b1edbc	69	** - rev. 1.6 (2015-05-19)
AnnaBridge	171:3a7713b1edbc	70	** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
AnnaBridge	171:3a7713b1edbc	71	** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
AnnaBridge	171:3a7713b1edbc	72	** Added features for PORT.
AnnaBridge	171:3a7713b1edbc	73	** - rev. 1.7 (2015-05-25)
AnnaBridge	171:3a7713b1edbc	74	** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
AnnaBridge	171:3a7713b1edbc	75	** - rev. 1.8 (2015-05-27)
AnnaBridge	171:3a7713b1edbc	76	** Several USB features added.
AnnaBridge	171:3a7713b1edbc	77	**
AnnaBridge	171:3a7713b1edbc	78	** ###################################################################
AnnaBridge	171:3a7713b1edbc	79	*/
AnnaBridge	171:3a7713b1edbc	80
AnnaBridge	171:3a7713b1edbc	81	#ifndef _MKL27Z644_FEATURES_H_
AnnaBridge	171:3a7713b1edbc	82	#define _MKL27Z644_FEATURES_H_
AnnaBridge	171:3a7713b1edbc	83
AnnaBridge	171:3a7713b1edbc	84	/* SOC module features */
AnnaBridge	171:3a7713b1edbc	85
AnnaBridge	171:3a7713b1edbc	86	/* @brief ACMP availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	87	#define FSL_FEATURE_SOC_ACMP_COUNT (0)
AnnaBridge	171:3a7713b1edbc	88	/* @brief ADC16 availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	89	#define FSL_FEATURE_SOC_ADC16_COUNT (1)
AnnaBridge	171:3a7713b1edbc	90	/* @brief ADC12 availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	91	#define FSL_FEATURE_SOC_ADC12_COUNT (0)
AnnaBridge	171:3a7713b1edbc	92	/* @brief AFE availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	93	#define FSL_FEATURE_SOC_AFE_COUNT (0)
AnnaBridge	171:3a7713b1edbc	94	/* @brief AIPS availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	95	#define FSL_FEATURE_SOC_AIPS_COUNT (0)
AnnaBridge	171:3a7713b1edbc	96	/* @brief AOI availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	97	#define FSL_FEATURE_SOC_AOI_COUNT (0)
AnnaBridge	171:3a7713b1edbc	98	/* @brief AXBS availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	99	#define FSL_FEATURE_SOC_AXBS_COUNT (0)
AnnaBridge	171:3a7713b1edbc	100	/* @brief ASMC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	101	#define FSL_FEATURE_SOC_ASMC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	102	/* @brief CADC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	103	#define FSL_FEATURE_SOC_CADC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	104	/* @brief FLEXCAN availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	105	#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
AnnaBridge	171:3a7713b1edbc	106	/* @brief MMCAU availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	107	#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
AnnaBridge	171:3a7713b1edbc	108	/* @brief CMP availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	109	#define FSL_FEATURE_SOC_CMP_COUNT (1)
AnnaBridge	171:3a7713b1edbc	110	/* @brief CMT availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	111	#define FSL_FEATURE_SOC_CMT_COUNT (0)
AnnaBridge	171:3a7713b1edbc	112	/* @brief CNC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	113	#define FSL_FEATURE_SOC_CNC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	114	/* @brief CRC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	115	#define FSL_FEATURE_SOC_CRC_COUNT (1)
AnnaBridge	171:3a7713b1edbc	116	/* @brief DAC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	117	#define FSL_FEATURE_SOC_DAC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	118	/* @brief DAC32 availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	119	#define FSL_FEATURE_SOC_DAC32_COUNT (0)
AnnaBridge	171:3a7713b1edbc	120	/* @brief DCDC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	121	#define FSL_FEATURE_SOC_DCDC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	122	/* @brief DDR availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	123	#define FSL_FEATURE_SOC_DDR_COUNT (0)
AnnaBridge	171:3a7713b1edbc	124	/* @brief DMA availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	125	#define FSL_FEATURE_SOC_DMA_COUNT (1)
AnnaBridge	171:3a7713b1edbc	126	/* @brief EDMA availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	127	#define FSL_FEATURE_SOC_EDMA_COUNT (0)
AnnaBridge	171:3a7713b1edbc	128	/* @brief DMAMUX availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	129	#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
AnnaBridge	171:3a7713b1edbc	130	/* @brief DRY availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	131	#define FSL_FEATURE_SOC_DRY_COUNT (0)
AnnaBridge	171:3a7713b1edbc	132	/* @brief DSPI availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	133	#define FSL_FEATURE_SOC_DSPI_COUNT (0)
AnnaBridge	171:3a7713b1edbc	134	/* @brief EMVSIM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	135	#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
AnnaBridge	171:3a7713b1edbc	136	/* @brief ENC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	137	#define FSL_FEATURE_SOC_ENC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	138	/* @brief ENET availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	139	#define FSL_FEATURE_SOC_ENET_COUNT (0)
AnnaBridge	171:3a7713b1edbc	140	/* @brief EWM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	141	#define FSL_FEATURE_SOC_EWM_COUNT (0)
AnnaBridge	171:3a7713b1edbc	142	/* @brief FB availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	143	#define FSL_FEATURE_SOC_FB_COUNT (0)
AnnaBridge	171:3a7713b1edbc	144	/* @brief FGPIO availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	145	#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
AnnaBridge	171:3a7713b1edbc	146	/* @brief FLEXIO availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	147	#define FSL_FEATURE_SOC_FLEXIO_COUNT (1)
AnnaBridge	171:3a7713b1edbc	148	/* @brief FMC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	149	#define FSL_FEATURE_SOC_FMC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	150	/* @brief FSKDT availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	151	#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
AnnaBridge	171:3a7713b1edbc	152	/* @brief FTFA availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	153	#define FSL_FEATURE_SOC_FTFA_COUNT (1)
AnnaBridge	171:3a7713b1edbc	154	/* @brief FTFE availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	155	#define FSL_FEATURE_SOC_FTFE_COUNT (0)
AnnaBridge	171:3a7713b1edbc	156	/* @brief FTFL availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	157	#define FSL_FEATURE_SOC_FTFL_COUNT (0)
AnnaBridge	171:3a7713b1edbc	158	/* @brief FTM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	159	#define FSL_FEATURE_SOC_FTM_COUNT (0)
AnnaBridge	171:3a7713b1edbc	160	/* @brief FTMRA availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	161	#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
AnnaBridge	171:3a7713b1edbc	162	/* @brief FTMRE availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	163	#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
AnnaBridge	171:3a7713b1edbc	164	/* @brief FTMRH availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	165	#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
AnnaBridge	171:3a7713b1edbc	166	/* @brief GPIO availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	167	#define FSL_FEATURE_SOC_GPIO_COUNT (5)
AnnaBridge	171:3a7713b1edbc	168	/* @brief HSADC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	169	#define FSL_FEATURE_SOC_HSADC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	170	/* @brief I2C availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	171	#define FSL_FEATURE_SOC_I2C_COUNT (2)
AnnaBridge	171:3a7713b1edbc	172	/* @brief I2S availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	173	#define FSL_FEATURE_SOC_I2S_COUNT (0)
AnnaBridge	171:3a7713b1edbc	174	/* @brief ICS availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	175	#define FSL_FEATURE_SOC_ICS_COUNT (0)
AnnaBridge	171:3a7713b1edbc	176	/* @brief INTMUX availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	177	#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
AnnaBridge	171:3a7713b1edbc	178	/* @brief IRQ availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	179	#define FSL_FEATURE_SOC_IRQ_COUNT (0)
AnnaBridge	171:3a7713b1edbc	180	/* @brief KBI availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	181	#define FSL_FEATURE_SOC_KBI_COUNT (0)
AnnaBridge	171:3a7713b1edbc	182	/* @brief SLCD availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	183	#define FSL_FEATURE_SOC_SLCD_COUNT (0)
AnnaBridge	171:3a7713b1edbc	184	/* @brief LCDC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	185	#define FSL_FEATURE_SOC_LCDC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	186	/* @brief LDO availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	187	#define FSL_FEATURE_SOC_LDO_COUNT (0)
AnnaBridge	171:3a7713b1edbc	188	/* @brief LLWU availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	189	#define FSL_FEATURE_SOC_LLWU_COUNT (1)
AnnaBridge	171:3a7713b1edbc	190	/* @brief LMEM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	191	#define FSL_FEATURE_SOC_LMEM_COUNT (0)
AnnaBridge	171:3a7713b1edbc	192	/* @brief LPI2C availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	193	#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
AnnaBridge	171:3a7713b1edbc	194	/* @brief LPIT availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	195	#define FSL_FEATURE_SOC_LPIT_COUNT (0)
AnnaBridge	171:3a7713b1edbc	196	/* @brief LPSCI availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	197	#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
AnnaBridge	171:3a7713b1edbc	198	/* @brief LPSPI availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	199	#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
AnnaBridge	171:3a7713b1edbc	200	/* @brief LPTMR availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	201	#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
AnnaBridge	171:3a7713b1edbc	202	/* @brief LPTPM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	203	#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
AnnaBridge	171:3a7713b1edbc	204	/* @brief LPUART availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	205	#define FSL_FEATURE_SOC_LPUART_COUNT (2)
AnnaBridge	171:3a7713b1edbc	206	/* @brief LTC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	207	#define FSL_FEATURE_SOC_LTC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	208	/* @brief MC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	209	#define FSL_FEATURE_SOC_MC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	210	/* @brief MCG availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	211	#define FSL_FEATURE_SOC_MCG_COUNT (0)
AnnaBridge	171:3a7713b1edbc	212	/* @brief MCGLITE availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	213	#define FSL_FEATURE_SOC_MCGLITE_COUNT (1)
AnnaBridge	171:3a7713b1edbc	214	/* @brief MCM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	215	#define FSL_FEATURE_SOC_MCM_COUNT (1)
AnnaBridge	171:3a7713b1edbc	216	/* @brief MMAU availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	217	#define FSL_FEATURE_SOC_MMAU_COUNT (0)
AnnaBridge	171:3a7713b1edbc	218	/* @brief MMDVSQ availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	219	#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
AnnaBridge	171:3a7713b1edbc	220	/* @brief MPU availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	221	#define FSL_FEATURE_SOC_MPU_COUNT (0)
AnnaBridge	171:3a7713b1edbc	222	/* @brief MSCAN availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	223	#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
AnnaBridge	171:3a7713b1edbc	224	/* @brief MSCM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	225	#define FSL_FEATURE_SOC_MSCM_COUNT (0)
AnnaBridge	171:3a7713b1edbc	226	/* @brief MTB availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	227	#define FSL_FEATURE_SOC_MTB_COUNT (1)
AnnaBridge	171:3a7713b1edbc	228	/* @brief MTBDWT availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	229	#define FSL_FEATURE_SOC_MTBDWT_COUNT (1)
AnnaBridge	171:3a7713b1edbc	230	/* @brief MU availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	231	#define FSL_FEATURE_SOC_MU_COUNT (0)
AnnaBridge	171:3a7713b1edbc	232	/* @brief NFC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	233	#define FSL_FEATURE_SOC_NFC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	234	/* @brief OPAMP availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	235	#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
AnnaBridge	171:3a7713b1edbc	236	/* @brief OSC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	237	#define FSL_FEATURE_SOC_OSC_COUNT (1)
AnnaBridge	171:3a7713b1edbc	238	/* @brief OSC32 availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	239	#define FSL_FEATURE_SOC_OSC32_COUNT (0)
AnnaBridge	171:3a7713b1edbc	240	/* @brief OTFAD availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	241	#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
AnnaBridge	171:3a7713b1edbc	242	/* @brief PDB availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	243	#define FSL_FEATURE_SOC_PDB_COUNT (0)
AnnaBridge	171:3a7713b1edbc	244	/* @brief PCC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	245	#define FSL_FEATURE_SOC_PCC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	246	/* @brief PGA availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	247	#define FSL_FEATURE_SOC_PGA_COUNT (0)
AnnaBridge	171:3a7713b1edbc	248	/* @brief PIT availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	249	#define FSL_FEATURE_SOC_PIT_COUNT (1)
AnnaBridge	171:3a7713b1edbc	250	/* @brief PMC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	251	#define FSL_FEATURE_SOC_PMC_COUNT (1)
AnnaBridge	171:3a7713b1edbc	252	/* @brief PORT availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	253	#define FSL_FEATURE_SOC_PORT_COUNT (5)
AnnaBridge	171:3a7713b1edbc	254	/* @brief PWM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	255	#define FSL_FEATURE_SOC_PWM_COUNT (0)
AnnaBridge	171:3a7713b1edbc	256	/* @brief PWT availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	257	#define FSL_FEATURE_SOC_PWT_COUNT (0)
AnnaBridge	171:3a7713b1edbc	258	/* @brief QuadSPI availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	259	#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
AnnaBridge	171:3a7713b1edbc	260	/* @brief RCM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	261	#define FSL_FEATURE_SOC_RCM_COUNT (1)
AnnaBridge	171:3a7713b1edbc	262	/* @brief RFSYS availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	263	#define FSL_FEATURE_SOC_RFSYS_COUNT (0)
AnnaBridge	171:3a7713b1edbc	264	/* @brief RFVBAT availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	265	#define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
AnnaBridge	171:3a7713b1edbc	266	/* @brief RNG availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	267	#define FSL_FEATURE_SOC_RNG_COUNT (0)
AnnaBridge	171:3a7713b1edbc	268	/* @brief RNGB availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	269	#define FSL_FEATURE_SOC_RNGB_COUNT (0)
AnnaBridge	171:3a7713b1edbc	270	/* @brief ROM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	271	#define FSL_FEATURE_SOC_ROM_COUNT (1)
AnnaBridge	171:3a7713b1edbc	272	/* @brief RSIM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	273	#define FSL_FEATURE_SOC_RSIM_COUNT (0)
AnnaBridge	171:3a7713b1edbc	274	/* @brief RTC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	275	#define FSL_FEATURE_SOC_RTC_COUNT (1)
AnnaBridge	171:3a7713b1edbc	276	/* @brief SCG availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	277	#define FSL_FEATURE_SOC_SCG_COUNT (0)
AnnaBridge	171:3a7713b1edbc	278	/* @brief SCI availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	279	#define FSL_FEATURE_SOC_SCI_COUNT (0)
AnnaBridge	171:3a7713b1edbc	280	/* @brief SDHC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	281	#define FSL_FEATURE_SOC_SDHC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	282	/* @brief SDRAM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	283	#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
AnnaBridge	171:3a7713b1edbc	284	/* @brief SEMA42 availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	285	#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
AnnaBridge	171:3a7713b1edbc	286	/* @brief SIM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	287	#define FSL_FEATURE_SOC_SIM_COUNT (1)
AnnaBridge	171:3a7713b1edbc	288	/* @brief SMC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	289	#define FSL_FEATURE_SOC_SMC_COUNT (1)
AnnaBridge	171:3a7713b1edbc	290	/* @brief SPI availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	291	#define FSL_FEATURE_SOC_SPI_COUNT (2)
AnnaBridge	171:3a7713b1edbc	292	/* @brief TMR availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	293	#define FSL_FEATURE_SOC_TMR_COUNT (0)
AnnaBridge	171:3a7713b1edbc	294	/* @brief TPM availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	295	#define FSL_FEATURE_SOC_TPM_COUNT (3)
AnnaBridge	171:3a7713b1edbc	296	/* @brief TRGMUX availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	297	#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
AnnaBridge	171:3a7713b1edbc	298	/* @brief TRIAMP availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	299	#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
AnnaBridge	171:3a7713b1edbc	300	/* @brief TRNG availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	301	#define FSL_FEATURE_SOC_TRNG_COUNT (0)
AnnaBridge	171:3a7713b1edbc	302	/* @brief TSI availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	303	#define FSL_FEATURE_SOC_TSI_COUNT (0)
AnnaBridge	171:3a7713b1edbc	304	/* @brief TSTMR availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	305	#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
AnnaBridge	171:3a7713b1edbc	306	/* @brief UART availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	307	#define FSL_FEATURE_SOC_UART_COUNT (1)
AnnaBridge	171:3a7713b1edbc	308	/* @brief USB availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	309	#define FSL_FEATURE_SOC_USB_COUNT (1)
AnnaBridge	171:3a7713b1edbc	310	/* @brief USBDCD availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	311	#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
AnnaBridge	171:3a7713b1edbc	312	/* @brief USBHSDCD availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	313	#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
AnnaBridge	171:3a7713b1edbc	314	/* @brief USBPHY availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	315	#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
AnnaBridge	171:3a7713b1edbc	316	/* @brief VREF availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	317	#define FSL_FEATURE_SOC_VREF_COUNT (1)
AnnaBridge	171:3a7713b1edbc	318	/* @brief WDOG availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	319	#define FSL_FEATURE_SOC_WDOG_COUNT (0)
AnnaBridge	171:3a7713b1edbc	320	/* @brief XBAR availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	321	#define FSL_FEATURE_SOC_XBAR_COUNT (0)
AnnaBridge	171:3a7713b1edbc	322	/* @brief XBARA availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	323	#define FSL_FEATURE_SOC_XBARA_COUNT (0)
AnnaBridge	171:3a7713b1edbc	324	/* @brief XBARB availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	325	#define FSL_FEATURE_SOC_XBARB_COUNT (0)
AnnaBridge	171:3a7713b1edbc	326	/* @brief XCVR availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	327	#define FSL_FEATURE_SOC_XCVR_COUNT (0)
AnnaBridge	171:3a7713b1edbc	328	/* @brief XRDC availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	329	#define FSL_FEATURE_SOC_XRDC_COUNT (0)
AnnaBridge	171:3a7713b1edbc	330	/* @brief ZLL availability on the SoC. */
AnnaBridge	171:3a7713b1edbc	331	#define FSL_FEATURE_SOC_ZLL_COUNT (0)
AnnaBridge	171:3a7713b1edbc	332
AnnaBridge	171:3a7713b1edbc	333	/* ADC16 module features */
AnnaBridge	171:3a7713b1edbc	334
AnnaBridge	171:3a7713b1edbc	335	/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
AnnaBridge	171:3a7713b1edbc	336	#define FSL_FEATURE_ADC16_HAS_PGA (0)
AnnaBridge	171:3a7713b1edbc	337	/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
AnnaBridge	171:3a7713b1edbc	338	#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
AnnaBridge	171:3a7713b1edbc	339	/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
AnnaBridge	171:3a7713b1edbc	340	#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
AnnaBridge	171:3a7713b1edbc	341	/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
AnnaBridge	171:3a7713b1edbc	342	#define FSL_FEATURE_ADC16_HAS_DMA (1)
AnnaBridge	171:3a7713b1edbc	343	/* @brief Has differential mode (bitfield SC1x[DIFF]). */
AnnaBridge	171:3a7713b1edbc	344	#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
AnnaBridge	171:3a7713b1edbc	345	/* @brief Has FIFO (bit SC4[AFDEP]). */
AnnaBridge	171:3a7713b1edbc	346	#define FSL_FEATURE_ADC16_HAS_FIFO (0)
AnnaBridge	171:3a7713b1edbc	347	/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
AnnaBridge	171:3a7713b1edbc	348	#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
AnnaBridge	171:3a7713b1edbc	349	/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
AnnaBridge	171:3a7713b1edbc	350	#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
AnnaBridge	171:3a7713b1edbc	351	/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
AnnaBridge	171:3a7713b1edbc	352	#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
AnnaBridge	171:3a7713b1edbc	353	/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
AnnaBridge	171:3a7713b1edbc	354	#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
AnnaBridge	171:3a7713b1edbc	355	/* @brief Has HW averaging (bit SC3[AVGE]). */
AnnaBridge	171:3a7713b1edbc	356	#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
AnnaBridge	171:3a7713b1edbc	357	/* @brief Has offset correction (register OFS). */
AnnaBridge	171:3a7713b1edbc	358	#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
AnnaBridge	171:3a7713b1edbc	359	/* @brief Maximum ADC resolution. */
AnnaBridge	171:3a7713b1edbc	360	#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
AnnaBridge	171:3a7713b1edbc	361	/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
AnnaBridge	171:3a7713b1edbc	362	#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
AnnaBridge	171:3a7713b1edbc	363
AnnaBridge	171:3a7713b1edbc	364	/* CMP module features */
AnnaBridge	171:3a7713b1edbc	365
AnnaBridge	171:3a7713b1edbc	366	/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
AnnaBridge	171:3a7713b1edbc	367	#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
AnnaBridge	171:3a7713b1edbc	368	/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
AnnaBridge	171:3a7713b1edbc	369	#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0)
AnnaBridge	171:3a7713b1edbc	370	/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
AnnaBridge	171:3a7713b1edbc	371	#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	372	/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
AnnaBridge	171:3a7713b1edbc	373	#define FSL_FEATURE_CMP_HAS_DMA (1)
AnnaBridge	171:3a7713b1edbc	374	/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
AnnaBridge	171:3a7713b1edbc	375	#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
AnnaBridge	171:3a7713b1edbc	376	/* @brief Has DAC Test function in CMP (register DACTEST). */
AnnaBridge	171:3a7713b1edbc	377	#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
AnnaBridge	171:3a7713b1edbc	378
AnnaBridge	171:3a7713b1edbc	379	/* COP module features */
AnnaBridge	171:3a7713b1edbc	380
AnnaBridge	171:3a7713b1edbc	381	/* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */
AnnaBridge	171:3a7713b1edbc	382	#define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1)
AnnaBridge	171:3a7713b1edbc	383	/* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */
AnnaBridge	171:3a7713b1edbc	384	#define FSL_FEATURE_COP_HAS_STOP_ENABLE (1)
AnnaBridge	171:3a7713b1edbc	385	/* @brief Has more clock sources like MCGIRC */
AnnaBridge	171:3a7713b1edbc	386	#define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1)
AnnaBridge	171:3a7713b1edbc	387	/* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */
AnnaBridge	171:3a7713b1edbc	388	#define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1)
AnnaBridge	171:3a7713b1edbc	389
AnnaBridge	171:3a7713b1edbc	390	/* CRC module features */
AnnaBridge	171:3a7713b1edbc	391
AnnaBridge	171:3a7713b1edbc	392	/* @brief Has data register with name CRC */
AnnaBridge	171:3a7713b1edbc	393	#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
AnnaBridge	171:3a7713b1edbc	394
AnnaBridge	171:3a7713b1edbc	395	/* DMA module features */
AnnaBridge	171:3a7713b1edbc	396
AnnaBridge	171:3a7713b1edbc	397	/* @brief Total number of DMA channels on all modules. */
AnnaBridge	171:3a7713b1edbc	398	#define FSL_FEATURE_DMA_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMA_COUNT * 4)
AnnaBridge	171:3a7713b1edbc	399
AnnaBridge	171:3a7713b1edbc	400	/* DMAMUX module features */
AnnaBridge	171:3a7713b1edbc	401
AnnaBridge	171:3a7713b1edbc	402	/* @brief Number of DMA channels (related to number of register CHCFGn). */
AnnaBridge	171:3a7713b1edbc	403	#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
AnnaBridge	171:3a7713b1edbc	404	/* @brief Total number of DMA channels on all modules. */
AnnaBridge	171:3a7713b1edbc	405	#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (FSL_FEATURE_SOC_DMAMUX_COUNT * 4)
AnnaBridge	171:3a7713b1edbc	406	/* @brief Has the periodic trigger capability for the triggered DMA channel 0 (register bit CHCFG0[TRIG]). */
AnnaBridge	171:3a7713b1edbc	407	#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
AnnaBridge	171:3a7713b1edbc	408
AnnaBridge	171:3a7713b1edbc	409	/* FLEXIO module features */
AnnaBridge	171:3a7713b1edbc	410
AnnaBridge	171:3a7713b1edbc	411	/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
AnnaBridge	171:3a7713b1edbc	412	#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
AnnaBridge	171:3a7713b1edbc	413	/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
AnnaBridge	171:3a7713b1edbc	414	#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (0)
AnnaBridge	171:3a7713b1edbc	415	/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
AnnaBridge	171:3a7713b1edbc	416	#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (0)
AnnaBridge	171:3a7713b1edbc	417	/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
AnnaBridge	171:3a7713b1edbc	418	#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (0)
AnnaBridge	171:3a7713b1edbc	419	/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
AnnaBridge	171:3a7713b1edbc	420	#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (0)
AnnaBridge	171:3a7713b1edbc	421	/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
AnnaBridge	171:3a7713b1edbc	422	#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (0)
AnnaBridge	171:3a7713b1edbc	423	/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
AnnaBridge	171:3a7713b1edbc	424	#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (0)
AnnaBridge	171:3a7713b1edbc	425	/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
AnnaBridge	171:3a7713b1edbc	426	#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (0)
AnnaBridge	171:3a7713b1edbc	427	/* @brief Reset value of the FLEXIO_VERID register */
AnnaBridge	171:3a7713b1edbc	428	#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1000000)
AnnaBridge	171:3a7713b1edbc	429	/* @brief Reset value of the FLEXIO_PARAM register */
AnnaBridge	171:3a7713b1edbc	430	#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x10080404)
AnnaBridge	171:3a7713b1edbc	431
AnnaBridge	171:3a7713b1edbc	432	/* FLASH module features */
AnnaBridge	171:3a7713b1edbc	433
AnnaBridge	171:3a7713b1edbc	434	#if defined(CPU_MKL27Z32VDA4) \|\| defined(CPU_MKL27Z32VFM4) \|\| defined(CPU_MKL27Z32VFT4) \|\| defined(CPU_MKL27Z32VLH4) \|\| \
AnnaBridge	171:3a7713b1edbc	435	defined(CPU_MKL27Z32VMP4)
AnnaBridge	171:3a7713b1edbc	436	/* @brief Is of type FTFA. */
AnnaBridge	171:3a7713b1edbc	437	#define FSL_FEATURE_FLASH_IS_FTFA (1)
AnnaBridge	171:3a7713b1edbc	438	/* @brief Is of type FTFE. */
AnnaBridge	171:3a7713b1edbc	439	#define FSL_FEATURE_FLASH_IS_FTFE (0)
AnnaBridge	171:3a7713b1edbc	440	/* @brief Is of type FTFL. */
AnnaBridge	171:3a7713b1edbc	441	#define FSL_FEATURE_FLASH_IS_FTFL (0)
AnnaBridge	171:3a7713b1edbc	442	/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
AnnaBridge	171:3a7713b1edbc	443	#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
AnnaBridge	171:3a7713b1edbc	444	/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
AnnaBridge	171:3a7713b1edbc	445	#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
AnnaBridge	171:3a7713b1edbc	446	/* @brief Has EEPROM region protection (register FEPROT). */
AnnaBridge	171:3a7713b1edbc	447	#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
AnnaBridge	171:3a7713b1edbc	448	/* @brief Has data flash region protection (register FDPROT). */
AnnaBridge	171:3a7713b1edbc	449	#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
AnnaBridge	171:3a7713b1edbc	450	/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
AnnaBridge	171:3a7713b1edbc	451	#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
AnnaBridge	171:3a7713b1edbc	452	/* @brief Has flash cache control in FMC module. */
AnnaBridge	171:3a7713b1edbc	453	#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
AnnaBridge	171:3a7713b1edbc	454	/* @brief Has flash cache control in MCM module. */
AnnaBridge	171:3a7713b1edbc	455	#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
AnnaBridge	171:3a7713b1edbc	456	/* @brief P-Flash start address. */
AnnaBridge	171:3a7713b1edbc	457	#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
AnnaBridge	171:3a7713b1edbc	458	/* @brief P-Flash block count. */
AnnaBridge	171:3a7713b1edbc	459	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
AnnaBridge	171:3a7713b1edbc	460	/* @brief P-Flash block size. */
AnnaBridge	171:3a7713b1edbc	461	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768)
AnnaBridge	171:3a7713b1edbc	462	/* @brief P-Flash sector size. */
AnnaBridge	171:3a7713b1edbc	463	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
AnnaBridge	171:3a7713b1edbc	464	/* @brief P-Flash write unit size. */
AnnaBridge	171:3a7713b1edbc	465	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
AnnaBridge	171:3a7713b1edbc	466	/* @brief P-Flash data path width. */
AnnaBridge	171:3a7713b1edbc	467	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
AnnaBridge	171:3a7713b1edbc	468	/* @brief P-Flash block swap feature. */
AnnaBridge	171:3a7713b1edbc	469	#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
AnnaBridge	171:3a7713b1edbc	470	/* @brief P-Flash protection region count. */
AnnaBridge	171:3a7713b1edbc	471	#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
AnnaBridge	171:3a7713b1edbc	472	/* @brief Has FlexNVM memory. */
AnnaBridge	171:3a7713b1edbc	473	#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
AnnaBridge	171:3a7713b1edbc	474	/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
AnnaBridge	171:3a7713b1edbc	475	#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
AnnaBridge	171:3a7713b1edbc	476	/* @brief FlexNVM block count. */
AnnaBridge	171:3a7713b1edbc	477	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
AnnaBridge	171:3a7713b1edbc	478	/* @brief FlexNVM block size. */
AnnaBridge	171:3a7713b1edbc	479	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
AnnaBridge	171:3a7713b1edbc	480	/* @brief FlexNVM sector size. */
AnnaBridge	171:3a7713b1edbc	481	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
AnnaBridge	171:3a7713b1edbc	482	/* @brief FlexNVM write unit size. */
AnnaBridge	171:3a7713b1edbc	483	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
AnnaBridge	171:3a7713b1edbc	484	/* @brief FlexNVM data path width. */
AnnaBridge	171:3a7713b1edbc	485	#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
AnnaBridge	171:3a7713b1edbc	486	/* @brief Has FlexRAM memory. */
AnnaBridge	171:3a7713b1edbc	487	#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
AnnaBridge	171:3a7713b1edbc	488	/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
AnnaBridge	171:3a7713b1edbc	489	#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
AnnaBridge	171:3a7713b1edbc	490	/* @brief FlexRAM size. */
AnnaBridge	171:3a7713b1edbc	491	#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
AnnaBridge	171:3a7713b1edbc	492	/* @brief Has 0x00 Read 1s Block command. */
AnnaBridge	171:3a7713b1edbc	493	#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
AnnaBridge	171:3a7713b1edbc	494	/* @brief Has 0x01 Read 1s Section command. */
AnnaBridge	171:3a7713b1edbc	495	#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
AnnaBridge	171:3a7713b1edbc	496	/* @brief Has 0x02 Program Check command. */
AnnaBridge	171:3a7713b1edbc	497	#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
AnnaBridge	171:3a7713b1edbc	498	/* @brief Has 0x03 Read Resource command. */
AnnaBridge	171:3a7713b1edbc	499	#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
AnnaBridge	171:3a7713b1edbc	500	/* @brief Has 0x06 Program Longword command. */
AnnaBridge	171:3a7713b1edbc	501	#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
AnnaBridge	171:3a7713b1edbc	502	/* @brief Has 0x07 Program Phrase command. */
AnnaBridge	171:3a7713b1edbc	503	#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
AnnaBridge	171:3a7713b1edbc	504	/* @brief Has 0x08 Erase Flash Block command. */
AnnaBridge	171:3a7713b1edbc	505	#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
AnnaBridge	171:3a7713b1edbc	506	/* @brief Has 0x09 Erase Flash Sector command. */
AnnaBridge	171:3a7713b1edbc	507	#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
AnnaBridge	171:3a7713b1edbc	508	/* @brief Has 0x0B Program Section command. */
AnnaBridge	171:3a7713b1edbc	509	#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
AnnaBridge	171:3a7713b1edbc	510	/* @brief Has 0x40 Read 1s All Blocks command. */
AnnaBridge	171:3a7713b1edbc	511	#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0)
AnnaBridge	171:3a7713b1edbc	512	/* @brief Has 0x41 Read Once command. */
AnnaBridge	171:3a7713b1edbc	513	#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
AnnaBridge	171:3a7713b1edbc	514	/* @brief Has 0x43 Program Once command. */
AnnaBridge	171:3a7713b1edbc	515	#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
AnnaBridge	171:3a7713b1edbc	516	/* @brief Has 0x44 Erase All Blocks command. */
AnnaBridge	171:3a7713b1edbc	517	#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0)
AnnaBridge	171:3a7713b1edbc	518	/* @brief Has 0x45 Verify Backdoor Access Key command. */
AnnaBridge	171:3a7713b1edbc	519	#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
AnnaBridge	171:3a7713b1edbc	520	/* @brief Has 0x46 Swap Control command. */
AnnaBridge	171:3a7713b1edbc	521	#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
AnnaBridge	171:3a7713b1edbc	522	/* @brief Has 0x49 Erase All Blocks Unsecure command. */
AnnaBridge	171:3a7713b1edbc	523	#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
AnnaBridge	171:3a7713b1edbc	524	/* @brief Has 0x80 Program Partition command. */
AnnaBridge	171:3a7713b1edbc	525	#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
AnnaBridge	171:3a7713b1edbc	526	/* @brief Has 0x81 Set FlexRAM Function command. */
AnnaBridge	171:3a7713b1edbc	527	#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
AnnaBridge	171:3a7713b1edbc	528	/* @brief P-Flash Erase/Read 1st all block command address alignment. */
AnnaBridge	171:3a7713b1edbc	529	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge	171:3a7713b1edbc	530	/* @brief P-Flash Erase sector command address alignment. */
AnnaBridge	171:3a7713b1edbc	531	#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge	171:3a7713b1edbc	532	/* @brief P-Flash Rrogram/Verify section command address alignment. */
AnnaBridge	171:3a7713b1edbc	533	#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge	171:3a7713b1edbc	534	/* @brief P-Flash Read resource command address alignment. */
AnnaBridge	171:3a7713b1edbc	535	#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge	171:3a7713b1edbc	536	/* @brief P-Flash Program check command address alignment. */
AnnaBridge	171:3a7713b1edbc	537	#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge	171:3a7713b1edbc	538	/* @brief P-Flash Program check command address alignment. */
AnnaBridge	171:3a7713b1edbc	539	#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	171:3a7713b1edbc	540	/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
AnnaBridge	171:3a7713b1edbc	541	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	171:3a7713b1edbc	542	/* @brief FlexNVM Erase sector command address alignment. */
AnnaBridge	171:3a7713b1edbc	543	#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	171:3a7713b1edbc	544	/* @brief FlexNVM Rrogram/Verify section command address alignment. */
AnnaBridge	171:3a7713b1edbc	545	#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	171:3a7713b1edbc	546	/* @brief FlexNVM Read resource command address alignment. */
AnnaBridge	171:3a7713b1edbc	547	#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	171:3a7713b1edbc	548	/* @brief FlexNVM Program check command address alignment. */
AnnaBridge	171:3a7713b1edbc	549	#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	171:3a7713b1edbc	550	/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	551	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	552	/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	553	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	554	/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	555	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	556	/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	557	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	558	/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	559	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	560	/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	561	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	562	/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	563	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	564	/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	565	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	566	/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	567	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	568	/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	569	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	570	/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	571	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	572	/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	573	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	574	/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	575	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	576	/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	577	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	578	/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	579	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	580	/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	581	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	582	/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	583	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	584	/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	585	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	586	/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	587	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	588	/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	589	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	590	/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	591	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	592	/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	593	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	594	/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	595	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	596	/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	597	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	598	/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	599	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	600	/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	601	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	602	/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	603	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	604	/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	605	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	606	/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	607	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	608	/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	609	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	610	/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	611	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	612	/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	613	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	614	#elif defined(CPU_MKL27Z64VDA4) \|\| defined(CPU_MKL27Z64VFM4) \|\| defined(CPU_MKL27Z64VFT4) \|\| defined(CPU_MKL27Z64VLH4) \|\| \
AnnaBridge	171:3a7713b1edbc	615	defined(CPU_MKL27Z64VMP4)
AnnaBridge	171:3a7713b1edbc	616	/* @brief Is of type FTFA. */
AnnaBridge	171:3a7713b1edbc	617	#define FSL_FEATURE_FLASH_IS_FTFA (1)
AnnaBridge	171:3a7713b1edbc	618	/* @brief Is of type FTFE. */
AnnaBridge	171:3a7713b1edbc	619	#define FSL_FEATURE_FLASH_IS_FTFE (0)
AnnaBridge	171:3a7713b1edbc	620	/* @brief Is of type FTFL. */
AnnaBridge	171:3a7713b1edbc	621	#define FSL_FEATURE_FLASH_IS_FTFL (0)
AnnaBridge	171:3a7713b1edbc	622	/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
AnnaBridge	171:3a7713b1edbc	623	#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
AnnaBridge	171:3a7713b1edbc	624	/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
AnnaBridge	171:3a7713b1edbc	625	#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
AnnaBridge	171:3a7713b1edbc	626	/* @brief Has EEPROM region protection (register FEPROT). */
AnnaBridge	171:3a7713b1edbc	627	#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
AnnaBridge	171:3a7713b1edbc	628	/* @brief Has data flash region protection (register FDPROT). */
AnnaBridge	171:3a7713b1edbc	629	#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
AnnaBridge	171:3a7713b1edbc	630	/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
AnnaBridge	171:3a7713b1edbc	631	#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
AnnaBridge	171:3a7713b1edbc	632	/* @brief Has flash cache control in FMC module. */
AnnaBridge	171:3a7713b1edbc	633	#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0)
AnnaBridge	171:3a7713b1edbc	634	/* @brief Has flash cache control in MCM module. */
AnnaBridge	171:3a7713b1edbc	635	#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1)
AnnaBridge	171:3a7713b1edbc	636	/* @brief P-Flash start address. */
AnnaBridge	171:3a7713b1edbc	637	#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
AnnaBridge	171:3a7713b1edbc	638	/* @brief P-Flash block count. */
AnnaBridge	171:3a7713b1edbc	639	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
AnnaBridge	171:3a7713b1edbc	640	/* @brief P-Flash block size. */
AnnaBridge	171:3a7713b1edbc	641	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536)
AnnaBridge	171:3a7713b1edbc	642	/* @brief P-Flash sector size. */
AnnaBridge	171:3a7713b1edbc	643	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024)
AnnaBridge	171:3a7713b1edbc	644	/* @brief P-Flash write unit size. */
AnnaBridge	171:3a7713b1edbc	645	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
AnnaBridge	171:3a7713b1edbc	646	/* @brief P-Flash data path width. */
AnnaBridge	171:3a7713b1edbc	647	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4)
AnnaBridge	171:3a7713b1edbc	648	/* @brief P-Flash block swap feature. */
AnnaBridge	171:3a7713b1edbc	649	#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
AnnaBridge	171:3a7713b1edbc	650	/* @brief P-Flash protection region count. */
AnnaBridge	171:3a7713b1edbc	651	#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
AnnaBridge	171:3a7713b1edbc	652	/* @brief Has FlexNVM memory. */
AnnaBridge	171:3a7713b1edbc	653	#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
AnnaBridge	171:3a7713b1edbc	654	/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
AnnaBridge	171:3a7713b1edbc	655	#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
AnnaBridge	171:3a7713b1edbc	656	/* @brief FlexNVM block count. */
AnnaBridge	171:3a7713b1edbc	657	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
AnnaBridge	171:3a7713b1edbc	658	/* @brief FlexNVM block size. */
AnnaBridge	171:3a7713b1edbc	659	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
AnnaBridge	171:3a7713b1edbc	660	/* @brief FlexNVM sector size. */
AnnaBridge	171:3a7713b1edbc	661	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
AnnaBridge	171:3a7713b1edbc	662	/* @brief FlexNVM write unit size. */
AnnaBridge	171:3a7713b1edbc	663	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
AnnaBridge	171:3a7713b1edbc	664	/* @brief FlexNVM data path width. */
AnnaBridge	171:3a7713b1edbc	665	#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
AnnaBridge	171:3a7713b1edbc	666	/* @brief Has FlexRAM memory. */
AnnaBridge	171:3a7713b1edbc	667	#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
AnnaBridge	171:3a7713b1edbc	668	/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
AnnaBridge	171:3a7713b1edbc	669	#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
AnnaBridge	171:3a7713b1edbc	670	/* @brief FlexRAM size. */
AnnaBridge	171:3a7713b1edbc	671	#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
AnnaBridge	171:3a7713b1edbc	672	/* @brief Has 0x00 Read 1s Block command. */
AnnaBridge	171:3a7713b1edbc	673	#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
AnnaBridge	171:3a7713b1edbc	674	/* @brief Has 0x01 Read 1s Section command. */
AnnaBridge	171:3a7713b1edbc	675	#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
AnnaBridge	171:3a7713b1edbc	676	/* @brief Has 0x02 Program Check command. */
AnnaBridge	171:3a7713b1edbc	677	#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
AnnaBridge	171:3a7713b1edbc	678	/* @brief Has 0x03 Read Resource command. */
AnnaBridge	171:3a7713b1edbc	679	#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
AnnaBridge	171:3a7713b1edbc	680	/* @brief Has 0x06 Program Longword command. */
AnnaBridge	171:3a7713b1edbc	681	#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
AnnaBridge	171:3a7713b1edbc	682	/* @brief Has 0x07 Program Phrase command. */
AnnaBridge	171:3a7713b1edbc	683	#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
AnnaBridge	171:3a7713b1edbc	684	/* @brief Has 0x08 Erase Flash Block command. */
AnnaBridge	171:3a7713b1edbc	685	#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
AnnaBridge	171:3a7713b1edbc	686	/* @brief Has 0x09 Erase Flash Sector command. */
AnnaBridge	171:3a7713b1edbc	687	#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
AnnaBridge	171:3a7713b1edbc	688	/* @brief Has 0x0B Program Section command. */
AnnaBridge	171:3a7713b1edbc	689	#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
AnnaBridge	171:3a7713b1edbc	690	/* @brief Has 0x40 Read 1s All Blocks command. */
AnnaBridge	171:3a7713b1edbc	691	#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (0)
AnnaBridge	171:3a7713b1edbc	692	/* @brief Has 0x41 Read Once command. */
AnnaBridge	171:3a7713b1edbc	693	#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
AnnaBridge	171:3a7713b1edbc	694	/* @brief Has 0x43 Program Once command. */
AnnaBridge	171:3a7713b1edbc	695	#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
AnnaBridge	171:3a7713b1edbc	696	/* @brief Has 0x44 Erase All Blocks command. */
AnnaBridge	171:3a7713b1edbc	697	#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (0)
AnnaBridge	171:3a7713b1edbc	698	/* @brief Has 0x45 Verify Backdoor Access Key command. */
AnnaBridge	171:3a7713b1edbc	699	#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
AnnaBridge	171:3a7713b1edbc	700	/* @brief Has 0x46 Swap Control command. */
AnnaBridge	171:3a7713b1edbc	701	#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
AnnaBridge	171:3a7713b1edbc	702	/* @brief Has 0x49 Erase All Blocks Unsecure command. */
AnnaBridge	171:3a7713b1edbc	703	#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1)
AnnaBridge	171:3a7713b1edbc	704	/* @brief Has 0x80 Program Partition command. */
AnnaBridge	171:3a7713b1edbc	705	#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
AnnaBridge	171:3a7713b1edbc	706	/* @brief Has 0x81 Set FlexRAM Function command. */
AnnaBridge	171:3a7713b1edbc	707	#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
AnnaBridge	171:3a7713b1edbc	708	/* @brief P-Flash Erase/Read 1st all block command address alignment. */
AnnaBridge	171:3a7713b1edbc	709	#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge	171:3a7713b1edbc	710	/* @brief P-Flash Erase sector command address alignment. */
AnnaBridge	171:3a7713b1edbc	711	#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge	171:3a7713b1edbc	712	/* @brief P-Flash Rrogram/Verify section command address alignment. */
AnnaBridge	171:3a7713b1edbc	713	#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge	171:3a7713b1edbc	714	/* @brief P-Flash Read resource command address alignment. */
AnnaBridge	171:3a7713b1edbc	715	#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge	171:3a7713b1edbc	716	/* @brief P-Flash Program check command address alignment. */
AnnaBridge	171:3a7713b1edbc	717	#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
AnnaBridge	171:3a7713b1edbc	718	/* @brief P-Flash Program check command address alignment. */
AnnaBridge	171:3a7713b1edbc	719	#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	171:3a7713b1edbc	720	/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
AnnaBridge	171:3a7713b1edbc	721	#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	171:3a7713b1edbc	722	/* @brief FlexNVM Erase sector command address alignment. */
AnnaBridge	171:3a7713b1edbc	723	#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	171:3a7713b1edbc	724	/* @brief FlexNVM Rrogram/Verify section command address alignment. */
AnnaBridge	171:3a7713b1edbc	725	#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	171:3a7713b1edbc	726	/* @brief FlexNVM Read resource command address alignment. */
AnnaBridge	171:3a7713b1edbc	727	#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	171:3a7713b1edbc	728	/* @brief FlexNVM Program check command address alignment. */
AnnaBridge	171:3a7713b1edbc	729	#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
AnnaBridge	171:3a7713b1edbc	730	/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	731	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	732	/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	733	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	734	/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	735	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	736	/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	737	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	738	/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	739	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	740	/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	741	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	742	/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	743	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	744	/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	745	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	746	/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	747	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	748	/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	749	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	750	/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	751	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	752	/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	753	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	754	/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	755	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	756	/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	757	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	758	/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	759	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	760	/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	761	#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	762	/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	763	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	764	/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	765	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	766	/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	767	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	768	/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	769	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	770	/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	771	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	772	/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	773	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	774	/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	775	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	776	/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	777	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	778	/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	779	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	780	/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	781	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	782	/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	783	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	784	/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	785	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	786	/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	787	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	788	/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	789	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	790	/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	791	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	792	/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
AnnaBridge	171:3a7713b1edbc	793	#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
AnnaBridge	171:3a7713b1edbc	794	#endif /* defined(CPU_MKL27Z32VDA4) \|\| defined(CPU_MKL27Z32VFM4) \|\| defined(CPU_MKL27Z32VFT4) \|\| defined(CPU_MKL27Z32VLH4) \|\| \
AnnaBridge	171:3a7713b1edbc	795	defined(CPU_MKL27Z32VMP4) */
AnnaBridge	171:3a7713b1edbc	796
AnnaBridge	171:3a7713b1edbc	797	/* GPIO module features */
AnnaBridge	171:3a7713b1edbc	798
AnnaBridge	171:3a7713b1edbc	799	/* @brief Has fast (single cycle) access capability via a dedicated memory region. */
AnnaBridge	171:3a7713b1edbc	800	#define FSL_FEATURE_GPIO_HAS_FAST_GPIO (0)
AnnaBridge	171:3a7713b1edbc	801	/* @brief Has port input disable register (PIDR). */
AnnaBridge	171:3a7713b1edbc	802	#define FSL_FEATURE_GPIO_HAS_INPUT_DISABLE (0)
AnnaBridge	171:3a7713b1edbc	803	/* @brief Has dedicated interrupt vector. */
AnnaBridge	171:3a7713b1edbc	804	#define FSL_FEATURE_GPIO_HAS_PORT_INTERRUPT_VECTOR (1)
AnnaBridge	171:3a7713b1edbc	805
AnnaBridge	171:3a7713b1edbc	806	/* I2C module features */
AnnaBridge	171:3a7713b1edbc	807
AnnaBridge	171:3a7713b1edbc	808	/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
AnnaBridge	171:3a7713b1edbc	809	#define FSL_FEATURE_I2C_HAS_SMBUS (1)
AnnaBridge	171:3a7713b1edbc	810	/* @brief Maximum supported baud rate in kilobit per second. */
AnnaBridge	171:3a7713b1edbc	811	#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
AnnaBridge	171:3a7713b1edbc	812	/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
AnnaBridge	171:3a7713b1edbc	813	#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
AnnaBridge	171:3a7713b1edbc	814	/* @brief Has DMA support (register bit C1[DMAEN]). */
AnnaBridge	171:3a7713b1edbc	815	#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
AnnaBridge	171:3a7713b1edbc	816	/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
AnnaBridge	171:3a7713b1edbc	817	#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
AnnaBridge	171:3a7713b1edbc	818	/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
AnnaBridge	171:3a7713b1edbc	819	#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
AnnaBridge	171:3a7713b1edbc	820	/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
AnnaBridge	171:3a7713b1edbc	821	#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
AnnaBridge	171:3a7713b1edbc	822	/* @brief Maximum width of the glitch filter in number of bus clocks. */
AnnaBridge	171:3a7713b1edbc	823	#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
AnnaBridge	171:3a7713b1edbc	824	/* @brief Has control of the drive capability of the I2C pins. */
AnnaBridge	171:3a7713b1edbc	825	#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
AnnaBridge	171:3a7713b1edbc	826	/* @brief Has double buffering support (register S2). */
AnnaBridge	171:3a7713b1edbc	827	#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1)
AnnaBridge	171:3a7713b1edbc	828
AnnaBridge	171:3a7713b1edbc	829	/* LLWU module features */
AnnaBridge	171:3a7713b1edbc	830
AnnaBridge	171:3a7713b1edbc	831	/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	832	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
AnnaBridge	171:3a7713b1edbc	833	/* @brief Has pins 8-15 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	834	#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
AnnaBridge	171:3a7713b1edbc	835	/* @brief Maximum number of internal modules connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	836	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
AnnaBridge	171:3a7713b1edbc	837	/* @brief Number of digital filters. */
AnnaBridge	171:3a7713b1edbc	838	#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
AnnaBridge	171:3a7713b1edbc	839	/* @brief Has MF5 register. */
AnnaBridge	171:3a7713b1edbc	840	#define FSL_FEATURE_LLWU_HAS_MF (0)
AnnaBridge	171:3a7713b1edbc	841	/* @brief Has PF register. */
AnnaBridge	171:3a7713b1edbc	842	#define FSL_FEATURE_LLWU_HAS_PF (0)
AnnaBridge	171:3a7713b1edbc	843	/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
AnnaBridge	171:3a7713b1edbc	844	#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
AnnaBridge	171:3a7713b1edbc	845	/* @brief Has external pin 0 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	846	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0)
AnnaBridge	171:3a7713b1edbc	847	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	848	#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	849	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	850	#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	851	/* @brief Has external pin 1 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	852	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0)
AnnaBridge	171:3a7713b1edbc	853	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	854	#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	855	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	856	#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	857	/* @brief Has external pin 2 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	858	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0)
AnnaBridge	171:3a7713b1edbc	859	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	860	#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	861	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	862	#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	863	/* @brief Has external pin 3 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	864	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (0)
AnnaBridge	171:3a7713b1edbc	865	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	866	#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	867	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	868	#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	869	/* @brief Has external pin 4 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	870	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0)
AnnaBridge	171:3a7713b1edbc	871	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	872	#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	873	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	874	#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	875	/* @brief Has external pin 5 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	876	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
AnnaBridge	171:3a7713b1edbc	877	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	878	#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
AnnaBridge	171:3a7713b1edbc	879	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	880	#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	881	/* @brief Has external pin 6 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	882	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
AnnaBridge	171:3a7713b1edbc	883	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	884	#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
AnnaBridge	171:3a7713b1edbc	885	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	886	#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
AnnaBridge	171:3a7713b1edbc	887	/* @brief Has external pin 7 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	888	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
AnnaBridge	171:3a7713b1edbc	889	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	890	#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
AnnaBridge	171:3a7713b1edbc	891	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	892	#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
AnnaBridge	171:3a7713b1edbc	893	/* @brief Has external pin 8 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	894	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
AnnaBridge	171:3a7713b1edbc	895	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	896	#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
AnnaBridge	171:3a7713b1edbc	897	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	898	#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
AnnaBridge	171:3a7713b1edbc	899	/* @brief Has external pin 9 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	900	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
AnnaBridge	171:3a7713b1edbc	901	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	902	#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
AnnaBridge	171:3a7713b1edbc	903	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	904	#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
AnnaBridge	171:3a7713b1edbc	905	/* @brief Has external pin 10 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	906	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
AnnaBridge	171:3a7713b1edbc	907	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	908	#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
AnnaBridge	171:3a7713b1edbc	909	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	910	#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
AnnaBridge	171:3a7713b1edbc	911	/* @brief Has external pin 11 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	912	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0)
AnnaBridge	171:3a7713b1edbc	913	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	914	#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	915	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	916	#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	917	/* @brief Has external pin 12 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	918	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0)
AnnaBridge	171:3a7713b1edbc	919	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	920	#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	921	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	922	#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	923	/* @brief Has external pin 13 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	924	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0)
AnnaBridge	171:3a7713b1edbc	925	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	926	#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	927	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	928	#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	929	/* @brief Has external pin 14 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	930	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
AnnaBridge	171:3a7713b1edbc	931	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	932	#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
AnnaBridge	171:3a7713b1edbc	933	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	934	#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
AnnaBridge	171:3a7713b1edbc	935	/* @brief Has external pin 15 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	936	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
AnnaBridge	171:3a7713b1edbc	937	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	938	#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
AnnaBridge	171:3a7713b1edbc	939	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	940	#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
AnnaBridge	171:3a7713b1edbc	941	/* @brief Has external pin 16 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	942	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
AnnaBridge	171:3a7713b1edbc	943	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	944	#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	945	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	946	#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	947	/* @brief Has external pin 17 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	948	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
AnnaBridge	171:3a7713b1edbc	949	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	950	#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	951	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	952	#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	953	/* @brief Has external pin 18 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	954	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
AnnaBridge	171:3a7713b1edbc	955	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	956	#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	957	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	958	#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	959	/* @brief Has external pin 19 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	960	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
AnnaBridge	171:3a7713b1edbc	961	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	962	#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	963	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	964	#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	965	/* @brief Has external pin 20 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	966	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
AnnaBridge	171:3a7713b1edbc	967	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	968	#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	969	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	970	#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	971	/* @brief Has external pin 21 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	972	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
AnnaBridge	171:3a7713b1edbc	973	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	974	#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	975	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	976	#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	977	/* @brief Has external pin 22 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	978	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
AnnaBridge	171:3a7713b1edbc	979	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	980	#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	981	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	982	#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	983	/* @brief Has external pin 23 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	984	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
AnnaBridge	171:3a7713b1edbc	985	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	986	#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	987	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	988	#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	989	/* @brief Has external pin 24 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	990	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
AnnaBridge	171:3a7713b1edbc	991	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	992	#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	993	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	994	#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	995	/* @brief Has external pin 25 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	996	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
AnnaBridge	171:3a7713b1edbc	997	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	998	#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	999	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	1000	#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	1001	/* @brief Has external pin 26 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1002	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
AnnaBridge	171:3a7713b1edbc	1003	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	1004	#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	1005	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	1006	#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	1007	/* @brief Has external pin 27 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1008	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
AnnaBridge	171:3a7713b1edbc	1009	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	1010	#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	1011	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	1012	#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	1013	/* @brief Has external pin 28 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1014	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
AnnaBridge	171:3a7713b1edbc	1015	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	1016	#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	1017	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	1018	#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	1019	/* @brief Has external pin 29 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1020	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
AnnaBridge	171:3a7713b1edbc	1021	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	1022	#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	1023	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	1024	#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	1025	/* @brief Has external pin 30 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1026	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
AnnaBridge	171:3a7713b1edbc	1027	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	1028	#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	1029	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	1030	#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	1031	/* @brief Has external pin 31 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1032	#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
AnnaBridge	171:3a7713b1edbc	1033	/* @brief Index of port of external pin. */
AnnaBridge	171:3a7713b1edbc	1034	#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
AnnaBridge	171:3a7713b1edbc	1035	/* @brief Number of external pin port on specified port. */
AnnaBridge	171:3a7713b1edbc	1036	#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
AnnaBridge	171:3a7713b1edbc	1037	/* @brief Has internal module 0 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1038	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
AnnaBridge	171:3a7713b1edbc	1039	/* @brief Has internal module 1 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1040	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
AnnaBridge	171:3a7713b1edbc	1041	/* @brief Has internal module 2 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1042	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (0)
AnnaBridge	171:3a7713b1edbc	1043	/* @brief Has internal module 3 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1044	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
AnnaBridge	171:3a7713b1edbc	1045	/* @brief Has internal module 4 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1046	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
AnnaBridge	171:3a7713b1edbc	1047	/* @brief Has internal module 5 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1048	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
AnnaBridge	171:3a7713b1edbc	1049	/* @brief Has internal module 6 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1050	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
AnnaBridge	171:3a7713b1edbc	1051	/* @brief Has internal module 7 connected to LLWU device. */
AnnaBridge	171:3a7713b1edbc	1052	#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
AnnaBridge	171:3a7713b1edbc	1053	/* @brief Has Version ID Register (LLWU_VERID). */
AnnaBridge	171:3a7713b1edbc	1054	#define FSL_FEATURE_LLWU_HAS_VERID (0)
AnnaBridge	171:3a7713b1edbc	1055	/* @brief Has Parameter Register (LLWU_PARAM). */
AnnaBridge	171:3a7713b1edbc	1056	#define FSL_FEATURE_LLWU_HAS_PARAM (0)
AnnaBridge	171:3a7713b1edbc	1057	/* @brief Width of registers of the LLWU. */
AnnaBridge	171:3a7713b1edbc	1058	#define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
AnnaBridge	171:3a7713b1edbc	1059	/* @brief Has DMA Enable register (LLWU_DE). */
AnnaBridge	171:3a7713b1edbc	1060	#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
AnnaBridge	171:3a7713b1edbc	1061
AnnaBridge	171:3a7713b1edbc	1062	/* LPTMR module features */
AnnaBridge	171:3a7713b1edbc	1063
AnnaBridge	171:3a7713b1edbc	1064	/* @brief Has shared interrupt handler with another LPTMR module. */
AnnaBridge	171:3a7713b1edbc	1065	#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
AnnaBridge	171:3a7713b1edbc	1066
AnnaBridge	171:3a7713b1edbc	1067	/* LPUART module features */
AnnaBridge	171:3a7713b1edbc	1068
AnnaBridge	171:3a7713b1edbc	1069	/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
AnnaBridge	171:3a7713b1edbc	1070	#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
AnnaBridge	171:3a7713b1edbc	1071	/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
AnnaBridge	171:3a7713b1edbc	1072	#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
AnnaBridge	171:3a7713b1edbc	1073	/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
AnnaBridge	171:3a7713b1edbc	1074	#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
AnnaBridge	171:3a7713b1edbc	1075	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge	171:3a7713b1edbc	1076	#define FSL_FEATURE_LPUART_HAS_FIFO (0)
AnnaBridge	171:3a7713b1edbc	1077	/* @brief Has 32-bit register MODIR */
AnnaBridge	171:3a7713b1edbc	1078	#define FSL_FEATURE_LPUART_HAS_MODIR (0)
AnnaBridge	171:3a7713b1edbc	1079	/* @brief Hardware flow control (RTS, CTS) is supported. */
AnnaBridge	171:3a7713b1edbc	1080	#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1081	/* @brief Infrared (modulation) is supported. */
AnnaBridge	171:3a7713b1edbc	1082	#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1083	/* @brief 2 bits long stop bit is available. */
AnnaBridge	171:3a7713b1edbc	1084	#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
AnnaBridge	171:3a7713b1edbc	1085	/* @brief Maximal data width without parity bit. */
AnnaBridge	171:3a7713b1edbc	1086	#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
AnnaBridge	171:3a7713b1edbc	1087	/* @brief Baud rate fine adjustment is available. */
AnnaBridge	171:3a7713b1edbc	1088	#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1089	/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
AnnaBridge	171:3a7713b1edbc	1090	#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
AnnaBridge	171:3a7713b1edbc	1091	/* @brief Baud rate oversampling is available. */
AnnaBridge	171:3a7713b1edbc	1092	#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
AnnaBridge	171:3a7713b1edbc	1093	/* @brief Baud rate oversampling is available. */
AnnaBridge	171:3a7713b1edbc	1094	#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
AnnaBridge	171:3a7713b1edbc	1095	/* @brief Peripheral type. */
AnnaBridge	171:3a7713b1edbc	1096	#define FSL_FEATURE_LPUART_IS_SCI (1)
AnnaBridge	171:3a7713b1edbc	1097	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge	171:3a7713b1edbc	1098	#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0)
AnnaBridge	171:3a7713b1edbc	1099	/* @brief Maximal data width without parity bit. */
AnnaBridge	171:3a7713b1edbc	1100	#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
AnnaBridge	171:3a7713b1edbc	1101	/* @brief Maximal data width with parity bit. */
AnnaBridge	171:3a7713b1edbc	1102	#define FSL_FEATURE_LPUART_MAX_DATA_WIDTH_WITH_PARITY (9)
AnnaBridge	171:3a7713b1edbc	1103	/* @brief Supports two match addresses to filter incoming frames. */
AnnaBridge	171:3a7713b1edbc	1104	#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
AnnaBridge	171:3a7713b1edbc	1105	/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
AnnaBridge	171:3a7713b1edbc	1106	#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
AnnaBridge	171:3a7713b1edbc	1107	/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
AnnaBridge	171:3a7713b1edbc	1108	#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
AnnaBridge	171:3a7713b1edbc	1109	/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
AnnaBridge	171:3a7713b1edbc	1110	#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
AnnaBridge	171:3a7713b1edbc	1111	/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
AnnaBridge	171:3a7713b1edbc	1112	#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1113	/* @brief Has improved smart card (ISO7816 protocol) support. */
AnnaBridge	171:3a7713b1edbc	1114	#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1115	/* @brief Has local operation network (CEA709.1-B protocol) support. */
AnnaBridge	171:3a7713b1edbc	1116	#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1117	/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
AnnaBridge	171:3a7713b1edbc	1118	#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
AnnaBridge	171:3a7713b1edbc	1119	/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
AnnaBridge	171:3a7713b1edbc	1120	#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (0)
AnnaBridge	171:3a7713b1edbc	1121	/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
AnnaBridge	171:3a7713b1edbc	1122	#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
AnnaBridge	171:3a7713b1edbc	1123	/* @brief Has separate DMA RX and TX requests. */
AnnaBridge	171:3a7713b1edbc	1124	#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
AnnaBridge	171:3a7713b1edbc	1125	/* @brief Has LPAURT_PARAM. */
AnnaBridge	171:3a7713b1edbc	1126	#define FSL_FEATURE_LPUART_HAS_PARAM (0)
AnnaBridge	171:3a7713b1edbc	1127	/* @brief Has LPUART_VERID. */
AnnaBridge	171:3a7713b1edbc	1128	#define FSL_FEATURE_LPUART_HAS_VERID (0)
AnnaBridge	171:3a7713b1edbc	1129	/* @brief Has LPUART_GLOBAL. */
AnnaBridge	171:3a7713b1edbc	1130	#define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
AnnaBridge	171:3a7713b1edbc	1131	/* @brief Has LPUART_PINCFG. */
AnnaBridge	171:3a7713b1edbc	1132	#define FSL_FEATURE_LPUART_HAS_PINCFG (0)
AnnaBridge	171:3a7713b1edbc	1133
AnnaBridge	171:3a7713b1edbc	1134	/* MCGLITE module features */
AnnaBridge	171:3a7713b1edbc	1135
AnnaBridge	171:3a7713b1edbc	1136	/* @brief Defines that clock generator is MCG Lite. */
AnnaBridge	171:3a7713b1edbc	1137	#define FSL_FEATURE_MCGLITE_MCGLITE (1)
AnnaBridge	171:3a7713b1edbc	1138	/* @brief Has Crystal Oscillator Operation Mode Selection. */
AnnaBridge	171:3a7713b1edbc	1139	#define FSL_FEATURE_MCGLITE_HAS_HGO0 (1)
AnnaBridge	171:3a7713b1edbc	1140	/* @brief Has HCTRIM register available. */
AnnaBridge	171:3a7713b1edbc	1141	#define FSL_FEATURE_MCGLITE_HAS_HCTRIM (0)
AnnaBridge	171:3a7713b1edbc	1142	/* @brief Has HTTRIM register available. */
AnnaBridge	171:3a7713b1edbc	1143	#define FSL_FEATURE_MCGLITE_HAS_HTTRIM (0)
AnnaBridge	171:3a7713b1edbc	1144	/* @brief Has HFTRIM register available. */
AnnaBridge	171:3a7713b1edbc	1145	#define FSL_FEATURE_MCGLITE_HAS_HFTRIM (0)
AnnaBridge	171:3a7713b1edbc	1146	/* @brief Has LTRIMRNG register available. */
AnnaBridge	171:3a7713b1edbc	1147	#define FSL_FEATURE_MCGLITE_HAS_LTRIMRNG (0)
AnnaBridge	171:3a7713b1edbc	1148	/* @brief Has LFTRIM register available. */
AnnaBridge	171:3a7713b1edbc	1149	#define FSL_FEATURE_MCGLITE_HAS_LFTRIM (0)
AnnaBridge	171:3a7713b1edbc	1150	/* @brief Has LSTRIM register available. */
AnnaBridge	171:3a7713b1edbc	1151	#define FSL_FEATURE_MCGLITE_HAS_LSTRIM (0)
AnnaBridge	171:3a7713b1edbc	1152	/* @brief Has External Clock Source Frequency Range Selection. */
AnnaBridge	171:3a7713b1edbc	1153	#define FSL_FEATURE_MCGLITE_HAS_RANGE0 (1)
AnnaBridge	171:3a7713b1edbc	1154
AnnaBridge	171:3a7713b1edbc	1155	/* interrupt module features */
AnnaBridge	171:3a7713b1edbc	1156
AnnaBridge	171:3a7713b1edbc	1157	/* @brief Lowest interrupt request number. */
AnnaBridge	171:3a7713b1edbc	1158	#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
AnnaBridge	171:3a7713b1edbc	1159	/* @brief Highest interrupt request number. */
AnnaBridge	171:3a7713b1edbc	1160	#define FSL_FEATURE_INTERRUPT_IRQ_MAX (31)
AnnaBridge	171:3a7713b1edbc	1161
AnnaBridge	171:3a7713b1edbc	1162	/* OSC module features */
AnnaBridge	171:3a7713b1edbc	1163
AnnaBridge	171:3a7713b1edbc	1164	/* @brief Has OSC1 external oscillator. */
AnnaBridge	171:3a7713b1edbc	1165	#define FSL_FEATURE_OSC_HAS_OSC1 (0)
AnnaBridge	171:3a7713b1edbc	1166	/* @brief Has OSC0 external oscillator. */
AnnaBridge	171:3a7713b1edbc	1167	#define FSL_FEATURE_OSC_HAS_OSC0 (1)
AnnaBridge	171:3a7713b1edbc	1168	/* @brief Has OSC external oscillator (without index). */
AnnaBridge	171:3a7713b1edbc	1169	#define FSL_FEATURE_OSC_HAS_OSC (0)
AnnaBridge	171:3a7713b1edbc	1170	/* @brief Number of OSC external oscillators. */
AnnaBridge	171:3a7713b1edbc	1171	#define FSL_FEATURE_OSC_OSC_COUNT (1)
AnnaBridge	171:3a7713b1edbc	1172	/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
AnnaBridge	171:3a7713b1edbc	1173	#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
AnnaBridge	171:3a7713b1edbc	1174
AnnaBridge	171:3a7713b1edbc	1175	/* PIT module features */
AnnaBridge	171:3a7713b1edbc	1176
AnnaBridge	171:3a7713b1edbc	1177	/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
AnnaBridge	171:3a7713b1edbc	1178	#define FSL_FEATURE_PIT_TIMER_COUNT (2)
AnnaBridge	171:3a7713b1edbc	1179	/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
AnnaBridge	171:3a7713b1edbc	1180	#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
AnnaBridge	171:3a7713b1edbc	1181	/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
AnnaBridge	171:3a7713b1edbc	1182	#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
AnnaBridge	171:3a7713b1edbc	1183	/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
AnnaBridge	171:3a7713b1edbc	1184	#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1)
AnnaBridge	171:3a7713b1edbc	1185
AnnaBridge	171:3a7713b1edbc	1186	/* PMC module features */
AnnaBridge	171:3a7713b1edbc	1187
AnnaBridge	171:3a7713b1edbc	1188	/* @brief Has Bandgap Enable In VLPx Operation support. */
AnnaBridge	171:3a7713b1edbc	1189	#define FSL_FEATURE_PMC_HAS_BGEN (1)
AnnaBridge	171:3a7713b1edbc	1190	/* @brief Has Bandgap Buffer Enable. */
AnnaBridge	171:3a7713b1edbc	1191	#define FSL_FEATURE_PMC_HAS_BGBE (1)
AnnaBridge	171:3a7713b1edbc	1192	/* @brief Has Bandgap Buffer Drive Select. */
AnnaBridge	171:3a7713b1edbc	1193	#define FSL_FEATURE_PMC_HAS_BGBDS (0)
AnnaBridge	171:3a7713b1edbc	1194	/* @brief Has Low-Voltage Detect Voltage Select support. */
AnnaBridge	171:3a7713b1edbc	1195	#define FSL_FEATURE_PMC_HAS_LVDV (1)
AnnaBridge	171:3a7713b1edbc	1196	/* @brief Has Low-Voltage Warning Voltage Select support. */
AnnaBridge	171:3a7713b1edbc	1197	#define FSL_FEATURE_PMC_HAS_LVWV (1)
AnnaBridge	171:3a7713b1edbc	1198	/* @brief Has LPO. */
AnnaBridge	171:3a7713b1edbc	1199	#define FSL_FEATURE_PMC_HAS_LPO (0)
AnnaBridge	171:3a7713b1edbc	1200	/* @brief Has VLPx option PMC_REGSC[VLPO]. */
AnnaBridge	171:3a7713b1edbc	1201	#define FSL_FEATURE_PMC_HAS_VLPO (1)
AnnaBridge	171:3a7713b1edbc	1202	/* @brief Has acknowledge isolation support. */
AnnaBridge	171:3a7713b1edbc	1203	#define FSL_FEATURE_PMC_HAS_ACKISO (1)
AnnaBridge	171:3a7713b1edbc	1204	/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
AnnaBridge	171:3a7713b1edbc	1205	#define FSL_FEATURE_PMC_HAS_REGFPM (0)
AnnaBridge	171:3a7713b1edbc	1206	/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
AnnaBridge	171:3a7713b1edbc	1207	#define FSL_FEATURE_PMC_HAS_REGONS (1)
AnnaBridge	171:3a7713b1edbc	1208	/* @brief Has PMC_HVDSC1. */
AnnaBridge	171:3a7713b1edbc	1209	#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
AnnaBridge	171:3a7713b1edbc	1210	/* @brief Has PMC_PARAM. */
AnnaBridge	171:3a7713b1edbc	1211	#define FSL_FEATURE_PMC_HAS_PARAM (0)
AnnaBridge	171:3a7713b1edbc	1212	/* @brief Has PMC_VERID. */
AnnaBridge	171:3a7713b1edbc	1213	#define FSL_FEATURE_PMC_HAS_VERID (0)
AnnaBridge	171:3a7713b1edbc	1214
AnnaBridge	171:3a7713b1edbc	1215	/* PORT module features */
AnnaBridge	171:3a7713b1edbc	1216
AnnaBridge	171:3a7713b1edbc	1217	/* @brief Has control lock (register bit PCR[LK]). */
AnnaBridge	171:3a7713b1edbc	1218	#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0)
AnnaBridge	171:3a7713b1edbc	1219	/* @brief Has open drain control (register bit PCR[ODE]). */
AnnaBridge	171:3a7713b1edbc	1220	#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0)
AnnaBridge	171:3a7713b1edbc	1221	/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
AnnaBridge	171:3a7713b1edbc	1222	#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0)
AnnaBridge	171:3a7713b1edbc	1223	/* @brief Has DMA request (register bit field PCR[IRQC] values). */
AnnaBridge	171:3a7713b1edbc	1224	#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
AnnaBridge	171:3a7713b1edbc	1225	/* @brief Has pull resistor selection available. */
AnnaBridge	171:3a7713b1edbc	1226	#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
AnnaBridge	171:3a7713b1edbc	1227	/* @brief Has pull resistor enable (register bit PCR[PE]). */
AnnaBridge	171:3a7713b1edbc	1228	#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
AnnaBridge	171:3a7713b1edbc	1229	/* @brief Has slew rate control (register bit PCR[SRE]). */
AnnaBridge	171:3a7713b1edbc	1230	#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
AnnaBridge	171:3a7713b1edbc	1231	/* @brief Has passive filter (register bit field PCR[PFE]). */
AnnaBridge	171:3a7713b1edbc	1232	#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
AnnaBridge	171:3a7713b1edbc	1233	/* @brief Has drive strength control (register bit PCR[DSE]). */
AnnaBridge	171:3a7713b1edbc	1234	#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
AnnaBridge	171:3a7713b1edbc	1235	/* @brief Has separate drive strength register (HDRVE). */
AnnaBridge	171:3a7713b1edbc	1236	#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
AnnaBridge	171:3a7713b1edbc	1237	/* @brief Has glitch filter (register IOFLT). */
AnnaBridge	171:3a7713b1edbc	1238	#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
AnnaBridge	171:3a7713b1edbc	1239	/* @brief Defines width of PCR[MUX] field. */
AnnaBridge	171:3a7713b1edbc	1240	#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
AnnaBridge	171:3a7713b1edbc	1241	/* @brief Has dedicated interrupt vector. */
AnnaBridge	171:3a7713b1edbc	1242	#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
AnnaBridge	171:3a7713b1edbc	1243	/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
AnnaBridge	171:3a7713b1edbc	1244	#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
AnnaBridge	171:3a7713b1edbc	1245	/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
AnnaBridge	171:3a7713b1edbc	1246	#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
AnnaBridge	171:3a7713b1edbc	1247
AnnaBridge	171:3a7713b1edbc	1248	/* RCM module features */
AnnaBridge	171:3a7713b1edbc	1249
AnnaBridge	171:3a7713b1edbc	1250	/* @brief Has Loss-of-Lock Reset support. */
AnnaBridge	171:3a7713b1edbc	1251	#define FSL_FEATURE_RCM_HAS_LOL (0)
AnnaBridge	171:3a7713b1edbc	1252	/* @brief Has Loss-of-Clock Reset support. */
AnnaBridge	171:3a7713b1edbc	1253	#define FSL_FEATURE_RCM_HAS_LOC (0)
AnnaBridge	171:3a7713b1edbc	1254	/* @brief Has JTAG generated Reset support. */
AnnaBridge	171:3a7713b1edbc	1255	#define FSL_FEATURE_RCM_HAS_JTAG (0)
AnnaBridge	171:3a7713b1edbc	1256	/* @brief Has EzPort generated Reset support. */
AnnaBridge	171:3a7713b1edbc	1257	#define FSL_FEATURE_RCM_HAS_EZPORT (0)
AnnaBridge	171:3a7713b1edbc	1258	/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
AnnaBridge	171:3a7713b1edbc	1259	#define FSL_FEATURE_RCM_HAS_EZPMS (0)
AnnaBridge	171:3a7713b1edbc	1260	/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
AnnaBridge	171:3a7713b1edbc	1261	#define FSL_FEATURE_RCM_HAS_BOOTROM (1)
AnnaBridge	171:3a7713b1edbc	1262	/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
AnnaBridge	171:3a7713b1edbc	1263	#define FSL_FEATURE_RCM_HAS_SSRS (1)
AnnaBridge	171:3a7713b1edbc	1264	/* @brief Has Version ID Register (RCM_VERID). */
AnnaBridge	171:3a7713b1edbc	1265	#define FSL_FEATURE_RCM_HAS_VERID (0)
AnnaBridge	171:3a7713b1edbc	1266	/* @brief Has Parameter Register (RCM_PARAM). */
AnnaBridge	171:3a7713b1edbc	1267	#define FSL_FEATURE_RCM_HAS_PARAM (0)
AnnaBridge	171:3a7713b1edbc	1268	/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
AnnaBridge	171:3a7713b1edbc	1269	#define FSL_FEATURE_RCM_HAS_SRIE (0)
AnnaBridge	171:3a7713b1edbc	1270	/* @brief Width of registers of the RCM. */
AnnaBridge	171:3a7713b1edbc	1271	#define FSL_FEATURE_RCM_REG_WIDTH (8)
AnnaBridge	171:3a7713b1edbc	1272	/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
AnnaBridge	171:3a7713b1edbc	1273	#define FSL_FEATURE_RCM_HAS_CORE1 (0)
AnnaBridge	171:3a7713b1edbc	1274	/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
AnnaBridge	171:3a7713b1edbc	1275	#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
AnnaBridge	171:3a7713b1edbc	1276	/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
AnnaBridge	171:3a7713b1edbc	1277	#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
AnnaBridge	171:3a7713b1edbc	1278
AnnaBridge	171:3a7713b1edbc	1279	/* RTC module features */
AnnaBridge	171:3a7713b1edbc	1280
AnnaBridge	171:3a7713b1edbc	1281	/* @brief Has wakeup pin. */
AnnaBridge	171:3a7713b1edbc	1282	#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
AnnaBridge	171:3a7713b1edbc	1283	/* @brief Has wakeup pin selection (bit field CR[WPS]). */
AnnaBridge	171:3a7713b1edbc	1284	#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
AnnaBridge	171:3a7713b1edbc	1285	/* @brief Has low power features (registers MER, MCLR and MCHR). */
AnnaBridge	171:3a7713b1edbc	1286	#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
AnnaBridge	171:3a7713b1edbc	1287	/* @brief Has read/write access control (registers WAR and RAR). */
AnnaBridge	171:3a7713b1edbc	1288	#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0)
AnnaBridge	171:3a7713b1edbc	1289	/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
AnnaBridge	171:3a7713b1edbc	1290	#define FSL_FEATURE_RTC_HAS_SECURITY (0)
AnnaBridge	171:3a7713b1edbc	1291	/* @brief Has RTC_CLKIN available. */
AnnaBridge	171:3a7713b1edbc	1292	#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1)
AnnaBridge	171:3a7713b1edbc	1293	/* @brief Has prescaler adjust for LPO. */
AnnaBridge	171:3a7713b1edbc	1294	#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
AnnaBridge	171:3a7713b1edbc	1295	/* @brief Has Clock Pin Enable field. */
AnnaBridge	171:3a7713b1edbc	1296	#define FSL_FEATURE_RTC_HAS_CPE (0)
AnnaBridge	171:3a7713b1edbc	1297	/* @brief Has Timer Seconds Interrupt Configuration field. */
AnnaBridge	171:3a7713b1edbc	1298	#define FSL_FEATURE_RTC_HAS_TSIC (0)
AnnaBridge	171:3a7713b1edbc	1299	/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
AnnaBridge	171:3a7713b1edbc	1300	#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
AnnaBridge	171:3a7713b1edbc	1301
AnnaBridge	171:3a7713b1edbc	1302	/* SIM module features */
AnnaBridge	171:3a7713b1edbc	1303
AnnaBridge	171:3a7713b1edbc	1304	/* @brief Has USB FS divider. */
AnnaBridge	171:3a7713b1edbc	1305	#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
AnnaBridge	171:3a7713b1edbc	1306	/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
AnnaBridge	171:3a7713b1edbc	1307	#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
AnnaBridge	171:3a7713b1edbc	1308	/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
AnnaBridge	171:3a7713b1edbc	1309	#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0)
AnnaBridge	171:3a7713b1edbc	1310	/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
AnnaBridge	171:3a7713b1edbc	1311	#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
AnnaBridge	171:3a7713b1edbc	1312	/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
AnnaBridge	171:3a7713b1edbc	1313	#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
AnnaBridge	171:3a7713b1edbc	1314	/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
AnnaBridge	171:3a7713b1edbc	1315	#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
AnnaBridge	171:3a7713b1edbc	1316	/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
AnnaBridge	171:3a7713b1edbc	1317	#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
AnnaBridge	171:3a7713b1edbc	1318	/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
AnnaBridge	171:3a7713b1edbc	1319	#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
AnnaBridge	171:3a7713b1edbc	1320	/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
AnnaBridge	171:3a7713b1edbc	1321	#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
AnnaBridge	171:3a7713b1edbc	1322	/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
AnnaBridge	171:3a7713b1edbc	1323	#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
AnnaBridge	171:3a7713b1edbc	1324	/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
AnnaBridge	171:3a7713b1edbc	1325	#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
AnnaBridge	171:3a7713b1edbc	1326	/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
AnnaBridge	171:3a7713b1edbc	1327	#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
AnnaBridge	171:3a7713b1edbc	1328	/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
AnnaBridge	171:3a7713b1edbc	1329	#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
AnnaBridge	171:3a7713b1edbc	1330	/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
AnnaBridge	171:3a7713b1edbc	1331	#define FSL_FEATURE_SIM_OPT_HAS_ODE (1)
AnnaBridge	171:3a7713b1edbc	1332	/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
AnnaBridge	171:3a7713b1edbc	1333	#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (2)
AnnaBridge	171:3a7713b1edbc	1334	/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
AnnaBridge	171:3a7713b1edbc	1335	#define FSL_FEATURE_SIM_OPT_UART_COUNT (1)
AnnaBridge	171:3a7713b1edbc	1336	/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
AnnaBridge	171:3a7713b1edbc	1337	#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
AnnaBridge	171:3a7713b1edbc	1338	/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
AnnaBridge	171:3a7713b1edbc	1339	#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
AnnaBridge	171:3a7713b1edbc	1340	/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
AnnaBridge	171:3a7713b1edbc	1341	#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (1)
AnnaBridge	171:3a7713b1edbc	1342	/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
AnnaBridge	171:3a7713b1edbc	1343	#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1)
AnnaBridge	171:3a7713b1edbc	1344	/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
AnnaBridge	171:3a7713b1edbc	1345	#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (1)
AnnaBridge	171:3a7713b1edbc	1346	/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
AnnaBridge	171:3a7713b1edbc	1347	#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
AnnaBridge	171:3a7713b1edbc	1348	/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
AnnaBridge	171:3a7713b1edbc	1349	#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
AnnaBridge	171:3a7713b1edbc	1350	/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
AnnaBridge	171:3a7713b1edbc	1351	#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
AnnaBridge	171:3a7713b1edbc	1352	/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
AnnaBridge	171:3a7713b1edbc	1353	#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (1)
AnnaBridge	171:3a7713b1edbc	1354	/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
AnnaBridge	171:3a7713b1edbc	1355	#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (1)
AnnaBridge	171:3a7713b1edbc	1356	/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
AnnaBridge	171:3a7713b1edbc	1357	#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0)
AnnaBridge	171:3a7713b1edbc	1358	/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
AnnaBridge	171:3a7713b1edbc	1359	#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0)
AnnaBridge	171:3a7713b1edbc	1360	/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
AnnaBridge	171:3a7713b1edbc	1361	#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0)
AnnaBridge	171:3a7713b1edbc	1362	/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
AnnaBridge	171:3a7713b1edbc	1363	#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0)
AnnaBridge	171:3a7713b1edbc	1364	/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
AnnaBridge	171:3a7713b1edbc	1365	#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0)
AnnaBridge	171:3a7713b1edbc	1366	/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
AnnaBridge	171:3a7713b1edbc	1367	#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0)
AnnaBridge	171:3a7713b1edbc	1368	/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
AnnaBridge	171:3a7713b1edbc	1369	#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0)
AnnaBridge	171:3a7713b1edbc	1370	/* @brief Has FTM module(s) configuration. */
AnnaBridge	171:3a7713b1edbc	1371	#define FSL_FEATURE_SIM_OPT_HAS_FTM (0)
AnnaBridge	171:3a7713b1edbc	1372	/* @brief Number of FTM modules. */
AnnaBridge	171:3a7713b1edbc	1373	#define FSL_FEATURE_SIM_OPT_FTM_COUNT (0)
AnnaBridge	171:3a7713b1edbc	1374	/* @brief Number of FTM triggers with selectable source. */
AnnaBridge	171:3a7713b1edbc	1375	#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0)
AnnaBridge	171:3a7713b1edbc	1376	/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
AnnaBridge	171:3a7713b1edbc	1377	#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0)
AnnaBridge	171:3a7713b1edbc	1378	/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
AnnaBridge	171:3a7713b1edbc	1379	#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
AnnaBridge	171:3a7713b1edbc	1380	/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
AnnaBridge	171:3a7713b1edbc	1381	#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0)
AnnaBridge	171:3a7713b1edbc	1382	/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
AnnaBridge	171:3a7713b1edbc	1383	#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0)
AnnaBridge	171:3a7713b1edbc	1384	/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
AnnaBridge	171:3a7713b1edbc	1385	#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
AnnaBridge	171:3a7713b1edbc	1386	/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
AnnaBridge	171:3a7713b1edbc	1387	#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
AnnaBridge	171:3a7713b1edbc	1388	/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
AnnaBridge	171:3a7713b1edbc	1389	#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0)
AnnaBridge	171:3a7713b1edbc	1390	/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
AnnaBridge	171:3a7713b1edbc	1391	#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0)
AnnaBridge	171:3a7713b1edbc	1392	/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
AnnaBridge	171:3a7713b1edbc	1393	#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0)
AnnaBridge	171:3a7713b1edbc	1394	/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
AnnaBridge	171:3a7713b1edbc	1395	#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
AnnaBridge	171:3a7713b1edbc	1396	/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
AnnaBridge	171:3a7713b1edbc	1397	#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
AnnaBridge	171:3a7713b1edbc	1398	/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
AnnaBridge	171:3a7713b1edbc	1399	#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
AnnaBridge	171:3a7713b1edbc	1400	/* @brief Has TPM module(s) configuration. */
AnnaBridge	171:3a7713b1edbc	1401	#define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
AnnaBridge	171:3a7713b1edbc	1402	/* @brief The highest TPM module index. */
AnnaBridge	171:3a7713b1edbc	1403	#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
AnnaBridge	171:3a7713b1edbc	1404	/* @brief Has TPM module with index 0. */
AnnaBridge	171:3a7713b1edbc	1405	#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1)
AnnaBridge	171:3a7713b1edbc	1406	/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
AnnaBridge	171:3a7713b1edbc	1407	#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1)
AnnaBridge	171:3a7713b1edbc	1408	/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
AnnaBridge	171:3a7713b1edbc	1409	#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1)
AnnaBridge	171:3a7713b1edbc	1410	/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
AnnaBridge	171:3a7713b1edbc	1411	#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
AnnaBridge	171:3a7713b1edbc	1412	/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
AnnaBridge	171:3a7713b1edbc	1413	#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1)
AnnaBridge	171:3a7713b1edbc	1414	/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
AnnaBridge	171:3a7713b1edbc	1415	#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (2)
AnnaBridge	171:3a7713b1edbc	1416	/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
AnnaBridge	171:3a7713b1edbc	1417	#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1)
AnnaBridge	171:3a7713b1edbc	1418	/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
AnnaBridge	171:3a7713b1edbc	1419	#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1)
AnnaBridge	171:3a7713b1edbc	1420	/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
AnnaBridge	171:3a7713b1edbc	1421	#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0)
AnnaBridge	171:3a7713b1edbc	1422	/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
AnnaBridge	171:3a7713b1edbc	1423	#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0)
AnnaBridge	171:3a7713b1edbc	1424	/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
AnnaBridge	171:3a7713b1edbc	1425	#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
AnnaBridge	171:3a7713b1edbc	1426	/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
AnnaBridge	171:3a7713b1edbc	1427	#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
AnnaBridge	171:3a7713b1edbc	1428	/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
AnnaBridge	171:3a7713b1edbc	1429	#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
AnnaBridge	171:3a7713b1edbc	1430	/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
AnnaBridge	171:3a7713b1edbc	1431	#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
AnnaBridge	171:3a7713b1edbc	1432	/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
AnnaBridge	171:3a7713b1edbc	1433	#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
AnnaBridge	171:3a7713b1edbc	1434	/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
AnnaBridge	171:3a7713b1edbc	1435	#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
AnnaBridge	171:3a7713b1edbc	1436	/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
AnnaBridge	171:3a7713b1edbc	1437	#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
AnnaBridge	171:3a7713b1edbc	1438	/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
AnnaBridge	171:3a7713b1edbc	1439	#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
AnnaBridge	171:3a7713b1edbc	1440	/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
AnnaBridge	171:3a7713b1edbc	1441	#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
AnnaBridge	171:3a7713b1edbc	1442	/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
AnnaBridge	171:3a7713b1edbc	1443	#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
AnnaBridge	171:3a7713b1edbc	1444	/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
AnnaBridge	171:3a7713b1edbc	1445	#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1)
AnnaBridge	171:3a7713b1edbc	1446	/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
AnnaBridge	171:3a7713b1edbc	1447	#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (1)
AnnaBridge	171:3a7713b1edbc	1448	/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
AnnaBridge	171:3a7713b1edbc	1449	#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (1)
AnnaBridge	171:3a7713b1edbc	1450	/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
AnnaBridge	171:3a7713b1edbc	1451	#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
AnnaBridge	171:3a7713b1edbc	1452	/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
AnnaBridge	171:3a7713b1edbc	1453	#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
AnnaBridge	171:3a7713b1edbc	1454	/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
AnnaBridge	171:3a7713b1edbc	1455	#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0)
AnnaBridge	171:3a7713b1edbc	1456	/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
AnnaBridge	171:3a7713b1edbc	1457	#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
AnnaBridge	171:3a7713b1edbc	1458	/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
AnnaBridge	171:3a7713b1edbc	1459	#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0)
AnnaBridge	171:3a7713b1edbc	1460	/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
AnnaBridge	171:3a7713b1edbc	1461	#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
AnnaBridge	171:3a7713b1edbc	1462	/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
AnnaBridge	171:3a7713b1edbc	1463	#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
AnnaBridge	171:3a7713b1edbc	1464	/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
AnnaBridge	171:3a7713b1edbc	1465	#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3)
AnnaBridge	171:3a7713b1edbc	1466	/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
AnnaBridge	171:3a7713b1edbc	1467	#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
AnnaBridge	171:3a7713b1edbc	1468	/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
AnnaBridge	171:3a7713b1edbc	1469	#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
AnnaBridge	171:3a7713b1edbc	1470	/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
AnnaBridge	171:3a7713b1edbc	1471	#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
AnnaBridge	171:3a7713b1edbc	1472	/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
AnnaBridge	171:3a7713b1edbc	1473	#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
AnnaBridge	171:3a7713b1edbc	1474	/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
AnnaBridge	171:3a7713b1edbc	1475	#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
AnnaBridge	171:3a7713b1edbc	1476	/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
AnnaBridge	171:3a7713b1edbc	1477	#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
AnnaBridge	171:3a7713b1edbc	1478	/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
AnnaBridge	171:3a7713b1edbc	1479	#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
AnnaBridge	171:3a7713b1edbc	1480	/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
AnnaBridge	171:3a7713b1edbc	1481	#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
AnnaBridge	171:3a7713b1edbc	1482	/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
AnnaBridge	171:3a7713b1edbc	1483	#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0)
AnnaBridge	171:3a7713b1edbc	1484	/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
AnnaBridge	171:3a7713b1edbc	1485	#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
AnnaBridge	171:3a7713b1edbc	1486	/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
AnnaBridge	171:3a7713b1edbc	1487	#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
AnnaBridge	171:3a7713b1edbc	1488	/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
AnnaBridge	171:3a7713b1edbc	1489	#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
AnnaBridge	171:3a7713b1edbc	1490	/* @brief Has device die ID (register bit field SDID[DIEID]). */
AnnaBridge	171:3a7713b1edbc	1491	#define FSL_FEATURE_SIM_SDID_HAS_DIEID (0)
AnnaBridge	171:3a7713b1edbc	1492	/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
AnnaBridge	171:3a7713b1edbc	1493	#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1)
AnnaBridge	171:3a7713b1edbc	1494	/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
AnnaBridge	171:3a7713b1edbc	1495	#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
AnnaBridge	171:3a7713b1edbc	1496	/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
AnnaBridge	171:3a7713b1edbc	1497	#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
AnnaBridge	171:3a7713b1edbc	1498	/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
AnnaBridge	171:3a7713b1edbc	1499	#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
AnnaBridge	171:3a7713b1edbc	1500	/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
AnnaBridge	171:3a7713b1edbc	1501	#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
AnnaBridge	171:3a7713b1edbc	1502	/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
AnnaBridge	171:3a7713b1edbc	1503	#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
AnnaBridge	171:3a7713b1edbc	1504	/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
AnnaBridge	171:3a7713b1edbc	1505	#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
AnnaBridge	171:3a7713b1edbc	1506	/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
AnnaBridge	171:3a7713b1edbc	1507	#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
AnnaBridge	171:3a7713b1edbc	1508	/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
AnnaBridge	171:3a7713b1edbc	1509	#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
AnnaBridge	171:3a7713b1edbc	1510	/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
AnnaBridge	171:3a7713b1edbc	1511	#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
AnnaBridge	171:3a7713b1edbc	1512	/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
AnnaBridge	171:3a7713b1edbc	1513	#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
AnnaBridge	171:3a7713b1edbc	1514	/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
AnnaBridge	171:3a7713b1edbc	1515	#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
AnnaBridge	171:3a7713b1edbc	1516	/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
AnnaBridge	171:3a7713b1edbc	1517	#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
AnnaBridge	171:3a7713b1edbc	1518	/* @brief Has miscellanious control register (register MCR). */
AnnaBridge	171:3a7713b1edbc	1519	#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
AnnaBridge	171:3a7713b1edbc	1520	/* @brief Has COP watchdog (registers COPC and SRVCOP). */
AnnaBridge	171:3a7713b1edbc	1521	#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1)
AnnaBridge	171:3a7713b1edbc	1522	/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
AnnaBridge	171:3a7713b1edbc	1523	#define FSL_FEATURE_SIM_HAS_COP_STOP (1)
AnnaBridge	171:3a7713b1edbc	1524	/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
AnnaBridge	171:3a7713b1edbc	1525	#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
AnnaBridge	171:3a7713b1edbc	1526
AnnaBridge	171:3a7713b1edbc	1527	/* SMC module features */
AnnaBridge	171:3a7713b1edbc	1528
AnnaBridge	171:3a7713b1edbc	1529	/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
AnnaBridge	171:3a7713b1edbc	1530	#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
AnnaBridge	171:3a7713b1edbc	1531	/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
AnnaBridge	171:3a7713b1edbc	1532	#define FSL_FEATURE_SMC_HAS_LPOPO (1)
AnnaBridge	171:3a7713b1edbc	1533	/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
AnnaBridge	171:3a7713b1edbc	1534	#define FSL_FEATURE_SMC_HAS_PORPO (1)
AnnaBridge	171:3a7713b1edbc	1535	/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
AnnaBridge	171:3a7713b1edbc	1536	#define FSL_FEATURE_SMC_HAS_LPWUI (0)
AnnaBridge	171:3a7713b1edbc	1537	/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
AnnaBridge	171:3a7713b1edbc	1538	#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
AnnaBridge	171:3a7713b1edbc	1539	/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
AnnaBridge	171:3a7713b1edbc	1540	#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
AnnaBridge	171:3a7713b1edbc	1541	/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
AnnaBridge	171:3a7713b1edbc	1542	#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1)
AnnaBridge	171:3a7713b1edbc	1543	/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
AnnaBridge	171:3a7713b1edbc	1544	#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
AnnaBridge	171:3a7713b1edbc	1545	/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
AnnaBridge	171:3a7713b1edbc	1546	#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
AnnaBridge	171:3a7713b1edbc	1547	/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
AnnaBridge	171:3a7713b1edbc	1548	#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
AnnaBridge	171:3a7713b1edbc	1549	/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
AnnaBridge	171:3a7713b1edbc	1550	#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
AnnaBridge	171:3a7713b1edbc	1551	/* @brief Has stop submode. */
AnnaBridge	171:3a7713b1edbc	1552	#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
AnnaBridge	171:3a7713b1edbc	1553	/* @brief Has stop submode 0(VLLS0). */
AnnaBridge	171:3a7713b1edbc	1554	#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
AnnaBridge	171:3a7713b1edbc	1555	/* @brief Has stop submode 2(VLLS2). */
AnnaBridge	171:3a7713b1edbc	1556	#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0)
AnnaBridge	171:3a7713b1edbc	1557	/* @brief Has SMC_PARAM. */
AnnaBridge	171:3a7713b1edbc	1558	#define FSL_FEATURE_SMC_HAS_PARAM (0)
AnnaBridge	171:3a7713b1edbc	1559	/* @brief Has SMC_VERID. */
AnnaBridge	171:3a7713b1edbc	1560	#define FSL_FEATURE_SMC_HAS_VERID (0)
AnnaBridge	171:3a7713b1edbc	1561
AnnaBridge	171:3a7713b1edbc	1562	/* SPI module features */
AnnaBridge	171:3a7713b1edbc	1563
AnnaBridge	171:3a7713b1edbc	1564	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge	171:3a7713b1edbc	1565	#define FSL_FEATURE_SPI_HAS_FIFO (1)
AnnaBridge	171:3a7713b1edbc	1566	/* @brief Has DMA support (register bit fields C2[RXDMAE] and C2[TXDMAE]). */
AnnaBridge	171:3a7713b1edbc	1567	#define FSL_FEATURE_SPI_HAS_DMA_SUPPORT (1)
AnnaBridge	171:3a7713b1edbc	1568	/* @brief Has separate DMA RX and TX requests. */
AnnaBridge	171:3a7713b1edbc	1569	#define FSL_FEATURE_SPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
AnnaBridge	171:3a7713b1edbc	1570	/* @brief Receive/transmit FIFO size in number of 16-bit communication items. */
AnnaBridge	171:3a7713b1edbc	1571	#define FSL_FEATURE_SPI_FIFO_SIZEn(x) \
AnnaBridge	171:3a7713b1edbc	1572	((x) == SPI0 ? (0) : \
AnnaBridge	171:3a7713b1edbc	1573	((x) == SPI1 ? (4) : (-1)))
AnnaBridge	171:3a7713b1edbc	1574	/* @brief Maximum transfer data width in bits. */
AnnaBridge	171:3a7713b1edbc	1575	#define FSL_FEATURE_SPI_MAX_DATA_WIDTH (16)
AnnaBridge	171:3a7713b1edbc	1576	/* @brief The data register name has postfix (L as low and H as high). */
AnnaBridge	171:3a7713b1edbc	1577	#define FSL_FEATURE_SPI_DATA_REGISTER_HAS_POSTFIX (1)
AnnaBridge	171:3a7713b1edbc	1578	/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
AnnaBridge	171:3a7713b1edbc	1579	#define FSL_FEATURE_SPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
AnnaBridge	171:3a7713b1edbc	1580	/* @brief Has 16-bit data transfer support. */
AnnaBridge	171:3a7713b1edbc	1581	#define FSL_FEATURE_SPI_16BIT_TRANSFERS (1)
AnnaBridge	171:3a7713b1edbc	1582
AnnaBridge	171:3a7713b1edbc	1583	/* SysTick module features */
AnnaBridge	171:3a7713b1edbc	1584
AnnaBridge	171:3a7713b1edbc	1585	/* @brief Systick has external reference clock. */
AnnaBridge	171:3a7713b1edbc	1586	#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1)
AnnaBridge	171:3a7713b1edbc	1587	/* @brief Systick external reference clock is core clock divided by this value. */
AnnaBridge	171:3a7713b1edbc	1588	#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16)
AnnaBridge	171:3a7713b1edbc	1589
AnnaBridge	171:3a7713b1edbc	1590	/* TPM module features */
AnnaBridge	171:3a7713b1edbc	1591
AnnaBridge	171:3a7713b1edbc	1592	/* @brief Bus clock is the source clock for the module. */
AnnaBridge	171:3a7713b1edbc	1593	#define FSL_FEATURE_TPM_BUS_CLOCK (0)
AnnaBridge	171:3a7713b1edbc	1594	/* @brief Number of channels. */
AnnaBridge	171:3a7713b1edbc	1595	#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \
AnnaBridge	171:3a7713b1edbc	1596	((x) == TPM0 ? (6) : \
AnnaBridge	171:3a7713b1edbc	1597	((x) == TPM1 ? (2) : \
AnnaBridge	171:3a7713b1edbc	1598	((x) == TPM2 ? (2) : (-1))))
AnnaBridge	171:3a7713b1edbc	1599	/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
AnnaBridge	171:3a7713b1edbc	1600	#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
AnnaBridge	171:3a7713b1edbc	1601	/* @brief Has TPM_PARAM. */
AnnaBridge	171:3a7713b1edbc	1602	#define FSL_FEATURE_TPM_HAS_PARAM (0)
AnnaBridge	171:3a7713b1edbc	1603	/* @brief Has TPM_VERID. */
AnnaBridge	171:3a7713b1edbc	1604	#define FSL_FEATURE_TPM_HAS_VERID (0)
AnnaBridge	171:3a7713b1edbc	1605	/* @brief Has TPM_GLOBAL. */
AnnaBridge	171:3a7713b1edbc	1606	#define FSL_FEATURE_TPM_HAS_GLOBAL (0)
AnnaBridge	171:3a7713b1edbc	1607	/* @brief Has TPM_TRIG. */
AnnaBridge	171:3a7713b1edbc	1608	#define FSL_FEATURE_TPM_HAS_TRIG (0)
AnnaBridge	171:3a7713b1edbc	1609	/* @brief Has counter pause on trigger. */
AnnaBridge	171:3a7713b1edbc	1610	#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
AnnaBridge	171:3a7713b1edbc	1611	/* @brief Has external trigger selection. */
AnnaBridge	171:3a7713b1edbc	1612	#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
AnnaBridge	171:3a7713b1edbc	1613	/* @brief Has TPM_COMBINE. */
AnnaBridge	171:3a7713b1edbc	1614	#define FSL_FEATURE_TPM_HAS_COMBINE (0)
AnnaBridge	171:3a7713b1edbc	1615	/* @brief Has TPM_FILTER. */
AnnaBridge	171:3a7713b1edbc	1616	#define FSL_FEATURE_TPM_HAS_FILTER (0)
AnnaBridge	171:3a7713b1edbc	1617	/* @brief Has TPM_QDCTRL. */
AnnaBridge	171:3a7713b1edbc	1618	#define FSL_FEATURE_TPM_HAS_QDCTRL (0)
AnnaBridge	171:3a7713b1edbc	1619
AnnaBridge	171:3a7713b1edbc	1620	/* UART module features */
AnnaBridge	171:3a7713b1edbc	1621
AnnaBridge	171:3a7713b1edbc	1622	/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
AnnaBridge	171:3a7713b1edbc	1623	#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
AnnaBridge	171:3a7713b1edbc	1624	/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
AnnaBridge	171:3a7713b1edbc	1625	#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1626	/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
AnnaBridge	171:3a7713b1edbc	1627	#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0)
AnnaBridge	171:3a7713b1edbc	1628	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge	171:3a7713b1edbc	1629	#define FSL_FEATURE_UART_HAS_FIFO (0)
AnnaBridge	171:3a7713b1edbc	1630	/* @brief Hardware flow control (RTS, CTS) is supported. */
AnnaBridge	171:3a7713b1edbc	1631	#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1632	/* @brief Infrared (modulation) is supported. */
AnnaBridge	171:3a7713b1edbc	1633	#define FSL_FEATURE_UART_HAS_IR_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1634	/* @brief 2 bits long stop bit is available. */
AnnaBridge	171:3a7713b1edbc	1635	#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1636	/* @brief Maximal data width without parity bit. */
AnnaBridge	171:3a7713b1edbc	1637	#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1638	/* @brief Baud rate fine adjustment is available. */
AnnaBridge	171:3a7713b1edbc	1639	#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
AnnaBridge	171:3a7713b1edbc	1640	/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
AnnaBridge	171:3a7713b1edbc	1641	#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1642	/* @brief Baud rate oversampling is available. */
AnnaBridge	171:3a7713b1edbc	1643	#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1644	/* @brief Baud rate oversampling is available. */
AnnaBridge	171:3a7713b1edbc	1645	#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1646	/* @brief Peripheral type. */
AnnaBridge	171:3a7713b1edbc	1647	#define FSL_FEATURE_UART_IS_SCI (0)
AnnaBridge	171:3a7713b1edbc	1648	/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
AnnaBridge	171:3a7713b1edbc	1649	#define FSL_FEATURE_UART_FIFO_SIZEn(x) (0)
AnnaBridge	171:3a7713b1edbc	1650	/* @brief Maximal data width without parity bit. */
AnnaBridge	171:3a7713b1edbc	1651	#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
AnnaBridge	171:3a7713b1edbc	1652	/* @brief Maximal data width with parity bit. */
AnnaBridge	171:3a7713b1edbc	1653	#define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
AnnaBridge	171:3a7713b1edbc	1654	/* @brief Supports two match addresses to filter incoming frames. */
AnnaBridge	171:3a7713b1edbc	1655	#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
AnnaBridge	171:3a7713b1edbc	1656	/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
AnnaBridge	171:3a7713b1edbc	1657	#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
AnnaBridge	171:3a7713b1edbc	1658	/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
AnnaBridge	171:3a7713b1edbc	1659	#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
AnnaBridge	171:3a7713b1edbc	1660	/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
AnnaBridge	171:3a7713b1edbc	1661	#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
AnnaBridge	171:3a7713b1edbc	1662	/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
AnnaBridge	171:3a7713b1edbc	1663	#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
AnnaBridge	171:3a7713b1edbc	1664	/* @brief Has improved smart card (ISO7816 protocol) support. */
AnnaBridge	171:3a7713b1edbc	1665	#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1)
AnnaBridge	171:3a7713b1edbc	1666	/* @brief Has local operation network (CEA709.1-B protocol) support. */
AnnaBridge	171:3a7713b1edbc	1667	#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
AnnaBridge	171:3a7713b1edbc	1668	/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
AnnaBridge	171:3a7713b1edbc	1669	#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
AnnaBridge	171:3a7713b1edbc	1670	/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
AnnaBridge	171:3a7713b1edbc	1671	#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (0)
AnnaBridge	171:3a7713b1edbc	1672	/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
AnnaBridge	171:3a7713b1edbc	1673	#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (0)
AnnaBridge	171:3a7713b1edbc	1674	/* @brief Has separate DMA RX and TX requests. */
AnnaBridge	171:3a7713b1edbc	1675	#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
AnnaBridge	171:3a7713b1edbc	1676
AnnaBridge	171:3a7713b1edbc	1677	/* USB module features */
AnnaBridge	171:3a7713b1edbc	1678
AnnaBridge	171:3a7713b1edbc	1679	/* @brief HOST mode enabled */
AnnaBridge	171:3a7713b1edbc	1680	#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (0)
AnnaBridge	171:3a7713b1edbc	1681	/* @brief OTG mode enabled */
AnnaBridge	171:3a7713b1edbc	1682	#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (0)
AnnaBridge	171:3a7713b1edbc	1683	/* @brief Size of the USB dedicated RAM */
AnnaBridge	171:3a7713b1edbc	1684	#define FSL_FEATURE_USB_KHCI_USB_RAM (512)
AnnaBridge	171:3a7713b1edbc	1685	/* @brief Base address of the USB dedicated RAM */
AnnaBridge	171:3a7713b1edbc	1686	#define FSL_FEATURE_USB_KHCI_USB_RAM_BASE_ADDRESS (1074782208)
AnnaBridge	171:3a7713b1edbc	1687	/* @brief Has KEEP_ALIVE_CTRL register */
AnnaBridge	171:3a7713b1edbc	1688	#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (1)
AnnaBridge	171:3a7713b1edbc	1689	/* @brief Has the Dynamic SOF threshold compare support */
AnnaBridge	171:3a7713b1edbc	1690	#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
AnnaBridge	171:3a7713b1edbc	1691	/* @brief Has the VBUS detect support */
AnnaBridge	171:3a7713b1edbc	1692	#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
AnnaBridge	171:3a7713b1edbc	1693	/* @brief Has the IRC48M module clock support */
AnnaBridge	171:3a7713b1edbc	1694	#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
AnnaBridge	171:3a7713b1edbc	1695	/* @brief Number of endpoints supported */
AnnaBridge	171:3a7713b1edbc	1696	#define FSL_FEATURE_USB_ENDPT_COUNT (16)
AnnaBridge	171:3a7713b1edbc	1697
AnnaBridge	171:3a7713b1edbc	1698	/* VREF module features */
AnnaBridge	171:3a7713b1edbc	1699
AnnaBridge	171:3a7713b1edbc	1700	/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
AnnaBridge	171:3a7713b1edbc	1701	#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
AnnaBridge	171:3a7713b1edbc	1702	/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
AnnaBridge	171:3a7713b1edbc	1703	#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
AnnaBridge	171:3a7713b1edbc	1704	/* @brief Describes the set of SC[MODE_LV] bitfield values */
AnnaBridge	171:3a7713b1edbc	1705	#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
AnnaBridge	171:3a7713b1edbc	1706	/* @brief Module has also low reference (registers VREFL/VREFH) */
AnnaBridge	171:3a7713b1edbc	1707	#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
AnnaBridge	171:3a7713b1edbc	1708	/* @brief Has VREF_TRM4. */
AnnaBridge	171:3a7713b1edbc	1709	#define FSL_FEATURE_VREF_HAS_TRM4 (0)
AnnaBridge	171:3a7713b1edbc	1710
AnnaBridge	171:3a7713b1edbc	1711	#endif /* _MKL27Z644_FEATURES_H_ */
AnnaBridge	171:3a7713b1edbc	1712