mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_K66F/TOOLCHAIN_IAR/fsl_sdramc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 3 * Copyright 2016-2017 NXP
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 6 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 9 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 13 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 171:3a7713b1edbc 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 17 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 29 */
AnnaBridge 171:3a7713b1edbc 30 #ifndef _FSL_SDRAMC_H_
AnnaBridge 171:3a7713b1edbc 31 #define _FSL_SDRAMC_H_
AnnaBridge 171:3a7713b1edbc 32
AnnaBridge 171:3a7713b1edbc 33 #include "fsl_common.h"
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35 /*!
AnnaBridge 171:3a7713b1edbc 36 * @addtogroup sdramc
AnnaBridge 171:3a7713b1edbc 37 * @{
AnnaBridge 171:3a7713b1edbc 38 */
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 42 * Definitions
AnnaBridge 171:3a7713b1edbc 43 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 44
AnnaBridge 171:3a7713b1edbc 45 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 46 /*@{*/
AnnaBridge 171:3a7713b1edbc 47 /*! @brief SDRAMC driver version 2.1.0. */
AnnaBridge 171:3a7713b1edbc 48 #define FSL_SDRAMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
AnnaBridge 171:3a7713b1edbc 49 /*@}*/
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /*! @brief SDRAM controller auto-refresh timing. */
AnnaBridge 171:3a7713b1edbc 52 typedef enum _sdramc_refresh_time
AnnaBridge 171:3a7713b1edbc 53 {
AnnaBridge 171:3a7713b1edbc 54 kSDRAMC_RefreshThreeClocks = 0x0U, /*!< The refresh timing with three bus clocks. */
AnnaBridge 171:3a7713b1edbc 55 kSDRAMC_RefreshSixClocks, /*!< The refresh timing with six bus clocks. */
AnnaBridge 171:3a7713b1edbc 56 kSDRAMC_RefreshNineClocks /*!< The refresh timing with nine bus clocks. */
AnnaBridge 171:3a7713b1edbc 57 } sdramc_refresh_time_t;
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 /*!
AnnaBridge 171:3a7713b1edbc 60 * @brief Setting latency for SDRAM controller timing specifications.
AnnaBridge 171:3a7713b1edbc 61 *
AnnaBridge 171:3a7713b1edbc 62 * The latency setting affects the following SDRAM timing specifications:
AnnaBridge 171:3a7713b1edbc 63 * - trcd: SRAS assertion to SCAS assertion \n
AnnaBridge 171:3a7713b1edbc 64 * - tcasl: SCAS assertion to data out \n
AnnaBridge 171:3a7713b1edbc 65 * - tras: ACTV command to Precharge command \n
AnnaBridge 171:3a7713b1edbc 66 * - trp: Precharge command to ACTV command \n
AnnaBridge 171:3a7713b1edbc 67 * - trwl, trdl: Last data input to Precharge command \n
AnnaBridge 171:3a7713b1edbc 68 * - tep: Last data out to Precharge command \n
AnnaBridge 171:3a7713b1edbc 69 * The details of the latency setting and timing specifications are shown in the following table list. \n
AnnaBridge 171:3a7713b1edbc 70 * latency trcd: tcasl tras trp trwl,trdl tep \n
AnnaBridge 171:3a7713b1edbc 71 * 0 1 bus clock 1 bus clock 2 bus clocks 1 bus clock 1 bus clock 1 bus clock \n
AnnaBridge 171:3a7713b1edbc 72 * 1 2 bus clock 2 bus clock 4 bus clocks 2 bus clock 1 bus clock 1 bus clock \n
AnnaBridge 171:3a7713b1edbc 73 * 2 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock \n
AnnaBridge 171:3a7713b1edbc 74 * 3 3 bus clock 3 bus clock 6 bus clocks 3 bus clock 1 bus clock 1 bus clock \n
AnnaBridge 171:3a7713b1edbc 75 */
AnnaBridge 171:3a7713b1edbc 76 typedef enum _sdramc_latency
AnnaBridge 171:3a7713b1edbc 77 {
AnnaBridge 171:3a7713b1edbc 78 kSDRAMC_LatencyZero = 0x0U, /*!< Latency 0. */
AnnaBridge 171:3a7713b1edbc 79 kSDRAMC_LatencyOne, /*!< Latency 1. */
AnnaBridge 171:3a7713b1edbc 80 kSDRAMC_LatencyTwo, /*!< Latency 2. */
AnnaBridge 171:3a7713b1edbc 81 kSDRAMC_LatencyThree, /*!< Latency 3. */
AnnaBridge 171:3a7713b1edbc 82 } sdramc_latency_t;
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 /*! @brief SDRAM controller command bit location. */
AnnaBridge 171:3a7713b1edbc 85 typedef enum _sdramc_command_bit_location
AnnaBridge 171:3a7713b1edbc 86 {
AnnaBridge 171:3a7713b1edbc 87 kSDRAMC_Commandbit17 = 0x0U, /*!< Command bit location is bit 17. */
AnnaBridge 171:3a7713b1edbc 88 kSDRAMC_Commandbit18, /*!< Command bit location is bit 18. */
AnnaBridge 171:3a7713b1edbc 89 kSDRAMC_Commandbit19, /*!< Command bit location is bit 19. */
AnnaBridge 171:3a7713b1edbc 90 kSDRAMC_Commandbit20, /*!< Command bit location is bit 20. */
AnnaBridge 171:3a7713b1edbc 91 kSDRAMC_Commandbit21, /*!< Command bit location is bit 21. */
AnnaBridge 171:3a7713b1edbc 92 kSDRAMC_Commandbit22, /*!< Command bit location is bit 22. */
AnnaBridge 171:3a7713b1edbc 93 kSDRAMC_Commandbit23, /*!< Command bit location is bit 23. */
AnnaBridge 171:3a7713b1edbc 94 kSDRAMC_Commandbit24 /*!< Command bit location is bit 24. */
AnnaBridge 171:3a7713b1edbc 95 } sdramc_command_bit_location_t;
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 /*! @brief SDRAM controller command. */
AnnaBridge 171:3a7713b1edbc 98 typedef enum _sdramc_command
AnnaBridge 171:3a7713b1edbc 99 {
AnnaBridge 171:3a7713b1edbc 100 kSDRAMC_ImrsCommand = 0x0U, /*!< Initiate MRS command. */
AnnaBridge 171:3a7713b1edbc 101 kSDRAMC_PrechargeCommand, /*!< Initiate precharge command. */
AnnaBridge 171:3a7713b1edbc 102 kSDRAMC_SelfrefreshEnterCommand, /*!< Enter self-refresh command. */
AnnaBridge 171:3a7713b1edbc 103 kSDRAMC_SelfrefreshExitCommand, /*!< Exit self-refresh command. */
AnnaBridge 171:3a7713b1edbc 104 kSDRAMC_AutoRefreshEnableCommand, /*!< Enable Auto refresh command. */
AnnaBridge 171:3a7713b1edbc 105 kSDRAMC_AutoRefreshDisableCommand, /*!< Disable Auto refresh command. */
AnnaBridge 171:3a7713b1edbc 106 } sdramc_command_t;
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 /*! @brief SDRAM port size. */
AnnaBridge 171:3a7713b1edbc 109 typedef enum _sdramc_port_size
AnnaBridge 171:3a7713b1edbc 110 {
AnnaBridge 171:3a7713b1edbc 111 kSDRAMC_PortSize32Bit = 0x0U, /*!< 32-Bit port size. */
AnnaBridge 171:3a7713b1edbc 112 kSDRAMC_PortSize8Bit, /*!< 8-Bit port size. */
AnnaBridge 171:3a7713b1edbc 113 kSDRAMC_PortSize16Bit /*!< 16-Bit port size. */
AnnaBridge 171:3a7713b1edbc 114 } sdramc_port_size_t;
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 /*! @brief SDRAM controller block selection. */
AnnaBridge 171:3a7713b1edbc 117 typedef enum _sdramc_block_selection
AnnaBridge 171:3a7713b1edbc 118 {
AnnaBridge 171:3a7713b1edbc 119 kSDRAMC_Block0 = 0x0U, /*!< Select SDRAM block 0. */
AnnaBridge 171:3a7713b1edbc 120 kSDRAMC_Block1, /*!< Select SDRAM block 1. */
AnnaBridge 171:3a7713b1edbc 121 } sdramc_block_selection_t;
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123 /*! @brief SDRAM controller block control configuration structure. */
AnnaBridge 171:3a7713b1edbc 124 typedef struct _sdramc_blockctl_config
AnnaBridge 171:3a7713b1edbc 125 {
AnnaBridge 171:3a7713b1edbc 126 sdramc_block_selection_t block; /*!< The block number. */
AnnaBridge 171:3a7713b1edbc 127 sdramc_port_size_t portSize; /*!< The port size of the associated SDRAM block. */
AnnaBridge 171:3a7713b1edbc 128 sdramc_command_bit_location_t location; /*!< The command bit location. */
AnnaBridge 171:3a7713b1edbc 129 sdramc_latency_t latency; /*!< The latency for some timing specifications. */
AnnaBridge 171:3a7713b1edbc 130 uint32_t address; /*!< The base address of the SDRAM block. */
AnnaBridge 171:3a7713b1edbc 131 uint32_t addressMask; /*!< The base address mask of the SDRAM block. */
AnnaBridge 171:3a7713b1edbc 132 } sdramc_blockctl_config_t;
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 /*! @brief SDRAM controller refresh timing configuration structure. */
AnnaBridge 171:3a7713b1edbc 135 typedef struct _sdramc_refresh_config
AnnaBridge 171:3a7713b1edbc 136 {
AnnaBridge 171:3a7713b1edbc 137 sdramc_refresh_time_t refreshTime; /*!< Trc:The number of bus clocks inserted
AnnaBridge 171:3a7713b1edbc 138 between a REF and next ACTIVE command. */
AnnaBridge 171:3a7713b1edbc 139 uint32_t sdramRefreshRow; /*!< The SDRAM refresh time each row: ns/row. */
AnnaBridge 171:3a7713b1edbc 140 uint32_t busClock_Hz; /*!< The bus clock for SDRAMC. */
AnnaBridge 171:3a7713b1edbc 141 } sdramc_refresh_config_t;
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 /*!
AnnaBridge 171:3a7713b1edbc 144 * @brief SDRAM controller configuration structure.
AnnaBridge 171:3a7713b1edbc 145 *
AnnaBridge 171:3a7713b1edbc 146 * Defines a configure structure and uses the SDRAMC_Configure() function to make necessary
AnnaBridge 171:3a7713b1edbc 147 * initializations.
AnnaBridge 171:3a7713b1edbc 148 */
AnnaBridge 171:3a7713b1edbc 149 typedef struct _sdramc_config_t
AnnaBridge 171:3a7713b1edbc 150 {
AnnaBridge 171:3a7713b1edbc 151 sdramc_refresh_config_t *refreshConfig; /*!< Refresh timing configure structure pointer. */
AnnaBridge 171:3a7713b1edbc 152 sdramc_blockctl_config_t *blockConfig; /*!< Block configure structure pointer. If both SDRAM
AnnaBridge 171:3a7713b1edbc 153 blocks are used, use the two continuous blockConfig. */
AnnaBridge 171:3a7713b1edbc 154 uint8_t numBlockConfig; /*!< SDRAM block numbers for configuration. */
AnnaBridge 171:3a7713b1edbc 155 } sdramc_config_t;
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 158 * API
AnnaBridge 171:3a7713b1edbc 159 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 162 extern "C" {
AnnaBridge 171:3a7713b1edbc 163 #endif
AnnaBridge 171:3a7713b1edbc 164
AnnaBridge 171:3a7713b1edbc 165 /*!
AnnaBridge 171:3a7713b1edbc 166 * @name SDRAM Controller Initialization and De-initialization
AnnaBridge 171:3a7713b1edbc 167 * @{
AnnaBridge 171:3a7713b1edbc 168 */
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170 /*!
AnnaBridge 171:3a7713b1edbc 171 * @brief Initializes the SDRAM controller.
AnnaBridge 171:3a7713b1edbc 172 * This function ungates the SDRAM controller clock and initializes the SDRAM controller.
AnnaBridge 171:3a7713b1edbc 173 * This function must be called before calling any other SDRAM controller driver functions.
AnnaBridge 171:3a7713b1edbc 174 * Example
AnnaBridge 171:3a7713b1edbc 175 @code
AnnaBridge 171:3a7713b1edbc 176 sdramc_refresh_config_t refreshConfig;
AnnaBridge 171:3a7713b1edbc 177 sdramc_blockctl_config_t blockConfig;
AnnaBridge 171:3a7713b1edbc 178 sdramc_config_t config;
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 refreshConfig.refreshTime = kSDRAM_RefreshThreeClocks;
AnnaBridge 171:3a7713b1edbc 181 refreshConfig.sdramRefreshRow = 15625;
AnnaBridge 171:3a7713b1edbc 182 refreshConfig.busClock = 60000000;
AnnaBridge 171:3a7713b1edbc 183
AnnaBridge 171:3a7713b1edbc 184 blockConfig.block = kSDRAMC_Block0;
AnnaBridge 171:3a7713b1edbc 185 blockConfig.portSize = kSDRAMC_PortSize16Bit;
AnnaBridge 171:3a7713b1edbc 186 blockConfig.location = kSDRAMC_Commandbit19;
AnnaBridge 171:3a7713b1edbc 187 blockConfig.latency = kSDRAMC_RefreshThreeClocks;
AnnaBridge 171:3a7713b1edbc 188 blockConfig.address = SDRAM_START_ADDRESS;
AnnaBridge 171:3a7713b1edbc 189 blockConfig.addressMask = 0x7c0000;
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 config.refreshConfig = &refreshConfig,
AnnaBridge 171:3a7713b1edbc 192 config.blockConfig = &blockConfig,
AnnaBridge 171:3a7713b1edbc 193 config.totalBlocks = 1;
AnnaBridge 171:3a7713b1edbc 194
AnnaBridge 171:3a7713b1edbc 195 SDRAMC_Init(SDRAM, &config);
AnnaBridge 171:3a7713b1edbc 196 @endcode
AnnaBridge 171:3a7713b1edbc 197 *
AnnaBridge 171:3a7713b1edbc 198 * @param base SDRAM controller peripheral base address.
AnnaBridge 171:3a7713b1edbc 199 * @param configure The SDRAM configuration structure pointer.
AnnaBridge 171:3a7713b1edbc 200 */
AnnaBridge 171:3a7713b1edbc 201 void SDRAMC_Init(SDRAM_Type *base, sdramc_config_t *configure);
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 /*!
AnnaBridge 171:3a7713b1edbc 204 * @brief Deinitializes the SDRAM controller module and gates the clock.
AnnaBridge 171:3a7713b1edbc 205 * This function gates the SDRAM controller clock. As a result, the SDRAM
AnnaBridge 171:3a7713b1edbc 206 * controller module doesn't work after calling this function.
AnnaBridge 171:3a7713b1edbc 207 *
AnnaBridge 171:3a7713b1edbc 208 * @param base SDRAM controller peripheral base address.
AnnaBridge 171:3a7713b1edbc 209 */
AnnaBridge 171:3a7713b1edbc 210 void SDRAMC_Deinit(SDRAM_Type *base);
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 /* @} */
AnnaBridge 171:3a7713b1edbc 213
AnnaBridge 171:3a7713b1edbc 214 /*!
AnnaBridge 171:3a7713b1edbc 215 * @name SDRAM Controller Basic Operation
AnnaBridge 171:3a7713b1edbc 216 * @{
AnnaBridge 171:3a7713b1edbc 217 */
AnnaBridge 171:3a7713b1edbc 218
AnnaBridge 171:3a7713b1edbc 219 /*!
AnnaBridge 171:3a7713b1edbc 220 * @brief Sends the SDRAM command.
AnnaBridge 171:3a7713b1edbc 221 * This function sends commands to SDRAM. The commands are precharge command, initialization MRS command,
AnnaBridge 171:3a7713b1edbc 222 * auto-refresh enable/disable command, and self-refresh enter/exit commands.
AnnaBridge 171:3a7713b1edbc 223 * Note that the self-refresh enter/exit commands are all blocks setting and "block"
AnnaBridge 171:3a7713b1edbc 224 * is ignored. Ensure to set the correct "block" when send other commands.
AnnaBridge 171:3a7713b1edbc 225 *
AnnaBridge 171:3a7713b1edbc 226 * @param base SDRAM controller peripheral base address.
AnnaBridge 171:3a7713b1edbc 227 * @param block The block selection.
AnnaBridge 171:3a7713b1edbc 228 * @param command The SDRAM command, see "sdramc_command_t".
AnnaBridge 171:3a7713b1edbc 229 * kSDRAMC_ImrsCommand - Initialize MRS command \n
AnnaBridge 171:3a7713b1edbc 230 * kSDRAMC_PrechargeCommand - Initialize precharge command \n
AnnaBridge 171:3a7713b1edbc 231 * kSDRAMC_SelfrefreshEnterCommand - Enter self-refresh command \n
AnnaBridge 171:3a7713b1edbc 232 * kSDRAMC_SelfrefreshExitCommand - Exit self-refresh command \n
AnnaBridge 171:3a7713b1edbc 233 * kSDRAMC_AutoRefreshEnableCommand - Enable auto refresh command \n
AnnaBridge 171:3a7713b1edbc 234 * kSDRAMC_AutoRefreshDisableCommand - Disable auto refresh command
AnnaBridge 171:3a7713b1edbc 235 */
AnnaBridge 171:3a7713b1edbc 236 void SDRAMC_SendCommand(SDRAM_Type *base, sdramc_block_selection_t block, sdramc_command_t command);
AnnaBridge 171:3a7713b1edbc 237
AnnaBridge 171:3a7713b1edbc 238 /*!
AnnaBridge 171:3a7713b1edbc 239 * @brief Enables/disables the write protection.
AnnaBridge 171:3a7713b1edbc 240 *
AnnaBridge 171:3a7713b1edbc 241 * @param base SDRAM peripheral base address.
AnnaBridge 171:3a7713b1edbc 242 * @param block The block which is selected.
AnnaBridge 171:3a7713b1edbc 243 * @param enable True enable write protection, false disable write protection.
AnnaBridge 171:3a7713b1edbc 244 */
AnnaBridge 171:3a7713b1edbc 245 static inline void SDRAMC_EnableWriteProtect(SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
AnnaBridge 171:3a7713b1edbc 246 {
AnnaBridge 171:3a7713b1edbc 247 if (enable)
AnnaBridge 171:3a7713b1edbc 248 {
AnnaBridge 171:3a7713b1edbc 249 base->BLOCK[block].CM |= SDRAM_CM_WP_MASK;
AnnaBridge 171:3a7713b1edbc 250 }
AnnaBridge 171:3a7713b1edbc 251 else
AnnaBridge 171:3a7713b1edbc 252 {
AnnaBridge 171:3a7713b1edbc 253 base->BLOCK[block].CM &= ~SDRAM_CM_WP_MASK;
AnnaBridge 171:3a7713b1edbc 254 }
AnnaBridge 171:3a7713b1edbc 255 }
AnnaBridge 171:3a7713b1edbc 256
AnnaBridge 171:3a7713b1edbc 257 /*!
AnnaBridge 171:3a7713b1edbc 258 * @brief Enables/disables the valid operation.
AnnaBridge 171:3a7713b1edbc 259 *
AnnaBridge 171:3a7713b1edbc 260 * @param base SDRAM peripheral base address.
AnnaBridge 171:3a7713b1edbc 261 * @param block The block which is selected.
AnnaBridge 171:3a7713b1edbc 262 * @param enable True enable the valid operation; false disable the valid operation.
AnnaBridge 171:3a7713b1edbc 263 */
AnnaBridge 171:3a7713b1edbc 264 static inline void SDRAMC_EnableOperateValid(SDRAM_Type *base, sdramc_block_selection_t block, bool enable)
AnnaBridge 171:3a7713b1edbc 265 {
AnnaBridge 171:3a7713b1edbc 266 if (enable)
AnnaBridge 171:3a7713b1edbc 267 {
AnnaBridge 171:3a7713b1edbc 268 base->BLOCK[block].CM |= SDRAM_CM_V_MASK;
AnnaBridge 171:3a7713b1edbc 269 }
AnnaBridge 171:3a7713b1edbc 270 else
AnnaBridge 171:3a7713b1edbc 271 {
AnnaBridge 171:3a7713b1edbc 272 base->BLOCK[block].CM &= ~SDRAM_CM_V_MASK;
AnnaBridge 171:3a7713b1edbc 273 }
AnnaBridge 171:3a7713b1edbc 274 }
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 /* @} */
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 279 }
AnnaBridge 171:3a7713b1edbc 280 #endif
AnnaBridge 171:3a7713b1edbc 281
AnnaBridge 171:3a7713b1edbc 282 /*! @}*/
AnnaBridge 171:3a7713b1edbc 283
AnnaBridge 171:3a7713b1edbc 284 #endif /* _FSL_SDRAMC_H_*/