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TARGET_K22F/TOOLCHAIN_IAR/fsl_dspi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/*
AnnaBridge	171:3a7713b1edbc	2	* Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge	171:3a7713b1edbc	3	* All rights reserved.
AnnaBridge	171:3a7713b1edbc	4	*
AnnaBridge	171:3a7713b1edbc	5	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	6	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	7	*
AnnaBridge	171:3a7713b1edbc	8	* o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge	171:3a7713b1edbc	9	* of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge	171:3a7713b1edbc	12	* list of conditions and the following disclaimer in the documentation and/or
AnnaBridge	171:3a7713b1edbc	13	* other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	14	*
AnnaBridge	171:3a7713b1edbc	15	* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge	171:3a7713b1edbc	16	* contributors may be used to endorse or promote products derived from this
AnnaBridge	171:3a7713b1edbc	17	* software without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	18	*
AnnaBridge	171:3a7713b1edbc	19	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge	171:3a7713b1edbc	20	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge	171:3a7713b1edbc	21	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	22	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge	171:3a7713b1edbc	23	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge	171:3a7713b1edbc	24	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge	171:3a7713b1edbc	25	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge	171:3a7713b1edbc	26	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge	171:3a7713b1edbc	27	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge	171:3a7713b1edbc	28	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	29	*/
AnnaBridge	171:3a7713b1edbc	30	#ifndef _FSL_DSPI_H_
AnnaBridge	171:3a7713b1edbc	31	#define _FSL_DSPI_H_
AnnaBridge	171:3a7713b1edbc	32
AnnaBridge	171:3a7713b1edbc	33	#include "fsl_common.h"
AnnaBridge	171:3a7713b1edbc	34
AnnaBridge	171:3a7713b1edbc	35	/*!
AnnaBridge	171:3a7713b1edbc	36	* @addtogroup dspi
AnnaBridge	171:3a7713b1edbc	37	* @{
AnnaBridge	171:3a7713b1edbc	38	*/
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	/! @file /
AnnaBridge	171:3a7713b1edbc	41
AnnaBridge	171:3a7713b1edbc	42	/**********************************************************************************************************************
AnnaBridge	171:3a7713b1edbc	43	* Definitions
AnnaBridge	171:3a7713b1edbc	44	*********************************************************************************************************************/
AnnaBridge	171:3a7713b1edbc	45
AnnaBridge	171:3a7713b1edbc	46	/! @name Driver version /
AnnaBridge	171:3a7713b1edbc	47	/@{/
AnnaBridge	171:3a7713b1edbc	48	/! @brief DSPI driver version 2.1.0. /
AnnaBridge	171:3a7713b1edbc	49	#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
AnnaBridge	171:3a7713b1edbc	50	/@}/
AnnaBridge	171:3a7713b1edbc	51
AnnaBridge	171:3a7713b1edbc	52	/! @name Dummy data /
AnnaBridge	171:3a7713b1edbc	53	/@{/
AnnaBridge	171:3a7713b1edbc	54	#define DSPI_MASTER_DUMMY_DATA (0x00U) /!< Master dummy data used for tx if there is not txData. /
AnnaBridge	171:3a7713b1edbc	55	#define DSPI_SLAVE_DUMMY_DATA (0x00U) /!< Slave dummy data used for tx if there is not txData. /
AnnaBridge	171:3a7713b1edbc	56	/@}/
AnnaBridge	171:3a7713b1edbc	57
AnnaBridge	171:3a7713b1edbc	58	/! @brief Status for the DSPI driver./
AnnaBridge	171:3a7713b1edbc	59	enum _dspi_status
AnnaBridge	171:3a7713b1edbc	60	{
AnnaBridge	171:3a7713b1edbc	61	kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0), /!< DSPI transfer is busy./
AnnaBridge	171:3a7713b1edbc	62	kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1), /!< DSPI driver error. /
AnnaBridge	171:3a7713b1edbc	63	kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2), /!< DSPI is idle./
AnnaBridge	171:3a7713b1edbc	64	kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /!< DSPI transfer out Of range. /
AnnaBridge	171:3a7713b1edbc	65	};
AnnaBridge	171:3a7713b1edbc	66
AnnaBridge	171:3a7713b1edbc	67	/! @brief DSPI status flags in SPIx_SR register./
AnnaBridge	171:3a7713b1edbc	68	enum _dspi_flags
AnnaBridge	171:3a7713b1edbc	69	{
AnnaBridge	171:3a7713b1edbc	70	kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK, /!< Transfer Complete Flag. /
AnnaBridge	171:3a7713b1edbc	71	kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK, /!< End of Queue Flag./
AnnaBridge	171:3a7713b1edbc	72	kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK, /!< Transmit FIFO Underflow Flag./
AnnaBridge	171:3a7713b1edbc	73	kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /!< Transmit FIFO Fill Flag./
AnnaBridge	171:3a7713b1edbc	74	kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK, /!< Receive FIFO Overflow Flag./
AnnaBridge	171:3a7713b1edbc	75	kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /!< Receive FIFO Drain Flag./
AnnaBridge	171:3a7713b1edbc	76	kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK, /!< The module is in Stopped/Running state./
AnnaBridge	171:3a7713b1edbc	77	kDSPI_AllStatusFlag = SPI_SR_TCF_MASK \| SPI_SR_EOQF_MASK \| SPI_SR_TFUF_MASK \| SPI_SR_TFFF_MASK \| SPI_SR_RFOF_MASK \|
AnnaBridge	171:3a7713b1edbc	78	SPI_SR_RFDF_MASK \| SPI_SR_TXRXS_MASK /!< All status above./
AnnaBridge	171:3a7713b1edbc	79	};
AnnaBridge	171:3a7713b1edbc	80
AnnaBridge	171:3a7713b1edbc	81	/! @brief DSPI interrupt source./
AnnaBridge	171:3a7713b1edbc	82	enum _dspi_interrupt_enable
AnnaBridge	171:3a7713b1edbc	83	{
AnnaBridge	171:3a7713b1edbc	84	kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK, /!< TCF interrupt enable./
AnnaBridge	171:3a7713b1edbc	85	kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK, /!< EOQF interrupt enable./
AnnaBridge	171:3a7713b1edbc	86	kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK, /!< TFUF interrupt enable./
AnnaBridge	171:3a7713b1edbc	87	kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /!< TFFF interrupt enable, DMA disable./
AnnaBridge	171:3a7713b1edbc	88	kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK, /!< RFOF interrupt enable./
AnnaBridge	171:3a7713b1edbc	89	kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /!< RFDF interrupt enable, DMA disable./
AnnaBridge	171:3a7713b1edbc	90	kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK \| SPI_RSER_EOQF_RE_MASK \| SPI_RSER_TFUF_RE_MASK \|
AnnaBridge	171:3a7713b1edbc	91	SPI_RSER_TFFF_RE_MASK \| SPI_RSER_RFOF_RE_MASK \| SPI_RSER_RFDF_RE_MASK
AnnaBridge	171:3a7713b1edbc	92	/!< All above interrupts enable./
AnnaBridge	171:3a7713b1edbc	93	};
AnnaBridge	171:3a7713b1edbc	94
AnnaBridge	171:3a7713b1edbc	95	/! @brief DSPI DMA source./
AnnaBridge	171:3a7713b1edbc	96	enum _dspi_dma_enable
AnnaBridge	171:3a7713b1edbc	97	{
AnnaBridge	171:3a7713b1edbc	98	kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK \| SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DMA requests.
AnnaBridge	171:3a7713b1edbc	99	No Tx interrupt request. */
AnnaBridge	171:3a7713b1edbc	100	kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK \| SPI_RSER_RFDF_DIRS_MASK) /*!< RFDF flag generates DMA requests.
AnnaBridge	171:3a7713b1edbc	101	No Rx interrupt request. */
AnnaBridge	171:3a7713b1edbc	102	};
AnnaBridge	171:3a7713b1edbc	103
AnnaBridge	171:3a7713b1edbc	104	/! @brief DSPI master or slave mode configuration./
AnnaBridge	171:3a7713b1edbc	105	typedef enum _dspi_master_slave_mode
AnnaBridge	171:3a7713b1edbc	106	{
AnnaBridge	171:3a7713b1edbc	107	kDSPI_Master = 1U, /!< DSPI peripheral operates in master mode./
AnnaBridge	171:3a7713b1edbc	108	kDSPI_Slave = 0U /!< DSPI peripheral operates in slave mode./
AnnaBridge	171:3a7713b1edbc	109	} dspi_master_slave_mode_t;
AnnaBridge	171:3a7713b1edbc	110
AnnaBridge	171:3a7713b1edbc	111	/*!
AnnaBridge	171:3a7713b1edbc	112	* @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer Format. This field is valid
AnnaBridge	171:3a7713b1edbc	113	* only when CPHA bit in CTAR register is 0.
AnnaBridge	171:3a7713b1edbc	114	*/
AnnaBridge	171:3a7713b1edbc	115	typedef enum _dspi_master_sample_point
AnnaBridge	171:3a7713b1edbc	116	{
AnnaBridge	171:3a7713b1edbc	117	kDSPI_SckToSin0Clock = 0U, /!< 0 system clocks between SCK edge and SIN sample./
AnnaBridge	171:3a7713b1edbc	118	kDSPI_SckToSin1Clock = 1U, /!< 1 system clock between SCK edge and SIN sample./
AnnaBridge	171:3a7713b1edbc	119	kDSPI_SckToSin2Clock = 2U /!< 2 system clocks between SCK edge and SIN sample./
AnnaBridge	171:3a7713b1edbc	120	} dspi_master_sample_point_t;
AnnaBridge	171:3a7713b1edbc	121
AnnaBridge	171:3a7713b1edbc	122	/! @brief DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure)./
AnnaBridge	171:3a7713b1edbc	123	typedef enum _dspi_which_pcs_config
AnnaBridge	171:3a7713b1edbc	124	{
AnnaBridge	171:3a7713b1edbc	125	kDSPI_Pcs0 = 1U << 0, /!< Pcs[0] /
AnnaBridge	171:3a7713b1edbc	126	kDSPI_Pcs1 = 1U << 1, /!< Pcs[1] /
AnnaBridge	171:3a7713b1edbc	127	kDSPI_Pcs2 = 1U << 2, /!< Pcs[2] /
AnnaBridge	171:3a7713b1edbc	128	kDSPI_Pcs3 = 1U << 3, /!< Pcs[3] /
AnnaBridge	171:3a7713b1edbc	129	kDSPI_Pcs4 = 1U << 4, /!< Pcs[4] /
AnnaBridge	171:3a7713b1edbc	130	kDSPI_Pcs5 = 1U << 5 /!< Pcs[5] /
AnnaBridge	171:3a7713b1edbc	131	} dspi_which_pcs_t;
AnnaBridge	171:3a7713b1edbc	132
AnnaBridge	171:3a7713b1edbc	133	/! @brief DSPI Peripheral Chip Select (Pcs) Polarity configuration./
AnnaBridge	171:3a7713b1edbc	134	typedef enum _dspi_pcs_polarity_config
AnnaBridge	171:3a7713b1edbc	135	{
AnnaBridge	171:3a7713b1edbc	136	kDSPI_PcsActiveHigh = 0U, /!< Pcs Active High (idles low). /
AnnaBridge	171:3a7713b1edbc	137	kDSPI_PcsActiveLow = 1U /!< Pcs Active Low (idles high). /
AnnaBridge	171:3a7713b1edbc	138	} dspi_pcs_polarity_config_t;
AnnaBridge	171:3a7713b1edbc	139
AnnaBridge	171:3a7713b1edbc	140	/! @brief DSPI Peripheral Chip Select (Pcs) Polarity./
AnnaBridge	171:3a7713b1edbc	141	enum _dspi_pcs_polarity
AnnaBridge	171:3a7713b1edbc	142	{
AnnaBridge	171:3a7713b1edbc	143	kDSPI_Pcs0ActiveLow = 1U << 0, /!< Pcs0 Active Low (idles high). /
AnnaBridge	171:3a7713b1edbc	144	kDSPI_Pcs1ActiveLow = 1U << 1, /!< Pcs1 Active Low (idles high). /
AnnaBridge	171:3a7713b1edbc	145	kDSPI_Pcs2ActiveLow = 1U << 2, /!< Pcs2 Active Low (idles high). /
AnnaBridge	171:3a7713b1edbc	146	kDSPI_Pcs3ActiveLow = 1U << 3, /!< Pcs3 Active Low (idles high). /
AnnaBridge	171:3a7713b1edbc	147	kDSPI_Pcs4ActiveLow = 1U << 4, /!< Pcs4 Active Low (idles high). /
AnnaBridge	171:3a7713b1edbc	148	kDSPI_Pcs5ActiveLow = 1U << 5, /!< Pcs5 Active Low (idles high). /
AnnaBridge	171:3a7713b1edbc	149	kDSPI_PcsAllActiveLow = 0xFFU /!< Pcs0 to Pcs5 Active Low (idles high). /
AnnaBridge	171:3a7713b1edbc	150	};
AnnaBridge	171:3a7713b1edbc	151
AnnaBridge	171:3a7713b1edbc	152	/! @brief DSPI clock polarity configuration for a given CTAR./
AnnaBridge	171:3a7713b1edbc	153	typedef enum _dspi_clock_polarity
AnnaBridge	171:3a7713b1edbc	154	{
AnnaBridge	171:3a7713b1edbc	155	kDSPI_ClockPolarityActiveHigh = 0U, /!< CPOL=0. Active-high DSPI clock (idles low)./
AnnaBridge	171:3a7713b1edbc	156	kDSPI_ClockPolarityActiveLow = 1U /!< CPOL=1. Active-low DSPI clock (idles high)./
AnnaBridge	171:3a7713b1edbc	157	} dspi_clock_polarity_t;
AnnaBridge	171:3a7713b1edbc	158
AnnaBridge	171:3a7713b1edbc	159	/! @brief DSPI clock phase configuration for a given CTAR./
AnnaBridge	171:3a7713b1edbc	160	typedef enum _dspi_clock_phase
AnnaBridge	171:3a7713b1edbc	161	{
AnnaBridge	171:3a7713b1edbc	162	kDSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the
AnnaBridge	171:3a7713b1edbc	163	following edge.*/
AnnaBridge	171:3a7713b1edbc	164	kDSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the
AnnaBridge	171:3a7713b1edbc	165	following edge.*/
AnnaBridge	171:3a7713b1edbc	166	} dspi_clock_phase_t;
AnnaBridge	171:3a7713b1edbc	167
AnnaBridge	171:3a7713b1edbc	168	/! @brief DSPI data shifter direction options for a given CTAR./
AnnaBridge	171:3a7713b1edbc	169	typedef enum _dspi_shift_direction
AnnaBridge	171:3a7713b1edbc	170	{
AnnaBridge	171:3a7713b1edbc	171	kDSPI_MsbFirst = 0U, /!< Data transfers start with most significant bit./
AnnaBridge	171:3a7713b1edbc	172	kDSPI_LsbFirst = 1U /!< Data transfers start with least significant bit./
AnnaBridge	171:3a7713b1edbc	173	} dspi_shift_direction_t;
AnnaBridge	171:3a7713b1edbc	174
AnnaBridge	171:3a7713b1edbc	175	/! @brief DSPI delay type selection./
AnnaBridge	171:3a7713b1edbc	176	typedef enum _dspi_delay_type
AnnaBridge	171:3a7713b1edbc	177	{
AnnaBridge	171:3a7713b1edbc	178	kDSPI_PcsToSck = 1U, /!< Pcs-to-SCK delay. /
AnnaBridge	171:3a7713b1edbc	179	kDSPI_LastSckToPcs, /!< Last SCK edge to Pcs delay. /
AnnaBridge	171:3a7713b1edbc	180	kDSPI_BetweenTransfer /!< Delay between transfers. /
AnnaBridge	171:3a7713b1edbc	181	} dspi_delay_type_t;
AnnaBridge	171:3a7713b1edbc	182
AnnaBridge	171:3a7713b1edbc	183	/! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection./
AnnaBridge	171:3a7713b1edbc	184	typedef enum _dspi_ctar_selection
AnnaBridge	171:3a7713b1edbc	185	{
AnnaBridge	171:3a7713b1edbc	186	kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode, note that CTAR0 and CTAR0_SLAVE are the
AnnaBridge	171:3a7713b1edbc	187	same register address. */
AnnaBridge	171:3a7713b1edbc	188	kDSPI_Ctar1 = 1U, /!< CTAR1 selection option for master mode only. /
AnnaBridge	171:3a7713b1edbc	189	kDSPI_Ctar2 = 2U, /!< CTAR2 selection option for master mode only , note that some device do not support CTAR2. /
AnnaBridge	171:3a7713b1edbc	190	kDSPI_Ctar3 = 3U, /!< CTAR3 selection option for master mode only , note that some device do not support CTAR3. /
AnnaBridge	171:3a7713b1edbc	191	kDSPI_Ctar4 = 4U, /!< CTAR4 selection option for master mode only , note that some device do not support CTAR4. /
AnnaBridge	171:3a7713b1edbc	192	kDSPI_Ctar5 = 5U, /!< CTAR5 selection option for master mode only , note that some device do not support CTAR5. /
AnnaBridge	171:3a7713b1edbc	193	kDSPI_Ctar6 = 6U, /!< CTAR6 selection option for master mode only , note that some device do not support CTAR6. /
AnnaBridge	171:3a7713b1edbc	194	kDSPI_Ctar7 = 7U /!< CTAR7 selection option for master mode only , note that some device do not support CTAR7. /
AnnaBridge	171:3a7713b1edbc	195	} dspi_ctar_selection_t;
AnnaBridge	171:3a7713b1edbc	196
AnnaBridge	171:3a7713b1edbc	197	#define DSPI_MASTER_CTAR_SHIFT (0U) /!< DSPI master CTAR shift macro , internal used. /
AnnaBridge	171:3a7713b1edbc	198	#define DSPI_MASTER_CTAR_MASK (0x0FU) /!< DSPI master CTAR mask macro , internal used. /
AnnaBridge	171:3a7713b1edbc	199	#define DSPI_MASTER_PCS_SHIFT (4U) /!< DSPI master PCS shift macro , internal used. /
AnnaBridge	171:3a7713b1edbc	200	#define DSPI_MASTER_PCS_MASK (0xF0U) /!< DSPI master PCS mask macro , internal used. /
AnnaBridge	171:3a7713b1edbc	201	/! @brief Can use this enumeration for DSPI master transfer configFlags. /
AnnaBridge	171:3a7713b1edbc	202	enum _dspi_transfer_config_flag_for_master
AnnaBridge	171:3a7713b1edbc	203	{
AnnaBridge	171:3a7713b1edbc	204	kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR0 setting. /
AnnaBridge	171:3a7713b1edbc	205	kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR1 setting. /
AnnaBridge	171:3a7713b1edbc	206	kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR2 setting. /
AnnaBridge	171:3a7713b1edbc	207	kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR3 setting. /
AnnaBridge	171:3a7713b1edbc	208	kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR4 setting. /
AnnaBridge	171:3a7713b1edbc	209	kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR5 setting. /
AnnaBridge	171:3a7713b1edbc	210	kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR6 setting. /
AnnaBridge	171:3a7713b1edbc	211	kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /!< DSPI master transfer use CTAR7 setting. /
AnnaBridge	171:3a7713b1edbc	212
AnnaBridge	171:3a7713b1edbc	213	kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /!< DSPI master transfer use PCS0 signal. /
AnnaBridge	171:3a7713b1edbc	214	kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /!< DSPI master transfer use PCS1 signal. /
AnnaBridge	171:3a7713b1edbc	215	kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /!< DSPI master transfer use PCS2 signal./
AnnaBridge	171:3a7713b1edbc	216	kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /!< DSPI master transfer use PCS3 signal. /
AnnaBridge	171:3a7713b1edbc	217	kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /!< DSPI master transfer use PCS4 signal. /
AnnaBridge	171:3a7713b1edbc	218	kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /!< DSPI master transfer use PCS5 signal. /
AnnaBridge	171:3a7713b1edbc	219
AnnaBridge	171:3a7713b1edbc	220	kDSPI_MasterPcsContinuous = 1U << 20, /!< Is PCS signal continuous. /
AnnaBridge	171:3a7713b1edbc	221	kDSPI_MasterActiveAfterTransfer = 1U << 21, /!< Is PCS signal active after last frame transfer./
AnnaBridge	171:3a7713b1edbc	222	};
AnnaBridge	171:3a7713b1edbc	223
AnnaBridge	171:3a7713b1edbc	224	#define DSPI_SLAVE_CTAR_SHIFT (0U) /!< DSPI slave CTAR shift macro , internal used. /
AnnaBridge	171:3a7713b1edbc	225	#define DSPI_SLAVE_CTAR_MASK (0x07U) /!< DSPI slave CTAR mask macro , internal used. /
AnnaBridge	171:3a7713b1edbc	226	/! @brief Can use this enum for DSPI slave transfer configFlags. /
AnnaBridge	171:3a7713b1edbc	227	enum _dspi_transfer_config_flag_for_slave
AnnaBridge	171:3a7713b1edbc	228	{
AnnaBridge	171:3a7713b1edbc	229	kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /!< DSPI slave transfer use CTAR0 setting. /
AnnaBridge	171:3a7713b1edbc	230	/!< DSPI slave can only use PCS0. /
AnnaBridge	171:3a7713b1edbc	231	};
AnnaBridge	171:3a7713b1edbc	232
AnnaBridge	171:3a7713b1edbc	233	/! @brief DSPI transfer state, which is used for DSPI transactional APIs' state machine. /
AnnaBridge	171:3a7713b1edbc	234	enum _dspi_transfer_state
AnnaBridge	171:3a7713b1edbc	235	{
AnnaBridge	171:3a7713b1edbc	236	kDSPI_Idle = 0x0U, /!< Nothing in the transmitter/receiver. /
AnnaBridge	171:3a7713b1edbc	237	kDSPI_Busy, /!< Transfer queue is not finished. /
AnnaBridge	171:3a7713b1edbc	238	kDSPI_Error /!< Transfer error. /
AnnaBridge	171:3a7713b1edbc	239	};
AnnaBridge	171:3a7713b1edbc	240
AnnaBridge	171:3a7713b1edbc	241	/! @brief DSPI master command date configuration used for SPIx_PUSHR./
AnnaBridge	171:3a7713b1edbc	242	typedef struct _dspi_command_data_config
AnnaBridge	171:3a7713b1edbc	243	{
AnnaBridge	171:3a7713b1edbc	244	bool isPcsContinuous; /!< Option to enable the continuous assertion of chip select between transfers./
AnnaBridge	171:3a7713b1edbc	245	dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
AnnaBridge	171:3a7713b1edbc	246	Register (CTAR) to use for CTAS.*/
AnnaBridge	171:3a7713b1edbc	247	dspi_which_pcs_t whichPcs; /!< The desired PCS signal to use for the data transfer./
AnnaBridge	171:3a7713b1edbc	248	bool isEndOfQueue; /!< Signals that the current transfer is the last in the queue./
AnnaBridge	171:3a7713b1edbc	249	bool clearTransferCount; /!< Clears SPI Transfer Counter (SPI_TCNT) before transmission starts./
AnnaBridge	171:3a7713b1edbc	250	} dspi_command_data_config_t;
AnnaBridge	171:3a7713b1edbc	251
AnnaBridge	171:3a7713b1edbc	252	/! @brief DSPI master ctar configuration structure./
AnnaBridge	171:3a7713b1edbc	253	typedef struct _dspi_master_ctar_config
AnnaBridge	171:3a7713b1edbc	254	{
AnnaBridge	171:3a7713b1edbc	255	uint32_t baudRate; /!< Baud Rate for DSPI. /
AnnaBridge	171:3a7713b1edbc	256	uint32_t bitsPerFrame; /!< Bits per frame, minimum 4, maximum 16./
AnnaBridge	171:3a7713b1edbc	257	dspi_clock_polarity_t cpol; /!< Clock polarity. /
AnnaBridge	171:3a7713b1edbc	258	dspi_clock_phase_t cpha; /!< Clock phase. /
AnnaBridge	171:3a7713b1edbc	259	dspi_shift_direction_t direction; /!< MSB or LSB data shift direction. /
AnnaBridge	171:3a7713b1edbc	260
AnnaBridge	171:3a7713b1edbc	261	uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time with nanosecond , set to 0 sets the minimum
AnnaBridge	171:3a7713b1edbc	262	delay. It sets the boundary value if out of range that can be set.*/
AnnaBridge	171:3a7713b1edbc	263	uint32_t lastSckToPcsDelayInNanoSec; /*!< Last SCK to PCS delay time with nanosecond , set to 0 sets the
AnnaBridge	171:3a7713b1edbc	264	minimum delay.It sets the boundary value if out of range that can be
AnnaBridge	171:3a7713b1edbc	265	set.*/
AnnaBridge	171:3a7713b1edbc	266	uint32_t betweenTransferDelayInNanoSec; /*!< After SCK delay time with nanosecond , set to 0 sets the minimum
AnnaBridge	171:3a7713b1edbc	267	delay.It sets the boundary value if out of range that can be set.*/
AnnaBridge	171:3a7713b1edbc	268	} dspi_master_ctar_config_t;
AnnaBridge	171:3a7713b1edbc	269
AnnaBridge	171:3a7713b1edbc	270	/! @brief DSPI master configuration structure./
AnnaBridge	171:3a7713b1edbc	271	typedef struct _dspi_master_config
AnnaBridge	171:3a7713b1edbc	272	{
AnnaBridge	171:3a7713b1edbc	273	dspi_ctar_selection_t whichCtar; /!< Desired CTAR to use. /
AnnaBridge	171:3a7713b1edbc	274	dspi_master_ctar_config_t ctarConfig; /!< Set the ctarConfig to the desired CTAR. /
AnnaBridge	171:3a7713b1edbc	275
AnnaBridge	171:3a7713b1edbc	276	dspi_which_pcs_t whichPcs; /!< Desired Peripheral Chip Select (pcs). /
AnnaBridge	171:3a7713b1edbc	277	dspi_pcs_polarity_config_t pcsActiveHighOrLow; /!< Desired PCS active high or low. /
AnnaBridge	171:3a7713b1edbc	278
AnnaBridge	171:3a7713b1edbc	279	bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable . Note that continuous SCK is only
AnnaBridge	171:3a7713b1edbc	280	supported for CPHA = 1.*/
AnnaBridge	171:3a7713b1edbc	281	bool enableRxFifoOverWrite; /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming
AnnaBridge	171:3a7713b1edbc	282	data is ignored, the data from the transfer that generated the overflow
AnnaBridge	171:3a7713b1edbc	283	is either ignored. ROOE = 1, the incoming data is shifted in to the
AnnaBridge	171:3a7713b1edbc	284	shift to the shift register. */
AnnaBridge	171:3a7713b1edbc	285
AnnaBridge	171:3a7713b1edbc	286	bool enableModifiedTimingFormat; /!< Enables a modified transfer format to be used if it's true./
AnnaBridge	171:3a7713b1edbc	287	dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer
AnnaBridge	171:3a7713b1edbc	288	Format. It's valid only when CPHA=0. */
AnnaBridge	171:3a7713b1edbc	289	} dspi_master_config_t;
AnnaBridge	171:3a7713b1edbc	290
AnnaBridge	171:3a7713b1edbc	291	/! @brief DSPI slave ctar configuration structure./
AnnaBridge	171:3a7713b1edbc	292	typedef struct _dspi_slave_ctar_config
AnnaBridge	171:3a7713b1edbc	293	{
AnnaBridge	171:3a7713b1edbc	294	uint32_t bitsPerFrame; /!< Bits per frame, minimum 4, maximum 16./
AnnaBridge	171:3a7713b1edbc	295	dspi_clock_polarity_t cpol; /!< Clock polarity. /
AnnaBridge	171:3a7713b1edbc	296	dspi_clock_phase_t cpha; /!< Clock phase. /
AnnaBridge	171:3a7713b1edbc	297	/!< Slave only supports MSB , does not support LSB./
AnnaBridge	171:3a7713b1edbc	298	} dspi_slave_ctar_config_t;
AnnaBridge	171:3a7713b1edbc	299
AnnaBridge	171:3a7713b1edbc	300	/! @brief DSPI slave configuration structure./
AnnaBridge	171:3a7713b1edbc	301	typedef struct _dspi_slave_config
AnnaBridge	171:3a7713b1edbc	302	{
AnnaBridge	171:3a7713b1edbc	303	dspi_ctar_selection_t whichCtar; /!< Desired CTAR to use. /
AnnaBridge	171:3a7713b1edbc	304	dspi_slave_ctar_config_t ctarConfig; /!< Set the ctarConfig to the desired CTAR. /
AnnaBridge	171:3a7713b1edbc	305
AnnaBridge	171:3a7713b1edbc	306	bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that continuous SCK is only
AnnaBridge	171:3a7713b1edbc	307	supported for CPHA = 1.*/
AnnaBridge	171:3a7713b1edbc	308	bool enableRxFifoOverWrite; /*!< ROOE, Receive FIFO overflow overwrite enable. ROOE = 0, the incoming
AnnaBridge	171:3a7713b1edbc	309	data is ignored, the data from the transfer that generated the overflow
AnnaBridge	171:3a7713b1edbc	310	is either ignored. ROOE = 1, the incoming data is shifted in to the
AnnaBridge	171:3a7713b1edbc	311	shift to the shift register. */
AnnaBridge	171:3a7713b1edbc	312	bool enableModifiedTimingFormat; /!< Enables a modified transfer format to be used if it's true./
AnnaBridge	171:3a7713b1edbc	313	dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in Modified Transfer
AnnaBridge	171:3a7713b1edbc	314	Format. It's valid only when CPHA=0. */
AnnaBridge	171:3a7713b1edbc	315	} dspi_slave_config_t;
AnnaBridge	171:3a7713b1edbc	316
AnnaBridge	171:3a7713b1edbc	317	/*!
AnnaBridge	171:3a7713b1edbc	318	* @brief Forward declaration of the _dspi_master_handle typedefs.
AnnaBridge	171:3a7713b1edbc	319	*/
AnnaBridge	171:3a7713b1edbc	320	typedef struct _dspi_master_handle dspi_master_handle_t;
AnnaBridge	171:3a7713b1edbc	321
AnnaBridge	171:3a7713b1edbc	322	/*!
AnnaBridge	171:3a7713b1edbc	323	* @brief Forward declaration of the _dspi_slave_handle typedefs.
AnnaBridge	171:3a7713b1edbc	324	*/
AnnaBridge	171:3a7713b1edbc	325	typedef struct _dspi_slave_handle dspi_slave_handle_t;
AnnaBridge	171:3a7713b1edbc	326
AnnaBridge	171:3a7713b1edbc	327	/*!
AnnaBridge	171:3a7713b1edbc	328	* @brief Completion callback function pointer type.
AnnaBridge	171:3a7713b1edbc	329	*
AnnaBridge	171:3a7713b1edbc	330	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	331	* @param handle Pointer to the handle for the DSPI master.
AnnaBridge	171:3a7713b1edbc	332	* @param status Success or error code describing whether the transfer completed.
AnnaBridge	171:3a7713b1edbc	333	* @param userData Arbitrary pointer-dataSized value passed from the application.
AnnaBridge	171:3a7713b1edbc	334	*/
AnnaBridge	171:3a7713b1edbc	335	typedef void (dspi_master_transfer_callback_t)(SPI_Type base,
AnnaBridge	171:3a7713b1edbc	336	dspi_master_handle_t *handle,
AnnaBridge	171:3a7713b1edbc	337	status_t status,
AnnaBridge	171:3a7713b1edbc	338	void *userData);
AnnaBridge	171:3a7713b1edbc	339	/*!
AnnaBridge	171:3a7713b1edbc	340	* @brief Completion callback function pointer type.
AnnaBridge	171:3a7713b1edbc	341	*
AnnaBridge	171:3a7713b1edbc	342	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	343	* @param handle Pointer to the handle for the DSPI slave.
AnnaBridge	171:3a7713b1edbc	344	* @param status Success or error code describing whether the transfer completed.
AnnaBridge	171:3a7713b1edbc	345	* @param userData Arbitrary pointer-dataSized value passed from the application.
AnnaBridge	171:3a7713b1edbc	346	*/
AnnaBridge	171:3a7713b1edbc	347	typedef void (dspi_slave_transfer_callback_t)(SPI_Type base,
AnnaBridge	171:3a7713b1edbc	348	dspi_slave_handle_t *handle,
AnnaBridge	171:3a7713b1edbc	349	status_t status,
AnnaBridge	171:3a7713b1edbc	350	void *userData);
AnnaBridge	171:3a7713b1edbc	351
AnnaBridge	171:3a7713b1edbc	352	/! @brief DSPI master/slave transfer structure./
AnnaBridge	171:3a7713b1edbc	353	typedef struct _dspi_transfer
AnnaBridge	171:3a7713b1edbc	354	{
AnnaBridge	171:3a7713b1edbc	355	uint8_t txData; /!< Send buffer. */
AnnaBridge	171:3a7713b1edbc	356	uint8_t rxData; /!< Receive buffer. */
AnnaBridge	171:3a7713b1edbc	357	volatile size_t dataSize; /!< Transfer bytes. /
AnnaBridge	171:3a7713b1edbc	358
AnnaBridge	171:3a7713b1edbc	359	uint32_t
AnnaBridge	171:3a7713b1edbc	360	configFlags; /*!< Transfer transfer configuration flags , set from _dspi_transfer_config_flag_for_master if the
AnnaBridge	171:3a7713b1edbc	361	transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer
AnnaBridge	171:3a7713b1edbc	362	is used for slave.*/
AnnaBridge	171:3a7713b1edbc	363	} dspi_transfer_t;
AnnaBridge	171:3a7713b1edbc	364
AnnaBridge	171:3a7713b1edbc	365	/! @brief DSPI master transfer handle structure used for transactional API. /
AnnaBridge	171:3a7713b1edbc	366	struct _dspi_master_handle
AnnaBridge	171:3a7713b1edbc	367	{
AnnaBridge	171:3a7713b1edbc	368	uint32_t bitsPerFrame; /!< Desired number of bits per frame. /
AnnaBridge	171:3a7713b1edbc	369	volatile uint32_t command; /!< Desired data command. /
AnnaBridge	171:3a7713b1edbc	370	volatile uint32_t lastCommand; /!< Desired last data command. /
AnnaBridge	171:3a7713b1edbc	371
AnnaBridge	171:3a7713b1edbc	372	uint8_t fifoSize; /!< FIFO dataSize. /
AnnaBridge	171:3a7713b1edbc	373
AnnaBridge	171:3a7713b1edbc	374	volatile bool isPcsActiveAfterTransfer; /!< Is PCS signal keep active after the last frame transfer./
AnnaBridge	171:3a7713b1edbc	375	volatile bool isThereExtraByte; /!< Is there extra byte./
AnnaBridge	171:3a7713b1edbc	376
AnnaBridge	171:3a7713b1edbc	377	uint8_t volatile txData; /!< Send buffer. */
AnnaBridge	171:3a7713b1edbc	378	uint8_t volatile rxData; /!< Receive buffer. */
AnnaBridge	171:3a7713b1edbc	379	volatile size_t remainingSendByteCount; /!< Number of bytes remaining to send./
AnnaBridge	171:3a7713b1edbc	380	volatile size_t remainingReceiveByteCount; /!< Number of bytes remaining to receive./
AnnaBridge	171:3a7713b1edbc	381	size_t totalByteCount; /!< Number of transfer bytes/
AnnaBridge	171:3a7713b1edbc	382
AnnaBridge	171:3a7713b1edbc	383	volatile uint8_t state; /!< DSPI transfer state , _dspi_transfer_state./
AnnaBridge	171:3a7713b1edbc	384
AnnaBridge	171:3a7713b1edbc	385	dspi_master_transfer_callback_t callback; /!< Completion callback. /
AnnaBridge	171:3a7713b1edbc	386	void userData; /!< Callback user data. */
AnnaBridge	171:3a7713b1edbc	387	};
AnnaBridge	171:3a7713b1edbc	388
AnnaBridge	171:3a7713b1edbc	389	/! @brief DSPI slave transfer handle structure used for transactional API. /
AnnaBridge	171:3a7713b1edbc	390	struct _dspi_slave_handle
AnnaBridge	171:3a7713b1edbc	391	{
AnnaBridge	171:3a7713b1edbc	392	uint32_t bitsPerFrame; /!< Desired number of bits per frame. /
AnnaBridge	171:3a7713b1edbc	393	volatile bool isThereExtraByte; /!< Is there extra byte./
AnnaBridge	171:3a7713b1edbc	394
AnnaBridge	171:3a7713b1edbc	395	uint8_t volatile txData; /!< Send buffer. */
AnnaBridge	171:3a7713b1edbc	396	uint8_t volatile rxData; /!< Receive buffer. */
AnnaBridge	171:3a7713b1edbc	397	volatile size_t remainingSendByteCount; /!< Number of bytes remaining to send./
AnnaBridge	171:3a7713b1edbc	398	volatile size_t remainingReceiveByteCount; /!< Number of bytes remaining to receive./
AnnaBridge	171:3a7713b1edbc	399	size_t totalByteCount; /!< Number of transfer bytes/
AnnaBridge	171:3a7713b1edbc	400
AnnaBridge	171:3a7713b1edbc	401	volatile uint8_t state; /!< DSPI transfer state./
AnnaBridge	171:3a7713b1edbc	402
AnnaBridge	171:3a7713b1edbc	403	volatile uint32_t errorCount; /!< Error count for slave transfer./
AnnaBridge	171:3a7713b1edbc	404
AnnaBridge	171:3a7713b1edbc	405	dspi_slave_transfer_callback_t callback; /!< Completion callback. /
AnnaBridge	171:3a7713b1edbc	406	void userData; /!< Callback user data. */
AnnaBridge	171:3a7713b1edbc	407	};
AnnaBridge	171:3a7713b1edbc	408
AnnaBridge	171:3a7713b1edbc	409	/**********************************************************************************************************************
AnnaBridge	171:3a7713b1edbc	410	* API
AnnaBridge	171:3a7713b1edbc	411	*********************************************************************************************************************/
AnnaBridge	171:3a7713b1edbc	412	#if defined(__cplusplus)
AnnaBridge	171:3a7713b1edbc	413	extern "C" {
AnnaBridge	171:3a7713b1edbc	414	#endif /_cplusplus/
AnnaBridge	171:3a7713b1edbc	415
AnnaBridge	171:3a7713b1edbc	416	/*!
AnnaBridge	171:3a7713b1edbc	417	* @name Initialization and deinitialization
AnnaBridge	171:3a7713b1edbc	418	* @{
AnnaBridge	171:3a7713b1edbc	419	*/
AnnaBridge	171:3a7713b1edbc	420
AnnaBridge	171:3a7713b1edbc	421	/*!
AnnaBridge	171:3a7713b1edbc	422	* @brief Initializes the DSPI master.
AnnaBridge	171:3a7713b1edbc	423	*
AnnaBridge	171:3a7713b1edbc	424	* This function initializes the DSPI master configuration. An example use case is as follows:
AnnaBridge	171:3a7713b1edbc	425	* @code
AnnaBridge	171:3a7713b1edbc	426	* dspi_master_config_t masterConfig;
AnnaBridge	171:3a7713b1edbc	427	* masterConfig.whichCtar = kDSPI_Ctar0;
AnnaBridge	171:3a7713b1edbc	428	* masterConfig.ctarConfig.baudRate = 500000000;
AnnaBridge	171:3a7713b1edbc	429	* masterConfig.ctarConfig.bitsPerFrame = 8;
AnnaBridge	171:3a7713b1edbc	430	* masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
AnnaBridge	171:3a7713b1edbc	431	* masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
AnnaBridge	171:3a7713b1edbc	432	* masterConfig.ctarConfig.direction = kDSPI_MsbFirst;
AnnaBridge	171:3a7713b1edbc	433	* masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ;
AnnaBridge	171:3a7713b1edbc	434	* masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ;
AnnaBridge	171:3a7713b1edbc	435	* masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000 / masterConfig.ctarConfig.baudRate ;
AnnaBridge	171:3a7713b1edbc	436	* masterConfig.whichPcs = kDSPI_Pcs0;
AnnaBridge	171:3a7713b1edbc	437	* masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow;
AnnaBridge	171:3a7713b1edbc	438	* masterConfig.enableContinuousSCK = false;
AnnaBridge	171:3a7713b1edbc	439	* masterConfig.enableRxFifoOverWrite = false;
AnnaBridge	171:3a7713b1edbc	440	* masterConfig.enableModifiedTimingFormat = false;
AnnaBridge	171:3a7713b1edbc	441	* masterConfig.samplePoint = kDSPI_SckToSin0Clock;
AnnaBridge	171:3a7713b1edbc	442	* DSPI_MasterInit(base, &masterConfig, srcClock_Hz);
AnnaBridge	171:3a7713b1edbc	443	* @endcode
AnnaBridge	171:3a7713b1edbc	444	*
AnnaBridge	171:3a7713b1edbc	445	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	446	* @param masterConfig Pointer to structure dspi_master_config_t.
AnnaBridge	171:3a7713b1edbc	447	* @param srcClock_Hz Module source input clock in Hertz
AnnaBridge	171:3a7713b1edbc	448	*/
AnnaBridge	171:3a7713b1edbc	449	void DSPI_MasterInit(SPI_Type base, const dspi_master_config_t masterConfig, uint32_t srcClock_Hz);
AnnaBridge	171:3a7713b1edbc	450
AnnaBridge	171:3a7713b1edbc	451	/*!
AnnaBridge	171:3a7713b1edbc	452	* @brief Sets the dspi_master_config_t structure to default values.
AnnaBridge	171:3a7713b1edbc	453	*
AnnaBridge	171:3a7713b1edbc	454	* The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit().
AnnaBridge	171:3a7713b1edbc	455	* User may use the initialized structure unchanged in DSPI_MasterInit() or modify the structure
AnnaBridge	171:3a7713b1edbc	456	* before calling DSPI_MasterInit().
AnnaBridge	171:3a7713b1edbc	457	* Example:
AnnaBridge	171:3a7713b1edbc	458	* @code
AnnaBridge	171:3a7713b1edbc	459	* dspi_master_config_t masterConfig;
AnnaBridge	171:3a7713b1edbc	460	* DSPI_MasterGetDefaultConfig(&masterConfig);
AnnaBridge	171:3a7713b1edbc	461	* @endcode
AnnaBridge	171:3a7713b1edbc	462	* @param masterConfig pointer to dspi_master_config_t structure
AnnaBridge	171:3a7713b1edbc	463	*/
AnnaBridge	171:3a7713b1edbc	464	void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig);
AnnaBridge	171:3a7713b1edbc	465
AnnaBridge	171:3a7713b1edbc	466	/*!
AnnaBridge	171:3a7713b1edbc	467	* @brief DSPI slave configuration.
AnnaBridge	171:3a7713b1edbc	468	*
AnnaBridge	171:3a7713b1edbc	469	* This function initializes the DSPI slave configuration. An example use case is as follows:
AnnaBridge	171:3a7713b1edbc	470	* @code
AnnaBridge	171:3a7713b1edbc	471	* dspi_slave_config_t slaveConfig;
AnnaBridge	171:3a7713b1edbc	472	* slaveConfig->whichCtar = kDSPI_Ctar0;
AnnaBridge	171:3a7713b1edbc	473	* slaveConfig->ctarConfig.bitsPerFrame = 8;
AnnaBridge	171:3a7713b1edbc	474	* slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
AnnaBridge	171:3a7713b1edbc	475	* slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
AnnaBridge	171:3a7713b1edbc	476	* slaveConfig->enableContinuousSCK = false;
AnnaBridge	171:3a7713b1edbc	477	* slaveConfig->enableRxFifoOverWrite = false;
AnnaBridge	171:3a7713b1edbc	478	* slaveConfig->enableModifiedTimingFormat = false;
AnnaBridge	171:3a7713b1edbc	479	* slaveConfig->samplePoint = kDSPI_SckToSin0Clock;
AnnaBridge	171:3a7713b1edbc	480	* DSPI_SlaveInit(base, &slaveConfig);
AnnaBridge	171:3a7713b1edbc	481	* @endcode
AnnaBridge	171:3a7713b1edbc	482	*
AnnaBridge	171:3a7713b1edbc	483	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	484	* @param slaveConfig Pointer to structure dspi_master_config_t.
AnnaBridge	171:3a7713b1edbc	485	*/
AnnaBridge	171:3a7713b1edbc	486	void DSPI_SlaveInit(SPI_Type base, const dspi_slave_config_t slaveConfig);
AnnaBridge	171:3a7713b1edbc	487
AnnaBridge	171:3a7713b1edbc	488	/*!
AnnaBridge	171:3a7713b1edbc	489	* @brief Sets the dspi_slave_config_t structure to default values.
AnnaBridge	171:3a7713b1edbc	490	*
AnnaBridge	171:3a7713b1edbc	491	* The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit().
AnnaBridge	171:3a7713b1edbc	492	* User may use the initialized structure unchanged in DSPI_SlaveInit(), or modify the structure
AnnaBridge	171:3a7713b1edbc	493	* before calling DSPI_SlaveInit().
AnnaBridge	171:3a7713b1edbc	494	* Example:
AnnaBridge	171:3a7713b1edbc	495	* @code
AnnaBridge	171:3a7713b1edbc	496	* dspi_slave_config_t slaveConfig;
AnnaBridge	171:3a7713b1edbc	497	* DSPI_SlaveGetDefaultConfig(&slaveConfig);
AnnaBridge	171:3a7713b1edbc	498	* @endcode
AnnaBridge	171:3a7713b1edbc	499	* @param slaveConfig pointer to dspi_slave_config_t structure.
AnnaBridge	171:3a7713b1edbc	500	*/
AnnaBridge	171:3a7713b1edbc	501	void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig);
AnnaBridge	171:3a7713b1edbc	502
AnnaBridge	171:3a7713b1edbc	503	/*!
AnnaBridge	171:3a7713b1edbc	504	* @brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock.
AnnaBridge	171:3a7713b1edbc	505	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	506	*/
AnnaBridge	171:3a7713b1edbc	507	void DSPI_Deinit(SPI_Type *base);
AnnaBridge	171:3a7713b1edbc	508
AnnaBridge	171:3a7713b1edbc	509	/*!
AnnaBridge	171:3a7713b1edbc	510	* @brief Enables the DSPI peripheral and sets the MCR MDIS to 0.
AnnaBridge	171:3a7713b1edbc	511	*
AnnaBridge	171:3a7713b1edbc	512	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	513	* @param enable pass true to enable module, false to disable module.
AnnaBridge	171:3a7713b1edbc	514	*/
AnnaBridge	171:3a7713b1edbc	515	static inline void DSPI_Enable(SPI_Type *base, bool enable)
AnnaBridge	171:3a7713b1edbc	516	{
AnnaBridge	171:3a7713b1edbc	517	if (enable)
AnnaBridge	171:3a7713b1edbc	518	{
AnnaBridge	171:3a7713b1edbc	519	base->MCR &= ~SPI_MCR_MDIS_MASK;
AnnaBridge	171:3a7713b1edbc	520	}
AnnaBridge	171:3a7713b1edbc	521	else
AnnaBridge	171:3a7713b1edbc	522	{
AnnaBridge	171:3a7713b1edbc	523	base->MCR \|= SPI_MCR_MDIS_MASK;
AnnaBridge	171:3a7713b1edbc	524	}
AnnaBridge	171:3a7713b1edbc	525	}
AnnaBridge	171:3a7713b1edbc	526
AnnaBridge	171:3a7713b1edbc	527	/*!
AnnaBridge	171:3a7713b1edbc	528	*@}
AnnaBridge	171:3a7713b1edbc	529	*/
AnnaBridge	171:3a7713b1edbc	530
AnnaBridge	171:3a7713b1edbc	531	/*!
AnnaBridge	171:3a7713b1edbc	532	* @name Status
AnnaBridge	171:3a7713b1edbc	533	* @{
AnnaBridge	171:3a7713b1edbc	534	*/
AnnaBridge	171:3a7713b1edbc	535
AnnaBridge	171:3a7713b1edbc	536	/*!
AnnaBridge	171:3a7713b1edbc	537	* @brief Gets the DSPI status flag state.
AnnaBridge	171:3a7713b1edbc	538	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	539	* @return The DSPI status(in SR register).
AnnaBridge	171:3a7713b1edbc	540	*/
AnnaBridge	171:3a7713b1edbc	541	static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base)
AnnaBridge	171:3a7713b1edbc	542	{
AnnaBridge	171:3a7713b1edbc	543	return (base->SR);
AnnaBridge	171:3a7713b1edbc	544	}
AnnaBridge	171:3a7713b1edbc	545
AnnaBridge	171:3a7713b1edbc	546	/*!
AnnaBridge	171:3a7713b1edbc	547	* @brief Clears the DSPI status flag.
AnnaBridge	171:3a7713b1edbc	548	*
AnnaBridge	171:3a7713b1edbc	549	* This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the
AnnaBridge	171:3a7713b1edbc	550	* desired status bit to clear. The list of status bits is defined in the dspi_status_and_interrupt_request_t. The
AnnaBridge	171:3a7713b1edbc	551	* function uses these bit positions in its algorithm to clear the desired flag state.
AnnaBridge	171:3a7713b1edbc	552	* Example usage:
AnnaBridge	171:3a7713b1edbc	553	* @code
AnnaBridge	171:3a7713b1edbc	554	* DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag\|kDSPI_EndOfQueueFlag);
AnnaBridge	171:3a7713b1edbc	555	* @endcode
AnnaBridge	171:3a7713b1edbc	556	*
AnnaBridge	171:3a7713b1edbc	557	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	558	* @param statusFlags The status flag , used from type dspi_flags.
AnnaBridge	171:3a7713b1edbc	559	*/
AnnaBridge	171:3a7713b1edbc	560	static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
AnnaBridge	171:3a7713b1edbc	561	{
AnnaBridge	171:3a7713b1edbc	562	base->SR = statusFlags; /!< The status flags are cleared by writing 1 (w1c)./
AnnaBridge	171:3a7713b1edbc	563	}
AnnaBridge	171:3a7713b1edbc	564
AnnaBridge	171:3a7713b1edbc	565	/*!
AnnaBridge	171:3a7713b1edbc	566	*@}
AnnaBridge	171:3a7713b1edbc	567	*/
AnnaBridge	171:3a7713b1edbc	568
AnnaBridge	171:3a7713b1edbc	569	/*!
AnnaBridge	171:3a7713b1edbc	570	* @name Interrupts
AnnaBridge	171:3a7713b1edbc	571	* @{
AnnaBridge	171:3a7713b1edbc	572	*/
AnnaBridge	171:3a7713b1edbc	573
AnnaBridge	171:3a7713b1edbc	574	/*!
AnnaBridge	171:3a7713b1edbc	575	* @brief Enables the DSPI interrupts.
AnnaBridge	171:3a7713b1edbc	576	*
AnnaBridge	171:3a7713b1edbc	577	* This function configures the various interrupt masks of the DSPI. The parameters are base and an interrupt mask.
AnnaBridge	171:3a7713b1edbc	578	* Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request.
AnnaBridge	171:3a7713b1edbc	579	*
AnnaBridge	171:3a7713b1edbc	580	* @code
AnnaBridge	171:3a7713b1edbc	581	* DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable \| kDSPI_EndOfQueueInterruptEnable );
AnnaBridge	171:3a7713b1edbc	582	* @endcode
AnnaBridge	171:3a7713b1edbc	583	*
AnnaBridge	171:3a7713b1edbc	584	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	585	* @param mask The interrupt mask, can use the enum _dspi_interrupt_enable.
AnnaBridge	171:3a7713b1edbc	586	*/
AnnaBridge	171:3a7713b1edbc	587	void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask);
AnnaBridge	171:3a7713b1edbc	588
AnnaBridge	171:3a7713b1edbc	589	/*!
AnnaBridge	171:3a7713b1edbc	590	* @brief Disables the DSPI interrupts.
AnnaBridge	171:3a7713b1edbc	591	*
AnnaBridge	171:3a7713b1edbc	592	* @code
AnnaBridge	171:3a7713b1edbc	593	* DSPI_DisableInterrupts(base, kDSPI_TxCompleteInterruptEnable \| kDSPI_EndOfQueueInterruptEnable );
AnnaBridge	171:3a7713b1edbc	594	* @endcode
AnnaBridge	171:3a7713b1edbc	595	*
AnnaBridge	171:3a7713b1edbc	596	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	597	* @param mask The interrupt mask, can use the enum _dspi_interrupt_enable.
AnnaBridge	171:3a7713b1edbc	598	*/
AnnaBridge	171:3a7713b1edbc	599	static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask)
AnnaBridge	171:3a7713b1edbc	600	{
AnnaBridge	171:3a7713b1edbc	601	base->RSER &= ~mask;
AnnaBridge	171:3a7713b1edbc	602	}
AnnaBridge	171:3a7713b1edbc	603
AnnaBridge	171:3a7713b1edbc	604	/*!
AnnaBridge	171:3a7713b1edbc	605	*@}
AnnaBridge	171:3a7713b1edbc	606	*/
AnnaBridge	171:3a7713b1edbc	607
AnnaBridge	171:3a7713b1edbc	608	/*!
AnnaBridge	171:3a7713b1edbc	609	* @name DMA Control
AnnaBridge	171:3a7713b1edbc	610	* @{
AnnaBridge	171:3a7713b1edbc	611	*/
AnnaBridge	171:3a7713b1edbc	612
AnnaBridge	171:3a7713b1edbc	613	/*!
AnnaBridge	171:3a7713b1edbc	614	* @brief Enables the DSPI DMA request.
AnnaBridge	171:3a7713b1edbc	615	*
AnnaBridge	171:3a7713b1edbc	616	* This function configures the Rx and Tx DMA mask of the DSPI. The parameters are base and a DMA mask.
AnnaBridge	171:3a7713b1edbc	617	* @code
AnnaBridge	171:3a7713b1edbc	618	* DSPI_EnableDMA(base, kDSPI_TxDmaEnable \| kDSPI_RxDmaEnable);
AnnaBridge	171:3a7713b1edbc	619	* @endcode
AnnaBridge	171:3a7713b1edbc	620	*
AnnaBridge	171:3a7713b1edbc	621	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	622	* @param mask The interrupt mask can use the enum dspi_dma_enable.
AnnaBridge	171:3a7713b1edbc	623	*/
AnnaBridge	171:3a7713b1edbc	624	static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask)
AnnaBridge	171:3a7713b1edbc	625	{
AnnaBridge	171:3a7713b1edbc	626	base->RSER \|= mask;
AnnaBridge	171:3a7713b1edbc	627	}
AnnaBridge	171:3a7713b1edbc	628
AnnaBridge	171:3a7713b1edbc	629	/*!
AnnaBridge	171:3a7713b1edbc	630	* @brief Disables the DSPI DMA request.
AnnaBridge	171:3a7713b1edbc	631	*
AnnaBridge	171:3a7713b1edbc	632	* This function configures the Rx and Tx DMA mask of the DSPI. The parameters are base and a DMA mask.
AnnaBridge	171:3a7713b1edbc	633	* @code
AnnaBridge	171:3a7713b1edbc	634	* SPI_DisableDMA(base, kDSPI_TxDmaEnable \| kDSPI_RxDmaEnable);
AnnaBridge	171:3a7713b1edbc	635	* @endcode
AnnaBridge	171:3a7713b1edbc	636	*
AnnaBridge	171:3a7713b1edbc	637	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	638	* @param mask The interrupt mask can use the enum dspi_dma_enable.
AnnaBridge	171:3a7713b1edbc	639	*/
AnnaBridge	171:3a7713b1edbc	640	static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask)
AnnaBridge	171:3a7713b1edbc	641	{
AnnaBridge	171:3a7713b1edbc	642	base->RSER &= ~mask;
AnnaBridge	171:3a7713b1edbc	643	}
AnnaBridge	171:3a7713b1edbc	644
AnnaBridge	171:3a7713b1edbc	645	/*!
AnnaBridge	171:3a7713b1edbc	646	* @brief Gets the DSPI master PUSHR data register address for the DMA operation.
AnnaBridge	171:3a7713b1edbc	647	*
AnnaBridge	171:3a7713b1edbc	648	* This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation.
AnnaBridge	171:3a7713b1edbc	649	*
AnnaBridge	171:3a7713b1edbc	650	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	651	* @return The DSPI master PUSHR data register address.
AnnaBridge	171:3a7713b1edbc	652	*/
AnnaBridge	171:3a7713b1edbc	653	static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base)
AnnaBridge	171:3a7713b1edbc	654	{
AnnaBridge	171:3a7713b1edbc	655	return (uint32_t) & (base->PUSHR);
AnnaBridge	171:3a7713b1edbc	656	}
AnnaBridge	171:3a7713b1edbc	657
AnnaBridge	171:3a7713b1edbc	658	/*!
AnnaBridge	171:3a7713b1edbc	659	* @brief Gets the DSPI slave PUSHR data register address for the DMA operation.
AnnaBridge	171:3a7713b1edbc	660	*
AnnaBridge	171:3a7713b1edbc	661	* This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation.
AnnaBridge	171:3a7713b1edbc	662	*
AnnaBridge	171:3a7713b1edbc	663	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	664	* @return The DSPI slave PUSHR data register address.
AnnaBridge	171:3a7713b1edbc	665	*/
AnnaBridge	171:3a7713b1edbc	666	static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base)
AnnaBridge	171:3a7713b1edbc	667	{
AnnaBridge	171:3a7713b1edbc	668	return (uint32_t) & (base->PUSHR_SLAVE);
AnnaBridge	171:3a7713b1edbc	669	}
AnnaBridge	171:3a7713b1edbc	670
AnnaBridge	171:3a7713b1edbc	671	/*!
AnnaBridge	171:3a7713b1edbc	672	* @brief Gets the DSPI POPR data register address for the DMA operation.
AnnaBridge	171:3a7713b1edbc	673	*
AnnaBridge	171:3a7713b1edbc	674	* This function gets the DSPI POPR data register address as this value is needed for the DMA operation.
AnnaBridge	171:3a7713b1edbc	675	*
AnnaBridge	171:3a7713b1edbc	676	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	677	* @return The DSPI POPR data register address.
AnnaBridge	171:3a7713b1edbc	678	*/
AnnaBridge	171:3a7713b1edbc	679	static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base)
AnnaBridge	171:3a7713b1edbc	680	{
AnnaBridge	171:3a7713b1edbc	681	return (uint32_t) & (base->POPR);
AnnaBridge	171:3a7713b1edbc	682	}
AnnaBridge	171:3a7713b1edbc	683
AnnaBridge	171:3a7713b1edbc	684	/*!
AnnaBridge	171:3a7713b1edbc	685	*@}
AnnaBridge	171:3a7713b1edbc	686	*/
AnnaBridge	171:3a7713b1edbc	687
AnnaBridge	171:3a7713b1edbc	688	/*!
AnnaBridge	171:3a7713b1edbc	689	* @name Bus Operations
AnnaBridge	171:3a7713b1edbc	690	* @{
AnnaBridge	171:3a7713b1edbc	691	*/
AnnaBridge	171:3a7713b1edbc	692
AnnaBridge	171:3a7713b1edbc	693	/*!
AnnaBridge	171:3a7713b1edbc	694	* @brief Configures the DSPI for master or slave.
AnnaBridge	171:3a7713b1edbc	695	*
AnnaBridge	171:3a7713b1edbc	696	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	697	* @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t.
AnnaBridge	171:3a7713b1edbc	698	*/
AnnaBridge	171:3a7713b1edbc	699	static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode)
AnnaBridge	171:3a7713b1edbc	700	{
AnnaBridge	171:3a7713b1edbc	701	base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) \| SPI_MCR_MSTR(mode);
AnnaBridge	171:3a7713b1edbc	702	}
AnnaBridge	171:3a7713b1edbc	703
AnnaBridge	171:3a7713b1edbc	704	/*!
AnnaBridge	171:3a7713b1edbc	705	* @brief Returns whether the DSPI module is in master mode.
AnnaBridge	171:3a7713b1edbc	706	*
AnnaBridge	171:3a7713b1edbc	707	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	708	* @return Returns true if the module is in master mode or false if the module is in slave mode.
AnnaBridge	171:3a7713b1edbc	709	*/
AnnaBridge	171:3a7713b1edbc	710	static inline bool DSPI_IsMaster(SPI_Type *base)
AnnaBridge	171:3a7713b1edbc	711	{
AnnaBridge	171:3a7713b1edbc	712	return (bool)((base->MCR) & SPI_MCR_MSTR_MASK);
AnnaBridge	171:3a7713b1edbc	713	}
AnnaBridge	171:3a7713b1edbc	714	/*!
AnnaBridge	171:3a7713b1edbc	715	* @brief Starts the DSPI transfers and clears HALT bit in MCR.
AnnaBridge	171:3a7713b1edbc	716	*
AnnaBridge	171:3a7713b1edbc	717	* This function sets the module to begin data transfer in either master or slave mode.
AnnaBridge	171:3a7713b1edbc	718	*
AnnaBridge	171:3a7713b1edbc	719	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	720	*/
AnnaBridge	171:3a7713b1edbc	721	static inline void DSPI_StartTransfer(SPI_Type *base)
AnnaBridge	171:3a7713b1edbc	722	{
AnnaBridge	171:3a7713b1edbc	723	base->MCR &= ~SPI_MCR_HALT_MASK;
AnnaBridge	171:3a7713b1edbc	724	}
AnnaBridge	171:3a7713b1edbc	725	/*!
AnnaBridge	171:3a7713b1edbc	726	* @brief Stops (halts) DSPI transfers and sets HALT bit in MCR.
AnnaBridge	171:3a7713b1edbc	727	*
AnnaBridge	171:3a7713b1edbc	728	* This function stops data transfers in either master or slave mode.
AnnaBridge	171:3a7713b1edbc	729	*
AnnaBridge	171:3a7713b1edbc	730	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	731	*/
AnnaBridge	171:3a7713b1edbc	732	static inline void DSPI_StopTransfer(SPI_Type *base)
AnnaBridge	171:3a7713b1edbc	733	{
AnnaBridge	171:3a7713b1edbc	734	base->MCR \|= SPI_MCR_HALT_MASK;
AnnaBridge	171:3a7713b1edbc	735	}
AnnaBridge	171:3a7713b1edbc	736
AnnaBridge	171:3a7713b1edbc	737	/*!
AnnaBridge	171:3a7713b1edbc	738	* @brief Enables (or disables) the DSPI FIFOs.
AnnaBridge	171:3a7713b1edbc	739	*
AnnaBridge	171:3a7713b1edbc	740	* This function allows the caller to disable/enable the Tx and Rx FIFOs (independently).
AnnaBridge	171:3a7713b1edbc	741	* Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO configuration. To enable,
AnnaBridge	171:3a7713b1edbc	742	* the caller must pass in a logic 1 (true).
AnnaBridge	171:3a7713b1edbc	743	*
AnnaBridge	171:3a7713b1edbc	744	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	745	* @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO
AnnaBridge	171:3a7713b1edbc	746	* @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO
AnnaBridge	171:3a7713b1edbc	747	*/
AnnaBridge	171:3a7713b1edbc	748	static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo)
AnnaBridge	171:3a7713b1edbc	749	{
AnnaBridge	171:3a7713b1edbc	750	base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK \| SPI_MCR_DIS_TXF_MASK))) \| SPI_MCR_DIS_TXF(!enableTxFifo) \|
AnnaBridge	171:3a7713b1edbc	751	SPI_MCR_DIS_RXF(!enableRxFifo);
AnnaBridge	171:3a7713b1edbc	752	}
AnnaBridge	171:3a7713b1edbc	753
AnnaBridge	171:3a7713b1edbc	754	/*!
AnnaBridge	171:3a7713b1edbc	755	* @brief Flushes the DSPI FIFOs.
AnnaBridge	171:3a7713b1edbc	756	*
AnnaBridge	171:3a7713b1edbc	757	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	758	* @param flushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO
AnnaBridge	171:3a7713b1edbc	759	* @param flushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO
AnnaBridge	171:3a7713b1edbc	760	*/
AnnaBridge	171:3a7713b1edbc	761	static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo)
AnnaBridge	171:3a7713b1edbc	762	{
AnnaBridge	171:3a7713b1edbc	763	base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK \| SPI_MCR_CLR_RXF_MASK))) \| SPI_MCR_CLR_TXF(flushTxFifo) \|
AnnaBridge	171:3a7713b1edbc	764	SPI_MCR_CLR_RXF(flushRxFifo);
AnnaBridge	171:3a7713b1edbc	765	}
AnnaBridge	171:3a7713b1edbc	766
AnnaBridge	171:3a7713b1edbc	767	/*!
AnnaBridge	171:3a7713b1edbc	768	* @brief Configures the DSPI peripheral chip select polarity simultaneously.
AnnaBridge	171:3a7713b1edbc	769	* For example, PCS0 and PCS1 set to active low and other PCS set to active high. Note that the number of
AnnaBridge	171:3a7713b1edbc	770	* PCSs is specific to the device.
AnnaBridge	171:3a7713b1edbc	771	* @code
AnnaBridge	171:3a7713b1edbc	772	* DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow \| kDSPI_Pcs1ActiveLow);
AnnaBridge	171:3a7713b1edbc	773	@endcode
AnnaBridge	171:3a7713b1edbc	774	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	775	* @param mask The PCS polarity mask , can use the enum _dspi_pcs_polarity.
AnnaBridge	171:3a7713b1edbc	776	*/
AnnaBridge	171:3a7713b1edbc	777	static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask)
AnnaBridge	171:3a7713b1edbc	778	{
AnnaBridge	171:3a7713b1edbc	779	base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) \| SPI_MCR_PCSIS(mask);
AnnaBridge	171:3a7713b1edbc	780	}
AnnaBridge	171:3a7713b1edbc	781
AnnaBridge	171:3a7713b1edbc	782	/*!
AnnaBridge	171:3a7713b1edbc	783	* @brief Sets the DSPI baud rate in bits per second.
AnnaBridge	171:3a7713b1edbc	784	*
AnnaBridge	171:3a7713b1edbc	785	* This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without
AnnaBridge	171:3a7713b1edbc	786	* exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the
AnnaBridge	171:3a7713b1edbc	787	* caller also provide the frequency of the module source clock (in Hertz).
AnnaBridge	171:3a7713b1edbc	788	*
AnnaBridge	171:3a7713b1edbc	789	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	790	* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t
AnnaBridge	171:3a7713b1edbc	791	* @param baudRate_Bps The desired baud rate in bits per second
AnnaBridge	171:3a7713b1edbc	792	* @param srcClock_Hz Module source input clock in Hertz
AnnaBridge	171:3a7713b1edbc	793	* @return The actual calculated baud rate
AnnaBridge	171:3a7713b1edbc	794	*/
AnnaBridge	171:3a7713b1edbc	795	uint32_t DSPI_MasterSetBaudRate(SPI_Type *base,
AnnaBridge	171:3a7713b1edbc	796	dspi_ctar_selection_t whichCtar,
AnnaBridge	171:3a7713b1edbc	797	uint32_t baudRate_Bps,
AnnaBridge	171:3a7713b1edbc	798	uint32_t srcClock_Hz);
AnnaBridge	171:3a7713b1edbc	799
AnnaBridge	171:3a7713b1edbc	800	/*!
AnnaBridge	171:3a7713b1edbc	801	* @brief Manually configures the delay prescaler and scaler for a particular CTAR.
AnnaBridge	171:3a7713b1edbc	802	*
AnnaBridge	171:3a7713b1edbc	803	* This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar
AnnaBridge	171:3a7713b1edbc	804	* (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT)and scalar (DT).
AnnaBridge	171:3a7713b1edbc	805	*
AnnaBridge	171:3a7713b1edbc	806	* These delay names are available in type dspi_delay_type_t.
AnnaBridge	171:3a7713b1edbc	807	*
AnnaBridge	171:3a7713b1edbc	808	* The user passes the delay to configure along with the prescaler and scaler value.
AnnaBridge	171:3a7713b1edbc	809	* This allows the user to directly set the prescaler/scaler values if they have pre-calculated them or if they simply
AnnaBridge	171:3a7713b1edbc	810	* wish to manually increment either value.
AnnaBridge	171:3a7713b1edbc	811	*
AnnaBridge	171:3a7713b1edbc	812	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	813	* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t.
AnnaBridge	171:3a7713b1edbc	814	* @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3).
AnnaBridge	171:3a7713b1edbc	815	* @param scaler The scaler delay value (can be any integer between 0 to 15).
AnnaBridge	171:3a7713b1edbc	816	* @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
AnnaBridge	171:3a7713b1edbc	817	*/
AnnaBridge	171:3a7713b1edbc	818	void DSPI_MasterSetDelayScaler(
AnnaBridge	171:3a7713b1edbc	819	SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay);
AnnaBridge	171:3a7713b1edbc	820
AnnaBridge	171:3a7713b1edbc	821	/*!
AnnaBridge	171:3a7713b1edbc	822	* @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds.
AnnaBridge	171:3a7713b1edbc	823	*
AnnaBridge	171:3a7713b1edbc	824	* This function calculates the values for:
AnnaBridge	171:3a7713b1edbc	825	* PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or
AnnaBridge	171:3a7713b1edbc	826	* After SCK delay pre-scalar (PASC) and scalar (ASC), or
AnnaBridge	171:3a7713b1edbc	827	* Delay after transfer pre-scalar (PDT)and scalar (DT).
AnnaBridge	171:3a7713b1edbc	828	*
AnnaBridge	171:3a7713b1edbc	829	* These delay names are available in type dspi_delay_type_t.
AnnaBridge	171:3a7713b1edbc	830	*
AnnaBridge	171:3a7713b1edbc	831	* The user passes which delay they want to configure along with the desired delay value in nanoseconds. The function
AnnaBridge	171:3a7713b1edbc	832	* calculates the values needed for the prescaler and scaler and returning the actual calculated delay as an exact
AnnaBridge	171:3a7713b1edbc	833	* delay match may not be possible. In this case, the closest match is calculated without going below the desired
AnnaBridge	171:3a7713b1edbc	834	* delay value input.
AnnaBridge	171:3a7713b1edbc	835	* It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum
AnnaBridge	171:3a7713b1edbc	836	* supported delay is returned. The higher level peripheral driver alerts the user of an out of range delay
AnnaBridge	171:3a7713b1edbc	837	* input.
AnnaBridge	171:3a7713b1edbc	838	*
AnnaBridge	171:3a7713b1edbc	839	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	840	* @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t.
AnnaBridge	171:3a7713b1edbc	841	* @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t
AnnaBridge	171:3a7713b1edbc	842	* @param srcClock_Hz Module source input clock in Hertz
AnnaBridge	171:3a7713b1edbc	843	* @param delayTimeInNanoSec The desired delay value in nanoseconds.
AnnaBridge	171:3a7713b1edbc	844	* @return The actual calculated delay value.
AnnaBridge	171:3a7713b1edbc	845	*/
AnnaBridge	171:3a7713b1edbc	846	uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base,
AnnaBridge	171:3a7713b1edbc	847	dspi_ctar_selection_t whichCtar,
AnnaBridge	171:3a7713b1edbc	848	dspi_delay_type_t whichDelay,
AnnaBridge	171:3a7713b1edbc	849	uint32_t srcClock_Hz,
AnnaBridge	171:3a7713b1edbc	850	uint32_t delayTimeInNanoSec);
AnnaBridge	171:3a7713b1edbc	851
AnnaBridge	171:3a7713b1edbc	852	/*!
AnnaBridge	171:3a7713b1edbc	853	* @brief Writes data into the data buffer for master mode.
AnnaBridge	171:3a7713b1edbc	854	*
AnnaBridge	171:3a7713b1edbc	855	* In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
AnnaBridge	171:3a7713b1edbc	856	* provides characteristics of the data such as the optional continuous chip select
AnnaBridge	171:3a7713b1edbc	857	* operation between transfers, the desired Clock and Transfer Attributes register to use for the
AnnaBridge	171:3a7713b1edbc	858	* associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
AnnaBridge	171:3a7713b1edbc	859	* transfer is the last in the queue, and whether to clear the transfer count (normally needed when
AnnaBridge	171:3a7713b1edbc	860	* sending the first frame of a data packet). This is an example:
AnnaBridge	171:3a7713b1edbc	861	* @code
AnnaBridge	171:3a7713b1edbc	862	* dspi_command_data_config_t commandConfig;
AnnaBridge	171:3a7713b1edbc	863	* commandConfig.isPcsContinuous = true;
AnnaBridge	171:3a7713b1edbc	864	* commandConfig.whichCtar = kDSPICtar0;
AnnaBridge	171:3a7713b1edbc	865	* commandConfig.whichPcs = kDSPIPcs0;
AnnaBridge	171:3a7713b1edbc	866	* commandConfig.clearTransferCount = false;
AnnaBridge	171:3a7713b1edbc	867	* commandConfig.isEndOfQueue = false;
AnnaBridge	171:3a7713b1edbc	868	* DSPI_MasterWriteData(base, &commandConfig, dataWord);
AnnaBridge	171:3a7713b1edbc	869	@endcode
AnnaBridge	171:3a7713b1edbc	870	*
AnnaBridge	171:3a7713b1edbc	871	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	872	* @param command Pointer to command structure.
AnnaBridge	171:3a7713b1edbc	873	* @param data The data word to be sent.
AnnaBridge	171:3a7713b1edbc	874	*/
AnnaBridge	171:3a7713b1edbc	875	static inline void DSPI_MasterWriteData(SPI_Type base, dspi_command_data_config_t command, uint16_t data)
AnnaBridge	171:3a7713b1edbc	876	{
AnnaBridge	171:3a7713b1edbc	877	base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) \| SPI_PUSHR_CTAS(command->whichCtar) \|
AnnaBridge	171:3a7713b1edbc	878	SPI_PUSHR_PCS(command->whichPcs) \| SPI_PUSHR_EOQ(command->isEndOfQueue) \|
AnnaBridge	171:3a7713b1edbc	879	SPI_PUSHR_CTCNT(command->clearTransferCount) \| SPI_PUSHR_TXDATA(data);
AnnaBridge	171:3a7713b1edbc	880	}
AnnaBridge	171:3a7713b1edbc	881
AnnaBridge	171:3a7713b1edbc	882	/*!
AnnaBridge	171:3a7713b1edbc	883	* @brief Sets the dspi_command_data_config_t structure to default values.
AnnaBridge	171:3a7713b1edbc	884	*
AnnaBridge	171:3a7713b1edbc	885	* The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx().
AnnaBridge	171:3a7713b1edbc	886	* User may use the initialized structure unchanged in DSPI_MasterWrite_xx() or modify the structure
AnnaBridge	171:3a7713b1edbc	887	* before calling DSPI_MasterWrite_xx().
AnnaBridge	171:3a7713b1edbc	888	* Example:
AnnaBridge	171:3a7713b1edbc	889	* @code
AnnaBridge	171:3a7713b1edbc	890	* dspi_command_data_config_t command;
AnnaBridge	171:3a7713b1edbc	891	* DSPI_GetDefaultDataCommandConfig(&command);
AnnaBridge	171:3a7713b1edbc	892	* @endcode
AnnaBridge	171:3a7713b1edbc	893	* @param command pointer to dspi_command_data_config_t structure.
AnnaBridge	171:3a7713b1edbc	894	*/
AnnaBridge	171:3a7713b1edbc	895	void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command);
AnnaBridge	171:3a7713b1edbc	896
AnnaBridge	171:3a7713b1edbc	897	/*!
AnnaBridge	171:3a7713b1edbc	898	* @brief Writes data into the data buffer master mode and waits till complete to return.
AnnaBridge	171:3a7713b1edbc	899	*
AnnaBridge	171:3a7713b1edbc	900	* In master mode, the 16-bit data is appended to the 16-bit command info. The command portion
AnnaBridge	171:3a7713b1edbc	901	* provides characteristics of the data such as the optional continuous chip select
AnnaBridge	171:3a7713b1edbc	902	* operation between transfers, the desired Clock and Transfer Attributes register to use for the
AnnaBridge	171:3a7713b1edbc	903	* associated SPI frame, the desired PCS signal to use for the data transfer, whether the current
AnnaBridge	171:3a7713b1edbc	904	* transfer is the last in the queue, and whether to clear the transfer count (normally needed when
AnnaBridge	171:3a7713b1edbc	905	* sending the first frame of a data packet). This is an example:
AnnaBridge	171:3a7713b1edbc	906	* @code
AnnaBridge	171:3a7713b1edbc	907	* dspi_command_config_t commandConfig;
AnnaBridge	171:3a7713b1edbc	908	* commandConfig.isPcsContinuous = true;
AnnaBridge	171:3a7713b1edbc	909	* commandConfig.whichCtar = kDSPICtar0;
AnnaBridge	171:3a7713b1edbc	910	* commandConfig.whichPcs = kDSPIPcs1;
AnnaBridge	171:3a7713b1edbc	911	* commandConfig.clearTransferCount = false;
AnnaBridge	171:3a7713b1edbc	912	* commandConfig.isEndOfQueue = false;
AnnaBridge	171:3a7713b1edbc	913	* DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord);
AnnaBridge	171:3a7713b1edbc	914	* @endcode
AnnaBridge	171:3a7713b1edbc	915	*
AnnaBridge	171:3a7713b1edbc	916	* Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
AnnaBridge	171:3a7713b1edbc	917	* enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol,
AnnaBridge	171:3a7713b1edbc	918	* receive data is available when transmit completes.
AnnaBridge	171:3a7713b1edbc	919	*
AnnaBridge	171:3a7713b1edbc	920	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	921	* @param command Pointer to command structure.
AnnaBridge	171:3a7713b1edbc	922	* @param data The data word to be sent.
AnnaBridge	171:3a7713b1edbc	923	*/
AnnaBridge	171:3a7713b1edbc	924	void DSPI_MasterWriteDataBlocking(SPI_Type base, dspi_command_data_config_t command, uint16_t data);
AnnaBridge	171:3a7713b1edbc	925
AnnaBridge	171:3a7713b1edbc	926	/*!
AnnaBridge	171:3a7713b1edbc	927	* @brief Returns the DSPI command word formatted to the PUSHR data register bit field.
AnnaBridge	171:3a7713b1edbc	928	*
AnnaBridge	171:3a7713b1edbc	929	* This function allows the caller to pass in the data command structure and returns the command word formatted
AnnaBridge	171:3a7713b1edbc	930	* according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the
AnnaBridge	171:3a7713b1edbc	931	* desired data to send and use the function DSPI_HAL_WriteCommandDataMastermode or
AnnaBridge	171:3a7713b1edbc	932	* DSPI_HAL_WriteCommandDataMastermodeBlocking to write the entire 32-bit command data word to the PUSHR. This helps
AnnaBridge	171:3a7713b1edbc	933	* improve performance in cases where the command structure is constant. For example, the user calls this function
AnnaBridge	171:3a7713b1edbc	934	* before starting a transfer to generate the command word. When they are ready to transmit the data, they OR
AnnaBridge	171:3a7713b1edbc	935	* this formatted command word with the desired data to transmit. This process increases transmit performance when
AnnaBridge	171:3a7713b1edbc	936	* compared to calling send functions such as DSPI_HAL_WriteDataMastermode which format the command word each time a
AnnaBridge	171:3a7713b1edbc	937	* data word is to be sent.
AnnaBridge	171:3a7713b1edbc	938	*
AnnaBridge	171:3a7713b1edbc	939	* @param command Pointer to command structure.
AnnaBridge	171:3a7713b1edbc	940	* @return The command word formatted to the PUSHR data register bit field.
AnnaBridge	171:3a7713b1edbc	941	*/
AnnaBridge	171:3a7713b1edbc	942	static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command)
AnnaBridge	171:3a7713b1edbc	943	{
AnnaBridge	171:3a7713b1edbc	944	/* Format the 16-bit command word according to the PUSHR data register bit field*/
AnnaBridge	171:3a7713b1edbc	945	return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) \| SPI_PUSHR_CTAS(command->whichCtar) \|
AnnaBridge	171:3a7713b1edbc	946	SPI_PUSHR_PCS(command->whichPcs) \| SPI_PUSHR_EOQ(command->isEndOfQueue) \|
AnnaBridge	171:3a7713b1edbc	947	SPI_PUSHR_CTCNT(command->clearTransferCount));
AnnaBridge	171:3a7713b1edbc	948	}
AnnaBridge	171:3a7713b1edbc	949
AnnaBridge	171:3a7713b1edbc	950	/*!
AnnaBridge	171:3a7713b1edbc	951	* @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data
AnnaBridge	171:3a7713b1edbc	952	* buffer, master mode and waits till complete to return.
AnnaBridge	171:3a7713b1edbc	953	*
AnnaBridge	171:3a7713b1edbc	954	* In this function, the user must append the 16-bit data to the 16-bit command info then provide the total 32-bit word
AnnaBridge	171:3a7713b1edbc	955	* as the data to send.
AnnaBridge	171:3a7713b1edbc	956	* The command portion provides characteristics of the data such as the optional continuous chip select operation
AnnaBridge	171:3a7713b1edbc	957	* between
AnnaBridge	171:3a7713b1edbc	958	* transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS
AnnaBridge	171:3a7713b1edbc	959	* signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the
AnnaBridge	171:3a7713b1edbc	960	* transfer count (normally needed when sending the first frame of a data packet). The user is responsible for
AnnaBridge	171:3a7713b1edbc	961	* appending this command with the data to send. This is an example:
AnnaBridge	171:3a7713b1edbc	962	* @code
AnnaBridge	171:3a7713b1edbc	963	* dataWord = <16-bit command> \| <16-bit data>;
AnnaBridge	171:3a7713b1edbc	964	* DSPI_HAL_WriteCommandDataMastermodeBlocking(base, dataWord);
AnnaBridge	171:3a7713b1edbc	965	* @endcode
AnnaBridge	171:3a7713b1edbc	966	*
AnnaBridge	171:3a7713b1edbc	967	* Note that this function does not return until after the transmit is complete. Also note that the DSPI must be
AnnaBridge	171:3a7713b1edbc	968	* enabled and running to transmit data (MCR[MDIS] & [HALT] = 0).
AnnaBridge	171:3a7713b1edbc	969	* Because the SPI is a synchronous protocol, the receive data is available when transmit completes.
AnnaBridge	171:3a7713b1edbc	970	*
AnnaBridge	171:3a7713b1edbc	971	* For a blocking polling transfer, see methods below.
AnnaBridge	171:3a7713b1edbc	972	* Option 1:
AnnaBridge	171:3a7713b1edbc	973	* uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command);
AnnaBridge	171:3a7713b1edbc	974	* uint32_t data0 = command_to_send \| data_need_to_send_0;
AnnaBridge	171:3a7713b1edbc	975	* uint32_t data1 = command_to_send \| data_need_to_send_1;
AnnaBridge	171:3a7713b1edbc	976	* uint32_t data2 = command_to_send \| data_need_to_send_2;
AnnaBridge	171:3a7713b1edbc	977	*
AnnaBridge	171:3a7713b1edbc	978	* DSPI_MasterWriteCommandDataBlocking(base,data0);
AnnaBridge	171:3a7713b1edbc	979	* DSPI_MasterWriteCommandDataBlocking(base,data1);
AnnaBridge	171:3a7713b1edbc	980	* DSPI_MasterWriteCommandDataBlocking(base,data2);
AnnaBridge	171:3a7713b1edbc	981	*
AnnaBridge	171:3a7713b1edbc	982	* Option 2:
AnnaBridge	171:3a7713b1edbc	983	* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0);
AnnaBridge	171:3a7713b1edbc	984	* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1);
AnnaBridge	171:3a7713b1edbc	985	* DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2);
AnnaBridge	171:3a7713b1edbc	986	*
AnnaBridge	171:3a7713b1edbc	987	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	988	* @param data The data word (command and data combined) to be sent
AnnaBridge	171:3a7713b1edbc	989	*/
AnnaBridge	171:3a7713b1edbc	990	void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data);
AnnaBridge	171:3a7713b1edbc	991
AnnaBridge	171:3a7713b1edbc	992	/*!
AnnaBridge	171:3a7713b1edbc	993	* @brief Writes data into the data buffer in slave mode.
AnnaBridge	171:3a7713b1edbc	994	*
AnnaBridge	171:3a7713b1edbc	995	* In slave mode, up to 16-bit words may be written.
AnnaBridge	171:3a7713b1edbc	996	*
AnnaBridge	171:3a7713b1edbc	997	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	998	* @param data The data to send.
AnnaBridge	171:3a7713b1edbc	999	*/
AnnaBridge	171:3a7713b1edbc	1000	static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data)
AnnaBridge	171:3a7713b1edbc	1001	{
AnnaBridge	171:3a7713b1edbc	1002	base->PUSHR_SLAVE = data;
AnnaBridge	171:3a7713b1edbc	1003	}
AnnaBridge	171:3a7713b1edbc	1004
AnnaBridge	171:3a7713b1edbc	1005	/*!
AnnaBridge	171:3a7713b1edbc	1006	* @brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns.
AnnaBridge	171:3a7713b1edbc	1007	*
AnnaBridge	171:3a7713b1edbc	1008	* In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data
AnnaBridge	171:3a7713b1edbc	1009	* into data register, and finally waits until the data is transmitted.
AnnaBridge	171:3a7713b1edbc	1010	*
AnnaBridge	171:3a7713b1edbc	1011	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	1012	* @param data The data to send.
AnnaBridge	171:3a7713b1edbc	1013	*/
AnnaBridge	171:3a7713b1edbc	1014	void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data);
AnnaBridge	171:3a7713b1edbc	1015
AnnaBridge	171:3a7713b1edbc	1016	/*!
AnnaBridge	171:3a7713b1edbc	1017	* @brief Reads data from the data buffer.
AnnaBridge	171:3a7713b1edbc	1018	*
AnnaBridge	171:3a7713b1edbc	1019	* @param base DSPI peripheral address.
AnnaBridge	171:3a7713b1edbc	1020	* @return The data from the read data buffer.
AnnaBridge	171:3a7713b1edbc	1021	*/
AnnaBridge	171:3a7713b1edbc	1022	static inline uint32_t DSPI_ReadData(SPI_Type *base)
AnnaBridge	171:3a7713b1edbc	1023	{
AnnaBridge	171:3a7713b1edbc	1024	return (base->POPR);
AnnaBridge	171:3a7713b1edbc	1025	}
AnnaBridge	171:3a7713b1edbc	1026
AnnaBridge	171:3a7713b1edbc	1027	/*!
AnnaBridge	171:3a7713b1edbc	1028	*@}
AnnaBridge	171:3a7713b1edbc	1029	*/
AnnaBridge	171:3a7713b1edbc	1030
AnnaBridge	171:3a7713b1edbc	1031	/*!
AnnaBridge	171:3a7713b1edbc	1032	* @name Transactional
AnnaBridge	171:3a7713b1edbc	1033	* @{
AnnaBridge	171:3a7713b1edbc	1034	*/
AnnaBridge	171:3a7713b1edbc	1035	/Transactional APIs/
AnnaBridge	171:3a7713b1edbc	1036
AnnaBridge	171:3a7713b1edbc	1037	/*!
AnnaBridge	171:3a7713b1edbc	1038	* @brief Initializes the DSPI master handle.
AnnaBridge	171:3a7713b1edbc	1039	*
AnnaBridge	171:3a7713b1edbc	1040	* This function initializes the DSPI handle which can be used for other DSPI transactional APIs. Usually, for a
AnnaBridge	171:3a7713b1edbc	1041	* specified DSPI instance, call this API once to get the initialized handle.
AnnaBridge	171:3a7713b1edbc	1042	*
AnnaBridge	171:3a7713b1edbc	1043	* @param base DSPI peripheral base address.
AnnaBridge	171:3a7713b1edbc	1044	* @param handle DSPI handle pointer to dspi_master_handle_t.
AnnaBridge	171:3a7713b1edbc	1045	* @param callback dspi callback.
AnnaBridge	171:3a7713b1edbc	1046	* @param userData callback function parameter.
AnnaBridge	171:3a7713b1edbc	1047	*/
AnnaBridge	171:3a7713b1edbc	1048	void DSPI_MasterTransferCreateHandle(SPI_Type *base,
AnnaBridge	171:3a7713b1edbc	1049	dspi_master_handle_t *handle,
AnnaBridge	171:3a7713b1edbc	1050	dspi_master_transfer_callback_t callback,
AnnaBridge	171:3a7713b1edbc	1051	void *userData);
AnnaBridge	171:3a7713b1edbc	1052
AnnaBridge	171:3a7713b1edbc	1053	/*!
AnnaBridge	171:3a7713b1edbc	1054	* @brief DSPI master transfer data using polling.
AnnaBridge	171:3a7713b1edbc	1055	*
AnnaBridge	171:3a7713b1edbc	1056	* This function transfers data with polling. This is a blocking function, which does not return until all transfers
AnnaBridge	171:3a7713b1edbc	1057	* have been
AnnaBridge	171:3a7713b1edbc	1058	* completed.
AnnaBridge	171:3a7713b1edbc	1059	*
AnnaBridge	171:3a7713b1edbc	1060	* @param base DSPI peripheral base address.
AnnaBridge	171:3a7713b1edbc	1061	* @param transfer pointer to dspi_transfer_t structure.
AnnaBridge	171:3a7713b1edbc	1062	* @return status of status_t.
AnnaBridge	171:3a7713b1edbc	1063	*/
AnnaBridge	171:3a7713b1edbc	1064	status_t DSPI_MasterTransferBlocking(SPI_Type base, dspi_transfer_t transfer);
AnnaBridge	171:3a7713b1edbc	1065
AnnaBridge	171:3a7713b1edbc	1066	/*!
AnnaBridge	171:3a7713b1edbc	1067	* @brief DSPI master transfer data using interrupts.
AnnaBridge	171:3a7713b1edbc	1068	*
AnnaBridge	171:3a7713b1edbc	1069	* This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all
AnnaBridge	171:3a7713b1edbc	1070	data
AnnaBridge	171:3a7713b1edbc	1071	* have been transferred, the callback function is called.
AnnaBridge	171:3a7713b1edbc	1072
AnnaBridge	171:3a7713b1edbc	1073	* @param base DSPI peripheral base address.
AnnaBridge	171:3a7713b1edbc	1074	* @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
AnnaBridge	171:3a7713b1edbc	1075	* @param transfer pointer to dspi_transfer_t structure.
AnnaBridge	171:3a7713b1edbc	1076	* @return status of status_t.
AnnaBridge	171:3a7713b1edbc	1077	*/
AnnaBridge	171:3a7713b1edbc	1078	status_t DSPI_MasterTransferNonBlocking(SPI_Type base, dspi_master_handle_t handle, dspi_transfer_t *transfer);
AnnaBridge	171:3a7713b1edbc	1079
AnnaBridge	171:3a7713b1edbc	1080	/*!
AnnaBridge	171:3a7713b1edbc	1081	* @brief Gets the master transfer count.
AnnaBridge	171:3a7713b1edbc	1082	*
AnnaBridge	171:3a7713b1edbc	1083	* This function gets the master transfer count.
AnnaBridge	171:3a7713b1edbc	1084	*
AnnaBridge	171:3a7713b1edbc	1085	* @param base DSPI peripheral base address.
AnnaBridge	171:3a7713b1edbc	1086	* @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
AnnaBridge	171:3a7713b1edbc	1087	* @param count Number of bytes transferred so far by the non-blocking transaction.
AnnaBridge	171:3a7713b1edbc	1088	* @return status of status_t.
AnnaBridge	171:3a7713b1edbc	1089	*/
AnnaBridge	171:3a7713b1edbc	1090	status_t DSPI_MasterTransferGetCount(SPI_Type base, dspi_master_handle_t handle, size_t *count);
AnnaBridge	171:3a7713b1edbc	1091
AnnaBridge	171:3a7713b1edbc	1092	/*!
AnnaBridge	171:3a7713b1edbc	1093	* @brief DSPI master aborts transfer using an interrupt.
AnnaBridge	171:3a7713b1edbc	1094	*
AnnaBridge	171:3a7713b1edbc	1095	* This function aborts a transfer using an interrupt.
AnnaBridge	171:3a7713b1edbc	1096	*
AnnaBridge	171:3a7713b1edbc	1097	* @param base DSPI peripheral base address.
AnnaBridge	171:3a7713b1edbc	1098	* @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
AnnaBridge	171:3a7713b1edbc	1099	*/
AnnaBridge	171:3a7713b1edbc	1100	void DSPI_MasterTransferAbort(SPI_Type base, dspi_master_handle_t handle);
AnnaBridge	171:3a7713b1edbc	1101
AnnaBridge	171:3a7713b1edbc	1102	/*!
AnnaBridge	171:3a7713b1edbc	1103	* @brief DSPI Master IRQ handler function.
AnnaBridge	171:3a7713b1edbc	1104	*
AnnaBridge	171:3a7713b1edbc	1105	* This function processes the DSPI transmit and receive IRQ.
AnnaBridge	171:3a7713b1edbc	1106
AnnaBridge	171:3a7713b1edbc	1107	* @param base DSPI peripheral base address.
AnnaBridge	171:3a7713b1edbc	1108	* @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
AnnaBridge	171:3a7713b1edbc	1109	*/
AnnaBridge	171:3a7713b1edbc	1110	void DSPI_MasterTransferHandleIRQ(SPI_Type base, dspi_master_handle_t handle);
AnnaBridge	171:3a7713b1edbc	1111
AnnaBridge	171:3a7713b1edbc	1112	/*!
AnnaBridge	171:3a7713b1edbc	1113	* @brief Initializes the DSPI slave handle.
AnnaBridge	171:3a7713b1edbc	1114	*
AnnaBridge	171:3a7713b1edbc	1115	* This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a
AnnaBridge	171:3a7713b1edbc	1116	* specified DSPI instance, call this API once to get the initialized handle.
AnnaBridge	171:3a7713b1edbc	1117	*
AnnaBridge	171:3a7713b1edbc	1118	* @param handle DSPI handle pointer to dspi_slave_handle_t.
AnnaBridge	171:3a7713b1edbc	1119	* @param base DSPI peripheral base address.
AnnaBridge	171:3a7713b1edbc	1120	* @param callback DSPI callback.
AnnaBridge	171:3a7713b1edbc	1121	* @param userData callback function parameter.
AnnaBridge	171:3a7713b1edbc	1122	*/
AnnaBridge	171:3a7713b1edbc	1123	void DSPI_SlaveTransferCreateHandle(SPI_Type *base,
AnnaBridge	171:3a7713b1edbc	1124	dspi_slave_handle_t *handle,
AnnaBridge	171:3a7713b1edbc	1125	dspi_slave_transfer_callback_t callback,
AnnaBridge	171:3a7713b1edbc	1126	void *userData);
AnnaBridge	171:3a7713b1edbc	1127
AnnaBridge	171:3a7713b1edbc	1128	/*!
AnnaBridge	171:3a7713b1edbc	1129	* @brief DSPI slave transfers data using an interrupt.
AnnaBridge	171:3a7713b1edbc	1130	*
AnnaBridge	171:3a7713b1edbc	1131	* This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all
AnnaBridge	171:3a7713b1edbc	1132	* data
AnnaBridge	171:3a7713b1edbc	1133	* have been transferred, the callback function is called.
AnnaBridge	171:3a7713b1edbc	1134	*
AnnaBridge	171:3a7713b1edbc	1135	* @param base DSPI peripheral base address.
AnnaBridge	171:3a7713b1edbc	1136	* @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
AnnaBridge	171:3a7713b1edbc	1137	* @param transfer pointer to dspi_transfer_t structure.
AnnaBridge	171:3a7713b1edbc	1138	* @return status of status_t.
AnnaBridge	171:3a7713b1edbc	1139	*/
AnnaBridge	171:3a7713b1edbc	1140	status_t DSPI_SlaveTransferNonBlocking(SPI_Type base, dspi_slave_handle_t handle, dspi_transfer_t *transfer);
AnnaBridge	171:3a7713b1edbc	1141
AnnaBridge	171:3a7713b1edbc	1142	/*!
AnnaBridge	171:3a7713b1edbc	1143	* @brief Gets the slave transfer count.
AnnaBridge	171:3a7713b1edbc	1144	*
AnnaBridge	171:3a7713b1edbc	1145	* This function gets the slave transfer count.
AnnaBridge	171:3a7713b1edbc	1146	*
AnnaBridge	171:3a7713b1edbc	1147	* @param base DSPI peripheral base address.
AnnaBridge	171:3a7713b1edbc	1148	* @param handle pointer to dspi_master_handle_t structure which stores the transfer state.
AnnaBridge	171:3a7713b1edbc	1149	* @param count Number of bytes transferred so far by the non-blocking transaction.
AnnaBridge	171:3a7713b1edbc	1150	* @return status of status_t.
AnnaBridge	171:3a7713b1edbc	1151	*/
AnnaBridge	171:3a7713b1edbc	1152	status_t DSPI_SlaveTransferGetCount(SPI_Type base, dspi_slave_handle_t handle, size_t *count);
AnnaBridge	171:3a7713b1edbc	1153
AnnaBridge	171:3a7713b1edbc	1154	/*!
AnnaBridge	171:3a7713b1edbc	1155	* @brief DSPI slave aborts a transfer using an interrupt.
AnnaBridge	171:3a7713b1edbc	1156	*
AnnaBridge	171:3a7713b1edbc	1157	* This function aborts transfer using an interrupt.
AnnaBridge	171:3a7713b1edbc	1158	*
AnnaBridge	171:3a7713b1edbc	1159	* @param base DSPI peripheral base address.
AnnaBridge	171:3a7713b1edbc	1160	* @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
AnnaBridge	171:3a7713b1edbc	1161	*/
AnnaBridge	171:3a7713b1edbc	1162	void DSPI_SlaveTransferAbort(SPI_Type base, dspi_slave_handle_t handle);
AnnaBridge	171:3a7713b1edbc	1163
AnnaBridge	171:3a7713b1edbc	1164	/*!
AnnaBridge	171:3a7713b1edbc	1165	* @brief DSPI Master IRQ handler function.
AnnaBridge	171:3a7713b1edbc	1166	*
AnnaBridge	171:3a7713b1edbc	1167	* This function processes the DSPI transmit and receive IRQ.
AnnaBridge	171:3a7713b1edbc	1168	*
AnnaBridge	171:3a7713b1edbc	1169	* @param base DSPI peripheral base address.
AnnaBridge	171:3a7713b1edbc	1170	* @param handle pointer to dspi_slave_handle_t structure which stores the transfer state.
AnnaBridge	171:3a7713b1edbc	1171	*/
AnnaBridge	171:3a7713b1edbc	1172	void DSPI_SlaveTransferHandleIRQ(SPI_Type base, dspi_slave_handle_t handle);
AnnaBridge	171:3a7713b1edbc	1173
AnnaBridge	171:3a7713b1edbc	1174	/*!
AnnaBridge	171:3a7713b1edbc	1175	*@}
AnnaBridge	171:3a7713b1edbc	1176	*/
AnnaBridge	171:3a7713b1edbc	1177
AnnaBridge	171:3a7713b1edbc	1178	#if defined(__cplusplus)
AnnaBridge	171:3a7713b1edbc	1179	}
AnnaBridge	171:3a7713b1edbc	1180	#endif /_cplusplus/
AnnaBridge	171:3a7713b1edbc	1181	/*!
AnnaBridge	171:3a7713b1edbc	1182	*@}
AnnaBridge	171:3a7713b1edbc	1183	*/
AnnaBridge	171:3a7713b1edbc	1184
AnnaBridge	171:3a7713b1edbc	1185	#endif /_FSL_DSPI_H_/