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TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/*
AnnaBridge	171:3a7713b1edbc	2	** ###################################################################
AnnaBridge	171:3a7713b1edbc	3	** Compilers: ARM Compiler
AnnaBridge	171:3a7713b1edbc	4	** Freescale C/C++ for Embedded ARM
AnnaBridge	171:3a7713b1edbc	5	** GNU C Compiler
AnnaBridge	171:3a7713b1edbc	6	** IAR ANSI C/C++ Compiler for ARM
AnnaBridge	171:3a7713b1edbc	7	**
AnnaBridge	171:3a7713b1edbc	8	** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
AnnaBridge	171:3a7713b1edbc	9	** K20P32M50SF0RM Rev. 1, Oct 2011
AnnaBridge	171:3a7713b1edbc	10	** K20P48M50SF0RM Rev. 1, Oct 2011
AnnaBridge	171:3a7713b1edbc	11	**
AnnaBridge	171:3a7713b1edbc	12	** Version: rev. 2.0, 2012-03-19
AnnaBridge	171:3a7713b1edbc	13	**
AnnaBridge	171:3a7713b1edbc	14	** Abstract:
AnnaBridge	171:3a7713b1edbc	15	** CMSIS Peripheral Access Layer for MK20D5
AnnaBridge	171:3a7713b1edbc	16	**
AnnaBridge	171:3a7713b1edbc	17	** Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved.
AnnaBridge	171:3a7713b1edbc	18	**
AnnaBridge	171:3a7713b1edbc	19	** http: www.freescale.com
AnnaBridge	171:3a7713b1edbc	20	** mail: support@freescale.com
AnnaBridge	171:3a7713b1edbc	21	**
AnnaBridge	171:3a7713b1edbc	22	** Revisions:
AnnaBridge	171:3a7713b1edbc	23	** - rev. 1.0 (2011-12-15)
AnnaBridge	171:3a7713b1edbc	24	** Initial version
AnnaBridge	171:3a7713b1edbc	25	** - rev. 2.0 (2012-03-19)
AnnaBridge	171:3a7713b1edbc	26	** PDB Peripheral register structure updated.
AnnaBridge	171:3a7713b1edbc	27	** DMA Registers and bits for unsupported DMA channels removed.
AnnaBridge	171:3a7713b1edbc	28	**
AnnaBridge	171:3a7713b1edbc	29	** ###################################################################
AnnaBridge	171:3a7713b1edbc	30	*/
AnnaBridge	171:3a7713b1edbc	31
AnnaBridge	171:3a7713b1edbc	32	/**
AnnaBridge	171:3a7713b1edbc	33	* @file MK20D5.h
AnnaBridge	171:3a7713b1edbc	34	* @version 2.0
AnnaBridge	171:3a7713b1edbc	35	* @date 2012-03-19
AnnaBridge	171:3a7713b1edbc	36	* @brief CMSIS Peripheral Access Layer for MK20D5
AnnaBridge	171:3a7713b1edbc	37	*
AnnaBridge	171:3a7713b1edbc	38	* CMSIS Peripheral Access Layer for MK20D5
AnnaBridge	171:3a7713b1edbc	39	*/
AnnaBridge	171:3a7713b1edbc	40
AnnaBridge	171:3a7713b1edbc	41	#if !defined(MK20D5_H_)
AnnaBridge	171:3a7713b1edbc	42	#define MK20D5_H_ /*< Symbol preventing repeated inclusion /
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/** Memory map major version (memory maps with equal major version number are
AnnaBridge	171:3a7713b1edbc	45	* compatible) */
AnnaBridge	171:3a7713b1edbc	46	#define MCU_MEM_MAP_VERSION 0x0200u
AnnaBridge	171:3a7713b1edbc	47	/** Memory map minor version */
AnnaBridge	171:3a7713b1edbc	48	#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
AnnaBridge	171:3a7713b1edbc	49
AnnaBridge	171:3a7713b1edbc	50	/**
AnnaBridge	171:3a7713b1edbc	51	* @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge	171:3a7713b1edbc	52	* 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
AnnaBridge	171:3a7713b1edbc	53	* @param Reg Register to access.
AnnaBridge	171:3a7713b1edbc	54	* @param Bit Bit number to access.
AnnaBridge	171:3a7713b1edbc	55	* @return Value of the targeted bit in the bit band region.
AnnaBridge	171:3a7713b1edbc	56	*/
AnnaBridge	171:3a7713b1edbc	57	#define BITBAND_REG(Reg,Bit) (((uint32_t volatile)(0x42000000u + (32u((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u((uint32_t)(Bit))))))
AnnaBridge	171:3a7713b1edbc	58
AnnaBridge	171:3a7713b1edbc	59	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	60	-- Interrupt vector numbers
AnnaBridge	171:3a7713b1edbc	61	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	62
AnnaBridge	171:3a7713b1edbc	63	/**
AnnaBridge	171:3a7713b1edbc	64	* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
AnnaBridge	171:3a7713b1edbc	65	* @{
AnnaBridge	171:3a7713b1edbc	66	*/
AnnaBridge	171:3a7713b1edbc	67
AnnaBridge	171:3a7713b1edbc	68	/** Interrupt Number Definitions */
AnnaBridge	171:3a7713b1edbc	69	typedef enum IRQn {
AnnaBridge	171:3a7713b1edbc	70	/* Core interrupts */
AnnaBridge	171:3a7713b1edbc	71	NonMaskableInt_IRQn = -14, /*< Non Maskable Interrupt /
AnnaBridge	171:3a7713b1edbc	72	MemoryManagement_IRQn = -12, /*< Cortex-M4 Memory Management Interrupt /
AnnaBridge	171:3a7713b1edbc	73	BusFault_IRQn = -11, /*< Cortex-M4 Bus Fault Interrupt /
AnnaBridge	171:3a7713b1edbc	74	UsageFault_IRQn = -10, /*< Cortex-M4 Usage Fault Interrupt /
AnnaBridge	171:3a7713b1edbc	75	SVCall_IRQn = -5, /*< Cortex-M4 SV Call Interrupt /
AnnaBridge	171:3a7713b1edbc	76	DebugMonitor_IRQn = -4, /*< Cortex-M4 Debug Monitor Interrupt /
AnnaBridge	171:3a7713b1edbc	77	PendSV_IRQn = -2, /*< Cortex-M4 Pend SV Interrupt /
AnnaBridge	171:3a7713b1edbc	78	SysTick_IRQn = -1, /*< Cortex-M4 System Tick Interrupt /
AnnaBridge	171:3a7713b1edbc	79
AnnaBridge	171:3a7713b1edbc	80	/* Device specific interrupts */
AnnaBridge	171:3a7713b1edbc	81	DMA0_IRQn = 0, /*< DMA channel 0 transfer complete interrupt /
AnnaBridge	171:3a7713b1edbc	82	DMA1_IRQn = 1, /*< DMA channel 1 transfer complete interrupt /
AnnaBridge	171:3a7713b1edbc	83	DMA2_IRQn = 2, /*< DMA channel 2 transfer complete interrupt /
AnnaBridge	171:3a7713b1edbc	84	DMA3_IRQn = 3, /*< DMA channel 3 transfer complete interrupt /
AnnaBridge	171:3a7713b1edbc	85	DMA_Error_IRQn = 4, /*< DMA error interrupt /
AnnaBridge	171:3a7713b1edbc	86	Reserved21_IRQn = 5, /*< Reserved interrupt 21 /
AnnaBridge	171:3a7713b1edbc	87	FTFL_IRQn = 6, /*< FTFL interrupt /
AnnaBridge	171:3a7713b1edbc	88	Read_Collision_IRQn = 7, /*< Read collision interrupt /
AnnaBridge	171:3a7713b1edbc	89	LVD_LVW_IRQn = 8, /*< Low Voltage Detect, Low Voltage Warning /
AnnaBridge	171:3a7713b1edbc	90	LLW_IRQn = 9, /*< Low Leakage Wakeup /
AnnaBridge	171:3a7713b1edbc	91	Watchdog_IRQn = 10, /*< WDOG interrupt /
AnnaBridge	171:3a7713b1edbc	92	I2C0_IRQn = 11, /*< I2C0 interrupt /
AnnaBridge	171:3a7713b1edbc	93	SPI0_IRQn = 12, /*< SPI0 interrupt /
AnnaBridge	171:3a7713b1edbc	94	I2S0_Tx_IRQn = 13, /*< I2S0 transmit interrupt /
AnnaBridge	171:3a7713b1edbc	95	I2S0_Rx_IRQn = 14, /*< I2S0 receive interrupt /
AnnaBridge	171:3a7713b1edbc	96	UART0_LON_IRQn = 15, /*< UART0 LON interrupt /
AnnaBridge	171:3a7713b1edbc	97	UART0_RX_TX_IRQn = 16, /*< UART0 receive/transmit interrupt /
AnnaBridge	171:3a7713b1edbc	98	UART0_ERR_IRQn = 17, /*< UART0 error interrupt /
AnnaBridge	171:3a7713b1edbc	99	UART1_RX_TX_IRQn = 18, /*< UART1 receive/transmit interrupt /
AnnaBridge	171:3a7713b1edbc	100	UART1_ERR_IRQn = 19, /*< UART1 error interrupt /
AnnaBridge	171:3a7713b1edbc	101	UART2_RX_TX_IRQn = 20, /*< UART2 receive/transmit interrupt /
AnnaBridge	171:3a7713b1edbc	102	UART2_ERR_IRQn = 21, /*< UART2 error interrupt /
AnnaBridge	171:3a7713b1edbc	103	ADC0_IRQn = 22, /*< ADC0 interrupt /
AnnaBridge	171:3a7713b1edbc	104	CMP0_IRQn = 23, /*< CMP0 interrupt /
AnnaBridge	171:3a7713b1edbc	105	CMP1_IRQn = 24, /*< CMP1 interrupt /
AnnaBridge	171:3a7713b1edbc	106	FTM0_IRQn = 25, /*< FTM0 fault, overflow and channels interrupt /
AnnaBridge	171:3a7713b1edbc	107	FTM1_IRQn = 26, /*< FTM1 fault, overflow and channels interrupt /
AnnaBridge	171:3a7713b1edbc	108	CMT_IRQn = 27, /*< CMT interrupt /
AnnaBridge	171:3a7713b1edbc	109	RTC_IRQn = 28, /*< RTC interrupt /
AnnaBridge	171:3a7713b1edbc	110	RTC_Seconds_IRQn = 29, /*< RTC seconds interrupt /
AnnaBridge	171:3a7713b1edbc	111	PIT0_IRQn = 30, /*< PIT timer channel 0 interrupt /
AnnaBridge	171:3a7713b1edbc	112	PIT1_IRQn = 31, /*< PIT timer channel 1 interrupt /
AnnaBridge	171:3a7713b1edbc	113	PIT2_IRQn = 32, /*< PIT timer channel 2 interrupt /
AnnaBridge	171:3a7713b1edbc	114	PIT3_IRQn = 33, /*< PIT timer channel 3 interrupt /
AnnaBridge	171:3a7713b1edbc	115	PDB0_IRQn = 34, /*< PDB0 interrupt /
AnnaBridge	171:3a7713b1edbc	116	USB0_IRQn = 35, /*< USB0 interrupt /
AnnaBridge	171:3a7713b1edbc	117	USBDCD_IRQn = 36, /*< USBDCD interrupt /
AnnaBridge	171:3a7713b1edbc	118	TSI0_IRQn = 37, /*< TSI0 interrupt /
AnnaBridge	171:3a7713b1edbc	119	MCG_IRQn = 38, /*< MCG interrupt /
AnnaBridge	171:3a7713b1edbc	120	LPTimer_IRQn = 39, /*< LPTimer interrupt /
AnnaBridge	171:3a7713b1edbc	121	PORTA_IRQn = 40, /*< Port A interrupt /
AnnaBridge	171:3a7713b1edbc	122	PORTB_IRQn = 41, /*< Port B interrupt /
AnnaBridge	171:3a7713b1edbc	123	PORTC_IRQn = 42, /*< Port C interrupt /
AnnaBridge	171:3a7713b1edbc	124	PORTD_IRQn = 43, /*< Port D interrupt /
AnnaBridge	171:3a7713b1edbc	125	PORTE_IRQn = 44, /*< Port E interrupt /
AnnaBridge	171:3a7713b1edbc	126	SWI_IRQn = 45 /*< Software interrupt /
AnnaBridge	171:3a7713b1edbc	127	} IRQn_Type;
AnnaBridge	171:3a7713b1edbc	128
AnnaBridge	171:3a7713b1edbc	129	/**
AnnaBridge	171:3a7713b1edbc	130	* @}
AnnaBridge	171:3a7713b1edbc	131	/ / end of group Interrupt_vector_numbers */
AnnaBridge	171:3a7713b1edbc	132
AnnaBridge	171:3a7713b1edbc	133
AnnaBridge	171:3a7713b1edbc	134	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	135	-- Cortex M4 Core Configuration
AnnaBridge	171:3a7713b1edbc	136	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	137
AnnaBridge	171:3a7713b1edbc	138	/**
AnnaBridge	171:3a7713b1edbc	139	* @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
AnnaBridge	171:3a7713b1edbc	140	* @{
AnnaBridge	171:3a7713b1edbc	141	*/
AnnaBridge	171:3a7713b1edbc	142
AnnaBridge	171:3a7713b1edbc	143	#define __MPU_PRESENT 0 /*< Defines if an MPU is present or not /
AnnaBridge	171:3a7713b1edbc	144	#define __NVIC_PRIO_BITS 4 /*< Number of priority bits implemented in the NVIC /
AnnaBridge	171:3a7713b1edbc	145	#define __Vendor_SysTickConfig 0 /*< Vendor specific implementation of SysTickConfig is defined /
AnnaBridge	171:3a7713b1edbc	146
AnnaBridge	171:3a7713b1edbc	147	#include "core_cm4.h" /* Core Peripheral Access Layer */
AnnaBridge	171:3a7713b1edbc	148	#include "system_MK20D5.h" /* Device specific configuration file */
AnnaBridge	171:3a7713b1edbc	149
AnnaBridge	171:3a7713b1edbc	150	/**
AnnaBridge	171:3a7713b1edbc	151	* @}
AnnaBridge	171:3a7713b1edbc	152	/ / end of group Cortex_Core_Configuration */
AnnaBridge	171:3a7713b1edbc	153
AnnaBridge	171:3a7713b1edbc	154
AnnaBridge	171:3a7713b1edbc	155	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	156	-- Device Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	157	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	158
AnnaBridge	171:3a7713b1edbc	159	/**
AnnaBridge	171:3a7713b1edbc	160	* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	161	* @{
AnnaBridge	171:3a7713b1edbc	162	*/
AnnaBridge	171:3a7713b1edbc	163
AnnaBridge	171:3a7713b1edbc	164
AnnaBridge	171:3a7713b1edbc	165	/*
AnnaBridge	171:3a7713b1edbc	166	** Start of section using anonymous unions
AnnaBridge	171:3a7713b1edbc	167	*/
AnnaBridge	171:3a7713b1edbc	168
AnnaBridge	171:3a7713b1edbc	169	#if defined(__ARMCC_VERSION)
AnnaBridge	171:3a7713b1edbc	170	#pragma push
AnnaBridge	171:3a7713b1edbc	171	#pragma anon_unions
AnnaBridge	171:3a7713b1edbc	172	#elif defined(__CWCC__)
AnnaBridge	171:3a7713b1edbc	173	#pragma push
AnnaBridge	171:3a7713b1edbc	174	#pragma cpp_extensions on
AnnaBridge	171:3a7713b1edbc	175	#elif defined(__GNUC__)
AnnaBridge	171:3a7713b1edbc	176	/* anonymous unions are enabled by default */
AnnaBridge	171:3a7713b1edbc	177	#elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge	171:3a7713b1edbc	178	#pragma language=extended
AnnaBridge	171:3a7713b1edbc	179	#else
AnnaBridge	171:3a7713b1edbc	180	#error Not supported compiler type
AnnaBridge	171:3a7713b1edbc	181	#endif
AnnaBridge	171:3a7713b1edbc	182
AnnaBridge	171:3a7713b1edbc	183	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	184	-- ADC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	185	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	186
AnnaBridge	171:3a7713b1edbc	187	/**
AnnaBridge	171:3a7713b1edbc	188	* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	189	* @{
AnnaBridge	171:3a7713b1edbc	190	*/
AnnaBridge	171:3a7713b1edbc	191
AnnaBridge	171:3a7713b1edbc	192	/** ADC - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	193	typedef struct {
AnnaBridge	171:3a7713b1edbc	194	__IO uint32_t SC1[2]; /*< ADC status and control registers 1, array offset: 0x0, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	195	__IO uint32_t CFG1; /*< ADC configuration register 1, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	196	__IO uint32_t CFG2; /*< Configuration register 2, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	197	__I uint32_t R[2]; /*< ADC data result register, array offset: 0x10, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	198	__IO uint32_t CV1; /*< Compare value registers, offset: 0x18 /
AnnaBridge	171:3a7713b1edbc	199	__IO uint32_t CV2; /*< Compare value registers, offset: 0x1C /
AnnaBridge	171:3a7713b1edbc	200	__IO uint32_t SC2; /*< Status and control register 2, offset: 0x20 /
AnnaBridge	171:3a7713b1edbc	201	__IO uint32_t SC3; /*< Status and control register 3, offset: 0x24 /
AnnaBridge	171:3a7713b1edbc	202	__IO uint32_t OFS; /*< ADC offset correction register, offset: 0x28 /
AnnaBridge	171:3a7713b1edbc	203	__IO uint32_t PG; /*< ADC plus-side gain register, offset: 0x2C /
AnnaBridge	171:3a7713b1edbc	204	__IO uint32_t MG; /*< ADC minus-side gain register, offset: 0x30 /
AnnaBridge	171:3a7713b1edbc	205	__IO uint32_t CLPD; /*< ADC plus-side general calibration value register, offset: 0x34 /
AnnaBridge	171:3a7713b1edbc	206	__IO uint32_t CLPS; /*< ADC plus-side general calibration value register, offset: 0x38 /
AnnaBridge	171:3a7713b1edbc	207	__IO uint32_t CLP4; /*< ADC plus-side general calibration value register, offset: 0x3C /
AnnaBridge	171:3a7713b1edbc	208	__IO uint32_t CLP3; /*< ADC plus-side general calibration value register, offset: 0x40 /
AnnaBridge	171:3a7713b1edbc	209	__IO uint32_t CLP2; /*< ADC plus-side general calibration value register, offset: 0x44 /
AnnaBridge	171:3a7713b1edbc	210	__IO uint32_t CLP1; /*< ADC plus-side general calibration value register, offset: 0x48 /
AnnaBridge	171:3a7713b1edbc	211	__IO uint32_t CLP0; /*< ADC plus-side general calibration value register, offset: 0x4C /
AnnaBridge	171:3a7713b1edbc	212	uint8_t RESERVED_0[4];
AnnaBridge	171:3a7713b1edbc	213	__IO uint32_t CLMD; /*< ADC minus-side general calibration value register, offset: 0x54 /
AnnaBridge	171:3a7713b1edbc	214	__IO uint32_t CLMS; /*< ADC minus-side general calibration value register, offset: 0x58 /
AnnaBridge	171:3a7713b1edbc	215	__IO uint32_t CLM4; /*< ADC minus-side general calibration value register, offset: 0x5C /
AnnaBridge	171:3a7713b1edbc	216	__IO uint32_t CLM3; /*< ADC minus-side general calibration value register, offset: 0x60 /
AnnaBridge	171:3a7713b1edbc	217	__IO uint32_t CLM2; /*< ADC minus-side general calibration value register, offset: 0x64 /
AnnaBridge	171:3a7713b1edbc	218	__IO uint32_t CLM1; /*< ADC minus-side general calibration value register, offset: 0x68 /
AnnaBridge	171:3a7713b1edbc	219	__IO uint32_t CLM0; /*< ADC minus-side general calibration value register, offset: 0x6C /
AnnaBridge	171:3a7713b1edbc	220	} ADC_Type;
AnnaBridge	171:3a7713b1edbc	221
AnnaBridge	171:3a7713b1edbc	222	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	223	-- ADC Register Masks
AnnaBridge	171:3a7713b1edbc	224	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	225
AnnaBridge	171:3a7713b1edbc	226	/**
AnnaBridge	171:3a7713b1edbc	227	* @addtogroup ADC_Register_Masks ADC Register Masks
AnnaBridge	171:3a7713b1edbc	228	* @{
AnnaBridge	171:3a7713b1edbc	229	*/
AnnaBridge	171:3a7713b1edbc	230
AnnaBridge	171:3a7713b1edbc	231	/* SC1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	232	#define ADC_SC1_ADCH_MASK 0x1Fu
AnnaBridge	171:3a7713b1edbc	233	#define ADC_SC1_ADCH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	234	#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
AnnaBridge	171:3a7713b1edbc	235	#define ADC_SC1_DIFF_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	236	#define ADC_SC1_DIFF_SHIFT 5
AnnaBridge	171:3a7713b1edbc	237	#define ADC_SC1_AIEN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	238	#define ADC_SC1_AIEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	239	#define ADC_SC1_COCO_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	240	#define ADC_SC1_COCO_SHIFT 7
AnnaBridge	171:3a7713b1edbc	241	/* CFG1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	242	#define ADC_CFG1_ADICLK_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	243	#define ADC_CFG1_ADICLK_SHIFT 0
AnnaBridge	171:3a7713b1edbc	244	#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
AnnaBridge	171:3a7713b1edbc	245	#define ADC_CFG1_MODE_MASK 0xCu
AnnaBridge	171:3a7713b1edbc	246	#define ADC_CFG1_MODE_SHIFT 2
AnnaBridge	171:3a7713b1edbc	247	#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
AnnaBridge	171:3a7713b1edbc	248	#define ADC_CFG1_ADLSMP_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	249	#define ADC_CFG1_ADLSMP_SHIFT 4
AnnaBridge	171:3a7713b1edbc	250	#define ADC_CFG1_ADIV_MASK 0x60u
AnnaBridge	171:3a7713b1edbc	251	#define ADC_CFG1_ADIV_SHIFT 5
AnnaBridge	171:3a7713b1edbc	252	#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
AnnaBridge	171:3a7713b1edbc	253	#define ADC_CFG1_ADLPC_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	254	#define ADC_CFG1_ADLPC_SHIFT 7
AnnaBridge	171:3a7713b1edbc	255	/* CFG2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	256	#define ADC_CFG2_ADLSTS_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	257	#define ADC_CFG2_ADLSTS_SHIFT 0
AnnaBridge	171:3a7713b1edbc	258	#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
AnnaBridge	171:3a7713b1edbc	259	#define ADC_CFG2_ADHSC_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	260	#define ADC_CFG2_ADHSC_SHIFT 2
AnnaBridge	171:3a7713b1edbc	261	#define ADC_CFG2_ADACKEN_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	262	#define ADC_CFG2_ADACKEN_SHIFT 3
AnnaBridge	171:3a7713b1edbc	263	#define ADC_CFG2_MUXSEL_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	264	#define ADC_CFG2_MUXSEL_SHIFT 4
AnnaBridge	171:3a7713b1edbc	265	/* R Bit Fields */
AnnaBridge	171:3a7713b1edbc	266	#define ADC_R_D_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	267	#define ADC_R_D_SHIFT 0
AnnaBridge	171:3a7713b1edbc	268	#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
AnnaBridge	171:3a7713b1edbc	269	/* CV1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	270	#define ADC_CV1_CV_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	271	#define ADC_CV1_CV_SHIFT 0
AnnaBridge	171:3a7713b1edbc	272	#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
AnnaBridge	171:3a7713b1edbc	273	/* CV2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	274	#define ADC_CV2_CV_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	275	#define ADC_CV2_CV_SHIFT 0
AnnaBridge	171:3a7713b1edbc	276	#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
AnnaBridge	171:3a7713b1edbc	277	/* SC2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	278	#define ADC_SC2_REFSEL_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	279	#define ADC_SC2_REFSEL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	280	#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
AnnaBridge	171:3a7713b1edbc	281	#define ADC_SC2_DMAEN_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	282	#define ADC_SC2_DMAEN_SHIFT 2
AnnaBridge	171:3a7713b1edbc	283	#define ADC_SC2_ACREN_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	284	#define ADC_SC2_ACREN_SHIFT 3
AnnaBridge	171:3a7713b1edbc	285	#define ADC_SC2_ACFGT_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	286	#define ADC_SC2_ACFGT_SHIFT 4
AnnaBridge	171:3a7713b1edbc	287	#define ADC_SC2_ACFE_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	288	#define ADC_SC2_ACFE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	289	#define ADC_SC2_ADTRG_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	290	#define ADC_SC2_ADTRG_SHIFT 6
AnnaBridge	171:3a7713b1edbc	291	#define ADC_SC2_ADACT_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	292	#define ADC_SC2_ADACT_SHIFT 7
AnnaBridge	171:3a7713b1edbc	293	/* SC3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	294	#define ADC_SC3_AVGS_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	295	#define ADC_SC3_AVGS_SHIFT 0
AnnaBridge	171:3a7713b1edbc	296	#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
AnnaBridge	171:3a7713b1edbc	297	#define ADC_SC3_AVGE_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	298	#define ADC_SC3_AVGE_SHIFT 2
AnnaBridge	171:3a7713b1edbc	299	#define ADC_SC3_ADCO_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	300	#define ADC_SC3_ADCO_SHIFT 3
AnnaBridge	171:3a7713b1edbc	301	#define ADC_SC3_CALF_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	302	#define ADC_SC3_CALF_SHIFT 6
AnnaBridge	171:3a7713b1edbc	303	#define ADC_SC3_CAL_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	304	#define ADC_SC3_CAL_SHIFT 7
AnnaBridge	171:3a7713b1edbc	305	/* OFS Bit Fields */
AnnaBridge	171:3a7713b1edbc	306	#define ADC_OFS_OFS_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	307	#define ADC_OFS_OFS_SHIFT 0
AnnaBridge	171:3a7713b1edbc	308	#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
AnnaBridge	171:3a7713b1edbc	309	/* PG Bit Fields */
AnnaBridge	171:3a7713b1edbc	310	#define ADC_PG_PG_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	311	#define ADC_PG_PG_SHIFT 0
AnnaBridge	171:3a7713b1edbc	312	#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
AnnaBridge	171:3a7713b1edbc	313	/* MG Bit Fields */
AnnaBridge	171:3a7713b1edbc	314	#define ADC_MG_MG_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	315	#define ADC_MG_MG_SHIFT 0
AnnaBridge	171:3a7713b1edbc	316	#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
AnnaBridge	171:3a7713b1edbc	317	/* CLPD Bit Fields */
AnnaBridge	171:3a7713b1edbc	318	#define ADC_CLPD_CLPD_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	319	#define ADC_CLPD_CLPD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	320	#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
AnnaBridge	171:3a7713b1edbc	321	/* CLPS Bit Fields */
AnnaBridge	171:3a7713b1edbc	322	#define ADC_CLPS_CLPS_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	323	#define ADC_CLPS_CLPS_SHIFT 0
AnnaBridge	171:3a7713b1edbc	324	#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
AnnaBridge	171:3a7713b1edbc	325	/* CLP4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	326	#define ADC_CLP4_CLP4_MASK 0x3FFu
AnnaBridge	171:3a7713b1edbc	327	#define ADC_CLP4_CLP4_SHIFT 0
AnnaBridge	171:3a7713b1edbc	328	#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
AnnaBridge	171:3a7713b1edbc	329	/* CLP3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	330	#define ADC_CLP3_CLP3_MASK 0x1FFu
AnnaBridge	171:3a7713b1edbc	331	#define ADC_CLP3_CLP3_SHIFT 0
AnnaBridge	171:3a7713b1edbc	332	#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
AnnaBridge	171:3a7713b1edbc	333	/* CLP2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	334	#define ADC_CLP2_CLP2_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	335	#define ADC_CLP2_CLP2_SHIFT 0
AnnaBridge	171:3a7713b1edbc	336	#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
AnnaBridge	171:3a7713b1edbc	337	/* CLP1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	338	#define ADC_CLP1_CLP1_MASK 0x7Fu
AnnaBridge	171:3a7713b1edbc	339	#define ADC_CLP1_CLP1_SHIFT 0
AnnaBridge	171:3a7713b1edbc	340	#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
AnnaBridge	171:3a7713b1edbc	341	/* CLP0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	342	#define ADC_CLP0_CLP0_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	343	#define ADC_CLP0_CLP0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	344	#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
AnnaBridge	171:3a7713b1edbc	345	/* CLMD Bit Fields */
AnnaBridge	171:3a7713b1edbc	346	#define ADC_CLMD_CLMD_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	347	#define ADC_CLMD_CLMD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	348	#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
AnnaBridge	171:3a7713b1edbc	349	/* CLMS Bit Fields */
AnnaBridge	171:3a7713b1edbc	350	#define ADC_CLMS_CLMS_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	351	#define ADC_CLMS_CLMS_SHIFT 0
AnnaBridge	171:3a7713b1edbc	352	#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
AnnaBridge	171:3a7713b1edbc	353	/* CLM4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	354	#define ADC_CLM4_CLM4_MASK 0x3FFu
AnnaBridge	171:3a7713b1edbc	355	#define ADC_CLM4_CLM4_SHIFT 0
AnnaBridge	171:3a7713b1edbc	356	#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
AnnaBridge	171:3a7713b1edbc	357	/* CLM3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	358	#define ADC_CLM3_CLM3_MASK 0x1FFu
AnnaBridge	171:3a7713b1edbc	359	#define ADC_CLM3_CLM3_SHIFT 0
AnnaBridge	171:3a7713b1edbc	360	#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
AnnaBridge	171:3a7713b1edbc	361	/* CLM2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	362	#define ADC_CLM2_CLM2_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	363	#define ADC_CLM2_CLM2_SHIFT 0
AnnaBridge	171:3a7713b1edbc	364	#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
AnnaBridge	171:3a7713b1edbc	365	/* CLM1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	366	#define ADC_CLM1_CLM1_MASK 0x7Fu
AnnaBridge	171:3a7713b1edbc	367	#define ADC_CLM1_CLM1_SHIFT 0
AnnaBridge	171:3a7713b1edbc	368	#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
AnnaBridge	171:3a7713b1edbc	369	/* CLM0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	370	#define ADC_CLM0_CLM0_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	371	#define ADC_CLM0_CLM0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	372	#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
AnnaBridge	171:3a7713b1edbc	373
AnnaBridge	171:3a7713b1edbc	374	/**
AnnaBridge	171:3a7713b1edbc	375	* @}
AnnaBridge	171:3a7713b1edbc	376	/ / end of group ADC_Register_Masks */
AnnaBridge	171:3a7713b1edbc	377
AnnaBridge	171:3a7713b1edbc	378
AnnaBridge	171:3a7713b1edbc	379	/* ADC - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	380	/** Peripheral ADC0 base address */
AnnaBridge	171:3a7713b1edbc	381	#define ADC0_BASE (0x4003B000u)
AnnaBridge	171:3a7713b1edbc	382	/** Peripheral ADC0 base pointer */
AnnaBridge	171:3a7713b1edbc	383	#define ADC0 ((ADC_Type *)ADC0_BASE)
AnnaBridge	171:3a7713b1edbc	384
AnnaBridge	171:3a7713b1edbc	385	/**
AnnaBridge	171:3a7713b1edbc	386	* @}
AnnaBridge	171:3a7713b1edbc	387	/ / end of group ADC_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	388
AnnaBridge	171:3a7713b1edbc	389
AnnaBridge	171:3a7713b1edbc	390	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	391	-- CMP Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	392	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	393
AnnaBridge	171:3a7713b1edbc	394	/**
AnnaBridge	171:3a7713b1edbc	395	* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	396	* @{
AnnaBridge	171:3a7713b1edbc	397	*/
AnnaBridge	171:3a7713b1edbc	398
AnnaBridge	171:3a7713b1edbc	399	/** CMP - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	400	typedef struct {
AnnaBridge	171:3a7713b1edbc	401	__IO uint8_t CR0; /*< CMP Control Register 0, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	402	__IO uint8_t CR1; /*< CMP Control Register 1, offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	403	__IO uint8_t FPR; /*< CMP Filter Period Register, offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	404	__IO uint8_t SCR; /*< CMP Status and Control Register, offset: 0x3 /
AnnaBridge	171:3a7713b1edbc	405	__IO uint8_t DACCR; /*< DAC Control Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	406	__IO uint8_t MUXCR; /*< MUX Control Register, offset: 0x5 /
AnnaBridge	171:3a7713b1edbc	407	} CMP_Type;
AnnaBridge	171:3a7713b1edbc	408
AnnaBridge	171:3a7713b1edbc	409	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	410	-- CMP Register Masks
AnnaBridge	171:3a7713b1edbc	411	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	412
AnnaBridge	171:3a7713b1edbc	413	/**
AnnaBridge	171:3a7713b1edbc	414	* @addtogroup CMP_Register_Masks CMP Register Masks
AnnaBridge	171:3a7713b1edbc	415	* @{
AnnaBridge	171:3a7713b1edbc	416	*/
AnnaBridge	171:3a7713b1edbc	417
AnnaBridge	171:3a7713b1edbc	418	/* CR0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	419	#define CMP_CR0_HYSTCTR_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	420	#define CMP_CR0_HYSTCTR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	421	#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
AnnaBridge	171:3a7713b1edbc	422	#define CMP_CR0_FILTER_CNT_MASK 0x70u
AnnaBridge	171:3a7713b1edbc	423	#define CMP_CR0_FILTER_CNT_SHIFT 4
AnnaBridge	171:3a7713b1edbc	424	#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
AnnaBridge	171:3a7713b1edbc	425	/* CR1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	426	#define CMP_CR1_EN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	427	#define CMP_CR1_EN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	428	#define CMP_CR1_OPE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	429	#define CMP_CR1_OPE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	430	#define CMP_CR1_COS_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	431	#define CMP_CR1_COS_SHIFT 2
AnnaBridge	171:3a7713b1edbc	432	#define CMP_CR1_INV_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	433	#define CMP_CR1_INV_SHIFT 3
AnnaBridge	171:3a7713b1edbc	434	#define CMP_CR1_PMODE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	435	#define CMP_CR1_PMODE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	436	#define CMP_CR1_WE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	437	#define CMP_CR1_WE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	438	#define CMP_CR1_SE_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	439	#define CMP_CR1_SE_SHIFT 7
AnnaBridge	171:3a7713b1edbc	440	/* FPR Bit Fields */
AnnaBridge	171:3a7713b1edbc	441	#define CMP_FPR_FILT_PER_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	442	#define CMP_FPR_FILT_PER_SHIFT 0
AnnaBridge	171:3a7713b1edbc	443	#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
AnnaBridge	171:3a7713b1edbc	444	/* SCR Bit Fields */
AnnaBridge	171:3a7713b1edbc	445	#define CMP_SCR_COUT_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	446	#define CMP_SCR_COUT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	447	#define CMP_SCR_CFF_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	448	#define CMP_SCR_CFF_SHIFT 1
AnnaBridge	171:3a7713b1edbc	449	#define CMP_SCR_CFR_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	450	#define CMP_SCR_CFR_SHIFT 2
AnnaBridge	171:3a7713b1edbc	451	#define CMP_SCR_IEF_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	452	#define CMP_SCR_IEF_SHIFT 3
AnnaBridge	171:3a7713b1edbc	453	#define CMP_SCR_IER_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	454	#define CMP_SCR_IER_SHIFT 4
AnnaBridge	171:3a7713b1edbc	455	#define CMP_SCR_DMAEN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	456	#define CMP_SCR_DMAEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	457	/* DACCR Bit Fields */
AnnaBridge	171:3a7713b1edbc	458	#define CMP_DACCR_VOSEL_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	459	#define CMP_DACCR_VOSEL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	460	#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
AnnaBridge	171:3a7713b1edbc	461	#define CMP_DACCR_VRSEL_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	462	#define CMP_DACCR_VRSEL_SHIFT 6
AnnaBridge	171:3a7713b1edbc	463	#define CMP_DACCR_DACEN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	464	#define CMP_DACCR_DACEN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	465	/* MUXCR Bit Fields */
AnnaBridge	171:3a7713b1edbc	466	#define CMP_MUXCR_MSEL_MASK 0x7u
AnnaBridge	171:3a7713b1edbc	467	#define CMP_MUXCR_MSEL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	468	#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
AnnaBridge	171:3a7713b1edbc	469	#define CMP_MUXCR_PSEL_MASK 0x38u
AnnaBridge	171:3a7713b1edbc	470	#define CMP_MUXCR_PSEL_SHIFT 3
AnnaBridge	171:3a7713b1edbc	471	#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
AnnaBridge	171:3a7713b1edbc	472
AnnaBridge	171:3a7713b1edbc	473	/**
AnnaBridge	171:3a7713b1edbc	474	* @}
AnnaBridge	171:3a7713b1edbc	475	/ / end of group CMP_Register_Masks */
AnnaBridge	171:3a7713b1edbc	476
AnnaBridge	171:3a7713b1edbc	477
AnnaBridge	171:3a7713b1edbc	478	/* CMP - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	479	/** Peripheral CMP0 base address */
AnnaBridge	171:3a7713b1edbc	480	#define CMP0_BASE (0x40073000u)
AnnaBridge	171:3a7713b1edbc	481	/** Peripheral CMP0 base pointer */
AnnaBridge	171:3a7713b1edbc	482	#define CMP0 ((CMP_Type *)CMP0_BASE)
AnnaBridge	171:3a7713b1edbc	483	/** Peripheral CMP1 base address */
AnnaBridge	171:3a7713b1edbc	484	#define CMP1_BASE (0x40073008u)
AnnaBridge	171:3a7713b1edbc	485	/** Peripheral CMP1 base pointer */
AnnaBridge	171:3a7713b1edbc	486	#define CMP1 ((CMP_Type *)CMP1_BASE)
AnnaBridge	171:3a7713b1edbc	487
AnnaBridge	171:3a7713b1edbc	488	/**
AnnaBridge	171:3a7713b1edbc	489	* @}
AnnaBridge	171:3a7713b1edbc	490	/ / end of group CMP_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	491
AnnaBridge	171:3a7713b1edbc	492
AnnaBridge	171:3a7713b1edbc	493	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	494	-- CMT Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	495	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	496
AnnaBridge	171:3a7713b1edbc	497	/**
AnnaBridge	171:3a7713b1edbc	498	* @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	499	* @{
AnnaBridge	171:3a7713b1edbc	500	*/
AnnaBridge	171:3a7713b1edbc	501
AnnaBridge	171:3a7713b1edbc	502	/** CMT - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	503	typedef struct {
AnnaBridge	171:3a7713b1edbc	504	__IO uint8_t CGH1; /*< CMT Carrier Generator High Data Register 1, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	505	__IO uint8_t CGL1; /*< CMT Carrier Generator Low Data Register 1, offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	506	__IO uint8_t CGH2; /*< CMT Carrier Generator High Data Register 2, offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	507	__IO uint8_t CGL2; /*< CMT Carrier Generator Low Data Register 2, offset: 0x3 /
AnnaBridge	171:3a7713b1edbc	508	__IO uint8_t OC; /*< CMT Output Control Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	509	__IO uint8_t MSC; /*< CMT Modulator Status and Control Register, offset: 0x5 /
AnnaBridge	171:3a7713b1edbc	510	__IO uint8_t CMD1; /*< CMT Modulator Data Register Mark High, offset: 0x6 /
AnnaBridge	171:3a7713b1edbc	511	__IO uint8_t CMD2; /*< CMT Modulator Data Register Mark Low, offset: 0x7 /
AnnaBridge	171:3a7713b1edbc	512	__IO uint8_t CMD3; /*< CMT Modulator Data Register Space High, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	513	__IO uint8_t CMD4; /*< CMT Modulator Data Register Space Low, offset: 0x9 /
AnnaBridge	171:3a7713b1edbc	514	__IO uint8_t PPS; /*< CMT Primary Prescaler Register, offset: 0xA /
AnnaBridge	171:3a7713b1edbc	515	__IO uint8_t DMA; /*< CMT Direct Memory Access, offset: 0xB /
AnnaBridge	171:3a7713b1edbc	516	} CMT_Type;
AnnaBridge	171:3a7713b1edbc	517
AnnaBridge	171:3a7713b1edbc	518	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	519	-- CMT Register Masks
AnnaBridge	171:3a7713b1edbc	520	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	521
AnnaBridge	171:3a7713b1edbc	522	/**
AnnaBridge	171:3a7713b1edbc	523	* @addtogroup CMT_Register_Masks CMT Register Masks
AnnaBridge	171:3a7713b1edbc	524	* @{
AnnaBridge	171:3a7713b1edbc	525	*/
AnnaBridge	171:3a7713b1edbc	526
AnnaBridge	171:3a7713b1edbc	527	/* CGH1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	528	#define CMT_CGH1_PH_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	529	#define CMT_CGH1_PH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	530	#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
AnnaBridge	171:3a7713b1edbc	531	/* CGL1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	532	#define CMT_CGL1_PL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	533	#define CMT_CGL1_PL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	534	#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
AnnaBridge	171:3a7713b1edbc	535	/* CGH2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	536	#define CMT_CGH2_SH_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	537	#define CMT_CGH2_SH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	538	#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
AnnaBridge	171:3a7713b1edbc	539	/* CGL2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	540	#define CMT_CGL2_SL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	541	#define CMT_CGL2_SL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	542	#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
AnnaBridge	171:3a7713b1edbc	543	/* OC Bit Fields */
AnnaBridge	171:3a7713b1edbc	544	#define CMT_OC_IROPEN_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	545	#define CMT_OC_IROPEN_SHIFT 5
AnnaBridge	171:3a7713b1edbc	546	#define CMT_OC_CMTPOL_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	547	#define CMT_OC_CMTPOL_SHIFT 6
AnnaBridge	171:3a7713b1edbc	548	#define CMT_OC_IROL_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	549	#define CMT_OC_IROL_SHIFT 7
AnnaBridge	171:3a7713b1edbc	550	/* MSC Bit Fields */
AnnaBridge	171:3a7713b1edbc	551	#define CMT_MSC_MCGEN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	552	#define CMT_MSC_MCGEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	553	#define CMT_MSC_EOCIE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	554	#define CMT_MSC_EOCIE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	555	#define CMT_MSC_FSK_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	556	#define CMT_MSC_FSK_SHIFT 2
AnnaBridge	171:3a7713b1edbc	557	#define CMT_MSC_BASE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	558	#define CMT_MSC_BASE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	559	#define CMT_MSC_EXSPC_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	560	#define CMT_MSC_EXSPC_SHIFT 4
AnnaBridge	171:3a7713b1edbc	561	#define CMT_MSC_CMTDIV_MASK 0x60u
AnnaBridge	171:3a7713b1edbc	562	#define CMT_MSC_CMTDIV_SHIFT 5
AnnaBridge	171:3a7713b1edbc	563	#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
AnnaBridge	171:3a7713b1edbc	564	#define CMT_MSC_EOCF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	565	#define CMT_MSC_EOCF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	566	/* CMD1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	567	#define CMT_CMD1_MB_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	568	#define CMT_CMD1_MB_SHIFT 0
AnnaBridge	171:3a7713b1edbc	569	#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
AnnaBridge	171:3a7713b1edbc	570	/* CMD2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	571	#define CMT_CMD2_MB_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	572	#define CMT_CMD2_MB_SHIFT 0
AnnaBridge	171:3a7713b1edbc	573	#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
AnnaBridge	171:3a7713b1edbc	574	/* CMD3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	575	#define CMT_CMD3_SB_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	576	#define CMT_CMD3_SB_SHIFT 0
AnnaBridge	171:3a7713b1edbc	577	#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
AnnaBridge	171:3a7713b1edbc	578	/* CMD4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	579	#define CMT_CMD4_SB_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	580	#define CMT_CMD4_SB_SHIFT 0
AnnaBridge	171:3a7713b1edbc	581	#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
AnnaBridge	171:3a7713b1edbc	582	/* PPS Bit Fields */
AnnaBridge	171:3a7713b1edbc	583	#define CMT_PPS_PPSDIV_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	584	#define CMT_PPS_PPSDIV_SHIFT 0
AnnaBridge	171:3a7713b1edbc	585	#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
AnnaBridge	171:3a7713b1edbc	586	/* DMA Bit Fields */
AnnaBridge	171:3a7713b1edbc	587	#define CMT_DMA_DMA_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	588	#define CMT_DMA_DMA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	589
AnnaBridge	171:3a7713b1edbc	590	/**
AnnaBridge	171:3a7713b1edbc	591	* @}
AnnaBridge	171:3a7713b1edbc	592	/ / end of group CMT_Register_Masks */
AnnaBridge	171:3a7713b1edbc	593
AnnaBridge	171:3a7713b1edbc	594
AnnaBridge	171:3a7713b1edbc	595	/* CMT - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	596	/** Peripheral CMT base address */
AnnaBridge	171:3a7713b1edbc	597	#define CMT_BASE (0x40062000u)
AnnaBridge	171:3a7713b1edbc	598	/** Peripheral CMT base pointer */
AnnaBridge	171:3a7713b1edbc	599	#define CMT ((CMT_Type *)CMT_BASE)
AnnaBridge	171:3a7713b1edbc	600
AnnaBridge	171:3a7713b1edbc	601	/**
AnnaBridge	171:3a7713b1edbc	602	* @}
AnnaBridge	171:3a7713b1edbc	603	/ / end of group CMT_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	604
AnnaBridge	171:3a7713b1edbc	605
AnnaBridge	171:3a7713b1edbc	606	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	607	-- CRC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	608	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	609
AnnaBridge	171:3a7713b1edbc	610	/**
AnnaBridge	171:3a7713b1edbc	611	* @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	612	* @{
AnnaBridge	171:3a7713b1edbc	613	*/
AnnaBridge	171:3a7713b1edbc	614
AnnaBridge	171:3a7713b1edbc	615	/** CRC - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	616	typedef struct {
AnnaBridge	171:3a7713b1edbc	617	union { /* offset: 0x0 */
AnnaBridge	171:3a7713b1edbc	618	struct { /* offset: 0x0 */
AnnaBridge	171:3a7713b1edbc	619	__IO uint16_t CRCL; /*< CRC_CRCL register., offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	620	__IO uint16_t CRCH; /*< CRC_CRCH register., offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	621	} ACCESS16BIT;
AnnaBridge	171:3a7713b1edbc	622	__IO uint32_t CRC; /*< CRC Data Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	623	struct { /* offset: 0x0 */
AnnaBridge	171:3a7713b1edbc	624	__IO uint8_t CRCLL; /*< CRC_CRCLL register., offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	625	__IO uint8_t CRCLU; /*< CRC_CRCLU register., offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	626	__IO uint8_t CRCHL; /*< CRC_CRCHL register., offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	627	__IO uint8_t CRCHU; /*< CRC_CRCHU register., offset: 0x3 /
AnnaBridge	171:3a7713b1edbc	628	} ACCESS8BIT;
AnnaBridge	171:3a7713b1edbc	629	};
AnnaBridge	171:3a7713b1edbc	630	union { /* offset: 0x4 */
AnnaBridge	171:3a7713b1edbc	631	struct { /* offset: 0x4 */
AnnaBridge	171:3a7713b1edbc	632	__IO uint16_t GPOLYL; /*< CRC_GPOLYL register., offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	633	__IO uint16_t GPOLYH; /*< CRC_GPOLYH register., offset: 0x6 /
AnnaBridge	171:3a7713b1edbc	634	} GPOLY_ACCESS16BIT;
AnnaBridge	171:3a7713b1edbc	635	__IO uint32_t GPOLY; /*< CRC Polynomial Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	636	struct { /* offset: 0x4 */
AnnaBridge	171:3a7713b1edbc	637	__IO uint8_t GPOLYLL; /*< CRC_GPOLYLL register., offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	638	__IO uint8_t GPOLYLU; /*< CRC_GPOLYLU register., offset: 0x5 /
AnnaBridge	171:3a7713b1edbc	639	__IO uint8_t GPOLYHL; /*< CRC_GPOLYHL register., offset: 0x6 /
AnnaBridge	171:3a7713b1edbc	640	__IO uint8_t GPOLYHU; /*< CRC_GPOLYHU register., offset: 0x7 /
AnnaBridge	171:3a7713b1edbc	641	} GPOLY_ACCESS8BIT;
AnnaBridge	171:3a7713b1edbc	642	};
AnnaBridge	171:3a7713b1edbc	643	union { /* offset: 0x8 */
AnnaBridge	171:3a7713b1edbc	644	__IO uint32_t CTRL; /*< CRC Control Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	645	struct { /* offset: 0x8 */
AnnaBridge	171:3a7713b1edbc	646	uint8_t RESERVED_0[3];
AnnaBridge	171:3a7713b1edbc	647	__IO uint8_t CTRLHU; /*< CRC_CTRLHU register., offset: 0xB /
AnnaBridge	171:3a7713b1edbc	648	} CTRL_ACCESS8BIT;
AnnaBridge	171:3a7713b1edbc	649	};
AnnaBridge	171:3a7713b1edbc	650	} CRC_Type;
AnnaBridge	171:3a7713b1edbc	651
AnnaBridge	171:3a7713b1edbc	652	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	653	-- CRC Register Masks
AnnaBridge	171:3a7713b1edbc	654	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	655
AnnaBridge	171:3a7713b1edbc	656	/**
AnnaBridge	171:3a7713b1edbc	657	* @addtogroup CRC_Register_Masks CRC Register Masks
AnnaBridge	171:3a7713b1edbc	658	* @{
AnnaBridge	171:3a7713b1edbc	659	*/
AnnaBridge	171:3a7713b1edbc	660
AnnaBridge	171:3a7713b1edbc	661	/* CRCL Bit Fields */
AnnaBridge	171:3a7713b1edbc	662	#define CRC_CRCL_CRCL_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	663	#define CRC_CRCL_CRCL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	664	#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
AnnaBridge	171:3a7713b1edbc	665	/* CRCH Bit Fields */
AnnaBridge	171:3a7713b1edbc	666	#define CRC_CRCH_CRCH_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	667	#define CRC_CRCH_CRCH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	668	#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
AnnaBridge	171:3a7713b1edbc	669	/* CRC Bit Fields */
AnnaBridge	171:3a7713b1edbc	670	#define CRC_CRC_LL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	671	#define CRC_CRC_LL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	672	#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
AnnaBridge	171:3a7713b1edbc	673	#define CRC_CRC_LU_MASK 0xFF00u
AnnaBridge	171:3a7713b1edbc	674	#define CRC_CRC_LU_SHIFT 8
AnnaBridge	171:3a7713b1edbc	675	#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
AnnaBridge	171:3a7713b1edbc	676	#define CRC_CRC_HL_MASK 0xFF0000u
AnnaBridge	171:3a7713b1edbc	677	#define CRC_CRC_HL_SHIFT 16
AnnaBridge	171:3a7713b1edbc	678	#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
AnnaBridge	171:3a7713b1edbc	679	#define CRC_CRC_HU_MASK 0xFF000000u
AnnaBridge	171:3a7713b1edbc	680	#define CRC_CRC_HU_SHIFT 24
AnnaBridge	171:3a7713b1edbc	681	#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
AnnaBridge	171:3a7713b1edbc	682	/* CRCLL Bit Fields */
AnnaBridge	171:3a7713b1edbc	683	#define CRC_CRCLL_CRCLL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	684	#define CRC_CRCLL_CRCLL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	685	#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
AnnaBridge	171:3a7713b1edbc	686	/* CRCLU Bit Fields */
AnnaBridge	171:3a7713b1edbc	687	#define CRC_CRCLU_CRCLU_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	688	#define CRC_CRCLU_CRCLU_SHIFT 0
AnnaBridge	171:3a7713b1edbc	689	#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
AnnaBridge	171:3a7713b1edbc	690	/* CRCHL Bit Fields */
AnnaBridge	171:3a7713b1edbc	691	#define CRC_CRCHL_CRCHL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	692	#define CRC_CRCHL_CRCHL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	693	#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
AnnaBridge	171:3a7713b1edbc	694	/* CRCHU Bit Fields */
AnnaBridge	171:3a7713b1edbc	695	#define CRC_CRCHU_CRCHU_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	696	#define CRC_CRCHU_CRCHU_SHIFT 0
AnnaBridge	171:3a7713b1edbc	697	#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
AnnaBridge	171:3a7713b1edbc	698	/* GPOLYL Bit Fields */
AnnaBridge	171:3a7713b1edbc	699	#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	700	#define CRC_GPOLYL_GPOLYL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	701	#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
AnnaBridge	171:3a7713b1edbc	702	/* GPOLYH Bit Fields */
AnnaBridge	171:3a7713b1edbc	703	#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	704	#define CRC_GPOLYH_GPOLYH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	705	#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
AnnaBridge	171:3a7713b1edbc	706	/* GPOLY Bit Fields */
AnnaBridge	171:3a7713b1edbc	707	#define CRC_GPOLY_LOW_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	708	#define CRC_GPOLY_LOW_SHIFT 0
AnnaBridge	171:3a7713b1edbc	709	#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
AnnaBridge	171:3a7713b1edbc	710	#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	711	#define CRC_GPOLY_HIGH_SHIFT 16
AnnaBridge	171:3a7713b1edbc	712	#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
AnnaBridge	171:3a7713b1edbc	713	/* GPOLYLL Bit Fields */
AnnaBridge	171:3a7713b1edbc	714	#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	715	#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	716	#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
AnnaBridge	171:3a7713b1edbc	717	/* GPOLYLU Bit Fields */
AnnaBridge	171:3a7713b1edbc	718	#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	719	#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
AnnaBridge	171:3a7713b1edbc	720	#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
AnnaBridge	171:3a7713b1edbc	721	/* GPOLYHL Bit Fields */
AnnaBridge	171:3a7713b1edbc	722	#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	723	#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	724	#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
AnnaBridge	171:3a7713b1edbc	725	/* GPOLYHU Bit Fields */
AnnaBridge	171:3a7713b1edbc	726	#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	727	#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
AnnaBridge	171:3a7713b1edbc	728	#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
AnnaBridge	171:3a7713b1edbc	729	/* CTRL Bit Fields */
AnnaBridge	171:3a7713b1edbc	730	#define CRC_CTRL_TCRC_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	731	#define CRC_CTRL_TCRC_SHIFT 24
AnnaBridge	171:3a7713b1edbc	732	#define CRC_CTRL_WAS_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	733	#define CRC_CTRL_WAS_SHIFT 25
AnnaBridge	171:3a7713b1edbc	734	#define CRC_CTRL_FXOR_MASK 0x4000000u
AnnaBridge	171:3a7713b1edbc	735	#define CRC_CTRL_FXOR_SHIFT 26
AnnaBridge	171:3a7713b1edbc	736	#define CRC_CTRL_TOTR_MASK 0x30000000u
AnnaBridge	171:3a7713b1edbc	737	#define CRC_CTRL_TOTR_SHIFT 28
AnnaBridge	171:3a7713b1edbc	738	#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
AnnaBridge	171:3a7713b1edbc	739	#define CRC_CTRL_TOT_MASK 0xC0000000u
AnnaBridge	171:3a7713b1edbc	740	#define CRC_CTRL_TOT_SHIFT 30
AnnaBridge	171:3a7713b1edbc	741	#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
AnnaBridge	171:3a7713b1edbc	742	/* CTRLHU Bit Fields */
AnnaBridge	171:3a7713b1edbc	743	#define CRC_CTRLHU_TCRC_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	744	#define CRC_CTRLHU_TCRC_SHIFT 0
AnnaBridge	171:3a7713b1edbc	745	#define CRC_CTRLHU_WAS_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	746	#define CRC_CTRLHU_WAS_SHIFT 1
AnnaBridge	171:3a7713b1edbc	747	#define CRC_CTRLHU_FXOR_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	748	#define CRC_CTRLHU_FXOR_SHIFT 2
AnnaBridge	171:3a7713b1edbc	749	#define CRC_CTRLHU_TOTR_MASK 0x30u
AnnaBridge	171:3a7713b1edbc	750	#define CRC_CTRLHU_TOTR_SHIFT 4
AnnaBridge	171:3a7713b1edbc	751	#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
AnnaBridge	171:3a7713b1edbc	752	#define CRC_CTRLHU_TOT_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	753	#define CRC_CTRLHU_TOT_SHIFT 6
AnnaBridge	171:3a7713b1edbc	754	#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
AnnaBridge	171:3a7713b1edbc	755
AnnaBridge	171:3a7713b1edbc	756	/**
AnnaBridge	171:3a7713b1edbc	757	* @}
AnnaBridge	171:3a7713b1edbc	758	/ / end of group CRC_Register_Masks */
AnnaBridge	171:3a7713b1edbc	759
AnnaBridge	171:3a7713b1edbc	760
AnnaBridge	171:3a7713b1edbc	761	/* CRC - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	762	/** Peripheral CRC base address */
AnnaBridge	171:3a7713b1edbc	763	#define CRC_BASE (0x40032000u)
AnnaBridge	171:3a7713b1edbc	764	/** Peripheral CRC base pointer */
AnnaBridge	171:3a7713b1edbc	765	#define CRC0 ((CRC_Type *)CRC_BASE)
AnnaBridge	171:3a7713b1edbc	766
AnnaBridge	171:3a7713b1edbc	767	/**
AnnaBridge	171:3a7713b1edbc	768	* @}
AnnaBridge	171:3a7713b1edbc	769	/ / end of group CRC_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	770
AnnaBridge	171:3a7713b1edbc	771
AnnaBridge	171:3a7713b1edbc	772	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	773	-- DMA Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	774	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	775
AnnaBridge	171:3a7713b1edbc	776	/**
AnnaBridge	171:3a7713b1edbc	777	* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	778	* @{
AnnaBridge	171:3a7713b1edbc	779	*/
AnnaBridge	171:3a7713b1edbc	780
AnnaBridge	171:3a7713b1edbc	781	/** DMA - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	782	typedef struct {
AnnaBridge	171:3a7713b1edbc	783	__IO uint32_t CR; /*< Control Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	784	__I uint32_t ES; /*< Error Status Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	785	uint8_t RESERVED_0[4];
AnnaBridge	171:3a7713b1edbc	786	__IO uint32_t ERQ; /*< Enable Request Register, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	787	uint8_t RESERVED_1[4];
AnnaBridge	171:3a7713b1edbc	788	__IO uint32_t EEI; /*< Enable Error Interrupt Register, offset: 0x14 /
AnnaBridge	171:3a7713b1edbc	789	__O uint8_t CEEI; /*< Clear Enable Error Interrupt Register, offset: 0x18 /
AnnaBridge	171:3a7713b1edbc	790	__O uint8_t SEEI; /*< Set Enable Error Interrupt Register, offset: 0x19 /
AnnaBridge	171:3a7713b1edbc	791	__O uint8_t CERQ; /*< Clear Enable Request Register, offset: 0x1A /
AnnaBridge	171:3a7713b1edbc	792	__O uint8_t SERQ; /*< Set Enable Request Register, offset: 0x1B /
AnnaBridge	171:3a7713b1edbc	793	__O uint8_t CDNE; /*< Clear DONE Status Bit Register, offset: 0x1C /
AnnaBridge	171:3a7713b1edbc	794	__O uint8_t SSRT; /*< Set START Bit Register, offset: 0x1D /
AnnaBridge	171:3a7713b1edbc	795	__O uint8_t CERR; /*< Clear Error Register, offset: 0x1E /
AnnaBridge	171:3a7713b1edbc	796	__O uint8_t CINT; /*< Clear Interrupt Request Register, offset: 0x1F /
AnnaBridge	171:3a7713b1edbc	797	uint8_t RESERVED_2[4];
AnnaBridge	171:3a7713b1edbc	798	__IO uint32_t INT; /*< Interrupt Request Register, offset: 0x24 /
AnnaBridge	171:3a7713b1edbc	799	uint8_t RESERVED_3[4];
AnnaBridge	171:3a7713b1edbc	800	__IO uint32_t ERR; /*< Error Register, offset: 0x2C /
AnnaBridge	171:3a7713b1edbc	801	uint8_t RESERVED_4[4];
AnnaBridge	171:3a7713b1edbc	802	__IO uint32_t HRS; /*< Hardware Request Status Register, offset: 0x34 /
AnnaBridge	171:3a7713b1edbc	803	uint8_t RESERVED_5[200];
AnnaBridge	171:3a7713b1edbc	804	__IO uint8_t DCHPRI3; /*< Channel n Priority Register, offset: 0x100 /
AnnaBridge	171:3a7713b1edbc	805	__IO uint8_t DCHPRI2; /*< Channel n Priority Register, offset: 0x101 /
AnnaBridge	171:3a7713b1edbc	806	__IO uint8_t DCHPRI1; /*< Channel n Priority Register, offset: 0x102 /
AnnaBridge	171:3a7713b1edbc	807	__IO uint8_t DCHPRI0; /*< Channel n Priority Register, offset: 0x103 /
AnnaBridge	171:3a7713b1edbc	808	uint8_t RESERVED_6[3836];
AnnaBridge	171:3a7713b1edbc	809	struct { /* offset: 0x1000, array step: 0x20 */
AnnaBridge	171:3a7713b1edbc	810	__IO uint32_t SADDR; /*< TCD Source Address, array offset: 0x1000, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	811	__IO uint16_t SOFF; /*< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	812	__IO uint16_t ATTR; /*< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	813	union { /* offset: 0x1008, array step: 0x20 */
AnnaBridge	171:3a7713b1edbc	814	__IO uint32_t NBYTES_MLNO; /*< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	815	__IO uint32_t NBYTES_MLOFFNO; /*< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	816	__IO uint32_t NBYTES_MLOFFYES; /*< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	817	};
AnnaBridge	171:3a7713b1edbc	818	__IO uint32_t SLAST; /*< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	819	__IO uint32_t DADDR; /*< TCD Destination Address, array offset: 0x1010, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	820	__IO uint16_t DOFF; /*< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	821	union { /* offset: 0x1016, array step: 0x20 */
AnnaBridge	171:3a7713b1edbc	822	__IO uint16_t CITER_ELINKNO; /*< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	823	__IO uint16_t CITER_ELINKYES; /*< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	824	};
AnnaBridge	171:3a7713b1edbc	825	__IO uint32_t DLAST_SGA; /*< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	826	__IO uint16_t CSR; /*< TCD Control and Status, array offset: 0x101C, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	827	union { /* offset: 0x101E, array step: 0x20 */
AnnaBridge	171:3a7713b1edbc	828	__IO uint16_t BITER_ELINKNO; /*< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	829	__IO uint16_t BITER_ELINKYES; /*< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 /
AnnaBridge	171:3a7713b1edbc	830	};
AnnaBridge	171:3a7713b1edbc	831	} TCD[4];
AnnaBridge	171:3a7713b1edbc	832	} DMA_Type;
AnnaBridge	171:3a7713b1edbc	833
AnnaBridge	171:3a7713b1edbc	834	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	835	-- DMA Register Masks
AnnaBridge	171:3a7713b1edbc	836	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	837
AnnaBridge	171:3a7713b1edbc	838	/**
AnnaBridge	171:3a7713b1edbc	839	* @addtogroup DMA_Register_Masks DMA Register Masks
AnnaBridge	171:3a7713b1edbc	840	* @{
AnnaBridge	171:3a7713b1edbc	841	*/
AnnaBridge	171:3a7713b1edbc	842
AnnaBridge	171:3a7713b1edbc	843	/* CR Bit Fields */
AnnaBridge	171:3a7713b1edbc	844	#define DMA_CR_EDBG_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	845	#define DMA_CR_EDBG_SHIFT 1
AnnaBridge	171:3a7713b1edbc	846	#define DMA_CR_ERCA_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	847	#define DMA_CR_ERCA_SHIFT 2
AnnaBridge	171:3a7713b1edbc	848	#define DMA_CR_HOE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	849	#define DMA_CR_HOE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	850	#define DMA_CR_HALT_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	851	#define DMA_CR_HALT_SHIFT 5
AnnaBridge	171:3a7713b1edbc	852	#define DMA_CR_CLM_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	853	#define DMA_CR_CLM_SHIFT 6
AnnaBridge	171:3a7713b1edbc	854	#define DMA_CR_EMLM_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	855	#define DMA_CR_EMLM_SHIFT 7
AnnaBridge	171:3a7713b1edbc	856	#define DMA_CR_ECX_MASK 0x10000u
AnnaBridge	171:3a7713b1edbc	857	#define DMA_CR_ECX_SHIFT 16
AnnaBridge	171:3a7713b1edbc	858	#define DMA_CR_CX_MASK 0x20000u
AnnaBridge	171:3a7713b1edbc	859	#define DMA_CR_CX_SHIFT 17
AnnaBridge	171:3a7713b1edbc	860	/* ES Bit Fields */
AnnaBridge	171:3a7713b1edbc	861	#define DMA_ES_DBE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	862	#define DMA_ES_DBE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	863	#define DMA_ES_SBE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	864	#define DMA_ES_SBE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	865	#define DMA_ES_SGE_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	866	#define DMA_ES_SGE_SHIFT 2
AnnaBridge	171:3a7713b1edbc	867	#define DMA_ES_NCE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	868	#define DMA_ES_NCE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	869	#define DMA_ES_DOE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	870	#define DMA_ES_DOE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	871	#define DMA_ES_DAE_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	872	#define DMA_ES_DAE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	873	#define DMA_ES_SOE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	874	#define DMA_ES_SOE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	875	#define DMA_ES_SAE_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	876	#define DMA_ES_SAE_SHIFT 7
AnnaBridge	171:3a7713b1edbc	877	#define DMA_ES_ERRCHN_MASK 0xF00u
AnnaBridge	171:3a7713b1edbc	878	#define DMA_ES_ERRCHN_SHIFT 8
AnnaBridge	171:3a7713b1edbc	879	#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
AnnaBridge	171:3a7713b1edbc	880	#define DMA_ES_CPE_MASK 0x4000u
AnnaBridge	171:3a7713b1edbc	881	#define DMA_ES_CPE_SHIFT 14
AnnaBridge	171:3a7713b1edbc	882	#define DMA_ES_ECX_MASK 0x10000u
AnnaBridge	171:3a7713b1edbc	883	#define DMA_ES_ECX_SHIFT 16
AnnaBridge	171:3a7713b1edbc	884	#define DMA_ES_VLD_MASK 0x80000000u
AnnaBridge	171:3a7713b1edbc	885	#define DMA_ES_VLD_SHIFT 31
AnnaBridge	171:3a7713b1edbc	886	/* ERQ Bit Fields */
AnnaBridge	171:3a7713b1edbc	887	#define DMA_ERQ_ERQ0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	888	#define DMA_ERQ_ERQ0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	889	#define DMA_ERQ_ERQ1_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	890	#define DMA_ERQ_ERQ1_SHIFT 1
AnnaBridge	171:3a7713b1edbc	891	#define DMA_ERQ_ERQ2_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	892	#define DMA_ERQ_ERQ2_SHIFT 2
AnnaBridge	171:3a7713b1edbc	893	#define DMA_ERQ_ERQ3_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	894	#define DMA_ERQ_ERQ3_SHIFT 3
AnnaBridge	171:3a7713b1edbc	895	/* EEI Bit Fields */
AnnaBridge	171:3a7713b1edbc	896	#define DMA_EEI_EEI0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	897	#define DMA_EEI_EEI0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	898	#define DMA_EEI_EEI1_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	899	#define DMA_EEI_EEI1_SHIFT 1
AnnaBridge	171:3a7713b1edbc	900	#define DMA_EEI_EEI2_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	901	#define DMA_EEI_EEI2_SHIFT 2
AnnaBridge	171:3a7713b1edbc	902	#define DMA_EEI_EEI3_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	903	#define DMA_EEI_EEI3_SHIFT 3
AnnaBridge	171:3a7713b1edbc	904	/* CEEI Bit Fields */
AnnaBridge	171:3a7713b1edbc	905	#define DMA_CEEI_CEEI_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	906	#define DMA_CEEI_CEEI_SHIFT 0
AnnaBridge	171:3a7713b1edbc	907	#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
AnnaBridge	171:3a7713b1edbc	908	#define DMA_CEEI_CAEE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	909	#define DMA_CEEI_CAEE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	910	#define DMA_CEEI_NOP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	911	#define DMA_CEEI_NOP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	912	/* SEEI Bit Fields */
AnnaBridge	171:3a7713b1edbc	913	#define DMA_SEEI_SEEI_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	914	#define DMA_SEEI_SEEI_SHIFT 0
AnnaBridge	171:3a7713b1edbc	915	#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
AnnaBridge	171:3a7713b1edbc	916	#define DMA_SEEI_SAEE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	917	#define DMA_SEEI_SAEE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	918	#define DMA_SEEI_NOP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	919	#define DMA_SEEI_NOP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	920	/* CERQ Bit Fields */
AnnaBridge	171:3a7713b1edbc	921	#define DMA_CERQ_CERQ_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	922	#define DMA_CERQ_CERQ_SHIFT 0
AnnaBridge	171:3a7713b1edbc	923	#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
AnnaBridge	171:3a7713b1edbc	924	#define DMA_CERQ_CAER_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	925	#define DMA_CERQ_CAER_SHIFT 6
AnnaBridge	171:3a7713b1edbc	926	#define DMA_CERQ_NOP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	927	#define DMA_CERQ_NOP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	928	/* SERQ Bit Fields */
AnnaBridge	171:3a7713b1edbc	929	#define DMA_SERQ_SERQ_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	930	#define DMA_SERQ_SERQ_SHIFT 0
AnnaBridge	171:3a7713b1edbc	931	#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
AnnaBridge	171:3a7713b1edbc	932	#define DMA_SERQ_SAER_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	933	#define DMA_SERQ_SAER_SHIFT 6
AnnaBridge	171:3a7713b1edbc	934	#define DMA_SERQ_NOP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	935	#define DMA_SERQ_NOP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	936	/* CDNE Bit Fields */
AnnaBridge	171:3a7713b1edbc	937	#define DMA_CDNE_CDNE_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	938	#define DMA_CDNE_CDNE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	939	#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
AnnaBridge	171:3a7713b1edbc	940	#define DMA_CDNE_CADN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	941	#define DMA_CDNE_CADN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	942	#define DMA_CDNE_NOP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	943	#define DMA_CDNE_NOP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	944	/* SSRT Bit Fields */
AnnaBridge	171:3a7713b1edbc	945	#define DMA_SSRT_SSRT_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	946	#define DMA_SSRT_SSRT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	947	#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
AnnaBridge	171:3a7713b1edbc	948	#define DMA_SSRT_SAST_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	949	#define DMA_SSRT_SAST_SHIFT 6
AnnaBridge	171:3a7713b1edbc	950	#define DMA_SSRT_NOP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	951	#define DMA_SSRT_NOP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	952	/* CERR Bit Fields */
AnnaBridge	171:3a7713b1edbc	953	#define DMA_CERR_CERR_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	954	#define DMA_CERR_CERR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	955	#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
AnnaBridge	171:3a7713b1edbc	956	#define DMA_CERR_CAEI_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	957	#define DMA_CERR_CAEI_SHIFT 6
AnnaBridge	171:3a7713b1edbc	958	#define DMA_CERR_NOP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	959	#define DMA_CERR_NOP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	960	/* CINT Bit Fields */
AnnaBridge	171:3a7713b1edbc	961	#define DMA_CINT_CINT_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	962	#define DMA_CINT_CINT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	963	#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
AnnaBridge	171:3a7713b1edbc	964	#define DMA_CINT_CAIR_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	965	#define DMA_CINT_CAIR_SHIFT 6
AnnaBridge	171:3a7713b1edbc	966	#define DMA_CINT_NOP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	967	#define DMA_CINT_NOP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	968	/* INT Bit Fields */
AnnaBridge	171:3a7713b1edbc	969	#define DMA_INT_INT0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	970	#define DMA_INT_INT0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	971	#define DMA_INT_INT1_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	972	#define DMA_INT_INT1_SHIFT 1
AnnaBridge	171:3a7713b1edbc	973	#define DMA_INT_INT2_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	974	#define DMA_INT_INT2_SHIFT 2
AnnaBridge	171:3a7713b1edbc	975	#define DMA_INT_INT3_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	976	#define DMA_INT_INT3_SHIFT 3
AnnaBridge	171:3a7713b1edbc	977	/* ERR Bit Fields */
AnnaBridge	171:3a7713b1edbc	978	#define DMA_ERR_ERR0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	979	#define DMA_ERR_ERR0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	980	#define DMA_ERR_ERR1_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	981	#define DMA_ERR_ERR1_SHIFT 1
AnnaBridge	171:3a7713b1edbc	982	#define DMA_ERR_ERR2_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	983	#define DMA_ERR_ERR2_SHIFT 2
AnnaBridge	171:3a7713b1edbc	984	#define DMA_ERR_ERR3_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	985	#define DMA_ERR_ERR3_SHIFT 3
AnnaBridge	171:3a7713b1edbc	986	/* HRS Bit Fields */
AnnaBridge	171:3a7713b1edbc	987	#define DMA_HRS_HRS0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	988	#define DMA_HRS_HRS0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	989	#define DMA_HRS_HRS1_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	990	#define DMA_HRS_HRS1_SHIFT 1
AnnaBridge	171:3a7713b1edbc	991	#define DMA_HRS_HRS2_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	992	#define DMA_HRS_HRS2_SHIFT 2
AnnaBridge	171:3a7713b1edbc	993	#define DMA_HRS_HRS3_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	994	#define DMA_HRS_HRS3_SHIFT 3
AnnaBridge	171:3a7713b1edbc	995	/* DCHPRI3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	996	#define DMA_DCHPRI3_CHPRI_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	997	#define DMA_DCHPRI3_CHPRI_SHIFT 0
AnnaBridge	171:3a7713b1edbc	998	#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
AnnaBridge	171:3a7713b1edbc	999	#define DMA_DCHPRI3_DPA_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1000	#define DMA_DCHPRI3_DPA_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1001	#define DMA_DCHPRI3_ECP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1002	#define DMA_DCHPRI3_ECP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1003	/* DCHPRI2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1004	#define DMA_DCHPRI2_CHPRI_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	1005	#define DMA_DCHPRI2_CHPRI_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1006	#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
AnnaBridge	171:3a7713b1edbc	1007	#define DMA_DCHPRI2_DPA_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1008	#define DMA_DCHPRI2_DPA_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1009	#define DMA_DCHPRI2_ECP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1010	#define DMA_DCHPRI2_ECP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1011	/* DCHPRI1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1012	#define DMA_DCHPRI1_CHPRI_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	1013	#define DMA_DCHPRI1_CHPRI_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1014	#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
AnnaBridge	171:3a7713b1edbc	1015	#define DMA_DCHPRI1_DPA_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1016	#define DMA_DCHPRI1_DPA_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1017	#define DMA_DCHPRI1_ECP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1018	#define DMA_DCHPRI1_ECP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1019	/* DCHPRI0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1020	#define DMA_DCHPRI0_CHPRI_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	1021	#define DMA_DCHPRI0_CHPRI_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1022	#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
AnnaBridge	171:3a7713b1edbc	1023	#define DMA_DCHPRI0_DPA_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1024	#define DMA_DCHPRI0_DPA_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1025	#define DMA_DCHPRI0_ECP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1026	#define DMA_DCHPRI0_ECP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1027	/* SADDR Bit Fields */
AnnaBridge	171:3a7713b1edbc	1028	#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	1029	#define DMA_SADDR_SADDR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1030	#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
AnnaBridge	171:3a7713b1edbc	1031	/* SOFF Bit Fields */
AnnaBridge	171:3a7713b1edbc	1032	#define DMA_SOFF_SOFF_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	1033	#define DMA_SOFF_SOFF_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1034	#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
AnnaBridge	171:3a7713b1edbc	1035	/* ATTR Bit Fields */
AnnaBridge	171:3a7713b1edbc	1036	#define DMA_ATTR_DSIZE_MASK 0x7u
AnnaBridge	171:3a7713b1edbc	1037	#define DMA_ATTR_DSIZE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1038	#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
AnnaBridge	171:3a7713b1edbc	1039	#define DMA_ATTR_DMOD_MASK 0xF8u
AnnaBridge	171:3a7713b1edbc	1040	#define DMA_ATTR_DMOD_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1041	#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
AnnaBridge	171:3a7713b1edbc	1042	#define DMA_ATTR_SSIZE_MASK 0x700u
AnnaBridge	171:3a7713b1edbc	1043	#define DMA_ATTR_SSIZE_SHIFT 8
AnnaBridge	171:3a7713b1edbc	1044	#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
AnnaBridge	171:3a7713b1edbc	1045	#define DMA_ATTR_SMOD_MASK 0xF800u
AnnaBridge	171:3a7713b1edbc	1046	#define DMA_ATTR_SMOD_SHIFT 11
AnnaBridge	171:3a7713b1edbc	1047	#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
AnnaBridge	171:3a7713b1edbc	1048	/* NBYTES_MLNO Bit Fields */
AnnaBridge	171:3a7713b1edbc	1049	#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	1050	#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1051	#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
AnnaBridge	171:3a7713b1edbc	1052	/* NBYTES_MLOFFNO Bit Fields */
AnnaBridge	171:3a7713b1edbc	1053	#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
AnnaBridge	171:3a7713b1edbc	1054	#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1055	#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
AnnaBridge	171:3a7713b1edbc	1056	#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
AnnaBridge	171:3a7713b1edbc	1057	#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
AnnaBridge	171:3a7713b1edbc	1058	#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
AnnaBridge	171:3a7713b1edbc	1059	#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
AnnaBridge	171:3a7713b1edbc	1060	/* NBYTES_MLOFFYES Bit Fields */
AnnaBridge	171:3a7713b1edbc	1061	#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
AnnaBridge	171:3a7713b1edbc	1062	#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1063	#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
AnnaBridge	171:3a7713b1edbc	1064	#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
AnnaBridge	171:3a7713b1edbc	1065	#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
AnnaBridge	171:3a7713b1edbc	1066	#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
AnnaBridge	171:3a7713b1edbc	1067	#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
AnnaBridge	171:3a7713b1edbc	1068	#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
AnnaBridge	171:3a7713b1edbc	1069	#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
AnnaBridge	171:3a7713b1edbc	1070	#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
AnnaBridge	171:3a7713b1edbc	1071	/* SLAST Bit Fields */
AnnaBridge	171:3a7713b1edbc	1072	#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	1073	#define DMA_SLAST_SLAST_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1074	#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
AnnaBridge	171:3a7713b1edbc	1075	/* DADDR Bit Fields */
AnnaBridge	171:3a7713b1edbc	1076	#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	1077	#define DMA_DADDR_DADDR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1078	#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
AnnaBridge	171:3a7713b1edbc	1079	/* DOFF Bit Fields */
AnnaBridge	171:3a7713b1edbc	1080	#define DMA_DOFF_DOFF_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	1081	#define DMA_DOFF_DOFF_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1082	#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
AnnaBridge	171:3a7713b1edbc	1083	/* CITER_ELINKNO Bit Fields */
AnnaBridge	171:3a7713b1edbc	1084	#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
AnnaBridge	171:3a7713b1edbc	1085	#define DMA_CITER_ELINKNO_CITER_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1086	#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
AnnaBridge	171:3a7713b1edbc	1087	#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
AnnaBridge	171:3a7713b1edbc	1088	#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
AnnaBridge	171:3a7713b1edbc	1089	/* CITER_ELINKYES Bit Fields */
AnnaBridge	171:3a7713b1edbc	1090	#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
AnnaBridge	171:3a7713b1edbc	1091	#define DMA_CITER_ELINKYES_CITER_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1092	#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
AnnaBridge	171:3a7713b1edbc	1093	#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
AnnaBridge	171:3a7713b1edbc	1094	#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
AnnaBridge	171:3a7713b1edbc	1095	#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
AnnaBridge	171:3a7713b1edbc	1096	#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
AnnaBridge	171:3a7713b1edbc	1097	#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
AnnaBridge	171:3a7713b1edbc	1098	/* DLAST_SGA Bit Fields */
AnnaBridge	171:3a7713b1edbc	1099	#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	1100	#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1101	#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
AnnaBridge	171:3a7713b1edbc	1102	/* CSR Bit Fields */
AnnaBridge	171:3a7713b1edbc	1103	#define DMA_CSR_START_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1104	#define DMA_CSR_START_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1105	#define DMA_CSR_INTMAJOR_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1106	#define DMA_CSR_INTMAJOR_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1107	#define DMA_CSR_INTHALF_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1108	#define DMA_CSR_INTHALF_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1109	#define DMA_CSR_DREQ_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1110	#define DMA_CSR_DREQ_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1111	#define DMA_CSR_ESG_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1112	#define DMA_CSR_ESG_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1113	#define DMA_CSR_MAJORELINK_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1114	#define DMA_CSR_MAJORELINK_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1115	#define DMA_CSR_ACTIVE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1116	#define DMA_CSR_ACTIVE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1117	#define DMA_CSR_DONE_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1118	#define DMA_CSR_DONE_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1119	#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
AnnaBridge	171:3a7713b1edbc	1120	#define DMA_CSR_MAJORLINKCH_SHIFT 8
AnnaBridge	171:3a7713b1edbc	1121	#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
AnnaBridge	171:3a7713b1edbc	1122	#define DMA_CSR_BWC_MASK 0xC000u
AnnaBridge	171:3a7713b1edbc	1123	#define DMA_CSR_BWC_SHIFT 14
AnnaBridge	171:3a7713b1edbc	1124	#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
AnnaBridge	171:3a7713b1edbc	1125	/* BITER_ELINKNO Bit Fields */
AnnaBridge	171:3a7713b1edbc	1126	#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
AnnaBridge	171:3a7713b1edbc	1127	#define DMA_BITER_ELINKNO_BITER_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1128	#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
AnnaBridge	171:3a7713b1edbc	1129	#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
AnnaBridge	171:3a7713b1edbc	1130	#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
AnnaBridge	171:3a7713b1edbc	1131	/* BITER_ELINKYES Bit Fields */
AnnaBridge	171:3a7713b1edbc	1132	#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
AnnaBridge	171:3a7713b1edbc	1133	#define DMA_BITER_ELINKYES_BITER_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1134	#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
AnnaBridge	171:3a7713b1edbc	1135	#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
AnnaBridge	171:3a7713b1edbc	1136	#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
AnnaBridge	171:3a7713b1edbc	1137	#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
AnnaBridge	171:3a7713b1edbc	1138	#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
AnnaBridge	171:3a7713b1edbc	1139	#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
AnnaBridge	171:3a7713b1edbc	1140
AnnaBridge	171:3a7713b1edbc	1141	/**
AnnaBridge	171:3a7713b1edbc	1142	* @}
AnnaBridge	171:3a7713b1edbc	1143	/ / end of group DMA_Register_Masks */
AnnaBridge	171:3a7713b1edbc	1144
AnnaBridge	171:3a7713b1edbc	1145
AnnaBridge	171:3a7713b1edbc	1146	/* DMA - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	1147	/** Peripheral DMA base address */
AnnaBridge	171:3a7713b1edbc	1148	#define DMA_BASE (0x40008000u)
AnnaBridge	171:3a7713b1edbc	1149	/** Peripheral DMA base pointer */
AnnaBridge	171:3a7713b1edbc	1150	#define DMA0 ((DMA_Type *)DMA_BASE)
AnnaBridge	171:3a7713b1edbc	1151
AnnaBridge	171:3a7713b1edbc	1152	/**
AnnaBridge	171:3a7713b1edbc	1153	* @}
AnnaBridge	171:3a7713b1edbc	1154	/ / end of group DMA_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	1155
AnnaBridge	171:3a7713b1edbc	1156
AnnaBridge	171:3a7713b1edbc	1157	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1158	-- DMAMUX Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	1159	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	1160
AnnaBridge	171:3a7713b1edbc	1161	/**
AnnaBridge	171:3a7713b1edbc	1162	* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	1163	* @{
AnnaBridge	171:3a7713b1edbc	1164	*/
AnnaBridge	171:3a7713b1edbc	1165
AnnaBridge	171:3a7713b1edbc	1166	/** DMAMUX - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	1167	typedef struct {
AnnaBridge	171:3a7713b1edbc	1168	__IO uint8_t CHCFG[16]; /*< Channel Configuration Register, array offset: 0x0, array step: 0x1 /
AnnaBridge	171:3a7713b1edbc	1169	} DMAMUX_Type;
AnnaBridge	171:3a7713b1edbc	1170
AnnaBridge	171:3a7713b1edbc	1171	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1172	-- DMAMUX Register Masks
AnnaBridge	171:3a7713b1edbc	1173	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	1174
AnnaBridge	171:3a7713b1edbc	1175	/**
AnnaBridge	171:3a7713b1edbc	1176	* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
AnnaBridge	171:3a7713b1edbc	1177	* @{
AnnaBridge	171:3a7713b1edbc	1178	*/
AnnaBridge	171:3a7713b1edbc	1179
AnnaBridge	171:3a7713b1edbc	1180	/* CHCFG Bit Fields */
AnnaBridge	171:3a7713b1edbc	1181	#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	1182	#define DMAMUX_CHCFG_SOURCE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1183	#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
AnnaBridge	171:3a7713b1edbc	1184	#define DMAMUX_CHCFG_TRIG_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1185	#define DMAMUX_CHCFG_TRIG_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1186	#define DMAMUX_CHCFG_ENBL_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1187	#define DMAMUX_CHCFG_ENBL_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1188
AnnaBridge	171:3a7713b1edbc	1189	/**
AnnaBridge	171:3a7713b1edbc	1190	* @}
AnnaBridge	171:3a7713b1edbc	1191	/ / end of group DMAMUX_Register_Masks */
AnnaBridge	171:3a7713b1edbc	1192
AnnaBridge	171:3a7713b1edbc	1193
AnnaBridge	171:3a7713b1edbc	1194	/* DMAMUX - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	1195	/** Peripheral DMAMUX base address */
AnnaBridge	171:3a7713b1edbc	1196	#define DMAMUX_BASE (0x40021000u)
AnnaBridge	171:3a7713b1edbc	1197	/** Peripheral DMAMUX base pointer */
AnnaBridge	171:3a7713b1edbc	1198	#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
AnnaBridge	171:3a7713b1edbc	1199
AnnaBridge	171:3a7713b1edbc	1200	/**
AnnaBridge	171:3a7713b1edbc	1201	* @}
AnnaBridge	171:3a7713b1edbc	1202	/ / end of group DMAMUX_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	1203
AnnaBridge	171:3a7713b1edbc	1204
AnnaBridge	171:3a7713b1edbc	1205	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1206	-- EWM Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	1207	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	1208
AnnaBridge	171:3a7713b1edbc	1209	/**
AnnaBridge	171:3a7713b1edbc	1210	* @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	1211	* @{
AnnaBridge	171:3a7713b1edbc	1212	*/
AnnaBridge	171:3a7713b1edbc	1213
AnnaBridge	171:3a7713b1edbc	1214	/** EWM - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	1215	typedef struct {
AnnaBridge	171:3a7713b1edbc	1216	__IO uint8_t CTRL; /*< Control Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	1217	__O uint8_t SERV; /*< Service Register, offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	1218	__IO uint8_t CMPL; /*< Compare Low Register, offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	1219	__IO uint8_t CMPH; /*< Compare High Register, offset: 0x3 /
AnnaBridge	171:3a7713b1edbc	1220	} EWM_Type;
AnnaBridge	171:3a7713b1edbc	1221
AnnaBridge	171:3a7713b1edbc	1222	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1223	-- EWM Register Masks
AnnaBridge	171:3a7713b1edbc	1224	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	1225
AnnaBridge	171:3a7713b1edbc	1226	/**
AnnaBridge	171:3a7713b1edbc	1227	* @addtogroup EWM_Register_Masks EWM Register Masks
AnnaBridge	171:3a7713b1edbc	1228	* @{
AnnaBridge	171:3a7713b1edbc	1229	*/
AnnaBridge	171:3a7713b1edbc	1230
AnnaBridge	171:3a7713b1edbc	1231	/* CTRL Bit Fields */
AnnaBridge	171:3a7713b1edbc	1232	#define EWM_CTRL_EWMEN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1233	#define EWM_CTRL_EWMEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1234	#define EWM_CTRL_ASSIN_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1235	#define EWM_CTRL_ASSIN_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1236	#define EWM_CTRL_INEN_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1237	#define EWM_CTRL_INEN_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1238	#define EWM_CTRL_INTEN_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1239	#define EWM_CTRL_INTEN_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1240	/* SERV Bit Fields */
AnnaBridge	171:3a7713b1edbc	1241	#define EWM_SERV_SERVICE_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1242	#define EWM_SERV_SERVICE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1243	#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
AnnaBridge	171:3a7713b1edbc	1244	/* CMPL Bit Fields */
AnnaBridge	171:3a7713b1edbc	1245	#define EWM_CMPL_COMPAREL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1246	#define EWM_CMPL_COMPAREL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1247	#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
AnnaBridge	171:3a7713b1edbc	1248	/* CMPH Bit Fields */
AnnaBridge	171:3a7713b1edbc	1249	#define EWM_CMPH_COMPAREH_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1250	#define EWM_CMPH_COMPAREH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1251	#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
AnnaBridge	171:3a7713b1edbc	1252
AnnaBridge	171:3a7713b1edbc	1253	/**
AnnaBridge	171:3a7713b1edbc	1254	* @}
AnnaBridge	171:3a7713b1edbc	1255	/ / end of group EWM_Register_Masks */
AnnaBridge	171:3a7713b1edbc	1256
AnnaBridge	171:3a7713b1edbc	1257
AnnaBridge	171:3a7713b1edbc	1258	/* EWM - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	1259	/** Peripheral EWM base address */
AnnaBridge	171:3a7713b1edbc	1260	#define EWM_BASE (0x40061000u)
AnnaBridge	171:3a7713b1edbc	1261	/** Peripheral EWM base pointer */
AnnaBridge	171:3a7713b1edbc	1262	#define EWM ((EWM_Type *)EWM_BASE)
AnnaBridge	171:3a7713b1edbc	1263
AnnaBridge	171:3a7713b1edbc	1264	/**
AnnaBridge	171:3a7713b1edbc	1265	* @}
AnnaBridge	171:3a7713b1edbc	1266	/ / end of group EWM_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	1267
AnnaBridge	171:3a7713b1edbc	1268
AnnaBridge	171:3a7713b1edbc	1269	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1270	-- FMC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	1271	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	1272
AnnaBridge	171:3a7713b1edbc	1273	/**
AnnaBridge	171:3a7713b1edbc	1274	* @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	1275	* @{
AnnaBridge	171:3a7713b1edbc	1276	*/
AnnaBridge	171:3a7713b1edbc	1277
AnnaBridge	171:3a7713b1edbc	1278	/** FMC - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	1279	typedef struct {
AnnaBridge	171:3a7713b1edbc	1280	__IO uint32_t PFAPR; /*< Flash Access Protection Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	1281	__IO uint32_t PFB0CR; /*< Flash Control Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	1282	uint8_t RESERVED_0[248];
AnnaBridge	171:3a7713b1edbc	1283	struct { /* offset: 0x100, array step: 0x20 */
AnnaBridge	171:3a7713b1edbc	1284	__IO uint32_t TAGVD[2]; /*< Cache Tag Storage, array offset: 0x100, array step: index0x20, index20x4 /
AnnaBridge	171:3a7713b1edbc	1285	uint8_t RESERVED_0[24];
AnnaBridge	171:3a7713b1edbc	1286	} TAG_WAY[4];
AnnaBridge	171:3a7713b1edbc	1287	uint8_t RESERVED_1[132];
AnnaBridge	171:3a7713b1edbc	1288	struct { /* offset: 0x204, array step: 0x8 */
AnnaBridge	171:3a7713b1edbc	1289	__IO uint32_t DATAW0S; /*< Cache Data Storage, array offset: 0x204, array step: 0x8 /
AnnaBridge	171:3a7713b1edbc	1290	uint8_t RESERVED_0[4];
AnnaBridge	171:3a7713b1edbc	1291	} DATAW0S[2];
AnnaBridge	171:3a7713b1edbc	1292	uint8_t RESERVED_2[48];
AnnaBridge	171:3a7713b1edbc	1293	struct { /* offset: 0x244, array step: 0x8 */
AnnaBridge	171:3a7713b1edbc	1294	__IO uint32_t DATAW1S; /*< Cache Data Storage, array offset: 0x244, array step: 0x8 /
AnnaBridge	171:3a7713b1edbc	1295	uint8_t RESERVED_0[4];
AnnaBridge	171:3a7713b1edbc	1296	} DATAW1S[2];
AnnaBridge	171:3a7713b1edbc	1297	uint8_t RESERVED_3[48];
AnnaBridge	171:3a7713b1edbc	1298	struct { /* offset: 0x284, array step: 0x8 */
AnnaBridge	171:3a7713b1edbc	1299	__IO uint32_t DATAW2S; /*< Cache Data Storage, array offset: 0x284, array step: 0x8 /
AnnaBridge	171:3a7713b1edbc	1300	uint8_t RESERVED_0[4];
AnnaBridge	171:3a7713b1edbc	1301	} DATAW2S[2];
AnnaBridge	171:3a7713b1edbc	1302	uint8_t RESERVED_4[48];
AnnaBridge	171:3a7713b1edbc	1303	struct { /* offset: 0x2C4, array step: 0x8 */
AnnaBridge	171:3a7713b1edbc	1304	__IO uint32_t DATAW3S; /*< Cache Data Storage, array offset: 0x2C4, array step: 0x8 /
AnnaBridge	171:3a7713b1edbc	1305	uint8_t RESERVED_0[4];
AnnaBridge	171:3a7713b1edbc	1306	} DATAW3S[2];
AnnaBridge	171:3a7713b1edbc	1307	} FMC_Type;
AnnaBridge	171:3a7713b1edbc	1308
AnnaBridge	171:3a7713b1edbc	1309	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1310	-- FMC Register Masks
AnnaBridge	171:3a7713b1edbc	1311	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	1312
AnnaBridge	171:3a7713b1edbc	1313	/**
AnnaBridge	171:3a7713b1edbc	1314	* @addtogroup FMC_Register_Masks FMC Register Masks
AnnaBridge	171:3a7713b1edbc	1315	* @{
AnnaBridge	171:3a7713b1edbc	1316	*/
AnnaBridge	171:3a7713b1edbc	1317
AnnaBridge	171:3a7713b1edbc	1318	/* PFAPR Bit Fields */
AnnaBridge	171:3a7713b1edbc	1319	#define FMC_PFAPR_M0AP_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	1320	#define FMC_PFAPR_M0AP_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1321	#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
AnnaBridge	171:3a7713b1edbc	1322	#define FMC_PFAPR_M1AP_MASK 0xCu
AnnaBridge	171:3a7713b1edbc	1323	#define FMC_PFAPR_M1AP_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1324	#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
AnnaBridge	171:3a7713b1edbc	1325	#define FMC_PFAPR_M2AP_MASK 0x30u
AnnaBridge	171:3a7713b1edbc	1326	#define FMC_PFAPR_M2AP_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1327	#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
AnnaBridge	171:3a7713b1edbc	1328	#define FMC_PFAPR_M3AP_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	1329	#define FMC_PFAPR_M3AP_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1330	#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
AnnaBridge	171:3a7713b1edbc	1331	#define FMC_PFAPR_M0PFD_MASK 0x10000u
AnnaBridge	171:3a7713b1edbc	1332	#define FMC_PFAPR_M0PFD_SHIFT 16
AnnaBridge	171:3a7713b1edbc	1333	#define FMC_PFAPR_M1PFD_MASK 0x20000u
AnnaBridge	171:3a7713b1edbc	1334	#define FMC_PFAPR_M1PFD_SHIFT 17
AnnaBridge	171:3a7713b1edbc	1335	#define FMC_PFAPR_M2PFD_MASK 0x40000u
AnnaBridge	171:3a7713b1edbc	1336	#define FMC_PFAPR_M2PFD_SHIFT 18
AnnaBridge	171:3a7713b1edbc	1337	#define FMC_PFAPR_M3PFD_MASK 0x80000u
AnnaBridge	171:3a7713b1edbc	1338	#define FMC_PFAPR_M3PFD_SHIFT 19
AnnaBridge	171:3a7713b1edbc	1339	/* PFB0CR Bit Fields */
AnnaBridge	171:3a7713b1edbc	1340	#define FMC_PFB0CR_B0SEBE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1341	#define FMC_PFB0CR_B0SEBE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1342	#define FMC_PFB0CR_B0IPE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1343	#define FMC_PFB0CR_B0IPE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1344	#define FMC_PFB0CR_B0DPE_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1345	#define FMC_PFB0CR_B0DPE_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1346	#define FMC_PFB0CR_B0ICE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1347	#define FMC_PFB0CR_B0ICE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1348	#define FMC_PFB0CR_B0DCE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1349	#define FMC_PFB0CR_B0DCE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1350	#define FMC_PFB0CR_CRC_MASK 0xE0u
AnnaBridge	171:3a7713b1edbc	1351	#define FMC_PFB0CR_CRC_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1352	#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
AnnaBridge	171:3a7713b1edbc	1353	#define FMC_PFB0CR_B0MW_MASK 0x60000u
AnnaBridge	171:3a7713b1edbc	1354	#define FMC_PFB0CR_B0MW_SHIFT 17
AnnaBridge	171:3a7713b1edbc	1355	#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
AnnaBridge	171:3a7713b1edbc	1356	#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
AnnaBridge	171:3a7713b1edbc	1357	#define FMC_PFB0CR_S_B_INV_SHIFT 19
AnnaBridge	171:3a7713b1edbc	1358	#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
AnnaBridge	171:3a7713b1edbc	1359	#define FMC_PFB0CR_CINV_WAY_SHIFT 20
AnnaBridge	171:3a7713b1edbc	1360	#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
AnnaBridge	171:3a7713b1edbc	1361	#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
AnnaBridge	171:3a7713b1edbc	1362	#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
AnnaBridge	171:3a7713b1edbc	1363	#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
AnnaBridge	171:3a7713b1edbc	1364	#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
AnnaBridge	171:3a7713b1edbc	1365	#define FMC_PFB0CR_B0RWSC_SHIFT 28
AnnaBridge	171:3a7713b1edbc	1366	#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
AnnaBridge	171:3a7713b1edbc	1367	/* TAGVD Bit Fields */
AnnaBridge	171:3a7713b1edbc	1368	#define FMC_TAGVD_valid_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1369	#define FMC_TAGVD_valid_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1370	#define FMC_TAGVD_tag_MASK 0x7FFC0u
AnnaBridge	171:3a7713b1edbc	1371	#define FMC_TAGVD_tag_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1372	#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
AnnaBridge	171:3a7713b1edbc	1373	/* DATAW0S Bit Fields */
AnnaBridge	171:3a7713b1edbc	1374	#define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	1375	#define FMC_DATAW0S_data_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1376	#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
AnnaBridge	171:3a7713b1edbc	1377	/* DATAW1S Bit Fields */
AnnaBridge	171:3a7713b1edbc	1378	#define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	1379	#define FMC_DATAW1S_data_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1380	#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
AnnaBridge	171:3a7713b1edbc	1381	/* DATAW2S Bit Fields */
AnnaBridge	171:3a7713b1edbc	1382	#define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	1383	#define FMC_DATAW2S_data_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1384	#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
AnnaBridge	171:3a7713b1edbc	1385	/* DATAW3S Bit Fields */
AnnaBridge	171:3a7713b1edbc	1386	#define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	1387	#define FMC_DATAW3S_data_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1388	#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
AnnaBridge	171:3a7713b1edbc	1389
AnnaBridge	171:3a7713b1edbc	1390	/**
AnnaBridge	171:3a7713b1edbc	1391	* @}
AnnaBridge	171:3a7713b1edbc	1392	/ / end of group FMC_Register_Masks */
AnnaBridge	171:3a7713b1edbc	1393
AnnaBridge	171:3a7713b1edbc	1394
AnnaBridge	171:3a7713b1edbc	1395	/* FMC - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	1396	/** Peripheral FMC base address */
AnnaBridge	171:3a7713b1edbc	1397	#define FMC_BASE (0x4001F000u)
AnnaBridge	171:3a7713b1edbc	1398	/** Peripheral FMC base pointer */
AnnaBridge	171:3a7713b1edbc	1399	#define FMC ((FMC_Type *)FMC_BASE)
AnnaBridge	171:3a7713b1edbc	1400
AnnaBridge	171:3a7713b1edbc	1401	/**
AnnaBridge	171:3a7713b1edbc	1402	* @}
AnnaBridge	171:3a7713b1edbc	1403	/ / end of group FMC_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	1404
AnnaBridge	171:3a7713b1edbc	1405
AnnaBridge	171:3a7713b1edbc	1406	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1407	-- FTFL Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	1408	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	1409
AnnaBridge	171:3a7713b1edbc	1410	/**
AnnaBridge	171:3a7713b1edbc	1411	* @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	1412	* @{
AnnaBridge	171:3a7713b1edbc	1413	*/
AnnaBridge	171:3a7713b1edbc	1414
AnnaBridge	171:3a7713b1edbc	1415	/** FTFL - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	1416	typedef struct {
AnnaBridge	171:3a7713b1edbc	1417	__IO uint8_t FSTAT; /*< Flash Status Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	1418	__IO uint8_t FCNFG; /*< Flash Configuration Register, offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	1419	__I uint8_t FSEC; /*< Flash Security Register, offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	1420	__I uint8_t FOPT; /*< Flash Option Register, offset: 0x3 /
AnnaBridge	171:3a7713b1edbc	1421	__IO uint8_t FCCOB3; /*< Flash Common Command Object Registers, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	1422	__IO uint8_t FCCOB2; /*< Flash Common Command Object Registers, offset: 0x5 /
AnnaBridge	171:3a7713b1edbc	1423	__IO uint8_t FCCOB1; /*< Flash Common Command Object Registers, offset: 0x6 /
AnnaBridge	171:3a7713b1edbc	1424	__IO uint8_t FCCOB0; /*< Flash Common Command Object Registers, offset: 0x7 /
AnnaBridge	171:3a7713b1edbc	1425	__IO uint8_t FCCOB7; /*< Flash Common Command Object Registers, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	1426	__IO uint8_t FCCOB6; /*< Flash Common Command Object Registers, offset: 0x9 /
AnnaBridge	171:3a7713b1edbc	1427	__IO uint8_t FCCOB5; /*< Flash Common Command Object Registers, offset: 0xA /
AnnaBridge	171:3a7713b1edbc	1428	__IO uint8_t FCCOB4; /*< Flash Common Command Object Registers, offset: 0xB /
AnnaBridge	171:3a7713b1edbc	1429	__IO uint8_t FCCOBB; /*< Flash Common Command Object Registers, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	1430	__IO uint8_t FCCOBA; /*< Flash Common Command Object Registers, offset: 0xD /
AnnaBridge	171:3a7713b1edbc	1431	__IO uint8_t FCCOB9; /*< Flash Common Command Object Registers, offset: 0xE /
AnnaBridge	171:3a7713b1edbc	1432	__IO uint8_t FCCOB8; /*< Flash Common Command Object Registers, offset: 0xF /
AnnaBridge	171:3a7713b1edbc	1433	__IO uint8_t FPROT3; /*< Program Flash Protection Registers, offset: 0x10 /
AnnaBridge	171:3a7713b1edbc	1434	__IO uint8_t FPROT2; /*< Program Flash Protection Registers, offset: 0x11 /
AnnaBridge	171:3a7713b1edbc	1435	__IO uint8_t FPROT1; /*< Program Flash Protection Registers, offset: 0x12 /
AnnaBridge	171:3a7713b1edbc	1436	__IO uint8_t FPROT0; /*< Program Flash Protection Registers, offset: 0x13 /
AnnaBridge	171:3a7713b1edbc	1437	uint8_t RESERVED_0[2];
AnnaBridge	171:3a7713b1edbc	1438	__IO uint8_t FEPROT; /*< EEPROM Protection Register, offset: 0x16 /
AnnaBridge	171:3a7713b1edbc	1439	__IO uint8_t FDPROT; /*< Data Flash Protection Register, offset: 0x17 /
AnnaBridge	171:3a7713b1edbc	1440	} FTFL_Type;
AnnaBridge	171:3a7713b1edbc	1441
AnnaBridge	171:3a7713b1edbc	1442	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1443	-- FTFL Register Masks
AnnaBridge	171:3a7713b1edbc	1444	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	1445
AnnaBridge	171:3a7713b1edbc	1446	/**
AnnaBridge	171:3a7713b1edbc	1447	* @addtogroup FTFL_Register_Masks FTFL Register Masks
AnnaBridge	171:3a7713b1edbc	1448	* @{
AnnaBridge	171:3a7713b1edbc	1449	*/
AnnaBridge	171:3a7713b1edbc	1450
AnnaBridge	171:3a7713b1edbc	1451	/* FSTAT Bit Fields */
AnnaBridge	171:3a7713b1edbc	1452	#define FTFL_FSTAT_MGSTAT0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1453	#define FTFL_FSTAT_MGSTAT0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1454	#define FTFL_FSTAT_FPVIOL_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1455	#define FTFL_FSTAT_FPVIOL_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1456	#define FTFL_FSTAT_ACCERR_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1457	#define FTFL_FSTAT_ACCERR_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1458	#define FTFL_FSTAT_RDCOLERR_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1459	#define FTFL_FSTAT_RDCOLERR_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1460	#define FTFL_FSTAT_CCIF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1461	#define FTFL_FSTAT_CCIF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1462	/* FCNFG Bit Fields */
AnnaBridge	171:3a7713b1edbc	1463	#define FTFL_FCNFG_EEERDY_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1464	#define FTFL_FCNFG_EEERDY_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1465	#define FTFL_FCNFG_RAMRDY_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1466	#define FTFL_FCNFG_RAMRDY_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1467	#define FTFL_FCNFG_PFLSH_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1468	#define FTFL_FCNFG_PFLSH_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1469	#define FTFL_FCNFG_ERSSUSP_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1470	#define FTFL_FCNFG_ERSSUSP_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1471	#define FTFL_FCNFG_ERSAREQ_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1472	#define FTFL_FCNFG_ERSAREQ_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1473	#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1474	#define FTFL_FCNFG_RDCOLLIE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1475	#define FTFL_FCNFG_CCIE_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1476	#define FTFL_FCNFG_CCIE_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1477	/* FSEC Bit Fields */
AnnaBridge	171:3a7713b1edbc	1478	#define FTFL_FSEC_SEC_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	1479	#define FTFL_FSEC_SEC_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1480	#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
AnnaBridge	171:3a7713b1edbc	1481	#define FTFL_FSEC_FSLACC_MASK 0xCu
AnnaBridge	171:3a7713b1edbc	1482	#define FTFL_FSEC_FSLACC_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1483	#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
AnnaBridge	171:3a7713b1edbc	1484	#define FTFL_FSEC_MEEN_MASK 0x30u
AnnaBridge	171:3a7713b1edbc	1485	#define FTFL_FSEC_MEEN_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1486	#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
AnnaBridge	171:3a7713b1edbc	1487	#define FTFL_FSEC_KEYEN_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	1488	#define FTFL_FSEC_KEYEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1489	#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
AnnaBridge	171:3a7713b1edbc	1490	/* FOPT Bit Fields */
AnnaBridge	171:3a7713b1edbc	1491	#define FTFL_FOPT_OPT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1492	#define FTFL_FOPT_OPT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1493	#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
AnnaBridge	171:3a7713b1edbc	1494	/* FCCOB3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1495	#define FTFL_FCCOB3_CCOBn_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1496	#define FTFL_FCCOB3_CCOBn_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1497	#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
AnnaBridge	171:3a7713b1edbc	1498	/* FCCOB2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1499	#define FTFL_FCCOB2_CCOBn_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1500	#define FTFL_FCCOB2_CCOBn_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1501	#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
AnnaBridge	171:3a7713b1edbc	1502	/* FCCOB1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1503	#define FTFL_FCCOB1_CCOBn_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1504	#define FTFL_FCCOB1_CCOBn_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1505	#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
AnnaBridge	171:3a7713b1edbc	1506	/* FCCOB0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1507	#define FTFL_FCCOB0_CCOBn_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1508	#define FTFL_FCCOB0_CCOBn_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1509	#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
AnnaBridge	171:3a7713b1edbc	1510	/* FCCOB7 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1511	#define FTFL_FCCOB7_CCOBn_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1512	#define FTFL_FCCOB7_CCOBn_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1513	#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
AnnaBridge	171:3a7713b1edbc	1514	/* FCCOB6 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1515	#define FTFL_FCCOB6_CCOBn_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1516	#define FTFL_FCCOB6_CCOBn_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1517	#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
AnnaBridge	171:3a7713b1edbc	1518	/* FCCOB5 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1519	#define FTFL_FCCOB5_CCOBn_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1520	#define FTFL_FCCOB5_CCOBn_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1521	#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
AnnaBridge	171:3a7713b1edbc	1522	/* FCCOB4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1523	#define FTFL_FCCOB4_CCOBn_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1524	#define FTFL_FCCOB4_CCOBn_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1525	#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
AnnaBridge	171:3a7713b1edbc	1526	/* FCCOBB Bit Fields */
AnnaBridge	171:3a7713b1edbc	1527	#define FTFL_FCCOBB_CCOBn_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1528	#define FTFL_FCCOBB_CCOBn_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1529	#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
AnnaBridge	171:3a7713b1edbc	1530	/* FCCOBA Bit Fields */
AnnaBridge	171:3a7713b1edbc	1531	#define FTFL_FCCOBA_CCOBn_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1532	#define FTFL_FCCOBA_CCOBn_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1533	#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
AnnaBridge	171:3a7713b1edbc	1534	/* FCCOB9 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1535	#define FTFL_FCCOB9_CCOBn_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1536	#define FTFL_FCCOB9_CCOBn_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1537	#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
AnnaBridge	171:3a7713b1edbc	1538	/* FCCOB8 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1539	#define FTFL_FCCOB8_CCOBn_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1540	#define FTFL_FCCOB8_CCOBn_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1541	#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
AnnaBridge	171:3a7713b1edbc	1542	/* FPROT3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1543	#define FTFL_FPROT3_PROT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1544	#define FTFL_FPROT3_PROT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1545	#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
AnnaBridge	171:3a7713b1edbc	1546	/* FPROT2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1547	#define FTFL_FPROT2_PROT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1548	#define FTFL_FPROT2_PROT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1549	#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
AnnaBridge	171:3a7713b1edbc	1550	/* FPROT1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1551	#define FTFL_FPROT1_PROT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1552	#define FTFL_FPROT1_PROT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1553	#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
AnnaBridge	171:3a7713b1edbc	1554	/* FPROT0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	1555	#define FTFL_FPROT0_PROT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1556	#define FTFL_FPROT0_PROT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1557	#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
AnnaBridge	171:3a7713b1edbc	1558	/* FEPROT Bit Fields */
AnnaBridge	171:3a7713b1edbc	1559	#define FTFL_FEPROT_EPROT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1560	#define FTFL_FEPROT_EPROT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1561	#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
AnnaBridge	171:3a7713b1edbc	1562	/* FDPROT Bit Fields */
AnnaBridge	171:3a7713b1edbc	1563	#define FTFL_FDPROT_DPROT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	1564	#define FTFL_FDPROT_DPROT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1565	#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
AnnaBridge	171:3a7713b1edbc	1566
AnnaBridge	171:3a7713b1edbc	1567	/**
AnnaBridge	171:3a7713b1edbc	1568	* @}
AnnaBridge	171:3a7713b1edbc	1569	/ / end of group FTFL_Register_Masks */
AnnaBridge	171:3a7713b1edbc	1570
AnnaBridge	171:3a7713b1edbc	1571
AnnaBridge	171:3a7713b1edbc	1572	/* FTFL - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	1573	/** Peripheral FTFL base address */
AnnaBridge	171:3a7713b1edbc	1574	#define FTFL_BASE (0x40020000u)
AnnaBridge	171:3a7713b1edbc	1575	/** Peripheral FTFL base pointer */
AnnaBridge	171:3a7713b1edbc	1576	#define FTFL ((FTFL_Type *)FTFL_BASE)
AnnaBridge	171:3a7713b1edbc	1577
AnnaBridge	171:3a7713b1edbc	1578	/**
AnnaBridge	171:3a7713b1edbc	1579	* @}
AnnaBridge	171:3a7713b1edbc	1580	/ / end of group FTFL_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	1581
AnnaBridge	171:3a7713b1edbc	1582
AnnaBridge	171:3a7713b1edbc	1583	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1584	-- FTM Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	1585	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	1586
AnnaBridge	171:3a7713b1edbc	1587	/**
AnnaBridge	171:3a7713b1edbc	1588	* @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	1589	* @{
AnnaBridge	171:3a7713b1edbc	1590	*/
AnnaBridge	171:3a7713b1edbc	1591
AnnaBridge	171:3a7713b1edbc	1592	/** FTM - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	1593	typedef struct {
AnnaBridge	171:3a7713b1edbc	1594	__IO uint32_t SC; /*< Status and Control, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	1595	__IO uint32_t CNT; /*< Counter, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	1596	__IO uint32_t MOD; /*< Modulo, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	1597	struct { /* offset: 0xC, array step: 0x8 */
AnnaBridge	171:3a7713b1edbc	1598	__IO uint32_t CnSC; /*< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 /
AnnaBridge	171:3a7713b1edbc	1599	__IO uint32_t CnV; /*< Channel (n) Value, array offset: 0x10, array step: 0x8 /
AnnaBridge	171:3a7713b1edbc	1600	} CONTROLS[8];
AnnaBridge	171:3a7713b1edbc	1601	__IO uint32_t CNTIN; /*< Counter Initial Value, offset: 0x4C /
AnnaBridge	171:3a7713b1edbc	1602	__I uint32_t STATUS; /*< Capture and Compare Status, offset: 0x50 /
AnnaBridge	171:3a7713b1edbc	1603	__IO uint32_t MODE; /*< Features Mode Selection, offset: 0x54 /
AnnaBridge	171:3a7713b1edbc	1604	__IO uint32_t SYNC; /*< Synchronization, offset: 0x58 /
AnnaBridge	171:3a7713b1edbc	1605	__IO uint32_t OUTINIT; /*< Initial State for Channels Output, offset: 0x5C /
AnnaBridge	171:3a7713b1edbc	1606	__IO uint32_t OUTMASK; /*< Output Mask, offset: 0x60 /
AnnaBridge	171:3a7713b1edbc	1607	__IO uint32_t COMBINE; /*< Function for Linked Channels, offset: 0x64 /
AnnaBridge	171:3a7713b1edbc	1608	__IO uint32_t DEADTIME; /*< Deadtime Insertion Control, offset: 0x68 /
AnnaBridge	171:3a7713b1edbc	1609	__IO uint32_t EXTTRIG; /*< FTM External Trigger, offset: 0x6C /
AnnaBridge	171:3a7713b1edbc	1610	__IO uint32_t POL; /*< Channels Polarity, offset: 0x70 /
AnnaBridge	171:3a7713b1edbc	1611	__IO uint32_t FMS; /*< Fault Mode Status, offset: 0x74 /
AnnaBridge	171:3a7713b1edbc	1612	__IO uint32_t FILTER; /*< Input Capture Filter Control, offset: 0x78 /
AnnaBridge	171:3a7713b1edbc	1613	__IO uint32_t FLTCTRL; /*< Fault Control, offset: 0x7C /
AnnaBridge	171:3a7713b1edbc	1614	__IO uint32_t QDCTRL; /*< Quadrature Decoder Control and Status, offset: 0x80 /
AnnaBridge	171:3a7713b1edbc	1615	__IO uint32_t CONF; /*< Configuration, offset: 0x84 /
AnnaBridge	171:3a7713b1edbc	1616	__IO uint32_t FLTPOL; /*< FTM Fault Input Polarity, offset: 0x88 /
AnnaBridge	171:3a7713b1edbc	1617	__IO uint32_t SYNCONF; /*< Synchronization Configuration, offset: 0x8C /
AnnaBridge	171:3a7713b1edbc	1618	__IO uint32_t INVCTRL; /*< FTM Inverting Control, offset: 0x90 /
AnnaBridge	171:3a7713b1edbc	1619	__IO uint32_t SWOCTRL; /*< FTM Software Output Control, offset: 0x94 /
AnnaBridge	171:3a7713b1edbc	1620	__IO uint32_t PWMLOAD; /*< FTM PWM Load, offset: 0x98 /
AnnaBridge	171:3a7713b1edbc	1621	} FTM_Type;
AnnaBridge	171:3a7713b1edbc	1622
AnnaBridge	171:3a7713b1edbc	1623	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	1624	-- FTM Register Masks
AnnaBridge	171:3a7713b1edbc	1625	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	1626
AnnaBridge	171:3a7713b1edbc	1627	/**
AnnaBridge	171:3a7713b1edbc	1628	* @addtogroup FTM_Register_Masks FTM Register Masks
AnnaBridge	171:3a7713b1edbc	1629	* @{
AnnaBridge	171:3a7713b1edbc	1630	*/
AnnaBridge	171:3a7713b1edbc	1631
AnnaBridge	171:3a7713b1edbc	1632	/* SC Bit Fields */
AnnaBridge	171:3a7713b1edbc	1633	#define FTM_SC_PS_MASK 0x7u
AnnaBridge	171:3a7713b1edbc	1634	#define FTM_SC_PS_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1635	#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
AnnaBridge	171:3a7713b1edbc	1636	#define FTM_SC_CLKS_MASK 0x18u
AnnaBridge	171:3a7713b1edbc	1637	#define FTM_SC_CLKS_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1638	#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
AnnaBridge	171:3a7713b1edbc	1639	#define FTM_SC_CPWMS_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1640	#define FTM_SC_CPWMS_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1641	#define FTM_SC_TOIE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1642	#define FTM_SC_TOIE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1643	#define FTM_SC_TOF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1644	#define FTM_SC_TOF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1645	/* CNT Bit Fields */
AnnaBridge	171:3a7713b1edbc	1646	#define FTM_CNT_COUNT_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	1647	#define FTM_CNT_COUNT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1648	#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
AnnaBridge	171:3a7713b1edbc	1649	/* MOD Bit Fields */
AnnaBridge	171:3a7713b1edbc	1650	#define FTM_MOD_MOD_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	1651	#define FTM_MOD_MOD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1652	#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
AnnaBridge	171:3a7713b1edbc	1653	/* CnSC Bit Fields */
AnnaBridge	171:3a7713b1edbc	1654	#define FTM_CnSC_DMA_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1655	#define FTM_CnSC_DMA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1656	#define FTM_CnSC_ELSA_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1657	#define FTM_CnSC_ELSA_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1658	#define FTM_CnSC_ELSB_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1659	#define FTM_CnSC_ELSB_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1660	#define FTM_CnSC_MSA_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1661	#define FTM_CnSC_MSA_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1662	#define FTM_CnSC_MSB_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1663	#define FTM_CnSC_MSB_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1664	#define FTM_CnSC_CHIE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1665	#define FTM_CnSC_CHIE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1666	#define FTM_CnSC_CHF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1667	#define FTM_CnSC_CHF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1668	/* CnV Bit Fields */
AnnaBridge	171:3a7713b1edbc	1669	#define FTM_CnV_VAL_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	1670	#define FTM_CnV_VAL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1671	#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
AnnaBridge	171:3a7713b1edbc	1672	/* CNTIN Bit Fields */
AnnaBridge	171:3a7713b1edbc	1673	#define FTM_CNTIN_INIT_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	1674	#define FTM_CNTIN_INIT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1675	#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
AnnaBridge	171:3a7713b1edbc	1676	/* STATUS Bit Fields */
AnnaBridge	171:3a7713b1edbc	1677	#define FTM_STATUS_CH0F_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1678	#define FTM_STATUS_CH0F_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1679	#define FTM_STATUS_CH1F_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1680	#define FTM_STATUS_CH1F_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1681	#define FTM_STATUS_CH2F_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1682	#define FTM_STATUS_CH2F_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1683	#define FTM_STATUS_CH3F_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1684	#define FTM_STATUS_CH3F_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1685	#define FTM_STATUS_CH4F_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1686	#define FTM_STATUS_CH4F_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1687	#define FTM_STATUS_CH5F_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1688	#define FTM_STATUS_CH5F_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1689	#define FTM_STATUS_CH6F_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1690	#define FTM_STATUS_CH6F_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1691	#define FTM_STATUS_CH7F_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1692	#define FTM_STATUS_CH7F_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1693	/* MODE Bit Fields */
AnnaBridge	171:3a7713b1edbc	1694	#define FTM_MODE_FTMEN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1695	#define FTM_MODE_FTMEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1696	#define FTM_MODE_INIT_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1697	#define FTM_MODE_INIT_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1698	#define FTM_MODE_WPDIS_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1699	#define FTM_MODE_WPDIS_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1700	#define FTM_MODE_PWMSYNC_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1701	#define FTM_MODE_PWMSYNC_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1702	#define FTM_MODE_CAPTEST_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1703	#define FTM_MODE_CAPTEST_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1704	#define FTM_MODE_FAULTM_MASK 0x60u
AnnaBridge	171:3a7713b1edbc	1705	#define FTM_MODE_FAULTM_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1706	#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
AnnaBridge	171:3a7713b1edbc	1707	#define FTM_MODE_FAULTIE_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1708	#define FTM_MODE_FAULTIE_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1709	/* SYNC Bit Fields */
AnnaBridge	171:3a7713b1edbc	1710	#define FTM_SYNC_CNTMIN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1711	#define FTM_SYNC_CNTMIN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1712	#define FTM_SYNC_CNTMAX_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1713	#define FTM_SYNC_CNTMAX_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1714	#define FTM_SYNC_REINIT_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1715	#define FTM_SYNC_REINIT_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1716	#define FTM_SYNC_SYNCHOM_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1717	#define FTM_SYNC_SYNCHOM_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1718	#define FTM_SYNC_TRIG0_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1719	#define FTM_SYNC_TRIG0_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1720	#define FTM_SYNC_TRIG1_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1721	#define FTM_SYNC_TRIG1_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1722	#define FTM_SYNC_TRIG2_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1723	#define FTM_SYNC_TRIG2_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1724	#define FTM_SYNC_SWSYNC_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1725	#define FTM_SYNC_SWSYNC_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1726	/* OUTINIT Bit Fields */
AnnaBridge	171:3a7713b1edbc	1727	#define FTM_OUTINIT_CH0OI_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1728	#define FTM_OUTINIT_CH0OI_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1729	#define FTM_OUTINIT_CH1OI_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1730	#define FTM_OUTINIT_CH1OI_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1731	#define FTM_OUTINIT_CH2OI_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1732	#define FTM_OUTINIT_CH2OI_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1733	#define FTM_OUTINIT_CH3OI_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1734	#define FTM_OUTINIT_CH3OI_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1735	#define FTM_OUTINIT_CH4OI_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1736	#define FTM_OUTINIT_CH4OI_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1737	#define FTM_OUTINIT_CH5OI_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1738	#define FTM_OUTINIT_CH5OI_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1739	#define FTM_OUTINIT_CH6OI_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1740	#define FTM_OUTINIT_CH6OI_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1741	#define FTM_OUTINIT_CH7OI_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1742	#define FTM_OUTINIT_CH7OI_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1743	/* OUTMASK Bit Fields */
AnnaBridge	171:3a7713b1edbc	1744	#define FTM_OUTMASK_CH0OM_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1745	#define FTM_OUTMASK_CH0OM_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1746	#define FTM_OUTMASK_CH1OM_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1747	#define FTM_OUTMASK_CH1OM_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1748	#define FTM_OUTMASK_CH2OM_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1749	#define FTM_OUTMASK_CH2OM_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1750	#define FTM_OUTMASK_CH3OM_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1751	#define FTM_OUTMASK_CH3OM_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1752	#define FTM_OUTMASK_CH4OM_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1753	#define FTM_OUTMASK_CH4OM_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1754	#define FTM_OUTMASK_CH5OM_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1755	#define FTM_OUTMASK_CH5OM_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1756	#define FTM_OUTMASK_CH6OM_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1757	#define FTM_OUTMASK_CH6OM_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1758	#define FTM_OUTMASK_CH7OM_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1759	#define FTM_OUTMASK_CH7OM_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1760	/* COMBINE Bit Fields */
AnnaBridge	171:3a7713b1edbc	1761	#define FTM_COMBINE_COMBINE0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1762	#define FTM_COMBINE_COMBINE0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1763	#define FTM_COMBINE_COMP0_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1764	#define FTM_COMBINE_COMP0_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1765	#define FTM_COMBINE_DECAPEN0_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1766	#define FTM_COMBINE_DECAPEN0_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1767	#define FTM_COMBINE_DECAP0_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1768	#define FTM_COMBINE_DECAP0_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1769	#define FTM_COMBINE_DTEN0_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1770	#define FTM_COMBINE_DTEN0_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1771	#define FTM_COMBINE_SYNCEN0_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1772	#define FTM_COMBINE_SYNCEN0_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1773	#define FTM_COMBINE_FAULTEN0_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1774	#define FTM_COMBINE_FAULTEN0_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1775	#define FTM_COMBINE_COMBINE1_MASK 0x100u
AnnaBridge	171:3a7713b1edbc	1776	#define FTM_COMBINE_COMBINE1_SHIFT 8
AnnaBridge	171:3a7713b1edbc	1777	#define FTM_COMBINE_COMP1_MASK 0x200u
AnnaBridge	171:3a7713b1edbc	1778	#define FTM_COMBINE_COMP1_SHIFT 9
AnnaBridge	171:3a7713b1edbc	1779	#define FTM_COMBINE_DECAPEN1_MASK 0x400u
AnnaBridge	171:3a7713b1edbc	1780	#define FTM_COMBINE_DECAPEN1_SHIFT 10
AnnaBridge	171:3a7713b1edbc	1781	#define FTM_COMBINE_DECAP1_MASK 0x800u
AnnaBridge	171:3a7713b1edbc	1782	#define FTM_COMBINE_DECAP1_SHIFT 11
AnnaBridge	171:3a7713b1edbc	1783	#define FTM_COMBINE_DTEN1_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	1784	#define FTM_COMBINE_DTEN1_SHIFT 12
AnnaBridge	171:3a7713b1edbc	1785	#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
AnnaBridge	171:3a7713b1edbc	1786	#define FTM_COMBINE_SYNCEN1_SHIFT 13
AnnaBridge	171:3a7713b1edbc	1787	#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
AnnaBridge	171:3a7713b1edbc	1788	#define FTM_COMBINE_FAULTEN1_SHIFT 14
AnnaBridge	171:3a7713b1edbc	1789	#define FTM_COMBINE_COMBINE2_MASK 0x10000u
AnnaBridge	171:3a7713b1edbc	1790	#define FTM_COMBINE_COMBINE2_SHIFT 16
AnnaBridge	171:3a7713b1edbc	1791	#define FTM_COMBINE_COMP2_MASK 0x20000u
AnnaBridge	171:3a7713b1edbc	1792	#define FTM_COMBINE_COMP2_SHIFT 17
AnnaBridge	171:3a7713b1edbc	1793	#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
AnnaBridge	171:3a7713b1edbc	1794	#define FTM_COMBINE_DECAPEN2_SHIFT 18
AnnaBridge	171:3a7713b1edbc	1795	#define FTM_COMBINE_DECAP2_MASK 0x80000u
AnnaBridge	171:3a7713b1edbc	1796	#define FTM_COMBINE_DECAP2_SHIFT 19
AnnaBridge	171:3a7713b1edbc	1797	#define FTM_COMBINE_DTEN2_MASK 0x100000u
AnnaBridge	171:3a7713b1edbc	1798	#define FTM_COMBINE_DTEN2_SHIFT 20
AnnaBridge	171:3a7713b1edbc	1799	#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
AnnaBridge	171:3a7713b1edbc	1800	#define FTM_COMBINE_SYNCEN2_SHIFT 21
AnnaBridge	171:3a7713b1edbc	1801	#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
AnnaBridge	171:3a7713b1edbc	1802	#define FTM_COMBINE_FAULTEN2_SHIFT 22
AnnaBridge	171:3a7713b1edbc	1803	#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	1804	#define FTM_COMBINE_COMBINE3_SHIFT 24
AnnaBridge	171:3a7713b1edbc	1805	#define FTM_COMBINE_COMP3_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	1806	#define FTM_COMBINE_COMP3_SHIFT 25
AnnaBridge	171:3a7713b1edbc	1807	#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
AnnaBridge	171:3a7713b1edbc	1808	#define FTM_COMBINE_DECAPEN3_SHIFT 26
AnnaBridge	171:3a7713b1edbc	1809	#define FTM_COMBINE_DECAP3_MASK 0x8000000u
AnnaBridge	171:3a7713b1edbc	1810	#define FTM_COMBINE_DECAP3_SHIFT 27
AnnaBridge	171:3a7713b1edbc	1811	#define FTM_COMBINE_DTEN3_MASK 0x10000000u
AnnaBridge	171:3a7713b1edbc	1812	#define FTM_COMBINE_DTEN3_SHIFT 28
AnnaBridge	171:3a7713b1edbc	1813	#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
AnnaBridge	171:3a7713b1edbc	1814	#define FTM_COMBINE_SYNCEN3_SHIFT 29
AnnaBridge	171:3a7713b1edbc	1815	#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
AnnaBridge	171:3a7713b1edbc	1816	#define FTM_COMBINE_FAULTEN3_SHIFT 30
AnnaBridge	171:3a7713b1edbc	1817	/* DEADTIME Bit Fields */
AnnaBridge	171:3a7713b1edbc	1818	#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	1819	#define FTM_DEADTIME_DTVAL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1820	#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
AnnaBridge	171:3a7713b1edbc	1821	#define FTM_DEADTIME_DTPS_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	1822	#define FTM_DEADTIME_DTPS_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1823	#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
AnnaBridge	171:3a7713b1edbc	1824	/* EXTTRIG Bit Fields */
AnnaBridge	171:3a7713b1edbc	1825	#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1826	#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1827	#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1828	#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1829	#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1830	#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1831	#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1832	#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1833	#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1834	#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1835	#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1836	#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1837	#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1838	#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1839	#define FTM_EXTTRIG_TRIGF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1840	#define FTM_EXTTRIG_TRIGF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1841	/* POL Bit Fields */
AnnaBridge	171:3a7713b1edbc	1842	#define FTM_POL_POL0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1843	#define FTM_POL_POL0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1844	#define FTM_POL_POL1_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1845	#define FTM_POL_POL1_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1846	#define FTM_POL_POL2_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1847	#define FTM_POL_POL2_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1848	#define FTM_POL_POL3_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1849	#define FTM_POL_POL3_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1850	#define FTM_POL_POL4_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1851	#define FTM_POL_POL4_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1852	#define FTM_POL_POL5_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1853	#define FTM_POL_POL5_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1854	#define FTM_POL_POL6_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1855	#define FTM_POL_POL6_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1856	#define FTM_POL_POL7_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1857	#define FTM_POL_POL7_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1858	/* FMS Bit Fields */
AnnaBridge	171:3a7713b1edbc	1859	#define FTM_FMS_FAULTF0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1860	#define FTM_FMS_FAULTF0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1861	#define FTM_FMS_FAULTF1_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1862	#define FTM_FMS_FAULTF1_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1863	#define FTM_FMS_FAULTF2_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1864	#define FTM_FMS_FAULTF2_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1865	#define FTM_FMS_FAULTF3_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1866	#define FTM_FMS_FAULTF3_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1867	#define FTM_FMS_FAULTIN_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1868	#define FTM_FMS_FAULTIN_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1869	#define FTM_FMS_WPEN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1870	#define FTM_FMS_WPEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1871	#define FTM_FMS_FAULTF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1872	#define FTM_FMS_FAULTF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1873	/* FILTER Bit Fields */
AnnaBridge	171:3a7713b1edbc	1874	#define FTM_FILTER_CH0FVAL_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	1875	#define FTM_FILTER_CH0FVAL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1876	#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
AnnaBridge	171:3a7713b1edbc	1877	#define FTM_FILTER_CH1FVAL_MASK 0xF0u
AnnaBridge	171:3a7713b1edbc	1878	#define FTM_FILTER_CH1FVAL_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1879	#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
AnnaBridge	171:3a7713b1edbc	1880	#define FTM_FILTER_CH2FVAL_MASK 0xF00u
AnnaBridge	171:3a7713b1edbc	1881	#define FTM_FILTER_CH2FVAL_SHIFT 8
AnnaBridge	171:3a7713b1edbc	1882	#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
AnnaBridge	171:3a7713b1edbc	1883	#define FTM_FILTER_CH3FVAL_MASK 0xF000u
AnnaBridge	171:3a7713b1edbc	1884	#define FTM_FILTER_CH3FVAL_SHIFT 12
AnnaBridge	171:3a7713b1edbc	1885	#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
AnnaBridge	171:3a7713b1edbc	1886	/* FLTCTRL Bit Fields */
AnnaBridge	171:3a7713b1edbc	1887	#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1888	#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1889	#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1890	#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1891	#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1892	#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1893	#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1894	#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1895	#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1896	#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1897	#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1898	#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1899	#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1900	#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1901	#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1902	#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1903	#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
AnnaBridge	171:3a7713b1edbc	1904	#define FTM_FLTCTRL_FFVAL_SHIFT 8
AnnaBridge	171:3a7713b1edbc	1905	#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
AnnaBridge	171:3a7713b1edbc	1906	/* QDCTRL Bit Fields */
AnnaBridge	171:3a7713b1edbc	1907	#define FTM_QDCTRL_QUADEN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1908	#define FTM_QDCTRL_QUADEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1909	#define FTM_QDCTRL_TOFDIR_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1910	#define FTM_QDCTRL_TOFDIR_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1911	#define FTM_QDCTRL_QUADIR_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1912	#define FTM_QDCTRL_QUADIR_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1913	#define FTM_QDCTRL_QUADMODE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1914	#define FTM_QDCTRL_QUADMODE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1915	#define FTM_QDCTRL_PHBPOL_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1916	#define FTM_QDCTRL_PHBPOL_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1917	#define FTM_QDCTRL_PHAPOL_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1918	#define FTM_QDCTRL_PHAPOL_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1919	#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1920	#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1921	#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1922	#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1923	/* CONF Bit Fields */
AnnaBridge	171:3a7713b1edbc	1924	#define FTM_CONF_NUMTOF_MASK 0x1Fu
AnnaBridge	171:3a7713b1edbc	1925	#define FTM_CONF_NUMTOF_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1926	#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
AnnaBridge	171:3a7713b1edbc	1927	#define FTM_CONF_BDMMODE_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	1928	#define FTM_CONF_BDMMODE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1929	#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
AnnaBridge	171:3a7713b1edbc	1930	#define FTM_CONF_GTBEEN_MASK 0x200u
AnnaBridge	171:3a7713b1edbc	1931	#define FTM_CONF_GTBEEN_SHIFT 9
AnnaBridge	171:3a7713b1edbc	1932	#define FTM_CONF_GTBEOUT_MASK 0x400u
AnnaBridge	171:3a7713b1edbc	1933	#define FTM_CONF_GTBEOUT_SHIFT 10
AnnaBridge	171:3a7713b1edbc	1934	/* FLTPOL Bit Fields */
AnnaBridge	171:3a7713b1edbc	1935	#define FTM_FLTPOL_FLT0POL_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1936	#define FTM_FLTPOL_FLT0POL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1937	#define FTM_FLTPOL_FLT1POL_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1938	#define FTM_FLTPOL_FLT1POL_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1939	#define FTM_FLTPOL_FLT2POL_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1940	#define FTM_FLTPOL_FLT2POL_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1941	#define FTM_FLTPOL_FLT3POL_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1942	#define FTM_FLTPOL_FLT3POL_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1943	/* SYNCONF Bit Fields */
AnnaBridge	171:3a7713b1edbc	1944	#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1945	#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1946	#define FTM_SYNCONF_CNTINC_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1947	#define FTM_SYNCONF_CNTINC_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1948	#define FTM_SYNCONF_INVC_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1949	#define FTM_SYNCONF_INVC_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1950	#define FTM_SYNCONF_SWOC_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1951	#define FTM_SYNCONF_SWOC_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1952	#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1953	#define FTM_SYNCONF_SYNCMODE_SHIFT 7
AnnaBridge	171:3a7713b1edbc	1954	#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
AnnaBridge	171:3a7713b1edbc	1955	#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
AnnaBridge	171:3a7713b1edbc	1956	#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
AnnaBridge	171:3a7713b1edbc	1957	#define FTM_SYNCONF_SWWRBUF_SHIFT 9
AnnaBridge	171:3a7713b1edbc	1958	#define FTM_SYNCONF_SWOM_MASK 0x400u
AnnaBridge	171:3a7713b1edbc	1959	#define FTM_SYNCONF_SWOM_SHIFT 10
AnnaBridge	171:3a7713b1edbc	1960	#define FTM_SYNCONF_SWINVC_MASK 0x800u
AnnaBridge	171:3a7713b1edbc	1961	#define FTM_SYNCONF_SWINVC_SHIFT 11
AnnaBridge	171:3a7713b1edbc	1962	#define FTM_SYNCONF_SWSOC_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	1963	#define FTM_SYNCONF_SWSOC_SHIFT 12
AnnaBridge	171:3a7713b1edbc	1964	#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
AnnaBridge	171:3a7713b1edbc	1965	#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
AnnaBridge	171:3a7713b1edbc	1966	#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
AnnaBridge	171:3a7713b1edbc	1967	#define FTM_SYNCONF_HWWRBUF_SHIFT 17
AnnaBridge	171:3a7713b1edbc	1968	#define FTM_SYNCONF_HWOM_MASK 0x40000u
AnnaBridge	171:3a7713b1edbc	1969	#define FTM_SYNCONF_HWOM_SHIFT 18
AnnaBridge	171:3a7713b1edbc	1970	#define FTM_SYNCONF_HWINVC_MASK 0x80000u
AnnaBridge	171:3a7713b1edbc	1971	#define FTM_SYNCONF_HWINVC_SHIFT 19
AnnaBridge	171:3a7713b1edbc	1972	#define FTM_SYNCONF_HWSOC_MASK 0x100000u
AnnaBridge	171:3a7713b1edbc	1973	#define FTM_SYNCONF_HWSOC_SHIFT 20
AnnaBridge	171:3a7713b1edbc	1974	/* INVCTRL Bit Fields */
AnnaBridge	171:3a7713b1edbc	1975	#define FTM_INVCTRL_INV0EN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1976	#define FTM_INVCTRL_INV0EN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1977	#define FTM_INVCTRL_INV1EN_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1978	#define FTM_INVCTRL_INV1EN_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1979	#define FTM_INVCTRL_INV2EN_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1980	#define FTM_INVCTRL_INV2EN_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1981	#define FTM_INVCTRL_INV3EN_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1982	#define FTM_INVCTRL_INV3EN_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1983	/* SWOCTRL Bit Fields */
AnnaBridge	171:3a7713b1edbc	1984	#define FTM_SWOCTRL_CH0OC_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	1985	#define FTM_SWOCTRL_CH0OC_SHIFT 0
AnnaBridge	171:3a7713b1edbc	1986	#define FTM_SWOCTRL_CH1OC_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	1987	#define FTM_SWOCTRL_CH1OC_SHIFT 1
AnnaBridge	171:3a7713b1edbc	1988	#define FTM_SWOCTRL_CH2OC_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	1989	#define FTM_SWOCTRL_CH2OC_SHIFT 2
AnnaBridge	171:3a7713b1edbc	1990	#define FTM_SWOCTRL_CH3OC_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	1991	#define FTM_SWOCTRL_CH3OC_SHIFT 3
AnnaBridge	171:3a7713b1edbc	1992	#define FTM_SWOCTRL_CH4OC_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	1993	#define FTM_SWOCTRL_CH4OC_SHIFT 4
AnnaBridge	171:3a7713b1edbc	1994	#define FTM_SWOCTRL_CH5OC_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	1995	#define FTM_SWOCTRL_CH5OC_SHIFT 5
AnnaBridge	171:3a7713b1edbc	1996	#define FTM_SWOCTRL_CH6OC_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	1997	#define FTM_SWOCTRL_CH6OC_SHIFT 6
AnnaBridge	171:3a7713b1edbc	1998	#define FTM_SWOCTRL_CH7OC_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	1999	#define FTM_SWOCTRL_CH7OC_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2000	#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
AnnaBridge	171:3a7713b1edbc	2001	#define FTM_SWOCTRL_CH0OCV_SHIFT 8
AnnaBridge	171:3a7713b1edbc	2002	#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
AnnaBridge	171:3a7713b1edbc	2003	#define FTM_SWOCTRL_CH1OCV_SHIFT 9
AnnaBridge	171:3a7713b1edbc	2004	#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
AnnaBridge	171:3a7713b1edbc	2005	#define FTM_SWOCTRL_CH2OCV_SHIFT 10
AnnaBridge	171:3a7713b1edbc	2006	#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
AnnaBridge	171:3a7713b1edbc	2007	#define FTM_SWOCTRL_CH3OCV_SHIFT 11
AnnaBridge	171:3a7713b1edbc	2008	#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	2009	#define FTM_SWOCTRL_CH4OCV_SHIFT 12
AnnaBridge	171:3a7713b1edbc	2010	#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
AnnaBridge	171:3a7713b1edbc	2011	#define FTM_SWOCTRL_CH5OCV_SHIFT 13
AnnaBridge	171:3a7713b1edbc	2012	#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
AnnaBridge	171:3a7713b1edbc	2013	#define FTM_SWOCTRL_CH6OCV_SHIFT 14
AnnaBridge	171:3a7713b1edbc	2014	#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
AnnaBridge	171:3a7713b1edbc	2015	#define FTM_SWOCTRL_CH7OCV_SHIFT 15
AnnaBridge	171:3a7713b1edbc	2016	/* PWMLOAD Bit Fields */
AnnaBridge	171:3a7713b1edbc	2017	#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2018	#define FTM_PWMLOAD_CH0SEL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2019	#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2020	#define FTM_PWMLOAD_CH1SEL_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2021	#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	2022	#define FTM_PWMLOAD_CH2SEL_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2023	#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2024	#define FTM_PWMLOAD_CH3SEL_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2025	#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2026	#define FTM_PWMLOAD_CH4SEL_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2027	#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2028	#define FTM_PWMLOAD_CH5SEL_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2029	#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2030	#define FTM_PWMLOAD_CH6SEL_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2031	#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2032	#define FTM_PWMLOAD_CH7SEL_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2033	#define FTM_PWMLOAD_LDOK_MASK 0x200u
AnnaBridge	171:3a7713b1edbc	2034	#define FTM_PWMLOAD_LDOK_SHIFT 9
AnnaBridge	171:3a7713b1edbc	2035
AnnaBridge	171:3a7713b1edbc	2036	/**
AnnaBridge	171:3a7713b1edbc	2037	* @}
AnnaBridge	171:3a7713b1edbc	2038	/ / end of group FTM_Register_Masks */
AnnaBridge	171:3a7713b1edbc	2039
AnnaBridge	171:3a7713b1edbc	2040
AnnaBridge	171:3a7713b1edbc	2041	/* FTM - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	2042	/** Peripheral FTM0 base address */
AnnaBridge	171:3a7713b1edbc	2043	#define FTM0_BASE (0x40038000u)
AnnaBridge	171:3a7713b1edbc	2044	/** Peripheral FTM0 base pointer */
AnnaBridge	171:3a7713b1edbc	2045	#define FTM0 ((FTM_Type *)FTM0_BASE)
AnnaBridge	171:3a7713b1edbc	2046	/** Peripheral FTM1 base address */
AnnaBridge	171:3a7713b1edbc	2047	#define FTM1_BASE (0x40039000u)
AnnaBridge	171:3a7713b1edbc	2048	/** Peripheral FTM1 base pointer */
AnnaBridge	171:3a7713b1edbc	2049	#define FTM1 ((FTM_Type *)FTM1_BASE)
AnnaBridge	171:3a7713b1edbc	2050
AnnaBridge	171:3a7713b1edbc	2051	/**
AnnaBridge	171:3a7713b1edbc	2052	* @}
AnnaBridge	171:3a7713b1edbc	2053	/ / end of group FTM_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	2054
AnnaBridge	171:3a7713b1edbc	2055
AnnaBridge	171:3a7713b1edbc	2056	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2057	-- GPIO Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	2058	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	2059
AnnaBridge	171:3a7713b1edbc	2060	/**
AnnaBridge	171:3a7713b1edbc	2061	* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	2062	* @{
AnnaBridge	171:3a7713b1edbc	2063	*/
AnnaBridge	171:3a7713b1edbc	2064
AnnaBridge	171:3a7713b1edbc	2065	/** GPIO - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	2066	typedef struct {
AnnaBridge	171:3a7713b1edbc	2067	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	2068	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	2069	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	2070	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	2071	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
AnnaBridge	171:3a7713b1edbc	2072	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
AnnaBridge	171:3a7713b1edbc	2073	} GPIO_Type;
AnnaBridge	171:3a7713b1edbc	2074
AnnaBridge	171:3a7713b1edbc	2075	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2076	-- GPIO Register Masks
AnnaBridge	171:3a7713b1edbc	2077	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	2078
AnnaBridge	171:3a7713b1edbc	2079	/**
AnnaBridge	171:3a7713b1edbc	2080	* @addtogroup GPIO_Register_Masks GPIO Register Masks
AnnaBridge	171:3a7713b1edbc	2081	* @{
AnnaBridge	171:3a7713b1edbc	2082	*/
AnnaBridge	171:3a7713b1edbc	2083
AnnaBridge	171:3a7713b1edbc	2084	/* PDOR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2085	#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	2086	#define GPIO_PDOR_PDO_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2087	#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
AnnaBridge	171:3a7713b1edbc	2088	/* PSOR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2089	#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	2090	#define GPIO_PSOR_PTSO_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2091	#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
AnnaBridge	171:3a7713b1edbc	2092	/* PCOR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2093	#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	2094	#define GPIO_PCOR_PTCO_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2095	#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
AnnaBridge	171:3a7713b1edbc	2096	/* PTOR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2097	#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	2098	#define GPIO_PTOR_PTTO_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2099	#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
AnnaBridge	171:3a7713b1edbc	2100	/* PDIR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2101	#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	2102	#define GPIO_PDIR_PDI_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2103	#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
AnnaBridge	171:3a7713b1edbc	2104	/* PDDR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2105	#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	2106	#define GPIO_PDDR_PDD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2107	#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
AnnaBridge	171:3a7713b1edbc	2108
AnnaBridge	171:3a7713b1edbc	2109	/**
AnnaBridge	171:3a7713b1edbc	2110	* @}
AnnaBridge	171:3a7713b1edbc	2111	/ / end of group GPIO_Register_Masks */
AnnaBridge	171:3a7713b1edbc	2112
AnnaBridge	171:3a7713b1edbc	2113
AnnaBridge	171:3a7713b1edbc	2114	/* GPIO - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	2115	/** Peripheral PTA base address */
AnnaBridge	171:3a7713b1edbc	2116	#define PTA_BASE (0x400FF000u)
AnnaBridge	171:3a7713b1edbc	2117	/** Peripheral PTA base pointer */
AnnaBridge	171:3a7713b1edbc	2118	#define PTA ((GPIO_Type *)PTA_BASE)
AnnaBridge	171:3a7713b1edbc	2119	/** Peripheral PTB base address */
AnnaBridge	171:3a7713b1edbc	2120	#define PTB_BASE (0x400FF040u)
AnnaBridge	171:3a7713b1edbc	2121	/** Peripheral PTB base pointer */
AnnaBridge	171:3a7713b1edbc	2122	#define PTB ((GPIO_Type *)PTB_BASE)
AnnaBridge	171:3a7713b1edbc	2123	/** Peripheral PTC base address */
AnnaBridge	171:3a7713b1edbc	2124	#define PTC_BASE (0x400FF080u)
AnnaBridge	171:3a7713b1edbc	2125	/** Peripheral PTC base pointer */
AnnaBridge	171:3a7713b1edbc	2126	#define PTC ((GPIO_Type *)PTC_BASE)
AnnaBridge	171:3a7713b1edbc	2127	/** Peripheral PTD base address */
AnnaBridge	171:3a7713b1edbc	2128	#define PTD_BASE (0x400FF0C0u)
AnnaBridge	171:3a7713b1edbc	2129	/** Peripheral PTD base pointer */
AnnaBridge	171:3a7713b1edbc	2130	#define PTD ((GPIO_Type *)PTD_BASE)
AnnaBridge	171:3a7713b1edbc	2131	/** Peripheral PTE base address */
AnnaBridge	171:3a7713b1edbc	2132	#define PTE_BASE (0x400FF100u)
AnnaBridge	171:3a7713b1edbc	2133	/** Peripheral PTE base pointer */
AnnaBridge	171:3a7713b1edbc	2134	#define PTE ((GPIO_Type *)PTE_BASE)
AnnaBridge	171:3a7713b1edbc	2135
AnnaBridge	171:3a7713b1edbc	2136	/**
AnnaBridge	171:3a7713b1edbc	2137	* @}
AnnaBridge	171:3a7713b1edbc	2138	/ / end of group GPIO_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	2139
AnnaBridge	171:3a7713b1edbc	2140
AnnaBridge	171:3a7713b1edbc	2141	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2142	-- I2C Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	2143	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	2144
AnnaBridge	171:3a7713b1edbc	2145	/**
AnnaBridge	171:3a7713b1edbc	2146	* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	2147	* @{
AnnaBridge	171:3a7713b1edbc	2148	*/
AnnaBridge	171:3a7713b1edbc	2149
AnnaBridge	171:3a7713b1edbc	2150	/** I2C - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	2151	typedef struct {
AnnaBridge	171:3a7713b1edbc	2152	__IO uint8_t A1; /*< I2C Address Register 1, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	2153	__IO uint8_t F; /*< I2C Frequency Divider register, offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	2154	__IO uint8_t C1; /*< I2C Control Register 1, offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	2155	__IO uint8_t S; /*< I2C Status Register, offset: 0x3 /
AnnaBridge	171:3a7713b1edbc	2156	__IO uint8_t D; /*< I2C Data I/O register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	2157	__IO uint8_t C2; /*< I2C Control Register 2, offset: 0x5 /
AnnaBridge	171:3a7713b1edbc	2158	__IO uint8_t FLT; /*< I2C Programmable Input Glitch Filter register, offset: 0x6 /
AnnaBridge	171:3a7713b1edbc	2159	__IO uint8_t RA; /*< I2C Range Address register, offset: 0x7 /
AnnaBridge	171:3a7713b1edbc	2160	__IO uint8_t SMB; /*< I2C SMBus Control and Status register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	2161	__IO uint8_t A2; /*< I2C Address Register 2, offset: 0x9 /
AnnaBridge	171:3a7713b1edbc	2162	__IO uint8_t SLTH; /*< I2C SCL Low Timeout Register High, offset: 0xA /
AnnaBridge	171:3a7713b1edbc	2163	__IO uint8_t SLTL; /*< I2C SCL Low Timeout Register Low, offset: 0xB /
AnnaBridge	171:3a7713b1edbc	2164	} I2C_Type;
AnnaBridge	171:3a7713b1edbc	2165
AnnaBridge	171:3a7713b1edbc	2166	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2167	-- I2C Register Masks
AnnaBridge	171:3a7713b1edbc	2168	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	2169
AnnaBridge	171:3a7713b1edbc	2170	/**
AnnaBridge	171:3a7713b1edbc	2171	* @addtogroup I2C_Register_Masks I2C Register Masks
AnnaBridge	171:3a7713b1edbc	2172	* @{
AnnaBridge	171:3a7713b1edbc	2173	*/
AnnaBridge	171:3a7713b1edbc	2174
AnnaBridge	171:3a7713b1edbc	2175	/* A1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2176	#define I2C_A1_AD_MASK 0xFEu
AnnaBridge	171:3a7713b1edbc	2177	#define I2C_A1_AD_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2178	#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
AnnaBridge	171:3a7713b1edbc	2179	/* F Bit Fields */
AnnaBridge	171:3a7713b1edbc	2180	#define I2C_F_ICR_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	2181	#define I2C_F_ICR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2182	#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
AnnaBridge	171:3a7713b1edbc	2183	#define I2C_F_MULT_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	2184	#define I2C_F_MULT_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2185	#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
AnnaBridge	171:3a7713b1edbc	2186	/* C1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2187	#define I2C_C1_DMAEN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2188	#define I2C_C1_DMAEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2189	#define I2C_C1_WUEN_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2190	#define I2C_C1_WUEN_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2191	#define I2C_C1_RSTA_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	2192	#define I2C_C1_RSTA_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2193	#define I2C_C1_TXAK_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2194	#define I2C_C1_TXAK_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2195	#define I2C_C1_TX_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2196	#define I2C_C1_TX_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2197	#define I2C_C1_MST_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2198	#define I2C_C1_MST_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2199	#define I2C_C1_IICIE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2200	#define I2C_C1_IICIE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2201	#define I2C_C1_IICEN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2202	#define I2C_C1_IICEN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2203	/* S Bit Fields */
AnnaBridge	171:3a7713b1edbc	2204	#define I2C_S_RXAK_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2205	#define I2C_S_RXAK_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2206	#define I2C_S_IICIF_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2207	#define I2C_S_IICIF_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2208	#define I2C_S_SRW_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	2209	#define I2C_S_SRW_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2210	#define I2C_S_RAM_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2211	#define I2C_S_RAM_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2212	#define I2C_S_ARBL_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2213	#define I2C_S_ARBL_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2214	#define I2C_S_BUSY_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2215	#define I2C_S_BUSY_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2216	#define I2C_S_IAAS_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2217	#define I2C_S_IAAS_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2218	#define I2C_S_TCF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2219	#define I2C_S_TCF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2220	/* D Bit Fields */
AnnaBridge	171:3a7713b1edbc	2221	#define I2C_D_DATA_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	2222	#define I2C_D_DATA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2223	#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
AnnaBridge	171:3a7713b1edbc	2224	/* C2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2225	#define I2C_C2_AD_MASK 0x7u
AnnaBridge	171:3a7713b1edbc	2226	#define I2C_C2_AD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2227	#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
AnnaBridge	171:3a7713b1edbc	2228	#define I2C_C2_RMEN_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2229	#define I2C_C2_RMEN_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2230	#define I2C_C2_SBRC_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2231	#define I2C_C2_SBRC_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2232	#define I2C_C2_HDRS_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2233	#define I2C_C2_HDRS_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2234	#define I2C_C2_ADEXT_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2235	#define I2C_C2_ADEXT_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2236	#define I2C_C2_GCAEN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2237	#define I2C_C2_GCAEN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2238	/* FLT Bit Fields */
AnnaBridge	171:3a7713b1edbc	2239	#define I2C_FLT_FLT_MASK 0x1Fu
AnnaBridge	171:3a7713b1edbc	2240	#define I2C_FLT_FLT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2241	#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
AnnaBridge	171:3a7713b1edbc	2242	/* RA Bit Fields */
AnnaBridge	171:3a7713b1edbc	2243	#define I2C_RA_RAD_MASK 0xFEu
AnnaBridge	171:3a7713b1edbc	2244	#define I2C_RA_RAD_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2245	#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
AnnaBridge	171:3a7713b1edbc	2246	/* SMB Bit Fields */
AnnaBridge	171:3a7713b1edbc	2247	#define I2C_SMB_SHTF2IE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2248	#define I2C_SMB_SHTF2IE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2249	#define I2C_SMB_SHTF2_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2250	#define I2C_SMB_SHTF2_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2251	#define I2C_SMB_SHTF1_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	2252	#define I2C_SMB_SHTF1_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2253	#define I2C_SMB_SLTF_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2254	#define I2C_SMB_SLTF_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2255	#define I2C_SMB_TCKSEL_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2256	#define I2C_SMB_TCKSEL_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2257	#define I2C_SMB_SIICAEN_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2258	#define I2C_SMB_SIICAEN_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2259	#define I2C_SMB_ALERTEN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2260	#define I2C_SMB_ALERTEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2261	#define I2C_SMB_FACK_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2262	#define I2C_SMB_FACK_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2263	/* A2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2264	#define I2C_A2_SAD_MASK 0xFEu
AnnaBridge	171:3a7713b1edbc	2265	#define I2C_A2_SAD_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2266	#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
AnnaBridge	171:3a7713b1edbc	2267	/* SLTH Bit Fields */
AnnaBridge	171:3a7713b1edbc	2268	#define I2C_SLTH_SSLT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	2269	#define I2C_SLTH_SSLT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2270	#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
AnnaBridge	171:3a7713b1edbc	2271	/* SLTL Bit Fields */
AnnaBridge	171:3a7713b1edbc	2272	#define I2C_SLTL_SSLT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	2273	#define I2C_SLTL_SSLT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2274	#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
AnnaBridge	171:3a7713b1edbc	2275
AnnaBridge	171:3a7713b1edbc	2276	/**
AnnaBridge	171:3a7713b1edbc	2277	* @}
AnnaBridge	171:3a7713b1edbc	2278	/ / end of group I2C_Register_Masks */
AnnaBridge	171:3a7713b1edbc	2279
AnnaBridge	171:3a7713b1edbc	2280
AnnaBridge	171:3a7713b1edbc	2281	/* I2C - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	2282	/** Peripheral I2C0 base address */
AnnaBridge	171:3a7713b1edbc	2283	#define I2C0_BASE (0x40066000u)
AnnaBridge	171:3a7713b1edbc	2284	/** Peripheral I2C0 base pointer */
AnnaBridge	171:3a7713b1edbc	2285	#define I2C0 ((I2C_Type *)I2C0_BASE)
AnnaBridge	171:3a7713b1edbc	2286
AnnaBridge	171:3a7713b1edbc	2287	/**
AnnaBridge	171:3a7713b1edbc	2288	* @}
AnnaBridge	171:3a7713b1edbc	2289	/ / end of group I2C_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	2290
AnnaBridge	171:3a7713b1edbc	2291
AnnaBridge	171:3a7713b1edbc	2292	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2293	-- I2S Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	2294	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	2295
AnnaBridge	171:3a7713b1edbc	2296	/**
AnnaBridge	171:3a7713b1edbc	2297	* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	2298	* @{
AnnaBridge	171:3a7713b1edbc	2299	*/
AnnaBridge	171:3a7713b1edbc	2300
AnnaBridge	171:3a7713b1edbc	2301	/** I2S - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	2302	typedef struct {
AnnaBridge	171:3a7713b1edbc	2303	__IO uint32_t TCSR; /*< SAI Transmit Control Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	2304	__IO uint32_t TCR1; /*< SAI Transmit Configuration 1 Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	2305	__IO uint32_t TCR2; /*< SAI Transmit Configuration 2 Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	2306	__IO uint32_t TCR3; /*< SAI Transmit Configuration 3 Register, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	2307	__IO uint32_t TCR4; /*< SAI Transmit Configuration 4 Register, offset: 0x10 /
AnnaBridge	171:3a7713b1edbc	2308	__IO uint32_t TCR5; /*< SAI Transmit Configuration 5 Register, offset: 0x14 /
AnnaBridge	171:3a7713b1edbc	2309	uint8_t RESERVED_0[8];
AnnaBridge	171:3a7713b1edbc	2310	__O uint32_t TDR[2]; /*< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	2311	uint8_t RESERVED_1[24];
AnnaBridge	171:3a7713b1edbc	2312	__I uint32_t TFR[2]; /*< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	2313	uint8_t RESERVED_2[24];
AnnaBridge	171:3a7713b1edbc	2314	__IO uint32_t TMR; /*< SAI Transmit Mask Register, offset: 0x60 /
AnnaBridge	171:3a7713b1edbc	2315	uint8_t RESERVED_3[28];
AnnaBridge	171:3a7713b1edbc	2316	__IO uint32_t RCSR; /*< SAI Receive Control Register, offset: 0x80 /
AnnaBridge	171:3a7713b1edbc	2317	__IO uint32_t RCR1; /*< SAI Receive Configuration 1 Register, offset: 0x84 /
AnnaBridge	171:3a7713b1edbc	2318	__IO uint32_t RCR2; /*< SAI Receive Configuration 2 Register, offset: 0x88 /
AnnaBridge	171:3a7713b1edbc	2319	__IO uint32_t RCR3; /*< SAI Receive Configuration 3 Register, offset: 0x8C /
AnnaBridge	171:3a7713b1edbc	2320	__IO uint32_t RCR4; /*< SAI Receive Configuration 4 Register, offset: 0x90 /
AnnaBridge	171:3a7713b1edbc	2321	__IO uint32_t RCR5; /*< SAI Receive Configuration 5 Register, offset: 0x94 /
AnnaBridge	171:3a7713b1edbc	2322	uint8_t RESERVED_4[8];
AnnaBridge	171:3a7713b1edbc	2323	__I uint32_t RDR[2]; /*< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	2324	uint8_t RESERVED_5[24];
AnnaBridge	171:3a7713b1edbc	2325	__I uint32_t RFR[2]; /*< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	2326	uint8_t RESERVED_6[24];
AnnaBridge	171:3a7713b1edbc	2327	__IO uint32_t RMR; /*< SAI Receive Mask Register, offset: 0xE0 /
AnnaBridge	171:3a7713b1edbc	2328	uint8_t RESERVED_7[28];
AnnaBridge	171:3a7713b1edbc	2329	__IO uint32_t MCR; /*< SAI MCLK Control Register, offset: 0x100 /
AnnaBridge	171:3a7713b1edbc	2330	__IO uint32_t MDR; /*< MCLK Divide Register, offset: 0x104 /
AnnaBridge	171:3a7713b1edbc	2331	} I2S_Type;
AnnaBridge	171:3a7713b1edbc	2332
AnnaBridge	171:3a7713b1edbc	2333	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2334	-- I2S Register Masks
AnnaBridge	171:3a7713b1edbc	2335	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	2336
AnnaBridge	171:3a7713b1edbc	2337	/**
AnnaBridge	171:3a7713b1edbc	2338	* @addtogroup I2S_Register_Masks I2S Register Masks
AnnaBridge	171:3a7713b1edbc	2339	* @{
AnnaBridge	171:3a7713b1edbc	2340	*/
AnnaBridge	171:3a7713b1edbc	2341
AnnaBridge	171:3a7713b1edbc	2342	/* TCSR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2343	#define I2S_TCSR_FRDE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2344	#define I2S_TCSR_FRDE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2345	#define I2S_TCSR_FWDE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2346	#define I2S_TCSR_FWDE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2347	#define I2S_TCSR_FRIE_MASK 0x100u
AnnaBridge	171:3a7713b1edbc	2348	#define I2S_TCSR_FRIE_SHIFT 8
AnnaBridge	171:3a7713b1edbc	2349	#define I2S_TCSR_FWIE_MASK 0x200u
AnnaBridge	171:3a7713b1edbc	2350	#define I2S_TCSR_FWIE_SHIFT 9
AnnaBridge	171:3a7713b1edbc	2351	#define I2S_TCSR_FEIE_MASK 0x400u
AnnaBridge	171:3a7713b1edbc	2352	#define I2S_TCSR_FEIE_SHIFT 10
AnnaBridge	171:3a7713b1edbc	2353	#define I2S_TCSR_SEIE_MASK 0x800u
AnnaBridge	171:3a7713b1edbc	2354	#define I2S_TCSR_SEIE_SHIFT 11
AnnaBridge	171:3a7713b1edbc	2355	#define I2S_TCSR_WSIE_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	2356	#define I2S_TCSR_WSIE_SHIFT 12
AnnaBridge	171:3a7713b1edbc	2357	#define I2S_TCSR_FRF_MASK 0x10000u
AnnaBridge	171:3a7713b1edbc	2358	#define I2S_TCSR_FRF_SHIFT 16
AnnaBridge	171:3a7713b1edbc	2359	#define I2S_TCSR_FWF_MASK 0x20000u
AnnaBridge	171:3a7713b1edbc	2360	#define I2S_TCSR_FWF_SHIFT 17
AnnaBridge	171:3a7713b1edbc	2361	#define I2S_TCSR_FEF_MASK 0x40000u
AnnaBridge	171:3a7713b1edbc	2362	#define I2S_TCSR_FEF_SHIFT 18
AnnaBridge	171:3a7713b1edbc	2363	#define I2S_TCSR_SEF_MASK 0x80000u
AnnaBridge	171:3a7713b1edbc	2364	#define I2S_TCSR_SEF_SHIFT 19
AnnaBridge	171:3a7713b1edbc	2365	#define I2S_TCSR_WSF_MASK 0x100000u
AnnaBridge	171:3a7713b1edbc	2366	#define I2S_TCSR_WSF_SHIFT 20
AnnaBridge	171:3a7713b1edbc	2367	#define I2S_TCSR_SR_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	2368	#define I2S_TCSR_SR_SHIFT 24
AnnaBridge	171:3a7713b1edbc	2369	#define I2S_TCSR_FR_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	2370	#define I2S_TCSR_FR_SHIFT 25
AnnaBridge	171:3a7713b1edbc	2371	#define I2S_TCSR_BCE_MASK 0x10000000u
AnnaBridge	171:3a7713b1edbc	2372	#define I2S_TCSR_BCE_SHIFT 28
AnnaBridge	171:3a7713b1edbc	2373	#define I2S_TCSR_DBGE_MASK 0x20000000u
AnnaBridge	171:3a7713b1edbc	2374	#define I2S_TCSR_DBGE_SHIFT 29
AnnaBridge	171:3a7713b1edbc	2375	#define I2S_TCSR_STOPE_MASK 0x40000000u
AnnaBridge	171:3a7713b1edbc	2376	#define I2S_TCSR_STOPE_SHIFT 30
AnnaBridge	171:3a7713b1edbc	2377	#define I2S_TCSR_TE_MASK 0x80000000u
AnnaBridge	171:3a7713b1edbc	2378	#define I2S_TCSR_TE_SHIFT 31
AnnaBridge	171:3a7713b1edbc	2379	/* TCR1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2380	#define I2S_TCR1_TFW_MASK 0x7u
AnnaBridge	171:3a7713b1edbc	2381	#define I2S_TCR1_TFW_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2382	#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
AnnaBridge	171:3a7713b1edbc	2383	/* TCR2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2384	#define I2S_TCR2_DIV_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	2385	#define I2S_TCR2_DIV_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2386	#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
AnnaBridge	171:3a7713b1edbc	2387	#define I2S_TCR2_BCD_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	2388	#define I2S_TCR2_BCD_SHIFT 24
AnnaBridge	171:3a7713b1edbc	2389	#define I2S_TCR2_BCP_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	2390	#define I2S_TCR2_BCP_SHIFT 25
AnnaBridge	171:3a7713b1edbc	2391	#define I2S_TCR2_MSEL_MASK 0xC000000u
AnnaBridge	171:3a7713b1edbc	2392	#define I2S_TCR2_MSEL_SHIFT 26
AnnaBridge	171:3a7713b1edbc	2393	#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
AnnaBridge	171:3a7713b1edbc	2394	#define I2S_TCR2_BCI_MASK 0x10000000u
AnnaBridge	171:3a7713b1edbc	2395	#define I2S_TCR2_BCI_SHIFT 28
AnnaBridge	171:3a7713b1edbc	2396	#define I2S_TCR2_BCS_MASK 0x20000000u
AnnaBridge	171:3a7713b1edbc	2397	#define I2S_TCR2_BCS_SHIFT 29
AnnaBridge	171:3a7713b1edbc	2398	#define I2S_TCR2_SYNC_MASK 0xC0000000u
AnnaBridge	171:3a7713b1edbc	2399	#define I2S_TCR2_SYNC_SHIFT 30
AnnaBridge	171:3a7713b1edbc	2400	#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
AnnaBridge	171:3a7713b1edbc	2401	/* TCR3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2402	#define I2S_TCR3_WDFL_MASK 0x1Fu
AnnaBridge	171:3a7713b1edbc	2403	#define I2S_TCR3_WDFL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2404	#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
AnnaBridge	171:3a7713b1edbc	2405	#define I2S_TCR3_TCE_MASK 0x30000u
AnnaBridge	171:3a7713b1edbc	2406	#define I2S_TCR3_TCE_SHIFT 16
AnnaBridge	171:3a7713b1edbc	2407	#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
AnnaBridge	171:3a7713b1edbc	2408	/* TCR4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2409	#define I2S_TCR4_FSD_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2410	#define I2S_TCR4_FSD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2411	#define I2S_TCR4_FSP_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2412	#define I2S_TCR4_FSP_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2413	#define I2S_TCR4_FSE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2414	#define I2S_TCR4_FSE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2415	#define I2S_TCR4_MF_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2416	#define I2S_TCR4_MF_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2417	#define I2S_TCR4_SYWD_MASK 0x1F00u
AnnaBridge	171:3a7713b1edbc	2418	#define I2S_TCR4_SYWD_SHIFT 8
AnnaBridge	171:3a7713b1edbc	2419	#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
AnnaBridge	171:3a7713b1edbc	2420	#define I2S_TCR4_FRSZ_MASK 0x1F0000u
AnnaBridge	171:3a7713b1edbc	2421	#define I2S_TCR4_FRSZ_SHIFT 16
AnnaBridge	171:3a7713b1edbc	2422	#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
AnnaBridge	171:3a7713b1edbc	2423	/* TCR5 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2424	#define I2S_TCR5_FBT_MASK 0x1F00u
AnnaBridge	171:3a7713b1edbc	2425	#define I2S_TCR5_FBT_SHIFT 8
AnnaBridge	171:3a7713b1edbc	2426	#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
AnnaBridge	171:3a7713b1edbc	2427	#define I2S_TCR5_W0W_MASK 0x1F0000u
AnnaBridge	171:3a7713b1edbc	2428	#define I2S_TCR5_W0W_SHIFT 16
AnnaBridge	171:3a7713b1edbc	2429	#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
AnnaBridge	171:3a7713b1edbc	2430	#define I2S_TCR5_WNW_MASK 0x1F000000u
AnnaBridge	171:3a7713b1edbc	2431	#define I2S_TCR5_WNW_SHIFT 24
AnnaBridge	171:3a7713b1edbc	2432	#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
AnnaBridge	171:3a7713b1edbc	2433	/* TDR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2434	#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	2435	#define I2S_TDR_TDR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2436	#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
AnnaBridge	171:3a7713b1edbc	2437	/* TFR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2438	#define I2S_TFR_RFP_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	2439	#define I2S_TFR_RFP_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2440	#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
AnnaBridge	171:3a7713b1edbc	2441	#define I2S_TFR_WFP_MASK 0xF0000u
AnnaBridge	171:3a7713b1edbc	2442	#define I2S_TFR_WFP_SHIFT 16
AnnaBridge	171:3a7713b1edbc	2443	#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
AnnaBridge	171:3a7713b1edbc	2444	/* TMR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2445	#define I2S_TMR_TWM_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	2446	#define I2S_TMR_TWM_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2447	#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
AnnaBridge	171:3a7713b1edbc	2448	/* RCSR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2449	#define I2S_RCSR_FRDE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2450	#define I2S_RCSR_FRDE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2451	#define I2S_RCSR_FWDE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2452	#define I2S_RCSR_FWDE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2453	#define I2S_RCSR_FRIE_MASK 0x100u
AnnaBridge	171:3a7713b1edbc	2454	#define I2S_RCSR_FRIE_SHIFT 8
AnnaBridge	171:3a7713b1edbc	2455	#define I2S_RCSR_FWIE_MASK 0x200u
AnnaBridge	171:3a7713b1edbc	2456	#define I2S_RCSR_FWIE_SHIFT 9
AnnaBridge	171:3a7713b1edbc	2457	#define I2S_RCSR_FEIE_MASK 0x400u
AnnaBridge	171:3a7713b1edbc	2458	#define I2S_RCSR_FEIE_SHIFT 10
AnnaBridge	171:3a7713b1edbc	2459	#define I2S_RCSR_SEIE_MASK 0x800u
AnnaBridge	171:3a7713b1edbc	2460	#define I2S_RCSR_SEIE_SHIFT 11
AnnaBridge	171:3a7713b1edbc	2461	#define I2S_RCSR_WSIE_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	2462	#define I2S_RCSR_WSIE_SHIFT 12
AnnaBridge	171:3a7713b1edbc	2463	#define I2S_RCSR_FRF_MASK 0x10000u
AnnaBridge	171:3a7713b1edbc	2464	#define I2S_RCSR_FRF_SHIFT 16
AnnaBridge	171:3a7713b1edbc	2465	#define I2S_RCSR_FWF_MASK 0x20000u
AnnaBridge	171:3a7713b1edbc	2466	#define I2S_RCSR_FWF_SHIFT 17
AnnaBridge	171:3a7713b1edbc	2467	#define I2S_RCSR_FEF_MASK 0x40000u
AnnaBridge	171:3a7713b1edbc	2468	#define I2S_RCSR_FEF_SHIFT 18
AnnaBridge	171:3a7713b1edbc	2469	#define I2S_RCSR_SEF_MASK 0x80000u
AnnaBridge	171:3a7713b1edbc	2470	#define I2S_RCSR_SEF_SHIFT 19
AnnaBridge	171:3a7713b1edbc	2471	#define I2S_RCSR_WSF_MASK 0x100000u
AnnaBridge	171:3a7713b1edbc	2472	#define I2S_RCSR_WSF_SHIFT 20
AnnaBridge	171:3a7713b1edbc	2473	#define I2S_RCSR_SR_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	2474	#define I2S_RCSR_SR_SHIFT 24
AnnaBridge	171:3a7713b1edbc	2475	#define I2S_RCSR_FR_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	2476	#define I2S_RCSR_FR_SHIFT 25
AnnaBridge	171:3a7713b1edbc	2477	#define I2S_RCSR_BCE_MASK 0x10000000u
AnnaBridge	171:3a7713b1edbc	2478	#define I2S_RCSR_BCE_SHIFT 28
AnnaBridge	171:3a7713b1edbc	2479	#define I2S_RCSR_DBGE_MASK 0x20000000u
AnnaBridge	171:3a7713b1edbc	2480	#define I2S_RCSR_DBGE_SHIFT 29
AnnaBridge	171:3a7713b1edbc	2481	#define I2S_RCSR_STOPE_MASK 0x40000000u
AnnaBridge	171:3a7713b1edbc	2482	#define I2S_RCSR_STOPE_SHIFT 30
AnnaBridge	171:3a7713b1edbc	2483	#define I2S_RCSR_RE_MASK 0x80000000u
AnnaBridge	171:3a7713b1edbc	2484	#define I2S_RCSR_RE_SHIFT 31
AnnaBridge	171:3a7713b1edbc	2485	/* RCR1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2486	#define I2S_RCR1_RFW_MASK 0x7u
AnnaBridge	171:3a7713b1edbc	2487	#define I2S_RCR1_RFW_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2488	#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
AnnaBridge	171:3a7713b1edbc	2489	/* RCR2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2490	#define I2S_RCR2_DIV_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	2491	#define I2S_RCR2_DIV_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2492	#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
AnnaBridge	171:3a7713b1edbc	2493	#define I2S_RCR2_BCD_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	2494	#define I2S_RCR2_BCD_SHIFT 24
AnnaBridge	171:3a7713b1edbc	2495	#define I2S_RCR2_BCP_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	2496	#define I2S_RCR2_BCP_SHIFT 25
AnnaBridge	171:3a7713b1edbc	2497	#define I2S_RCR2_MSEL_MASK 0xC000000u
AnnaBridge	171:3a7713b1edbc	2498	#define I2S_RCR2_MSEL_SHIFT 26
AnnaBridge	171:3a7713b1edbc	2499	#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
AnnaBridge	171:3a7713b1edbc	2500	#define I2S_RCR2_BCI_MASK 0x10000000u
AnnaBridge	171:3a7713b1edbc	2501	#define I2S_RCR2_BCI_SHIFT 28
AnnaBridge	171:3a7713b1edbc	2502	#define I2S_RCR2_BCS_MASK 0x20000000u
AnnaBridge	171:3a7713b1edbc	2503	#define I2S_RCR2_BCS_SHIFT 29
AnnaBridge	171:3a7713b1edbc	2504	#define I2S_RCR2_SYNC_MASK 0xC0000000u
AnnaBridge	171:3a7713b1edbc	2505	#define I2S_RCR2_SYNC_SHIFT 30
AnnaBridge	171:3a7713b1edbc	2506	#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
AnnaBridge	171:3a7713b1edbc	2507	/* RCR3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2508	#define I2S_RCR3_WDFL_MASK 0x1Fu
AnnaBridge	171:3a7713b1edbc	2509	#define I2S_RCR3_WDFL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2510	#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
AnnaBridge	171:3a7713b1edbc	2511	#define I2S_RCR3_RCE_MASK 0x30000u
AnnaBridge	171:3a7713b1edbc	2512	#define I2S_RCR3_RCE_SHIFT 16
AnnaBridge	171:3a7713b1edbc	2513	#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
AnnaBridge	171:3a7713b1edbc	2514	/* RCR4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2515	#define I2S_RCR4_FSD_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2516	#define I2S_RCR4_FSD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2517	#define I2S_RCR4_FSP_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2518	#define I2S_RCR4_FSP_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2519	#define I2S_RCR4_FSE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2520	#define I2S_RCR4_FSE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2521	#define I2S_RCR4_MF_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2522	#define I2S_RCR4_MF_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2523	#define I2S_RCR4_SYWD_MASK 0x1F00u
AnnaBridge	171:3a7713b1edbc	2524	#define I2S_RCR4_SYWD_SHIFT 8
AnnaBridge	171:3a7713b1edbc	2525	#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
AnnaBridge	171:3a7713b1edbc	2526	#define I2S_RCR4_FRSZ_MASK 0x1F0000u
AnnaBridge	171:3a7713b1edbc	2527	#define I2S_RCR4_FRSZ_SHIFT 16
AnnaBridge	171:3a7713b1edbc	2528	#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
AnnaBridge	171:3a7713b1edbc	2529	/* RCR5 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2530	#define I2S_RCR5_FBT_MASK 0x1F00u
AnnaBridge	171:3a7713b1edbc	2531	#define I2S_RCR5_FBT_SHIFT 8
AnnaBridge	171:3a7713b1edbc	2532	#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
AnnaBridge	171:3a7713b1edbc	2533	#define I2S_RCR5_W0W_MASK 0x1F0000u
AnnaBridge	171:3a7713b1edbc	2534	#define I2S_RCR5_W0W_SHIFT 16
AnnaBridge	171:3a7713b1edbc	2535	#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
AnnaBridge	171:3a7713b1edbc	2536	#define I2S_RCR5_WNW_MASK 0x1F000000u
AnnaBridge	171:3a7713b1edbc	2537	#define I2S_RCR5_WNW_SHIFT 24
AnnaBridge	171:3a7713b1edbc	2538	#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
AnnaBridge	171:3a7713b1edbc	2539	/* RDR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2540	#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	2541	#define I2S_RDR_RDR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2542	#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
AnnaBridge	171:3a7713b1edbc	2543	/* RFR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2544	#define I2S_RFR_RFP_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	2545	#define I2S_RFR_RFP_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2546	#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
AnnaBridge	171:3a7713b1edbc	2547	#define I2S_RFR_WFP_MASK 0xF0000u
AnnaBridge	171:3a7713b1edbc	2548	#define I2S_RFR_WFP_SHIFT 16
AnnaBridge	171:3a7713b1edbc	2549	#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
AnnaBridge	171:3a7713b1edbc	2550	/* RMR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2551	#define I2S_RMR_RWM_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	2552	#define I2S_RMR_RWM_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2553	#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
AnnaBridge	171:3a7713b1edbc	2554	/* MCR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2555	#define I2S_MCR_MICS_MASK 0x3000000u
AnnaBridge	171:3a7713b1edbc	2556	#define I2S_MCR_MICS_SHIFT 24
AnnaBridge	171:3a7713b1edbc	2557	#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
AnnaBridge	171:3a7713b1edbc	2558	#define I2S_MCR_MOE_MASK 0x40000000u
AnnaBridge	171:3a7713b1edbc	2559	#define I2S_MCR_MOE_SHIFT 30
AnnaBridge	171:3a7713b1edbc	2560	#define I2S_MCR_DUF_MASK 0x80000000u
AnnaBridge	171:3a7713b1edbc	2561	#define I2S_MCR_DUF_SHIFT 31
AnnaBridge	171:3a7713b1edbc	2562	/* MDR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2563	#define I2S_MDR_DIVIDE_MASK 0xFFFu
AnnaBridge	171:3a7713b1edbc	2564	#define I2S_MDR_DIVIDE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2565	#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
AnnaBridge	171:3a7713b1edbc	2566	#define I2S_MDR_FRACT_MASK 0xFF000u
AnnaBridge	171:3a7713b1edbc	2567	#define I2S_MDR_FRACT_SHIFT 12
AnnaBridge	171:3a7713b1edbc	2568	#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
AnnaBridge	171:3a7713b1edbc	2569
AnnaBridge	171:3a7713b1edbc	2570	/**
AnnaBridge	171:3a7713b1edbc	2571	* @}
AnnaBridge	171:3a7713b1edbc	2572	/ / end of group I2S_Register_Masks */
AnnaBridge	171:3a7713b1edbc	2573
AnnaBridge	171:3a7713b1edbc	2574
AnnaBridge	171:3a7713b1edbc	2575	/* I2S - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	2576	/** Peripheral I2S0 base address */
AnnaBridge	171:3a7713b1edbc	2577	#define I2S0_BASE (0x4002F000u)
AnnaBridge	171:3a7713b1edbc	2578	/** Peripheral I2S0 base pointer */
AnnaBridge	171:3a7713b1edbc	2579	#define I2S0 ((I2S_Type *)I2S0_BASE)
AnnaBridge	171:3a7713b1edbc	2580
AnnaBridge	171:3a7713b1edbc	2581	/**
AnnaBridge	171:3a7713b1edbc	2582	* @}
AnnaBridge	171:3a7713b1edbc	2583	/ / end of group I2S_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	2584
AnnaBridge	171:3a7713b1edbc	2585
AnnaBridge	171:3a7713b1edbc	2586	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2587	-- LLWU Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	2588	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	2589
AnnaBridge	171:3a7713b1edbc	2590	/**
AnnaBridge	171:3a7713b1edbc	2591	* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	2592	* @{
AnnaBridge	171:3a7713b1edbc	2593	*/
AnnaBridge	171:3a7713b1edbc	2594
AnnaBridge	171:3a7713b1edbc	2595	/** LLWU - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	2596	typedef struct {
AnnaBridge	171:3a7713b1edbc	2597	__IO uint8_t PE1; /*< LLWU Pin Enable 1 Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	2598	__IO uint8_t PE2; /*< LLWU Pin Enable 2 Register, offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	2599	__IO uint8_t PE3; /*< LLWU Pin Enable 3 Register, offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	2600	__IO uint8_t PE4; /*< LLWU Pin Enable 4 Register, offset: 0x3 /
AnnaBridge	171:3a7713b1edbc	2601	__IO uint8_t ME; /*< LLWU Module Enable Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	2602	__IO uint8_t F1; /*< LLWU Flag 1 Register, offset: 0x5 /
AnnaBridge	171:3a7713b1edbc	2603	__IO uint8_t F2; /*< LLWU Flag 2 Register, offset: 0x6 /
AnnaBridge	171:3a7713b1edbc	2604	__I uint8_t F3; /*< LLWU Flag 3 Register, offset: 0x7 /
AnnaBridge	171:3a7713b1edbc	2605	__IO uint8_t FILT1; /*< LLWU Pin Filter 1 Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	2606	__IO uint8_t FILT2; /*< LLWU Pin Filter 2 Register, offset: 0x9 /
AnnaBridge	171:3a7713b1edbc	2607	__IO uint8_t RST; /*< LLWU Reset Enable Register, offset: 0xA /
AnnaBridge	171:3a7713b1edbc	2608	} LLWU_Type;
AnnaBridge	171:3a7713b1edbc	2609
AnnaBridge	171:3a7713b1edbc	2610	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2611	-- LLWU Register Masks
AnnaBridge	171:3a7713b1edbc	2612	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	2613
AnnaBridge	171:3a7713b1edbc	2614	/**
AnnaBridge	171:3a7713b1edbc	2615	* @addtogroup LLWU_Register_Masks LLWU Register Masks
AnnaBridge	171:3a7713b1edbc	2616	* @{
AnnaBridge	171:3a7713b1edbc	2617	*/
AnnaBridge	171:3a7713b1edbc	2618
AnnaBridge	171:3a7713b1edbc	2619	/* PE1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2620	#define LLWU_PE1_WUPE0_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	2621	#define LLWU_PE1_WUPE0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2622	#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
AnnaBridge	171:3a7713b1edbc	2623	#define LLWU_PE1_WUPE1_MASK 0xCu
AnnaBridge	171:3a7713b1edbc	2624	#define LLWU_PE1_WUPE1_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2625	#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
AnnaBridge	171:3a7713b1edbc	2626	#define LLWU_PE1_WUPE2_MASK 0x30u
AnnaBridge	171:3a7713b1edbc	2627	#define LLWU_PE1_WUPE2_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2628	#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
AnnaBridge	171:3a7713b1edbc	2629	#define LLWU_PE1_WUPE3_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	2630	#define LLWU_PE1_WUPE3_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2631	#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
AnnaBridge	171:3a7713b1edbc	2632	/* PE2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2633	#define LLWU_PE2_WUPE4_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	2634	#define LLWU_PE2_WUPE4_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2635	#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
AnnaBridge	171:3a7713b1edbc	2636	#define LLWU_PE2_WUPE5_MASK 0xCu
AnnaBridge	171:3a7713b1edbc	2637	#define LLWU_PE2_WUPE5_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2638	#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
AnnaBridge	171:3a7713b1edbc	2639	#define LLWU_PE2_WUPE6_MASK 0x30u
AnnaBridge	171:3a7713b1edbc	2640	#define LLWU_PE2_WUPE6_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2641	#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
AnnaBridge	171:3a7713b1edbc	2642	#define LLWU_PE2_WUPE7_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	2643	#define LLWU_PE2_WUPE7_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2644	#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
AnnaBridge	171:3a7713b1edbc	2645	/* PE3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2646	#define LLWU_PE3_WUPE8_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	2647	#define LLWU_PE3_WUPE8_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2648	#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
AnnaBridge	171:3a7713b1edbc	2649	#define LLWU_PE3_WUPE9_MASK 0xCu
AnnaBridge	171:3a7713b1edbc	2650	#define LLWU_PE3_WUPE9_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2651	#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
AnnaBridge	171:3a7713b1edbc	2652	#define LLWU_PE3_WUPE10_MASK 0x30u
AnnaBridge	171:3a7713b1edbc	2653	#define LLWU_PE3_WUPE10_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2654	#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
AnnaBridge	171:3a7713b1edbc	2655	#define LLWU_PE3_WUPE11_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	2656	#define LLWU_PE3_WUPE11_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2657	#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
AnnaBridge	171:3a7713b1edbc	2658	/* PE4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2659	#define LLWU_PE4_WUPE12_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	2660	#define LLWU_PE4_WUPE12_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2661	#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
AnnaBridge	171:3a7713b1edbc	2662	#define LLWU_PE4_WUPE13_MASK 0xCu
AnnaBridge	171:3a7713b1edbc	2663	#define LLWU_PE4_WUPE13_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2664	#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
AnnaBridge	171:3a7713b1edbc	2665	#define LLWU_PE4_WUPE14_MASK 0x30u
AnnaBridge	171:3a7713b1edbc	2666	#define LLWU_PE4_WUPE14_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2667	#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
AnnaBridge	171:3a7713b1edbc	2668	#define LLWU_PE4_WUPE15_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	2669	#define LLWU_PE4_WUPE15_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2670	#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
AnnaBridge	171:3a7713b1edbc	2671	/* ME Bit Fields */
AnnaBridge	171:3a7713b1edbc	2672	#define LLWU_ME_WUME0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2673	#define LLWU_ME_WUME0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2674	#define LLWU_ME_WUME1_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2675	#define LLWU_ME_WUME1_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2676	#define LLWU_ME_WUME2_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	2677	#define LLWU_ME_WUME2_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2678	#define LLWU_ME_WUME3_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2679	#define LLWU_ME_WUME3_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2680	#define LLWU_ME_WUME4_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2681	#define LLWU_ME_WUME4_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2682	#define LLWU_ME_WUME5_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2683	#define LLWU_ME_WUME5_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2684	#define LLWU_ME_WUME6_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2685	#define LLWU_ME_WUME6_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2686	#define LLWU_ME_WUME7_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2687	#define LLWU_ME_WUME7_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2688	/* F1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2689	#define LLWU_F1_WUF0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2690	#define LLWU_F1_WUF0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2691	#define LLWU_F1_WUF1_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2692	#define LLWU_F1_WUF1_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2693	#define LLWU_F1_WUF2_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	2694	#define LLWU_F1_WUF2_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2695	#define LLWU_F1_WUF3_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2696	#define LLWU_F1_WUF3_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2697	#define LLWU_F1_WUF4_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2698	#define LLWU_F1_WUF4_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2699	#define LLWU_F1_WUF5_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2700	#define LLWU_F1_WUF5_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2701	#define LLWU_F1_WUF6_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2702	#define LLWU_F1_WUF6_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2703	#define LLWU_F1_WUF7_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2704	#define LLWU_F1_WUF7_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2705	/* F2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2706	#define LLWU_F2_WUF8_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2707	#define LLWU_F2_WUF8_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2708	#define LLWU_F2_WUF9_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2709	#define LLWU_F2_WUF9_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2710	#define LLWU_F2_WUF10_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	2711	#define LLWU_F2_WUF10_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2712	#define LLWU_F2_WUF11_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2713	#define LLWU_F2_WUF11_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2714	#define LLWU_F2_WUF12_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2715	#define LLWU_F2_WUF12_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2716	#define LLWU_F2_WUF13_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2717	#define LLWU_F2_WUF13_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2718	#define LLWU_F2_WUF14_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2719	#define LLWU_F2_WUF14_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2720	#define LLWU_F2_WUF15_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2721	#define LLWU_F2_WUF15_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2722	/* F3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2723	#define LLWU_F3_MWUF0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2724	#define LLWU_F3_MWUF0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2725	#define LLWU_F3_MWUF1_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2726	#define LLWU_F3_MWUF1_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2727	#define LLWU_F3_MWUF2_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	2728	#define LLWU_F3_MWUF2_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2729	#define LLWU_F3_MWUF3_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2730	#define LLWU_F3_MWUF3_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2731	#define LLWU_F3_MWUF4_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2732	#define LLWU_F3_MWUF4_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2733	#define LLWU_F3_MWUF5_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2734	#define LLWU_F3_MWUF5_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2735	#define LLWU_F3_MWUF6_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2736	#define LLWU_F3_MWUF6_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2737	#define LLWU_F3_MWUF7_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2738	#define LLWU_F3_MWUF7_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2739	/* FILT1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2740	#define LLWU_FILT1_FILTSEL_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	2741	#define LLWU_FILT1_FILTSEL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2742	#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
AnnaBridge	171:3a7713b1edbc	2743	#define LLWU_FILT1_FILTE_MASK 0x60u
AnnaBridge	171:3a7713b1edbc	2744	#define LLWU_FILT1_FILTE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2745	#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
AnnaBridge	171:3a7713b1edbc	2746	#define LLWU_FILT1_FILTF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2747	#define LLWU_FILT1_FILTF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2748	/* FILT2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2749	#define LLWU_FILT2_FILTSEL_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	2750	#define LLWU_FILT2_FILTSEL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2751	#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
AnnaBridge	171:3a7713b1edbc	2752	#define LLWU_FILT2_FILTE_MASK 0x60u
AnnaBridge	171:3a7713b1edbc	2753	#define LLWU_FILT2_FILTE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2754	#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
AnnaBridge	171:3a7713b1edbc	2755	#define LLWU_FILT2_FILTF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2756	#define LLWU_FILT2_FILTF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2757	/* RST Bit Fields */
AnnaBridge	171:3a7713b1edbc	2758	#define LLWU_RST_RSTFILT_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2759	#define LLWU_RST_RSTFILT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2760	#define LLWU_RST_LLRSTE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2761	#define LLWU_RST_LLRSTE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2762
AnnaBridge	171:3a7713b1edbc	2763	/**
AnnaBridge	171:3a7713b1edbc	2764	* @}
AnnaBridge	171:3a7713b1edbc	2765	/ / end of group LLWU_Register_Masks */
AnnaBridge	171:3a7713b1edbc	2766
AnnaBridge	171:3a7713b1edbc	2767
AnnaBridge	171:3a7713b1edbc	2768	/* LLWU - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	2769	/** Peripheral LLWU base address */
AnnaBridge	171:3a7713b1edbc	2770	#define LLWU_BASE (0x4007C000u)
AnnaBridge	171:3a7713b1edbc	2771	/** Peripheral LLWU base pointer */
AnnaBridge	171:3a7713b1edbc	2772	#define LLWU ((LLWU_Type *)LLWU_BASE)
AnnaBridge	171:3a7713b1edbc	2773
AnnaBridge	171:3a7713b1edbc	2774	/**
AnnaBridge	171:3a7713b1edbc	2775	* @}
AnnaBridge	171:3a7713b1edbc	2776	/ / end of group LLWU_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	2777
AnnaBridge	171:3a7713b1edbc	2778
AnnaBridge	171:3a7713b1edbc	2779	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2780	-- LPTMR Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	2781	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	2782
AnnaBridge	171:3a7713b1edbc	2783	/**
AnnaBridge	171:3a7713b1edbc	2784	* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	2785	* @{
AnnaBridge	171:3a7713b1edbc	2786	*/
AnnaBridge	171:3a7713b1edbc	2787
AnnaBridge	171:3a7713b1edbc	2788	/** LPTMR - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	2789	typedef struct {
AnnaBridge	171:3a7713b1edbc	2790	__IO uint32_t CSR; /*< Low Power Timer Control Status Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	2791	__IO uint32_t PSR; /*< Low Power Timer Prescale Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	2792	__IO uint32_t CMR; /*< Low Power Timer Compare Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	2793	__I uint32_t CNR; /*< Low Power Timer Counter Register, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	2794	} LPTMR_Type;
AnnaBridge	171:3a7713b1edbc	2795
AnnaBridge	171:3a7713b1edbc	2796	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2797	-- LPTMR Register Masks
AnnaBridge	171:3a7713b1edbc	2798	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	2799
AnnaBridge	171:3a7713b1edbc	2800	/**
AnnaBridge	171:3a7713b1edbc	2801	* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
AnnaBridge	171:3a7713b1edbc	2802	* @{
AnnaBridge	171:3a7713b1edbc	2803	*/
AnnaBridge	171:3a7713b1edbc	2804
AnnaBridge	171:3a7713b1edbc	2805	/* CSR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2806	#define LPTMR_CSR_TEN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2807	#define LPTMR_CSR_TEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2808	#define LPTMR_CSR_TMS_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2809	#define LPTMR_CSR_TMS_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2810	#define LPTMR_CSR_TFC_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	2811	#define LPTMR_CSR_TFC_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2812	#define LPTMR_CSR_TPP_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2813	#define LPTMR_CSR_TPP_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2814	#define LPTMR_CSR_TPS_MASK 0x30u
AnnaBridge	171:3a7713b1edbc	2815	#define LPTMR_CSR_TPS_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2816	#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
AnnaBridge	171:3a7713b1edbc	2817	#define LPTMR_CSR_TIE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2818	#define LPTMR_CSR_TIE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2819	#define LPTMR_CSR_TCF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2820	#define LPTMR_CSR_TCF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2821	/* PSR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2822	#define LPTMR_PSR_PCS_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	2823	#define LPTMR_PSR_PCS_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2824	#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
AnnaBridge	171:3a7713b1edbc	2825	#define LPTMR_PSR_PBYP_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	2826	#define LPTMR_PSR_PBYP_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2827	#define LPTMR_PSR_PRESCALE_MASK 0x78u
AnnaBridge	171:3a7713b1edbc	2828	#define LPTMR_PSR_PRESCALE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2829	#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
AnnaBridge	171:3a7713b1edbc	2830	/* CMR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2831	#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	2832	#define LPTMR_CMR_COMPARE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2833	#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
AnnaBridge	171:3a7713b1edbc	2834	/* CNR Bit Fields */
AnnaBridge	171:3a7713b1edbc	2835	#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	2836	#define LPTMR_CNR_COUNTER_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2837	#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
AnnaBridge	171:3a7713b1edbc	2838
AnnaBridge	171:3a7713b1edbc	2839	/**
AnnaBridge	171:3a7713b1edbc	2840	* @}
AnnaBridge	171:3a7713b1edbc	2841	/ / end of group LPTMR_Register_Masks */
AnnaBridge	171:3a7713b1edbc	2842
AnnaBridge	171:3a7713b1edbc	2843
AnnaBridge	171:3a7713b1edbc	2844	/* LPTMR - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	2845	/** Peripheral LPTMR0 base address */
AnnaBridge	171:3a7713b1edbc	2846	#define LPTMR0_BASE (0x40040000u)
AnnaBridge	171:3a7713b1edbc	2847	/** Peripheral LPTMR0 base pointer */
AnnaBridge	171:3a7713b1edbc	2848	#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
AnnaBridge	171:3a7713b1edbc	2849
AnnaBridge	171:3a7713b1edbc	2850	/**
AnnaBridge	171:3a7713b1edbc	2851	* @}
AnnaBridge	171:3a7713b1edbc	2852	/ / end of group LPTMR_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	2853
AnnaBridge	171:3a7713b1edbc	2854
AnnaBridge	171:3a7713b1edbc	2855	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2856	-- MCG Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	2857	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	2858
AnnaBridge	171:3a7713b1edbc	2859	/**
AnnaBridge	171:3a7713b1edbc	2860	* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	2861	* @{
AnnaBridge	171:3a7713b1edbc	2862	*/
AnnaBridge	171:3a7713b1edbc	2863
AnnaBridge	171:3a7713b1edbc	2864	/** MCG - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	2865	typedef struct {
AnnaBridge	171:3a7713b1edbc	2866	__IO uint8_t C1; /*< MCG Control 1 Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	2867	__IO uint8_t C2; /*< MCG Control 2 Register, offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	2868	__IO uint8_t C3; /*< MCG Control 3 Register, offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	2869	__IO uint8_t C4; /*< MCG Control 4 Register, offset: 0x3 /
AnnaBridge	171:3a7713b1edbc	2870	__IO uint8_t C5; /*< MCG Control 5 Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	2871	__IO uint8_t C6; /*< MCG Control 6 Register, offset: 0x5 /
AnnaBridge	171:3a7713b1edbc	2872	__I uint8_t S; /*< MCG Status Register, offset: 0x6 /
AnnaBridge	171:3a7713b1edbc	2873	uint8_t RESERVED_0[1];
AnnaBridge	171:3a7713b1edbc	2874	__IO uint8_t SC; /*< MCG Status and Control Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	2875	uint8_t RESERVED_1[1];
AnnaBridge	171:3a7713b1edbc	2876	__IO uint8_t ATCVH; /*< MCG Auto Trim Compare Value High Register, offset: 0xA /
AnnaBridge	171:3a7713b1edbc	2877	__IO uint8_t ATCVL; /*< MCG Auto Trim Compare Value Low Register, offset: 0xB /
AnnaBridge	171:3a7713b1edbc	2878	__IO uint8_t C7; /*< MCG Control 7 Register, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	2879	__IO uint8_t C8; /*< MCG Control 8 Register, offset: 0xD /
AnnaBridge	171:3a7713b1edbc	2880	} MCG_Type;
AnnaBridge	171:3a7713b1edbc	2881
AnnaBridge	171:3a7713b1edbc	2882	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	2883	-- MCG Register Masks
AnnaBridge	171:3a7713b1edbc	2884	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	2885
AnnaBridge	171:3a7713b1edbc	2886	/**
AnnaBridge	171:3a7713b1edbc	2887	* @addtogroup MCG_Register_Masks MCG Register Masks
AnnaBridge	171:3a7713b1edbc	2888	* @{
AnnaBridge	171:3a7713b1edbc	2889	*/
AnnaBridge	171:3a7713b1edbc	2890
AnnaBridge	171:3a7713b1edbc	2891	/* C1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2892	#define MCG_C1_IREFSTEN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2893	#define MCG_C1_IREFSTEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2894	#define MCG_C1_IRCLKEN_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2895	#define MCG_C1_IRCLKEN_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2896	#define MCG_C1_IREFS_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	2897	#define MCG_C1_IREFS_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2898	#define MCG_C1_FRDIV_MASK 0x38u
AnnaBridge	171:3a7713b1edbc	2899	#define MCG_C1_FRDIV_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2900	#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
AnnaBridge	171:3a7713b1edbc	2901	#define MCG_C1_CLKS_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	2902	#define MCG_C1_CLKS_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2903	#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
AnnaBridge	171:3a7713b1edbc	2904	/* C2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2905	#define MCG_C2_IRCS_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2906	#define MCG_C2_IRCS_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2907	#define MCG_C2_LP_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2908	#define MCG_C2_LP_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2909	#define MCG_C2_EREFS0_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	2910	#define MCG_C2_EREFS0_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2911	#define MCG_C2_HGO0_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	2912	#define MCG_C2_HGO0_SHIFT 3
AnnaBridge	171:3a7713b1edbc	2913	#define MCG_C2_RANGE0_MASK 0x30u
AnnaBridge	171:3a7713b1edbc	2914	#define MCG_C2_RANGE0_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2915	#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
AnnaBridge	171:3a7713b1edbc	2916	#define MCG_C2_LOCRE0_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2917	#define MCG_C2_LOCRE0_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2918	/* C3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2919	#define MCG_C3_SCTRIM_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	2920	#define MCG_C3_SCTRIM_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2921	#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
AnnaBridge	171:3a7713b1edbc	2922	/* C4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2923	#define MCG_C4_SCFTRIM_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2924	#define MCG_C4_SCFTRIM_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2925	#define MCG_C4_FCTRIM_MASK 0x1Eu
AnnaBridge	171:3a7713b1edbc	2926	#define MCG_C4_FCTRIM_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2927	#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
AnnaBridge	171:3a7713b1edbc	2928	#define MCG_C4_DRST_DRS_MASK 0x60u
AnnaBridge	171:3a7713b1edbc	2929	#define MCG_C4_DRST_DRS_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2930	#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
AnnaBridge	171:3a7713b1edbc	2931	#define MCG_C4_DMX32_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2932	#define MCG_C4_DMX32_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2933	/* C5 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2934	#define MCG_C5_PRDIV0_MASK 0x1Fu
AnnaBridge	171:3a7713b1edbc	2935	#define MCG_C5_PRDIV0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2936	#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
AnnaBridge	171:3a7713b1edbc	2937	#define MCG_C5_PLLSTEN0_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2938	#define MCG_C5_PLLSTEN0_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2939	#define MCG_C5_PLLCLKEN0_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2940	#define MCG_C5_PLLCLKEN0_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2941	/* C6 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2942	#define MCG_C6_VDIV0_MASK 0x1Fu
AnnaBridge	171:3a7713b1edbc	2943	#define MCG_C6_VDIV0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2944	#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
AnnaBridge	171:3a7713b1edbc	2945	#define MCG_C6_CME0_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2946	#define MCG_C6_CME0_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2947	#define MCG_C6_PLLS_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2948	#define MCG_C6_PLLS_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2949	#define MCG_C6_LOLIE0_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2950	#define MCG_C6_LOLIE0_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2951	/* S Bit Fields */
AnnaBridge	171:3a7713b1edbc	2952	#define MCG_S_IRCST_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2953	#define MCG_S_IRCST_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2954	#define MCG_S_OSCINIT0_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	2955	#define MCG_S_OSCINIT0_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2956	#define MCG_S_CLKST_MASK 0xCu
AnnaBridge	171:3a7713b1edbc	2957	#define MCG_S_CLKST_SHIFT 2
AnnaBridge	171:3a7713b1edbc	2958	#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
AnnaBridge	171:3a7713b1edbc	2959	#define MCG_S_IREFST_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2960	#define MCG_S_IREFST_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2961	#define MCG_S_PLLST_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2962	#define MCG_S_PLLST_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2963	#define MCG_S_LOCK0_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2964	#define MCG_S_LOCK0_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2965	#define MCG_S_LOLS0_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2966	#define MCG_S_LOLS0_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2967	/* SC Bit Fields */
AnnaBridge	171:3a7713b1edbc	2968	#define MCG_SC_LOCS0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2969	#define MCG_SC_LOCS0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2970	#define MCG_SC_FCRDIV_MASK 0xEu
AnnaBridge	171:3a7713b1edbc	2971	#define MCG_SC_FCRDIV_SHIFT 1
AnnaBridge	171:3a7713b1edbc	2972	#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
AnnaBridge	171:3a7713b1edbc	2973	#define MCG_SC_FLTPRSRV_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	2974	#define MCG_SC_FLTPRSRV_SHIFT 4
AnnaBridge	171:3a7713b1edbc	2975	#define MCG_SC_ATMF_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2976	#define MCG_SC_ATMF_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2977	#define MCG_SC_ATMS_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2978	#define MCG_SC_ATMS_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2979	#define MCG_SC_ATME_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	2980	#define MCG_SC_ATME_SHIFT 7
AnnaBridge	171:3a7713b1edbc	2981	/* ATCVH Bit Fields */
AnnaBridge	171:3a7713b1edbc	2982	#define MCG_ATCVH_ATCVH_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	2983	#define MCG_ATCVH_ATCVH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2984	#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
AnnaBridge	171:3a7713b1edbc	2985	/* ATCVL Bit Fields */
AnnaBridge	171:3a7713b1edbc	2986	#define MCG_ATCVL_ATCVL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	2987	#define MCG_ATCVL_ATCVL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2988	#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
AnnaBridge	171:3a7713b1edbc	2989	/* C7 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2990	#define MCG_C7_OSCSEL_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2991	#define MCG_C7_OSCSEL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2992	/* C8 Bit Fields */
AnnaBridge	171:3a7713b1edbc	2993	#define MCG_C8_LOCS1_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	2994	#define MCG_C8_LOCS1_SHIFT 0
AnnaBridge	171:3a7713b1edbc	2995	#define MCG_C8_CME1_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	2996	#define MCG_C8_CME1_SHIFT 5
AnnaBridge	171:3a7713b1edbc	2997	#define MCG_C8_LOLRE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	2998	#define MCG_C8_LOLRE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	2999	#define MCG_C8_LOCRE1_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	3000	#define MCG_C8_LOCRE1_SHIFT 7
AnnaBridge	171:3a7713b1edbc	3001
AnnaBridge	171:3a7713b1edbc	3002	/**
AnnaBridge	171:3a7713b1edbc	3003	* @}
AnnaBridge	171:3a7713b1edbc	3004	/ / end of group MCG_Register_Masks */
AnnaBridge	171:3a7713b1edbc	3005
AnnaBridge	171:3a7713b1edbc	3006
AnnaBridge	171:3a7713b1edbc	3007	/* MCG - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	3008	/** Peripheral MCG base address */
AnnaBridge	171:3a7713b1edbc	3009	#define MCG_BASE (0x40064000u)
AnnaBridge	171:3a7713b1edbc	3010	/** Peripheral MCG base pointer */
AnnaBridge	171:3a7713b1edbc	3011	#define MCG ((MCG_Type *)MCG_BASE)
AnnaBridge	171:3a7713b1edbc	3012
AnnaBridge	171:3a7713b1edbc	3013	/**
AnnaBridge	171:3a7713b1edbc	3014	* @}
AnnaBridge	171:3a7713b1edbc	3015	/ / end of group MCG_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	3016
AnnaBridge	171:3a7713b1edbc	3017
AnnaBridge	171:3a7713b1edbc	3018	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3019	-- NV Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3020	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3021
AnnaBridge	171:3a7713b1edbc	3022	/**
AnnaBridge	171:3a7713b1edbc	3023	* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3024	* @{
AnnaBridge	171:3a7713b1edbc	3025	*/
AnnaBridge	171:3a7713b1edbc	3026
AnnaBridge	171:3a7713b1edbc	3027	/** NV - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	3028	typedef struct {
AnnaBridge	171:3a7713b1edbc	3029	__I uint8_t BACKKEY3; /*< Backdoor Comparison Key 3., offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	3030	__I uint8_t BACKKEY2; /*< Backdoor Comparison Key 2., offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	3031	__I uint8_t BACKKEY1; /*< Backdoor Comparison Key 1., offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	3032	__I uint8_t BACKKEY0; /*< Backdoor Comparison Key 0., offset: 0x3 /
AnnaBridge	171:3a7713b1edbc	3033	__I uint8_t BACKKEY7; /*< Backdoor Comparison Key 7., offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	3034	__I uint8_t BACKKEY6; /*< Backdoor Comparison Key 6., offset: 0x5 /
AnnaBridge	171:3a7713b1edbc	3035	__I uint8_t BACKKEY5; /*< Backdoor Comparison Key 5., offset: 0x6 /
AnnaBridge	171:3a7713b1edbc	3036	__I uint8_t BACKKEY4; /*< Backdoor Comparison Key 4., offset: 0x7 /
AnnaBridge	171:3a7713b1edbc	3037	__I uint8_t FPROT3; /*< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	3038	__I uint8_t FPROT2; /*< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 /
AnnaBridge	171:3a7713b1edbc	3039	__I uint8_t FPROT1; /*< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA /
AnnaBridge	171:3a7713b1edbc	3040	__I uint8_t FPROT0; /*< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB /
AnnaBridge	171:3a7713b1edbc	3041	__I uint8_t FSEC; /*< Non-volatile Flash Security Register, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	3042	__I uint8_t FOPT; /*< Non-volatile Flash Option Register, offset: 0xD /
AnnaBridge	171:3a7713b1edbc	3043	__I uint8_t FEPROT; /*< Non-volatile EERAM Protection Register, offset: 0xE /
AnnaBridge	171:3a7713b1edbc	3044	__I uint8_t FDPROT; /*< Non-volatile D-Flash Protection Register, offset: 0xF /
AnnaBridge	171:3a7713b1edbc	3045	} NV_Type;
AnnaBridge	171:3a7713b1edbc	3046
AnnaBridge	171:3a7713b1edbc	3047	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3048	-- NV Register Masks
AnnaBridge	171:3a7713b1edbc	3049	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3050
AnnaBridge	171:3a7713b1edbc	3051	/**
AnnaBridge	171:3a7713b1edbc	3052	* @addtogroup NV_Register_Masks NV Register Masks
AnnaBridge	171:3a7713b1edbc	3053	* @{
AnnaBridge	171:3a7713b1edbc	3054	*/
AnnaBridge	171:3a7713b1edbc	3055
AnnaBridge	171:3a7713b1edbc	3056	/* BACKKEY3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3057	#define NV_BACKKEY3_KEY_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3058	#define NV_BACKKEY3_KEY_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3059	#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
AnnaBridge	171:3a7713b1edbc	3060	/* BACKKEY2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3061	#define NV_BACKKEY2_KEY_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3062	#define NV_BACKKEY2_KEY_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3063	#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
AnnaBridge	171:3a7713b1edbc	3064	/* BACKKEY1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3065	#define NV_BACKKEY1_KEY_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3066	#define NV_BACKKEY1_KEY_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3067	#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
AnnaBridge	171:3a7713b1edbc	3068	/* BACKKEY0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3069	#define NV_BACKKEY0_KEY_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3070	#define NV_BACKKEY0_KEY_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3071	#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
AnnaBridge	171:3a7713b1edbc	3072	/* BACKKEY7 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3073	#define NV_BACKKEY7_KEY_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3074	#define NV_BACKKEY7_KEY_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3075	#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
AnnaBridge	171:3a7713b1edbc	3076	/* BACKKEY6 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3077	#define NV_BACKKEY6_KEY_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3078	#define NV_BACKKEY6_KEY_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3079	#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
AnnaBridge	171:3a7713b1edbc	3080	/* BACKKEY5 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3081	#define NV_BACKKEY5_KEY_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3082	#define NV_BACKKEY5_KEY_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3083	#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
AnnaBridge	171:3a7713b1edbc	3084	/* BACKKEY4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3085	#define NV_BACKKEY4_KEY_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3086	#define NV_BACKKEY4_KEY_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3087	#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
AnnaBridge	171:3a7713b1edbc	3088	/* FPROT3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3089	#define NV_FPROT3_PROT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3090	#define NV_FPROT3_PROT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3091	#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
AnnaBridge	171:3a7713b1edbc	3092	/* FPROT2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3093	#define NV_FPROT2_PROT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3094	#define NV_FPROT2_PROT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3095	#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
AnnaBridge	171:3a7713b1edbc	3096	/* FPROT1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3097	#define NV_FPROT1_PROT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3098	#define NV_FPROT1_PROT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3099	#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
AnnaBridge	171:3a7713b1edbc	3100	/* FPROT0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3101	#define NV_FPROT0_PROT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3102	#define NV_FPROT0_PROT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3103	#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
AnnaBridge	171:3a7713b1edbc	3104	/* FSEC Bit Fields */
AnnaBridge	171:3a7713b1edbc	3105	#define NV_FSEC_SEC_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	3106	#define NV_FSEC_SEC_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3107	#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
AnnaBridge	171:3a7713b1edbc	3108	#define NV_FSEC_FSLACC_MASK 0xCu
AnnaBridge	171:3a7713b1edbc	3109	#define NV_FSEC_FSLACC_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3110	#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
AnnaBridge	171:3a7713b1edbc	3111	#define NV_FSEC_MEEN_MASK 0x30u
AnnaBridge	171:3a7713b1edbc	3112	#define NV_FSEC_MEEN_SHIFT 4
AnnaBridge	171:3a7713b1edbc	3113	#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
AnnaBridge	171:3a7713b1edbc	3114	#define NV_FSEC_KEYEN_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	3115	#define NV_FSEC_KEYEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	3116	#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
AnnaBridge	171:3a7713b1edbc	3117	/* FOPT Bit Fields */
AnnaBridge	171:3a7713b1edbc	3118	#define NV_FOPT_LPBOOT_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3119	#define NV_FOPT_LPBOOT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3120	#define NV_FOPT_EZPORT_DIS_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3121	#define NV_FOPT_EZPORT_DIS_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3122	/* FEPROT Bit Fields */
AnnaBridge	171:3a7713b1edbc	3123	#define NV_FEPROT_EPROT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3124	#define NV_FEPROT_EPROT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3125	#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
AnnaBridge	171:3a7713b1edbc	3126	/* FDPROT Bit Fields */
AnnaBridge	171:3a7713b1edbc	3127	#define NV_FDPROT_DPROT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3128	#define NV_FDPROT_DPROT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3129	#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
AnnaBridge	171:3a7713b1edbc	3130
AnnaBridge	171:3a7713b1edbc	3131	/**
AnnaBridge	171:3a7713b1edbc	3132	* @}
AnnaBridge	171:3a7713b1edbc	3133	/ / end of group NV_Register_Masks */
AnnaBridge	171:3a7713b1edbc	3134
AnnaBridge	171:3a7713b1edbc	3135
AnnaBridge	171:3a7713b1edbc	3136	/* NV - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	3137	/** Peripheral FTFL_FlashConfig base address */
AnnaBridge	171:3a7713b1edbc	3138	#define FTFL_FlashConfig_BASE (0x400u)
AnnaBridge	171:3a7713b1edbc	3139	/** Peripheral FTFL_FlashConfig base pointer */
AnnaBridge	171:3a7713b1edbc	3140	#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
AnnaBridge	171:3a7713b1edbc	3141
AnnaBridge	171:3a7713b1edbc	3142	/**
AnnaBridge	171:3a7713b1edbc	3143	* @}
AnnaBridge	171:3a7713b1edbc	3144	/ / end of group NV_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	3145
AnnaBridge	171:3a7713b1edbc	3146
AnnaBridge	171:3a7713b1edbc	3147	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3148	-- OSC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3149	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3150
AnnaBridge	171:3a7713b1edbc	3151	/**
AnnaBridge	171:3a7713b1edbc	3152	* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3153	* @{
AnnaBridge	171:3a7713b1edbc	3154	*/
AnnaBridge	171:3a7713b1edbc	3155
AnnaBridge	171:3a7713b1edbc	3156	/** OSC - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	3157	typedef struct {
AnnaBridge	171:3a7713b1edbc	3158	__IO uint8_t CR; /*< OSC Control Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	3159	} OSC_Type;
AnnaBridge	171:3a7713b1edbc	3160
AnnaBridge	171:3a7713b1edbc	3161	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3162	-- OSC Register Masks
AnnaBridge	171:3a7713b1edbc	3163	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3164
AnnaBridge	171:3a7713b1edbc	3165	/**
AnnaBridge	171:3a7713b1edbc	3166	* @addtogroup OSC_Register_Masks OSC Register Masks
AnnaBridge	171:3a7713b1edbc	3167	* @{
AnnaBridge	171:3a7713b1edbc	3168	*/
AnnaBridge	171:3a7713b1edbc	3169
AnnaBridge	171:3a7713b1edbc	3170	/* CR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3171	#define OSC_CR_SC16P_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3172	#define OSC_CR_SC16P_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3173	#define OSC_CR_SC8P_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3174	#define OSC_CR_SC8P_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3175	#define OSC_CR_SC4P_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	3176	#define OSC_CR_SC4P_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3177	#define OSC_CR_SC2P_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	3178	#define OSC_CR_SC2P_SHIFT 3
AnnaBridge	171:3a7713b1edbc	3179	#define OSC_CR_EREFSTEN_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	3180	#define OSC_CR_EREFSTEN_SHIFT 5
AnnaBridge	171:3a7713b1edbc	3181	#define OSC_CR_ERCLKEN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	3182	#define OSC_CR_ERCLKEN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	3183
AnnaBridge	171:3a7713b1edbc	3184	/**
AnnaBridge	171:3a7713b1edbc	3185	* @}
AnnaBridge	171:3a7713b1edbc	3186	/ / end of group OSC_Register_Masks */
AnnaBridge	171:3a7713b1edbc	3187
AnnaBridge	171:3a7713b1edbc	3188
AnnaBridge	171:3a7713b1edbc	3189	/* OSC - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	3190	/** Peripheral OSC0 base address */
AnnaBridge	171:3a7713b1edbc	3191	#define OSC0_BASE (0x40065000u)
AnnaBridge	171:3a7713b1edbc	3192	/** Peripheral OSC0 base pointer */
AnnaBridge	171:3a7713b1edbc	3193	#define OSC0 ((OSC_Type *)OSC0_BASE)
AnnaBridge	171:3a7713b1edbc	3194
AnnaBridge	171:3a7713b1edbc	3195	/**
AnnaBridge	171:3a7713b1edbc	3196	* @}
AnnaBridge	171:3a7713b1edbc	3197	/ / end of group OSC_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	3198
AnnaBridge	171:3a7713b1edbc	3199
AnnaBridge	171:3a7713b1edbc	3200	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3201	-- PDB Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3202	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3203
AnnaBridge	171:3a7713b1edbc	3204	/**
AnnaBridge	171:3a7713b1edbc	3205	* @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3206	* @{
AnnaBridge	171:3a7713b1edbc	3207	*/
AnnaBridge	171:3a7713b1edbc	3208
AnnaBridge	171:3a7713b1edbc	3209	/** PDB - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	3210	typedef struct {
AnnaBridge	171:3a7713b1edbc	3211	__IO uint32_t SC; /*< Status and Control Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	3212	__IO uint32_t MOD; /*< Modulus Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	3213	__I uint32_t CNT; /*< Counter Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	3214	__IO uint32_t IDLY; /*< Interrupt Delay Register, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	3215	struct { /* offset: 0x10, array step: 0x10 */
AnnaBridge	171:3a7713b1edbc	3216	__IO uint32_t C1; /*< Channel n Control Register 1, array offset: 0x10, array step: 0x10 /
AnnaBridge	171:3a7713b1edbc	3217	__IO uint32_t S; /*< Channel n Status Register, array offset: 0x14, array step: 0x10 /
AnnaBridge	171:3a7713b1edbc	3218	__IO uint32_t DLY[2]; /*< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index0x10, index20x4 /
AnnaBridge	171:3a7713b1edbc	3219	} CH[1];
AnnaBridge	171:3a7713b1edbc	3220	uint8_t RESERVED_0[368];
AnnaBridge	171:3a7713b1edbc	3221	__IO uint32_t POEN; /*< Pulse-Out n Enable Register, offset: 0x190 /
AnnaBridge	171:3a7713b1edbc	3222	__IO uint32_t PODLY[2]; /*< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	3223	} PDB_Type;
AnnaBridge	171:3a7713b1edbc	3224
AnnaBridge	171:3a7713b1edbc	3225	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3226	-- PDB Register Masks
AnnaBridge	171:3a7713b1edbc	3227	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3228
AnnaBridge	171:3a7713b1edbc	3229	/**
AnnaBridge	171:3a7713b1edbc	3230	* @addtogroup PDB_Register_Masks PDB Register Masks
AnnaBridge	171:3a7713b1edbc	3231	* @{
AnnaBridge	171:3a7713b1edbc	3232	*/
AnnaBridge	171:3a7713b1edbc	3233
AnnaBridge	171:3a7713b1edbc	3234	/* SC Bit Fields */
AnnaBridge	171:3a7713b1edbc	3235	#define PDB_SC_LDOK_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3236	#define PDB_SC_LDOK_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3237	#define PDB_SC_CONT_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3238	#define PDB_SC_CONT_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3239	#define PDB_SC_MULT_MASK 0xCu
AnnaBridge	171:3a7713b1edbc	3240	#define PDB_SC_MULT_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3241	#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
AnnaBridge	171:3a7713b1edbc	3242	#define PDB_SC_PDBIE_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	3243	#define PDB_SC_PDBIE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	3244	#define PDB_SC_PDBIF_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	3245	#define PDB_SC_PDBIF_SHIFT 6
AnnaBridge	171:3a7713b1edbc	3246	#define PDB_SC_PDBEN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	3247	#define PDB_SC_PDBEN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	3248	#define PDB_SC_TRGSEL_MASK 0xF00u
AnnaBridge	171:3a7713b1edbc	3249	#define PDB_SC_TRGSEL_SHIFT 8
AnnaBridge	171:3a7713b1edbc	3250	#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
AnnaBridge	171:3a7713b1edbc	3251	#define PDB_SC_PRESCALER_MASK 0x7000u
AnnaBridge	171:3a7713b1edbc	3252	#define PDB_SC_PRESCALER_SHIFT 12
AnnaBridge	171:3a7713b1edbc	3253	#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
AnnaBridge	171:3a7713b1edbc	3254	#define PDB_SC_DMAEN_MASK 0x8000u
AnnaBridge	171:3a7713b1edbc	3255	#define PDB_SC_DMAEN_SHIFT 15
AnnaBridge	171:3a7713b1edbc	3256	#define PDB_SC_SWTRIG_MASK 0x10000u
AnnaBridge	171:3a7713b1edbc	3257	#define PDB_SC_SWTRIG_SHIFT 16
AnnaBridge	171:3a7713b1edbc	3258	#define PDB_SC_PDBEIE_MASK 0x20000u
AnnaBridge	171:3a7713b1edbc	3259	#define PDB_SC_PDBEIE_SHIFT 17
AnnaBridge	171:3a7713b1edbc	3260	#define PDB_SC_LDMOD_MASK 0xC0000u
AnnaBridge	171:3a7713b1edbc	3261	#define PDB_SC_LDMOD_SHIFT 18
AnnaBridge	171:3a7713b1edbc	3262	#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
AnnaBridge	171:3a7713b1edbc	3263	/* MOD Bit Fields */
AnnaBridge	171:3a7713b1edbc	3264	#define PDB_MOD_MOD_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	3265	#define PDB_MOD_MOD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3266	#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
AnnaBridge	171:3a7713b1edbc	3267	/* CNT Bit Fields */
AnnaBridge	171:3a7713b1edbc	3268	#define PDB_CNT_CNT_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	3269	#define PDB_CNT_CNT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3270	#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
AnnaBridge	171:3a7713b1edbc	3271	/* IDLY Bit Fields */
AnnaBridge	171:3a7713b1edbc	3272	#define PDB_IDLY_IDLY_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	3273	#define PDB_IDLY_IDLY_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3274	#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
AnnaBridge	171:3a7713b1edbc	3275	/* C1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3276	#define PDB_C1_EN_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3277	#define PDB_C1_EN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3278	#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
AnnaBridge	171:3a7713b1edbc	3279	#define PDB_C1_TOS_MASK 0xFF00u
AnnaBridge	171:3a7713b1edbc	3280	#define PDB_C1_TOS_SHIFT 8
AnnaBridge	171:3a7713b1edbc	3281	#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
AnnaBridge	171:3a7713b1edbc	3282	#define PDB_C1_BB_MASK 0xFF0000u
AnnaBridge	171:3a7713b1edbc	3283	#define PDB_C1_BB_SHIFT 16
AnnaBridge	171:3a7713b1edbc	3284	#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
AnnaBridge	171:3a7713b1edbc	3285	/* S Bit Fields */
AnnaBridge	171:3a7713b1edbc	3286	#define PDB_S_ERR_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3287	#define PDB_S_ERR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3288	#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
AnnaBridge	171:3a7713b1edbc	3289	#define PDB_S_CF_MASK 0xFF0000u
AnnaBridge	171:3a7713b1edbc	3290	#define PDB_S_CF_SHIFT 16
AnnaBridge	171:3a7713b1edbc	3291	#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
AnnaBridge	171:3a7713b1edbc	3292	/* DLY Bit Fields */
AnnaBridge	171:3a7713b1edbc	3293	#define PDB_DLY_DLY_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	3294	#define PDB_DLY_DLY_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3295	#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
AnnaBridge	171:3a7713b1edbc	3296	/* POEN Bit Fields */
AnnaBridge	171:3a7713b1edbc	3297	#define PDB_POEN_POEN_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3298	#define PDB_POEN_POEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3299	#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
AnnaBridge	171:3a7713b1edbc	3300	/* PODLY Bit Fields */
AnnaBridge	171:3a7713b1edbc	3301	#define PDB_PODLY_DLY2_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	3302	#define PDB_PODLY_DLY2_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3303	#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
AnnaBridge	171:3a7713b1edbc	3304	#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	3305	#define PDB_PODLY_DLY1_SHIFT 16
AnnaBridge	171:3a7713b1edbc	3306	#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
AnnaBridge	171:3a7713b1edbc	3307
AnnaBridge	171:3a7713b1edbc	3308	/**
AnnaBridge	171:3a7713b1edbc	3309	* @}
AnnaBridge	171:3a7713b1edbc	3310	/ / end of group PDB_Register_Masks */
AnnaBridge	171:3a7713b1edbc	3311
AnnaBridge	171:3a7713b1edbc	3312
AnnaBridge	171:3a7713b1edbc	3313	/* PDB - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	3314	/** Peripheral PDB0 base address */
AnnaBridge	171:3a7713b1edbc	3315	#define PDB0_BASE (0x40036000u)
AnnaBridge	171:3a7713b1edbc	3316	/** Peripheral PDB0 base pointer */
AnnaBridge	171:3a7713b1edbc	3317	#define PDB0 ((PDB_Type *)PDB0_BASE)
AnnaBridge	171:3a7713b1edbc	3318
AnnaBridge	171:3a7713b1edbc	3319	/**
AnnaBridge	171:3a7713b1edbc	3320	* @}
AnnaBridge	171:3a7713b1edbc	3321	/ / end of group PDB_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	3322
AnnaBridge	171:3a7713b1edbc	3323
AnnaBridge	171:3a7713b1edbc	3324	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3325	-- PIT Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3326	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3327
AnnaBridge	171:3a7713b1edbc	3328	/**
AnnaBridge	171:3a7713b1edbc	3329	* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3330	* @{
AnnaBridge	171:3a7713b1edbc	3331	*/
AnnaBridge	171:3a7713b1edbc	3332
AnnaBridge	171:3a7713b1edbc	3333	/** PIT - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	3334	typedef struct {
AnnaBridge	171:3a7713b1edbc	3335	__IO uint32_t MCR; /*< PIT Module Control Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	3336	uint8_t RESERVED_0[252];
AnnaBridge	171:3a7713b1edbc	3337	struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge	171:3a7713b1edbc	3338	__IO uint32_t LDVAL; /*< Timer Load Value Register, array offset: 0x100, array step: 0x10 /
AnnaBridge	171:3a7713b1edbc	3339	__I uint32_t CVAL; /*< Current Timer Value Register, array offset: 0x104, array step: 0x10 /
AnnaBridge	171:3a7713b1edbc	3340	__IO uint32_t TCTRL; /*< Timer Control Register, array offset: 0x108, array step: 0x10 /
AnnaBridge	171:3a7713b1edbc	3341	__IO uint32_t TFLG; /*< Timer Flag Register, array offset: 0x10C, array step: 0x10 /
AnnaBridge	171:3a7713b1edbc	3342	} CHANNEL[4];
AnnaBridge	171:3a7713b1edbc	3343	} PIT_Type;
AnnaBridge	171:3a7713b1edbc	3344
AnnaBridge	171:3a7713b1edbc	3345	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3346	-- PIT Register Masks
AnnaBridge	171:3a7713b1edbc	3347	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3348
AnnaBridge	171:3a7713b1edbc	3349	/**
AnnaBridge	171:3a7713b1edbc	3350	* @addtogroup PIT_Register_Masks PIT Register Masks
AnnaBridge	171:3a7713b1edbc	3351	* @{
AnnaBridge	171:3a7713b1edbc	3352	*/
AnnaBridge	171:3a7713b1edbc	3353
AnnaBridge	171:3a7713b1edbc	3354	/* MCR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3355	#define PIT_MCR_FRZ_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3356	#define PIT_MCR_FRZ_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3357	#define PIT_MCR_MDIS_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3358	#define PIT_MCR_MDIS_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3359	/* LDVAL Bit Fields */
AnnaBridge	171:3a7713b1edbc	3360	#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	3361	#define PIT_LDVAL_TSV_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3362	#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
AnnaBridge	171:3a7713b1edbc	3363	/* CVAL Bit Fields */
AnnaBridge	171:3a7713b1edbc	3364	#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	3365	#define PIT_CVAL_TVL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3366	#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
AnnaBridge	171:3a7713b1edbc	3367	/* TCTRL Bit Fields */
AnnaBridge	171:3a7713b1edbc	3368	#define PIT_TCTRL_TEN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3369	#define PIT_TCTRL_TEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3370	#define PIT_TCTRL_TIE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3371	#define PIT_TCTRL_TIE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3372	/* TFLG Bit Fields */
AnnaBridge	171:3a7713b1edbc	3373	#define PIT_TFLG_TIF_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3374	#define PIT_TFLG_TIF_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3375
AnnaBridge	171:3a7713b1edbc	3376	/**
AnnaBridge	171:3a7713b1edbc	3377	* @}
AnnaBridge	171:3a7713b1edbc	3378	/ / end of group PIT_Register_Masks */
AnnaBridge	171:3a7713b1edbc	3379
AnnaBridge	171:3a7713b1edbc	3380
AnnaBridge	171:3a7713b1edbc	3381	/* PIT - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	3382	/** Peripheral PIT base address */
AnnaBridge	171:3a7713b1edbc	3383	#define PIT_BASE (0x40037000u)
AnnaBridge	171:3a7713b1edbc	3384	/** Peripheral PIT base pointer */
AnnaBridge	171:3a7713b1edbc	3385	#define PIT ((PIT_Type *)PIT_BASE)
AnnaBridge	171:3a7713b1edbc	3386
AnnaBridge	171:3a7713b1edbc	3387	/**
AnnaBridge	171:3a7713b1edbc	3388	* @}
AnnaBridge	171:3a7713b1edbc	3389	/ / end of group PIT_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	3390
AnnaBridge	171:3a7713b1edbc	3391
AnnaBridge	171:3a7713b1edbc	3392	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3393	-- PMC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3394	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3395
AnnaBridge	171:3a7713b1edbc	3396	/**
AnnaBridge	171:3a7713b1edbc	3397	* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3398	* @{
AnnaBridge	171:3a7713b1edbc	3399	*/
AnnaBridge	171:3a7713b1edbc	3400
AnnaBridge	171:3a7713b1edbc	3401	/** PMC - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	3402	typedef struct {
AnnaBridge	171:3a7713b1edbc	3403	__IO uint8_t LVDSC1; /*< Low Voltage Detect Status and Control 1 Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	3404	__IO uint8_t LVDSC2; /*< Low Voltage Detect Status and Control 2 Register, offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	3405	__IO uint8_t REGSC; /*< Regulator Status and Control Register, offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	3406	} PMC_Type;
AnnaBridge	171:3a7713b1edbc	3407
AnnaBridge	171:3a7713b1edbc	3408	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3409	-- PMC Register Masks
AnnaBridge	171:3a7713b1edbc	3410	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3411
AnnaBridge	171:3a7713b1edbc	3412	/**
AnnaBridge	171:3a7713b1edbc	3413	* @addtogroup PMC_Register_Masks PMC Register Masks
AnnaBridge	171:3a7713b1edbc	3414	* @{
AnnaBridge	171:3a7713b1edbc	3415	*/
AnnaBridge	171:3a7713b1edbc	3416
AnnaBridge	171:3a7713b1edbc	3417	/* LVDSC1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3418	#define PMC_LVDSC1_LVDV_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	3419	#define PMC_LVDSC1_LVDV_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3420	#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
AnnaBridge	171:3a7713b1edbc	3421	#define PMC_LVDSC1_LVDRE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	3422	#define PMC_LVDSC1_LVDRE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	3423	#define PMC_LVDSC1_LVDIE_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	3424	#define PMC_LVDSC1_LVDIE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	3425	#define PMC_LVDSC1_LVDACK_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	3426	#define PMC_LVDSC1_LVDACK_SHIFT 6
AnnaBridge	171:3a7713b1edbc	3427	#define PMC_LVDSC1_LVDF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	3428	#define PMC_LVDSC1_LVDF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	3429	/* LVDSC2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3430	#define PMC_LVDSC2_LVWV_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	3431	#define PMC_LVDSC2_LVWV_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3432	#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
AnnaBridge	171:3a7713b1edbc	3433	#define PMC_LVDSC2_LVWIE_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	3434	#define PMC_LVDSC2_LVWIE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	3435	#define PMC_LVDSC2_LVWACK_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	3436	#define PMC_LVDSC2_LVWACK_SHIFT 6
AnnaBridge	171:3a7713b1edbc	3437	#define PMC_LVDSC2_LVWF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	3438	#define PMC_LVDSC2_LVWF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	3439	/* REGSC Bit Fields */
AnnaBridge	171:3a7713b1edbc	3440	#define PMC_REGSC_BGBE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3441	#define PMC_REGSC_BGBE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3442	#define PMC_REGSC_REGONS_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	3443	#define PMC_REGSC_REGONS_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3444	#define PMC_REGSC_ACKISO_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	3445	#define PMC_REGSC_ACKISO_SHIFT 3
AnnaBridge	171:3a7713b1edbc	3446
AnnaBridge	171:3a7713b1edbc	3447	/**
AnnaBridge	171:3a7713b1edbc	3448	* @}
AnnaBridge	171:3a7713b1edbc	3449	/ / end of group PMC_Register_Masks */
AnnaBridge	171:3a7713b1edbc	3450
AnnaBridge	171:3a7713b1edbc	3451
AnnaBridge	171:3a7713b1edbc	3452	/* PMC - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	3453	/** Peripheral PMC base address */
AnnaBridge	171:3a7713b1edbc	3454	#define PMC_BASE (0x4007D000u)
AnnaBridge	171:3a7713b1edbc	3455	/** Peripheral PMC base pointer */
AnnaBridge	171:3a7713b1edbc	3456	#define PMC ((PMC_Type *)PMC_BASE)
AnnaBridge	171:3a7713b1edbc	3457
AnnaBridge	171:3a7713b1edbc	3458	/**
AnnaBridge	171:3a7713b1edbc	3459	* @}
AnnaBridge	171:3a7713b1edbc	3460	/ / end of group PMC_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	3461
AnnaBridge	171:3a7713b1edbc	3462
AnnaBridge	171:3a7713b1edbc	3463	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3464	-- PORT Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3465	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3466
AnnaBridge	171:3a7713b1edbc	3467	/**
AnnaBridge	171:3a7713b1edbc	3468	* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3469	* @{
AnnaBridge	171:3a7713b1edbc	3470	*/
AnnaBridge	171:3a7713b1edbc	3471
AnnaBridge	171:3a7713b1edbc	3472	/** PORT - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	3473	typedef struct {
AnnaBridge	171:3a7713b1edbc	3474	__IO uint32_t PCR[32]; /*< Pin Control Register n, array offset: 0x0, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	3475	__O uint32_t GPCLR; /*< Global Pin Control Low Register, offset: 0x80 /
AnnaBridge	171:3a7713b1edbc	3476	__O uint32_t GPCHR; /*< Global Pin Control High Register, offset: 0x84 /
AnnaBridge	171:3a7713b1edbc	3477	uint8_t RESERVED_0[24];
AnnaBridge	171:3a7713b1edbc	3478	__IO uint32_t ISFR; /*< Interrupt Status Flag Register, offset: 0xA0 /
AnnaBridge	171:3a7713b1edbc	3479	uint8_t RESERVED_1[28];
AnnaBridge	171:3a7713b1edbc	3480	__IO uint32_t DFER; /*< Digital Filter Enable Register, offset: 0xC0 /
AnnaBridge	171:3a7713b1edbc	3481	__IO uint32_t DFCR; /*< Digital Filter Clock Register, offset: 0xC4 /
AnnaBridge	171:3a7713b1edbc	3482	__IO uint32_t DFWR; /*< Digital Filter Width Register, offset: 0xC8 /
AnnaBridge	171:3a7713b1edbc	3483	} PORT_Type;
AnnaBridge	171:3a7713b1edbc	3484
AnnaBridge	171:3a7713b1edbc	3485	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3486	-- PORT Register Masks
AnnaBridge	171:3a7713b1edbc	3487	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3488
AnnaBridge	171:3a7713b1edbc	3489	/**
AnnaBridge	171:3a7713b1edbc	3490	* @addtogroup PORT_Register_Masks PORT Register Masks
AnnaBridge	171:3a7713b1edbc	3491	* @{
AnnaBridge	171:3a7713b1edbc	3492	*/
AnnaBridge	171:3a7713b1edbc	3493
AnnaBridge	171:3a7713b1edbc	3494	/* PCR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3495	#define PORT_PCR_PS_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3496	#define PORT_PCR_PS_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3497	#define PORT_PCR_PE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3498	#define PORT_PCR_PE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3499	#define PORT_PCR_SRE_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	3500	#define PORT_PCR_SRE_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3501	#define PORT_PCR_PFE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	3502	#define PORT_PCR_PFE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	3503	#define PORT_PCR_ODE_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	3504	#define PORT_PCR_ODE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	3505	#define PORT_PCR_DSE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	3506	#define PORT_PCR_DSE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	3507	#define PORT_PCR_MUX_MASK 0x700u
AnnaBridge	171:3a7713b1edbc	3508	#define PORT_PCR_MUX_SHIFT 8
AnnaBridge	171:3a7713b1edbc	3509	#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
AnnaBridge	171:3a7713b1edbc	3510	#define PORT_PCR_LK_MASK 0x8000u
AnnaBridge	171:3a7713b1edbc	3511	#define PORT_PCR_LK_SHIFT 15
AnnaBridge	171:3a7713b1edbc	3512	#define PORT_PCR_IRQC_MASK 0xF0000u
AnnaBridge	171:3a7713b1edbc	3513	#define PORT_PCR_IRQC_SHIFT 16
AnnaBridge	171:3a7713b1edbc	3514	#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
AnnaBridge	171:3a7713b1edbc	3515	#define PORT_PCR_ISF_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	3516	#define PORT_PCR_ISF_SHIFT 24
AnnaBridge	171:3a7713b1edbc	3517	/* GPCLR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3518	#define PORT_GPCLR_GPWD_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	3519	#define PORT_GPCLR_GPWD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3520	#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
AnnaBridge	171:3a7713b1edbc	3521	#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	3522	#define PORT_GPCLR_GPWE_SHIFT 16
AnnaBridge	171:3a7713b1edbc	3523	#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
AnnaBridge	171:3a7713b1edbc	3524	/* GPCHR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3525	#define PORT_GPCHR_GPWD_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	3526	#define PORT_GPCHR_GPWD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3527	#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
AnnaBridge	171:3a7713b1edbc	3528	#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	3529	#define PORT_GPCHR_GPWE_SHIFT 16
AnnaBridge	171:3a7713b1edbc	3530	#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
AnnaBridge	171:3a7713b1edbc	3531	/* ISFR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3532	#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	3533	#define PORT_ISFR_ISF_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3534	#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
AnnaBridge	171:3a7713b1edbc	3535	/* DFER Bit Fields */
AnnaBridge	171:3a7713b1edbc	3536	#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	3537	#define PORT_DFER_DFE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3538	#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
AnnaBridge	171:3a7713b1edbc	3539	/* DFCR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3540	#define PORT_DFCR_CS_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3541	#define PORT_DFCR_CS_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3542	/* DFWR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3543	#define PORT_DFWR_FILT_MASK 0x1Fu
AnnaBridge	171:3a7713b1edbc	3544	#define PORT_DFWR_FILT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3545	#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
AnnaBridge	171:3a7713b1edbc	3546
AnnaBridge	171:3a7713b1edbc	3547	/**
AnnaBridge	171:3a7713b1edbc	3548	* @}
AnnaBridge	171:3a7713b1edbc	3549	/ / end of group PORT_Register_Masks */
AnnaBridge	171:3a7713b1edbc	3550
AnnaBridge	171:3a7713b1edbc	3551
AnnaBridge	171:3a7713b1edbc	3552	/* PORT - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	3553	/** Peripheral PORTA base address */
AnnaBridge	171:3a7713b1edbc	3554	#define PORTA_BASE (0x40049000u)
AnnaBridge	171:3a7713b1edbc	3555	/** Peripheral PORTA base pointer */
AnnaBridge	171:3a7713b1edbc	3556	#define PORTA ((PORT_Type *)PORTA_BASE)
AnnaBridge	171:3a7713b1edbc	3557	/** Peripheral PORTB base address */
AnnaBridge	171:3a7713b1edbc	3558	#define PORTB_BASE (0x4004A000u)
AnnaBridge	171:3a7713b1edbc	3559	/** Peripheral PORTB base pointer */
AnnaBridge	171:3a7713b1edbc	3560	#define PORTB ((PORT_Type *)PORTB_BASE)
AnnaBridge	171:3a7713b1edbc	3561	/** Peripheral PORTC base address */
AnnaBridge	171:3a7713b1edbc	3562	#define PORTC_BASE (0x4004B000u)
AnnaBridge	171:3a7713b1edbc	3563	/** Peripheral PORTC base pointer */
AnnaBridge	171:3a7713b1edbc	3564	#define PORTC ((PORT_Type *)PORTC_BASE)
AnnaBridge	171:3a7713b1edbc	3565	/** Peripheral PORTD base address */
AnnaBridge	171:3a7713b1edbc	3566	#define PORTD_BASE (0x4004C000u)
AnnaBridge	171:3a7713b1edbc	3567	/** Peripheral PORTD base pointer */
AnnaBridge	171:3a7713b1edbc	3568	#define PORTD ((PORT_Type *)PORTD_BASE)
AnnaBridge	171:3a7713b1edbc	3569	/** Peripheral PORTE base address */
AnnaBridge	171:3a7713b1edbc	3570	#define PORTE_BASE (0x4004D000u)
AnnaBridge	171:3a7713b1edbc	3571	/** Peripheral PORTE base pointer */
AnnaBridge	171:3a7713b1edbc	3572	#define PORTE ((PORT_Type *)PORTE_BASE)
AnnaBridge	171:3a7713b1edbc	3573
AnnaBridge	171:3a7713b1edbc	3574	/**
AnnaBridge	171:3a7713b1edbc	3575	* @}
AnnaBridge	171:3a7713b1edbc	3576	/ / end of group PORT_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	3577
AnnaBridge	171:3a7713b1edbc	3578
AnnaBridge	171:3a7713b1edbc	3579	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3580	-- RCM Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3581	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3582
AnnaBridge	171:3a7713b1edbc	3583	/**
AnnaBridge	171:3a7713b1edbc	3584	* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3585	* @{
AnnaBridge	171:3a7713b1edbc	3586	*/
AnnaBridge	171:3a7713b1edbc	3587
AnnaBridge	171:3a7713b1edbc	3588	/** RCM - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	3589	typedef struct {
AnnaBridge	171:3a7713b1edbc	3590	__I uint8_t SRS0; /*< System Reset Status Register 0, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	3591	__I uint8_t SRS1; /*< System Reset Status Register 1, offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	3592	uint8_t RESERVED_0[2];
AnnaBridge	171:3a7713b1edbc	3593	__IO uint8_t RPFC; /*< Reset Pin Filter Control Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	3594	__IO uint8_t RPFW; /*< Reset Pin Filter Width Register, offset: 0x5 /
AnnaBridge	171:3a7713b1edbc	3595	uint8_t RESERVED_1[1];
AnnaBridge	171:3a7713b1edbc	3596	__I uint8_t MR; /*< Mode Register, offset: 0x7 /
AnnaBridge	171:3a7713b1edbc	3597	} RCM_Type;
AnnaBridge	171:3a7713b1edbc	3598
AnnaBridge	171:3a7713b1edbc	3599	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3600	-- RCM Register Masks
AnnaBridge	171:3a7713b1edbc	3601	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3602
AnnaBridge	171:3a7713b1edbc	3603	/**
AnnaBridge	171:3a7713b1edbc	3604	* @addtogroup RCM_Register_Masks RCM Register Masks
AnnaBridge	171:3a7713b1edbc	3605	* @{
AnnaBridge	171:3a7713b1edbc	3606	*/
AnnaBridge	171:3a7713b1edbc	3607
AnnaBridge	171:3a7713b1edbc	3608	/* SRS0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3609	#define RCM_SRS0_WAKEUP_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3610	#define RCM_SRS0_WAKEUP_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3611	#define RCM_SRS0_LVD_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3612	#define RCM_SRS0_LVD_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3613	#define RCM_SRS0_LOC_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	3614	#define RCM_SRS0_LOC_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3615	#define RCM_SRS0_LOL_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	3616	#define RCM_SRS0_LOL_SHIFT 3
AnnaBridge	171:3a7713b1edbc	3617	#define RCM_SRS0_WDOG_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	3618	#define RCM_SRS0_WDOG_SHIFT 5
AnnaBridge	171:3a7713b1edbc	3619	#define RCM_SRS0_PIN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	3620	#define RCM_SRS0_PIN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	3621	#define RCM_SRS0_POR_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	3622	#define RCM_SRS0_POR_SHIFT 7
AnnaBridge	171:3a7713b1edbc	3623	/* SRS1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3624	#define RCM_SRS1_JTAG_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3625	#define RCM_SRS1_JTAG_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3626	#define RCM_SRS1_LOCKUP_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3627	#define RCM_SRS1_LOCKUP_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3628	#define RCM_SRS1_SW_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	3629	#define RCM_SRS1_SW_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3630	#define RCM_SRS1_MDM_AP_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	3631	#define RCM_SRS1_MDM_AP_SHIFT 3
AnnaBridge	171:3a7713b1edbc	3632	#define RCM_SRS1_EZPT_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	3633	#define RCM_SRS1_EZPT_SHIFT 4
AnnaBridge	171:3a7713b1edbc	3634	#define RCM_SRS1_SACKERR_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	3635	#define RCM_SRS1_SACKERR_SHIFT 5
AnnaBridge	171:3a7713b1edbc	3636	/* RPFC Bit Fields */
AnnaBridge	171:3a7713b1edbc	3637	#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	3638	#define RCM_RPFC_RSTFLTSRW_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3639	#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
AnnaBridge	171:3a7713b1edbc	3640	#define RCM_RPFC_RSTFLTSS_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	3641	#define RCM_RPFC_RSTFLTSS_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3642	/* RPFW Bit Fields */
AnnaBridge	171:3a7713b1edbc	3643	#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
AnnaBridge	171:3a7713b1edbc	3644	#define RCM_RPFW_RSTFLTSEL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3645	#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
AnnaBridge	171:3a7713b1edbc	3646	/* MR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3647	#define RCM_MR_EZP_MS_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3648	#define RCM_MR_EZP_MS_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3649
AnnaBridge	171:3a7713b1edbc	3650	/**
AnnaBridge	171:3a7713b1edbc	3651	* @}
AnnaBridge	171:3a7713b1edbc	3652	/ / end of group RCM_Register_Masks */
AnnaBridge	171:3a7713b1edbc	3653
AnnaBridge	171:3a7713b1edbc	3654
AnnaBridge	171:3a7713b1edbc	3655	/* RCM - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	3656	/** Peripheral RCM base address */
AnnaBridge	171:3a7713b1edbc	3657	#define RCM_BASE (0x4007F000u)
AnnaBridge	171:3a7713b1edbc	3658	/** Peripheral RCM base pointer */
AnnaBridge	171:3a7713b1edbc	3659	#define RCM ((RCM_Type *)RCM_BASE)
AnnaBridge	171:3a7713b1edbc	3660
AnnaBridge	171:3a7713b1edbc	3661	/**
AnnaBridge	171:3a7713b1edbc	3662	* @}
AnnaBridge	171:3a7713b1edbc	3663	/ / end of group RCM_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	3664
AnnaBridge	171:3a7713b1edbc	3665
AnnaBridge	171:3a7713b1edbc	3666	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3667	-- RFSYS Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3668	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3669
AnnaBridge	171:3a7713b1edbc	3670	/**
AnnaBridge	171:3a7713b1edbc	3671	* @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3672	* @{
AnnaBridge	171:3a7713b1edbc	3673	*/
AnnaBridge	171:3a7713b1edbc	3674
AnnaBridge	171:3a7713b1edbc	3675	/** RFSYS - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	3676	typedef struct {
AnnaBridge	171:3a7713b1edbc	3677	__IO uint32_t REG[8]; /*< Register file register, array offset: 0x0, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	3678	} RFSYS_Type;
AnnaBridge	171:3a7713b1edbc	3679
AnnaBridge	171:3a7713b1edbc	3680	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3681	-- RFSYS Register Masks
AnnaBridge	171:3a7713b1edbc	3682	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3683
AnnaBridge	171:3a7713b1edbc	3684	/**
AnnaBridge	171:3a7713b1edbc	3685	* @addtogroup RFSYS_Register_Masks RFSYS Register Masks
AnnaBridge	171:3a7713b1edbc	3686	* @{
AnnaBridge	171:3a7713b1edbc	3687	*/
AnnaBridge	171:3a7713b1edbc	3688
AnnaBridge	171:3a7713b1edbc	3689	/* REG Bit Fields */
AnnaBridge	171:3a7713b1edbc	3690	#define RFSYS_REG_LL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3691	#define RFSYS_REG_LL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3692	#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
AnnaBridge	171:3a7713b1edbc	3693	#define RFSYS_REG_LH_MASK 0xFF00u
AnnaBridge	171:3a7713b1edbc	3694	#define RFSYS_REG_LH_SHIFT 8
AnnaBridge	171:3a7713b1edbc	3695	#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
AnnaBridge	171:3a7713b1edbc	3696	#define RFSYS_REG_HL_MASK 0xFF0000u
AnnaBridge	171:3a7713b1edbc	3697	#define RFSYS_REG_HL_SHIFT 16
AnnaBridge	171:3a7713b1edbc	3698	#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
AnnaBridge	171:3a7713b1edbc	3699	#define RFSYS_REG_HH_MASK 0xFF000000u
AnnaBridge	171:3a7713b1edbc	3700	#define RFSYS_REG_HH_SHIFT 24
AnnaBridge	171:3a7713b1edbc	3701	#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
AnnaBridge	171:3a7713b1edbc	3702
AnnaBridge	171:3a7713b1edbc	3703	/**
AnnaBridge	171:3a7713b1edbc	3704	* @}
AnnaBridge	171:3a7713b1edbc	3705	/ / end of group RFSYS_Register_Masks */
AnnaBridge	171:3a7713b1edbc	3706
AnnaBridge	171:3a7713b1edbc	3707
AnnaBridge	171:3a7713b1edbc	3708	/* RFSYS - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	3709	/** Peripheral RFSYS base address */
AnnaBridge	171:3a7713b1edbc	3710	#define RFSYS_BASE (0x40041000u)
AnnaBridge	171:3a7713b1edbc	3711	/** Peripheral RFSYS base pointer */
AnnaBridge	171:3a7713b1edbc	3712	#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
AnnaBridge	171:3a7713b1edbc	3713
AnnaBridge	171:3a7713b1edbc	3714	/**
AnnaBridge	171:3a7713b1edbc	3715	* @}
AnnaBridge	171:3a7713b1edbc	3716	/ / end of group RFSYS_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	3717
AnnaBridge	171:3a7713b1edbc	3718
AnnaBridge	171:3a7713b1edbc	3719	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3720	-- RFVBAT Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3721	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3722
AnnaBridge	171:3a7713b1edbc	3723	/**
AnnaBridge	171:3a7713b1edbc	3724	* @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3725	* @{
AnnaBridge	171:3a7713b1edbc	3726	*/
AnnaBridge	171:3a7713b1edbc	3727
AnnaBridge	171:3a7713b1edbc	3728	/** RFVBAT - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	3729	typedef struct {
AnnaBridge	171:3a7713b1edbc	3730	__IO uint32_t REG[8]; /*< VBAT register file register, array offset: 0x0, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	3731	} RFVBAT_Type;
AnnaBridge	171:3a7713b1edbc	3732
AnnaBridge	171:3a7713b1edbc	3733	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3734	-- RFVBAT Register Masks
AnnaBridge	171:3a7713b1edbc	3735	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3736
AnnaBridge	171:3a7713b1edbc	3737	/**
AnnaBridge	171:3a7713b1edbc	3738	* @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
AnnaBridge	171:3a7713b1edbc	3739	* @{
AnnaBridge	171:3a7713b1edbc	3740	*/
AnnaBridge	171:3a7713b1edbc	3741
AnnaBridge	171:3a7713b1edbc	3742	/* REG Bit Fields */
AnnaBridge	171:3a7713b1edbc	3743	#define RFVBAT_REG_LL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3744	#define RFVBAT_REG_LL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3745	#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
AnnaBridge	171:3a7713b1edbc	3746	#define RFVBAT_REG_LH_MASK 0xFF00u
AnnaBridge	171:3a7713b1edbc	3747	#define RFVBAT_REG_LH_SHIFT 8
AnnaBridge	171:3a7713b1edbc	3748	#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
AnnaBridge	171:3a7713b1edbc	3749	#define RFVBAT_REG_HL_MASK 0xFF0000u
AnnaBridge	171:3a7713b1edbc	3750	#define RFVBAT_REG_HL_SHIFT 16
AnnaBridge	171:3a7713b1edbc	3751	#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
AnnaBridge	171:3a7713b1edbc	3752	#define RFVBAT_REG_HH_MASK 0xFF000000u
AnnaBridge	171:3a7713b1edbc	3753	#define RFVBAT_REG_HH_SHIFT 24
AnnaBridge	171:3a7713b1edbc	3754	#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
AnnaBridge	171:3a7713b1edbc	3755
AnnaBridge	171:3a7713b1edbc	3756	/**
AnnaBridge	171:3a7713b1edbc	3757	* @}
AnnaBridge	171:3a7713b1edbc	3758	/ / end of group RFVBAT_Register_Masks */
AnnaBridge	171:3a7713b1edbc	3759
AnnaBridge	171:3a7713b1edbc	3760
AnnaBridge	171:3a7713b1edbc	3761	/* RFVBAT - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	3762	/** Peripheral RFVBAT base address */
AnnaBridge	171:3a7713b1edbc	3763	#define RFVBAT_BASE (0x4003E000u)
AnnaBridge	171:3a7713b1edbc	3764	/** Peripheral RFVBAT base pointer */
AnnaBridge	171:3a7713b1edbc	3765	#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
AnnaBridge	171:3a7713b1edbc	3766
AnnaBridge	171:3a7713b1edbc	3767	/**
AnnaBridge	171:3a7713b1edbc	3768	* @}
AnnaBridge	171:3a7713b1edbc	3769	/ / end of group RFVBAT_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	3770
AnnaBridge	171:3a7713b1edbc	3771
AnnaBridge	171:3a7713b1edbc	3772	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3773	-- RTC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3774	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3775
AnnaBridge	171:3a7713b1edbc	3776	/**
AnnaBridge	171:3a7713b1edbc	3777	* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3778	* @{
AnnaBridge	171:3a7713b1edbc	3779	*/
AnnaBridge	171:3a7713b1edbc	3780
AnnaBridge	171:3a7713b1edbc	3781	/** RTC - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	3782	typedef struct {
AnnaBridge	171:3a7713b1edbc	3783	__IO uint32_t TSR; /*< RTC Time Seconds Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	3784	__IO uint32_t TPR; /*< RTC Time Prescaler Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	3785	__IO uint32_t TAR; /*< RTC Time Alarm Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	3786	__IO uint32_t TCR; /*< RTC Time Compensation Register, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	3787	__IO uint32_t CR; /*< RTC Control Register, offset: 0x10 /
AnnaBridge	171:3a7713b1edbc	3788	__IO uint32_t SR; /*< RTC Status Register, offset: 0x14 /
AnnaBridge	171:3a7713b1edbc	3789	__IO uint32_t LR; /*< RTC Lock Register, offset: 0x18 /
AnnaBridge	171:3a7713b1edbc	3790	__IO uint32_t IER; /*< RTC Interrupt Enable Register, offset: 0x1C /
AnnaBridge	171:3a7713b1edbc	3791	uint8_t RESERVED_0[2016];
AnnaBridge	171:3a7713b1edbc	3792	__IO uint32_t WAR; /*< RTC Write Access Register, offset: 0x800 /
AnnaBridge	171:3a7713b1edbc	3793	__IO uint32_t RAR; /*< RTC Read Access Register, offset: 0x804 /
AnnaBridge	171:3a7713b1edbc	3794	} RTC_Type;
AnnaBridge	171:3a7713b1edbc	3795
AnnaBridge	171:3a7713b1edbc	3796	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3797	-- RTC Register Masks
AnnaBridge	171:3a7713b1edbc	3798	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3799
AnnaBridge	171:3a7713b1edbc	3800	/**
AnnaBridge	171:3a7713b1edbc	3801	* @addtogroup RTC_Register_Masks RTC Register Masks
AnnaBridge	171:3a7713b1edbc	3802	* @{
AnnaBridge	171:3a7713b1edbc	3803	*/
AnnaBridge	171:3a7713b1edbc	3804
AnnaBridge	171:3a7713b1edbc	3805	/* TSR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3806	#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	3807	#define RTC_TSR_TSR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3808	#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
AnnaBridge	171:3a7713b1edbc	3809	/* TPR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3810	#define RTC_TPR_TPR_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	3811	#define RTC_TPR_TPR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3812	#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
AnnaBridge	171:3a7713b1edbc	3813	/* TAR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3814	#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	3815	#define RTC_TAR_TAR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3816	#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
AnnaBridge	171:3a7713b1edbc	3817	/* TCR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3818	#define RTC_TCR_TCR_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	3819	#define RTC_TCR_TCR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3820	#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
AnnaBridge	171:3a7713b1edbc	3821	#define RTC_TCR_CIR_MASK 0xFF00u
AnnaBridge	171:3a7713b1edbc	3822	#define RTC_TCR_CIR_SHIFT 8
AnnaBridge	171:3a7713b1edbc	3823	#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
AnnaBridge	171:3a7713b1edbc	3824	#define RTC_TCR_TCV_MASK 0xFF0000u
AnnaBridge	171:3a7713b1edbc	3825	#define RTC_TCR_TCV_SHIFT 16
AnnaBridge	171:3a7713b1edbc	3826	#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
AnnaBridge	171:3a7713b1edbc	3827	#define RTC_TCR_CIC_MASK 0xFF000000u
AnnaBridge	171:3a7713b1edbc	3828	#define RTC_TCR_CIC_SHIFT 24
AnnaBridge	171:3a7713b1edbc	3829	#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
AnnaBridge	171:3a7713b1edbc	3830	/* CR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3831	#define RTC_CR_SWR_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3832	#define RTC_CR_SWR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3833	#define RTC_CR_WPE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3834	#define RTC_CR_WPE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3835	#define RTC_CR_SUP_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	3836	#define RTC_CR_SUP_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3837	#define RTC_CR_UM_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	3838	#define RTC_CR_UM_SHIFT 3
AnnaBridge	171:3a7713b1edbc	3839	#define RTC_CR_OSCE_MASK 0x100u
AnnaBridge	171:3a7713b1edbc	3840	#define RTC_CR_OSCE_SHIFT 8
AnnaBridge	171:3a7713b1edbc	3841	#define RTC_CR_CLKO_MASK 0x200u
AnnaBridge	171:3a7713b1edbc	3842	#define RTC_CR_CLKO_SHIFT 9
AnnaBridge	171:3a7713b1edbc	3843	#define RTC_CR_SC16P_MASK 0x400u
AnnaBridge	171:3a7713b1edbc	3844	#define RTC_CR_SC16P_SHIFT 10
AnnaBridge	171:3a7713b1edbc	3845	#define RTC_CR_SC8P_MASK 0x800u
AnnaBridge	171:3a7713b1edbc	3846	#define RTC_CR_SC8P_SHIFT 11
AnnaBridge	171:3a7713b1edbc	3847	#define RTC_CR_SC4P_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	3848	#define RTC_CR_SC4P_SHIFT 12
AnnaBridge	171:3a7713b1edbc	3849	#define RTC_CR_SC2P_MASK 0x2000u
AnnaBridge	171:3a7713b1edbc	3850	#define RTC_CR_SC2P_SHIFT 13
AnnaBridge	171:3a7713b1edbc	3851	/* SR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3852	#define RTC_SR_TIF_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3853	#define RTC_SR_TIF_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3854	#define RTC_SR_TOF_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3855	#define RTC_SR_TOF_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3856	#define RTC_SR_TAF_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	3857	#define RTC_SR_TAF_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3858	#define RTC_SR_TCE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	3859	#define RTC_SR_TCE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	3860	/* LR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3861	#define RTC_LR_TCL_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	3862	#define RTC_LR_TCL_SHIFT 3
AnnaBridge	171:3a7713b1edbc	3863	#define RTC_LR_CRL_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	3864	#define RTC_LR_CRL_SHIFT 4
AnnaBridge	171:3a7713b1edbc	3865	#define RTC_LR_SRL_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	3866	#define RTC_LR_SRL_SHIFT 5
AnnaBridge	171:3a7713b1edbc	3867	#define RTC_LR_LRL_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	3868	#define RTC_LR_LRL_SHIFT 6
AnnaBridge	171:3a7713b1edbc	3869	/* IER Bit Fields */
AnnaBridge	171:3a7713b1edbc	3870	#define RTC_IER_TIIE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3871	#define RTC_IER_TIIE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3872	#define RTC_IER_TOIE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3873	#define RTC_IER_TOIE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3874	#define RTC_IER_TAIE_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	3875	#define RTC_IER_TAIE_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3876	#define RTC_IER_TSIE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	3877	#define RTC_IER_TSIE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	3878	/* WAR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3879	#define RTC_WAR_TSRW_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3880	#define RTC_WAR_TSRW_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3881	#define RTC_WAR_TPRW_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3882	#define RTC_WAR_TPRW_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3883	#define RTC_WAR_TARW_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	3884	#define RTC_WAR_TARW_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3885	#define RTC_WAR_TCRW_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	3886	#define RTC_WAR_TCRW_SHIFT 3
AnnaBridge	171:3a7713b1edbc	3887	#define RTC_WAR_CRW_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	3888	#define RTC_WAR_CRW_SHIFT 4
AnnaBridge	171:3a7713b1edbc	3889	#define RTC_WAR_SRW_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	3890	#define RTC_WAR_SRW_SHIFT 5
AnnaBridge	171:3a7713b1edbc	3891	#define RTC_WAR_LRW_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	3892	#define RTC_WAR_LRW_SHIFT 6
AnnaBridge	171:3a7713b1edbc	3893	#define RTC_WAR_IERW_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	3894	#define RTC_WAR_IERW_SHIFT 7
AnnaBridge	171:3a7713b1edbc	3895	/* RAR Bit Fields */
AnnaBridge	171:3a7713b1edbc	3896	#define RTC_RAR_TSRR_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	3897	#define RTC_RAR_TSRR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	3898	#define RTC_RAR_TPRR_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	3899	#define RTC_RAR_TPRR_SHIFT 1
AnnaBridge	171:3a7713b1edbc	3900	#define RTC_RAR_TARR_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	3901	#define RTC_RAR_TARR_SHIFT 2
AnnaBridge	171:3a7713b1edbc	3902	#define RTC_RAR_TCRR_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	3903	#define RTC_RAR_TCRR_SHIFT 3
AnnaBridge	171:3a7713b1edbc	3904	#define RTC_RAR_CRR_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	3905	#define RTC_RAR_CRR_SHIFT 4
AnnaBridge	171:3a7713b1edbc	3906	#define RTC_RAR_SRR_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	3907	#define RTC_RAR_SRR_SHIFT 5
AnnaBridge	171:3a7713b1edbc	3908	#define RTC_RAR_LRR_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	3909	#define RTC_RAR_LRR_SHIFT 6
AnnaBridge	171:3a7713b1edbc	3910	#define RTC_RAR_IERR_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	3911	#define RTC_RAR_IERR_SHIFT 7
AnnaBridge	171:3a7713b1edbc	3912
AnnaBridge	171:3a7713b1edbc	3913	/**
AnnaBridge	171:3a7713b1edbc	3914	* @}
AnnaBridge	171:3a7713b1edbc	3915	/ / end of group RTC_Register_Masks */
AnnaBridge	171:3a7713b1edbc	3916
AnnaBridge	171:3a7713b1edbc	3917
AnnaBridge	171:3a7713b1edbc	3918	/* RTC - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	3919	/** Peripheral RTC base address */
AnnaBridge	171:3a7713b1edbc	3920	#define RTC_BASE (0x4003D000u)
AnnaBridge	171:3a7713b1edbc	3921	/** Peripheral RTC base pointer */
AnnaBridge	171:3a7713b1edbc	3922	#define RTC ((RTC_Type *)RTC_BASE)
AnnaBridge	171:3a7713b1edbc	3923
AnnaBridge	171:3a7713b1edbc	3924	/**
AnnaBridge	171:3a7713b1edbc	3925	* @}
AnnaBridge	171:3a7713b1edbc	3926	/ / end of group RTC_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	3927
AnnaBridge	171:3a7713b1edbc	3928
AnnaBridge	171:3a7713b1edbc	3929	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3930	-- SIM Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3931	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3932
AnnaBridge	171:3a7713b1edbc	3933	/**
AnnaBridge	171:3a7713b1edbc	3934	* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	3935	* @{
AnnaBridge	171:3a7713b1edbc	3936	*/
AnnaBridge	171:3a7713b1edbc	3937
AnnaBridge	171:3a7713b1edbc	3938	/** SIM - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	3939	typedef struct {
AnnaBridge	171:3a7713b1edbc	3940	__IO uint32_t SOPT1; /*< System Options Register 1, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	3941	__IO uint32_t SOPT1CFG; /*< SOPT1 Configuration Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	3942	uint8_t RESERVED_0[4092];
AnnaBridge	171:3a7713b1edbc	3943	__IO uint32_t SOPT2; /*< System Options Register 2, offset: 0x1004 /
AnnaBridge	171:3a7713b1edbc	3944	uint8_t RESERVED_1[4];
AnnaBridge	171:3a7713b1edbc	3945	__IO uint32_t SOPT4; /*< System Options Register 4, offset: 0x100C /
AnnaBridge	171:3a7713b1edbc	3946	__IO uint32_t SOPT5; /*< System Options Register 5, offset: 0x1010 /
AnnaBridge	171:3a7713b1edbc	3947	uint8_t RESERVED_2[4];
AnnaBridge	171:3a7713b1edbc	3948	__IO uint32_t SOPT7; /*< System Options Register 7, offset: 0x1018 /
AnnaBridge	171:3a7713b1edbc	3949	uint8_t RESERVED_3[8];
AnnaBridge	171:3a7713b1edbc	3950	__I uint32_t SDID; /*< System Device Identification Register, offset: 0x1024 /
AnnaBridge	171:3a7713b1edbc	3951	uint8_t RESERVED_4[12];
AnnaBridge	171:3a7713b1edbc	3952	__IO uint32_t SCGC4; /*< System Clock Gating Control Register 4, offset: 0x1034 /
AnnaBridge	171:3a7713b1edbc	3953	__IO uint32_t SCGC5; /*< System Clock Gating Control Register 5, offset: 0x1038 /
AnnaBridge	171:3a7713b1edbc	3954	__IO uint32_t SCGC6; /*< System Clock Gating Control Register 6, offset: 0x103C /
AnnaBridge	171:3a7713b1edbc	3955	__IO uint32_t SCGC7; /*< System Clock Gating Control Register 7, offset: 0x1040 /
AnnaBridge	171:3a7713b1edbc	3956	__IO uint32_t CLKDIV1; /*< System Clock Divider Register 1, offset: 0x1044 /
AnnaBridge	171:3a7713b1edbc	3957	__IO uint32_t CLKDIV2; /*< System Clock Divider Register 2, offset: 0x1048 /
AnnaBridge	171:3a7713b1edbc	3958	__IO uint32_t FCFG1; /*< Flash Configuration Register 1, offset: 0x104C /
AnnaBridge	171:3a7713b1edbc	3959	__I uint32_t FCFG2; /*< Flash Configuration Register 2, offset: 0x1050 /
AnnaBridge	171:3a7713b1edbc	3960	__I uint32_t UIDH; /*< Unique Identification Register High, offset: 0x1054 /
AnnaBridge	171:3a7713b1edbc	3961	__I uint32_t UIDMH; /*< Unique Identification Register Mid-High, offset: 0x1058 /
AnnaBridge	171:3a7713b1edbc	3962	__I uint32_t UIDML; /*< Unique Identification Register Mid Low, offset: 0x105C /
AnnaBridge	171:3a7713b1edbc	3963	__I uint32_t UIDL; /*< Unique Identification Register Low, offset: 0x1060 /
AnnaBridge	171:3a7713b1edbc	3964	} SIM_Type;
AnnaBridge	171:3a7713b1edbc	3965
AnnaBridge	171:3a7713b1edbc	3966	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	3967	-- SIM Register Masks
AnnaBridge	171:3a7713b1edbc	3968	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	3969
AnnaBridge	171:3a7713b1edbc	3970	/**
AnnaBridge	171:3a7713b1edbc	3971	* @addtogroup SIM_Register_Masks SIM Register Masks
AnnaBridge	171:3a7713b1edbc	3972	* @{
AnnaBridge	171:3a7713b1edbc	3973	*/
AnnaBridge	171:3a7713b1edbc	3974
AnnaBridge	171:3a7713b1edbc	3975	/* SOPT1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3976	#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
AnnaBridge	171:3a7713b1edbc	3977	#define SIM_SOPT1_RAMSIZE_SHIFT 12
AnnaBridge	171:3a7713b1edbc	3978	#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
AnnaBridge	171:3a7713b1edbc	3979	#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
AnnaBridge	171:3a7713b1edbc	3980	#define SIM_SOPT1_OSC32KSEL_SHIFT 18
AnnaBridge	171:3a7713b1edbc	3981	#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
AnnaBridge	171:3a7713b1edbc	3982	#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
AnnaBridge	171:3a7713b1edbc	3983	#define SIM_SOPT1_USBVSTBY_SHIFT 29
AnnaBridge	171:3a7713b1edbc	3984	#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
AnnaBridge	171:3a7713b1edbc	3985	#define SIM_SOPT1_USBSSTBY_SHIFT 30
AnnaBridge	171:3a7713b1edbc	3986	#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
AnnaBridge	171:3a7713b1edbc	3987	#define SIM_SOPT1_USBREGEN_SHIFT 31
AnnaBridge	171:3a7713b1edbc	3988	/* SOPT1CFG Bit Fields */
AnnaBridge	171:3a7713b1edbc	3989	#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	3990	#define SIM_SOPT1CFG_URWE_SHIFT 24
AnnaBridge	171:3a7713b1edbc	3991	#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	3992	#define SIM_SOPT1CFG_UVSWE_SHIFT 25
AnnaBridge	171:3a7713b1edbc	3993	#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
AnnaBridge	171:3a7713b1edbc	3994	#define SIM_SOPT1CFG_USSWE_SHIFT 26
AnnaBridge	171:3a7713b1edbc	3995	/* SOPT2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	3996	#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	3997	#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
AnnaBridge	171:3a7713b1edbc	3998	#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
AnnaBridge	171:3a7713b1edbc	3999	#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4000	#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
AnnaBridge	171:3a7713b1edbc	4001	#define SIM_SOPT2_PTD7PAD_MASK 0x800u
AnnaBridge	171:3a7713b1edbc	4002	#define SIM_SOPT2_PTD7PAD_SHIFT 11
AnnaBridge	171:3a7713b1edbc	4003	#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	4004	#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
AnnaBridge	171:3a7713b1edbc	4005	#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
AnnaBridge	171:3a7713b1edbc	4006	#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4007	#define SIM_SOPT2_USBSRC_MASK 0x40000u
AnnaBridge	171:3a7713b1edbc	4008	#define SIM_SOPT2_USBSRC_SHIFT 18
AnnaBridge	171:3a7713b1edbc	4009	/* SOPT4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4010	#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4011	#define SIM_SOPT4_FTM0FLT0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4012	#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4013	#define SIM_SOPT4_FTM0FLT1_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4014	#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	4015	#define SIM_SOPT4_FTM1FLT0_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4016	#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
AnnaBridge	171:3a7713b1edbc	4017	#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
AnnaBridge	171:3a7713b1edbc	4018	#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
AnnaBridge	171:3a7713b1edbc	4019	#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	4020	#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
AnnaBridge	171:3a7713b1edbc	4021	#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	4022	#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
AnnaBridge	171:3a7713b1edbc	4023	#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
AnnaBridge	171:3a7713b1edbc	4024	#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
AnnaBridge	171:3a7713b1edbc	4025	/* SOPT5 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4026	#define SIM_SOPT5_UART0TXSRC_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4027	#define SIM_SOPT5_UART0TXSRC_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4028	#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
AnnaBridge	171:3a7713b1edbc	4029	#define SIM_SOPT5_UART0RXSRC_SHIFT 2
AnnaBridge	171:3a7713b1edbc	4030	#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
AnnaBridge	171:3a7713b1edbc	4031	#define SIM_SOPT5_UART1TXSRC_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	4032	#define SIM_SOPT5_UART1TXSRC_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4033	#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
AnnaBridge	171:3a7713b1edbc	4034	#define SIM_SOPT5_UART1RXSRC_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4035	#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
AnnaBridge	171:3a7713b1edbc	4036	/* SOPT7 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4037	#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	4038	#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4039	#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
AnnaBridge	171:3a7713b1edbc	4040	#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	4041	#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4042	#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4043	#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4044	/* SDID Bit Fields */
AnnaBridge	171:3a7713b1edbc	4045	#define SIM_SDID_PINID_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	4046	#define SIM_SDID_PINID_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4047	#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
AnnaBridge	171:3a7713b1edbc	4048	#define SIM_SDID_FAMID_MASK 0x70u
AnnaBridge	171:3a7713b1edbc	4049	#define SIM_SDID_FAMID_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4050	#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
AnnaBridge	171:3a7713b1edbc	4051	#define SIM_SDID_REVID_MASK 0xF000u
AnnaBridge	171:3a7713b1edbc	4052	#define SIM_SDID_REVID_SHIFT 12
AnnaBridge	171:3a7713b1edbc	4053	#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
AnnaBridge	171:3a7713b1edbc	4054	/* SCGC4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4055	#define SIM_SCGC4_EWM_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4056	#define SIM_SCGC4_EWM_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4057	#define SIM_SCGC4_CMT_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	4058	#define SIM_SCGC4_CMT_SHIFT 2
AnnaBridge	171:3a7713b1edbc	4059	#define SIM_SCGC4_I2C0_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4060	#define SIM_SCGC4_I2C0_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4061	#define SIM_SCGC4_UART0_MASK 0x400u
AnnaBridge	171:3a7713b1edbc	4062	#define SIM_SCGC4_UART0_SHIFT 10
AnnaBridge	171:3a7713b1edbc	4063	#define SIM_SCGC4_UART1_MASK 0x800u
AnnaBridge	171:3a7713b1edbc	4064	#define SIM_SCGC4_UART1_SHIFT 11
AnnaBridge	171:3a7713b1edbc	4065	#define SIM_SCGC4_UART2_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	4066	#define SIM_SCGC4_UART2_SHIFT 12
AnnaBridge	171:3a7713b1edbc	4067	#define SIM_SCGC4_USBOTG_MASK 0x40000u
AnnaBridge	171:3a7713b1edbc	4068	#define SIM_SCGC4_USBOTG_SHIFT 18
AnnaBridge	171:3a7713b1edbc	4069	#define SIM_SCGC4_CMP_MASK 0x80000u
AnnaBridge	171:3a7713b1edbc	4070	#define SIM_SCGC4_CMP_SHIFT 19
AnnaBridge	171:3a7713b1edbc	4071	#define SIM_SCGC4_VREF_MASK 0x100000u
AnnaBridge	171:3a7713b1edbc	4072	#define SIM_SCGC4_VREF_SHIFT 20
AnnaBridge	171:3a7713b1edbc	4073	/* SCGC5 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4074	#define SIM_SCGC5_LPTIMER_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4075	#define SIM_SCGC5_LPTIMER_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4076	#define SIM_SCGC5_TSI_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	4077	#define SIM_SCGC5_TSI_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4078	#define SIM_SCGC5_PORTA_MASK 0x200u
AnnaBridge	171:3a7713b1edbc	4079	#define SIM_SCGC5_PORTA_SHIFT 9
AnnaBridge	171:3a7713b1edbc	4080	#define SIM_SCGC5_PORTB_MASK 0x400u
AnnaBridge	171:3a7713b1edbc	4081	#define SIM_SCGC5_PORTB_SHIFT 10
AnnaBridge	171:3a7713b1edbc	4082	#define SIM_SCGC5_PORTC_MASK 0x800u
AnnaBridge	171:3a7713b1edbc	4083	#define SIM_SCGC5_PORTC_SHIFT 11
AnnaBridge	171:3a7713b1edbc	4084	#define SIM_SCGC5_PORTD_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	4085	#define SIM_SCGC5_PORTD_SHIFT 12
AnnaBridge	171:3a7713b1edbc	4086	#define SIM_SCGC5_PORTE_MASK 0x2000u
AnnaBridge	171:3a7713b1edbc	4087	#define SIM_SCGC5_PORTE_SHIFT 13
AnnaBridge	171:3a7713b1edbc	4088	/* SCGC6 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4089	#define SIM_SCGC6_FTFL_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4090	#define SIM_SCGC6_FTFL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4091	#define SIM_SCGC6_DMAMUX_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4092	#define SIM_SCGC6_DMAMUX_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4093	#define SIM_SCGC6_SPI0_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	4094	#define SIM_SCGC6_SPI0_SHIFT 12
AnnaBridge	171:3a7713b1edbc	4095	#define SIM_SCGC6_I2S_MASK 0x8000u
AnnaBridge	171:3a7713b1edbc	4096	#define SIM_SCGC6_I2S_SHIFT 15
AnnaBridge	171:3a7713b1edbc	4097	#define SIM_SCGC6_CRC_MASK 0x40000u
AnnaBridge	171:3a7713b1edbc	4098	#define SIM_SCGC6_CRC_SHIFT 18
AnnaBridge	171:3a7713b1edbc	4099	#define SIM_SCGC6_USBDCD_MASK 0x200000u
AnnaBridge	171:3a7713b1edbc	4100	#define SIM_SCGC6_USBDCD_SHIFT 21
AnnaBridge	171:3a7713b1edbc	4101	#define SIM_SCGC6_PDB_MASK 0x400000u
AnnaBridge	171:3a7713b1edbc	4102	#define SIM_SCGC6_PDB_SHIFT 22
AnnaBridge	171:3a7713b1edbc	4103	#define SIM_SCGC6_PIT_MASK 0x800000u
AnnaBridge	171:3a7713b1edbc	4104	#define SIM_SCGC6_PIT_SHIFT 23
AnnaBridge	171:3a7713b1edbc	4105	#define SIM_SCGC6_FTM0_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	4106	#define SIM_SCGC6_FTM0_SHIFT 24
AnnaBridge	171:3a7713b1edbc	4107	#define SIM_SCGC6_FTM1_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	4108	#define SIM_SCGC6_FTM1_SHIFT 25
AnnaBridge	171:3a7713b1edbc	4109	#define SIM_SCGC6_ADC0_MASK 0x8000000u
AnnaBridge	171:3a7713b1edbc	4110	#define SIM_SCGC6_ADC0_SHIFT 27
AnnaBridge	171:3a7713b1edbc	4111	#define SIM_SCGC6_RTC_MASK 0x20000000u
AnnaBridge	171:3a7713b1edbc	4112	#define SIM_SCGC6_RTC_SHIFT 29
AnnaBridge	171:3a7713b1edbc	4113	/* SCGC7 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4114	#define SIM_SCGC7_DMA_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4115	#define SIM_SCGC7_DMA_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4116	/* CLKDIV1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4117	#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
AnnaBridge	171:3a7713b1edbc	4118	#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4119	#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
AnnaBridge	171:3a7713b1edbc	4120	#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
AnnaBridge	171:3a7713b1edbc	4121	#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
AnnaBridge	171:3a7713b1edbc	4122	#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
AnnaBridge	171:3a7713b1edbc	4123	#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
AnnaBridge	171:3a7713b1edbc	4124	#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
AnnaBridge	171:3a7713b1edbc	4125	#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
AnnaBridge	171:3a7713b1edbc	4126	/* CLKDIV2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4127	#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4128	#define SIM_CLKDIV2_USBFRAC_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4129	#define SIM_CLKDIV2_USBDIV_MASK 0xEu
AnnaBridge	171:3a7713b1edbc	4130	#define SIM_CLKDIV2_USBDIV_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4131	#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
AnnaBridge	171:3a7713b1edbc	4132	/* FCFG1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4133	#define SIM_FCFG1_FLASHDIS_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4134	#define SIM_FCFG1_FLASHDIS_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4135	#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4136	#define SIM_FCFG1_FLASHDOZE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4137	#define SIM_FCFG1_DEPART_MASK 0xF00u
AnnaBridge	171:3a7713b1edbc	4138	#define SIM_FCFG1_DEPART_SHIFT 8
AnnaBridge	171:3a7713b1edbc	4139	#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
AnnaBridge	171:3a7713b1edbc	4140	#define SIM_FCFG1_EESIZE_MASK 0xF0000u
AnnaBridge	171:3a7713b1edbc	4141	#define SIM_FCFG1_EESIZE_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4142	#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
AnnaBridge	171:3a7713b1edbc	4143	#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
AnnaBridge	171:3a7713b1edbc	4144	#define SIM_FCFG1_PFSIZE_SHIFT 24
AnnaBridge	171:3a7713b1edbc	4145	#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
AnnaBridge	171:3a7713b1edbc	4146	#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
AnnaBridge	171:3a7713b1edbc	4147	#define SIM_FCFG1_NVMSIZE_SHIFT 28
AnnaBridge	171:3a7713b1edbc	4148	#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
AnnaBridge	171:3a7713b1edbc	4149	/* FCFG2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4150	#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
AnnaBridge	171:3a7713b1edbc	4151	#define SIM_FCFG2_MAXADDR1_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4152	#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
AnnaBridge	171:3a7713b1edbc	4153	#define SIM_FCFG2_PFLSH_MASK 0x800000u
AnnaBridge	171:3a7713b1edbc	4154	#define SIM_FCFG2_PFLSH_SHIFT 23
AnnaBridge	171:3a7713b1edbc	4155	#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
AnnaBridge	171:3a7713b1edbc	4156	#define SIM_FCFG2_MAXADDR0_SHIFT 24
AnnaBridge	171:3a7713b1edbc	4157	#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
AnnaBridge	171:3a7713b1edbc	4158	/* UIDH Bit Fields */
AnnaBridge	171:3a7713b1edbc	4159	#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	4160	#define SIM_UIDH_UID_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4161	#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
AnnaBridge	171:3a7713b1edbc	4162	/* UIDMH Bit Fields */
AnnaBridge	171:3a7713b1edbc	4163	#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	4164	#define SIM_UIDMH_UID_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4165	#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
AnnaBridge	171:3a7713b1edbc	4166	/* UIDML Bit Fields */
AnnaBridge	171:3a7713b1edbc	4167	#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	4168	#define SIM_UIDML_UID_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4169	#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
AnnaBridge	171:3a7713b1edbc	4170	/* UIDL Bit Fields */
AnnaBridge	171:3a7713b1edbc	4171	#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	4172	#define SIM_UIDL_UID_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4173	#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
AnnaBridge	171:3a7713b1edbc	4174
AnnaBridge	171:3a7713b1edbc	4175	/**
AnnaBridge	171:3a7713b1edbc	4176	* @}
AnnaBridge	171:3a7713b1edbc	4177	/ / end of group SIM_Register_Masks */
AnnaBridge	171:3a7713b1edbc	4178
AnnaBridge	171:3a7713b1edbc	4179
AnnaBridge	171:3a7713b1edbc	4180	/* SIM - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	4181	/** Peripheral SIM base address */
AnnaBridge	171:3a7713b1edbc	4182	#define SIM_BASE (0x40047000u)
AnnaBridge	171:3a7713b1edbc	4183	/** Peripheral SIM base pointer */
AnnaBridge	171:3a7713b1edbc	4184	#define SIM ((SIM_Type *)SIM_BASE)
AnnaBridge	171:3a7713b1edbc	4185
AnnaBridge	171:3a7713b1edbc	4186	/**
AnnaBridge	171:3a7713b1edbc	4187	* @}
AnnaBridge	171:3a7713b1edbc	4188	/ / end of group SIM_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	4189
AnnaBridge	171:3a7713b1edbc	4190
AnnaBridge	171:3a7713b1edbc	4191	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	4192	-- SMC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	4193	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	4194
AnnaBridge	171:3a7713b1edbc	4195	/**
AnnaBridge	171:3a7713b1edbc	4196	* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	4197	* @{
AnnaBridge	171:3a7713b1edbc	4198	*/
AnnaBridge	171:3a7713b1edbc	4199
AnnaBridge	171:3a7713b1edbc	4200	/** SMC - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	4201	typedef struct {
AnnaBridge	171:3a7713b1edbc	4202	__IO uint8_t PMPROT; /*< Power Mode Protection Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	4203	__IO uint8_t PMCTRL; /*< Power Mode Control Register, offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	4204	__IO uint8_t VLLSCTRL; /*< VLLS Control Register, offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	4205	__I uint8_t PMSTAT; /*< Power Mode Status Register, offset: 0x3 /
AnnaBridge	171:3a7713b1edbc	4206	} SMC_Type;
AnnaBridge	171:3a7713b1edbc	4207
AnnaBridge	171:3a7713b1edbc	4208	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	4209	-- SMC Register Masks
AnnaBridge	171:3a7713b1edbc	4210	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	4211
AnnaBridge	171:3a7713b1edbc	4212	/**
AnnaBridge	171:3a7713b1edbc	4213	* @addtogroup SMC_Register_Masks SMC Register Masks
AnnaBridge	171:3a7713b1edbc	4214	* @{
AnnaBridge	171:3a7713b1edbc	4215	*/
AnnaBridge	171:3a7713b1edbc	4216
AnnaBridge	171:3a7713b1edbc	4217	/* PMPROT Bit Fields */
AnnaBridge	171:3a7713b1edbc	4218	#define SMC_PMPROT_AVLLS_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4219	#define SMC_PMPROT_AVLLS_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4220	#define SMC_PMPROT_ALLS_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	4221	#define SMC_PMPROT_ALLS_SHIFT 3
AnnaBridge	171:3a7713b1edbc	4222	#define SMC_PMPROT_AVLP_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	4223	#define SMC_PMPROT_AVLP_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4224	/* PMCTRL Bit Fields */
AnnaBridge	171:3a7713b1edbc	4225	#define SMC_PMCTRL_STOPM_MASK 0x7u
AnnaBridge	171:3a7713b1edbc	4226	#define SMC_PMCTRL_STOPM_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4227	#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
AnnaBridge	171:3a7713b1edbc	4228	#define SMC_PMCTRL_STOPA_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	4229	#define SMC_PMCTRL_STOPA_SHIFT 3
AnnaBridge	171:3a7713b1edbc	4230	#define SMC_PMCTRL_RUNM_MASK 0x60u
AnnaBridge	171:3a7713b1edbc	4231	#define SMC_PMCTRL_RUNM_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4232	#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
AnnaBridge	171:3a7713b1edbc	4233	#define SMC_PMCTRL_LPWUI_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4234	#define SMC_PMCTRL_LPWUI_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4235	/* VLLSCTRL Bit Fields */
AnnaBridge	171:3a7713b1edbc	4236	#define SMC_VLLSCTRL_VLLSM_MASK 0x7u
AnnaBridge	171:3a7713b1edbc	4237	#define SMC_VLLSCTRL_VLLSM_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4238	#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
AnnaBridge	171:3a7713b1edbc	4239	#define SMC_VLLSCTRL_PORPO_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	4240	#define SMC_VLLSCTRL_PORPO_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4241	/* PMSTAT Bit Fields */
AnnaBridge	171:3a7713b1edbc	4242	#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
AnnaBridge	171:3a7713b1edbc	4243	#define SMC_PMSTAT_PMSTAT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4244	#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
AnnaBridge	171:3a7713b1edbc	4245
AnnaBridge	171:3a7713b1edbc	4246	/**
AnnaBridge	171:3a7713b1edbc	4247	* @}
AnnaBridge	171:3a7713b1edbc	4248	/ / end of group SMC_Register_Masks */
AnnaBridge	171:3a7713b1edbc	4249
AnnaBridge	171:3a7713b1edbc	4250
AnnaBridge	171:3a7713b1edbc	4251	/* SMC - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	4252	/** Peripheral SMC base address */
AnnaBridge	171:3a7713b1edbc	4253	#define SMC_BASE (0x4007E000u)
AnnaBridge	171:3a7713b1edbc	4254	/** Peripheral SMC base pointer */
AnnaBridge	171:3a7713b1edbc	4255	#define SMC ((SMC_Type *)SMC_BASE)
AnnaBridge	171:3a7713b1edbc	4256
AnnaBridge	171:3a7713b1edbc	4257	/**
AnnaBridge	171:3a7713b1edbc	4258	* @}
AnnaBridge	171:3a7713b1edbc	4259	/ / end of group SMC_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	4260
AnnaBridge	171:3a7713b1edbc	4261
AnnaBridge	171:3a7713b1edbc	4262	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	4263	-- SPI Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	4264	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	4265
AnnaBridge	171:3a7713b1edbc	4266	/**
AnnaBridge	171:3a7713b1edbc	4267	* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	4268	* @{
AnnaBridge	171:3a7713b1edbc	4269	*/
AnnaBridge	171:3a7713b1edbc	4270
AnnaBridge	171:3a7713b1edbc	4271	/** SPI - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	4272	typedef struct {
AnnaBridge	171:3a7713b1edbc	4273	__IO uint32_t MCR; /*< DSPI Module Configuration Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	4274	uint8_t RESERVED_0[4];
AnnaBridge	171:3a7713b1edbc	4275	__IO uint32_t TCR; /*< DSPI Transfer Count Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	4276	union { /* offset: 0xC */
AnnaBridge	171:3a7713b1edbc	4277	__IO uint32_t CTAR[2]; /*< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	4278	__IO uint32_t CTAR_SLAVE[1]; /*< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	4279	};
AnnaBridge	171:3a7713b1edbc	4280	uint8_t RESERVED_1[24];
AnnaBridge	171:3a7713b1edbc	4281	__IO uint32_t SR; /*< DSPI Status Register, offset: 0x2C /
AnnaBridge	171:3a7713b1edbc	4282	__IO uint32_t RSER; /*< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 /
AnnaBridge	171:3a7713b1edbc	4283	union { /* offset: 0x34 */
AnnaBridge	171:3a7713b1edbc	4284	__IO uint32_t PUSHR; /*< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 /
AnnaBridge	171:3a7713b1edbc	4285	__IO uint32_t PUSHR_SLAVE; /*< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 /
AnnaBridge	171:3a7713b1edbc	4286	};
AnnaBridge	171:3a7713b1edbc	4287	__I uint32_t POPR; /*< DSPI POP RX FIFO Register, offset: 0x38 /
AnnaBridge	171:3a7713b1edbc	4288	__I uint32_t TXFR0; /*< DSPI Transmit FIFO Registers, offset: 0x3C /
AnnaBridge	171:3a7713b1edbc	4289	__I uint32_t TXFR1; /*< DSPI Transmit FIFO Registers, offset: 0x40 /
AnnaBridge	171:3a7713b1edbc	4290	__I uint32_t TXFR2; /*< DSPI Transmit FIFO Registers, offset: 0x44 /
AnnaBridge	171:3a7713b1edbc	4291	__I uint32_t TXFR3; /*< DSPI Transmit FIFO Registers, offset: 0x48 /
AnnaBridge	171:3a7713b1edbc	4292	uint8_t RESERVED_2[48];
AnnaBridge	171:3a7713b1edbc	4293	__I uint32_t RXFR0; /*< DSPI Receive FIFO Registers, offset: 0x7C /
AnnaBridge	171:3a7713b1edbc	4294	__I uint32_t RXFR1; /*< DSPI Receive FIFO Registers, offset: 0x80 /
AnnaBridge	171:3a7713b1edbc	4295	__I uint32_t RXFR2; /*< DSPI Receive FIFO Registers, offset: 0x84 /
AnnaBridge	171:3a7713b1edbc	4296	__I uint32_t RXFR3; /*< DSPI Receive FIFO Registers, offset: 0x88 /
AnnaBridge	171:3a7713b1edbc	4297	} SPI_Type;
AnnaBridge	171:3a7713b1edbc	4298
AnnaBridge	171:3a7713b1edbc	4299	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	4300	-- SPI Register Masks
AnnaBridge	171:3a7713b1edbc	4301	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	4302
AnnaBridge	171:3a7713b1edbc	4303	/**
AnnaBridge	171:3a7713b1edbc	4304	* @addtogroup SPI_Register_Masks SPI Register Masks
AnnaBridge	171:3a7713b1edbc	4305	* @{
AnnaBridge	171:3a7713b1edbc	4306	*/
AnnaBridge	171:3a7713b1edbc	4307
AnnaBridge	171:3a7713b1edbc	4308	/* MCR Bit Fields */
AnnaBridge	171:3a7713b1edbc	4309	#define SPI_MCR_HALT_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4310	#define SPI_MCR_HALT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4311	#define SPI_MCR_SMPL_PT_MASK 0x300u
AnnaBridge	171:3a7713b1edbc	4312	#define SPI_MCR_SMPL_PT_SHIFT 8
AnnaBridge	171:3a7713b1edbc	4313	#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
AnnaBridge	171:3a7713b1edbc	4314	#define SPI_MCR_CLR_RXF_MASK 0x400u
AnnaBridge	171:3a7713b1edbc	4315	#define SPI_MCR_CLR_RXF_SHIFT 10
AnnaBridge	171:3a7713b1edbc	4316	#define SPI_MCR_CLR_TXF_MASK 0x800u
AnnaBridge	171:3a7713b1edbc	4317	#define SPI_MCR_CLR_TXF_SHIFT 11
AnnaBridge	171:3a7713b1edbc	4318	#define SPI_MCR_DIS_RXF_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	4319	#define SPI_MCR_DIS_RXF_SHIFT 12
AnnaBridge	171:3a7713b1edbc	4320	#define SPI_MCR_DIS_TXF_MASK 0x2000u
AnnaBridge	171:3a7713b1edbc	4321	#define SPI_MCR_DIS_TXF_SHIFT 13
AnnaBridge	171:3a7713b1edbc	4322	#define SPI_MCR_MDIS_MASK 0x4000u
AnnaBridge	171:3a7713b1edbc	4323	#define SPI_MCR_MDIS_SHIFT 14
AnnaBridge	171:3a7713b1edbc	4324	#define SPI_MCR_DOZE_MASK 0x8000u
AnnaBridge	171:3a7713b1edbc	4325	#define SPI_MCR_DOZE_SHIFT 15
AnnaBridge	171:3a7713b1edbc	4326	#define SPI_MCR_PCSIS_MASK 0x3F0000u
AnnaBridge	171:3a7713b1edbc	4327	#define SPI_MCR_PCSIS_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4328	#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
AnnaBridge	171:3a7713b1edbc	4329	#define SPI_MCR_ROOE_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	4330	#define SPI_MCR_ROOE_SHIFT 24
AnnaBridge	171:3a7713b1edbc	4331	#define SPI_MCR_PCSSE_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	4332	#define SPI_MCR_PCSSE_SHIFT 25
AnnaBridge	171:3a7713b1edbc	4333	#define SPI_MCR_MTFE_MASK 0x4000000u
AnnaBridge	171:3a7713b1edbc	4334	#define SPI_MCR_MTFE_SHIFT 26
AnnaBridge	171:3a7713b1edbc	4335	#define SPI_MCR_FRZ_MASK 0x8000000u
AnnaBridge	171:3a7713b1edbc	4336	#define SPI_MCR_FRZ_SHIFT 27
AnnaBridge	171:3a7713b1edbc	4337	#define SPI_MCR_DCONF_MASK 0x30000000u
AnnaBridge	171:3a7713b1edbc	4338	#define SPI_MCR_DCONF_SHIFT 28
AnnaBridge	171:3a7713b1edbc	4339	#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
AnnaBridge	171:3a7713b1edbc	4340	#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
AnnaBridge	171:3a7713b1edbc	4341	#define SPI_MCR_CONT_SCKE_SHIFT 30
AnnaBridge	171:3a7713b1edbc	4342	#define SPI_MCR_MSTR_MASK 0x80000000u
AnnaBridge	171:3a7713b1edbc	4343	#define SPI_MCR_MSTR_SHIFT 31
AnnaBridge	171:3a7713b1edbc	4344	/* TCR Bit Fields */
AnnaBridge	171:3a7713b1edbc	4345	#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4346	#define SPI_TCR_SPI_TCNT_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4347	#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
AnnaBridge	171:3a7713b1edbc	4348	/* CTAR Bit Fields */
AnnaBridge	171:3a7713b1edbc	4349	#define SPI_CTAR_BR_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	4350	#define SPI_CTAR_BR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4351	#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
AnnaBridge	171:3a7713b1edbc	4352	#define SPI_CTAR_DT_MASK 0xF0u
AnnaBridge	171:3a7713b1edbc	4353	#define SPI_CTAR_DT_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4354	#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
AnnaBridge	171:3a7713b1edbc	4355	#define SPI_CTAR_ASC_MASK 0xF00u
AnnaBridge	171:3a7713b1edbc	4356	#define SPI_CTAR_ASC_SHIFT 8
AnnaBridge	171:3a7713b1edbc	4357	#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
AnnaBridge	171:3a7713b1edbc	4358	#define SPI_CTAR_CSSCK_MASK 0xF000u
AnnaBridge	171:3a7713b1edbc	4359	#define SPI_CTAR_CSSCK_SHIFT 12
AnnaBridge	171:3a7713b1edbc	4360	#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
AnnaBridge	171:3a7713b1edbc	4361	#define SPI_CTAR_PBR_MASK 0x30000u
AnnaBridge	171:3a7713b1edbc	4362	#define SPI_CTAR_PBR_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4363	#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
AnnaBridge	171:3a7713b1edbc	4364	#define SPI_CTAR_PDT_MASK 0xC0000u
AnnaBridge	171:3a7713b1edbc	4365	#define SPI_CTAR_PDT_SHIFT 18
AnnaBridge	171:3a7713b1edbc	4366	#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
AnnaBridge	171:3a7713b1edbc	4367	#define SPI_CTAR_PASC_MASK 0x300000u
AnnaBridge	171:3a7713b1edbc	4368	#define SPI_CTAR_PASC_SHIFT 20
AnnaBridge	171:3a7713b1edbc	4369	#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
AnnaBridge	171:3a7713b1edbc	4370	#define SPI_CTAR_PCSSCK_MASK 0xC00000u
AnnaBridge	171:3a7713b1edbc	4371	#define SPI_CTAR_PCSSCK_SHIFT 22
AnnaBridge	171:3a7713b1edbc	4372	#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
AnnaBridge	171:3a7713b1edbc	4373	#define SPI_CTAR_LSBFE_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	4374	#define SPI_CTAR_LSBFE_SHIFT 24
AnnaBridge	171:3a7713b1edbc	4375	#define SPI_CTAR_CPHA_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	4376	#define SPI_CTAR_CPHA_SHIFT 25
AnnaBridge	171:3a7713b1edbc	4377	#define SPI_CTAR_CPOL_MASK 0x4000000u
AnnaBridge	171:3a7713b1edbc	4378	#define SPI_CTAR_CPOL_SHIFT 26
AnnaBridge	171:3a7713b1edbc	4379	#define SPI_CTAR_FMSZ_MASK 0x78000000u
AnnaBridge	171:3a7713b1edbc	4380	#define SPI_CTAR_FMSZ_SHIFT 27
AnnaBridge	171:3a7713b1edbc	4381	#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
AnnaBridge	171:3a7713b1edbc	4382	#define SPI_CTAR_DBR_MASK 0x80000000u
AnnaBridge	171:3a7713b1edbc	4383	#define SPI_CTAR_DBR_SHIFT 31
AnnaBridge	171:3a7713b1edbc	4384	/* CTAR_SLAVE Bit Fields */
AnnaBridge	171:3a7713b1edbc	4385	#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	4386	#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
AnnaBridge	171:3a7713b1edbc	4387	#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
AnnaBridge	171:3a7713b1edbc	4388	#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
AnnaBridge	171:3a7713b1edbc	4389	#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
AnnaBridge	171:3a7713b1edbc	4390	#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
AnnaBridge	171:3a7713b1edbc	4391	#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
AnnaBridge	171:3a7713b1edbc	4392	/* SR Bit Fields */
AnnaBridge	171:3a7713b1edbc	4393	#define SPI_SR_POPNXTPTR_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	4394	#define SPI_SR_POPNXTPTR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4395	#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
AnnaBridge	171:3a7713b1edbc	4396	#define SPI_SR_RXCTR_MASK 0xF0u
AnnaBridge	171:3a7713b1edbc	4397	#define SPI_SR_RXCTR_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4398	#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
AnnaBridge	171:3a7713b1edbc	4399	#define SPI_SR_TXNXTPTR_MASK 0xF00u
AnnaBridge	171:3a7713b1edbc	4400	#define SPI_SR_TXNXTPTR_SHIFT 8
AnnaBridge	171:3a7713b1edbc	4401	#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
AnnaBridge	171:3a7713b1edbc	4402	#define SPI_SR_TXCTR_MASK 0xF000u
AnnaBridge	171:3a7713b1edbc	4403	#define SPI_SR_TXCTR_SHIFT 12
AnnaBridge	171:3a7713b1edbc	4404	#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
AnnaBridge	171:3a7713b1edbc	4405	#define SPI_SR_RFDF_MASK 0x20000u
AnnaBridge	171:3a7713b1edbc	4406	#define SPI_SR_RFDF_SHIFT 17
AnnaBridge	171:3a7713b1edbc	4407	#define SPI_SR_RFOF_MASK 0x80000u
AnnaBridge	171:3a7713b1edbc	4408	#define SPI_SR_RFOF_SHIFT 19
AnnaBridge	171:3a7713b1edbc	4409	#define SPI_SR_TFFF_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	4410	#define SPI_SR_TFFF_SHIFT 25
AnnaBridge	171:3a7713b1edbc	4411	#define SPI_SR_TFUF_MASK 0x8000000u
AnnaBridge	171:3a7713b1edbc	4412	#define SPI_SR_TFUF_SHIFT 27
AnnaBridge	171:3a7713b1edbc	4413	#define SPI_SR_EOQF_MASK 0x10000000u
AnnaBridge	171:3a7713b1edbc	4414	#define SPI_SR_EOQF_SHIFT 28
AnnaBridge	171:3a7713b1edbc	4415	#define SPI_SR_TXRXS_MASK 0x40000000u
AnnaBridge	171:3a7713b1edbc	4416	#define SPI_SR_TXRXS_SHIFT 30
AnnaBridge	171:3a7713b1edbc	4417	#define SPI_SR_TCF_MASK 0x80000000u
AnnaBridge	171:3a7713b1edbc	4418	#define SPI_SR_TCF_SHIFT 31
AnnaBridge	171:3a7713b1edbc	4419	/* RSER Bit Fields */
AnnaBridge	171:3a7713b1edbc	4420	#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
AnnaBridge	171:3a7713b1edbc	4421	#define SPI_RSER_RFDF_DIRS_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4422	#define SPI_RSER_RFDF_RE_MASK 0x20000u
AnnaBridge	171:3a7713b1edbc	4423	#define SPI_RSER_RFDF_RE_SHIFT 17
AnnaBridge	171:3a7713b1edbc	4424	#define SPI_RSER_RFOF_RE_MASK 0x80000u
AnnaBridge	171:3a7713b1edbc	4425	#define SPI_RSER_RFOF_RE_SHIFT 19
AnnaBridge	171:3a7713b1edbc	4426	#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	4427	#define SPI_RSER_TFFF_DIRS_SHIFT 24
AnnaBridge	171:3a7713b1edbc	4428	#define SPI_RSER_TFFF_RE_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	4429	#define SPI_RSER_TFFF_RE_SHIFT 25
AnnaBridge	171:3a7713b1edbc	4430	#define SPI_RSER_TFUF_RE_MASK 0x8000000u
AnnaBridge	171:3a7713b1edbc	4431	#define SPI_RSER_TFUF_RE_SHIFT 27
AnnaBridge	171:3a7713b1edbc	4432	#define SPI_RSER_EOQF_RE_MASK 0x10000000u
AnnaBridge	171:3a7713b1edbc	4433	#define SPI_RSER_EOQF_RE_SHIFT 28
AnnaBridge	171:3a7713b1edbc	4434	#define SPI_RSER_TCF_RE_MASK 0x80000000u
AnnaBridge	171:3a7713b1edbc	4435	#define SPI_RSER_TCF_RE_SHIFT 31
AnnaBridge	171:3a7713b1edbc	4436	/* PUSHR Bit Fields */
AnnaBridge	171:3a7713b1edbc	4437	#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4438	#define SPI_PUSHR_TXDATA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4439	#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4440	#define SPI_PUSHR_PCS_MASK 0x3F0000u
AnnaBridge	171:3a7713b1edbc	4441	#define SPI_PUSHR_PCS_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4442	#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
AnnaBridge	171:3a7713b1edbc	4443	#define SPI_PUSHR_CTCNT_MASK 0x4000000u
AnnaBridge	171:3a7713b1edbc	4444	#define SPI_PUSHR_CTCNT_SHIFT 26
AnnaBridge	171:3a7713b1edbc	4445	#define SPI_PUSHR_EOQ_MASK 0x8000000u
AnnaBridge	171:3a7713b1edbc	4446	#define SPI_PUSHR_EOQ_SHIFT 27
AnnaBridge	171:3a7713b1edbc	4447	#define SPI_PUSHR_CTAS_MASK 0x70000000u
AnnaBridge	171:3a7713b1edbc	4448	#define SPI_PUSHR_CTAS_SHIFT 28
AnnaBridge	171:3a7713b1edbc	4449	#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
AnnaBridge	171:3a7713b1edbc	4450	#define SPI_PUSHR_CONT_MASK 0x80000000u
AnnaBridge	171:3a7713b1edbc	4451	#define SPI_PUSHR_CONT_SHIFT 31
AnnaBridge	171:3a7713b1edbc	4452	/* PUSHR_SLAVE Bit Fields */
AnnaBridge	171:3a7713b1edbc	4453	#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	4454	#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4455	#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4456	/* POPR Bit Fields */
AnnaBridge	171:3a7713b1edbc	4457	#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	4458	#define SPI_POPR_RXDATA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4459	#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4460	/* TXFR0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4461	#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4462	#define SPI_TXFR0_TXDATA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4463	#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4464	#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4465	#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4466	#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4467	/* TXFR1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4468	#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4469	#define SPI_TXFR1_TXDATA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4470	#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4471	#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4472	#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4473	#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4474	/* TXFR2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4475	#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4476	#define SPI_TXFR2_TXDATA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4477	#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4478	#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4479	#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4480	#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4481	/* TXFR3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4482	#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4483	#define SPI_TXFR3_TXDATA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4484	#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4485	#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4486	#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4487	#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4488	/* RXFR0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4489	#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	4490	#define SPI_RXFR0_RXDATA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4491	#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4492	/* RXFR1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4493	#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	4494	#define SPI_RXFR1_RXDATA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4495	#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4496	/* RXFR2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4497	#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	4498	#define SPI_RXFR2_RXDATA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4499	#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4500	/* RXFR3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4501	#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
AnnaBridge	171:3a7713b1edbc	4502	#define SPI_RXFR3_RXDATA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4503	#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
AnnaBridge	171:3a7713b1edbc	4504
AnnaBridge	171:3a7713b1edbc	4505	/**
AnnaBridge	171:3a7713b1edbc	4506	* @}
AnnaBridge	171:3a7713b1edbc	4507	/ / end of group SPI_Register_Masks */
AnnaBridge	171:3a7713b1edbc	4508
AnnaBridge	171:3a7713b1edbc	4509
AnnaBridge	171:3a7713b1edbc	4510	/* SPI - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	4511	/** Peripheral SPI0 base address */
AnnaBridge	171:3a7713b1edbc	4512	#define SPI0_BASE (0x4002C000u)
AnnaBridge	171:3a7713b1edbc	4513	/** Peripheral SPI0 base pointer */
AnnaBridge	171:3a7713b1edbc	4514	#define SPI0 ((SPI_Type *)SPI0_BASE)
AnnaBridge	171:3a7713b1edbc	4515
AnnaBridge	171:3a7713b1edbc	4516	/**
AnnaBridge	171:3a7713b1edbc	4517	* @}
AnnaBridge	171:3a7713b1edbc	4518	/ / end of group SPI_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	4519
AnnaBridge	171:3a7713b1edbc	4520
AnnaBridge	171:3a7713b1edbc	4521	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	4522	-- TSI Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	4523	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	4524
AnnaBridge	171:3a7713b1edbc	4525	/**
AnnaBridge	171:3a7713b1edbc	4526	* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	4527	* @{
AnnaBridge	171:3a7713b1edbc	4528	*/
AnnaBridge	171:3a7713b1edbc	4529
AnnaBridge	171:3a7713b1edbc	4530	/** TSI - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	4531	typedef struct {
AnnaBridge	171:3a7713b1edbc	4532	__IO uint32_t GENCS; /*< General Control and Status Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	4533	__IO uint32_t SCANC; /*< SCAN Control Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	4534	__IO uint32_t PEN; /*< Pin Enable Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	4535	__I uint32_t WUCNTR; /*< Wake-Up Channel Counter Register, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	4536	uint8_t RESERVED_0[240];
AnnaBridge	171:3a7713b1edbc	4537	__I uint32_t CNTR1; /*< Counter Register, offset: 0x100 /
AnnaBridge	171:3a7713b1edbc	4538	__I uint32_t CNTR3; /*< Counter Register, offset: 0x104 /
AnnaBridge	171:3a7713b1edbc	4539	__I uint32_t CNTR5; /*< Counter Register, offset: 0x108 /
AnnaBridge	171:3a7713b1edbc	4540	__I uint32_t CNTR7; /*< Counter Register, offset: 0x10C /
AnnaBridge	171:3a7713b1edbc	4541	__I uint32_t CNTR9; /*< Counter Register, offset: 0x110 /
AnnaBridge	171:3a7713b1edbc	4542	__I uint32_t CNTR11; /*< Counter Register, offset: 0x114 /
AnnaBridge	171:3a7713b1edbc	4543	__I uint32_t CNTR13; /*< Counter Register, offset: 0x118 /
AnnaBridge	171:3a7713b1edbc	4544	__I uint32_t CNTR15; /*< Counter Register, offset: 0x11C /
AnnaBridge	171:3a7713b1edbc	4545	__IO uint32_t THRESHOLD; /*< Low Power Channel Threshold Register, offset: 0x120 /
AnnaBridge	171:3a7713b1edbc	4546	} TSI_Type;
AnnaBridge	171:3a7713b1edbc	4547
AnnaBridge	171:3a7713b1edbc	4548	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	4549	-- TSI Register Masks
AnnaBridge	171:3a7713b1edbc	4550	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	4551
AnnaBridge	171:3a7713b1edbc	4552	/**
AnnaBridge	171:3a7713b1edbc	4553	* @addtogroup TSI_Register_Masks TSI Register Masks
AnnaBridge	171:3a7713b1edbc	4554	* @{
AnnaBridge	171:3a7713b1edbc	4555	*/
AnnaBridge	171:3a7713b1edbc	4556
AnnaBridge	171:3a7713b1edbc	4557	/* GENCS Bit Fields */
AnnaBridge	171:3a7713b1edbc	4558	#define TSI_GENCS_STPE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4559	#define TSI_GENCS_STPE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4560	#define TSI_GENCS_STM_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4561	#define TSI_GENCS_STM_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4562	#define TSI_GENCS_ESOR_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	4563	#define TSI_GENCS_ESOR_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4564	#define TSI_GENCS_ERIE_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	4565	#define TSI_GENCS_ERIE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4566	#define TSI_GENCS_TSIIE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4567	#define TSI_GENCS_TSIIE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4568	#define TSI_GENCS_TSIEN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4569	#define TSI_GENCS_TSIEN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4570	#define TSI_GENCS_SWTS_MASK 0x100u
AnnaBridge	171:3a7713b1edbc	4571	#define TSI_GENCS_SWTS_SHIFT 8
AnnaBridge	171:3a7713b1edbc	4572	#define TSI_GENCS_SCNIP_MASK 0x200u
AnnaBridge	171:3a7713b1edbc	4573	#define TSI_GENCS_SCNIP_SHIFT 9
AnnaBridge	171:3a7713b1edbc	4574	#define TSI_GENCS_OVRF_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	4575	#define TSI_GENCS_OVRF_SHIFT 12
AnnaBridge	171:3a7713b1edbc	4576	#define TSI_GENCS_EXTERF_MASK 0x2000u
AnnaBridge	171:3a7713b1edbc	4577	#define TSI_GENCS_EXTERF_SHIFT 13
AnnaBridge	171:3a7713b1edbc	4578	#define TSI_GENCS_OUTRGF_MASK 0x4000u
AnnaBridge	171:3a7713b1edbc	4579	#define TSI_GENCS_OUTRGF_SHIFT 14
AnnaBridge	171:3a7713b1edbc	4580	#define TSI_GENCS_EOSF_MASK 0x8000u
AnnaBridge	171:3a7713b1edbc	4581	#define TSI_GENCS_EOSF_SHIFT 15
AnnaBridge	171:3a7713b1edbc	4582	#define TSI_GENCS_PS_MASK 0x70000u
AnnaBridge	171:3a7713b1edbc	4583	#define TSI_GENCS_PS_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4584	#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
AnnaBridge	171:3a7713b1edbc	4585	#define TSI_GENCS_NSCN_MASK 0xF80000u
AnnaBridge	171:3a7713b1edbc	4586	#define TSI_GENCS_NSCN_SHIFT 19
AnnaBridge	171:3a7713b1edbc	4587	#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
AnnaBridge	171:3a7713b1edbc	4588	#define TSI_GENCS_LPSCNITV_MASK 0xF000000u
AnnaBridge	171:3a7713b1edbc	4589	#define TSI_GENCS_LPSCNITV_SHIFT 24
AnnaBridge	171:3a7713b1edbc	4590	#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
AnnaBridge	171:3a7713b1edbc	4591	#define TSI_GENCS_LPCLKS_MASK 0x10000000u
AnnaBridge	171:3a7713b1edbc	4592	#define TSI_GENCS_LPCLKS_SHIFT 28
AnnaBridge	171:3a7713b1edbc	4593	/* SCANC Bit Fields */
AnnaBridge	171:3a7713b1edbc	4594	#define TSI_SCANC_AMPSC_MASK 0x7u
AnnaBridge	171:3a7713b1edbc	4595	#define TSI_SCANC_AMPSC_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4596	#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
AnnaBridge	171:3a7713b1edbc	4597	#define TSI_SCANC_AMCLKS_MASK 0x18u
AnnaBridge	171:3a7713b1edbc	4598	#define TSI_SCANC_AMCLKS_SHIFT 3
AnnaBridge	171:3a7713b1edbc	4599	#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
AnnaBridge	171:3a7713b1edbc	4600	#define TSI_SCANC_SMOD_MASK 0xFF00u
AnnaBridge	171:3a7713b1edbc	4601	#define TSI_SCANC_SMOD_SHIFT 8
AnnaBridge	171:3a7713b1edbc	4602	#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
AnnaBridge	171:3a7713b1edbc	4603	#define TSI_SCANC_EXTCHRG_MASK 0xF0000u
AnnaBridge	171:3a7713b1edbc	4604	#define TSI_SCANC_EXTCHRG_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4605	#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
AnnaBridge	171:3a7713b1edbc	4606	#define TSI_SCANC_REFCHRG_MASK 0xF000000u
AnnaBridge	171:3a7713b1edbc	4607	#define TSI_SCANC_REFCHRG_SHIFT 24
AnnaBridge	171:3a7713b1edbc	4608	#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
AnnaBridge	171:3a7713b1edbc	4609	/* PEN Bit Fields */
AnnaBridge	171:3a7713b1edbc	4610	#define TSI_PEN_PEN0_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4611	#define TSI_PEN_PEN0_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4612	#define TSI_PEN_PEN1_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4613	#define TSI_PEN_PEN1_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4614	#define TSI_PEN_PEN2_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	4615	#define TSI_PEN_PEN2_SHIFT 2
AnnaBridge	171:3a7713b1edbc	4616	#define TSI_PEN_PEN3_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	4617	#define TSI_PEN_PEN3_SHIFT 3
AnnaBridge	171:3a7713b1edbc	4618	#define TSI_PEN_PEN4_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	4619	#define TSI_PEN_PEN4_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4620	#define TSI_PEN_PEN5_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	4621	#define TSI_PEN_PEN5_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4622	#define TSI_PEN_PEN6_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4623	#define TSI_PEN_PEN6_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4624	#define TSI_PEN_PEN7_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4625	#define TSI_PEN_PEN7_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4626	#define TSI_PEN_PEN8_MASK 0x100u
AnnaBridge	171:3a7713b1edbc	4627	#define TSI_PEN_PEN8_SHIFT 8
AnnaBridge	171:3a7713b1edbc	4628	#define TSI_PEN_PEN9_MASK 0x200u
AnnaBridge	171:3a7713b1edbc	4629	#define TSI_PEN_PEN9_SHIFT 9
AnnaBridge	171:3a7713b1edbc	4630	#define TSI_PEN_PEN10_MASK 0x400u
AnnaBridge	171:3a7713b1edbc	4631	#define TSI_PEN_PEN10_SHIFT 10
AnnaBridge	171:3a7713b1edbc	4632	#define TSI_PEN_PEN11_MASK 0x800u
AnnaBridge	171:3a7713b1edbc	4633	#define TSI_PEN_PEN11_SHIFT 11
AnnaBridge	171:3a7713b1edbc	4634	#define TSI_PEN_PEN12_MASK 0x1000u
AnnaBridge	171:3a7713b1edbc	4635	#define TSI_PEN_PEN12_SHIFT 12
AnnaBridge	171:3a7713b1edbc	4636	#define TSI_PEN_PEN13_MASK 0x2000u
AnnaBridge	171:3a7713b1edbc	4637	#define TSI_PEN_PEN13_SHIFT 13
AnnaBridge	171:3a7713b1edbc	4638	#define TSI_PEN_PEN14_MASK 0x4000u
AnnaBridge	171:3a7713b1edbc	4639	#define TSI_PEN_PEN14_SHIFT 14
AnnaBridge	171:3a7713b1edbc	4640	#define TSI_PEN_PEN15_MASK 0x8000u
AnnaBridge	171:3a7713b1edbc	4641	#define TSI_PEN_PEN15_SHIFT 15
AnnaBridge	171:3a7713b1edbc	4642	#define TSI_PEN_LPSP_MASK 0xF0000u
AnnaBridge	171:3a7713b1edbc	4643	#define TSI_PEN_LPSP_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4644	#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
AnnaBridge	171:3a7713b1edbc	4645	/* WUCNTR Bit Fields */
AnnaBridge	171:3a7713b1edbc	4646	#define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4647	#define TSI_WUCNTR_WUCNT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4648	#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
AnnaBridge	171:3a7713b1edbc	4649	/* CNTR1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4650	#define TSI_CNTR1_CTN1_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4651	#define TSI_CNTR1_CTN1_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4652	#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
AnnaBridge	171:3a7713b1edbc	4653	#define TSI_CNTR1_CTN_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4654	#define TSI_CNTR1_CTN_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4655	#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
AnnaBridge	171:3a7713b1edbc	4656	/* CNTR3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4657	#define TSI_CNTR3_CTN1_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4658	#define TSI_CNTR3_CTN1_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4659	#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
AnnaBridge	171:3a7713b1edbc	4660	#define TSI_CNTR3_CTN_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4661	#define TSI_CNTR3_CTN_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4662	#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
AnnaBridge	171:3a7713b1edbc	4663	/* CNTR5 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4664	#define TSI_CNTR5_CTN1_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4665	#define TSI_CNTR5_CTN1_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4666	#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
AnnaBridge	171:3a7713b1edbc	4667	#define TSI_CNTR5_CTN_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4668	#define TSI_CNTR5_CTN_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4669	#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
AnnaBridge	171:3a7713b1edbc	4670	/* CNTR7 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4671	#define TSI_CNTR7_CTN1_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4672	#define TSI_CNTR7_CTN1_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4673	#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
AnnaBridge	171:3a7713b1edbc	4674	#define TSI_CNTR7_CTN_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4675	#define TSI_CNTR7_CTN_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4676	#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
AnnaBridge	171:3a7713b1edbc	4677	/* CNTR9 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4678	#define TSI_CNTR9_CTN1_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4679	#define TSI_CNTR9_CTN1_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4680	#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
AnnaBridge	171:3a7713b1edbc	4681	#define TSI_CNTR9_CTN_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4682	#define TSI_CNTR9_CTN_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4683	#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
AnnaBridge	171:3a7713b1edbc	4684	/* CNTR11 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4685	#define TSI_CNTR11_CTN1_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4686	#define TSI_CNTR11_CTN1_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4687	#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
AnnaBridge	171:3a7713b1edbc	4688	#define TSI_CNTR11_CTN_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4689	#define TSI_CNTR11_CTN_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4690	#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
AnnaBridge	171:3a7713b1edbc	4691	/* CNTR13 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4692	#define TSI_CNTR13_CTN1_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4693	#define TSI_CNTR13_CTN1_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4694	#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
AnnaBridge	171:3a7713b1edbc	4695	#define TSI_CNTR13_CTN_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4696	#define TSI_CNTR13_CTN_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4697	#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
AnnaBridge	171:3a7713b1edbc	4698	/* CNTR15 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4699	#define TSI_CNTR15_CTN1_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4700	#define TSI_CNTR15_CTN1_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4701	#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
AnnaBridge	171:3a7713b1edbc	4702	#define TSI_CNTR15_CTN_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4703	#define TSI_CNTR15_CTN_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4704	#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
AnnaBridge	171:3a7713b1edbc	4705	/* THRESHOLD Bit Fields */
AnnaBridge	171:3a7713b1edbc	4706	#define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	4707	#define TSI_THRESHOLD_HTHH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4708	#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
AnnaBridge	171:3a7713b1edbc	4709	#define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
AnnaBridge	171:3a7713b1edbc	4710	#define TSI_THRESHOLD_LTHH_SHIFT 16
AnnaBridge	171:3a7713b1edbc	4711	#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
AnnaBridge	171:3a7713b1edbc	4712
AnnaBridge	171:3a7713b1edbc	4713	/**
AnnaBridge	171:3a7713b1edbc	4714	* @}
AnnaBridge	171:3a7713b1edbc	4715	/ / end of group TSI_Register_Masks */
AnnaBridge	171:3a7713b1edbc	4716
AnnaBridge	171:3a7713b1edbc	4717
AnnaBridge	171:3a7713b1edbc	4718	/* TSI - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	4719	/** Peripheral TSI0 base address */
AnnaBridge	171:3a7713b1edbc	4720	#define TSI0_BASE (0x40045000u)
AnnaBridge	171:3a7713b1edbc	4721	/** Peripheral TSI0 base pointer */
AnnaBridge	171:3a7713b1edbc	4722	#define TSI0 ((TSI_Type *)TSI0_BASE)
AnnaBridge	171:3a7713b1edbc	4723
AnnaBridge	171:3a7713b1edbc	4724	/**
AnnaBridge	171:3a7713b1edbc	4725	* @}
AnnaBridge	171:3a7713b1edbc	4726	/ / end of group TSI_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	4727
AnnaBridge	171:3a7713b1edbc	4728
AnnaBridge	171:3a7713b1edbc	4729	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	4730	-- UART Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	4731	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	4732
AnnaBridge	171:3a7713b1edbc	4733	/**
AnnaBridge	171:3a7713b1edbc	4734	* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	4735	* @{
AnnaBridge	171:3a7713b1edbc	4736	*/
AnnaBridge	171:3a7713b1edbc	4737
AnnaBridge	171:3a7713b1edbc	4738	/** UART - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	4739	typedef struct {
AnnaBridge	171:3a7713b1edbc	4740	__IO uint8_t BDH; /*< UART Baud Rate Registers:High, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	4741	__IO uint8_t BDL; /*< UART Baud Rate Registers: Low, offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	4742	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	4743	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
AnnaBridge	171:3a7713b1edbc	4744	__I uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	4745	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
AnnaBridge	171:3a7713b1edbc	4746	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
AnnaBridge	171:3a7713b1edbc	4747	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
AnnaBridge	171:3a7713b1edbc	4748	__IO uint8_t MA1; /*< UART Match Address Registers 1, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	4749	__IO uint8_t MA2; /*< UART Match Address Registers 2, offset: 0x9 /
AnnaBridge	171:3a7713b1edbc	4750	__IO uint8_t C4; /*< UART Control Register 4, offset: 0xA /
AnnaBridge	171:3a7713b1edbc	4751	__IO uint8_t C5; /*< UART Control Register 5, offset: 0xB /
AnnaBridge	171:3a7713b1edbc	4752	__I uint8_t ED; /*< UART Extended Data Register, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	4753	__IO uint8_t MODEM; /*< UART Modem Register, offset: 0xD /
AnnaBridge	171:3a7713b1edbc	4754	__IO uint8_t IR; /*< UART Infrared Register, offset: 0xE /
AnnaBridge	171:3a7713b1edbc	4755	uint8_t RESERVED_0[1];
AnnaBridge	171:3a7713b1edbc	4756	__IO uint8_t PFIFO; /*< UART FIFO Parameters, offset: 0x10 /
AnnaBridge	171:3a7713b1edbc	4757	__IO uint8_t CFIFO; /*< UART FIFO Control Register, offset: 0x11 /
AnnaBridge	171:3a7713b1edbc	4758	__IO uint8_t SFIFO; /*< UART FIFO Status Register, offset: 0x12 /
AnnaBridge	171:3a7713b1edbc	4759	__IO uint8_t TWFIFO; /*< UART FIFO Transmit Watermark, offset: 0x13 /
AnnaBridge	171:3a7713b1edbc	4760	__I uint8_t TCFIFO; /*< UART FIFO Transmit Count, offset: 0x14 /
AnnaBridge	171:3a7713b1edbc	4761	__IO uint8_t RWFIFO; /*< UART FIFO Receive Watermark, offset: 0x15 /
AnnaBridge	171:3a7713b1edbc	4762	__I uint8_t RCFIFO; /*< UART FIFO Receive Count, offset: 0x16 /
AnnaBridge	171:3a7713b1edbc	4763	uint8_t RESERVED_1[1];
AnnaBridge	171:3a7713b1edbc	4764	__IO uint8_t C7816; /*< UART 7816 Control Register, offset: 0x18 /
AnnaBridge	171:3a7713b1edbc	4765	__IO uint8_t IE7816; /*< UART 7816 Interrupt Enable Register, offset: 0x19 /
AnnaBridge	171:3a7713b1edbc	4766	__IO uint8_t IS7816; /*< UART 7816 Interrupt Status Register, offset: 0x1A /
AnnaBridge	171:3a7713b1edbc	4767	union { /* offset: 0x1B */
AnnaBridge	171:3a7713b1edbc	4768	__IO uint8_t WP7816_T_TYPE0; /*< UART 7816 Wait Parameter Register, offset: 0x1B /
AnnaBridge	171:3a7713b1edbc	4769	__IO uint8_t WP7816_T_TYPE1; /*< UART 7816 Wait Parameter Register, offset: 0x1B /
AnnaBridge	171:3a7713b1edbc	4770	};
AnnaBridge	171:3a7713b1edbc	4771	__IO uint8_t WN7816; /*< UART 7816 Wait N Register, offset: 0x1C /
AnnaBridge	171:3a7713b1edbc	4772	__IO uint8_t WF7816; /*< UART 7816 Wait FD Register, offset: 0x1D /
AnnaBridge	171:3a7713b1edbc	4773	__IO uint8_t ET7816; /*< UART 7816 Error Threshold Register, offset: 0x1E /
AnnaBridge	171:3a7713b1edbc	4774	__IO uint8_t TL7816; /*< UART 7816 Transmit Length Register, offset: 0x1F /
AnnaBridge	171:3a7713b1edbc	4775	uint8_t RESERVED_2[1];
AnnaBridge	171:3a7713b1edbc	4776	__IO uint8_t C6; /*< UART CEA709.1-B Control Register 6, offset: 0x21 /
AnnaBridge	171:3a7713b1edbc	4777	__IO uint8_t PCTH; /*< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 /
AnnaBridge	171:3a7713b1edbc	4778	__IO uint8_t PCTL; /*< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 /
AnnaBridge	171:3a7713b1edbc	4779	__IO uint8_t B1T; /*< UART CEA709.1-B Beta1 Timer, offset: 0x24 /
AnnaBridge	171:3a7713b1edbc	4780	__IO uint8_t SDTH; /*< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 /
AnnaBridge	171:3a7713b1edbc	4781	__IO uint8_t SDTL; /*< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 /
AnnaBridge	171:3a7713b1edbc	4782	__IO uint8_t PRE; /*< UART CEA709.1-B Preamble, offset: 0x27 /
AnnaBridge	171:3a7713b1edbc	4783	__IO uint8_t TPL; /*< UART CEA709.1-B Transmit Packet Length, offset: 0x28 /
AnnaBridge	171:3a7713b1edbc	4784	__IO uint8_t IE; /*< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 /
AnnaBridge	171:3a7713b1edbc	4785	__IO uint8_t WB; /*< UART CEA709.1-B WBASE, offset: 0x2A /
AnnaBridge	171:3a7713b1edbc	4786	__IO uint8_t S3; /*< UART CEA709.1-B Status Register, offset: 0x2B /
AnnaBridge	171:3a7713b1edbc	4787	__IO uint8_t S4; /*< UART CEA709.1-B Status Register, offset: 0x2C /
AnnaBridge	171:3a7713b1edbc	4788	__I uint8_t RPL; /*< UART CEA709.1-B Received Packet Length, offset: 0x2D /
AnnaBridge	171:3a7713b1edbc	4789	__I uint8_t RPREL; /*< UART CEA709.1-B Received Preamble Length, offset: 0x2E /
AnnaBridge	171:3a7713b1edbc	4790	__IO uint8_t CPW; /*< UART CEA709.1-B Collision Pulse Width, offset: 0x2F /
AnnaBridge	171:3a7713b1edbc	4791	__IO uint8_t RIDT; /*< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 /
AnnaBridge	171:3a7713b1edbc	4792	__IO uint8_t TIDT; /*< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 /
AnnaBridge	171:3a7713b1edbc	4793	} UART_Type;
AnnaBridge	171:3a7713b1edbc	4794
AnnaBridge	171:3a7713b1edbc	4795	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	4796	-- UART Register Masks
AnnaBridge	171:3a7713b1edbc	4797	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	4798
AnnaBridge	171:3a7713b1edbc	4799	/**
AnnaBridge	171:3a7713b1edbc	4800	* @addtogroup UART_Register_Masks UART Register Masks
AnnaBridge	171:3a7713b1edbc	4801	* @{
AnnaBridge	171:3a7713b1edbc	4802	*/
AnnaBridge	171:3a7713b1edbc	4803
AnnaBridge	171:3a7713b1edbc	4804	/* BDH Bit Fields */
AnnaBridge	171:3a7713b1edbc	4805	#define UART_BDH_SBR_MASK 0x1Fu
AnnaBridge	171:3a7713b1edbc	4806	#define UART_BDH_SBR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4807	#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
AnnaBridge	171:3a7713b1edbc	4808	#define UART_BDH_RXEDGIE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4809	#define UART_BDH_RXEDGIE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4810	#define UART_BDH_LBKDIE_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4811	#define UART_BDH_LBKDIE_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4812	/* BDL Bit Fields */
AnnaBridge	171:3a7713b1edbc	4813	#define UART_BDL_SBR_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	4814	#define UART_BDL_SBR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4815	#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
AnnaBridge	171:3a7713b1edbc	4816	/* C1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4817	#define UART_C1_PT_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4818	#define UART_C1_PT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4819	#define UART_C1_PE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4820	#define UART_C1_PE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4821	#define UART_C1_ILT_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	4822	#define UART_C1_ILT_SHIFT 2
AnnaBridge	171:3a7713b1edbc	4823	#define UART_C1_WAKE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	4824	#define UART_C1_WAKE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	4825	#define UART_C1_M_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	4826	#define UART_C1_M_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4827	#define UART_C1_RSRC_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	4828	#define UART_C1_RSRC_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4829	#define UART_C1_UARTSWAI_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4830	#define UART_C1_UARTSWAI_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4831	#define UART_C1_LOOPS_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4832	#define UART_C1_LOOPS_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4833	/* C2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4834	#define UART_C2_SBK_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4835	#define UART_C2_SBK_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4836	#define UART_C2_RWU_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4837	#define UART_C2_RWU_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4838	#define UART_C2_RE_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	4839	#define UART_C2_RE_SHIFT 2
AnnaBridge	171:3a7713b1edbc	4840	#define UART_C2_TE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	4841	#define UART_C2_TE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	4842	#define UART_C2_ILIE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	4843	#define UART_C2_ILIE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4844	#define UART_C2_RIE_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	4845	#define UART_C2_RIE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4846	#define UART_C2_TCIE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4847	#define UART_C2_TCIE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4848	#define UART_C2_TIE_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4849	#define UART_C2_TIE_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4850	/* S1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4851	#define UART_S1_PF_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4852	#define UART_S1_PF_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4853	#define UART_S1_FE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4854	#define UART_S1_FE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4855	#define UART_S1_NF_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	4856	#define UART_S1_NF_SHIFT 2
AnnaBridge	171:3a7713b1edbc	4857	#define UART_S1_OR_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	4858	#define UART_S1_OR_SHIFT 3
AnnaBridge	171:3a7713b1edbc	4859	#define UART_S1_IDLE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	4860	#define UART_S1_IDLE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4861	#define UART_S1_RDRF_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	4862	#define UART_S1_RDRF_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4863	#define UART_S1_TC_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4864	#define UART_S1_TC_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4865	#define UART_S1_TDRE_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4866	#define UART_S1_TDRE_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4867	/* S2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4868	#define UART_S2_RAF_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4869	#define UART_S2_RAF_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4870	#define UART_S2_LBKDE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4871	#define UART_S2_LBKDE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4872	#define UART_S2_BRK13_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	4873	#define UART_S2_BRK13_SHIFT 2
AnnaBridge	171:3a7713b1edbc	4874	#define UART_S2_RWUID_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	4875	#define UART_S2_RWUID_SHIFT 3
AnnaBridge	171:3a7713b1edbc	4876	#define UART_S2_RXINV_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	4877	#define UART_S2_RXINV_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4878	#define UART_S2_MSBF_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	4879	#define UART_S2_MSBF_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4880	#define UART_S2_RXEDGIF_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4881	#define UART_S2_RXEDGIF_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4882	#define UART_S2_LBKDIF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4883	#define UART_S2_LBKDIF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4884	/* C3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4885	#define UART_C3_PEIE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4886	#define UART_C3_PEIE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4887	#define UART_C3_FEIE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4888	#define UART_C3_FEIE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4889	#define UART_C3_NEIE_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	4890	#define UART_C3_NEIE_SHIFT 2
AnnaBridge	171:3a7713b1edbc	4891	#define UART_C3_ORIE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	4892	#define UART_C3_ORIE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	4893	#define UART_C3_TXINV_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	4894	#define UART_C3_TXINV_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4895	#define UART_C3_TXDIR_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	4896	#define UART_C3_TXDIR_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4897	#define UART_C3_T8_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4898	#define UART_C3_T8_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4899	#define UART_C3_R8_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4900	#define UART_C3_R8_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4901	/* D Bit Fields */
AnnaBridge	171:3a7713b1edbc	4902	#define UART_D_RT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	4903	#define UART_D_RT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4904	#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
AnnaBridge	171:3a7713b1edbc	4905	/* MA1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4906	#define UART_MA1_MA_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	4907	#define UART_MA1_MA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4908	#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
AnnaBridge	171:3a7713b1edbc	4909	/* MA2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4910	#define UART_MA2_MA_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	4911	#define UART_MA2_MA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4912	#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
AnnaBridge	171:3a7713b1edbc	4913	/* C4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4914	#define UART_C4_BRFA_MASK 0x1Fu
AnnaBridge	171:3a7713b1edbc	4915	#define UART_C4_BRFA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4916	#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
AnnaBridge	171:3a7713b1edbc	4917	#define UART_C4_M10_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	4918	#define UART_C4_M10_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4919	#define UART_C4_MAEN2_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4920	#define UART_C4_MAEN2_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4921	#define UART_C4_MAEN1_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4922	#define UART_C4_MAEN1_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4923	/* C5 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4924	#define UART_C5_RDMAS_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	4925	#define UART_C5_RDMAS_SHIFT 5
AnnaBridge	171:3a7713b1edbc	4926	#define UART_C5_TDMAS_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4927	#define UART_C5_TDMAS_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4928	/* ED Bit Fields */
AnnaBridge	171:3a7713b1edbc	4929	#define UART_ED_PARITYE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4930	#define UART_ED_PARITYE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4931	#define UART_ED_NOISY_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4932	#define UART_ED_NOISY_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4933	/* MODEM Bit Fields */
AnnaBridge	171:3a7713b1edbc	4934	#define UART_MODEM_TXCTSE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4935	#define UART_MODEM_TXCTSE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4936	#define UART_MODEM_TXRTSE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4937	#define UART_MODEM_TXRTSE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4938	#define UART_MODEM_TXRTSPOL_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	4939	#define UART_MODEM_TXRTSPOL_SHIFT 2
AnnaBridge	171:3a7713b1edbc	4940	#define UART_MODEM_RXRTSE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	4941	#define UART_MODEM_RXRTSE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	4942	/* IR Bit Fields */
AnnaBridge	171:3a7713b1edbc	4943	#define UART_IR_TNP_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	4944	#define UART_IR_TNP_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4945	#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
AnnaBridge	171:3a7713b1edbc	4946	#define UART_IR_IREN_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	4947	#define UART_IR_IREN_SHIFT 2
AnnaBridge	171:3a7713b1edbc	4948	/* PFIFO Bit Fields */
AnnaBridge	171:3a7713b1edbc	4949	#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
AnnaBridge	171:3a7713b1edbc	4950	#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4951	#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
AnnaBridge	171:3a7713b1edbc	4952	#define UART_PFIFO_RXFE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	4953	#define UART_PFIFO_RXFE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	4954	#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
AnnaBridge	171:3a7713b1edbc	4955	#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	4956	#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
AnnaBridge	171:3a7713b1edbc	4957	#define UART_PFIFO_TXFE_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4958	#define UART_PFIFO_TXFE_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4959	/* CFIFO Bit Fields */
AnnaBridge	171:3a7713b1edbc	4960	#define UART_CFIFO_RXUFE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4961	#define UART_CFIFO_RXUFE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4962	#define UART_CFIFO_TXOFE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4963	#define UART_CFIFO_TXOFE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4964	#define UART_CFIFO_RXFLUSH_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4965	#define UART_CFIFO_RXFLUSH_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4966	#define UART_CFIFO_TXFLUSH_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4967	#define UART_CFIFO_TXFLUSH_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4968	/* SFIFO Bit Fields */
AnnaBridge	171:3a7713b1edbc	4969	#define UART_SFIFO_RXUF_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4970	#define UART_SFIFO_RXUF_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4971	#define UART_SFIFO_TXOF_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4972	#define UART_SFIFO_TXOF_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4973	#define UART_SFIFO_RXEMPT_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	4974	#define UART_SFIFO_RXEMPT_SHIFT 6
AnnaBridge	171:3a7713b1edbc	4975	#define UART_SFIFO_TXEMPT_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	4976	#define UART_SFIFO_TXEMPT_SHIFT 7
AnnaBridge	171:3a7713b1edbc	4977	/* TWFIFO Bit Fields */
AnnaBridge	171:3a7713b1edbc	4978	#define UART_TWFIFO_TXWATER_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	4979	#define UART_TWFIFO_TXWATER_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4980	#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
AnnaBridge	171:3a7713b1edbc	4981	/* TCFIFO Bit Fields */
AnnaBridge	171:3a7713b1edbc	4982	#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	4983	#define UART_TCFIFO_TXCOUNT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4984	#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
AnnaBridge	171:3a7713b1edbc	4985	/* RWFIFO Bit Fields */
AnnaBridge	171:3a7713b1edbc	4986	#define UART_RWFIFO_RXWATER_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	4987	#define UART_RWFIFO_RXWATER_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4988	#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
AnnaBridge	171:3a7713b1edbc	4989	/* RCFIFO Bit Fields */
AnnaBridge	171:3a7713b1edbc	4990	#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	4991	#define UART_RCFIFO_RXCOUNT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4992	#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
AnnaBridge	171:3a7713b1edbc	4993	/* C7816 Bit Fields */
AnnaBridge	171:3a7713b1edbc	4994	#define UART_C7816_ISO_7816E_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	4995	#define UART_C7816_ISO_7816E_SHIFT 0
AnnaBridge	171:3a7713b1edbc	4996	#define UART_C7816_TTYPE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	4997	#define UART_C7816_TTYPE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	4998	#define UART_C7816_INIT_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	4999	#define UART_C7816_INIT_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5000	#define UART_C7816_ANACK_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5001	#define UART_C7816_ANACK_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5002	#define UART_C7816_ONACK_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5003	#define UART_C7816_ONACK_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5004	/* IE7816 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5005	#define UART_IE7816_RXTE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5006	#define UART_IE7816_RXTE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5007	#define UART_IE7816_TXTE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5008	#define UART_IE7816_TXTE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5009	#define UART_IE7816_GTVE_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5010	#define UART_IE7816_GTVE_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5011	#define UART_IE7816_INITDE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5012	#define UART_IE7816_INITDE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5013	#define UART_IE7816_BWTE_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5014	#define UART_IE7816_BWTE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5015	#define UART_IE7816_CWTE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5016	#define UART_IE7816_CWTE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5017	#define UART_IE7816_WTE_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5018	#define UART_IE7816_WTE_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5019	/* IS7816 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5020	#define UART_IS7816_RXT_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5021	#define UART_IS7816_RXT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5022	#define UART_IS7816_TXT_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5023	#define UART_IS7816_TXT_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5024	#define UART_IS7816_GTV_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5025	#define UART_IS7816_GTV_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5026	#define UART_IS7816_INITD_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5027	#define UART_IS7816_INITD_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5028	#define UART_IS7816_BWT_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5029	#define UART_IS7816_BWT_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5030	#define UART_IS7816_CWT_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5031	#define UART_IS7816_CWT_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5032	#define UART_IS7816_WT_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5033	#define UART_IS7816_WT_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5034	/* WP7816_T_TYPE0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5035	#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5036	#define UART_WP7816_T_TYPE0_WI_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5037	#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
AnnaBridge	171:3a7713b1edbc	5038	/* WP7816_T_TYPE1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5039	#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	5040	#define UART_WP7816_T_TYPE1_BWI_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5041	#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
AnnaBridge	171:3a7713b1edbc	5042	#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
AnnaBridge	171:3a7713b1edbc	5043	#define UART_WP7816_T_TYPE1_CWI_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5044	#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
AnnaBridge	171:3a7713b1edbc	5045	/* WN7816 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5046	#define UART_WN7816_GTN_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5047	#define UART_WN7816_GTN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5048	#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
AnnaBridge	171:3a7713b1edbc	5049	/* WF7816 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5050	#define UART_WF7816_GTFD_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5051	#define UART_WF7816_GTFD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5052	#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
AnnaBridge	171:3a7713b1edbc	5053	/* ET7816 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5054	#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	5055	#define UART_ET7816_RXTHRESHOLD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5056	#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
AnnaBridge	171:3a7713b1edbc	5057	#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
AnnaBridge	171:3a7713b1edbc	5058	#define UART_ET7816_TXTHRESHOLD_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5059	#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
AnnaBridge	171:3a7713b1edbc	5060	/* TL7816 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5061	#define UART_TL7816_TLEN_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5062	#define UART_TL7816_TLEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5063	#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
AnnaBridge	171:3a7713b1edbc	5064	/* C6 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5065	#define UART_C6_CP_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5066	#define UART_C6_CP_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5067	#define UART_C6_CE_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5068	#define UART_C6_CE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5069	#define UART_C6_TX709_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5070	#define UART_C6_TX709_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5071	#define UART_C6_EN709_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5072	#define UART_C6_EN709_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5073	/* PCTH Bit Fields */
AnnaBridge	171:3a7713b1edbc	5074	#define UART_PCTH_PCTH_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5075	#define UART_PCTH_PCTH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5076	#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
AnnaBridge	171:3a7713b1edbc	5077	/* PCTL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5078	#define UART_PCTL_PCTL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5079	#define UART_PCTL_PCTL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5080	#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
AnnaBridge	171:3a7713b1edbc	5081	/* B1T Bit Fields */
AnnaBridge	171:3a7713b1edbc	5082	#define UART_B1T_B1T_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5083	#define UART_B1T_B1T_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5084	#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
AnnaBridge	171:3a7713b1edbc	5085	/* SDTH Bit Fields */
AnnaBridge	171:3a7713b1edbc	5086	#define UART_SDTH_SDTH_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5087	#define UART_SDTH_SDTH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5088	#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
AnnaBridge	171:3a7713b1edbc	5089	/* SDTL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5090	#define UART_SDTL_SDTL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5091	#define UART_SDTL_SDTL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5092	#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
AnnaBridge	171:3a7713b1edbc	5093	/* PRE Bit Fields */
AnnaBridge	171:3a7713b1edbc	5094	#define UART_PRE_PREAMBLE_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5095	#define UART_PRE_PREAMBLE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5096	#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
AnnaBridge	171:3a7713b1edbc	5097	/* TPL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5098	#define UART_TPL_TPL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5099	#define UART_TPL_TPL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5100	#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
AnnaBridge	171:3a7713b1edbc	5101	/* IE Bit Fields */
AnnaBridge	171:3a7713b1edbc	5102	#define UART_IE_TXFIE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5103	#define UART_IE_TXFIE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5104	#define UART_IE_PSIE_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5105	#define UART_IE_PSIE_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5106	#define UART_IE_PCTEIE_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5107	#define UART_IE_PCTEIE_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5108	#define UART_IE_PTXIE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5109	#define UART_IE_PTXIE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5110	#define UART_IE_PRXIE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5111	#define UART_IE_PRXIE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5112	#define UART_IE_ISDIE_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5113	#define UART_IE_ISDIE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5114	#define UART_IE_WBEIE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5115	#define UART_IE_WBEIE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5116	/* WB Bit Fields */
AnnaBridge	171:3a7713b1edbc	5117	#define UART_WB_WBASE_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5118	#define UART_WB_WBASE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5119	#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
AnnaBridge	171:3a7713b1edbc	5120	/* S3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5121	#define UART_S3_TXFF_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5122	#define UART_S3_TXFF_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5123	#define UART_S3_PSF_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5124	#define UART_S3_PSF_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5125	#define UART_S3_PCTEF_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5126	#define UART_S3_PCTEF_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5127	#define UART_S3_PTXF_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5128	#define UART_S3_PTXF_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5129	#define UART_S3_PRXF_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5130	#define UART_S3_PRXF_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5131	#define UART_S3_ISD_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5132	#define UART_S3_ISD_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5133	#define UART_S3_WBEF_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5134	#define UART_S3_WBEF_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5135	#define UART_S3_PEF_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5136	#define UART_S3_PEF_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5137	/* S4 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5138	#define UART_S4_FE_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5139	#define UART_S4_FE_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5140	#define UART_S4_ILCV_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5141	#define UART_S4_ILCV_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5142	#define UART_S4_CDET_MASK 0xCu
AnnaBridge	171:3a7713b1edbc	5143	#define UART_S4_CDET_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5144	#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
AnnaBridge	171:3a7713b1edbc	5145	#define UART_S4_INITF_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5146	#define UART_S4_INITF_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5147	/* RPL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5148	#define UART_RPL_RPL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5149	#define UART_RPL_RPL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5150	#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
AnnaBridge	171:3a7713b1edbc	5151	/* RPREL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5152	#define UART_RPREL_RPREL_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5153	#define UART_RPREL_RPREL_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5154	#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
AnnaBridge	171:3a7713b1edbc	5155	/* CPW Bit Fields */
AnnaBridge	171:3a7713b1edbc	5156	#define UART_CPW_CPW_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5157	#define UART_CPW_CPW_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5158	#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
AnnaBridge	171:3a7713b1edbc	5159	/* RIDT Bit Fields */
AnnaBridge	171:3a7713b1edbc	5160	#define UART_RIDT_RIDT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5161	#define UART_RIDT_RIDT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5162	#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
AnnaBridge	171:3a7713b1edbc	5163	/* TIDT Bit Fields */
AnnaBridge	171:3a7713b1edbc	5164	#define UART_TIDT_TIDT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5165	#define UART_TIDT_TIDT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5166	#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
AnnaBridge	171:3a7713b1edbc	5167
AnnaBridge	171:3a7713b1edbc	5168	/**
AnnaBridge	171:3a7713b1edbc	5169	* @}
AnnaBridge	171:3a7713b1edbc	5170	/ / end of group UART_Register_Masks */
AnnaBridge	171:3a7713b1edbc	5171
AnnaBridge	171:3a7713b1edbc	5172
AnnaBridge	171:3a7713b1edbc	5173	/* UART - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	5174	/** Peripheral UART0 base address */
AnnaBridge	171:3a7713b1edbc	5175	#define UART0_BASE (0x4006A000u)
AnnaBridge	171:3a7713b1edbc	5176	/** Peripheral UART0 base pointer */
AnnaBridge	171:3a7713b1edbc	5177	#define UART0 ((UART_Type *)UART0_BASE)
AnnaBridge	171:3a7713b1edbc	5178	/** Peripheral UART1 base address */
AnnaBridge	171:3a7713b1edbc	5179	#define UART1_BASE (0x4006B000u)
AnnaBridge	171:3a7713b1edbc	5180	/** Peripheral UART1 base pointer */
AnnaBridge	171:3a7713b1edbc	5181	#define UART1 ((UART_Type *)UART1_BASE)
AnnaBridge	171:3a7713b1edbc	5182	/** Peripheral UART2 base address */
AnnaBridge	171:3a7713b1edbc	5183	#define UART2_BASE (0x4006C000u)
AnnaBridge	171:3a7713b1edbc	5184	/** Peripheral UART2 base pointer */
AnnaBridge	171:3a7713b1edbc	5185	#define UART2 ((UART_Type *)UART2_BASE)
AnnaBridge	171:3a7713b1edbc	5186
AnnaBridge	171:3a7713b1edbc	5187	/**
AnnaBridge	171:3a7713b1edbc	5188	* @}
AnnaBridge	171:3a7713b1edbc	5189	/ / end of group UART_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	5190
AnnaBridge	171:3a7713b1edbc	5191
AnnaBridge	171:3a7713b1edbc	5192	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	5193	-- USB Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	5194	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	5195
AnnaBridge	171:3a7713b1edbc	5196	/**
AnnaBridge	171:3a7713b1edbc	5197	* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	5198	* @{
AnnaBridge	171:3a7713b1edbc	5199	*/
AnnaBridge	171:3a7713b1edbc	5200
AnnaBridge	171:3a7713b1edbc	5201	/** USB - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	5202	typedef struct {
AnnaBridge	171:3a7713b1edbc	5203	__I uint8_t PERID; /*< Peripheral ID Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	5204	uint8_t RESERVED_0[3];
AnnaBridge	171:3a7713b1edbc	5205	__I uint8_t IDCOMP; /*< Peripheral ID Complement Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	5206	uint8_t RESERVED_1[3];
AnnaBridge	171:3a7713b1edbc	5207	__I uint8_t REV; /*< Peripheral Revision Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	5208	uint8_t RESERVED_2[3];
AnnaBridge	171:3a7713b1edbc	5209	__I uint8_t ADDINFO; /*< Peripheral Additional Info Register, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	5210	uint8_t RESERVED_3[3];
AnnaBridge	171:3a7713b1edbc	5211	__IO uint8_t OTGISTAT; /*< OTG Interrupt Status Register, offset: 0x10 /
AnnaBridge	171:3a7713b1edbc	5212	uint8_t RESERVED_4[3];
AnnaBridge	171:3a7713b1edbc	5213	__IO uint8_t OTGICR; /*< OTG Interrupt Control Register, offset: 0x14 /
AnnaBridge	171:3a7713b1edbc	5214	uint8_t RESERVED_5[3];
AnnaBridge	171:3a7713b1edbc	5215	__IO uint8_t OTGSTAT; /*< OTG Status Register, offset: 0x18 /
AnnaBridge	171:3a7713b1edbc	5216	uint8_t RESERVED_6[3];
AnnaBridge	171:3a7713b1edbc	5217	__IO uint8_t OTGCTL; /*< OTG Control Register, offset: 0x1C /
AnnaBridge	171:3a7713b1edbc	5218	uint8_t RESERVED_7[99];
AnnaBridge	171:3a7713b1edbc	5219	__IO uint8_t ISTAT; /*< Interrupt Status Register, offset: 0x80 /
AnnaBridge	171:3a7713b1edbc	5220	uint8_t RESERVED_8[3];
AnnaBridge	171:3a7713b1edbc	5221	__IO uint8_t INTEN; /*< Interrupt Enable Register, offset: 0x84 /
AnnaBridge	171:3a7713b1edbc	5222	uint8_t RESERVED_9[3];
AnnaBridge	171:3a7713b1edbc	5223	__IO uint8_t ERRSTAT; /*< Error Interrupt Status Register, offset: 0x88 /
AnnaBridge	171:3a7713b1edbc	5224	uint8_t RESERVED_10[3];
AnnaBridge	171:3a7713b1edbc	5225	__IO uint8_t ERREN; /*< Error Interrupt Enable Register, offset: 0x8C /
AnnaBridge	171:3a7713b1edbc	5226	uint8_t RESERVED_11[3];
AnnaBridge	171:3a7713b1edbc	5227	__I uint8_t STAT; /*< Status Register, offset: 0x90 /
AnnaBridge	171:3a7713b1edbc	5228	uint8_t RESERVED_12[3];
AnnaBridge	171:3a7713b1edbc	5229	__IO uint8_t CTL; /*< Control Register, offset: 0x94 /
AnnaBridge	171:3a7713b1edbc	5230	uint8_t RESERVED_13[3];
AnnaBridge	171:3a7713b1edbc	5231	__IO uint8_t ADDR; /*< Address Register, offset: 0x98 /
AnnaBridge	171:3a7713b1edbc	5232	uint8_t RESERVED_14[3];
AnnaBridge	171:3a7713b1edbc	5233	__IO uint8_t BDTPAGE1; /*< BDT Page Register 1, offset: 0x9C /
AnnaBridge	171:3a7713b1edbc	5234	uint8_t RESERVED_15[3];
AnnaBridge	171:3a7713b1edbc	5235	__IO uint8_t FRMNUML; /*< Frame Number Register Low, offset: 0xA0 /
AnnaBridge	171:3a7713b1edbc	5236	uint8_t RESERVED_16[3];
AnnaBridge	171:3a7713b1edbc	5237	__IO uint8_t FRMNUMH; /*< Frame Number Register High, offset: 0xA4 /
AnnaBridge	171:3a7713b1edbc	5238	uint8_t RESERVED_17[3];
AnnaBridge	171:3a7713b1edbc	5239	__IO uint8_t TOKEN; /*< Token Register, offset: 0xA8 /
AnnaBridge	171:3a7713b1edbc	5240	uint8_t RESERVED_18[3];
AnnaBridge	171:3a7713b1edbc	5241	__IO uint8_t SOFTHLD; /*< SOF Threshold Register, offset: 0xAC /
AnnaBridge	171:3a7713b1edbc	5242	uint8_t RESERVED_19[3];
AnnaBridge	171:3a7713b1edbc	5243	__IO uint8_t BDTPAGE2; /*< BDT Page Register 2, offset: 0xB0 /
AnnaBridge	171:3a7713b1edbc	5244	uint8_t RESERVED_20[3];
AnnaBridge	171:3a7713b1edbc	5245	__IO uint8_t BDTPAGE3; /*< BDT Page Register 3, offset: 0xB4 /
AnnaBridge	171:3a7713b1edbc	5246	uint8_t RESERVED_21[11];
AnnaBridge	171:3a7713b1edbc	5247	struct { /* offset: 0xC0, array step: 0x4 */
AnnaBridge	171:3a7713b1edbc	5248	__IO uint8_t ENDPT; /*< Endpoint Control Register, array offset: 0xC0, array step: 0x4 /
AnnaBridge	171:3a7713b1edbc	5249	uint8_t RESERVED_0[3];
AnnaBridge	171:3a7713b1edbc	5250	} ENDPOINT[16];
AnnaBridge	171:3a7713b1edbc	5251	__IO uint8_t USBCTRL; /*< USB Control Register, offset: 0x100 /
AnnaBridge	171:3a7713b1edbc	5252	uint8_t RESERVED_22[3];
AnnaBridge	171:3a7713b1edbc	5253	__I uint8_t OBSERVE; /*< USB OTG Observe Register, offset: 0x104 /
AnnaBridge	171:3a7713b1edbc	5254	uint8_t RESERVED_23[3];
AnnaBridge	171:3a7713b1edbc	5255	__IO uint8_t CONTROL; /*< USB OTG Control Register, offset: 0x108 /
AnnaBridge	171:3a7713b1edbc	5256	uint8_t RESERVED_24[3];
AnnaBridge	171:3a7713b1edbc	5257	__IO uint8_t USBTRC0; /*< USB Transceiver Control Register 0, offset: 0x10C /
AnnaBridge	171:3a7713b1edbc	5258	uint8_t RESERVED_25[7];
AnnaBridge	171:3a7713b1edbc	5259	__IO uint8_t USBFRMADJUST; /*< Frame Adjust Register, offset: 0x114 /
AnnaBridge	171:3a7713b1edbc	5260	} USB_Type;
AnnaBridge	171:3a7713b1edbc	5261
AnnaBridge	171:3a7713b1edbc	5262	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	5263	-- USB Register Masks
AnnaBridge	171:3a7713b1edbc	5264	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	5265
AnnaBridge	171:3a7713b1edbc	5266	/**
AnnaBridge	171:3a7713b1edbc	5267	* @addtogroup USB_Register_Masks USB Register Masks
AnnaBridge	171:3a7713b1edbc	5268	* @{
AnnaBridge	171:3a7713b1edbc	5269	*/
AnnaBridge	171:3a7713b1edbc	5270
AnnaBridge	171:3a7713b1edbc	5271	/* PERID Bit Fields */
AnnaBridge	171:3a7713b1edbc	5272	#define USB_PERID_ID_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	5273	#define USB_PERID_ID_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5274	#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
AnnaBridge	171:3a7713b1edbc	5275	/* IDCOMP Bit Fields */
AnnaBridge	171:3a7713b1edbc	5276	#define USB_IDCOMP_NID_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	5277	#define USB_IDCOMP_NID_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5278	#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
AnnaBridge	171:3a7713b1edbc	5279	/* REV Bit Fields */
AnnaBridge	171:3a7713b1edbc	5280	#define USB_REV_REV_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5281	#define USB_REV_REV_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5282	#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
AnnaBridge	171:3a7713b1edbc	5283	/* ADDINFO Bit Fields */
AnnaBridge	171:3a7713b1edbc	5284	#define USB_ADDINFO_IEHOST_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5285	#define USB_ADDINFO_IEHOST_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5286	#define USB_ADDINFO_IRQNUM_MASK 0xF8u
AnnaBridge	171:3a7713b1edbc	5287	#define USB_ADDINFO_IRQNUM_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5288	#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
AnnaBridge	171:3a7713b1edbc	5289	/* OTGISTAT Bit Fields */
AnnaBridge	171:3a7713b1edbc	5290	#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5291	#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5292	#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5293	#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5294	#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5295	#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5296	#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5297	#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5298	#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5299	#define USB_OTGISTAT_ONEMSEC_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5300	#define USB_OTGISTAT_IDCHG_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5301	#define USB_OTGISTAT_IDCHG_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5302	/* OTGICR Bit Fields */
AnnaBridge	171:3a7713b1edbc	5303	#define USB_OTGICR_AVBUSEN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5304	#define USB_OTGICR_AVBUSEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5305	#define USB_OTGICR_BSESSEN_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5306	#define USB_OTGICR_BSESSEN_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5307	#define USB_OTGICR_SESSVLDEN_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5308	#define USB_OTGICR_SESSVLDEN_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5309	#define USB_OTGICR_LINESTATEEN_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5310	#define USB_OTGICR_LINESTATEEN_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5311	#define USB_OTGICR_ONEMSECEN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5312	#define USB_OTGICR_ONEMSECEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5313	#define USB_OTGICR_IDEN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5314	#define USB_OTGICR_IDEN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5315	/* OTGSTAT Bit Fields */
AnnaBridge	171:3a7713b1edbc	5316	#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5317	#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5318	#define USB_OTGSTAT_BSESSEND_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5319	#define USB_OTGSTAT_BSESSEND_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5320	#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5321	#define USB_OTGSTAT_SESS_VLD_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5322	#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5323	#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5324	#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5325	#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5326	#define USB_OTGSTAT_ID_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5327	#define USB_OTGSTAT_ID_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5328	/* OTGCTL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5329	#define USB_OTGCTL_OTGEN_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5330	#define USB_OTGCTL_OTGEN_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5331	#define USB_OTGCTL_DMLOW_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5332	#define USB_OTGCTL_DMLOW_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5333	#define USB_OTGCTL_DPLOW_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5334	#define USB_OTGCTL_DPLOW_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5335	#define USB_OTGCTL_DPHIGH_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5336	#define USB_OTGCTL_DPHIGH_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5337	/* ISTAT Bit Fields */
AnnaBridge	171:3a7713b1edbc	5338	#define USB_ISTAT_USBRST_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5339	#define USB_ISTAT_USBRST_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5340	#define USB_ISTAT_ERROR_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5341	#define USB_ISTAT_ERROR_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5342	#define USB_ISTAT_SOFTOK_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5343	#define USB_ISTAT_SOFTOK_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5344	#define USB_ISTAT_TOKDNE_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5345	#define USB_ISTAT_TOKDNE_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5346	#define USB_ISTAT_SLEEP_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5347	#define USB_ISTAT_SLEEP_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5348	#define USB_ISTAT_RESUME_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5349	#define USB_ISTAT_RESUME_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5350	#define USB_ISTAT_ATTACH_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5351	#define USB_ISTAT_ATTACH_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5352	#define USB_ISTAT_STALL_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5353	#define USB_ISTAT_STALL_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5354	/* INTEN Bit Fields */
AnnaBridge	171:3a7713b1edbc	5355	#define USB_INTEN_USBRSTEN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5356	#define USB_INTEN_USBRSTEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5357	#define USB_INTEN_ERROREN_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5358	#define USB_INTEN_ERROREN_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5359	#define USB_INTEN_SOFTOKEN_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5360	#define USB_INTEN_SOFTOKEN_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5361	#define USB_INTEN_TOKDNEEN_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5362	#define USB_INTEN_TOKDNEEN_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5363	#define USB_INTEN_SLEEPEN_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5364	#define USB_INTEN_SLEEPEN_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5365	#define USB_INTEN_RESUMEEN_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5366	#define USB_INTEN_RESUMEEN_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5367	#define USB_INTEN_ATTACHEN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5368	#define USB_INTEN_ATTACHEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5369	#define USB_INTEN_STALLEN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5370	#define USB_INTEN_STALLEN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5371	/* ERRSTAT Bit Fields */
AnnaBridge	171:3a7713b1edbc	5372	#define USB_ERRSTAT_PIDERR_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5373	#define USB_ERRSTAT_PIDERR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5374	#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5375	#define USB_ERRSTAT_CRC5EOF_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5376	#define USB_ERRSTAT_CRC16_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5377	#define USB_ERRSTAT_CRC16_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5378	#define USB_ERRSTAT_DFN8_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5379	#define USB_ERRSTAT_DFN8_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5380	#define USB_ERRSTAT_BTOERR_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5381	#define USB_ERRSTAT_BTOERR_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5382	#define USB_ERRSTAT_DMAERR_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5383	#define USB_ERRSTAT_DMAERR_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5384	#define USB_ERRSTAT_BTSERR_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5385	#define USB_ERRSTAT_BTSERR_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5386	/* ERREN Bit Fields */
AnnaBridge	171:3a7713b1edbc	5387	#define USB_ERREN_PIDERREN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5388	#define USB_ERREN_PIDERREN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5389	#define USB_ERREN_CRC5EOFEN_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5390	#define USB_ERREN_CRC5EOFEN_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5391	#define USB_ERREN_CRC16EN_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5392	#define USB_ERREN_CRC16EN_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5393	#define USB_ERREN_DFN8EN_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5394	#define USB_ERREN_DFN8EN_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5395	#define USB_ERREN_BTOERREN_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5396	#define USB_ERREN_BTOERREN_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5397	#define USB_ERREN_DMAERREN_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5398	#define USB_ERREN_DMAERREN_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5399	#define USB_ERREN_BTSERREN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5400	#define USB_ERREN_BTSERREN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5401	/* STAT Bit Fields */
AnnaBridge	171:3a7713b1edbc	5402	#define USB_STAT_ODD_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5403	#define USB_STAT_ODD_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5404	#define USB_STAT_TX_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5405	#define USB_STAT_TX_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5406	#define USB_STAT_ENDP_MASK 0xF0u
AnnaBridge	171:3a7713b1edbc	5407	#define USB_STAT_ENDP_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5408	#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
AnnaBridge	171:3a7713b1edbc	5409	/* CTL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5410	#define USB_CTL_USBENSOFEN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5411	#define USB_CTL_USBENSOFEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5412	#define USB_CTL_ODDRST_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5413	#define USB_CTL_ODDRST_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5414	#define USB_CTL_RESUME_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5415	#define USB_CTL_RESUME_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5416	#define USB_CTL_HOSTMODEEN_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5417	#define USB_CTL_HOSTMODEEN_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5418	#define USB_CTL_RESET_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5419	#define USB_CTL_RESET_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5420	#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5421	#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5422	#define USB_CTL_SE0_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5423	#define USB_CTL_SE0_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5424	#define USB_CTL_JSTATE_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5425	#define USB_CTL_JSTATE_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5426	/* ADDR Bit Fields */
AnnaBridge	171:3a7713b1edbc	5427	#define USB_ADDR_ADDR_MASK 0x7Fu
AnnaBridge	171:3a7713b1edbc	5428	#define USB_ADDR_ADDR_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5429	#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
AnnaBridge	171:3a7713b1edbc	5430	#define USB_ADDR_LSEN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5431	#define USB_ADDR_LSEN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5432	/* BDTPAGE1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5433	#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
AnnaBridge	171:3a7713b1edbc	5434	#define USB_BDTPAGE1_BDTBA_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5435	#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
AnnaBridge	171:3a7713b1edbc	5436	/* FRMNUML Bit Fields */
AnnaBridge	171:3a7713b1edbc	5437	#define USB_FRMNUML_FRM_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5438	#define USB_FRMNUML_FRM_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5439	#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
AnnaBridge	171:3a7713b1edbc	5440	/* FRMNUMH Bit Fields */
AnnaBridge	171:3a7713b1edbc	5441	#define USB_FRMNUMH_FRM_MASK 0x7u
AnnaBridge	171:3a7713b1edbc	5442	#define USB_FRMNUMH_FRM_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5443	#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
AnnaBridge	171:3a7713b1edbc	5444	/* TOKEN Bit Fields */
AnnaBridge	171:3a7713b1edbc	5445	#define USB_TOKEN_TOKENENDPT_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	5446	#define USB_TOKEN_TOKENENDPT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5447	#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
AnnaBridge	171:3a7713b1edbc	5448	#define USB_TOKEN_TOKENPID_MASK 0xF0u
AnnaBridge	171:3a7713b1edbc	5449	#define USB_TOKEN_TOKENPID_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5450	#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
AnnaBridge	171:3a7713b1edbc	5451	/* SOFTHLD Bit Fields */
AnnaBridge	171:3a7713b1edbc	5452	#define USB_SOFTHLD_CNT_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5453	#define USB_SOFTHLD_CNT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5454	#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
AnnaBridge	171:3a7713b1edbc	5455	/* BDTPAGE2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5456	#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5457	#define USB_BDTPAGE2_BDTBA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5458	#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
AnnaBridge	171:3a7713b1edbc	5459	/* BDTPAGE3 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5460	#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5461	#define USB_BDTPAGE3_BDTBA_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5462	#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
AnnaBridge	171:3a7713b1edbc	5463	/* ENDPT Bit Fields */
AnnaBridge	171:3a7713b1edbc	5464	#define USB_ENDPT_EPHSHK_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5465	#define USB_ENDPT_EPHSHK_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5466	#define USB_ENDPT_EPSTALL_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5467	#define USB_ENDPT_EPSTALL_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5468	#define USB_ENDPT_EPTXEN_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5469	#define USB_ENDPT_EPTXEN_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5470	#define USB_ENDPT_EPRXEN_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5471	#define USB_ENDPT_EPRXEN_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5472	#define USB_ENDPT_EPCTLDIS_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5473	#define USB_ENDPT_EPCTLDIS_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5474	#define USB_ENDPT_RETRYDIS_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5475	#define USB_ENDPT_RETRYDIS_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5476	#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5477	#define USB_ENDPT_HOSTWOHUB_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5478	/* USBCTRL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5479	#define USB_USBCTRL_PDE_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5480	#define USB_USBCTRL_PDE_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5481	#define USB_USBCTRL_SUSP_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5482	#define USB_USBCTRL_SUSP_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5483	/* OBSERVE Bit Fields */
AnnaBridge	171:3a7713b1edbc	5484	#define USB_OBSERVE_DMPD_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5485	#define USB_OBSERVE_DMPD_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5486	#define USB_OBSERVE_DPPD_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5487	#define USB_OBSERVE_DPPD_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5488	#define USB_OBSERVE_DPPU_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5489	#define USB_OBSERVE_DPPU_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5490	/* CONTROL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5491	#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5492	#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5493	/* USBTRC0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5494	#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5495	#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5496	#define USB_USBTRC0_SYNC_DET_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5497	#define USB_USBTRC0_SYNC_DET_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5498	#define USB_USBTRC0_USBRESMEN_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5499	#define USB_USBTRC0_USBRESMEN_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5500	#define USB_USBTRC0_USBRESET_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5501	#define USB_USBTRC0_USBRESET_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5502	/* USBFRMADJUST Bit Fields */
AnnaBridge	171:3a7713b1edbc	5503	#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
AnnaBridge	171:3a7713b1edbc	5504	#define USB_USBFRMADJUST_ADJ_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5505	#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
AnnaBridge	171:3a7713b1edbc	5506
AnnaBridge	171:3a7713b1edbc	5507	/**
AnnaBridge	171:3a7713b1edbc	5508	* @}
AnnaBridge	171:3a7713b1edbc	5509	/ / end of group USB_Register_Masks */
AnnaBridge	171:3a7713b1edbc	5510
AnnaBridge	171:3a7713b1edbc	5511
AnnaBridge	171:3a7713b1edbc	5512	/* USB - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	5513	/** Peripheral USB0 base address */
AnnaBridge	171:3a7713b1edbc	5514	#define USB0_BASE (0x40072000u)
AnnaBridge	171:3a7713b1edbc	5515	/** Peripheral USB0 base pointer */
AnnaBridge	171:3a7713b1edbc	5516	#define USB0 ((USB_Type *)USB0_BASE)
AnnaBridge	171:3a7713b1edbc	5517
AnnaBridge	171:3a7713b1edbc	5518	/**
AnnaBridge	171:3a7713b1edbc	5519	* @}
AnnaBridge	171:3a7713b1edbc	5520	/ / end of group USB_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	5521
AnnaBridge	171:3a7713b1edbc	5522
AnnaBridge	171:3a7713b1edbc	5523	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	5524	-- USBDCD Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	5525	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	5526
AnnaBridge	171:3a7713b1edbc	5527	/**
AnnaBridge	171:3a7713b1edbc	5528	* @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	5529	* @{
AnnaBridge	171:3a7713b1edbc	5530	*/
AnnaBridge	171:3a7713b1edbc	5531
AnnaBridge	171:3a7713b1edbc	5532	/** USBDCD - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	5533	typedef struct {
AnnaBridge	171:3a7713b1edbc	5534	__IO uint32_t CONTROL; /*< Control Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	5535	__IO uint32_t CLOCK; /*< Clock Register, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	5536	__I uint32_t STATUS; /*< Status Register, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	5537	uint8_t RESERVED_0[4];
AnnaBridge	171:3a7713b1edbc	5538	__IO uint32_t TIMER0; /*< TIMER0 Register, offset: 0x10 /
AnnaBridge	171:3a7713b1edbc	5539	__IO uint32_t TIMER1; /*< , offset: 0x14 /
AnnaBridge	171:3a7713b1edbc	5540	__IO uint32_t TIMER2; /*< , offset: 0x18 /
AnnaBridge	171:3a7713b1edbc	5541	} USBDCD_Type;
AnnaBridge	171:3a7713b1edbc	5542
AnnaBridge	171:3a7713b1edbc	5543	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	5544	-- USBDCD Register Masks
AnnaBridge	171:3a7713b1edbc	5545	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	5546
AnnaBridge	171:3a7713b1edbc	5547	/**
AnnaBridge	171:3a7713b1edbc	5548	* @addtogroup USBDCD_Register_Masks USBDCD Register Masks
AnnaBridge	171:3a7713b1edbc	5549	* @{
AnnaBridge	171:3a7713b1edbc	5550	*/
AnnaBridge	171:3a7713b1edbc	5551
AnnaBridge	171:3a7713b1edbc	5552	/* CONTROL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5553	#define USBDCD_CONTROL_IACK_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5554	#define USBDCD_CONTROL_IACK_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5555	#define USBDCD_CONTROL_IF_MASK 0x100u
AnnaBridge	171:3a7713b1edbc	5556	#define USBDCD_CONTROL_IF_SHIFT 8
AnnaBridge	171:3a7713b1edbc	5557	#define USBDCD_CONTROL_IE_MASK 0x10000u
AnnaBridge	171:3a7713b1edbc	5558	#define USBDCD_CONTROL_IE_SHIFT 16
AnnaBridge	171:3a7713b1edbc	5559	#define USBDCD_CONTROL_START_MASK 0x1000000u
AnnaBridge	171:3a7713b1edbc	5560	#define USBDCD_CONTROL_START_SHIFT 24
AnnaBridge	171:3a7713b1edbc	5561	#define USBDCD_CONTROL_SR_MASK 0x2000000u
AnnaBridge	171:3a7713b1edbc	5562	#define USBDCD_CONTROL_SR_SHIFT 25
AnnaBridge	171:3a7713b1edbc	5563	/* CLOCK Bit Fields */
AnnaBridge	171:3a7713b1edbc	5564	#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5565	#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5566	#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
AnnaBridge	171:3a7713b1edbc	5567	#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5568	#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
AnnaBridge	171:3a7713b1edbc	5569	/* STATUS Bit Fields */
AnnaBridge	171:3a7713b1edbc	5570	#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
AnnaBridge	171:3a7713b1edbc	5571	#define USBDCD_STATUS_SEQ_RES_SHIFT 16
AnnaBridge	171:3a7713b1edbc	5572	#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
AnnaBridge	171:3a7713b1edbc	5573	#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
AnnaBridge	171:3a7713b1edbc	5574	#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
AnnaBridge	171:3a7713b1edbc	5575	#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
AnnaBridge	171:3a7713b1edbc	5576	#define USBDCD_STATUS_ERR_MASK 0x100000u
AnnaBridge	171:3a7713b1edbc	5577	#define USBDCD_STATUS_ERR_SHIFT 20
AnnaBridge	171:3a7713b1edbc	5578	#define USBDCD_STATUS_TO_MASK 0x200000u
AnnaBridge	171:3a7713b1edbc	5579	#define USBDCD_STATUS_TO_SHIFT 21
AnnaBridge	171:3a7713b1edbc	5580	#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
AnnaBridge	171:3a7713b1edbc	5581	#define USBDCD_STATUS_ACTIVE_SHIFT 22
AnnaBridge	171:3a7713b1edbc	5582	/* TIMER0 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5583	#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
AnnaBridge	171:3a7713b1edbc	5584	#define USBDCD_TIMER0_TUNITCON_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5585	#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
AnnaBridge	171:3a7713b1edbc	5586	#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
AnnaBridge	171:3a7713b1edbc	5587	#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
AnnaBridge	171:3a7713b1edbc	5588	#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
AnnaBridge	171:3a7713b1edbc	5589	/* TIMER1 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5590	#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
AnnaBridge	171:3a7713b1edbc	5591	#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5592	#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
AnnaBridge	171:3a7713b1edbc	5593	#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
AnnaBridge	171:3a7713b1edbc	5594	#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
AnnaBridge	171:3a7713b1edbc	5595	#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
AnnaBridge	171:3a7713b1edbc	5596	/* TIMER2 Bit Fields */
AnnaBridge	171:3a7713b1edbc	5597	#define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
AnnaBridge	171:3a7713b1edbc	5598	#define USBDCD_TIMER2_CHECK_DM_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5599	#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
AnnaBridge	171:3a7713b1edbc	5600	#define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
AnnaBridge	171:3a7713b1edbc	5601	#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
AnnaBridge	171:3a7713b1edbc	5602	#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
AnnaBridge	171:3a7713b1edbc	5603
AnnaBridge	171:3a7713b1edbc	5604	/**
AnnaBridge	171:3a7713b1edbc	5605	* @}
AnnaBridge	171:3a7713b1edbc	5606	/ / end of group USBDCD_Register_Masks */
AnnaBridge	171:3a7713b1edbc	5607
AnnaBridge	171:3a7713b1edbc	5608
AnnaBridge	171:3a7713b1edbc	5609	/* USBDCD - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	5610	/** Peripheral USBDCD base address */
AnnaBridge	171:3a7713b1edbc	5611	#define USBDCD_BASE (0x40035000u)
AnnaBridge	171:3a7713b1edbc	5612	/** Peripheral USBDCD base pointer */
AnnaBridge	171:3a7713b1edbc	5613	#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
AnnaBridge	171:3a7713b1edbc	5614
AnnaBridge	171:3a7713b1edbc	5615	/**
AnnaBridge	171:3a7713b1edbc	5616	* @}
AnnaBridge	171:3a7713b1edbc	5617	/ / end of group USBDCD_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	5618
AnnaBridge	171:3a7713b1edbc	5619
AnnaBridge	171:3a7713b1edbc	5620	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	5621	-- VREF Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	5622	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	5623
AnnaBridge	171:3a7713b1edbc	5624	/**
AnnaBridge	171:3a7713b1edbc	5625	* @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	5626	* @{
AnnaBridge	171:3a7713b1edbc	5627	*/
AnnaBridge	171:3a7713b1edbc	5628
AnnaBridge	171:3a7713b1edbc	5629	/** VREF - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	5630	typedef struct {
AnnaBridge	171:3a7713b1edbc	5631	__IO uint8_t TRM; /*< VREF Trim Register, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	5632	__IO uint8_t SC; /*< VREF Status and Control Register, offset: 0x1 /
AnnaBridge	171:3a7713b1edbc	5633	} VREF_Type;
AnnaBridge	171:3a7713b1edbc	5634
AnnaBridge	171:3a7713b1edbc	5635	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	5636	-- VREF Register Masks
AnnaBridge	171:3a7713b1edbc	5637	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	5638
AnnaBridge	171:3a7713b1edbc	5639	/**
AnnaBridge	171:3a7713b1edbc	5640	* @addtogroup VREF_Register_Masks VREF Register Masks
AnnaBridge	171:3a7713b1edbc	5641	* @{
AnnaBridge	171:3a7713b1edbc	5642	*/
AnnaBridge	171:3a7713b1edbc	5643
AnnaBridge	171:3a7713b1edbc	5644	/* TRM Bit Fields */
AnnaBridge	171:3a7713b1edbc	5645	#define VREF_TRM_TRIM_MASK 0x3Fu
AnnaBridge	171:3a7713b1edbc	5646	#define VREF_TRM_TRIM_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5647	#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
AnnaBridge	171:3a7713b1edbc	5648	#define VREF_TRM_CHOPEN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5649	#define VREF_TRM_CHOPEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5650	/* SC Bit Fields */
AnnaBridge	171:3a7713b1edbc	5651	#define VREF_SC_MODE_LV_MASK 0x3u
AnnaBridge	171:3a7713b1edbc	5652	#define VREF_SC_MODE_LV_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5653	#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
AnnaBridge	171:3a7713b1edbc	5654	#define VREF_SC_VREFST_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5655	#define VREF_SC_VREFST_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5656	#define VREF_SC_REGEN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5657	#define VREF_SC_REGEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5658	#define VREF_SC_VREFEN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5659	#define VREF_SC_VREFEN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5660
AnnaBridge	171:3a7713b1edbc	5661	/**
AnnaBridge	171:3a7713b1edbc	5662	* @}
AnnaBridge	171:3a7713b1edbc	5663	/ / end of group VREF_Register_Masks */
AnnaBridge	171:3a7713b1edbc	5664
AnnaBridge	171:3a7713b1edbc	5665
AnnaBridge	171:3a7713b1edbc	5666	/* VREF - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	5667	/** Peripheral VREF base address */
AnnaBridge	171:3a7713b1edbc	5668	#define VREF_BASE (0x40074000u)
AnnaBridge	171:3a7713b1edbc	5669	/** Peripheral VREF base pointer */
AnnaBridge	171:3a7713b1edbc	5670	#define VREF ((VREF_Type *)VREF_BASE)
AnnaBridge	171:3a7713b1edbc	5671
AnnaBridge	171:3a7713b1edbc	5672	/**
AnnaBridge	171:3a7713b1edbc	5673	* @}
AnnaBridge	171:3a7713b1edbc	5674	/ / end of group VREF_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	5675
AnnaBridge	171:3a7713b1edbc	5676
AnnaBridge	171:3a7713b1edbc	5677	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	5678	-- WDOG Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	5679	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	5680
AnnaBridge	171:3a7713b1edbc	5681	/**
AnnaBridge	171:3a7713b1edbc	5682	* @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
AnnaBridge	171:3a7713b1edbc	5683	* @{
AnnaBridge	171:3a7713b1edbc	5684	*/
AnnaBridge	171:3a7713b1edbc	5685
AnnaBridge	171:3a7713b1edbc	5686	/** WDOG - Register Layout Typedef */
AnnaBridge	171:3a7713b1edbc	5687	typedef struct {
AnnaBridge	171:3a7713b1edbc	5688	__IO uint16_t STCTRLH; /*< Watchdog Status and Control Register High, offset: 0x0 /
AnnaBridge	171:3a7713b1edbc	5689	__IO uint16_t STCTRLL; /*< Watchdog Status and Control Register Low, offset: 0x2 /
AnnaBridge	171:3a7713b1edbc	5690	__IO uint16_t TOVALH; /*< Watchdog Time-out Value Register High, offset: 0x4 /
AnnaBridge	171:3a7713b1edbc	5691	__IO uint16_t TOVALL; /*< Watchdog Time-out Value Register Low, offset: 0x6 /
AnnaBridge	171:3a7713b1edbc	5692	__IO uint16_t WINH; /*< Watchdog Window Register High, offset: 0x8 /
AnnaBridge	171:3a7713b1edbc	5693	__IO uint16_t WINL; /*< Watchdog Window Register Low, offset: 0xA /
AnnaBridge	171:3a7713b1edbc	5694	__IO uint16_t REFRESH; /*< Watchdog Refresh Register, offset: 0xC /
AnnaBridge	171:3a7713b1edbc	5695	__IO uint16_t UNLOCK; /*< Watchdog Unlock Register, offset: 0xE /
AnnaBridge	171:3a7713b1edbc	5696	__IO uint16_t TMROUTH; /*< Watchdog Timer Output Register High, offset: 0x10 /
AnnaBridge	171:3a7713b1edbc	5697	__IO uint16_t TMROUTL; /*< Watchdog Timer Output Register Low, offset: 0x12 /
AnnaBridge	171:3a7713b1edbc	5698	__IO uint16_t RSTCNT; /*< Watchdog Reset Count Register, offset: 0x14 /
AnnaBridge	171:3a7713b1edbc	5699	__IO uint16_t PRESC; /*< Watchdog Prescaler Register, offset: 0x16 /
AnnaBridge	171:3a7713b1edbc	5700	} WDOG_Type;
AnnaBridge	171:3a7713b1edbc	5701
AnnaBridge	171:3a7713b1edbc	5702	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	5703	-- WDOG Register Masks
AnnaBridge	171:3a7713b1edbc	5704	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	5705
AnnaBridge	171:3a7713b1edbc	5706	/**
AnnaBridge	171:3a7713b1edbc	5707	* @addtogroup WDOG_Register_Masks WDOG Register Masks
AnnaBridge	171:3a7713b1edbc	5708	* @{
AnnaBridge	171:3a7713b1edbc	5709	*/
AnnaBridge	171:3a7713b1edbc	5710
AnnaBridge	171:3a7713b1edbc	5711	/* STCTRLH Bit Fields */
AnnaBridge	171:3a7713b1edbc	5712	#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
AnnaBridge	171:3a7713b1edbc	5713	#define WDOG_STCTRLH_WDOGEN_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5714	#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
AnnaBridge	171:3a7713b1edbc	5715	#define WDOG_STCTRLH_CLKSRC_SHIFT 1
AnnaBridge	171:3a7713b1edbc	5716	#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
AnnaBridge	171:3a7713b1edbc	5717	#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
AnnaBridge	171:3a7713b1edbc	5718	#define WDOG_STCTRLH_WINEN_MASK 0x8u
AnnaBridge	171:3a7713b1edbc	5719	#define WDOG_STCTRLH_WINEN_SHIFT 3
AnnaBridge	171:3a7713b1edbc	5720	#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
AnnaBridge	171:3a7713b1edbc	5721	#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
AnnaBridge	171:3a7713b1edbc	5722	#define WDOG_STCTRLH_DBGEN_MASK 0x20u
AnnaBridge	171:3a7713b1edbc	5723	#define WDOG_STCTRLH_DBGEN_SHIFT 5
AnnaBridge	171:3a7713b1edbc	5724	#define WDOG_STCTRLH_STOPEN_MASK 0x40u
AnnaBridge	171:3a7713b1edbc	5725	#define WDOG_STCTRLH_STOPEN_SHIFT 6
AnnaBridge	171:3a7713b1edbc	5726	#define WDOG_STCTRLH_WAITEN_MASK 0x80u
AnnaBridge	171:3a7713b1edbc	5727	#define WDOG_STCTRLH_WAITEN_SHIFT 7
AnnaBridge	171:3a7713b1edbc	5728	#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
AnnaBridge	171:3a7713b1edbc	5729	#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
AnnaBridge	171:3a7713b1edbc	5730	#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
AnnaBridge	171:3a7713b1edbc	5731	#define WDOG_STCTRLH_TESTSEL_SHIFT 11
AnnaBridge	171:3a7713b1edbc	5732	#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
AnnaBridge	171:3a7713b1edbc	5733	#define WDOG_STCTRLH_BYTESEL_SHIFT 12
AnnaBridge	171:3a7713b1edbc	5734	#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
AnnaBridge	171:3a7713b1edbc	5735	#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
AnnaBridge	171:3a7713b1edbc	5736	#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
AnnaBridge	171:3a7713b1edbc	5737	/* STCTRLL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5738	#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
AnnaBridge	171:3a7713b1edbc	5739	#define WDOG_STCTRLL_INTFLG_SHIFT 15
AnnaBridge	171:3a7713b1edbc	5740	/* TOVALH Bit Fields */
AnnaBridge	171:3a7713b1edbc	5741	#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	5742	#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5743	#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
AnnaBridge	171:3a7713b1edbc	5744	/* TOVALL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5745	#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	5746	#define WDOG_TOVALL_TOVALLOW_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5747	#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
AnnaBridge	171:3a7713b1edbc	5748	/* WINH Bit Fields */
AnnaBridge	171:3a7713b1edbc	5749	#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	5750	#define WDOG_WINH_WINHIGH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5751	#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
AnnaBridge	171:3a7713b1edbc	5752	/* WINL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5753	#define WDOG_WINL_WINLOW_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	5754	#define WDOG_WINL_WINLOW_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5755	#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
AnnaBridge	171:3a7713b1edbc	5756	/* REFRESH Bit Fields */
AnnaBridge	171:3a7713b1edbc	5757	#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	5758	#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5759	#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
AnnaBridge	171:3a7713b1edbc	5760	/* UNLOCK Bit Fields */
AnnaBridge	171:3a7713b1edbc	5761	#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	5762	#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5763	#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
AnnaBridge	171:3a7713b1edbc	5764	/* TMROUTH Bit Fields */
AnnaBridge	171:3a7713b1edbc	5765	#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	5766	#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5767	#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
AnnaBridge	171:3a7713b1edbc	5768	/* TMROUTL Bit Fields */
AnnaBridge	171:3a7713b1edbc	5769	#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	5770	#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5771	#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
AnnaBridge	171:3a7713b1edbc	5772	/* RSTCNT Bit Fields */
AnnaBridge	171:3a7713b1edbc	5773	#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
AnnaBridge	171:3a7713b1edbc	5774	#define WDOG_RSTCNT_RSTCNT_SHIFT 0
AnnaBridge	171:3a7713b1edbc	5775	#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
AnnaBridge	171:3a7713b1edbc	5776	/* PRESC Bit Fields */
AnnaBridge	171:3a7713b1edbc	5777	#define WDOG_PRESC_PRESCVAL_MASK 0x700u
AnnaBridge	171:3a7713b1edbc	5778	#define WDOG_PRESC_PRESCVAL_SHIFT 8
AnnaBridge	171:3a7713b1edbc	5779	#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
AnnaBridge	171:3a7713b1edbc	5780
AnnaBridge	171:3a7713b1edbc	5781	/**
AnnaBridge	171:3a7713b1edbc	5782	* @}
AnnaBridge	171:3a7713b1edbc	5783	/ / end of group WDOG_Register_Masks */
AnnaBridge	171:3a7713b1edbc	5784
AnnaBridge	171:3a7713b1edbc	5785
AnnaBridge	171:3a7713b1edbc	5786	/* WDOG - Peripheral instance base addresses */
AnnaBridge	171:3a7713b1edbc	5787	/** Peripheral WDOG base address */
AnnaBridge	171:3a7713b1edbc	5788	#define WDOG_BASE (0x40052000u)
AnnaBridge	171:3a7713b1edbc	5789	/** Peripheral WDOG base pointer */
AnnaBridge	171:3a7713b1edbc	5790	#define WDOG ((WDOG_Type *)WDOG_BASE)
AnnaBridge	171:3a7713b1edbc	5791
AnnaBridge	171:3a7713b1edbc	5792	/**
AnnaBridge	171:3a7713b1edbc	5793	* @}
AnnaBridge	171:3a7713b1edbc	5794	/ / end of group WDOG_Peripheral_Access_Layer */
AnnaBridge	171:3a7713b1edbc	5795
AnnaBridge	171:3a7713b1edbc	5796
AnnaBridge	171:3a7713b1edbc	5797	/*
AnnaBridge	171:3a7713b1edbc	5798	** End of section using anonymous unions
AnnaBridge	171:3a7713b1edbc	5799	*/
AnnaBridge	171:3a7713b1edbc	5800
AnnaBridge	171:3a7713b1edbc	5801	#if defined(__ARMCC_VERSION)
AnnaBridge	171:3a7713b1edbc	5802	#pragma pop
AnnaBridge	171:3a7713b1edbc	5803	#elif defined(__CWCC__)
AnnaBridge	171:3a7713b1edbc	5804	#pragma pop
AnnaBridge	171:3a7713b1edbc	5805	#elif defined(__GNUC__)
AnnaBridge	171:3a7713b1edbc	5806	/* leave anonymous unions enabled */
AnnaBridge	171:3a7713b1edbc	5807	#elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge	171:3a7713b1edbc	5808	#pragma language=default
AnnaBridge	171:3a7713b1edbc	5809	#else
AnnaBridge	171:3a7713b1edbc	5810	#error Not supported compiler type
AnnaBridge	171:3a7713b1edbc	5811	#endif
AnnaBridge	171:3a7713b1edbc	5812
AnnaBridge	171:3a7713b1edbc	5813	/**
AnnaBridge	171:3a7713b1edbc	5814	* @}
AnnaBridge	171:3a7713b1edbc	5815	/ / end of group Peripheral_access_layer */
AnnaBridge	171:3a7713b1edbc	5816
AnnaBridge	171:3a7713b1edbc	5817
AnnaBridge	171:3a7713b1edbc	5818	/* ----------------------------------------------------------------------------
AnnaBridge	171:3a7713b1edbc	5819	-- Backward Compatibility
AnnaBridge	171:3a7713b1edbc	5820	---------------------------------------------------------------------------- */
AnnaBridge	171:3a7713b1edbc	5821
AnnaBridge	171:3a7713b1edbc	5822	/**
AnnaBridge	171:3a7713b1edbc	5823	* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
AnnaBridge	171:3a7713b1edbc	5824	* @{
AnnaBridge	171:3a7713b1edbc	5825	*/
AnnaBridge	171:3a7713b1edbc	5826
AnnaBridge	171:3a7713b1edbc	5827	/* No backward compatibility issues. */
AnnaBridge	171:3a7713b1edbc	5828
AnnaBridge	171:3a7713b1edbc	5829	/**
AnnaBridge	171:3a7713b1edbc	5830	* @}
AnnaBridge	171:3a7713b1edbc	5831	/ / end of group Backward_Compatibility_Symbols */
AnnaBridge	171:3a7713b1edbc	5832
AnnaBridge	171:3a7713b1edbc	5833
AnnaBridge	171:3a7713b1edbc	5834	#endif /* #if !defined(MK20D5_H_) */
AnnaBridge	171:3a7713b1edbc	5835
AnnaBridge	171:3a7713b1edbc	5836	/* MK20D5.h, eof. */