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TARGET_GR_LYCHEE/TOOLCHAIN_IAR/core_ca.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/************************************************************************//
AnnaBridge	171:3a7713b1edbc	2	* @file core_ca.h
AnnaBridge	171:3a7713b1edbc	3	* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
AnnaBridge	171:3a7713b1edbc	4	* @version V1.0.1
AnnaBridge	171:3a7713b1edbc	5	* @date 07. May 2018
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	7	/*
AnnaBridge	171:3a7713b1edbc	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	171:3a7713b1edbc	9	*
AnnaBridge	171:3a7713b1edbc	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	171:3a7713b1edbc	11	*
AnnaBridge	171:3a7713b1edbc	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	171:3a7713b1edbc	13	* not use this file except in compliance with the License.
AnnaBridge	171:3a7713b1edbc	14	* You may obtain a copy of the License at
AnnaBridge	171:3a7713b1edbc	15	*
AnnaBridge	171:3a7713b1edbc	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	171:3a7713b1edbc	17	*
AnnaBridge	171:3a7713b1edbc	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	171:3a7713b1edbc	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	171:3a7713b1edbc	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	171:3a7713b1edbc	21	* See the License for the specific language governing permissions and
AnnaBridge	171:3a7713b1edbc	22	* limitations under the License.
AnnaBridge	171:3a7713b1edbc	23	*/
AnnaBridge	171:3a7713b1edbc	24
AnnaBridge	171:3a7713b1edbc	25	#if defined ( __ICCARM__ )
AnnaBridge	171:3a7713b1edbc	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	171:3a7713b1edbc	27	#elif defined (__clang__)
AnnaBridge	171:3a7713b1edbc	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	171:3a7713b1edbc	29	#endif
AnnaBridge	171:3a7713b1edbc	30
AnnaBridge	171:3a7713b1edbc	31	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	32	extern "C" {
AnnaBridge	171:3a7713b1edbc	33	#endif
AnnaBridge	171:3a7713b1edbc	34
AnnaBridge	171:3a7713b1edbc	35	#ifndef __CORE_CA_H_GENERIC
AnnaBridge	171:3a7713b1edbc	36	#define __CORE_CA_H_GENERIC
AnnaBridge	171:3a7713b1edbc	37
AnnaBridge	171:3a7713b1edbc	38
AnnaBridge	171:3a7713b1edbc	39	/*******************************************************************************
AnnaBridge	171:3a7713b1edbc	40	* CMSIS definitions
AnnaBridge	171:3a7713b1edbc	41	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	42
AnnaBridge	171:3a7713b1edbc	43	/* CMSIS CA definitions */
AnnaBridge	171:3a7713b1edbc	44	#define __CA_CMSIS_VERSION_MAIN (1U) /!< \brief [31:16] CMSIS-Core(A) main version /
AnnaBridge	171:3a7713b1edbc	45	#define __CA_CMSIS_VERSION_SUB (1U) /!< \brief [15:0] CMSIS-Core(A) sub version /
AnnaBridge	171:3a7713b1edbc	46	#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	171:3a7713b1edbc	47	__CA_CMSIS_VERSION_SUB ) /!< \brief CMSIS-Core(A) version number /
AnnaBridge	171:3a7713b1edbc	48
AnnaBridge	171:3a7713b1edbc	49	#if defined ( __CC_ARM )
AnnaBridge	171:3a7713b1edbc	50	#if defined __TARGET_FPU_VFP
AnnaBridge	171:3a7713b1edbc	51	#if (__FPU_PRESENT == 1)
AnnaBridge	171:3a7713b1edbc	52	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	53	#else
AnnaBridge	171:3a7713b1edbc	54	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	55	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	56	#endif
AnnaBridge	171:3a7713b1edbc	57	#else
AnnaBridge	171:3a7713b1edbc	58	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	59	#endif
AnnaBridge	171:3a7713b1edbc	60
AnnaBridge	171:3a7713b1edbc	61	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	172:65be27845400	62	#if defined __ARM_FP
AnnaBridge	171:3a7713b1edbc	63	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
AnnaBridge	171:3a7713b1edbc	64	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	65	#else
AnnaBridge	171:3a7713b1edbc	66	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	67	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	68	#endif
AnnaBridge	171:3a7713b1edbc	69	#else
AnnaBridge	171:3a7713b1edbc	70	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	71	#endif
AnnaBridge	171:3a7713b1edbc	72
AnnaBridge	171:3a7713b1edbc	73	#elif defined ( __ICCARM__ )
AnnaBridge	171:3a7713b1edbc	74	#if defined __ARMVFP__
AnnaBridge	171:3a7713b1edbc	75	#if (__FPU_PRESENT == 1)
AnnaBridge	171:3a7713b1edbc	76	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	77	#else
AnnaBridge	171:3a7713b1edbc	78	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	79	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	80	#endif
AnnaBridge	171:3a7713b1edbc	81	#else
AnnaBridge	171:3a7713b1edbc	82	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	83	#endif
AnnaBridge	171:3a7713b1edbc	84
AnnaBridge	171:3a7713b1edbc	85	#elif defined ( __TMS470__ )
AnnaBridge	171:3a7713b1edbc	86	#if defined __TI_VFP_SUPPORT__
AnnaBridge	171:3a7713b1edbc	87	#if (__FPU_PRESENT == 1)
AnnaBridge	171:3a7713b1edbc	88	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	89	#else
AnnaBridge	171:3a7713b1edbc	90	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	91	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	92	#endif
AnnaBridge	171:3a7713b1edbc	93	#else
AnnaBridge	171:3a7713b1edbc	94	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	95	#endif
AnnaBridge	171:3a7713b1edbc	96
AnnaBridge	171:3a7713b1edbc	97	#elif defined ( __GNUC__ )
AnnaBridge	171:3a7713b1edbc	98	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	171:3a7713b1edbc	99	#if (__FPU_PRESENT == 1)
AnnaBridge	171:3a7713b1edbc	100	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	101	#else
AnnaBridge	171:3a7713b1edbc	102	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	103	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	104	#endif
AnnaBridge	171:3a7713b1edbc	105	#else
AnnaBridge	171:3a7713b1edbc	106	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	107	#endif
AnnaBridge	171:3a7713b1edbc	108
AnnaBridge	171:3a7713b1edbc	109	#elif defined ( __TASKING__ )
AnnaBridge	171:3a7713b1edbc	110	#if defined __FPU_VFP__
AnnaBridge	171:3a7713b1edbc	111	#if (__FPU_PRESENT == 1)
AnnaBridge	171:3a7713b1edbc	112	#define __FPU_USED 1U
AnnaBridge	171:3a7713b1edbc	113	#else
AnnaBridge	171:3a7713b1edbc	114	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	171:3a7713b1edbc	115	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	116	#endif
AnnaBridge	171:3a7713b1edbc	117	#else
AnnaBridge	171:3a7713b1edbc	118	#define __FPU_USED 0U
AnnaBridge	171:3a7713b1edbc	119	#endif
AnnaBridge	171:3a7713b1edbc	120	#endif
AnnaBridge	171:3a7713b1edbc	121
AnnaBridge	171:3a7713b1edbc	122	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	171:3a7713b1edbc	123
AnnaBridge	171:3a7713b1edbc	124	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	125	}
AnnaBridge	171:3a7713b1edbc	126	#endif
AnnaBridge	171:3a7713b1edbc	127
AnnaBridge	171:3a7713b1edbc	128	#endif /* __CORE_CA_H_GENERIC */
AnnaBridge	171:3a7713b1edbc	129
AnnaBridge	171:3a7713b1edbc	130	#ifndef __CMSIS_GENERIC
AnnaBridge	171:3a7713b1edbc	131
AnnaBridge	171:3a7713b1edbc	132	#ifndef __CORE_CA_H_DEPENDANT
AnnaBridge	171:3a7713b1edbc	133	#define __CORE_CA_H_DEPENDANT
AnnaBridge	171:3a7713b1edbc	134
AnnaBridge	171:3a7713b1edbc	135	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	136	extern "C" {
AnnaBridge	171:3a7713b1edbc	137	#endif
AnnaBridge	171:3a7713b1edbc	138
AnnaBridge	171:3a7713b1edbc	139	/* check device defines and use defaults */
AnnaBridge	171:3a7713b1edbc	140	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	171:3a7713b1edbc	141	#ifndef __CA_REV
AnnaBridge	171:3a7713b1edbc	142	#define __CA_REV 0x0000U
AnnaBridge	171:3a7713b1edbc	143	#warning "__CA_REV not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	144	#endif
AnnaBridge	171:3a7713b1edbc	145
AnnaBridge	171:3a7713b1edbc	146	#ifndef __FPU_PRESENT
AnnaBridge	171:3a7713b1edbc	147	#define __FPU_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	148	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	149	#endif
AnnaBridge	171:3a7713b1edbc	150
AnnaBridge	171:3a7713b1edbc	151	#ifndef __GIC_PRESENT
AnnaBridge	171:3a7713b1edbc	152	#define __GIC_PRESENT 1U
AnnaBridge	171:3a7713b1edbc	153	#warning "__GIC_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	154	#endif
AnnaBridge	171:3a7713b1edbc	155
AnnaBridge	171:3a7713b1edbc	156	#ifndef __TIM_PRESENT
AnnaBridge	171:3a7713b1edbc	157	#define __TIM_PRESENT 1U
AnnaBridge	171:3a7713b1edbc	158	#warning "__TIM_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	159	#endif
AnnaBridge	171:3a7713b1edbc	160
AnnaBridge	171:3a7713b1edbc	161	#ifndef __L2C_PRESENT
AnnaBridge	171:3a7713b1edbc	162	#define __L2C_PRESENT 0U
AnnaBridge	171:3a7713b1edbc	163	#warning "__L2C_PRESENT not defined in device header file; using default!"
AnnaBridge	171:3a7713b1edbc	164	#endif
AnnaBridge	171:3a7713b1edbc	165	#endif
AnnaBridge	171:3a7713b1edbc	166
AnnaBridge	171:3a7713b1edbc	167	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	171:3a7713b1edbc	168	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	169	#define __I volatile /!< \brief Defines 'read only' permissions /
AnnaBridge	171:3a7713b1edbc	170	#else
AnnaBridge	171:3a7713b1edbc	171	#define __I volatile const /!< \brief Defines 'read only' permissions /
AnnaBridge	171:3a7713b1edbc	172	#endif
AnnaBridge	171:3a7713b1edbc	173	#define __O volatile /!< \brief Defines 'write only' permissions /
AnnaBridge	171:3a7713b1edbc	174	#define __IO volatile /!< \brief Defines 'read / write' permissions /
AnnaBridge	171:3a7713b1edbc	175
AnnaBridge	171:3a7713b1edbc	176	/* following defines should be used for structure members */
AnnaBridge	171:3a7713b1edbc	177	#define __IM volatile const /!< \brief Defines 'read only' structure member permissions /
AnnaBridge	171:3a7713b1edbc	178	#define __OM volatile /!< \brief Defines 'write only' structure member permissions /
AnnaBridge	171:3a7713b1edbc	179	#define __IOM volatile /!< \brief Defines 'read / write' structure member permissions /
AnnaBridge	171:3a7713b1edbc	180	#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas
AnnaBridge	171:3a7713b1edbc	181
AnnaBridge	171:3a7713b1edbc	182	/*******************************************************************************
AnnaBridge	171:3a7713b1edbc	183	* Register Abstraction
AnnaBridge	171:3a7713b1edbc	184	Core Register contain:
AnnaBridge	171:3a7713b1edbc	185	- CPSR
AnnaBridge	171:3a7713b1edbc	186	- CP15 Registers
AnnaBridge	171:3a7713b1edbc	187	- L2C-310 Cache Controller
AnnaBridge	171:3a7713b1edbc	188	- Generic Interrupt Controller Distributor
AnnaBridge	171:3a7713b1edbc	189	- Generic Interrupt Controller Interface
AnnaBridge	171:3a7713b1edbc	190	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	191
AnnaBridge	171:3a7713b1edbc	192	/* Core Register CPSR */
AnnaBridge	171:3a7713b1edbc	193	typedef union
AnnaBridge	171:3a7713b1edbc	194	{
AnnaBridge	171:3a7713b1edbc	195	struct
AnnaBridge	171:3a7713b1edbc	196	{
AnnaBridge	171:3a7713b1edbc	197	uint32_t M:5; /!< \brief bit: 0.. 4 Mode field /
AnnaBridge	171:3a7713b1edbc	198	uint32_t T:1; /!< \brief bit: 5 Thumb execution state bit /
AnnaBridge	171:3a7713b1edbc	199	uint32_t F:1; /!< \brief bit: 6 FIQ mask bit /
AnnaBridge	171:3a7713b1edbc	200	uint32_t I:1; /!< \brief bit: 7 IRQ mask bit /
AnnaBridge	171:3a7713b1edbc	201	uint32_t A:1; /!< \brief bit: 8 Asynchronous abort mask bit /
AnnaBridge	171:3a7713b1edbc	202	uint32_t E:1; /!< \brief bit: 9 Endianness execution state bit /
AnnaBridge	171:3a7713b1edbc	203	uint32_t IT1:6; /!< \brief bit: 10..15 If-Then execution state bits 2-7 /
AnnaBridge	171:3a7713b1edbc	204	uint32_t GE:4; /!< \brief bit: 16..19 Greater than or Equal flags /
AnnaBridge	171:3a7713b1edbc	205	RESERVED(0:4, uint32_t)
AnnaBridge	171:3a7713b1edbc	206	uint32_t J:1; /!< \brief bit: 24 Jazelle bit /
AnnaBridge	171:3a7713b1edbc	207	uint32_t IT0:2; /!< \brief bit: 25..26 If-Then execution state bits 0-1 /
AnnaBridge	171:3a7713b1edbc	208	uint32_t Q:1; /!< \brief bit: 27 Saturation condition flag /
AnnaBridge	171:3a7713b1edbc	209	uint32_t V:1; /!< \brief bit: 28 Overflow condition code flag /
AnnaBridge	171:3a7713b1edbc	210	uint32_t C:1; /!< \brief bit: 29 Carry condition code flag /
AnnaBridge	171:3a7713b1edbc	211	uint32_t Z:1; /!< \brief bit: 30 Zero condition code flag /
AnnaBridge	171:3a7713b1edbc	212	uint32_t N:1; /!< \brief bit: 31 Negative condition code flag /
AnnaBridge	171:3a7713b1edbc	213	} b; /!< \brief Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	214	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	171:3a7713b1edbc	215	} CPSR_Type;
AnnaBridge	171:3a7713b1edbc	216
AnnaBridge	171:3a7713b1edbc	217
AnnaBridge	171:3a7713b1edbc	218
AnnaBridge	171:3a7713b1edbc	219	/* CPSR Register Definitions */
AnnaBridge	171:3a7713b1edbc	220	#define CPSR_N_Pos 31U /!< \brief CPSR: N Position /
AnnaBridge	171:3a7713b1edbc	221	#define CPSR_N_Msk (1UL << CPSR_N_Pos) /!< \brief CPSR: N Mask /
AnnaBridge	171:3a7713b1edbc	222
AnnaBridge	171:3a7713b1edbc	223	#define CPSR_Z_Pos 30U /!< \brief CPSR: Z Position /
AnnaBridge	171:3a7713b1edbc	224	#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /!< \brief CPSR: Z Mask /
AnnaBridge	171:3a7713b1edbc	225
AnnaBridge	171:3a7713b1edbc	226	#define CPSR_C_Pos 29U /!< \brief CPSR: C Position /
AnnaBridge	171:3a7713b1edbc	227	#define CPSR_C_Msk (1UL << CPSR_C_Pos) /!< \brief CPSR: C Mask /
AnnaBridge	171:3a7713b1edbc	228
AnnaBridge	171:3a7713b1edbc	229	#define CPSR_V_Pos 28U /!< \brief CPSR: V Position /
AnnaBridge	171:3a7713b1edbc	230	#define CPSR_V_Msk (1UL << CPSR_V_Pos) /!< \brief CPSR: V Mask /
AnnaBridge	171:3a7713b1edbc	231
AnnaBridge	171:3a7713b1edbc	232	#define CPSR_Q_Pos 27U /!< \brief CPSR: Q Position /
AnnaBridge	171:3a7713b1edbc	233	#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /!< \brief CPSR: Q Mask /
AnnaBridge	171:3a7713b1edbc	234
AnnaBridge	171:3a7713b1edbc	235	#define CPSR_IT0_Pos 25U /!< \brief CPSR: IT0 Position /
AnnaBridge	171:3a7713b1edbc	236	#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /!< \brief CPSR: IT0 Mask /
AnnaBridge	171:3a7713b1edbc	237
AnnaBridge	171:3a7713b1edbc	238	#define CPSR_J_Pos 24U /!< \brief CPSR: J Position /
AnnaBridge	171:3a7713b1edbc	239	#define CPSR_J_Msk (1UL << CPSR_J_Pos) /!< \brief CPSR: J Mask /
AnnaBridge	171:3a7713b1edbc	240
AnnaBridge	171:3a7713b1edbc	241	#define CPSR_GE_Pos 16U /!< \brief CPSR: GE Position /
AnnaBridge	171:3a7713b1edbc	242	#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /!< \brief CPSR: GE Mask /
AnnaBridge	171:3a7713b1edbc	243
AnnaBridge	171:3a7713b1edbc	244	#define CPSR_IT1_Pos 10U /!< \brief CPSR: IT1 Position /
AnnaBridge	171:3a7713b1edbc	245	#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /!< \brief CPSR: IT1 Mask /
AnnaBridge	171:3a7713b1edbc	246
AnnaBridge	171:3a7713b1edbc	247	#define CPSR_E_Pos 9U /!< \brief CPSR: E Position /
AnnaBridge	171:3a7713b1edbc	248	#define CPSR_E_Msk (1UL << CPSR_E_Pos) /!< \brief CPSR: E Mask /
AnnaBridge	171:3a7713b1edbc	249
AnnaBridge	171:3a7713b1edbc	250	#define CPSR_A_Pos 8U /!< \brief CPSR: A Position /
AnnaBridge	171:3a7713b1edbc	251	#define CPSR_A_Msk (1UL << CPSR_A_Pos) /!< \brief CPSR: A Mask /
AnnaBridge	171:3a7713b1edbc	252
AnnaBridge	171:3a7713b1edbc	253	#define CPSR_I_Pos 7U /!< \brief CPSR: I Position /
AnnaBridge	171:3a7713b1edbc	254	#define CPSR_I_Msk (1UL << CPSR_I_Pos) /!< \brief CPSR: I Mask /
AnnaBridge	171:3a7713b1edbc	255
AnnaBridge	171:3a7713b1edbc	256	#define CPSR_F_Pos 6U /!< \brief CPSR: F Position /
AnnaBridge	171:3a7713b1edbc	257	#define CPSR_F_Msk (1UL << CPSR_F_Pos) /!< \brief CPSR: F Mask /
AnnaBridge	171:3a7713b1edbc	258
AnnaBridge	171:3a7713b1edbc	259	#define CPSR_T_Pos 5U /!< \brief CPSR: T Position /
AnnaBridge	171:3a7713b1edbc	260	#define CPSR_T_Msk (1UL << CPSR_T_Pos) /!< \brief CPSR: T Mask /
AnnaBridge	171:3a7713b1edbc	261
AnnaBridge	171:3a7713b1edbc	262	#define CPSR_M_Pos 0U /!< \brief CPSR: M Position /
AnnaBridge	171:3a7713b1edbc	263	#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /!< \brief CPSR: M Mask /
AnnaBridge	171:3a7713b1edbc	264
AnnaBridge	171:3a7713b1edbc	265	#define CPSR_M_USR 0x10U /!< \brief CPSR: M User mode (PL0) /
AnnaBridge	171:3a7713b1edbc	266	#define CPSR_M_FIQ 0x11U /!< \brief CPSR: M Fast Interrupt mode (PL1) /
AnnaBridge	171:3a7713b1edbc	267	#define CPSR_M_IRQ 0x12U /!< \brief CPSR: M Interrupt mode (PL1) /
AnnaBridge	171:3a7713b1edbc	268	#define CPSR_M_SVC 0x13U /!< \brief CPSR: M Supervisor mode (PL1) /
AnnaBridge	171:3a7713b1edbc	269	#define CPSR_M_MON 0x16U /!< \brief CPSR: M Monitor mode (PL1) /
AnnaBridge	171:3a7713b1edbc	270	#define CPSR_M_ABT 0x17U /!< \brief CPSR: M Abort mode (PL1) /
AnnaBridge	171:3a7713b1edbc	271	#define CPSR_M_HYP 0x1AU /!< \brief CPSR: M Hypervisor mode (PL2) /
AnnaBridge	171:3a7713b1edbc	272	#define CPSR_M_UND 0x1BU /!< \brief CPSR: M Undefined mode (PL1) /
AnnaBridge	171:3a7713b1edbc	273	#define CPSR_M_SYS 0x1FU /!< \brief CPSR: M System mode (PL1) /
AnnaBridge	171:3a7713b1edbc	274
AnnaBridge	171:3a7713b1edbc	275	/* CP15 Register SCTLR */
AnnaBridge	171:3a7713b1edbc	276	typedef union
AnnaBridge	171:3a7713b1edbc	277	{
AnnaBridge	171:3a7713b1edbc	278	struct
AnnaBridge	171:3a7713b1edbc	279	{
AnnaBridge	171:3a7713b1edbc	280	uint32_t M:1; /!< \brief bit: 0 MMU enable /
AnnaBridge	171:3a7713b1edbc	281	uint32_t A:1; /!< \brief bit: 1 Alignment check enable /
AnnaBridge	171:3a7713b1edbc	282	uint32_t C:1; /!< \brief bit: 2 Cache enable /
AnnaBridge	171:3a7713b1edbc	283	RESERVED(0:2, uint32_t)
AnnaBridge	171:3a7713b1edbc	284	uint32_t CP15BEN:1; /!< \brief bit: 5 CP15 barrier enable /
AnnaBridge	171:3a7713b1edbc	285	RESERVED(1:1, uint32_t)
AnnaBridge	171:3a7713b1edbc	286	uint32_t B:1; /!< \brief bit: 7 Endianness model /
AnnaBridge	171:3a7713b1edbc	287	RESERVED(2:2, uint32_t)
AnnaBridge	171:3a7713b1edbc	288	uint32_t SW:1; /!< \brief bit: 10 SWP and SWPB enable /
AnnaBridge	171:3a7713b1edbc	289	uint32_t Z:1; /!< \brief bit: 11 Branch prediction enable /
AnnaBridge	171:3a7713b1edbc	290	uint32_t I:1; /!< \brief bit: 12 Instruction cache enable /
AnnaBridge	171:3a7713b1edbc	291	uint32_t V:1; /!< \brief bit: 13 Vectors bit /
AnnaBridge	171:3a7713b1edbc	292	uint32_t RR:1; /!< \brief bit: 14 Round Robin select /
AnnaBridge	171:3a7713b1edbc	293	RESERVED(3:2, uint32_t)
AnnaBridge	171:3a7713b1edbc	294	uint32_t HA:1; /!< \brief bit: 17 Hardware Access flag enable /
AnnaBridge	171:3a7713b1edbc	295	RESERVED(4:1, uint32_t)
AnnaBridge	171:3a7713b1edbc	296	uint32_t WXN:1; /!< \brief bit: 19 Write permission implies XN /
AnnaBridge	171:3a7713b1edbc	297	uint32_t UWXN:1; /!< \brief bit: 20 Unprivileged write permission implies PL1 XN /
AnnaBridge	171:3a7713b1edbc	298	uint32_t FI:1; /!< \brief bit: 21 Fast interrupts configuration enable /
AnnaBridge	171:3a7713b1edbc	299	uint32_t U:1; /!< \brief bit: 22 Alignment model /
AnnaBridge	171:3a7713b1edbc	300	RESERVED(5:1, uint32_t)
AnnaBridge	171:3a7713b1edbc	301	uint32_t VE:1; /!< \brief bit: 24 Interrupt Vectors Enable /
AnnaBridge	171:3a7713b1edbc	302	uint32_t EE:1; /!< \brief bit: 25 Exception Endianness /
AnnaBridge	171:3a7713b1edbc	303	RESERVED(6:1, uint32_t)
AnnaBridge	171:3a7713b1edbc	304	uint32_t NMFI:1; /!< \brief bit: 27 Non-maskable FIQ (NMFI) support /
AnnaBridge	171:3a7713b1edbc	305	uint32_t TRE:1; /!< \brief bit: 28 TEX remap enable. /
AnnaBridge	171:3a7713b1edbc	306	uint32_t AFE:1; /!< \brief bit: 29 Access flag enable /
AnnaBridge	171:3a7713b1edbc	307	uint32_t TE:1; /!< \brief bit: 30 Thumb Exception enable /
AnnaBridge	171:3a7713b1edbc	308	RESERVED(7:1, uint32_t)
AnnaBridge	171:3a7713b1edbc	309	} b; /!< \brief Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	310	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	171:3a7713b1edbc	311	} SCTLR_Type;
AnnaBridge	171:3a7713b1edbc	312
AnnaBridge	171:3a7713b1edbc	313	#define SCTLR_TE_Pos 30U /!< \brief SCTLR: TE Position /
AnnaBridge	171:3a7713b1edbc	314	#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /!< \brief SCTLR: TE Mask /
AnnaBridge	171:3a7713b1edbc	315
AnnaBridge	171:3a7713b1edbc	316	#define SCTLR_AFE_Pos 29U /!< \brief SCTLR: AFE Position /
AnnaBridge	171:3a7713b1edbc	317	#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /!< \brief SCTLR: AFE Mask /
AnnaBridge	171:3a7713b1edbc	318
AnnaBridge	171:3a7713b1edbc	319	#define SCTLR_TRE_Pos 28U /!< \brief SCTLR: TRE Position /
AnnaBridge	171:3a7713b1edbc	320	#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /!< \brief SCTLR: TRE Mask /
AnnaBridge	171:3a7713b1edbc	321
AnnaBridge	171:3a7713b1edbc	322	#define SCTLR_NMFI_Pos 27U /!< \brief SCTLR: NMFI Position /
AnnaBridge	171:3a7713b1edbc	323	#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /!< \brief SCTLR: NMFI Mask /
AnnaBridge	171:3a7713b1edbc	324
AnnaBridge	171:3a7713b1edbc	325	#define SCTLR_EE_Pos 25U /!< \brief SCTLR: EE Position /
AnnaBridge	171:3a7713b1edbc	326	#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /!< \brief SCTLR: EE Mask /
AnnaBridge	171:3a7713b1edbc	327
AnnaBridge	171:3a7713b1edbc	328	#define SCTLR_VE_Pos 24U /!< \brief SCTLR: VE Position /
AnnaBridge	171:3a7713b1edbc	329	#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /!< \brief SCTLR: VE Mask /
AnnaBridge	171:3a7713b1edbc	330
AnnaBridge	171:3a7713b1edbc	331	#define SCTLR_U_Pos 22U /!< \brief SCTLR: U Position /
AnnaBridge	171:3a7713b1edbc	332	#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /!< \brief SCTLR: U Mask /
AnnaBridge	171:3a7713b1edbc	333
AnnaBridge	171:3a7713b1edbc	334	#define SCTLR_FI_Pos 21U /!< \brief SCTLR: FI Position /
AnnaBridge	171:3a7713b1edbc	335	#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /!< \brief SCTLR: FI Mask /
AnnaBridge	171:3a7713b1edbc	336
AnnaBridge	171:3a7713b1edbc	337	#define SCTLR_UWXN_Pos 20U /!< \brief SCTLR: UWXN Position /
AnnaBridge	171:3a7713b1edbc	338	#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /!< \brief SCTLR: UWXN Mask /
AnnaBridge	171:3a7713b1edbc	339
AnnaBridge	171:3a7713b1edbc	340	#define SCTLR_WXN_Pos 19U /!< \brief SCTLR: WXN Position /
AnnaBridge	171:3a7713b1edbc	341	#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /!< \brief SCTLR: WXN Mask /
AnnaBridge	171:3a7713b1edbc	342
AnnaBridge	171:3a7713b1edbc	343	#define SCTLR_HA_Pos 17U /!< \brief SCTLR: HA Position /
AnnaBridge	171:3a7713b1edbc	344	#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /!< \brief SCTLR: HA Mask /
AnnaBridge	171:3a7713b1edbc	345
AnnaBridge	171:3a7713b1edbc	346	#define SCTLR_RR_Pos 14U /!< \brief SCTLR: RR Position /
AnnaBridge	171:3a7713b1edbc	347	#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /!< \brief SCTLR: RR Mask /
AnnaBridge	171:3a7713b1edbc	348
AnnaBridge	171:3a7713b1edbc	349	#define SCTLR_V_Pos 13U /!< \brief SCTLR: V Position /
AnnaBridge	171:3a7713b1edbc	350	#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /!< \brief SCTLR: V Mask /
AnnaBridge	171:3a7713b1edbc	351
AnnaBridge	171:3a7713b1edbc	352	#define SCTLR_I_Pos 12U /!< \brief SCTLR: I Position /
AnnaBridge	171:3a7713b1edbc	353	#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /!< \brief SCTLR: I Mask /
AnnaBridge	171:3a7713b1edbc	354
AnnaBridge	171:3a7713b1edbc	355	#define SCTLR_Z_Pos 11U /!< \brief SCTLR: Z Position /
AnnaBridge	171:3a7713b1edbc	356	#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /!< \brief SCTLR: Z Mask /
AnnaBridge	171:3a7713b1edbc	357
AnnaBridge	171:3a7713b1edbc	358	#define SCTLR_SW_Pos 10U /!< \brief SCTLR: SW Position /
AnnaBridge	171:3a7713b1edbc	359	#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /!< \brief SCTLR: SW Mask /
AnnaBridge	171:3a7713b1edbc	360
AnnaBridge	171:3a7713b1edbc	361	#define SCTLR_B_Pos 7U /!< \brief SCTLR: B Position /
AnnaBridge	171:3a7713b1edbc	362	#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /!< \brief SCTLR: B Mask /
AnnaBridge	171:3a7713b1edbc	363
AnnaBridge	171:3a7713b1edbc	364	#define SCTLR_CP15BEN_Pos 5U /!< \brief SCTLR: CP15BEN Position /
AnnaBridge	171:3a7713b1edbc	365	#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /!< \brief SCTLR: CP15BEN Mask /
AnnaBridge	171:3a7713b1edbc	366
AnnaBridge	171:3a7713b1edbc	367	#define SCTLR_C_Pos 2U /!< \brief SCTLR: C Position /
AnnaBridge	171:3a7713b1edbc	368	#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /!< \brief SCTLR: C Mask /
AnnaBridge	171:3a7713b1edbc	369
AnnaBridge	171:3a7713b1edbc	370	#define SCTLR_A_Pos 1U /!< \brief SCTLR: A Position /
AnnaBridge	171:3a7713b1edbc	371	#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /!< \brief SCTLR: A Mask /
AnnaBridge	171:3a7713b1edbc	372
AnnaBridge	171:3a7713b1edbc	373	#define SCTLR_M_Pos 0U /!< \brief SCTLR: M Position /
AnnaBridge	171:3a7713b1edbc	374	#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /!< \brief SCTLR: M Mask /
AnnaBridge	171:3a7713b1edbc	375
AnnaBridge	171:3a7713b1edbc	376	/* CP15 Register ACTLR */
AnnaBridge	171:3a7713b1edbc	377	typedef union
AnnaBridge	171:3a7713b1edbc	378	{
AnnaBridge	171:3a7713b1edbc	379	#if __CORTEX_A == 5 \|\| defined(DOXYGEN)
AnnaBridge	171:3a7713b1edbc	380	/** \brief Structure used for bit access on Cortex-A5 */
AnnaBridge	171:3a7713b1edbc	381	struct
AnnaBridge	171:3a7713b1edbc	382	{
AnnaBridge	171:3a7713b1edbc	383	uint32_t FW:1; /!< \brief bit: 0 Cache and TLB maintenance broadcast /
AnnaBridge	171:3a7713b1edbc	384	RESERVED(0:5, uint32_t)
AnnaBridge	171:3a7713b1edbc	385	uint32_t SMP:1; /!< \brief bit: 6 Enables coherent requests to the processor /
AnnaBridge	171:3a7713b1edbc	386	uint32_t EXCL:1; /!< \brief bit: 7 Exclusive L1/L2 cache control /
AnnaBridge	171:3a7713b1edbc	387	RESERVED(1:2, uint32_t)
AnnaBridge	171:3a7713b1edbc	388	uint32_t DODMBS:1; /!< \brief bit: 10 Disable optimized data memory barrier behavior /
AnnaBridge	171:3a7713b1edbc	389	uint32_t DWBST:1; /!< \brief bit: 11 AXI data write bursts to Normal memory /
AnnaBridge	171:3a7713b1edbc	390	uint32_t RADIS:1; /!< \brief bit: 12 L1 Data Cache read-allocate mode disable /
AnnaBridge	171:3a7713b1edbc	391	uint32_t L1PCTL:2; /!< \brief bit:13..14 L1 Data prefetch control /
AnnaBridge	171:3a7713b1edbc	392	uint32_t BP:2; /!< \brief bit:16..15 Branch prediction policy /
AnnaBridge	171:3a7713b1edbc	393	uint32_t RSDIS:1; /!< \brief bit: 17 Disable return stack operation /
AnnaBridge	171:3a7713b1edbc	394	uint32_t BTDIS:1; /!< \brief bit: 18 Disable indirect Branch Target Address Cache (BTAC) /
AnnaBridge	171:3a7713b1edbc	395	RESERVED(3:9, uint32_t)
AnnaBridge	171:3a7713b1edbc	396	uint32_t DBDI:1; /!< \brief bit: 28 Disable branch dual issue /
AnnaBridge	171:3a7713b1edbc	397	RESERVED(7:3, uint32_t)
AnnaBridge	171:3a7713b1edbc	398	} b;
AnnaBridge	171:3a7713b1edbc	399	#endif
AnnaBridge	171:3a7713b1edbc	400	#if __CORTEX_A == 7 \|\| defined(DOXYGEN)
AnnaBridge	171:3a7713b1edbc	401	/** \brief Structure used for bit access on Cortex-A7 */
AnnaBridge	171:3a7713b1edbc	402	struct
AnnaBridge	171:3a7713b1edbc	403	{
AnnaBridge	171:3a7713b1edbc	404	RESERVED(0:6, uint32_t)
AnnaBridge	171:3a7713b1edbc	405	uint32_t SMP:1; /!< \brief bit: 6 Enables coherent requests to the processor /
AnnaBridge	171:3a7713b1edbc	406	RESERVED(1:3, uint32_t)
AnnaBridge	171:3a7713b1edbc	407	uint32_t DODMBS:1; /!< \brief bit: 10 Disable optimized data memory barrier behavior /
AnnaBridge	171:3a7713b1edbc	408	uint32_t L2RADIS:1; /!< \brief bit: 11 L2 Data Cache read-allocate mode disable /
AnnaBridge	171:3a7713b1edbc	409	uint32_t L1RADIS:1; /!< \brief bit: 12 L1 Data Cache read-allocate mode disable /
AnnaBridge	171:3a7713b1edbc	410	uint32_t L1PCTL:2; /!< \brief bit:13..14 L1 Data prefetch control /
AnnaBridge	171:3a7713b1edbc	411	uint32_t DDVM:1; /!< \brief bit: 15 Disable Distributed Virtual Memory (DVM) transactions /
AnnaBridge	171:3a7713b1edbc	412	RESERVED(3:12, uint32_t)
AnnaBridge	171:3a7713b1edbc	413	uint32_t DDI:1; /!< \brief bit: 28 Disable dual issue /
AnnaBridge	171:3a7713b1edbc	414	RESERVED(7:3, uint32_t)
AnnaBridge	171:3a7713b1edbc	415	} b;
AnnaBridge	171:3a7713b1edbc	416	#endif
AnnaBridge	171:3a7713b1edbc	417	#if __CORTEX_A == 9 \|\| defined(DOXYGEN)
AnnaBridge	171:3a7713b1edbc	418	/** \brief Structure used for bit access on Cortex-A9 */
AnnaBridge	171:3a7713b1edbc	419	struct
AnnaBridge	171:3a7713b1edbc	420	{
AnnaBridge	171:3a7713b1edbc	421	uint32_t FW:1; /!< \brief bit: 0 Cache and TLB maintenance broadcast /
AnnaBridge	171:3a7713b1edbc	422	RESERVED(0:1, uint32_t)
AnnaBridge	171:3a7713b1edbc	423	uint32_t L1PE:1; /!< \brief bit: 2 Dside prefetch /
AnnaBridge	171:3a7713b1edbc	424	uint32_t WFLZM:1; /!< \brief bit: 3 Cache and TLB maintenance broadcast /
AnnaBridge	171:3a7713b1edbc	425	RESERVED(1:2, uint32_t)
AnnaBridge	171:3a7713b1edbc	426	uint32_t SMP:1; /!< \brief bit: 6 Enables coherent requests to the processor /
AnnaBridge	171:3a7713b1edbc	427	uint32_t EXCL:1; /!< \brief bit: 7 Exclusive L1/L2 cache control /
AnnaBridge	171:3a7713b1edbc	428	uint32_t AOW:1; /!< \brief bit: 8 Enable allocation in one cache way only /
AnnaBridge	171:3a7713b1edbc	429	uint32_t PARITY:1; /!< \brief bit: 9 Support for parity checking, if implemented /
AnnaBridge	171:3a7713b1edbc	430	RESERVED(7:22, uint32_t)
AnnaBridge	171:3a7713b1edbc	431	} b;
AnnaBridge	171:3a7713b1edbc	432	#endif
AnnaBridge	171:3a7713b1edbc	433	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	171:3a7713b1edbc	434	} ACTLR_Type;
AnnaBridge	171:3a7713b1edbc	435
AnnaBridge	171:3a7713b1edbc	436	#define ACTLR_DDI_Pos 28U /!< \brief ACTLR: DDI Position /
AnnaBridge	171:3a7713b1edbc	437	#define ACTLR_DDI_Msk (1UL << ACTLR_DDI_Pos) /!< \brief ACTLR: DDI Mask /
AnnaBridge	171:3a7713b1edbc	438
AnnaBridge	171:3a7713b1edbc	439	#define ACTLR_DBDI_Pos 28U /!< \brief ACTLR: DBDI Position /
AnnaBridge	171:3a7713b1edbc	440	#define ACTLR_DBDI_Msk (1UL << ACTLR_DBDI_Pos) /!< \brief ACTLR: DBDI Mask /
AnnaBridge	171:3a7713b1edbc	441
AnnaBridge	171:3a7713b1edbc	442	#define ACTLR_BTDIS_Pos 18U /!< \brief ACTLR: BTDIS Position /
AnnaBridge	171:3a7713b1edbc	443	#define ACTLR_BTDIS_Msk (1UL << ACTLR_BTDIS_Pos) /!< \brief ACTLR: BTDIS Mask /
AnnaBridge	171:3a7713b1edbc	444
AnnaBridge	171:3a7713b1edbc	445	#define ACTLR_RSDIS_Pos 17U /!< \brief ACTLR: RSDIS Position /
AnnaBridge	171:3a7713b1edbc	446	#define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /!< \brief ACTLR: RSDIS Mask /
AnnaBridge	171:3a7713b1edbc	447
AnnaBridge	171:3a7713b1edbc	448	#define ACTLR_BP_Pos 15U /!< \brief ACTLR: BP Position /
AnnaBridge	171:3a7713b1edbc	449	#define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /!< \brief ACTLR: BP Mask /
AnnaBridge	171:3a7713b1edbc	450
AnnaBridge	171:3a7713b1edbc	451	#define ACTLR_DDVM_Pos 15U /!< \brief ACTLR: DDVM Position /
AnnaBridge	171:3a7713b1edbc	452	#define ACTLR_DDVM_Msk (1UL << ACTLR_DDVM_Pos) /!< \brief ACTLR: DDVM Mask /
AnnaBridge	171:3a7713b1edbc	453
AnnaBridge	171:3a7713b1edbc	454	#define ACTLR_L1PCTL_Pos 13U /!< \brief ACTLR: L1PCTL Position /
AnnaBridge	171:3a7713b1edbc	455	#define ACTLR_L1PCTL_Msk (3UL << ACTLR_L1PCTL_Pos) /!< \brief ACTLR: L1PCTL Mask /
AnnaBridge	171:3a7713b1edbc	456
AnnaBridge	171:3a7713b1edbc	457	#define ACTLR_RADIS_Pos 12U /!< \brief ACTLR: RADIS Position /
AnnaBridge	171:3a7713b1edbc	458	#define ACTLR_RADIS_Msk (1UL << ACTLR_RADIS_Pos) /!< \brief ACTLR: RADIS Mask /
AnnaBridge	171:3a7713b1edbc	459
AnnaBridge	171:3a7713b1edbc	460	#define ACTLR_L1RADIS_Pos 12U /!< \brief ACTLR: L1RADIS Position /
AnnaBridge	171:3a7713b1edbc	461	#define ACTLR_L1RADIS_Msk (1UL << ACTLR_L1RADIS_Pos) /!< \brief ACTLR: L1RADIS Mask /
AnnaBridge	171:3a7713b1edbc	462
AnnaBridge	171:3a7713b1edbc	463	#define ACTLR_DWBST_Pos 11U /!< \brief ACTLR: DWBST Position /
AnnaBridge	171:3a7713b1edbc	464	#define ACTLR_DWBST_Msk (1UL << ACTLR_DWBST_Pos) /!< \brief ACTLR: DWBST Mask /
AnnaBridge	171:3a7713b1edbc	465
AnnaBridge	171:3a7713b1edbc	466	#define ACTLR_L2RADIS_Pos 11U /!< \brief ACTLR: L2RADIS Position /
AnnaBridge	171:3a7713b1edbc	467	#define ACTLR_L2RADIS_Msk (1UL << ACTLR_L2RADIS_Pos) /!< \brief ACTLR: L2RADIS Mask /
AnnaBridge	171:3a7713b1edbc	468
AnnaBridge	171:3a7713b1edbc	469	#define ACTLR_DODMBS_Pos 10U /!< \brief ACTLR: DODMBS Position /
AnnaBridge	171:3a7713b1edbc	470	#define ACTLR_DODMBS_Msk (1UL << ACTLR_DODMBS_Pos) /!< \brief ACTLR: DODMBS Mask /
AnnaBridge	171:3a7713b1edbc	471
AnnaBridge	171:3a7713b1edbc	472	#define ACTLR_PARITY_Pos 9U /!< \brief ACTLR: PARITY Position /
AnnaBridge	171:3a7713b1edbc	473	#define ACTLR_PARITY_Msk (1UL << ACTLR_PARITY_Pos) /!< \brief ACTLR: PARITY Mask /
AnnaBridge	171:3a7713b1edbc	474
AnnaBridge	171:3a7713b1edbc	475	#define ACTLR_AOW_Pos 8U /!< \brief ACTLR: AOW Position /
AnnaBridge	171:3a7713b1edbc	476	#define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /!< \brief ACTLR: AOW Mask /
AnnaBridge	171:3a7713b1edbc	477
AnnaBridge	171:3a7713b1edbc	478	#define ACTLR_EXCL_Pos 7U /!< \brief ACTLR: EXCL Position /
AnnaBridge	171:3a7713b1edbc	479	#define ACTLR_EXCL_Msk (1UL << ACTLR_EXCL_Pos) /!< \brief ACTLR: EXCL Mask /
AnnaBridge	171:3a7713b1edbc	480
AnnaBridge	171:3a7713b1edbc	481	#define ACTLR_SMP_Pos 6U /!< \brief ACTLR: SMP Position /
AnnaBridge	171:3a7713b1edbc	482	#define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /!< \brief ACTLR: SMP Mask /
AnnaBridge	171:3a7713b1edbc	483
AnnaBridge	171:3a7713b1edbc	484	#define ACTLR_WFLZM_Pos 3U /!< \brief ACTLR: WFLZM Position /
AnnaBridge	171:3a7713b1edbc	485	#define ACTLR_WFLZM_Msk (1UL << ACTLR_WFLZM_Pos) /!< \brief ACTLR: WFLZM Mask /
AnnaBridge	171:3a7713b1edbc	486
AnnaBridge	171:3a7713b1edbc	487	#define ACTLR_L1PE_Pos 2U /!< \brief ACTLR: L1PE Position /
AnnaBridge	171:3a7713b1edbc	488	#define ACTLR_L1PE_Msk (1UL << ACTLR_L1PE_Pos) /!< \brief ACTLR: L1PE Mask /
AnnaBridge	171:3a7713b1edbc	489
AnnaBridge	171:3a7713b1edbc	490	#define ACTLR_FW_Pos 0U /!< \brief ACTLR: FW Position /
AnnaBridge	171:3a7713b1edbc	491	#define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /!< \brief ACTLR: FW Mask /
AnnaBridge	171:3a7713b1edbc	492
AnnaBridge	171:3a7713b1edbc	493	/* CP15 Register CPACR */
AnnaBridge	171:3a7713b1edbc	494	typedef union
AnnaBridge	171:3a7713b1edbc	495	{
AnnaBridge	171:3a7713b1edbc	496	struct
AnnaBridge	171:3a7713b1edbc	497	{
AnnaBridge	171:3a7713b1edbc	498	uint32_t CP0:2; /!< \brief bit: 0..1 Access rights for coprocessor 0 /
AnnaBridge	171:3a7713b1edbc	499	uint32_t CP1:2; /!< \brief bit: 2..3 Access rights for coprocessor 1 /
AnnaBridge	171:3a7713b1edbc	500	uint32_t CP2:2; /!< \brief bit: 4..5 Access rights for coprocessor 2 /
AnnaBridge	171:3a7713b1edbc	501	uint32_t CP3:2; /!< \brief bit: 6..7 Access rights for coprocessor 3 /
AnnaBridge	171:3a7713b1edbc	502	uint32_t CP4:2; /!< \brief bit: 8..9 Access rights for coprocessor 4 /
AnnaBridge	171:3a7713b1edbc	503	uint32_t CP5:2; /!< \brief bit:10..11 Access rights for coprocessor 5 /
AnnaBridge	171:3a7713b1edbc	504	uint32_t CP6:2; /!< \brief bit:12..13 Access rights for coprocessor 6 /
AnnaBridge	171:3a7713b1edbc	505	uint32_t CP7:2; /!< \brief bit:14..15 Access rights for coprocessor 7 /
AnnaBridge	171:3a7713b1edbc	506	uint32_t CP8:2; /!< \brief bit:16..17 Access rights for coprocessor 8 /
AnnaBridge	171:3a7713b1edbc	507	uint32_t CP9:2; /!< \brief bit:18..19 Access rights for coprocessor 9 /
AnnaBridge	171:3a7713b1edbc	508	uint32_t CP10:2; /!< \brief bit:20..21 Access rights for coprocessor 10 /
AnnaBridge	171:3a7713b1edbc	509	uint32_t CP11:2; /!< \brief bit:22..23 Access rights for coprocessor 11 /
AnnaBridge	171:3a7713b1edbc	510	uint32_t CP12:2; /!< \brief bit:24..25 Access rights for coprocessor 11 /
AnnaBridge	171:3a7713b1edbc	511	uint32_t CP13:2; /!< \brief bit:26..27 Access rights for coprocessor 11 /
AnnaBridge	171:3a7713b1edbc	512	uint32_t TRCDIS:1; /!< \brief bit: 28 Disable CP14 access to trace registers /
AnnaBridge	171:3a7713b1edbc	513	RESERVED(0:1, uint32_t)
AnnaBridge	171:3a7713b1edbc	514	uint32_t D32DIS:1; /!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file /
AnnaBridge	171:3a7713b1edbc	515	uint32_t ASEDIS:1; /!< \brief bit: 31 Disable Advanced SIMD Functionality /
AnnaBridge	171:3a7713b1edbc	516	} b; /!< \brief Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	517	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	171:3a7713b1edbc	518	} CPACR_Type;
AnnaBridge	171:3a7713b1edbc	519
AnnaBridge	171:3a7713b1edbc	520	#define CPACR_ASEDIS_Pos 31U /!< \brief CPACR: ASEDIS Position /
AnnaBridge	171:3a7713b1edbc	521	#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /!< \brief CPACR: ASEDIS Mask /
AnnaBridge	171:3a7713b1edbc	522
AnnaBridge	171:3a7713b1edbc	523	#define CPACR_D32DIS_Pos 30U /!< \brief CPACR: D32DIS Position /
AnnaBridge	171:3a7713b1edbc	524	#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /!< \brief CPACR: D32DIS Mask /
AnnaBridge	171:3a7713b1edbc	525
AnnaBridge	171:3a7713b1edbc	526	#define CPACR_TRCDIS_Pos 28U /!< \brief CPACR: D32DIS Position /
AnnaBridge	171:3a7713b1edbc	527	#define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /!< \brief CPACR: D32DIS Mask /
AnnaBridge	171:3a7713b1edbc	528
AnnaBridge	171:3a7713b1edbc	529	#define CPACR_CP_Pos_(n) (n2U) /!< \brief CPACR: CPn Position */
AnnaBridge	171:3a7713b1edbc	530	#define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /!< \brief CPACR: CPn Mask /
AnnaBridge	171:3a7713b1edbc	531
AnnaBridge	171:3a7713b1edbc	532	#define CPACR_CP_NA 0U /!< \brief CPACR CPn field: Access denied. /
AnnaBridge	171:3a7713b1edbc	533	#define CPACR_CP_PL1 1U /!< \brief CPACR CPn field: Accessible from PL1 only. /
AnnaBridge	171:3a7713b1edbc	534	#define CPACR_CP_FA 3U /!< \brief CPACR CPn field: Full access. /
AnnaBridge	171:3a7713b1edbc	535
AnnaBridge	171:3a7713b1edbc	536	/* CP15 Register DFSR */
AnnaBridge	171:3a7713b1edbc	537	typedef union
AnnaBridge	171:3a7713b1edbc	538	{
AnnaBridge	171:3a7713b1edbc	539	struct
AnnaBridge	171:3a7713b1edbc	540	{
AnnaBridge	171:3a7713b1edbc	541	uint32_t FS0:4; /!< \brief bit: 0.. 3 Fault Status bits bit 0-3 /
AnnaBridge	171:3a7713b1edbc	542	uint32_t Domain:4; /!< \brief bit: 4.. 7 Fault on which domain /
AnnaBridge	171:3a7713b1edbc	543	RESERVED(0:1, uint32_t)
AnnaBridge	171:3a7713b1edbc	544	uint32_t LPAE:1; /!< \brief bit: 9 Large Physical Address Extension /
AnnaBridge	171:3a7713b1edbc	545	uint32_t FS1:1; /!< \brief bit: 10 Fault Status bits bit 4 /
AnnaBridge	171:3a7713b1edbc	546	uint32_t WnR:1; /!< \brief bit: 11 Write not Read bit /
AnnaBridge	171:3a7713b1edbc	547	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
AnnaBridge	171:3a7713b1edbc	548	uint32_t CM:1; /!< \brief bit: 13 Cache maintenance fault /
AnnaBridge	171:3a7713b1edbc	549	RESERVED(1:18, uint32_t)
AnnaBridge	171:3a7713b1edbc	550	} s; /!< \brief Structure used for bit access in short format /
AnnaBridge	171:3a7713b1edbc	551	struct
AnnaBridge	171:3a7713b1edbc	552	{
AnnaBridge	171:3a7713b1edbc	553	uint32_t STATUS:5; /!< \brief bit: 0.. 5 Fault Status bits /
AnnaBridge	171:3a7713b1edbc	554	RESERVED(0:3, uint32_t)
AnnaBridge	171:3a7713b1edbc	555	uint32_t LPAE:1; /!< \brief bit: 9 Large Physical Address Extension /
AnnaBridge	171:3a7713b1edbc	556	RESERVED(1:1, uint32_t)
AnnaBridge	171:3a7713b1edbc	557	uint32_t WnR:1; /!< \brief bit: 11 Write not Read bit /
AnnaBridge	171:3a7713b1edbc	558	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
AnnaBridge	171:3a7713b1edbc	559	uint32_t CM:1; /!< \brief bit: 13 Cache maintenance fault /
AnnaBridge	171:3a7713b1edbc	560	RESERVED(2:18, uint32_t)
AnnaBridge	171:3a7713b1edbc	561	} l; /!< \brief Structure used for bit access in long format /
AnnaBridge	171:3a7713b1edbc	562	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	171:3a7713b1edbc	563	} DFSR_Type;
AnnaBridge	171:3a7713b1edbc	564
AnnaBridge	171:3a7713b1edbc	565	#define DFSR_CM_Pos 13U /!< \brief DFSR: CM Position /
AnnaBridge	171:3a7713b1edbc	566	#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /!< \brief DFSR: CM Mask /
AnnaBridge	171:3a7713b1edbc	567
AnnaBridge	171:3a7713b1edbc	568	#define DFSR_Ext_Pos 12U /!< \brief DFSR: Ext Position /
AnnaBridge	171:3a7713b1edbc	569	#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /!< \brief DFSR: Ext Mask /
AnnaBridge	171:3a7713b1edbc	570
AnnaBridge	171:3a7713b1edbc	571	#define DFSR_WnR_Pos 11U /!< \brief DFSR: WnR Position /
AnnaBridge	171:3a7713b1edbc	572	#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /!< \brief DFSR: WnR Mask /
AnnaBridge	171:3a7713b1edbc	573
AnnaBridge	171:3a7713b1edbc	574	#define DFSR_FS1_Pos 10U /!< \brief DFSR: FS1 Position /
AnnaBridge	171:3a7713b1edbc	575	#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /!< \brief DFSR: FS1 Mask /
AnnaBridge	171:3a7713b1edbc	576
AnnaBridge	171:3a7713b1edbc	577	#define DFSR_LPAE_Pos 9U /!< \brief DFSR: LPAE Position /
AnnaBridge	171:3a7713b1edbc	578	#define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /!< \brief DFSR: LPAE Mask /
AnnaBridge	171:3a7713b1edbc	579
AnnaBridge	171:3a7713b1edbc	580	#define DFSR_Domain_Pos 4U /!< \brief DFSR: Domain Position /
AnnaBridge	171:3a7713b1edbc	581	#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /!< \brief DFSR: Domain Mask /
AnnaBridge	171:3a7713b1edbc	582
AnnaBridge	171:3a7713b1edbc	583	#define DFSR_FS0_Pos 0U /!< \brief DFSR: FS0 Position /
AnnaBridge	171:3a7713b1edbc	584	#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /!< \brief DFSR: FS0 Mask /
AnnaBridge	171:3a7713b1edbc	585
AnnaBridge	171:3a7713b1edbc	586	#define DFSR_STATUS_Pos 0U /!< \brief DFSR: STATUS Position /
AnnaBridge	171:3a7713b1edbc	587	#define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /!< \brief DFSR: STATUS Mask /
AnnaBridge	171:3a7713b1edbc	588
AnnaBridge	171:3a7713b1edbc	589	/* CP15 Register IFSR */
AnnaBridge	171:3a7713b1edbc	590	typedef union
AnnaBridge	171:3a7713b1edbc	591	{
AnnaBridge	171:3a7713b1edbc	592	struct
AnnaBridge	171:3a7713b1edbc	593	{
AnnaBridge	171:3a7713b1edbc	594	uint32_t FS0:4; /!< \brief bit: 0.. 3 Fault Status bits bit 0-3 /
AnnaBridge	171:3a7713b1edbc	595	RESERVED(0:5, uint32_t)
AnnaBridge	171:3a7713b1edbc	596	uint32_t LPAE:1; /!< \brief bit: 9 Large Physical Address Extension /
AnnaBridge	171:3a7713b1edbc	597	uint32_t FS1:1; /!< \brief bit: 10 Fault Status bits bit 4 /
AnnaBridge	171:3a7713b1edbc	598	RESERVED(1:1, uint32_t)
AnnaBridge	171:3a7713b1edbc	599	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
AnnaBridge	171:3a7713b1edbc	600	RESERVED(2:19, uint32_t)
AnnaBridge	171:3a7713b1edbc	601	} s; /!< \brief Structure used for bit access in short format /
AnnaBridge	171:3a7713b1edbc	602	struct
AnnaBridge	171:3a7713b1edbc	603	{
AnnaBridge	171:3a7713b1edbc	604	uint32_t STATUS:6; /!< \brief bit: 0.. 5 Fault Status bits /
AnnaBridge	171:3a7713b1edbc	605	RESERVED(0:3, uint32_t)
AnnaBridge	171:3a7713b1edbc	606	uint32_t LPAE:1; /!< \brief bit: 9 Large Physical Address Extension /
AnnaBridge	171:3a7713b1edbc	607	RESERVED(1:2, uint32_t)
AnnaBridge	171:3a7713b1edbc	608	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
AnnaBridge	171:3a7713b1edbc	609	RESERVED(2:19, uint32_t)
AnnaBridge	171:3a7713b1edbc	610	} l; /!< \brief Structure used for bit access in long format /
AnnaBridge	171:3a7713b1edbc	611	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	171:3a7713b1edbc	612	} IFSR_Type;
AnnaBridge	171:3a7713b1edbc	613
AnnaBridge	171:3a7713b1edbc	614	#define IFSR_ExT_Pos 12U /!< \brief IFSR: ExT Position /
AnnaBridge	171:3a7713b1edbc	615	#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /!< \brief IFSR: ExT Mask /
AnnaBridge	171:3a7713b1edbc	616
AnnaBridge	171:3a7713b1edbc	617	#define IFSR_FS1_Pos 10U /!< \brief IFSR: FS1 Position /
AnnaBridge	171:3a7713b1edbc	618	#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /!< \brief IFSR: FS1 Mask /
AnnaBridge	171:3a7713b1edbc	619
AnnaBridge	171:3a7713b1edbc	620	#define IFSR_LPAE_Pos 9U /!< \brief IFSR: LPAE Position /
AnnaBridge	171:3a7713b1edbc	621	#define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /!< \brief IFSR: LPAE Mask /
AnnaBridge	171:3a7713b1edbc	622
AnnaBridge	171:3a7713b1edbc	623	#define IFSR_FS0_Pos 0U /!< \brief IFSR: FS0 Position /
AnnaBridge	171:3a7713b1edbc	624	#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /!< \brief IFSR: FS0 Mask /
AnnaBridge	171:3a7713b1edbc	625
AnnaBridge	171:3a7713b1edbc	626	#define IFSR_STATUS_Pos 0U /!< \brief IFSR: STATUS Position /
AnnaBridge	171:3a7713b1edbc	627	#define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /!< \brief IFSR: STATUS Mask /
AnnaBridge	171:3a7713b1edbc	628
AnnaBridge	171:3a7713b1edbc	629	/* CP15 Register ISR */
AnnaBridge	171:3a7713b1edbc	630	typedef union
AnnaBridge	171:3a7713b1edbc	631	{
AnnaBridge	171:3a7713b1edbc	632	struct
AnnaBridge	171:3a7713b1edbc	633	{
AnnaBridge	171:3a7713b1edbc	634	RESERVED(0:6, uint32_t)
AnnaBridge	171:3a7713b1edbc	635	uint32_t F:1; /!< \brief bit: 6 FIQ pending bit /
AnnaBridge	171:3a7713b1edbc	636	uint32_t I:1; /!< \brief bit: 7 IRQ pending bit /
AnnaBridge	171:3a7713b1edbc	637	uint32_t A:1; /!< \brief bit: 8 External abort pending bit /
AnnaBridge	171:3a7713b1edbc	638	RESERVED(1:23, uint32_t)
AnnaBridge	171:3a7713b1edbc	639	} b; /!< \brief Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	640	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	171:3a7713b1edbc	641	} ISR_Type;
AnnaBridge	171:3a7713b1edbc	642
AnnaBridge	171:3a7713b1edbc	643	#define ISR_A_Pos 13U /!< \brief ISR: A Position /
AnnaBridge	171:3a7713b1edbc	644	#define ISR_A_Msk (1UL << ISR_A_Pos) /!< \brief ISR: A Mask /
AnnaBridge	171:3a7713b1edbc	645
AnnaBridge	171:3a7713b1edbc	646	#define ISR_I_Pos 12U /!< \brief ISR: I Position /
AnnaBridge	171:3a7713b1edbc	647	#define ISR_I_Msk (1UL << ISR_I_Pos) /!< \brief ISR: I Mask /
AnnaBridge	171:3a7713b1edbc	648
AnnaBridge	171:3a7713b1edbc	649	#define ISR_F_Pos 11U /!< \brief ISR: F Position /
AnnaBridge	171:3a7713b1edbc	650	#define ISR_F_Msk (1UL << ISR_F_Pos) /!< \brief ISR: F Mask /
AnnaBridge	171:3a7713b1edbc	651
AnnaBridge	171:3a7713b1edbc	652	/* DACR Register */
AnnaBridge	171:3a7713b1edbc	653	#define DACR_D_Pos_(n) (2Un) /!< \brief DACR: Dn Position */
AnnaBridge	171:3a7713b1edbc	654	#define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /!< \brief DACR: Dn Mask /
AnnaBridge	171:3a7713b1edbc	655	#define DACR_Dn_NOACCESS 0U /!< \brief DACR Dn field: No access /
AnnaBridge	171:3a7713b1edbc	656	#define DACR_Dn_CLIENT 1U /!< \brief DACR Dn field: Client /
AnnaBridge	171:3a7713b1edbc	657	#define DACR_Dn_MANAGER 3U /!< \brief DACR Dn field: Manager /
AnnaBridge	171:3a7713b1edbc	658
AnnaBridge	171:3a7713b1edbc	659	/**
AnnaBridge	171:3a7713b1edbc	660	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	171:3a7713b1edbc	661	\param [in] field Name of the register bit field.
AnnaBridge	171:3a7713b1edbc	662	\param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	171:3a7713b1edbc	663	\return Masked and shifted value.
AnnaBridge	171:3a7713b1edbc	664	*/
AnnaBridge	171:3a7713b1edbc	665	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	171:3a7713b1edbc	666
AnnaBridge	171:3a7713b1edbc	667	/**
AnnaBridge	171:3a7713b1edbc	668	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	171:3a7713b1edbc	669	\param [in] field Name of the register bit field.
AnnaBridge	171:3a7713b1edbc	670	\param [in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	171:3a7713b1edbc	671	\return Masked and shifted bit field value.
AnnaBridge	171:3a7713b1edbc	672	*/
AnnaBridge	171:3a7713b1edbc	673	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	171:3a7713b1edbc	674
AnnaBridge	171:3a7713b1edbc	675
AnnaBridge	171:3a7713b1edbc	676	/**
AnnaBridge	171:3a7713b1edbc	677	\brief Union type to access the L2C_310 Cache Controller.
AnnaBridge	171:3a7713b1edbc	678	*/
AnnaBridge	171:3a7713b1edbc	679	#if (__L2C_PRESENT == 1U) \|\| defined(DOXYGEN)
AnnaBridge	171:3a7713b1edbc	680	typedef struct
AnnaBridge	171:3a7713b1edbc	681	{
AnnaBridge	171:3a7713b1edbc	682	__IM uint32_t CACHE_ID; /!< \brief Offset: 0x0000 (R/ ) Cache ID Register /
AnnaBridge	171:3a7713b1edbc	683	__IM uint32_t CACHE_TYPE; /!< \brief Offset: 0x0004 (R/ ) Cache Type Register /
AnnaBridge	171:3a7713b1edbc	684	RESERVED(0[0x3e], uint32_t)
AnnaBridge	171:3a7713b1edbc	685	__IOM uint32_t CONTROL; /!< \brief Offset: 0x0100 (R/W) Control Register /
AnnaBridge	171:3a7713b1edbc	686	__IOM uint32_t AUX_CNT; /!< \brief Offset: 0x0104 (R/W) Auxiliary Control /
AnnaBridge	171:3a7713b1edbc	687	RESERVED(1[0x3e], uint32_t)
AnnaBridge	171:3a7713b1edbc	688	__IOM uint32_t EVENT_CONTROL; /!< \brief Offset: 0x0200 (R/W) Event Counter Control /
AnnaBridge	171:3a7713b1edbc	689	__IOM uint32_t EVENT_COUNTER1_CONF; /!< \brief Offset: 0x0204 (R/W) Event Counter 1 Configuration /
AnnaBridge	171:3a7713b1edbc	690	__IOM uint32_t EVENT_COUNTER0_CONF; /!< \brief Offset: 0x0208 (R/W) Event Counter 1 Configuration /
AnnaBridge	171:3a7713b1edbc	691	RESERVED(2[0x2], uint32_t)
AnnaBridge	171:3a7713b1edbc	692	__IOM uint32_t INTERRUPT_MASK; /!< \brief Offset: 0x0214 (R/W) Interrupt Mask /
AnnaBridge	171:3a7713b1edbc	693	__IM uint32_t MASKED_INT_STATUS; /!< \brief Offset: 0x0218 (R/ ) Masked Interrupt Status /
AnnaBridge	171:3a7713b1edbc	694	__IM uint32_t RAW_INT_STATUS; /!< \brief Offset: 0x021c (R/ ) Raw Interrupt Status /
AnnaBridge	171:3a7713b1edbc	695	__OM uint32_t INTERRUPT_CLEAR; /!< \brief Offset: 0x0220 ( /W) Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	696	RESERVED(3[0x143], uint32_t)
AnnaBridge	171:3a7713b1edbc	697	__IOM uint32_t CACHE_SYNC; /!< \brief Offset: 0x0730 (R/W) Cache Sync /
AnnaBridge	171:3a7713b1edbc	698	RESERVED(4[0xf], uint32_t)
AnnaBridge	171:3a7713b1edbc	699	__IOM uint32_t INV_LINE_PA; /!< \brief Offset: 0x0770 (R/W) Invalidate Line By PA /
AnnaBridge	171:3a7713b1edbc	700	RESERVED(6[2], uint32_t)
AnnaBridge	171:3a7713b1edbc	701	__IOM uint32_t INV_WAY; /!< \brief Offset: 0x077c (R/W) Invalidate by Way /
AnnaBridge	171:3a7713b1edbc	702	RESERVED(5[0xc], uint32_t)
AnnaBridge	171:3a7713b1edbc	703	__IOM uint32_t CLEAN_LINE_PA; /!< \brief Offset: 0x07b0 (R/W) Clean Line by PA /
AnnaBridge	171:3a7713b1edbc	704	RESERVED(7[1], uint32_t)
AnnaBridge	171:3a7713b1edbc	705	__IOM uint32_t CLEAN_LINE_INDEX_WAY; /!< \brief Offset: 0x07b8 (R/W) Clean Line by Index/Way /
AnnaBridge	171:3a7713b1edbc	706	__IOM uint32_t CLEAN_WAY; /!< \brief Offset: 0x07bc (R/W) Clean by Way /
AnnaBridge	171:3a7713b1edbc	707	RESERVED(8[0xc], uint32_t)
AnnaBridge	171:3a7713b1edbc	708	__IOM uint32_t CLEAN_INV_LINE_PA; /!< \brief Offset: 0x07f0 (R/W) Clean and Invalidate Line by PA /
AnnaBridge	171:3a7713b1edbc	709	RESERVED(9[1], uint32_t)
AnnaBridge	171:3a7713b1edbc	710	__IOM uint32_t CLEAN_INV_LINE_INDEX_WAY; /!< \brief Offset: 0x07f8 (R/W) Clean and Invalidate Line by Index/Way /
AnnaBridge	171:3a7713b1edbc	711	__IOM uint32_t CLEAN_INV_WAY; /!< \brief Offset: 0x07fc (R/W) Clean and Invalidate by Way /
AnnaBridge	171:3a7713b1edbc	712	RESERVED(10[0x40], uint32_t)
AnnaBridge	171:3a7713b1edbc	713	__IOM uint32_t DATA_LOCK_0_WAY; /!< \brief Offset: 0x0900 (R/W) Data Lockdown 0 by Way /
AnnaBridge	171:3a7713b1edbc	714	__IOM uint32_t INST_LOCK_0_WAY; /!< \brief Offset: 0x0904 (R/W) Instruction Lockdown 0 by Way /
AnnaBridge	171:3a7713b1edbc	715	__IOM uint32_t DATA_LOCK_1_WAY; /!< \brief Offset: 0x0908 (R/W) Data Lockdown 1 by Way /
AnnaBridge	171:3a7713b1edbc	716	__IOM uint32_t INST_LOCK_1_WAY; /!< \brief Offset: 0x090c (R/W) Instruction Lockdown 1 by Way /
AnnaBridge	171:3a7713b1edbc	717	__IOM uint32_t DATA_LOCK_2_WAY; /!< \brief Offset: 0x0910 (R/W) Data Lockdown 2 by Way /
AnnaBridge	171:3a7713b1edbc	718	__IOM uint32_t INST_LOCK_2_WAY; /!< \brief Offset: 0x0914 (R/W) Instruction Lockdown 2 by Way /
AnnaBridge	171:3a7713b1edbc	719	__IOM uint32_t DATA_LOCK_3_WAY; /!< \brief Offset: 0x0918 (R/W) Data Lockdown 3 by Way /
AnnaBridge	171:3a7713b1edbc	720	__IOM uint32_t INST_LOCK_3_WAY; /!< \brief Offset: 0x091c (R/W) Instruction Lockdown 3 by Way /
AnnaBridge	171:3a7713b1edbc	721	__IOM uint32_t DATA_LOCK_4_WAY; /!< \brief Offset: 0x0920 (R/W) Data Lockdown 4 by Way /
AnnaBridge	171:3a7713b1edbc	722	__IOM uint32_t INST_LOCK_4_WAY; /!< \brief Offset: 0x0924 (R/W) Instruction Lockdown 4 by Way /
AnnaBridge	171:3a7713b1edbc	723	__IOM uint32_t DATA_LOCK_5_WAY; /!< \brief Offset: 0x0928 (R/W) Data Lockdown 5 by Way /
AnnaBridge	171:3a7713b1edbc	724	__IOM uint32_t INST_LOCK_5_WAY; /!< \brief Offset: 0x092c (R/W) Instruction Lockdown 5 by Way /
AnnaBridge	171:3a7713b1edbc	725	__IOM uint32_t DATA_LOCK_6_WAY; /!< \brief Offset: 0x0930 (R/W) Data Lockdown 5 by Way /
AnnaBridge	171:3a7713b1edbc	726	__IOM uint32_t INST_LOCK_6_WAY; /!< \brief Offset: 0x0934 (R/W) Instruction Lockdown 5 by Way /
AnnaBridge	171:3a7713b1edbc	727	__IOM uint32_t DATA_LOCK_7_WAY; /!< \brief Offset: 0x0938 (R/W) Data Lockdown 6 by Way /
AnnaBridge	171:3a7713b1edbc	728	__IOM uint32_t INST_LOCK_7_WAY; /!< \brief Offset: 0x093c (R/W) Instruction Lockdown 6 by Way /
AnnaBridge	171:3a7713b1edbc	729	RESERVED(11[0x4], uint32_t)
AnnaBridge	171:3a7713b1edbc	730	__IOM uint32_t LOCK_LINE_EN; /!< \brief Offset: 0x0950 (R/W) Lockdown by Line Enable /
AnnaBridge	171:3a7713b1edbc	731	__IOM uint32_t UNLOCK_ALL_BY_WAY; /!< \brief Offset: 0x0954 (R/W) Unlock All Lines by Way /
AnnaBridge	171:3a7713b1edbc	732	RESERVED(12[0xaa], uint32_t)
AnnaBridge	171:3a7713b1edbc	733	__IOM uint32_t ADDRESS_FILTER_START; /!< \brief Offset: 0x0c00 (R/W) Address Filtering Start /
AnnaBridge	171:3a7713b1edbc	734	__IOM uint32_t ADDRESS_FILTER_END; /!< \brief Offset: 0x0c04 (R/W) Address Filtering End /
AnnaBridge	171:3a7713b1edbc	735	RESERVED(13[0xce], uint32_t)
AnnaBridge	171:3a7713b1edbc	736	__IOM uint32_t DEBUG_CONTROL; /!< \brief Offset: 0x0f40 (R/W) Debug Control Register /
AnnaBridge	171:3a7713b1edbc	737	} L2C_310_TypeDef;
AnnaBridge	171:3a7713b1edbc	738
AnnaBridge	171:3a7713b1edbc	739	#define L2C_310 ((L2C_310_TypeDef )L2C_310_BASE) /!< \brief L2C_310 register set access pointer */
AnnaBridge	171:3a7713b1edbc	740	#endif
AnnaBridge	171:3a7713b1edbc	741
AnnaBridge	171:3a7713b1edbc	742	#if (__GIC_PRESENT == 1U) \|\| defined(DOXYGEN)
AnnaBridge	171:3a7713b1edbc	743
AnnaBridge	171:3a7713b1edbc	744	/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
AnnaBridge	171:3a7713b1edbc	745	*/
AnnaBridge	171:3a7713b1edbc	746	typedef struct
AnnaBridge	171:3a7713b1edbc	747	{
AnnaBridge	171:3a7713b1edbc	748	__IOM uint32_t CTLR; /!< \brief Offset: 0x000 (R/W) Distributor Control Register /
AnnaBridge	171:3a7713b1edbc	749	__IM uint32_t TYPER; /!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	171:3a7713b1edbc	750	__IM uint32_t IIDR; /!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register /
AnnaBridge	171:3a7713b1edbc	751	RESERVED(0, uint32_t)
AnnaBridge	171:3a7713b1edbc	752	__IOM uint32_t STATUSR; /!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional /
AnnaBridge	171:3a7713b1edbc	753	RESERVED(1[11], uint32_t)
AnnaBridge	171:3a7713b1edbc	754	__OM uint32_t SETSPI_NSR; /!< \brief Offset: 0x040 ( /W) Set SPI Register /
AnnaBridge	171:3a7713b1edbc	755	RESERVED(2, uint32_t)
AnnaBridge	171:3a7713b1edbc	756	__OM uint32_t CLRSPI_NSR; /!< \brief Offset: 0x048 ( /W) Clear SPI Register /
AnnaBridge	171:3a7713b1edbc	757	RESERVED(3, uint32_t)
AnnaBridge	171:3a7713b1edbc	758	__OM uint32_t SETSPI_SR; /!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register /
AnnaBridge	171:3a7713b1edbc	759	RESERVED(4, uint32_t)
AnnaBridge	171:3a7713b1edbc	760	__OM uint32_t CLRSPI_SR; /!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register /
AnnaBridge	171:3a7713b1edbc	761	RESERVED(5[9], uint32_t)
AnnaBridge	171:3a7713b1edbc	762	__IOM uint32_t IGROUPR[32]; /!< \brief Offset: 0x080 (R/W) Interrupt Group Registers /
AnnaBridge	171:3a7713b1edbc	763	__IOM uint32_t ISENABLER[32]; /!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers /
AnnaBridge	171:3a7713b1edbc	764	__IOM uint32_t ICENABLER[32]; /!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers /
AnnaBridge	171:3a7713b1edbc	765	__IOM uint32_t ISPENDR[32]; /!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers /
AnnaBridge	171:3a7713b1edbc	766	__IOM uint32_t ICPENDR[32]; /!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers /
AnnaBridge	171:3a7713b1edbc	767	__IOM uint32_t ISACTIVER[32]; /!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers /
AnnaBridge	171:3a7713b1edbc	768	__IOM uint32_t ICACTIVER[32]; /!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers /
AnnaBridge	171:3a7713b1edbc	769	__IOM uint32_t IPRIORITYR[255]; /!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers /
AnnaBridge	171:3a7713b1edbc	770	RESERVED(6, uint32_t)
AnnaBridge	171:3a7713b1edbc	771	__IOM uint32_t ITARGETSR[255]; /!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers /
AnnaBridge	171:3a7713b1edbc	772	RESERVED(7, uint32_t)
AnnaBridge	171:3a7713b1edbc	773	__IOM uint32_t ICFGR[64]; /!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers /
AnnaBridge	171:3a7713b1edbc	774	__IOM uint32_t IGRPMODR[32]; /!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers /
AnnaBridge	171:3a7713b1edbc	775	RESERVED(8[32], uint32_t)
AnnaBridge	171:3a7713b1edbc	776	__IOM uint32_t NSACR[64]; /!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers /
AnnaBridge	171:3a7713b1edbc	777	__OM uint32_t SGIR; /!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register /
AnnaBridge	171:3a7713b1edbc	778	RESERVED(9[3], uint32_t)
AnnaBridge	171:3a7713b1edbc	779	__IOM uint32_t CPENDSGIR[4]; /!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers /
AnnaBridge	171:3a7713b1edbc	780	__IOM uint32_t SPENDSGIR[4]; /!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers /
AnnaBridge	171:3a7713b1edbc	781	RESERVED(10[5236], uint32_t)
AnnaBridge	171:3a7713b1edbc	782	__IOM uint64_t IROUTER[988]; /!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers /
AnnaBridge	171:3a7713b1edbc	783	} GICDistributor_Type;
AnnaBridge	171:3a7713b1edbc	784
AnnaBridge	171:3a7713b1edbc	785	#define GICDistributor ((GICDistributor_Type ) GIC_DISTRIBUTOR_BASE ) /!< \brief GIC Distributor register set access pointer */
AnnaBridge	171:3a7713b1edbc	786
AnnaBridge	171:3a7713b1edbc	787	/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
AnnaBridge	171:3a7713b1edbc	788	*/
AnnaBridge	171:3a7713b1edbc	789	typedef struct
AnnaBridge	171:3a7713b1edbc	790	{
AnnaBridge	171:3a7713b1edbc	791	__IOM uint32_t CTLR; /!< \brief Offset: 0x000 (R/W) CPU Interface Control Register /
AnnaBridge	171:3a7713b1edbc	792	__IOM uint32_t PMR; /!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register /
AnnaBridge	171:3a7713b1edbc	793	__IOM uint32_t BPR; /!< \brief Offset: 0x008 (R/W) Binary Point Register /
AnnaBridge	171:3a7713b1edbc	794	__IM uint32_t IAR; /!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register /
AnnaBridge	171:3a7713b1edbc	795	__OM uint32_t EOIR; /!< \brief Offset: 0x010 ( /W) End Of Interrupt Register /
AnnaBridge	171:3a7713b1edbc	796	__IM uint32_t RPR; /!< \brief Offset: 0x014 (R/ ) Running Priority Register /
AnnaBridge	171:3a7713b1edbc	797	__IM uint32_t HPPIR; /!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register /
AnnaBridge	171:3a7713b1edbc	798	__IOM uint32_t ABPR; /!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register /
AnnaBridge	171:3a7713b1edbc	799	__IM uint32_t AIAR; /!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register /
AnnaBridge	171:3a7713b1edbc	800	__OM uint32_t AEOIR; /!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register /
AnnaBridge	171:3a7713b1edbc	801	__IM uint32_t AHPPIR; /!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register /
AnnaBridge	171:3a7713b1edbc	802	__IOM uint32_t STATUSR; /!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional /
AnnaBridge	171:3a7713b1edbc	803	RESERVED(1[40], uint32_t)
AnnaBridge	171:3a7713b1edbc	804	__IOM uint32_t APR[4]; /!< \brief Offset: 0x0D0 (R/W) Active Priority Register /
AnnaBridge	171:3a7713b1edbc	805	__IOM uint32_t NSAPR[4]; /!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register /
AnnaBridge	171:3a7713b1edbc	806	RESERVED(2[3], uint32_t)
AnnaBridge	171:3a7713b1edbc	807	__IM uint32_t IIDR; /!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register /
AnnaBridge	171:3a7713b1edbc	808	RESERVED(3[960], uint32_t)
AnnaBridge	171:3a7713b1edbc	809	__OM uint32_t DIR; /!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register /
AnnaBridge	171:3a7713b1edbc	810	} GICInterface_Type;
AnnaBridge	171:3a7713b1edbc	811
AnnaBridge	171:3a7713b1edbc	812	#define GICInterface ((GICInterface_Type ) GIC_INTERFACE_BASE ) /!< \brief GIC Interface register set access pointer */
AnnaBridge	171:3a7713b1edbc	813	#endif
AnnaBridge	171:3a7713b1edbc	814
AnnaBridge	171:3a7713b1edbc	815	#if (__TIM_PRESENT == 1U) \|\| defined(DOXYGEN)
AnnaBridge	171:3a7713b1edbc	816	#if ((__CORTEX_A == 5U) \|\| (__CORTEX_A == 9U)) \|\| defined(DOXYGEN)
AnnaBridge	171:3a7713b1edbc	817	/** \brief Structure type to access the Private Timer
AnnaBridge	171:3a7713b1edbc	818	*/
AnnaBridge	171:3a7713b1edbc	819	typedef struct
AnnaBridge	171:3a7713b1edbc	820	{
AnnaBridge	171:3a7713b1edbc	821	__IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register
AnnaBridge	171:3a7713b1edbc	822	__IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register
AnnaBridge	171:3a7713b1edbc	823	__IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register
AnnaBridge	171:3a7713b1edbc	824	__IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register
AnnaBridge	171:3a7713b1edbc	825	RESERVED(0[4], uint32_t)
AnnaBridge	171:3a7713b1edbc	826	__IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register
AnnaBridge	171:3a7713b1edbc	827	__IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register
AnnaBridge	171:3a7713b1edbc	828	__IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register
AnnaBridge	171:3a7713b1edbc	829	__IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register
AnnaBridge	171:3a7713b1edbc	830	__IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register
AnnaBridge	171:3a7713b1edbc	831	__OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register
AnnaBridge	171:3a7713b1edbc	832	} Timer_Type;
AnnaBridge	171:3a7713b1edbc	833	#define PTIM ((Timer_Type ) TIMER_BASE ) /!< \brief Timer register struct */
AnnaBridge	171:3a7713b1edbc	834	#endif
AnnaBridge	171:3a7713b1edbc	835	#endif
AnnaBridge	171:3a7713b1edbc	836
AnnaBridge	171:3a7713b1edbc	837	/*******************************************************************************
AnnaBridge	171:3a7713b1edbc	838	* Hardware Abstraction Layer
AnnaBridge	171:3a7713b1edbc	839	Core Function Interface contains:
AnnaBridge	171:3a7713b1edbc	840	- L1 Cache Functions
AnnaBridge	171:3a7713b1edbc	841	- L2C-310 Cache Controller Functions
AnnaBridge	171:3a7713b1edbc	842	- PL1 Timer Functions
AnnaBridge	171:3a7713b1edbc	843	- GIC Functions
AnnaBridge	171:3a7713b1edbc	844	- MMU Functions
AnnaBridge	171:3a7713b1edbc	845	******************************************************************************/
AnnaBridge	171:3a7713b1edbc	846
AnnaBridge	171:3a7713b1edbc	847	/* ########################## L1 Cache functions ################################# */
AnnaBridge	171:3a7713b1edbc	848
AnnaBridge	171:3a7713b1edbc	849	/** \brief Enable Caches by setting I and C bits in SCTLR register.
AnnaBridge	171:3a7713b1edbc	850	*/
AnnaBridge	171:3a7713b1edbc	851	__STATIC_FORCEINLINE void L1C_EnableCaches(void) {
AnnaBridge	171:3a7713b1edbc	852	__set_SCTLR( __get_SCTLR() \| SCTLR_I_Msk \| SCTLR_C_Msk);
AnnaBridge	171:3a7713b1edbc	853	__ISB();
AnnaBridge	171:3a7713b1edbc	854	}
AnnaBridge	171:3a7713b1edbc	855
AnnaBridge	171:3a7713b1edbc	856	/** \brief Disable Caches by clearing I and C bits in SCTLR register.
AnnaBridge	171:3a7713b1edbc	857	*/
AnnaBridge	171:3a7713b1edbc	858	__STATIC_FORCEINLINE void L1C_DisableCaches(void) {
AnnaBridge	171:3a7713b1edbc	859	__set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));
AnnaBridge	171:3a7713b1edbc	860	__ISB();
AnnaBridge	171:3a7713b1edbc	861	}
AnnaBridge	171:3a7713b1edbc	862
AnnaBridge	171:3a7713b1edbc	863	/** \brief Enable Branch Prediction by setting Z bit in SCTLR register.
AnnaBridge	171:3a7713b1edbc	864	*/
AnnaBridge	171:3a7713b1edbc	865	__STATIC_FORCEINLINE void L1C_EnableBTAC(void) {
AnnaBridge	171:3a7713b1edbc	866	__set_SCTLR( __get_SCTLR() \| SCTLR_Z_Msk);
AnnaBridge	171:3a7713b1edbc	867	__ISB();
AnnaBridge	171:3a7713b1edbc	868	}
AnnaBridge	171:3a7713b1edbc	869
AnnaBridge	171:3a7713b1edbc	870	/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register.
AnnaBridge	171:3a7713b1edbc	871	*/
AnnaBridge	171:3a7713b1edbc	872	__STATIC_FORCEINLINE void L1C_DisableBTAC(void) {
AnnaBridge	171:3a7713b1edbc	873	__set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));
AnnaBridge	171:3a7713b1edbc	874	__ISB();
AnnaBridge	171:3a7713b1edbc	875	}
AnnaBridge	171:3a7713b1edbc	876
AnnaBridge	171:3a7713b1edbc	877	/** \brief Invalidate entire branch predictor array
AnnaBridge	171:3a7713b1edbc	878	*/
AnnaBridge	171:3a7713b1edbc	879	__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
AnnaBridge	171:3a7713b1edbc	880	__set_BPIALL(0);
AnnaBridge	171:3a7713b1edbc	881	__DSB(); //ensure completion of the invalidation
AnnaBridge	171:3a7713b1edbc	882	__ISB(); //ensure instruction fetch path sees new state
AnnaBridge	171:3a7713b1edbc	883	}
AnnaBridge	171:3a7713b1edbc	884
AnnaBridge	171:3a7713b1edbc	885	/** \brief Invalidate the whole instruction cache
AnnaBridge	171:3a7713b1edbc	886	*/
AnnaBridge	171:3a7713b1edbc	887	__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {
AnnaBridge	171:3a7713b1edbc	888	__set_ICIALLU(0);
AnnaBridge	171:3a7713b1edbc	889	__DSB(); //ensure completion of the invalidation
AnnaBridge	171:3a7713b1edbc	890	__ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge	171:3a7713b1edbc	891	}
AnnaBridge	171:3a7713b1edbc	892
AnnaBridge	171:3a7713b1edbc	893	/** \brief Clean data cache line by address.
AnnaBridge	171:3a7713b1edbc	894	* \param [in] va Pointer to data to clear the cache for.
AnnaBridge	171:3a7713b1edbc	895	*/
AnnaBridge	171:3a7713b1edbc	896	__STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {
AnnaBridge	171:3a7713b1edbc	897	__set_DCCMVAC((uint32_t)va);
AnnaBridge	171:3a7713b1edbc	898	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge	171:3a7713b1edbc	899	}
AnnaBridge	171:3a7713b1edbc	900
AnnaBridge	171:3a7713b1edbc	901	/** \brief Invalidate data cache line by address.
AnnaBridge	171:3a7713b1edbc	902	* \param [in] va Pointer to data to invalidate the cache for.
AnnaBridge	171:3a7713b1edbc	903	*/
AnnaBridge	171:3a7713b1edbc	904	__STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {
AnnaBridge	171:3a7713b1edbc	905	__set_DCIMVAC((uint32_t)va);
AnnaBridge	171:3a7713b1edbc	906	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge	171:3a7713b1edbc	907	}
AnnaBridge	171:3a7713b1edbc	908
AnnaBridge	171:3a7713b1edbc	909	/** \brief Clean and Invalidate data cache by address.
AnnaBridge	171:3a7713b1edbc	910	* \param [in] va Pointer to data to invalidate the cache for.
AnnaBridge	171:3a7713b1edbc	911	*/
AnnaBridge	171:3a7713b1edbc	912	__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
AnnaBridge	171:3a7713b1edbc	913	__set_DCCIMVAC((uint32_t)va);
AnnaBridge	171:3a7713b1edbc	914	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge	171:3a7713b1edbc	915	}
AnnaBridge	171:3a7713b1edbc	916
AnnaBridge	171:3a7713b1edbc	917	/** \brief Calculate log2 rounded up
AnnaBridge	171:3a7713b1edbc	918	* - log(0) => 0
AnnaBridge	171:3a7713b1edbc	919	* - log(1) => 0
AnnaBridge	171:3a7713b1edbc	920	* - log(2) => 1
AnnaBridge	171:3a7713b1edbc	921	* - log(3) => 2
AnnaBridge	171:3a7713b1edbc	922	* - log(4) => 2
AnnaBridge	171:3a7713b1edbc	923	* - log(5) => 3
AnnaBridge	171:3a7713b1edbc	924	* : :
AnnaBridge	171:3a7713b1edbc	925	* - log(16) => 4
AnnaBridge	171:3a7713b1edbc	926	* - log(32) => 5
AnnaBridge	171:3a7713b1edbc	927	* : :
AnnaBridge	171:3a7713b1edbc	928	* \param [in] n input value parameter
AnnaBridge	171:3a7713b1edbc	929	* \return log2(n)
AnnaBridge	171:3a7713b1edbc	930	*/
AnnaBridge	171:3a7713b1edbc	931	__STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
AnnaBridge	171:3a7713b1edbc	932	{
AnnaBridge	171:3a7713b1edbc	933	if (n < 2U) {
AnnaBridge	171:3a7713b1edbc	934	return 0U;
AnnaBridge	171:3a7713b1edbc	935	}
AnnaBridge	171:3a7713b1edbc	936	uint8_t log = 0U;
AnnaBridge	171:3a7713b1edbc	937	uint32_t t = n;
AnnaBridge	171:3a7713b1edbc	938	while(t > 1U)
AnnaBridge	171:3a7713b1edbc	939	{
AnnaBridge	171:3a7713b1edbc	940	log++;
AnnaBridge	171:3a7713b1edbc	941	t >>= 1U;
AnnaBridge	171:3a7713b1edbc	942	}
AnnaBridge	171:3a7713b1edbc	943	if (n & 1U) { log++; }
AnnaBridge	171:3a7713b1edbc	944	return log;
AnnaBridge	171:3a7713b1edbc	945	}
AnnaBridge	171:3a7713b1edbc	946
AnnaBridge	171:3a7713b1edbc	947	/** \brief Apply cache maintenance to given cache level.
AnnaBridge	171:3a7713b1edbc	948	* \param [in] level cache level to be maintained
AnnaBridge	171:3a7713b1edbc	949	* \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean
AnnaBridge	171:3a7713b1edbc	950	*/
AnnaBridge	171:3a7713b1edbc	951	__STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
AnnaBridge	171:3a7713b1edbc	952	{
AnnaBridge	171:3a7713b1edbc	953	uint32_t Dummy;
AnnaBridge	171:3a7713b1edbc	954	uint32_t ccsidr;
AnnaBridge	171:3a7713b1edbc	955	uint32_t num_sets;
AnnaBridge	171:3a7713b1edbc	956	uint32_t num_ways;
AnnaBridge	171:3a7713b1edbc	957	uint32_t shift_way;
AnnaBridge	171:3a7713b1edbc	958	uint32_t log2_linesize;
AnnaBridge	171:3a7713b1edbc	959	int32_t log2_num_ways;
AnnaBridge	171:3a7713b1edbc	960
AnnaBridge	171:3a7713b1edbc	961	Dummy = level << 1U;
AnnaBridge	171:3a7713b1edbc	962	/* set csselr, select ccsidr register */
AnnaBridge	171:3a7713b1edbc	963	__set_CSSELR(Dummy);
AnnaBridge	171:3a7713b1edbc	964	/* get current ccsidr register */
AnnaBridge	171:3a7713b1edbc	965	ccsidr = __get_CCSIDR();
AnnaBridge	171:3a7713b1edbc	966	num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
AnnaBridge	171:3a7713b1edbc	967	num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
AnnaBridge	171:3a7713b1edbc	968	log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
AnnaBridge	171:3a7713b1edbc	969	log2_num_ways = __log2_up(num_ways);
AnnaBridge	171:3a7713b1edbc	970	if ((log2_num_ways < 0) \|\| (log2_num_ways > 32)) {
AnnaBridge	171:3a7713b1edbc	971	return; // FATAL ERROR
AnnaBridge	171:3a7713b1edbc	972	}
AnnaBridge	171:3a7713b1edbc	973	shift_way = 32U - (uint32_t)log2_num_ways;
AnnaBridge	171:3a7713b1edbc	974	for(int32_t way = num_ways-1; way >= 0; way--)
AnnaBridge	171:3a7713b1edbc	975	{
AnnaBridge	171:3a7713b1edbc	976	for(int32_t set = num_sets-1; set >= 0; set--)
AnnaBridge	171:3a7713b1edbc	977	{
AnnaBridge	171:3a7713b1edbc	978	Dummy = (level << 1U) \| (((uint32_t)set) << log2_linesize) \| (((uint32_t)way) << shift_way);
AnnaBridge	171:3a7713b1edbc	979	switch (maint)
AnnaBridge	171:3a7713b1edbc	980	{
AnnaBridge	171:3a7713b1edbc	981	case 0U: __set_DCISW(Dummy); break;
AnnaBridge	171:3a7713b1edbc	982	case 1U: __set_DCCSW(Dummy); break;
AnnaBridge	171:3a7713b1edbc	983	default: __set_DCCISW(Dummy); break;
AnnaBridge	171:3a7713b1edbc	984	}
AnnaBridge	171:3a7713b1edbc	985	}
AnnaBridge	171:3a7713b1edbc	986	}
AnnaBridge	171:3a7713b1edbc	987	__DMB();
AnnaBridge	171:3a7713b1edbc	988	}
AnnaBridge	171:3a7713b1edbc	989
AnnaBridge	171:3a7713b1edbc	990	/** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge	171:3a7713b1edbc	991	* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
AnnaBridge	171:3a7713b1edbc	992	* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
AnnaBridge	171:3a7713b1edbc	993	*/
AnnaBridge	171:3a7713b1edbc	994	__STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
AnnaBridge	171:3a7713b1edbc	995	uint32_t clidr;
AnnaBridge	171:3a7713b1edbc	996	uint32_t cache_type;
AnnaBridge	171:3a7713b1edbc	997	clidr = __get_CLIDR();
AnnaBridge	171:3a7713b1edbc	998	for(uint32_t i = 0U; i<7U; i++)
AnnaBridge	171:3a7713b1edbc	999	{
AnnaBridge	171:3a7713b1edbc	1000	cache_type = (clidr >> i*3U) & 0x7UL;
AnnaBridge	171:3a7713b1edbc	1001	if ((cache_type >= 2U) && (cache_type <= 4U))
AnnaBridge	171:3a7713b1edbc	1002	{
AnnaBridge	171:3a7713b1edbc	1003	__L1C_MaintainDCacheSetWay(i, op);
AnnaBridge	171:3a7713b1edbc	1004	}
AnnaBridge	171:3a7713b1edbc	1005	}
AnnaBridge	171:3a7713b1edbc	1006	}
AnnaBridge	171:3a7713b1edbc	1007
AnnaBridge	171:3a7713b1edbc	1008	/** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge	171:3a7713b1edbc	1009	* Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
AnnaBridge	171:3a7713b1edbc	1010	* \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
AnnaBridge	171:3a7713b1edbc	1011	* \deprecated Use generic L1C_CleanInvalidateCache instead.
AnnaBridge	171:3a7713b1edbc	1012	*/
AnnaBridge	171:3a7713b1edbc	1013	CMSIS_DEPRECATED
AnnaBridge	171:3a7713b1edbc	1014	__STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {
AnnaBridge	171:3a7713b1edbc	1015	L1C_CleanInvalidateCache(op);
AnnaBridge	171:3a7713b1edbc	1016	}
AnnaBridge	171:3a7713b1edbc	1017
AnnaBridge	171:3a7713b1edbc	1018	/** \brief Invalidate the whole data cache.
AnnaBridge	171:3a7713b1edbc	1019	*/
AnnaBridge	171:3a7713b1edbc	1020	__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {
AnnaBridge	171:3a7713b1edbc	1021	L1C_CleanInvalidateCache(0);
AnnaBridge	171:3a7713b1edbc	1022	}
AnnaBridge	171:3a7713b1edbc	1023
AnnaBridge	171:3a7713b1edbc	1024	/** \brief Clean the whole data cache.
AnnaBridge	171:3a7713b1edbc	1025	*/
AnnaBridge	171:3a7713b1edbc	1026	__STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {
AnnaBridge	171:3a7713b1edbc	1027	L1C_CleanInvalidateCache(1);
AnnaBridge	171:3a7713b1edbc	1028	}
AnnaBridge	171:3a7713b1edbc	1029
AnnaBridge	171:3a7713b1edbc	1030	/** \brief Clean and invalidate the whole data cache.
AnnaBridge	171:3a7713b1edbc	1031	*/
AnnaBridge	171:3a7713b1edbc	1032	__STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
AnnaBridge	171:3a7713b1edbc	1033	L1C_CleanInvalidateCache(2);
AnnaBridge	171:3a7713b1edbc	1034	}
AnnaBridge	171:3a7713b1edbc	1035
AnnaBridge	171:3a7713b1edbc	1036	/* ########################## L2 Cache functions ################################# */
AnnaBridge	171:3a7713b1edbc	1037	#if (__L2C_PRESENT == 1U) \|\| defined(DOXYGEN)
AnnaBridge	171:3a7713b1edbc	1038	/** \brief Cache Sync operation by writing CACHE_SYNC register.
AnnaBridge	171:3a7713b1edbc	1039	*/
AnnaBridge	171:3a7713b1edbc	1040	__STATIC_INLINE void L2C_Sync(void)
AnnaBridge	171:3a7713b1edbc	1041	{
AnnaBridge	171:3a7713b1edbc	1042	L2C_310->CACHE_SYNC = 0x0;
AnnaBridge	171:3a7713b1edbc	1043	}
AnnaBridge	171:3a7713b1edbc	1044
AnnaBridge	171:3a7713b1edbc	1045	/** \brief Read cache controller cache ID from CACHE_ID register.
AnnaBridge	171:3a7713b1edbc	1046	* \return L2C_310_TypeDef::CACHE_ID
AnnaBridge	171:3a7713b1edbc	1047	*/
AnnaBridge	171:3a7713b1edbc	1048	__STATIC_INLINE int L2C_GetID (void)
AnnaBridge	171:3a7713b1edbc	1049	{
AnnaBridge	171:3a7713b1edbc	1050	return L2C_310->CACHE_ID;
AnnaBridge	171:3a7713b1edbc	1051	}
AnnaBridge	171:3a7713b1edbc	1052
AnnaBridge	171:3a7713b1edbc	1053	/** \brief Read cache controller cache type from CACHE_TYPE register.
AnnaBridge	171:3a7713b1edbc	1054	* \return L2C_310_TypeDef::CACHE_TYPE
AnnaBridge	171:3a7713b1edbc	1055	*/
AnnaBridge	171:3a7713b1edbc	1056	__STATIC_INLINE int L2C_GetType (void)
AnnaBridge	171:3a7713b1edbc	1057	{
AnnaBridge	171:3a7713b1edbc	1058	return L2C_310->CACHE_TYPE;
AnnaBridge	171:3a7713b1edbc	1059	}
AnnaBridge	171:3a7713b1edbc	1060
AnnaBridge	171:3a7713b1edbc	1061	/** \brief Invalidate all cache by way
AnnaBridge	171:3a7713b1edbc	1062	*/
AnnaBridge	171:3a7713b1edbc	1063	__STATIC_INLINE void L2C_InvAllByWay (void)
AnnaBridge	171:3a7713b1edbc	1064	{
AnnaBridge	171:3a7713b1edbc	1065	unsigned int assoc;
AnnaBridge	171:3a7713b1edbc	1066
AnnaBridge	171:3a7713b1edbc	1067	if (L2C_310->AUX_CNT & (1U << 16U)) {
AnnaBridge	171:3a7713b1edbc	1068	assoc = 16U;
AnnaBridge	171:3a7713b1edbc	1069	} else {
AnnaBridge	171:3a7713b1edbc	1070	assoc = 8U;
AnnaBridge	171:3a7713b1edbc	1071	}
AnnaBridge	171:3a7713b1edbc	1072
AnnaBridge	171:3a7713b1edbc	1073	L2C_310->INV_WAY = (1U << assoc) - 1U;
AnnaBridge	171:3a7713b1edbc	1074	while(L2C_310->INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
AnnaBridge	171:3a7713b1edbc	1075
AnnaBridge	171:3a7713b1edbc	1076	L2C_Sync();
AnnaBridge	171:3a7713b1edbc	1077	}
AnnaBridge	171:3a7713b1edbc	1078
AnnaBridge	171:3a7713b1edbc	1079	/** \brief Clean and Invalidate all cache by way
AnnaBridge	171:3a7713b1edbc	1080	*/
AnnaBridge	171:3a7713b1edbc	1081	__STATIC_INLINE void L2C_CleanInvAllByWay (void)
AnnaBridge	171:3a7713b1edbc	1082	{
AnnaBridge	171:3a7713b1edbc	1083	unsigned int assoc;
AnnaBridge	171:3a7713b1edbc	1084
AnnaBridge	171:3a7713b1edbc	1085	if (L2C_310->AUX_CNT & (1U << 16U)) {
AnnaBridge	171:3a7713b1edbc	1086	assoc = 16U;
AnnaBridge	171:3a7713b1edbc	1087	} else {
AnnaBridge	171:3a7713b1edbc	1088	assoc = 8U;
AnnaBridge	171:3a7713b1edbc	1089	}
AnnaBridge	171:3a7713b1edbc	1090
AnnaBridge	171:3a7713b1edbc	1091	L2C_310->CLEAN_INV_WAY = (1U << assoc) - 1U;
AnnaBridge	171:3a7713b1edbc	1092	while(L2C_310->CLEAN_INV_WAY & ((1U << assoc) - 1U)); //poll invalidate
AnnaBridge	171:3a7713b1edbc	1093
AnnaBridge	171:3a7713b1edbc	1094	L2C_Sync();
AnnaBridge	171:3a7713b1edbc	1095	}
AnnaBridge	171:3a7713b1edbc	1096
AnnaBridge	171:3a7713b1edbc	1097	/** \brief Enable Level 2 Cache
AnnaBridge	171:3a7713b1edbc	1098	*/
AnnaBridge	171:3a7713b1edbc	1099	__STATIC_INLINE void L2C_Enable(void)
AnnaBridge	171:3a7713b1edbc	1100	{
AnnaBridge	171:3a7713b1edbc	1101	L2C_310->CONTROL = 0;
AnnaBridge	171:3a7713b1edbc	1102	L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
AnnaBridge	171:3a7713b1edbc	1103	L2C_310->DEBUG_CONTROL = 0;
AnnaBridge	171:3a7713b1edbc	1104	L2C_310->DATA_LOCK_0_WAY = 0;
AnnaBridge	171:3a7713b1edbc	1105	L2C_310->CACHE_SYNC = 0;
AnnaBridge	171:3a7713b1edbc	1106	L2C_310->CONTROL = 0x01;
AnnaBridge	171:3a7713b1edbc	1107	L2C_Sync();
AnnaBridge	171:3a7713b1edbc	1108	}
AnnaBridge	171:3a7713b1edbc	1109
AnnaBridge	171:3a7713b1edbc	1110	/** \brief Disable Level 2 Cache
AnnaBridge	171:3a7713b1edbc	1111	*/
AnnaBridge	171:3a7713b1edbc	1112	__STATIC_INLINE void L2C_Disable(void)
AnnaBridge	171:3a7713b1edbc	1113	{
AnnaBridge	171:3a7713b1edbc	1114	L2C_310->CONTROL = 0x00;
AnnaBridge	171:3a7713b1edbc	1115	L2C_Sync();
AnnaBridge	171:3a7713b1edbc	1116	}
AnnaBridge	171:3a7713b1edbc	1117
AnnaBridge	171:3a7713b1edbc	1118	/** \brief Invalidate cache by physical address
AnnaBridge	171:3a7713b1edbc	1119	* \param [in] pa Pointer to data to invalidate cache for.
AnnaBridge	171:3a7713b1edbc	1120	*/
AnnaBridge	171:3a7713b1edbc	1121	__STATIC_INLINE void L2C_InvPa (void *pa)
AnnaBridge	171:3a7713b1edbc	1122	{
AnnaBridge	171:3a7713b1edbc	1123	L2C_310->INV_LINE_PA = (unsigned int)pa;
AnnaBridge	171:3a7713b1edbc	1124	L2C_Sync();
AnnaBridge	171:3a7713b1edbc	1125	}
AnnaBridge	171:3a7713b1edbc	1126
AnnaBridge	171:3a7713b1edbc	1127	/** \brief Clean cache by physical address
AnnaBridge	171:3a7713b1edbc	1128	* \param [in] pa Pointer to data to invalidate cache for.
AnnaBridge	171:3a7713b1edbc	1129	*/
AnnaBridge	171:3a7713b1edbc	1130	__STATIC_INLINE void L2C_CleanPa (void *pa)
AnnaBridge	171:3a7713b1edbc	1131	{
AnnaBridge	171:3a7713b1edbc	1132	L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
AnnaBridge	171:3a7713b1edbc	1133	L2C_Sync();
AnnaBridge	171:3a7713b1edbc	1134	}
AnnaBridge	171:3a7713b1edbc	1135
AnnaBridge	171:3a7713b1edbc	1136	/** \brief Clean and invalidate cache by physical address
AnnaBridge	171:3a7713b1edbc	1137	* \param [in] pa Pointer to data to invalidate cache for.
AnnaBridge	171:3a7713b1edbc	1138	*/
AnnaBridge	171:3a7713b1edbc	1139	__STATIC_INLINE void L2C_CleanInvPa (void *pa)
AnnaBridge	171:3a7713b1edbc	1140	{
AnnaBridge	171:3a7713b1edbc	1141	L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
AnnaBridge	171:3a7713b1edbc	1142	L2C_Sync();
AnnaBridge	171:3a7713b1edbc	1143	}
AnnaBridge	171:3a7713b1edbc	1144	#endif
AnnaBridge	171:3a7713b1edbc	1145
AnnaBridge	171:3a7713b1edbc	1146	/* ########################## GIC functions ###################################### */
AnnaBridge	171:3a7713b1edbc	1147	#if (__GIC_PRESENT == 1U) \|\| defined(DOXYGEN)
AnnaBridge	171:3a7713b1edbc	1148
AnnaBridge	171:3a7713b1edbc	1149	/** \brief Enable the interrupt distributor using the GIC's CTLR register.
AnnaBridge	171:3a7713b1edbc	1150	*/
AnnaBridge	171:3a7713b1edbc	1151	__STATIC_INLINE void GIC_EnableDistributor(void)
AnnaBridge	171:3a7713b1edbc	1152	{
AnnaBridge	171:3a7713b1edbc	1153	GICDistributor->CTLR \|= 1U;
AnnaBridge	171:3a7713b1edbc	1154	}
AnnaBridge	171:3a7713b1edbc	1155
AnnaBridge	171:3a7713b1edbc	1156	/** \brief Disable the interrupt distributor using the GIC's CTLR register.
AnnaBridge	171:3a7713b1edbc	1157	*/
AnnaBridge	171:3a7713b1edbc	1158	__STATIC_INLINE void GIC_DisableDistributor(void)
AnnaBridge	171:3a7713b1edbc	1159	{
AnnaBridge	171:3a7713b1edbc	1160	GICDistributor->CTLR &=~1U;
AnnaBridge	171:3a7713b1edbc	1161	}
AnnaBridge	171:3a7713b1edbc	1162
AnnaBridge	171:3a7713b1edbc	1163	/** \brief Read the GIC's TYPER register.
AnnaBridge	171:3a7713b1edbc	1164	* \return GICDistributor_Type::TYPER
AnnaBridge	171:3a7713b1edbc	1165	*/
AnnaBridge	171:3a7713b1edbc	1166	__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
AnnaBridge	171:3a7713b1edbc	1167	{
AnnaBridge	171:3a7713b1edbc	1168	return (GICDistributor->TYPER);
AnnaBridge	171:3a7713b1edbc	1169	}
AnnaBridge	171:3a7713b1edbc	1170
AnnaBridge	171:3a7713b1edbc	1171	/** \brief Reads the GIC's IIDR register.
AnnaBridge	171:3a7713b1edbc	1172	* \return GICDistributor_Type::IIDR
AnnaBridge	171:3a7713b1edbc	1173	*/
AnnaBridge	171:3a7713b1edbc	1174	__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
AnnaBridge	171:3a7713b1edbc	1175	{
AnnaBridge	171:3a7713b1edbc	1176	return (GICDistributor->IIDR);
AnnaBridge	171:3a7713b1edbc	1177	}
AnnaBridge	171:3a7713b1edbc	1178
AnnaBridge	171:3a7713b1edbc	1179	/** \brief Sets the GIC's ITARGETSR register for the given interrupt.
AnnaBridge	171:3a7713b1edbc	1180	* \param [in] IRQn Interrupt to be configured.
AnnaBridge	171:3a7713b1edbc	1181	* \param [in] cpu_target CPU interfaces to assign this interrupt to.
AnnaBridge	171:3a7713b1edbc	1182	*/
AnnaBridge	171:3a7713b1edbc	1183	__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
AnnaBridge	171:3a7713b1edbc	1184	{
AnnaBridge	171:3a7713b1edbc	1185	uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
AnnaBridge	171:3a7713b1edbc	1186	GICDistributor->ITARGETSR[IRQn / 4U] = mask \| ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
AnnaBridge	171:3a7713b1edbc	1187	}
AnnaBridge	171:3a7713b1edbc	1188
AnnaBridge	171:3a7713b1edbc	1189	/** \brief Read the GIC's ITARGETSR register.
AnnaBridge	171:3a7713b1edbc	1190	* \param [in] IRQn Interrupt to acquire the configuration for.
AnnaBridge	171:3a7713b1edbc	1191	* \return GICDistributor_Type::ITARGETSR
AnnaBridge	171:3a7713b1edbc	1192	*/
AnnaBridge	171:3a7713b1edbc	1193	__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1194	{
AnnaBridge	171:3a7713b1edbc	1195	return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
AnnaBridge	171:3a7713b1edbc	1196	}
AnnaBridge	171:3a7713b1edbc	1197
AnnaBridge	171:3a7713b1edbc	1198	/** \brief Enable the CPU's interrupt interface.
AnnaBridge	171:3a7713b1edbc	1199	*/
AnnaBridge	171:3a7713b1edbc	1200	__STATIC_INLINE void GIC_EnableInterface(void)
AnnaBridge	171:3a7713b1edbc	1201	{
AnnaBridge	171:3a7713b1edbc	1202	GICInterface->CTLR \|= 1U; //enable interface
AnnaBridge	171:3a7713b1edbc	1203	}
AnnaBridge	171:3a7713b1edbc	1204
AnnaBridge	171:3a7713b1edbc	1205	/** \brief Disable the CPU's interrupt interface.
AnnaBridge	171:3a7713b1edbc	1206	*/
AnnaBridge	171:3a7713b1edbc	1207	__STATIC_INLINE void GIC_DisableInterface(void)
AnnaBridge	171:3a7713b1edbc	1208	{
AnnaBridge	171:3a7713b1edbc	1209	GICInterface->CTLR &=~1U; //disable distributor
AnnaBridge	171:3a7713b1edbc	1210	}
AnnaBridge	171:3a7713b1edbc	1211
AnnaBridge	171:3a7713b1edbc	1212	/** \brief Read the CPU's IAR register.
AnnaBridge	171:3a7713b1edbc	1213	* \return GICInterface_Type::IAR
AnnaBridge	171:3a7713b1edbc	1214	*/
AnnaBridge	171:3a7713b1edbc	1215	__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
AnnaBridge	171:3a7713b1edbc	1216	{
AnnaBridge	171:3a7713b1edbc	1217	return (IRQn_Type)(GICInterface->IAR);
AnnaBridge	171:3a7713b1edbc	1218	}
AnnaBridge	171:3a7713b1edbc	1219
AnnaBridge	171:3a7713b1edbc	1220	/** \brief Writes the given interrupt number to the CPU's EOIR register.
AnnaBridge	171:3a7713b1edbc	1221	* \param [in] IRQn The interrupt to be signaled as finished.
AnnaBridge	171:3a7713b1edbc	1222	*/
AnnaBridge	171:3a7713b1edbc	1223	__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1224	{
AnnaBridge	171:3a7713b1edbc	1225	GICInterface->EOIR = IRQn;
AnnaBridge	171:3a7713b1edbc	1226	}
AnnaBridge	171:3a7713b1edbc	1227
AnnaBridge	171:3a7713b1edbc	1228	/** \brief Enables the given interrupt using GIC's ISENABLER register.
AnnaBridge	171:3a7713b1edbc	1229	* \param [in] IRQn The interrupt to be enabled.
AnnaBridge	171:3a7713b1edbc	1230	*/
AnnaBridge	171:3a7713b1edbc	1231	__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1232	{
AnnaBridge	171:3a7713b1edbc	1233	GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
AnnaBridge	171:3a7713b1edbc	1234	}
AnnaBridge	171:3a7713b1edbc	1235
AnnaBridge	171:3a7713b1edbc	1236	/** \brief Get interrupt enable status using GIC's ISENABLER register.
AnnaBridge	171:3a7713b1edbc	1237	* \param [in] IRQn The interrupt to be queried.
AnnaBridge	171:3a7713b1edbc	1238	* \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
AnnaBridge	171:3a7713b1edbc	1239	*/
AnnaBridge	171:3a7713b1edbc	1240	__STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1241	{
AnnaBridge	171:3a7713b1edbc	1242	return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
AnnaBridge	171:3a7713b1edbc	1243	}
AnnaBridge	171:3a7713b1edbc	1244
AnnaBridge	171:3a7713b1edbc	1245	/** \brief Disables the given interrupt using GIC's ICENABLER register.
AnnaBridge	171:3a7713b1edbc	1246	* \param [in] IRQn The interrupt to be disabled.
AnnaBridge	171:3a7713b1edbc	1247	*/
AnnaBridge	171:3a7713b1edbc	1248	__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1249	{
AnnaBridge	171:3a7713b1edbc	1250	GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
AnnaBridge	171:3a7713b1edbc	1251	}
AnnaBridge	171:3a7713b1edbc	1252
AnnaBridge	171:3a7713b1edbc	1253	/** \brief Get interrupt pending status from GIC's ISPENDR register.
AnnaBridge	171:3a7713b1edbc	1254	* \param [in] IRQn The interrupt to be queried.
AnnaBridge	171:3a7713b1edbc	1255	* \return 0 - interrupt is not pending, 1 - interrupt is pendig.
AnnaBridge	171:3a7713b1edbc	1256	*/
AnnaBridge	171:3a7713b1edbc	1257	__STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1258	{
AnnaBridge	171:3a7713b1edbc	1259	uint32_t pend;
AnnaBridge	171:3a7713b1edbc	1260
AnnaBridge	171:3a7713b1edbc	1261	if (IRQn >= 16U) {
AnnaBridge	171:3a7713b1edbc	1262	pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
AnnaBridge	171:3a7713b1edbc	1263	} else {
AnnaBridge	171:3a7713b1edbc	1264	// INTID 0-15 Software Generated Interrupt
AnnaBridge	171:3a7713b1edbc	1265	pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
AnnaBridge	171:3a7713b1edbc	1266	// No CPU identification offered
AnnaBridge	171:3a7713b1edbc	1267	if (pend != 0U) {
AnnaBridge	171:3a7713b1edbc	1268	pend = 1U;
AnnaBridge	171:3a7713b1edbc	1269	} else {
AnnaBridge	171:3a7713b1edbc	1270	pend = 0U;
AnnaBridge	171:3a7713b1edbc	1271	}
AnnaBridge	171:3a7713b1edbc	1272	}
AnnaBridge	171:3a7713b1edbc	1273
AnnaBridge	171:3a7713b1edbc	1274	return (pend);
AnnaBridge	171:3a7713b1edbc	1275	}
AnnaBridge	171:3a7713b1edbc	1276
AnnaBridge	171:3a7713b1edbc	1277	/** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
AnnaBridge	171:3a7713b1edbc	1278	* \param [in] IRQn The interrupt to be enabled.
AnnaBridge	171:3a7713b1edbc	1279	*/
AnnaBridge	171:3a7713b1edbc	1280	__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1281	{
AnnaBridge	171:3a7713b1edbc	1282	if (IRQn >= 16U) {
AnnaBridge	171:3a7713b1edbc	1283	GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
AnnaBridge	171:3a7713b1edbc	1284	} else {
AnnaBridge	171:3a7713b1edbc	1285	// INTID 0-15 Software Generated Interrupt
AnnaBridge	171:3a7713b1edbc	1286	GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
AnnaBridge	171:3a7713b1edbc	1287	}
AnnaBridge	171:3a7713b1edbc	1288	}
AnnaBridge	171:3a7713b1edbc	1289
AnnaBridge	171:3a7713b1edbc	1290	/** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
AnnaBridge	171:3a7713b1edbc	1291	* \param [in] IRQn The interrupt to be enabled.
AnnaBridge	171:3a7713b1edbc	1292	*/
AnnaBridge	171:3a7713b1edbc	1293	__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1294	{
AnnaBridge	171:3a7713b1edbc	1295	if (IRQn >= 16U) {
AnnaBridge	171:3a7713b1edbc	1296	GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
AnnaBridge	171:3a7713b1edbc	1297	} else {
AnnaBridge	171:3a7713b1edbc	1298	// INTID 0-15 Software Generated Interrupt
AnnaBridge	171:3a7713b1edbc	1299	GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
AnnaBridge	171:3a7713b1edbc	1300	}
AnnaBridge	171:3a7713b1edbc	1301	}
AnnaBridge	171:3a7713b1edbc	1302
AnnaBridge	171:3a7713b1edbc	1303	/** \brief Sets the interrupt configuration using GIC's ICFGR register.
AnnaBridge	171:3a7713b1edbc	1304	* \param [in] IRQn The interrupt to be configured.
AnnaBridge	171:3a7713b1edbc	1305	* \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
AnnaBridge	171:3a7713b1edbc	1306	* Bit 1: 0 - level sensitive, 1 - edge triggered
AnnaBridge	171:3a7713b1edbc	1307	*/
AnnaBridge	171:3a7713b1edbc	1308	__STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
AnnaBridge	171:3a7713b1edbc	1309	{
AnnaBridge	171:3a7713b1edbc	1310	uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];
AnnaBridge	171:3a7713b1edbc	1311	uint32_t shift = (IRQn % 16U) << 1U;
AnnaBridge	171:3a7713b1edbc	1312
AnnaBridge	171:3a7713b1edbc	1313	icfgr &= (~(3U << shift));
AnnaBridge	171:3a7713b1edbc	1314	icfgr \|= ( int_config << shift);
AnnaBridge	171:3a7713b1edbc	1315
AnnaBridge	171:3a7713b1edbc	1316	GICDistributor->ICFGR[IRQn / 16U] = icfgr;
AnnaBridge	171:3a7713b1edbc	1317	}
AnnaBridge	171:3a7713b1edbc	1318
AnnaBridge	171:3a7713b1edbc	1319	/** \brief Get the interrupt configuration from the GIC's ICFGR register.
AnnaBridge	171:3a7713b1edbc	1320	* \param [in] IRQn Interrupt to acquire the configuration for.
AnnaBridge	171:3a7713b1edbc	1321	* \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
AnnaBridge	171:3a7713b1edbc	1322	* Bit 1: 0 - level sensitive, 1 - edge triggered
AnnaBridge	171:3a7713b1edbc	1323	*/
AnnaBridge	171:3a7713b1edbc	1324	__STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1325	{
AnnaBridge	171:3a7713b1edbc	1326	return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
AnnaBridge	171:3a7713b1edbc	1327	}
AnnaBridge	171:3a7713b1edbc	1328
AnnaBridge	171:3a7713b1edbc	1329	/** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
AnnaBridge	171:3a7713b1edbc	1330	* \param [in] IRQn The interrupt to be configured.
AnnaBridge	171:3a7713b1edbc	1331	* \param [in] priority The priority for the interrupt, lower values denote higher priorities.
AnnaBridge	171:3a7713b1edbc	1332	*/
AnnaBridge	171:3a7713b1edbc	1333	__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	171:3a7713b1edbc	1334	{
AnnaBridge	171:3a7713b1edbc	1335	uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
AnnaBridge	171:3a7713b1edbc	1336	GICDistributor->IPRIORITYR[IRQn / 4U] = mask \| ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
AnnaBridge	171:3a7713b1edbc	1337	}
AnnaBridge	171:3a7713b1edbc	1338
AnnaBridge	171:3a7713b1edbc	1339	/** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
AnnaBridge	171:3a7713b1edbc	1340	* \param [in] IRQn The interrupt to be queried.
AnnaBridge	171:3a7713b1edbc	1341	*/
AnnaBridge	171:3a7713b1edbc	1342	__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1343	{
AnnaBridge	171:3a7713b1edbc	1344	return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
AnnaBridge	171:3a7713b1edbc	1345	}
AnnaBridge	171:3a7713b1edbc	1346
AnnaBridge	171:3a7713b1edbc	1347	/** \brief Set the interrupt priority mask using CPU's PMR register.
AnnaBridge	171:3a7713b1edbc	1348	* \param [in] priority Priority mask to be set.
AnnaBridge	171:3a7713b1edbc	1349	*/
AnnaBridge	171:3a7713b1edbc	1350	__STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
AnnaBridge	171:3a7713b1edbc	1351	{
AnnaBridge	171:3a7713b1edbc	1352	GICInterface->PMR = priority & 0xFFUL; //set priority mask
AnnaBridge	171:3a7713b1edbc	1353	}
AnnaBridge	171:3a7713b1edbc	1354
AnnaBridge	171:3a7713b1edbc	1355	/** \brief Read the current interrupt priority mask from CPU's PMR register.
AnnaBridge	171:3a7713b1edbc	1356	* \result GICInterface_Type::PMR
AnnaBridge	171:3a7713b1edbc	1357	*/
AnnaBridge	171:3a7713b1edbc	1358	__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
AnnaBridge	171:3a7713b1edbc	1359	{
AnnaBridge	171:3a7713b1edbc	1360	return GICInterface->PMR;
AnnaBridge	171:3a7713b1edbc	1361	}
AnnaBridge	171:3a7713b1edbc	1362
AnnaBridge	171:3a7713b1edbc	1363	/** \brief Configures the group priority and subpriority split point using CPU's BPR register.
AnnaBridge	171:3a7713b1edbc	1364	* \param [in] binary_point Amount of bits used as subpriority.
AnnaBridge	171:3a7713b1edbc	1365	*/
AnnaBridge	171:3a7713b1edbc	1366	__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
AnnaBridge	171:3a7713b1edbc	1367	{
AnnaBridge	171:3a7713b1edbc	1368	GICInterface->BPR = binary_point & 7U; //set binary point
AnnaBridge	171:3a7713b1edbc	1369	}
AnnaBridge	171:3a7713b1edbc	1370
AnnaBridge	171:3a7713b1edbc	1371	/** \brief Read the current group priority and subpriority split point from CPU's BPR register.
AnnaBridge	171:3a7713b1edbc	1372	* \return GICInterface_Type::BPR
AnnaBridge	171:3a7713b1edbc	1373	*/
AnnaBridge	171:3a7713b1edbc	1374	__STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
AnnaBridge	171:3a7713b1edbc	1375	{
AnnaBridge	171:3a7713b1edbc	1376	return GICInterface->BPR;
AnnaBridge	171:3a7713b1edbc	1377	}
AnnaBridge	171:3a7713b1edbc	1378
AnnaBridge	171:3a7713b1edbc	1379	/** \brief Get the status for a given interrupt.
AnnaBridge	171:3a7713b1edbc	1380	* \param [in] IRQn The interrupt to get status for.
AnnaBridge	171:3a7713b1edbc	1381	* \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
AnnaBridge	171:3a7713b1edbc	1382	*/
AnnaBridge	171:3a7713b1edbc	1383	__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1384	{
AnnaBridge	171:3a7713b1edbc	1385	uint32_t pending, active;
AnnaBridge	171:3a7713b1edbc	1386
AnnaBridge	171:3a7713b1edbc	1387	active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
AnnaBridge	171:3a7713b1edbc	1388	pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
AnnaBridge	171:3a7713b1edbc	1389
AnnaBridge	171:3a7713b1edbc	1390	return ((active<<1U) \| pending);
AnnaBridge	171:3a7713b1edbc	1391	}
AnnaBridge	171:3a7713b1edbc	1392
AnnaBridge	171:3a7713b1edbc	1393	/** \brief Generate a software interrupt using GIC's SGIR register.
AnnaBridge	171:3a7713b1edbc	1394	* \param [in] IRQn Software interrupt to be generated.
AnnaBridge	171:3a7713b1edbc	1395	* \param [in] target_list List of CPUs the software interrupt should be forwarded to.
AnnaBridge	171:3a7713b1edbc	1396	* \param [in] filter_list Filter to be applied to determine interrupt receivers.
AnnaBridge	171:3a7713b1edbc	1397	*/
AnnaBridge	171:3a7713b1edbc	1398	__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
AnnaBridge	171:3a7713b1edbc	1399	{
AnnaBridge	171:3a7713b1edbc	1400	GICDistributor->SGIR = ((filter_list & 3U) << 24U) \| ((target_list & 0xFFUL) << 16U) \| (IRQn & 0x0FUL);
AnnaBridge	171:3a7713b1edbc	1401	}
AnnaBridge	171:3a7713b1edbc	1402
AnnaBridge	171:3a7713b1edbc	1403	/** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
AnnaBridge	171:3a7713b1edbc	1404	* \return GICInterface_Type::HPPIR
AnnaBridge	171:3a7713b1edbc	1405	*/
AnnaBridge	171:3a7713b1edbc	1406	__STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
AnnaBridge	171:3a7713b1edbc	1407	{
AnnaBridge	171:3a7713b1edbc	1408	return GICInterface->HPPIR;
AnnaBridge	171:3a7713b1edbc	1409	}
AnnaBridge	171:3a7713b1edbc	1410
AnnaBridge	171:3a7713b1edbc	1411	/** \brief Provides information about the implementer and revision of the CPU interface.
AnnaBridge	171:3a7713b1edbc	1412	* \return GICInterface_Type::IIDR
AnnaBridge	171:3a7713b1edbc	1413	*/
AnnaBridge	171:3a7713b1edbc	1414	__STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
AnnaBridge	171:3a7713b1edbc	1415	{
AnnaBridge	171:3a7713b1edbc	1416	return GICInterface->IIDR;
AnnaBridge	171:3a7713b1edbc	1417	}
AnnaBridge	171:3a7713b1edbc	1418
AnnaBridge	171:3a7713b1edbc	1419	/** \brief Set the interrupt group from the GIC's IGROUPR register.
AnnaBridge	171:3a7713b1edbc	1420	* \param [in] IRQn The interrupt to be queried.
AnnaBridge	171:3a7713b1edbc	1421	* \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
AnnaBridge	171:3a7713b1edbc	1422	*/
AnnaBridge	171:3a7713b1edbc	1423	__STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
AnnaBridge	171:3a7713b1edbc	1424	{
AnnaBridge	171:3a7713b1edbc	1425	uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
AnnaBridge	171:3a7713b1edbc	1426	uint32_t shift = (IRQn % 32U);
AnnaBridge	171:3a7713b1edbc	1427
AnnaBridge	171:3a7713b1edbc	1428	igroupr &= (~(1U << shift));
AnnaBridge	171:3a7713b1edbc	1429	igroupr \|= ( (group & 1U) << shift);
AnnaBridge	171:3a7713b1edbc	1430
AnnaBridge	171:3a7713b1edbc	1431	GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
AnnaBridge	171:3a7713b1edbc	1432	}
AnnaBridge	171:3a7713b1edbc	1433	#define GIC_SetSecurity GIC_SetGroup
AnnaBridge	171:3a7713b1edbc	1434
AnnaBridge	171:3a7713b1edbc	1435	/** \brief Get the interrupt group from the GIC's IGROUPR register.
AnnaBridge	171:3a7713b1edbc	1436	* \param [in] IRQn The interrupt to be queried.
AnnaBridge	171:3a7713b1edbc	1437	* \return 0 - Group 0, 1 - Group 1
AnnaBridge	171:3a7713b1edbc	1438	*/
AnnaBridge	171:3a7713b1edbc	1439	__STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
AnnaBridge	171:3a7713b1edbc	1440	{
AnnaBridge	171:3a7713b1edbc	1441	return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
AnnaBridge	171:3a7713b1edbc	1442	}
AnnaBridge	171:3a7713b1edbc	1443	#define GIC_GetSecurity GIC_GetGroup
AnnaBridge	171:3a7713b1edbc	1444
AnnaBridge	171:3a7713b1edbc	1445	/** \brief Initialize the interrupt distributor.
AnnaBridge	171:3a7713b1edbc	1446	*/
AnnaBridge	171:3a7713b1edbc	1447	__STATIC_INLINE void GIC_DistInit(void)
AnnaBridge	171:3a7713b1edbc	1448	{
AnnaBridge	171:3a7713b1edbc	1449	uint32_t i;
AnnaBridge	171:3a7713b1edbc	1450	uint32_t num_irq = 0U;
AnnaBridge	171:3a7713b1edbc	1451	uint32_t priority_field;
AnnaBridge	171:3a7713b1edbc	1452
AnnaBridge	171:3a7713b1edbc	1453	//A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
AnnaBridge	171:3a7713b1edbc	1454	//configuring all of the interrupts as Secure.
AnnaBridge	171:3a7713b1edbc	1455
AnnaBridge	171:3a7713b1edbc	1456	//Disable interrupt forwarding
AnnaBridge	171:3a7713b1edbc	1457	GIC_DisableDistributor();
AnnaBridge	171:3a7713b1edbc	1458	//Get the maximum number of interrupts that the GIC supports
AnnaBridge	171:3a7713b1edbc	1459	num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);
AnnaBridge	171:3a7713b1edbc	1460
AnnaBridge	171:3a7713b1edbc	1461	/* Priority level is implementation defined.
AnnaBridge	171:3a7713b1edbc	1462	To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
AnnaBridge	171:3a7713b1edbc	1463	priority field and read back the value stored.*/
AnnaBridge	171:3a7713b1edbc	1464	GIC_SetPriority((IRQn_Type)0U, 0xFFU);
AnnaBridge	171:3a7713b1edbc	1465	priority_field = GIC_GetPriority((IRQn_Type)0U);
AnnaBridge	171:3a7713b1edbc	1466
AnnaBridge	171:3a7713b1edbc	1467	for (i = 32U; i < num_irq; i++)
AnnaBridge	171:3a7713b1edbc	1468	{
AnnaBridge	171:3a7713b1edbc	1469	//Disable the SPI interrupt
AnnaBridge	171:3a7713b1edbc	1470	GIC_DisableIRQ((IRQn_Type)i);
AnnaBridge	171:3a7713b1edbc	1471	//Set level-sensitive (and N-N model)
AnnaBridge	171:3a7713b1edbc	1472	GIC_SetConfiguration((IRQn_Type)i, 0U);
AnnaBridge	171:3a7713b1edbc	1473	//Set priority
AnnaBridge	171:3a7713b1edbc	1474	GIC_SetPriority((IRQn_Type)i, priority_field/2U);
AnnaBridge	171:3a7713b1edbc	1475	//Set target list to CPU0
AnnaBridge	171:3a7713b1edbc	1476	GIC_SetTarget((IRQn_Type)i, 1U);
AnnaBridge	171:3a7713b1edbc	1477	}
AnnaBridge	171:3a7713b1edbc	1478	//Enable distributor
AnnaBridge	171:3a7713b1edbc	1479	GIC_EnableDistributor();
AnnaBridge	171:3a7713b1edbc	1480	}
AnnaBridge	171:3a7713b1edbc	1481
AnnaBridge	171:3a7713b1edbc	1482	/** \brief Initialize the CPU's interrupt interface
AnnaBridge	171:3a7713b1edbc	1483	*/
AnnaBridge	171:3a7713b1edbc	1484	__STATIC_INLINE void GIC_CPUInterfaceInit(void)
AnnaBridge	171:3a7713b1edbc	1485	{
AnnaBridge	171:3a7713b1edbc	1486	uint32_t i;
AnnaBridge	171:3a7713b1edbc	1487	uint32_t priority_field;
AnnaBridge	171:3a7713b1edbc	1488
AnnaBridge	171:3a7713b1edbc	1489	//A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
AnnaBridge	171:3a7713b1edbc	1490	//configuring all of the interrupts as Secure.
AnnaBridge	171:3a7713b1edbc	1491
AnnaBridge	171:3a7713b1edbc	1492	//Disable interrupt forwarding
AnnaBridge	171:3a7713b1edbc	1493	GIC_DisableInterface();
AnnaBridge	171:3a7713b1edbc	1494
AnnaBridge	171:3a7713b1edbc	1495	/* Priority level is implementation defined.
AnnaBridge	171:3a7713b1edbc	1496	To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
AnnaBridge	171:3a7713b1edbc	1497	priority field and read back the value stored.*/
AnnaBridge	171:3a7713b1edbc	1498	GIC_SetPriority((IRQn_Type)0U, 0xFFU);
AnnaBridge	171:3a7713b1edbc	1499	priority_field = GIC_GetPriority((IRQn_Type)0U);
AnnaBridge	171:3a7713b1edbc	1500
AnnaBridge	171:3a7713b1edbc	1501	//SGI and PPI
AnnaBridge	171:3a7713b1edbc	1502	for (i = 0U; i < 32U; i++)
AnnaBridge	171:3a7713b1edbc	1503	{
AnnaBridge	171:3a7713b1edbc	1504	if(i > 15U) {
AnnaBridge	171:3a7713b1edbc	1505	//Set level-sensitive (and N-N model) for PPI
AnnaBridge	171:3a7713b1edbc	1506	GIC_SetConfiguration((IRQn_Type)i, 0U);
AnnaBridge	171:3a7713b1edbc	1507	}
AnnaBridge	171:3a7713b1edbc	1508	//Disable SGI and PPI interrupts
AnnaBridge	171:3a7713b1edbc	1509	GIC_DisableIRQ((IRQn_Type)i);
AnnaBridge	171:3a7713b1edbc	1510	//Set priority
AnnaBridge	171:3a7713b1edbc	1511	GIC_SetPriority((IRQn_Type)i, priority_field/2U);
AnnaBridge	171:3a7713b1edbc	1512	}
AnnaBridge	171:3a7713b1edbc	1513	//Enable interface
AnnaBridge	171:3a7713b1edbc	1514	GIC_EnableInterface();
AnnaBridge	171:3a7713b1edbc	1515	//Set binary point to 0
AnnaBridge	171:3a7713b1edbc	1516	GIC_SetBinaryPoint(0U);
AnnaBridge	171:3a7713b1edbc	1517	//Set priority mask
AnnaBridge	171:3a7713b1edbc	1518	GIC_SetInterfacePriorityMask(0xFFU);
AnnaBridge	171:3a7713b1edbc	1519	}
AnnaBridge	171:3a7713b1edbc	1520
AnnaBridge	171:3a7713b1edbc	1521	/** \brief Initialize and enable the GIC
AnnaBridge	171:3a7713b1edbc	1522	*/
AnnaBridge	171:3a7713b1edbc	1523	__STATIC_INLINE void GIC_Enable(void)
AnnaBridge	171:3a7713b1edbc	1524	{
AnnaBridge	171:3a7713b1edbc	1525	GIC_DistInit();
AnnaBridge	171:3a7713b1edbc	1526	GIC_CPUInterfaceInit(); //per CPU
AnnaBridge	171:3a7713b1edbc	1527	}
AnnaBridge	171:3a7713b1edbc	1528	#endif
AnnaBridge	171:3a7713b1edbc	1529
AnnaBridge	171:3a7713b1edbc	1530	/* ########################## Generic Timer functions ############################ */
AnnaBridge	171:3a7713b1edbc	1531	#if (__TIM_PRESENT == 1U) \|\| defined(DOXYGEN)
AnnaBridge	171:3a7713b1edbc	1532
AnnaBridge	171:3a7713b1edbc	1533	/* PL1 Physical Timer */
AnnaBridge	171:3a7713b1edbc	1534	#if (__CORTEX_A == 7U) \|\| defined(DOXYGEN)
AnnaBridge	171:3a7713b1edbc	1535
AnnaBridge	171:3a7713b1edbc	1536	/** \brief Physical Timer Control register */
AnnaBridge	171:3a7713b1edbc	1537	typedef union
AnnaBridge	171:3a7713b1edbc	1538	{
AnnaBridge	171:3a7713b1edbc	1539	struct
AnnaBridge	171:3a7713b1edbc	1540	{
AnnaBridge	171:3a7713b1edbc	1541	uint32_t ENABLE:1; /!< \brief bit: 0 Enables the timer. /
AnnaBridge	171:3a7713b1edbc	1542	uint32_t IMASK:1; /!< \brief bit: 1 Timer output signal mask bit. /
AnnaBridge	171:3a7713b1edbc	1543	uint32_t ISTATUS:1; /!< \brief bit: 2 The status of the timer. /
AnnaBridge	171:3a7713b1edbc	1544	RESERVED(0:29, uint32_t)
AnnaBridge	171:3a7713b1edbc	1545	} b; /!< \brief Structure used for bit access /
AnnaBridge	171:3a7713b1edbc	1546	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	171:3a7713b1edbc	1547	} CNTP_CTL_Type;
AnnaBridge	171:3a7713b1edbc	1548
AnnaBridge	171:3a7713b1edbc	1549	/** \brief Configures the frequency the timer shall run at.
AnnaBridge	171:3a7713b1edbc	1550	* \param [in] value The timer frequency in Hz.
AnnaBridge	171:3a7713b1edbc	1551	*/
AnnaBridge	171:3a7713b1edbc	1552	__STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
AnnaBridge	171:3a7713b1edbc	1553	{
AnnaBridge	171:3a7713b1edbc	1554	__set_CNTFRQ(value);
AnnaBridge	171:3a7713b1edbc	1555	__ISB();
AnnaBridge	171:3a7713b1edbc	1556	}
AnnaBridge	171:3a7713b1edbc	1557
AnnaBridge	171:3a7713b1edbc	1558	/** \brief Sets the reset value of the timer.
AnnaBridge	171:3a7713b1edbc	1559	* \param [in] value The value the timer is loaded with.
AnnaBridge	171:3a7713b1edbc	1560	*/
AnnaBridge	171:3a7713b1edbc	1561	__STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
AnnaBridge	171:3a7713b1edbc	1562	{
AnnaBridge	171:3a7713b1edbc	1563	__set_CNTP_TVAL(value);
AnnaBridge	171:3a7713b1edbc	1564	__ISB();
AnnaBridge	171:3a7713b1edbc	1565	}
AnnaBridge	171:3a7713b1edbc	1566
AnnaBridge	171:3a7713b1edbc	1567	/** \brief Get the current counter value.
AnnaBridge	171:3a7713b1edbc	1568	* \return Current counter value.
AnnaBridge	171:3a7713b1edbc	1569	*/
AnnaBridge	171:3a7713b1edbc	1570	__STATIC_INLINE uint32_t PL1_GetCurrentValue(void)
AnnaBridge	171:3a7713b1edbc	1571	{
AnnaBridge	171:3a7713b1edbc	1572	return(__get_CNTP_TVAL());
AnnaBridge	171:3a7713b1edbc	1573	}
AnnaBridge	171:3a7713b1edbc	1574
AnnaBridge	171:3a7713b1edbc	1575	/** \brief Get the current physical counter value.
AnnaBridge	171:3a7713b1edbc	1576	* \return Current physical counter value.
AnnaBridge	171:3a7713b1edbc	1577	*/
AnnaBridge	171:3a7713b1edbc	1578	__STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)
AnnaBridge	171:3a7713b1edbc	1579	{
AnnaBridge	171:3a7713b1edbc	1580	return(__get_CNTPCT());
AnnaBridge	171:3a7713b1edbc	1581	}
AnnaBridge	171:3a7713b1edbc	1582
AnnaBridge	171:3a7713b1edbc	1583	/** \brief Set the physical compare value.
AnnaBridge	171:3a7713b1edbc	1584	* \param [in] value New physical timer compare value.
AnnaBridge	171:3a7713b1edbc	1585	*/
AnnaBridge	171:3a7713b1edbc	1586	__STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)
AnnaBridge	171:3a7713b1edbc	1587	{
AnnaBridge	171:3a7713b1edbc	1588	__set_CNTP_CVAL(value);
AnnaBridge	171:3a7713b1edbc	1589	__ISB();
AnnaBridge	171:3a7713b1edbc	1590	}
AnnaBridge	171:3a7713b1edbc	1591
AnnaBridge	171:3a7713b1edbc	1592	/** \brief Get the physical compare value.
AnnaBridge	171:3a7713b1edbc	1593	* \return Physical compare value.
AnnaBridge	171:3a7713b1edbc	1594	*/
AnnaBridge	171:3a7713b1edbc	1595	__STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)
AnnaBridge	171:3a7713b1edbc	1596	{
AnnaBridge	171:3a7713b1edbc	1597	return(__get_CNTP_CVAL());
AnnaBridge	171:3a7713b1edbc	1598	}
AnnaBridge	171:3a7713b1edbc	1599
AnnaBridge	171:3a7713b1edbc	1600	/** \brief Configure the timer by setting the control value.
AnnaBridge	171:3a7713b1edbc	1601	* \param [in] value New timer control value.
AnnaBridge	171:3a7713b1edbc	1602	*/
AnnaBridge	171:3a7713b1edbc	1603	__STATIC_INLINE void PL1_SetControl(uint32_t value)
AnnaBridge	171:3a7713b1edbc	1604	{
AnnaBridge	171:3a7713b1edbc	1605	__set_CNTP_CTL(value);
AnnaBridge	171:3a7713b1edbc	1606	__ISB();
AnnaBridge	171:3a7713b1edbc	1607	}
AnnaBridge	171:3a7713b1edbc	1608
AnnaBridge	171:3a7713b1edbc	1609	/** \brief Get the control value.
AnnaBridge	171:3a7713b1edbc	1610	* \return Control value.
AnnaBridge	171:3a7713b1edbc	1611	*/
AnnaBridge	171:3a7713b1edbc	1612	__STATIC_INLINE uint32_t PL1_GetControl(void)
AnnaBridge	171:3a7713b1edbc	1613	{
AnnaBridge	171:3a7713b1edbc	1614	return(__get_CNTP_CTL());
AnnaBridge	171:3a7713b1edbc	1615	}
AnnaBridge	171:3a7713b1edbc	1616	#endif
AnnaBridge	171:3a7713b1edbc	1617
AnnaBridge	171:3a7713b1edbc	1618	/* Private Timer */
AnnaBridge	171:3a7713b1edbc	1619	#if ((__CORTEX_A == 5U) \|\| (__CORTEX_A == 9U)) \|\| defined(DOXYGEN)
AnnaBridge	171:3a7713b1edbc	1620	/** \brief Set the load value to timers LOAD register.
AnnaBridge	171:3a7713b1edbc	1621	* \param [in] value The load value to be set.
AnnaBridge	171:3a7713b1edbc	1622	*/
AnnaBridge	171:3a7713b1edbc	1623	__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
AnnaBridge	171:3a7713b1edbc	1624	{
AnnaBridge	171:3a7713b1edbc	1625	PTIM->LOAD = value;
AnnaBridge	171:3a7713b1edbc	1626	}
AnnaBridge	171:3a7713b1edbc	1627
AnnaBridge	171:3a7713b1edbc	1628	/** \brief Get the load value from timers LOAD register.
AnnaBridge	171:3a7713b1edbc	1629	* \return Timer_Type::LOAD
AnnaBridge	171:3a7713b1edbc	1630	*/
AnnaBridge	171:3a7713b1edbc	1631	__STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
AnnaBridge	171:3a7713b1edbc	1632	{
AnnaBridge	171:3a7713b1edbc	1633	return(PTIM->LOAD);
AnnaBridge	171:3a7713b1edbc	1634	}
AnnaBridge	171:3a7713b1edbc	1635
AnnaBridge	171:3a7713b1edbc	1636	/** \brief Set current counter value from its COUNTER register.
AnnaBridge	171:3a7713b1edbc	1637	*/
AnnaBridge	171:3a7713b1edbc	1638	__STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
AnnaBridge	171:3a7713b1edbc	1639	{
AnnaBridge	171:3a7713b1edbc	1640	PTIM->COUNTER = value;
AnnaBridge	171:3a7713b1edbc	1641	}
AnnaBridge	171:3a7713b1edbc	1642
AnnaBridge	171:3a7713b1edbc	1643	/** \brief Get current counter value from timers COUNTER register.
AnnaBridge	171:3a7713b1edbc	1644	* \result Timer_Type::COUNTER
AnnaBridge	171:3a7713b1edbc	1645	*/
AnnaBridge	171:3a7713b1edbc	1646	__STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
AnnaBridge	171:3a7713b1edbc	1647	{
AnnaBridge	171:3a7713b1edbc	1648	return(PTIM->COUNTER);
AnnaBridge	171:3a7713b1edbc	1649	}
AnnaBridge	171:3a7713b1edbc	1650
AnnaBridge	171:3a7713b1edbc	1651	/** \brief Configure the timer using its CONTROL register.
AnnaBridge	171:3a7713b1edbc	1652	* \param [in] value The new configuration value to be set.
AnnaBridge	171:3a7713b1edbc	1653	*/
AnnaBridge	171:3a7713b1edbc	1654	__STATIC_INLINE void PTIM_SetControl(uint32_t value)
AnnaBridge	171:3a7713b1edbc	1655	{
AnnaBridge	171:3a7713b1edbc	1656	PTIM->CONTROL = value;
AnnaBridge	171:3a7713b1edbc	1657	}
AnnaBridge	171:3a7713b1edbc	1658
AnnaBridge	171:3a7713b1edbc	1659	/** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
AnnaBridge	171:3a7713b1edbc	1660	* \return Timer_Type::CONTROL
AnnaBridge	171:3a7713b1edbc	1661	*/
AnnaBridge	171:3a7713b1edbc	1662	__STATIC_INLINE uint32_t PTIM_GetControl(void)
AnnaBridge	171:3a7713b1edbc	1663	{
AnnaBridge	171:3a7713b1edbc	1664	return(PTIM->CONTROL);
AnnaBridge	171:3a7713b1edbc	1665	}
AnnaBridge	171:3a7713b1edbc	1666
AnnaBridge	171:3a7713b1edbc	1667	/** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
AnnaBridge	171:3a7713b1edbc	1668	* \return 0 - flag is not set, 1- flag is set
AnnaBridge	171:3a7713b1edbc	1669	*/
AnnaBridge	171:3a7713b1edbc	1670	__STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
AnnaBridge	171:3a7713b1edbc	1671	{
AnnaBridge	171:3a7713b1edbc	1672	return (PTIM->ISR & 1UL);
AnnaBridge	171:3a7713b1edbc	1673	}
AnnaBridge	171:3a7713b1edbc	1674
AnnaBridge	171:3a7713b1edbc	1675	/** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
AnnaBridge	171:3a7713b1edbc	1676	*/
AnnaBridge	171:3a7713b1edbc	1677	__STATIC_INLINE void PTIM_ClearEventFlag(void)
AnnaBridge	171:3a7713b1edbc	1678	{
AnnaBridge	171:3a7713b1edbc	1679	PTIM->ISR = 1;
AnnaBridge	171:3a7713b1edbc	1680	}
AnnaBridge	171:3a7713b1edbc	1681	#endif
AnnaBridge	171:3a7713b1edbc	1682	#endif
AnnaBridge	171:3a7713b1edbc	1683
AnnaBridge	171:3a7713b1edbc	1684	/* ########################## MMU functions ###################################### */
AnnaBridge	171:3a7713b1edbc	1685
AnnaBridge	171:3a7713b1edbc	1686	#define SECTION_DESCRIPTOR (0x2)
AnnaBridge	171:3a7713b1edbc	1687	#define SECTION_MASK (0xFFFFFFFC)
AnnaBridge	171:3a7713b1edbc	1688
AnnaBridge	171:3a7713b1edbc	1689	#define SECTION_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge	171:3a7713b1edbc	1690	#define SECTION_B_SHIFT (2)
AnnaBridge	171:3a7713b1edbc	1691	#define SECTION_C_SHIFT (3)
AnnaBridge	171:3a7713b1edbc	1692	#define SECTION_TEX0_SHIFT (12)
AnnaBridge	171:3a7713b1edbc	1693	#define SECTION_TEX1_SHIFT (13)
AnnaBridge	171:3a7713b1edbc	1694	#define SECTION_TEX2_SHIFT (14)
AnnaBridge	171:3a7713b1edbc	1695
AnnaBridge	171:3a7713b1edbc	1696	#define SECTION_XN_MASK (0xFFFFFFEF)
AnnaBridge	171:3a7713b1edbc	1697	#define SECTION_XN_SHIFT (4)
AnnaBridge	171:3a7713b1edbc	1698
AnnaBridge	171:3a7713b1edbc	1699	#define SECTION_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge	171:3a7713b1edbc	1700	#define SECTION_DOMAIN_SHIFT (5)
AnnaBridge	171:3a7713b1edbc	1701
AnnaBridge	171:3a7713b1edbc	1702	#define SECTION_P_MASK (0xFFFFFDFF)
AnnaBridge	171:3a7713b1edbc	1703	#define SECTION_P_SHIFT (9)
AnnaBridge	171:3a7713b1edbc	1704
AnnaBridge	171:3a7713b1edbc	1705	#define SECTION_AP_MASK (0xFFFF73FF)
AnnaBridge	171:3a7713b1edbc	1706	#define SECTION_AP_SHIFT (10)
AnnaBridge	171:3a7713b1edbc	1707	#define SECTION_AP2_SHIFT (15)
AnnaBridge	171:3a7713b1edbc	1708
AnnaBridge	171:3a7713b1edbc	1709	#define SECTION_S_MASK (0xFFFEFFFF)
AnnaBridge	171:3a7713b1edbc	1710	#define SECTION_S_SHIFT (16)
AnnaBridge	171:3a7713b1edbc	1711
AnnaBridge	171:3a7713b1edbc	1712	#define SECTION_NG_MASK (0xFFFDFFFF)
AnnaBridge	171:3a7713b1edbc	1713	#define SECTION_NG_SHIFT (17)
AnnaBridge	171:3a7713b1edbc	1714
AnnaBridge	171:3a7713b1edbc	1715	#define SECTION_NS_MASK (0xFFF7FFFF)
AnnaBridge	171:3a7713b1edbc	1716	#define SECTION_NS_SHIFT (19)
AnnaBridge	171:3a7713b1edbc	1717
AnnaBridge	171:3a7713b1edbc	1718	#define PAGE_L1_DESCRIPTOR (0x1)
AnnaBridge	171:3a7713b1edbc	1719	#define PAGE_L1_MASK (0xFFFFFFFC)
AnnaBridge	171:3a7713b1edbc	1720
AnnaBridge	171:3a7713b1edbc	1721	#define PAGE_L2_4K_DESC (0x2)
AnnaBridge	171:3a7713b1edbc	1722	#define PAGE_L2_4K_MASK (0xFFFFFFFD)
AnnaBridge	171:3a7713b1edbc	1723
AnnaBridge	171:3a7713b1edbc	1724	#define PAGE_L2_64K_DESC (0x1)
AnnaBridge	171:3a7713b1edbc	1725	#define PAGE_L2_64K_MASK (0xFFFFFFFC)
AnnaBridge	171:3a7713b1edbc	1726
AnnaBridge	171:3a7713b1edbc	1727	#define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
AnnaBridge	171:3a7713b1edbc	1728	#define PAGE_4K_B_SHIFT (2)
AnnaBridge	171:3a7713b1edbc	1729	#define PAGE_4K_C_SHIFT (3)
AnnaBridge	171:3a7713b1edbc	1730	#define PAGE_4K_TEX0_SHIFT (6)
AnnaBridge	171:3a7713b1edbc	1731	#define PAGE_4K_TEX1_SHIFT (7)
AnnaBridge	171:3a7713b1edbc	1732	#define PAGE_4K_TEX2_SHIFT (8)
AnnaBridge	171:3a7713b1edbc	1733
AnnaBridge	171:3a7713b1edbc	1734	#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge	171:3a7713b1edbc	1735	#define PAGE_64K_B_SHIFT (2)
AnnaBridge	171:3a7713b1edbc	1736	#define PAGE_64K_C_SHIFT (3)
AnnaBridge	171:3a7713b1edbc	1737	#define PAGE_64K_TEX0_SHIFT (12)
AnnaBridge	171:3a7713b1edbc	1738	#define PAGE_64K_TEX1_SHIFT (13)
AnnaBridge	171:3a7713b1edbc	1739	#define PAGE_64K_TEX2_SHIFT (14)
AnnaBridge	171:3a7713b1edbc	1740
AnnaBridge	171:3a7713b1edbc	1741	#define PAGE_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge	171:3a7713b1edbc	1742	#define PAGE_B_SHIFT (2)
AnnaBridge	171:3a7713b1edbc	1743	#define PAGE_C_SHIFT (3)
AnnaBridge	171:3a7713b1edbc	1744	#define PAGE_TEX_SHIFT (12)
AnnaBridge	171:3a7713b1edbc	1745
AnnaBridge	171:3a7713b1edbc	1746	#define PAGE_XN_4K_MASK (0xFFFFFFFE)
AnnaBridge	171:3a7713b1edbc	1747	#define PAGE_XN_4K_SHIFT (0)
AnnaBridge	171:3a7713b1edbc	1748	#define PAGE_XN_64K_MASK (0xFFFF7FFF)
AnnaBridge	171:3a7713b1edbc	1749	#define PAGE_XN_64K_SHIFT (15)
AnnaBridge	171:3a7713b1edbc	1750
AnnaBridge	171:3a7713b1edbc	1751	#define PAGE_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge	171:3a7713b1edbc	1752	#define PAGE_DOMAIN_SHIFT (5)
AnnaBridge	171:3a7713b1edbc	1753
AnnaBridge	171:3a7713b1edbc	1754	#define PAGE_P_MASK (0xFFFFFDFF)
AnnaBridge	171:3a7713b1edbc	1755	#define PAGE_P_SHIFT (9)
AnnaBridge	171:3a7713b1edbc	1756
AnnaBridge	171:3a7713b1edbc	1757	#define PAGE_AP_MASK (0xFFFFFDCF)
AnnaBridge	171:3a7713b1edbc	1758	#define PAGE_AP_SHIFT (4)
AnnaBridge	171:3a7713b1edbc	1759	#define PAGE_AP2_SHIFT (9)
AnnaBridge	171:3a7713b1edbc	1760
AnnaBridge	171:3a7713b1edbc	1761	#define PAGE_S_MASK (0xFFFFFBFF)
AnnaBridge	171:3a7713b1edbc	1762	#define PAGE_S_SHIFT (10)
AnnaBridge	171:3a7713b1edbc	1763
AnnaBridge	171:3a7713b1edbc	1764	#define PAGE_NG_MASK (0xFFFFF7FF)
AnnaBridge	171:3a7713b1edbc	1765	#define PAGE_NG_SHIFT (11)
AnnaBridge	171:3a7713b1edbc	1766
AnnaBridge	171:3a7713b1edbc	1767	#define PAGE_NS_MASK (0xFFFFFFF7)
AnnaBridge	171:3a7713b1edbc	1768	#define PAGE_NS_SHIFT (3)
AnnaBridge	171:3a7713b1edbc	1769
AnnaBridge	171:3a7713b1edbc	1770	#define OFFSET_1M (0x00100000)
AnnaBridge	171:3a7713b1edbc	1771	#define OFFSET_64K (0x00010000)
AnnaBridge	171:3a7713b1edbc	1772	#define OFFSET_4K (0x00001000)
AnnaBridge	171:3a7713b1edbc	1773
AnnaBridge	171:3a7713b1edbc	1774	#define DESCRIPTOR_FAULT (0x00000000)
AnnaBridge	171:3a7713b1edbc	1775
AnnaBridge	171:3a7713b1edbc	1776	/* Attributes enumerations */
AnnaBridge	171:3a7713b1edbc	1777
AnnaBridge	171:3a7713b1edbc	1778	/* Region size attributes */
AnnaBridge	171:3a7713b1edbc	1779	typedef enum
AnnaBridge	171:3a7713b1edbc	1780	{
AnnaBridge	171:3a7713b1edbc	1781	SECTION,
AnnaBridge	171:3a7713b1edbc	1782	PAGE_4k,
AnnaBridge	171:3a7713b1edbc	1783	PAGE_64k,
AnnaBridge	171:3a7713b1edbc	1784	} mmu_region_size_Type;
AnnaBridge	171:3a7713b1edbc	1785
AnnaBridge	171:3a7713b1edbc	1786	/* Region type attributes */
AnnaBridge	171:3a7713b1edbc	1787	typedef enum
AnnaBridge	171:3a7713b1edbc	1788	{
AnnaBridge	171:3a7713b1edbc	1789	NORMAL,
AnnaBridge	171:3a7713b1edbc	1790	DEVICE,
AnnaBridge	171:3a7713b1edbc	1791	SHARED_DEVICE,
AnnaBridge	171:3a7713b1edbc	1792	NON_SHARED_DEVICE,
AnnaBridge	171:3a7713b1edbc	1793	STRONGLY_ORDERED
AnnaBridge	171:3a7713b1edbc	1794	} mmu_memory_Type;
AnnaBridge	171:3a7713b1edbc	1795
AnnaBridge	171:3a7713b1edbc	1796	/* Region cacheability attributes */
AnnaBridge	171:3a7713b1edbc	1797	typedef enum
AnnaBridge	171:3a7713b1edbc	1798	{
AnnaBridge	171:3a7713b1edbc	1799	NON_CACHEABLE,
AnnaBridge	171:3a7713b1edbc	1800	WB_WA,
AnnaBridge	171:3a7713b1edbc	1801	WT,
AnnaBridge	171:3a7713b1edbc	1802	WB_NO_WA,
AnnaBridge	171:3a7713b1edbc	1803	} mmu_cacheability_Type;
AnnaBridge	171:3a7713b1edbc	1804
AnnaBridge	171:3a7713b1edbc	1805	/* Region parity check attributes */
AnnaBridge	171:3a7713b1edbc	1806	typedef enum
AnnaBridge	171:3a7713b1edbc	1807	{
AnnaBridge	171:3a7713b1edbc	1808	ECC_DISABLED,
AnnaBridge	171:3a7713b1edbc	1809	ECC_ENABLED,
AnnaBridge	171:3a7713b1edbc	1810	} mmu_ecc_check_Type;
AnnaBridge	171:3a7713b1edbc	1811
AnnaBridge	171:3a7713b1edbc	1812	/* Region execution attributes */
AnnaBridge	171:3a7713b1edbc	1813	typedef enum
AnnaBridge	171:3a7713b1edbc	1814	{
AnnaBridge	171:3a7713b1edbc	1815	EXECUTE,
AnnaBridge	171:3a7713b1edbc	1816	NON_EXECUTE,
AnnaBridge	171:3a7713b1edbc	1817	} mmu_execute_Type;
AnnaBridge	171:3a7713b1edbc	1818
AnnaBridge	171:3a7713b1edbc	1819	/* Region global attributes */
AnnaBridge	171:3a7713b1edbc	1820	typedef enum
AnnaBridge	171:3a7713b1edbc	1821	{
AnnaBridge	171:3a7713b1edbc	1822	GLOBAL,
AnnaBridge	171:3a7713b1edbc	1823	NON_GLOBAL,
AnnaBridge	171:3a7713b1edbc	1824	} mmu_global_Type;
AnnaBridge	171:3a7713b1edbc	1825
AnnaBridge	171:3a7713b1edbc	1826	/* Region shareability attributes */
AnnaBridge	171:3a7713b1edbc	1827	typedef enum
AnnaBridge	171:3a7713b1edbc	1828	{
AnnaBridge	171:3a7713b1edbc	1829	NON_SHARED,
AnnaBridge	171:3a7713b1edbc	1830	SHARED,
AnnaBridge	171:3a7713b1edbc	1831	} mmu_shared_Type;
AnnaBridge	171:3a7713b1edbc	1832
AnnaBridge	171:3a7713b1edbc	1833	/* Region security attributes */
AnnaBridge	171:3a7713b1edbc	1834	typedef enum
AnnaBridge	171:3a7713b1edbc	1835	{
AnnaBridge	171:3a7713b1edbc	1836	SECURE,
AnnaBridge	171:3a7713b1edbc	1837	NON_SECURE,
AnnaBridge	171:3a7713b1edbc	1838	} mmu_secure_Type;
AnnaBridge	171:3a7713b1edbc	1839
AnnaBridge	171:3a7713b1edbc	1840	/* Region access attributes */
AnnaBridge	171:3a7713b1edbc	1841	typedef enum
AnnaBridge	171:3a7713b1edbc	1842	{
AnnaBridge	171:3a7713b1edbc	1843	NO_ACCESS,
AnnaBridge	171:3a7713b1edbc	1844	RW,
AnnaBridge	171:3a7713b1edbc	1845	READ,
AnnaBridge	171:3a7713b1edbc	1846	} mmu_access_Type;
AnnaBridge	171:3a7713b1edbc	1847
AnnaBridge	171:3a7713b1edbc	1848	/* Memory Region definition */
AnnaBridge	171:3a7713b1edbc	1849	typedef struct RegionStruct {
AnnaBridge	171:3a7713b1edbc	1850	mmu_region_size_Type rg_t;
AnnaBridge	171:3a7713b1edbc	1851	mmu_memory_Type mem_t;
AnnaBridge	171:3a7713b1edbc	1852	uint8_t domain;
AnnaBridge	171:3a7713b1edbc	1853	mmu_cacheability_Type inner_norm_t;
AnnaBridge	171:3a7713b1edbc	1854	mmu_cacheability_Type outer_norm_t;
AnnaBridge	171:3a7713b1edbc	1855	mmu_ecc_check_Type e_t;
AnnaBridge	171:3a7713b1edbc	1856	mmu_execute_Type xn_t;
AnnaBridge	171:3a7713b1edbc	1857	mmu_global_Type g_t;
AnnaBridge	171:3a7713b1edbc	1858	mmu_secure_Type sec_t;
AnnaBridge	171:3a7713b1edbc	1859	mmu_access_Type priv_t;
AnnaBridge	171:3a7713b1edbc	1860	mmu_access_Type user_t;
AnnaBridge	171:3a7713b1edbc	1861	mmu_shared_Type sh_t;
AnnaBridge	171:3a7713b1edbc	1862
AnnaBridge	171:3a7713b1edbc	1863	} mmu_region_attributes_Type;
AnnaBridge	171:3a7713b1edbc	1864
AnnaBridge	171:3a7713b1edbc	1865	//Following macros define the descriptors and attributes
AnnaBridge	171:3a7713b1edbc	1866	//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
AnnaBridge	171:3a7713b1edbc	1867	#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	171:3a7713b1edbc	1868	region.domain = 0x0; \
AnnaBridge	171:3a7713b1edbc	1869	region.e_t = ECC_DISABLED; \
AnnaBridge	171:3a7713b1edbc	1870	region.g_t = GLOBAL; \
AnnaBridge	171:3a7713b1edbc	1871	region.inner_norm_t = WB_WA; \
AnnaBridge	171:3a7713b1edbc	1872	region.outer_norm_t = WB_WA; \
AnnaBridge	171:3a7713b1edbc	1873	region.mem_t = NORMAL; \
AnnaBridge	171:3a7713b1edbc	1874	region.sec_t = SECURE; \
AnnaBridge	171:3a7713b1edbc	1875	region.xn_t = EXECUTE; \
AnnaBridge	171:3a7713b1edbc	1876	region.priv_t = RW; \
AnnaBridge	171:3a7713b1edbc	1877	region.user_t = RW; \
AnnaBridge	171:3a7713b1edbc	1878	region.sh_t = NON_SHARED; \
AnnaBridge	171:3a7713b1edbc	1879	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	171:3a7713b1edbc	1880
AnnaBridge	171:3a7713b1edbc	1881	//Sect_Normal_NC. Outer & inner non-cacheable, non-shareable, executable, rw, domain 0
AnnaBridge	171:3a7713b1edbc	1882	#define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	171:3a7713b1edbc	1883	region.domain = 0x0; \
AnnaBridge	171:3a7713b1edbc	1884	region.e_t = ECC_DISABLED; \
AnnaBridge	171:3a7713b1edbc	1885	region.g_t = GLOBAL; \
AnnaBridge	171:3a7713b1edbc	1886	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	171:3a7713b1edbc	1887	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	171:3a7713b1edbc	1888	region.mem_t = NORMAL; \
AnnaBridge	171:3a7713b1edbc	1889	region.sec_t = SECURE; \
AnnaBridge	171:3a7713b1edbc	1890	region.xn_t = EXECUTE; \
AnnaBridge	171:3a7713b1edbc	1891	region.priv_t = RW; \
AnnaBridge	171:3a7713b1edbc	1892	region.user_t = RW; \
AnnaBridge	171:3a7713b1edbc	1893	region.sh_t = NON_SHARED; \
AnnaBridge	171:3a7713b1edbc	1894	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	171:3a7713b1edbc	1895
AnnaBridge	171:3a7713b1edbc	1896	//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
AnnaBridge	171:3a7713b1edbc	1897	#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	171:3a7713b1edbc	1898	region.domain = 0x0; \
AnnaBridge	171:3a7713b1edbc	1899	region.e_t = ECC_DISABLED; \
AnnaBridge	171:3a7713b1edbc	1900	region.g_t = GLOBAL; \
AnnaBridge	171:3a7713b1edbc	1901	region.inner_norm_t = WB_WA; \
AnnaBridge	171:3a7713b1edbc	1902	region.outer_norm_t = WB_WA; \
AnnaBridge	171:3a7713b1edbc	1903	region.mem_t = NORMAL; \
AnnaBridge	171:3a7713b1edbc	1904	region.sec_t = SECURE; \
AnnaBridge	171:3a7713b1edbc	1905	region.xn_t = EXECUTE; \
AnnaBridge	171:3a7713b1edbc	1906	region.priv_t = READ; \
AnnaBridge	171:3a7713b1edbc	1907	region.user_t = READ; \
AnnaBridge	171:3a7713b1edbc	1908	region.sh_t = NON_SHARED; \
AnnaBridge	171:3a7713b1edbc	1909	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	171:3a7713b1edbc	1910
AnnaBridge	171:3a7713b1edbc	1911	//Sect_Normal_RO. Sect_Normal_Cod, but not executable
AnnaBridge	171:3a7713b1edbc	1912	#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	171:3a7713b1edbc	1913	region.domain = 0x0; \
AnnaBridge	171:3a7713b1edbc	1914	region.e_t = ECC_DISABLED; \
AnnaBridge	171:3a7713b1edbc	1915	region.g_t = GLOBAL; \
AnnaBridge	171:3a7713b1edbc	1916	region.inner_norm_t = WB_WA; \
AnnaBridge	171:3a7713b1edbc	1917	region.outer_norm_t = WB_WA; \
AnnaBridge	171:3a7713b1edbc	1918	region.mem_t = NORMAL; \
AnnaBridge	171:3a7713b1edbc	1919	region.sec_t = SECURE; \
AnnaBridge	171:3a7713b1edbc	1920	region.xn_t = NON_EXECUTE; \
AnnaBridge	171:3a7713b1edbc	1921	region.priv_t = READ; \
AnnaBridge	171:3a7713b1edbc	1922	region.user_t = READ; \
AnnaBridge	171:3a7713b1edbc	1923	region.sh_t = NON_SHARED; \
AnnaBridge	171:3a7713b1edbc	1924	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	171:3a7713b1edbc	1925
AnnaBridge	171:3a7713b1edbc	1926	//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
AnnaBridge	171:3a7713b1edbc	1927	#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	171:3a7713b1edbc	1928	region.domain = 0x0; \
AnnaBridge	171:3a7713b1edbc	1929	region.e_t = ECC_DISABLED; \
AnnaBridge	171:3a7713b1edbc	1930	region.g_t = GLOBAL; \
AnnaBridge	171:3a7713b1edbc	1931	region.inner_norm_t = WB_WA; \
AnnaBridge	171:3a7713b1edbc	1932	region.outer_norm_t = WB_WA; \
AnnaBridge	171:3a7713b1edbc	1933	region.mem_t = NORMAL; \
AnnaBridge	171:3a7713b1edbc	1934	region.sec_t = SECURE; \
AnnaBridge	171:3a7713b1edbc	1935	region.xn_t = NON_EXECUTE; \
AnnaBridge	171:3a7713b1edbc	1936	region.priv_t = RW; \
AnnaBridge	171:3a7713b1edbc	1937	region.user_t = RW; \
AnnaBridge	171:3a7713b1edbc	1938	region.sh_t = NON_SHARED; \
AnnaBridge	171:3a7713b1edbc	1939	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	171:3a7713b1edbc	1940	//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
AnnaBridge	171:3a7713b1edbc	1941	#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	171:3a7713b1edbc	1942	region.domain = 0x0; \
AnnaBridge	171:3a7713b1edbc	1943	region.e_t = ECC_DISABLED; \
AnnaBridge	171:3a7713b1edbc	1944	region.g_t = GLOBAL; \
AnnaBridge	171:3a7713b1edbc	1945	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	171:3a7713b1edbc	1946	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	171:3a7713b1edbc	1947	region.mem_t = STRONGLY_ORDERED; \
AnnaBridge	171:3a7713b1edbc	1948	region.sec_t = SECURE; \
AnnaBridge	171:3a7713b1edbc	1949	region.xn_t = NON_EXECUTE; \
AnnaBridge	171:3a7713b1edbc	1950	region.priv_t = RW; \
AnnaBridge	171:3a7713b1edbc	1951	region.user_t = RW; \
AnnaBridge	171:3a7713b1edbc	1952	region.sh_t = NON_SHARED; \
AnnaBridge	171:3a7713b1edbc	1953	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	171:3a7713b1edbc	1954
AnnaBridge	171:3a7713b1edbc	1955	//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
AnnaBridge	171:3a7713b1edbc	1956	#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	171:3a7713b1edbc	1957	region.domain = 0x0; \
AnnaBridge	171:3a7713b1edbc	1958	region.e_t = ECC_DISABLED; \
AnnaBridge	171:3a7713b1edbc	1959	region.g_t = GLOBAL; \
AnnaBridge	171:3a7713b1edbc	1960	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	171:3a7713b1edbc	1961	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	171:3a7713b1edbc	1962	region.mem_t = STRONGLY_ORDERED; \
AnnaBridge	171:3a7713b1edbc	1963	region.sec_t = SECURE; \
AnnaBridge	171:3a7713b1edbc	1964	region.xn_t = NON_EXECUTE; \
AnnaBridge	171:3a7713b1edbc	1965	region.priv_t = READ; \
AnnaBridge	171:3a7713b1edbc	1966	region.user_t = READ; \
AnnaBridge	171:3a7713b1edbc	1967	region.sh_t = NON_SHARED; \
AnnaBridge	171:3a7713b1edbc	1968	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	171:3a7713b1edbc	1969
AnnaBridge	171:3a7713b1edbc	1970	//Sect_Device_RW. Sect_Device_RO, but writeable
AnnaBridge	171:3a7713b1edbc	1971	#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	171:3a7713b1edbc	1972	region.domain = 0x0; \
AnnaBridge	171:3a7713b1edbc	1973	region.e_t = ECC_DISABLED; \
AnnaBridge	171:3a7713b1edbc	1974	region.g_t = GLOBAL; \
AnnaBridge	171:3a7713b1edbc	1975	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	171:3a7713b1edbc	1976	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	171:3a7713b1edbc	1977	region.mem_t = STRONGLY_ORDERED; \
AnnaBridge	171:3a7713b1edbc	1978	region.sec_t = SECURE; \
AnnaBridge	171:3a7713b1edbc	1979	region.xn_t = NON_EXECUTE; \
AnnaBridge	171:3a7713b1edbc	1980	region.priv_t = RW; \
AnnaBridge	171:3a7713b1edbc	1981	region.user_t = RW; \
AnnaBridge	171:3a7713b1edbc	1982	region.sh_t = NON_SHARED; \
AnnaBridge	171:3a7713b1edbc	1983	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	171:3a7713b1edbc	1984	//Page_4k_Device_RW. Shared device, not executable, rw, domain 0
AnnaBridge	171:3a7713b1edbc	1985	#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
AnnaBridge	171:3a7713b1edbc	1986	region.domain = 0x0; \
AnnaBridge	171:3a7713b1edbc	1987	region.e_t = ECC_DISABLED; \
AnnaBridge	171:3a7713b1edbc	1988	region.g_t = GLOBAL; \
AnnaBridge	171:3a7713b1edbc	1989	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	171:3a7713b1edbc	1990	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	171:3a7713b1edbc	1991	region.mem_t = SHARED_DEVICE; \
AnnaBridge	171:3a7713b1edbc	1992	region.sec_t = SECURE; \
AnnaBridge	171:3a7713b1edbc	1993	region.xn_t = NON_EXECUTE; \
AnnaBridge	171:3a7713b1edbc	1994	region.priv_t = RW; \
AnnaBridge	171:3a7713b1edbc	1995	region.user_t = RW; \
AnnaBridge	171:3a7713b1edbc	1996	region.sh_t = NON_SHARED; \
AnnaBridge	171:3a7713b1edbc	1997	MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
AnnaBridge	171:3a7713b1edbc	1998
AnnaBridge	171:3a7713b1edbc	1999	//Page_64k_Device_RW. Shared device, not executable, rw, domain 0
AnnaBridge	171:3a7713b1edbc	2000	#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
AnnaBridge	171:3a7713b1edbc	2001	region.domain = 0x0; \
AnnaBridge	171:3a7713b1edbc	2002	region.e_t = ECC_DISABLED; \
AnnaBridge	171:3a7713b1edbc	2003	region.g_t = GLOBAL; \
AnnaBridge	171:3a7713b1edbc	2004	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	171:3a7713b1edbc	2005	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	171:3a7713b1edbc	2006	region.mem_t = SHARED_DEVICE; \
AnnaBridge	171:3a7713b1edbc	2007	region.sec_t = SECURE; \
AnnaBridge	171:3a7713b1edbc	2008	region.xn_t = NON_EXECUTE; \
AnnaBridge	171:3a7713b1edbc	2009	region.priv_t = RW; \
AnnaBridge	171:3a7713b1edbc	2010	region.user_t = RW; \
AnnaBridge	171:3a7713b1edbc	2011	region.sh_t = NON_SHARED; \
AnnaBridge	171:3a7713b1edbc	2012	MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
AnnaBridge	171:3a7713b1edbc	2013
AnnaBridge	171:3a7713b1edbc	2014	/** \brief Set section execution-never attribute
AnnaBridge	171:3a7713b1edbc	2015
AnnaBridge	171:3a7713b1edbc	2016	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	171:3a7713b1edbc	2017	\param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge	171:3a7713b1edbc	2018
AnnaBridge	171:3a7713b1edbc	2019	\return 0
AnnaBridge	171:3a7713b1edbc	2020	*/
AnnaBridge	171:3a7713b1edbc	2021	__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
AnnaBridge	171:3a7713b1edbc	2022	{
AnnaBridge	171:3a7713b1edbc	2023	*descriptor_l1 &= SECTION_XN_MASK;
AnnaBridge	171:3a7713b1edbc	2024	*descriptor_l1 \|= ((xn & 0x1) << SECTION_XN_SHIFT);
AnnaBridge	171:3a7713b1edbc	2025	return 0;
AnnaBridge	171:3a7713b1edbc	2026	}
AnnaBridge	171:3a7713b1edbc	2027
AnnaBridge	171:3a7713b1edbc	2028	/** \brief Set section domain
AnnaBridge	171:3a7713b1edbc	2029
AnnaBridge	171:3a7713b1edbc	2030	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	171:3a7713b1edbc	2031	\param [in] domain Section domain
AnnaBridge	171:3a7713b1edbc	2032
AnnaBridge	171:3a7713b1edbc	2033	\return 0
AnnaBridge	171:3a7713b1edbc	2034	*/
AnnaBridge	171:3a7713b1edbc	2035	__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge	171:3a7713b1edbc	2036	{
AnnaBridge	171:3a7713b1edbc	2037	*descriptor_l1 &= SECTION_DOMAIN_MASK;
AnnaBridge	171:3a7713b1edbc	2038	*descriptor_l1 \|= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
AnnaBridge	171:3a7713b1edbc	2039	return 0;
AnnaBridge	171:3a7713b1edbc	2040	}
AnnaBridge	171:3a7713b1edbc	2041
AnnaBridge	171:3a7713b1edbc	2042	/** \brief Set section parity check
AnnaBridge	171:3a7713b1edbc	2043
AnnaBridge	171:3a7713b1edbc	2044	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	171:3a7713b1edbc	2045	\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge	171:3a7713b1edbc	2046
AnnaBridge	171:3a7713b1edbc	2047	\return 0
AnnaBridge	171:3a7713b1edbc	2048	*/
AnnaBridge	171:3a7713b1edbc	2049	__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge	171:3a7713b1edbc	2050	{
AnnaBridge	171:3a7713b1edbc	2051	*descriptor_l1 &= SECTION_P_MASK;
AnnaBridge	171:3a7713b1edbc	2052	*descriptor_l1 \|= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge	171:3a7713b1edbc	2053	return 0;
AnnaBridge	171:3a7713b1edbc	2054	}
AnnaBridge	171:3a7713b1edbc	2055
AnnaBridge	171:3a7713b1edbc	2056	/** \brief Set section access privileges
AnnaBridge	171:3a7713b1edbc	2057
AnnaBridge	171:3a7713b1edbc	2058	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	171:3a7713b1edbc	2059	\param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge	171:3a7713b1edbc	2060	\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge	171:3a7713b1edbc	2061	\param [in] afe Access flag enable
AnnaBridge	171:3a7713b1edbc	2062
AnnaBridge	171:3a7713b1edbc	2063	\return 0
AnnaBridge	171:3a7713b1edbc	2064	*/
AnnaBridge	171:3a7713b1edbc	2065	__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge	171:3a7713b1edbc	2066	{
AnnaBridge	171:3a7713b1edbc	2067	uint32_t ap = 0;
AnnaBridge	171:3a7713b1edbc	2068
AnnaBridge	171:3a7713b1edbc	2069	if (afe == 0) { //full access
AnnaBridge	171:3a7713b1edbc	2070	if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge	171:3a7713b1edbc	2071	else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge	171:3a7713b1edbc	2072	else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge	171:3a7713b1edbc	2073	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge	171:3a7713b1edbc	2074	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge	171:3a7713b1edbc	2075	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge	171:3a7713b1edbc	2076	}
AnnaBridge	171:3a7713b1edbc	2077
AnnaBridge	171:3a7713b1edbc	2078	else { //Simplified access
AnnaBridge	171:3a7713b1edbc	2079	if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge	171:3a7713b1edbc	2080	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge	171:3a7713b1edbc	2081	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge	171:3a7713b1edbc	2082	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge	171:3a7713b1edbc	2083	}
AnnaBridge	171:3a7713b1edbc	2084
AnnaBridge	171:3a7713b1edbc	2085	*descriptor_l1 &= SECTION_AP_MASK;
AnnaBridge	171:3a7713b1edbc	2086	*descriptor_l1 \|= (ap & 0x3) << SECTION_AP_SHIFT;
AnnaBridge	171:3a7713b1edbc	2087	*descriptor_l1 \|= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
AnnaBridge	171:3a7713b1edbc	2088
AnnaBridge	171:3a7713b1edbc	2089	return 0;
AnnaBridge	171:3a7713b1edbc	2090	}
AnnaBridge	171:3a7713b1edbc	2091
AnnaBridge	171:3a7713b1edbc	2092	/** \brief Set section shareability
AnnaBridge	171:3a7713b1edbc	2093
AnnaBridge	171:3a7713b1edbc	2094	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	171:3a7713b1edbc	2095	\param [in] s_bit Section shareability: NON_SHARED, SHARED
AnnaBridge	171:3a7713b1edbc	2096
AnnaBridge	171:3a7713b1edbc	2097	\return 0
AnnaBridge	171:3a7713b1edbc	2098	*/
AnnaBridge	171:3a7713b1edbc	2099	__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
AnnaBridge	171:3a7713b1edbc	2100	{
AnnaBridge	171:3a7713b1edbc	2101	*descriptor_l1 &= SECTION_S_MASK;
AnnaBridge	171:3a7713b1edbc	2102	*descriptor_l1 \|= ((s_bit & 0x1) << SECTION_S_SHIFT);
AnnaBridge	171:3a7713b1edbc	2103	return 0;
AnnaBridge	171:3a7713b1edbc	2104	}
AnnaBridge	171:3a7713b1edbc	2105
AnnaBridge	171:3a7713b1edbc	2106	/** \brief Set section Global attribute
AnnaBridge	171:3a7713b1edbc	2107
AnnaBridge	171:3a7713b1edbc	2108	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	171:3a7713b1edbc	2109	\param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
AnnaBridge	171:3a7713b1edbc	2110
AnnaBridge	171:3a7713b1edbc	2111	\return 0
AnnaBridge	171:3a7713b1edbc	2112	*/
AnnaBridge	171:3a7713b1edbc	2113	__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
AnnaBridge	171:3a7713b1edbc	2114	{
AnnaBridge	171:3a7713b1edbc	2115	*descriptor_l1 &= SECTION_NG_MASK;
AnnaBridge	171:3a7713b1edbc	2116	*descriptor_l1 \|= ((g_bit & 0x1) << SECTION_NG_SHIFT);
AnnaBridge	171:3a7713b1edbc	2117	return 0;
AnnaBridge	171:3a7713b1edbc	2118	}
AnnaBridge	171:3a7713b1edbc	2119
AnnaBridge	171:3a7713b1edbc	2120	/** \brief Set section Security attribute
AnnaBridge	171:3a7713b1edbc	2121
AnnaBridge	171:3a7713b1edbc	2122	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	171:3a7713b1edbc	2123	\param [in] s_bit Section Security attribute: SECURE, NON_SECURE
AnnaBridge	171:3a7713b1edbc	2124
AnnaBridge	171:3a7713b1edbc	2125	\return 0
AnnaBridge	171:3a7713b1edbc	2126	*/
AnnaBridge	171:3a7713b1edbc	2127	__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge	171:3a7713b1edbc	2128	{
AnnaBridge	171:3a7713b1edbc	2129	*descriptor_l1 &= SECTION_NS_MASK;
AnnaBridge	171:3a7713b1edbc	2130	*descriptor_l1 \|= ((s_bit & 0x1) << SECTION_NS_SHIFT);
AnnaBridge	171:3a7713b1edbc	2131	return 0;
AnnaBridge	171:3a7713b1edbc	2132	}
AnnaBridge	171:3a7713b1edbc	2133
AnnaBridge	171:3a7713b1edbc	2134	/* Page 4k or 64k */
AnnaBridge	171:3a7713b1edbc	2135	/** \brief Set 4k/64k page execution-never attribute
AnnaBridge	171:3a7713b1edbc	2136
AnnaBridge	171:3a7713b1edbc	2137	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	171:3a7713b1edbc	2138	\param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge	171:3a7713b1edbc	2139	\param [in] page Page size: PAGE_4k, PAGE_64k,
AnnaBridge	171:3a7713b1edbc	2140
AnnaBridge	171:3a7713b1edbc	2141	\return 0
AnnaBridge	171:3a7713b1edbc	2142	*/
AnnaBridge	171:3a7713b1edbc	2143	__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
AnnaBridge	171:3a7713b1edbc	2144	{
AnnaBridge	171:3a7713b1edbc	2145	if (page == PAGE_4k)
AnnaBridge	171:3a7713b1edbc	2146	{
AnnaBridge	171:3a7713b1edbc	2147	*descriptor_l2 &= PAGE_XN_4K_MASK;
AnnaBridge	171:3a7713b1edbc	2148	*descriptor_l2 \|= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
AnnaBridge	171:3a7713b1edbc	2149	}
AnnaBridge	171:3a7713b1edbc	2150	else
AnnaBridge	171:3a7713b1edbc	2151	{
AnnaBridge	171:3a7713b1edbc	2152	*descriptor_l2 &= PAGE_XN_64K_MASK;
AnnaBridge	171:3a7713b1edbc	2153	*descriptor_l2 \|= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
AnnaBridge	171:3a7713b1edbc	2154	}
AnnaBridge	171:3a7713b1edbc	2155	return 0;
AnnaBridge	171:3a7713b1edbc	2156	}
AnnaBridge	171:3a7713b1edbc	2157
AnnaBridge	171:3a7713b1edbc	2158	/** \brief Set 4k/64k page domain
AnnaBridge	171:3a7713b1edbc	2159
AnnaBridge	171:3a7713b1edbc	2160	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	171:3a7713b1edbc	2161	\param [in] domain Page domain
AnnaBridge	171:3a7713b1edbc	2162
AnnaBridge	171:3a7713b1edbc	2163	\return 0
AnnaBridge	171:3a7713b1edbc	2164	*/
AnnaBridge	171:3a7713b1edbc	2165	__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge	171:3a7713b1edbc	2166	{
AnnaBridge	171:3a7713b1edbc	2167	*descriptor_l1 &= PAGE_DOMAIN_MASK;
AnnaBridge	171:3a7713b1edbc	2168	*descriptor_l1 \|= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
AnnaBridge	171:3a7713b1edbc	2169	return 0;
AnnaBridge	171:3a7713b1edbc	2170	}
AnnaBridge	171:3a7713b1edbc	2171
AnnaBridge	171:3a7713b1edbc	2172	/** \brief Set 4k/64k page parity check
AnnaBridge	171:3a7713b1edbc	2173
AnnaBridge	171:3a7713b1edbc	2174	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	171:3a7713b1edbc	2175	\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge	171:3a7713b1edbc	2176
AnnaBridge	171:3a7713b1edbc	2177	\return 0
AnnaBridge	171:3a7713b1edbc	2178	*/
AnnaBridge	171:3a7713b1edbc	2179	__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge	171:3a7713b1edbc	2180	{
AnnaBridge	171:3a7713b1edbc	2181	*descriptor_l1 &= SECTION_P_MASK;
AnnaBridge	171:3a7713b1edbc	2182	*descriptor_l1 \|= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge	171:3a7713b1edbc	2183	return 0;
AnnaBridge	171:3a7713b1edbc	2184	}
AnnaBridge	171:3a7713b1edbc	2185
AnnaBridge	171:3a7713b1edbc	2186	/** \brief Set 4k/64k page access privileges
AnnaBridge	171:3a7713b1edbc	2187
AnnaBridge	171:3a7713b1edbc	2188	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	171:3a7713b1edbc	2189	\param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge	171:3a7713b1edbc	2190	\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge	171:3a7713b1edbc	2191	\param [in] afe Access flag enable
AnnaBridge	171:3a7713b1edbc	2192
AnnaBridge	171:3a7713b1edbc	2193	\return 0
AnnaBridge	171:3a7713b1edbc	2194	*/
AnnaBridge	171:3a7713b1edbc	2195	__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge	171:3a7713b1edbc	2196	{
AnnaBridge	171:3a7713b1edbc	2197	uint32_t ap = 0;
AnnaBridge	171:3a7713b1edbc	2198
AnnaBridge	171:3a7713b1edbc	2199	if (afe == 0) { //full access
AnnaBridge	171:3a7713b1edbc	2200	if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge	171:3a7713b1edbc	2201	else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge	171:3a7713b1edbc	2202	else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge	171:3a7713b1edbc	2203	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge	171:3a7713b1edbc	2204	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge	171:3a7713b1edbc	2205	else if ((priv == READ) && (user == READ)) { ap = 0x6; }
AnnaBridge	171:3a7713b1edbc	2206	}
AnnaBridge	171:3a7713b1edbc	2207
AnnaBridge	171:3a7713b1edbc	2208	else { //Simplified access
AnnaBridge	171:3a7713b1edbc	2209	if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge	171:3a7713b1edbc	2210	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge	171:3a7713b1edbc	2211	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge	171:3a7713b1edbc	2212	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge	171:3a7713b1edbc	2213	}
AnnaBridge	171:3a7713b1edbc	2214
AnnaBridge	171:3a7713b1edbc	2215	*descriptor_l2 &= PAGE_AP_MASK;
AnnaBridge	171:3a7713b1edbc	2216	*descriptor_l2 \|= (ap & 0x3) << PAGE_AP_SHIFT;
AnnaBridge	171:3a7713b1edbc	2217	*descriptor_l2 \|= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
AnnaBridge	171:3a7713b1edbc	2218
AnnaBridge	171:3a7713b1edbc	2219	return 0;
AnnaBridge	171:3a7713b1edbc	2220	}
AnnaBridge	171:3a7713b1edbc	2221
AnnaBridge	171:3a7713b1edbc	2222	/** \brief Set 4k/64k page shareability
AnnaBridge	171:3a7713b1edbc	2223
AnnaBridge	171:3a7713b1edbc	2224	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	171:3a7713b1edbc	2225	\param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
AnnaBridge	171:3a7713b1edbc	2226
AnnaBridge	171:3a7713b1edbc	2227	\return 0
AnnaBridge	171:3a7713b1edbc	2228	*/
AnnaBridge	171:3a7713b1edbc	2229	__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
AnnaBridge	171:3a7713b1edbc	2230	{
AnnaBridge	171:3a7713b1edbc	2231	*descriptor_l2 &= PAGE_S_MASK;
AnnaBridge	171:3a7713b1edbc	2232	*descriptor_l2 \|= ((s_bit & 0x1) << PAGE_S_SHIFT);
AnnaBridge	171:3a7713b1edbc	2233	return 0;
AnnaBridge	171:3a7713b1edbc	2234	}
AnnaBridge	171:3a7713b1edbc	2235
AnnaBridge	171:3a7713b1edbc	2236	/** \brief Set 4k/64k page Global attribute
AnnaBridge	171:3a7713b1edbc	2237
AnnaBridge	171:3a7713b1edbc	2238	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	171:3a7713b1edbc	2239	\param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
AnnaBridge	171:3a7713b1edbc	2240
AnnaBridge	171:3a7713b1edbc	2241	\return 0
AnnaBridge	171:3a7713b1edbc	2242	*/
AnnaBridge	171:3a7713b1edbc	2243	__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
AnnaBridge	171:3a7713b1edbc	2244	{
AnnaBridge	171:3a7713b1edbc	2245	*descriptor_l2 &= PAGE_NG_MASK;
AnnaBridge	171:3a7713b1edbc	2246	*descriptor_l2 \|= ((g_bit & 0x1) << PAGE_NG_SHIFT);
AnnaBridge	171:3a7713b1edbc	2247	return 0;
AnnaBridge	171:3a7713b1edbc	2248	}
AnnaBridge	171:3a7713b1edbc	2249
AnnaBridge	171:3a7713b1edbc	2250	/** \brief Set 4k/64k page Security attribute
AnnaBridge	171:3a7713b1edbc	2251
AnnaBridge	171:3a7713b1edbc	2252	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	171:3a7713b1edbc	2253	\param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
AnnaBridge	171:3a7713b1edbc	2254
AnnaBridge	171:3a7713b1edbc	2255	\return 0
AnnaBridge	171:3a7713b1edbc	2256	*/
AnnaBridge	171:3a7713b1edbc	2257	__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge	171:3a7713b1edbc	2258	{
AnnaBridge	171:3a7713b1edbc	2259	*descriptor_l1 &= PAGE_NS_MASK;
AnnaBridge	171:3a7713b1edbc	2260	*descriptor_l1 \|= ((s_bit & 0x1) << PAGE_NS_SHIFT);
AnnaBridge	171:3a7713b1edbc	2261	return 0;
AnnaBridge	171:3a7713b1edbc	2262	}
AnnaBridge	171:3a7713b1edbc	2263
AnnaBridge	171:3a7713b1edbc	2264	/** \brief Set Section memory attributes
AnnaBridge	171:3a7713b1edbc	2265
AnnaBridge	171:3a7713b1edbc	2266	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	171:3a7713b1edbc	2267	\param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge	171:3a7713b1edbc	2268	\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge	171:3a7713b1edbc	2269	\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge	171:3a7713b1edbc	2270
AnnaBridge	171:3a7713b1edbc	2271	\return 0
AnnaBridge	171:3a7713b1edbc	2272	*/
AnnaBridge	171:3a7713b1edbc	2273	__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
AnnaBridge	171:3a7713b1edbc	2274	{
AnnaBridge	171:3a7713b1edbc	2275	*descriptor_l1 &= SECTION_TEXCB_MASK;
AnnaBridge	171:3a7713b1edbc	2276
AnnaBridge	171:3a7713b1edbc	2277	if (STRONGLY_ORDERED == mem)
AnnaBridge	171:3a7713b1edbc	2278	{
AnnaBridge	171:3a7713b1edbc	2279	return 0;
AnnaBridge	171:3a7713b1edbc	2280	}
AnnaBridge	171:3a7713b1edbc	2281	else if (SHARED_DEVICE == mem)
AnnaBridge	171:3a7713b1edbc	2282	{
AnnaBridge	171:3a7713b1edbc	2283	*descriptor_l1 \|= (1 << SECTION_B_SHIFT);
AnnaBridge	171:3a7713b1edbc	2284	}
AnnaBridge	171:3a7713b1edbc	2285	else if (NON_SHARED_DEVICE == mem)
AnnaBridge	171:3a7713b1edbc	2286	{
AnnaBridge	171:3a7713b1edbc	2287	*descriptor_l1 \|= (1 << SECTION_TEX1_SHIFT);
AnnaBridge	171:3a7713b1edbc	2288	}
AnnaBridge	171:3a7713b1edbc	2289	else if (NORMAL == mem)
AnnaBridge	171:3a7713b1edbc	2290	{
AnnaBridge	171:3a7713b1edbc	2291	*descriptor_l1 \|= 1 << SECTION_TEX2_SHIFT;
AnnaBridge	171:3a7713b1edbc	2292	switch(inner)
AnnaBridge	171:3a7713b1edbc	2293	{
AnnaBridge	171:3a7713b1edbc	2294	case NON_CACHEABLE:
AnnaBridge	171:3a7713b1edbc	2295	break;
AnnaBridge	171:3a7713b1edbc	2296	case WB_WA:
AnnaBridge	171:3a7713b1edbc	2297	*descriptor_l1 \|= (1 << SECTION_B_SHIFT);
AnnaBridge	171:3a7713b1edbc	2298	break;
AnnaBridge	171:3a7713b1edbc	2299	case WT:
AnnaBridge	171:3a7713b1edbc	2300	*descriptor_l1 \|= 1 << SECTION_C_SHIFT;
AnnaBridge	171:3a7713b1edbc	2301	break;
AnnaBridge	171:3a7713b1edbc	2302	case WB_NO_WA:
AnnaBridge	171:3a7713b1edbc	2303	*descriptor_l1 \|= (1 << SECTION_B_SHIFT) \| (1 << SECTION_C_SHIFT);
AnnaBridge	171:3a7713b1edbc	2304	break;
AnnaBridge	171:3a7713b1edbc	2305	}
AnnaBridge	171:3a7713b1edbc	2306	switch(outer)
AnnaBridge	171:3a7713b1edbc	2307	{
AnnaBridge	171:3a7713b1edbc	2308	case NON_CACHEABLE:
AnnaBridge	171:3a7713b1edbc	2309	break;
AnnaBridge	171:3a7713b1edbc	2310	case WB_WA:
AnnaBridge	171:3a7713b1edbc	2311	*descriptor_l1 \|= (1 << SECTION_TEX0_SHIFT);
AnnaBridge	171:3a7713b1edbc	2312	break;
AnnaBridge	171:3a7713b1edbc	2313	case WT:
AnnaBridge	171:3a7713b1edbc	2314	*descriptor_l1 \|= 1 << SECTION_TEX1_SHIFT;
AnnaBridge	171:3a7713b1edbc	2315	break;
AnnaBridge	171:3a7713b1edbc	2316	case WB_NO_WA:
AnnaBridge	171:3a7713b1edbc	2317	*descriptor_l1 \|= (1 << SECTION_TEX0_SHIFT) \| (1 << SECTION_TEX0_SHIFT);
AnnaBridge	171:3a7713b1edbc	2318	break;
AnnaBridge	171:3a7713b1edbc	2319	}
AnnaBridge	171:3a7713b1edbc	2320	}
AnnaBridge	171:3a7713b1edbc	2321	return 0;
AnnaBridge	171:3a7713b1edbc	2322	}
AnnaBridge	171:3a7713b1edbc	2323
AnnaBridge	171:3a7713b1edbc	2324	/** \brief Set 4k/64k page memory attributes
AnnaBridge	171:3a7713b1edbc	2325
AnnaBridge	171:3a7713b1edbc	2326	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	171:3a7713b1edbc	2327	\param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge	171:3a7713b1edbc	2328	\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge	171:3a7713b1edbc	2329	\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge	171:3a7713b1edbc	2330	\param [in] page Page size
AnnaBridge	171:3a7713b1edbc	2331
AnnaBridge	171:3a7713b1edbc	2332	\return 0
AnnaBridge	171:3a7713b1edbc	2333	*/
AnnaBridge	171:3a7713b1edbc	2334	__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
AnnaBridge	171:3a7713b1edbc	2335	{
AnnaBridge	171:3a7713b1edbc	2336	*descriptor_l2 &= PAGE_4K_TEXCB_MASK;
AnnaBridge	171:3a7713b1edbc	2337
AnnaBridge	171:3a7713b1edbc	2338	if (page == PAGE_64k)
AnnaBridge	171:3a7713b1edbc	2339	{
AnnaBridge	171:3a7713b1edbc	2340	//same as section
AnnaBridge	171:3a7713b1edbc	2341	MMU_MemorySection(descriptor_l2, mem, outer, inner);
AnnaBridge	171:3a7713b1edbc	2342	}
AnnaBridge	171:3a7713b1edbc	2343	else
AnnaBridge	171:3a7713b1edbc	2344	{
AnnaBridge	171:3a7713b1edbc	2345	if (STRONGLY_ORDERED == mem)
AnnaBridge	171:3a7713b1edbc	2346	{
AnnaBridge	171:3a7713b1edbc	2347	return 0;
AnnaBridge	171:3a7713b1edbc	2348	}
AnnaBridge	171:3a7713b1edbc	2349	else if (SHARED_DEVICE == mem)
AnnaBridge	171:3a7713b1edbc	2350	{
AnnaBridge	171:3a7713b1edbc	2351	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT);
AnnaBridge	171:3a7713b1edbc	2352	}
AnnaBridge	171:3a7713b1edbc	2353	else if (NON_SHARED_DEVICE == mem)
AnnaBridge	171:3a7713b1edbc	2354	{
AnnaBridge	171:3a7713b1edbc	2355	*descriptor_l2 \|= (1 << PAGE_4K_TEX1_SHIFT);
AnnaBridge	171:3a7713b1edbc	2356	}
AnnaBridge	171:3a7713b1edbc	2357	else if (NORMAL == mem)
AnnaBridge	171:3a7713b1edbc	2358	{
AnnaBridge	171:3a7713b1edbc	2359	*descriptor_l2 \|= 1 << PAGE_4K_TEX2_SHIFT;
AnnaBridge	171:3a7713b1edbc	2360	switch(inner)
AnnaBridge	171:3a7713b1edbc	2361	{
AnnaBridge	171:3a7713b1edbc	2362	case NON_CACHEABLE:
AnnaBridge	171:3a7713b1edbc	2363	break;
AnnaBridge	171:3a7713b1edbc	2364	case WB_WA:
AnnaBridge	171:3a7713b1edbc	2365	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT);
AnnaBridge	171:3a7713b1edbc	2366	break;
AnnaBridge	171:3a7713b1edbc	2367	case WT:
AnnaBridge	171:3a7713b1edbc	2368	*descriptor_l2 \|= 1 << PAGE_4K_C_SHIFT;
AnnaBridge	171:3a7713b1edbc	2369	break;
AnnaBridge	171:3a7713b1edbc	2370	case WB_NO_WA:
AnnaBridge	171:3a7713b1edbc	2371	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT) \| (1 << PAGE_4K_C_SHIFT);
AnnaBridge	171:3a7713b1edbc	2372	break;
AnnaBridge	171:3a7713b1edbc	2373	}
AnnaBridge	171:3a7713b1edbc	2374	switch(outer)
AnnaBridge	171:3a7713b1edbc	2375	{
AnnaBridge	171:3a7713b1edbc	2376	case NON_CACHEABLE:
AnnaBridge	171:3a7713b1edbc	2377	break;
AnnaBridge	171:3a7713b1edbc	2378	case WB_WA:
AnnaBridge	171:3a7713b1edbc	2379	*descriptor_l2 \|= (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge	171:3a7713b1edbc	2380	break;
AnnaBridge	171:3a7713b1edbc	2381	case WT:
AnnaBridge	171:3a7713b1edbc	2382	*descriptor_l2 \|= 1 << PAGE_4K_TEX1_SHIFT;
AnnaBridge	171:3a7713b1edbc	2383	break;
AnnaBridge	171:3a7713b1edbc	2384	case WB_NO_WA:
AnnaBridge	171:3a7713b1edbc	2385	*descriptor_l2 \|= (1 << PAGE_4K_TEX0_SHIFT) \| (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge	171:3a7713b1edbc	2386	break;
AnnaBridge	171:3a7713b1edbc	2387	}
AnnaBridge	171:3a7713b1edbc	2388	}
AnnaBridge	171:3a7713b1edbc	2389	}
AnnaBridge	171:3a7713b1edbc	2390
AnnaBridge	171:3a7713b1edbc	2391	return 0;
AnnaBridge	171:3a7713b1edbc	2392	}
AnnaBridge	171:3a7713b1edbc	2393
AnnaBridge	171:3a7713b1edbc	2394	/** \brief Create a L1 section descriptor
AnnaBridge	171:3a7713b1edbc	2395
AnnaBridge	171:3a7713b1edbc	2396	\param [out] descriptor L1 descriptor
AnnaBridge	171:3a7713b1edbc	2397	\param [in] reg Section attributes
AnnaBridge	171:3a7713b1edbc	2398
AnnaBridge	171:3a7713b1edbc	2399	\return 0
AnnaBridge	171:3a7713b1edbc	2400	*/
AnnaBridge	171:3a7713b1edbc	2401	__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
AnnaBridge	171:3a7713b1edbc	2402	{
AnnaBridge	171:3a7713b1edbc	2403	*descriptor = 0;
AnnaBridge	171:3a7713b1edbc	2404
AnnaBridge	171:3a7713b1edbc	2405	MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
AnnaBridge	171:3a7713b1edbc	2406	MMU_XNSection(descriptor,reg.xn_t);
AnnaBridge	171:3a7713b1edbc	2407	MMU_DomainSection(descriptor, reg.domain);
AnnaBridge	171:3a7713b1edbc	2408	MMU_PSection(descriptor, reg.e_t);
AnnaBridge	171:3a7713b1edbc	2409	MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
AnnaBridge	171:3a7713b1edbc	2410	MMU_SharedSection(descriptor,reg.sh_t);
AnnaBridge	171:3a7713b1edbc	2411	MMU_GlobalSection(descriptor,reg.g_t);
AnnaBridge	171:3a7713b1edbc	2412	MMU_SecureSection(descriptor,reg.sec_t);
AnnaBridge	171:3a7713b1edbc	2413	*descriptor &= SECTION_MASK;
AnnaBridge	171:3a7713b1edbc	2414	*descriptor \|= SECTION_DESCRIPTOR;
AnnaBridge	171:3a7713b1edbc	2415
AnnaBridge	171:3a7713b1edbc	2416	return 0;
AnnaBridge	171:3a7713b1edbc	2417	}
AnnaBridge	171:3a7713b1edbc	2418
AnnaBridge	171:3a7713b1edbc	2419
AnnaBridge	171:3a7713b1edbc	2420	/** \brief Create a L1 and L2 4k/64k page descriptor
AnnaBridge	171:3a7713b1edbc	2421
AnnaBridge	171:3a7713b1edbc	2422	\param [out] descriptor L1 descriptor
AnnaBridge	171:3a7713b1edbc	2423	\param [out] descriptor2 L2 descriptor
AnnaBridge	171:3a7713b1edbc	2424	\param [in] reg 4k/64k page attributes
AnnaBridge	171:3a7713b1edbc	2425
AnnaBridge	171:3a7713b1edbc	2426	\return 0
AnnaBridge	171:3a7713b1edbc	2427	*/
AnnaBridge	171:3a7713b1edbc	2428	__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t descriptor, uint32_t descriptor2, mmu_region_attributes_Type reg)
AnnaBridge	171:3a7713b1edbc	2429	{
AnnaBridge	171:3a7713b1edbc	2430	*descriptor = 0;
AnnaBridge	171:3a7713b1edbc	2431	*descriptor2 = 0;
AnnaBridge	171:3a7713b1edbc	2432
AnnaBridge	171:3a7713b1edbc	2433	switch (reg.rg_t)
AnnaBridge	171:3a7713b1edbc	2434	{
AnnaBridge	171:3a7713b1edbc	2435	case PAGE_4k:
AnnaBridge	171:3a7713b1edbc	2436	MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
AnnaBridge	171:3a7713b1edbc	2437	MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
AnnaBridge	171:3a7713b1edbc	2438	MMU_DomainPage(descriptor, reg.domain);
AnnaBridge	171:3a7713b1edbc	2439	MMU_PPage(descriptor, reg.e_t);
AnnaBridge	171:3a7713b1edbc	2440	MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge	171:3a7713b1edbc	2441	MMU_SharedPage(descriptor2,reg.sh_t);
AnnaBridge	171:3a7713b1edbc	2442	MMU_GlobalPage(descriptor2,reg.g_t);
AnnaBridge	171:3a7713b1edbc	2443	MMU_SecurePage(descriptor,reg.sec_t);
AnnaBridge	171:3a7713b1edbc	2444	*descriptor &= PAGE_L1_MASK;
AnnaBridge	171:3a7713b1edbc	2445	*descriptor \|= PAGE_L1_DESCRIPTOR;
AnnaBridge	171:3a7713b1edbc	2446	*descriptor2 &= PAGE_L2_4K_MASK;
AnnaBridge	171:3a7713b1edbc	2447	*descriptor2 \|= PAGE_L2_4K_DESC;
AnnaBridge	171:3a7713b1edbc	2448	break;
AnnaBridge	171:3a7713b1edbc	2449
AnnaBridge	171:3a7713b1edbc	2450	case PAGE_64k:
AnnaBridge	171:3a7713b1edbc	2451	MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
AnnaBridge	171:3a7713b1edbc	2452	MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
AnnaBridge	171:3a7713b1edbc	2453	MMU_DomainPage(descriptor, reg.domain);
AnnaBridge	171:3a7713b1edbc	2454	MMU_PPage(descriptor, reg.e_t);
AnnaBridge	171:3a7713b1edbc	2455	MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge	171:3a7713b1edbc	2456	MMU_SharedPage(descriptor2,reg.sh_t);
AnnaBridge	171:3a7713b1edbc	2457	MMU_GlobalPage(descriptor2,reg.g_t);
AnnaBridge	171:3a7713b1edbc	2458	MMU_SecurePage(descriptor,reg.sec_t);
AnnaBridge	171:3a7713b1edbc	2459	*descriptor &= PAGE_L1_MASK;
AnnaBridge	171:3a7713b1edbc	2460	*descriptor \|= PAGE_L1_DESCRIPTOR;
AnnaBridge	171:3a7713b1edbc	2461	*descriptor2 &= PAGE_L2_64K_MASK;
AnnaBridge	171:3a7713b1edbc	2462	*descriptor2 \|= PAGE_L2_64K_DESC;
AnnaBridge	171:3a7713b1edbc	2463	break;
AnnaBridge	171:3a7713b1edbc	2464
AnnaBridge	171:3a7713b1edbc	2465	case SECTION:
AnnaBridge	171:3a7713b1edbc	2466	//error
AnnaBridge	171:3a7713b1edbc	2467	break;
AnnaBridge	171:3a7713b1edbc	2468	}
AnnaBridge	171:3a7713b1edbc	2469
AnnaBridge	171:3a7713b1edbc	2470	return 0;
AnnaBridge	171:3a7713b1edbc	2471	}
AnnaBridge	171:3a7713b1edbc	2472
AnnaBridge	171:3a7713b1edbc	2473	/** \brief Create a 1MB Section
AnnaBridge	171:3a7713b1edbc	2474
AnnaBridge	171:3a7713b1edbc	2475	\param [in] ttb Translation table base address
AnnaBridge	171:3a7713b1edbc	2476	\param [in] base_address Section base address
AnnaBridge	171:3a7713b1edbc	2477	\param [in] count Number of sections to create
AnnaBridge	171:3a7713b1edbc	2478	\param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge	171:3a7713b1edbc	2479
AnnaBridge	171:3a7713b1edbc	2480	*/
AnnaBridge	171:3a7713b1edbc	2481	__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
AnnaBridge	171:3a7713b1edbc	2482	{
AnnaBridge	171:3a7713b1edbc	2483	uint32_t offset;
AnnaBridge	171:3a7713b1edbc	2484	uint32_t entry;
AnnaBridge	171:3a7713b1edbc	2485	uint32_t i;
AnnaBridge	171:3a7713b1edbc	2486
AnnaBridge	171:3a7713b1edbc	2487	offset = base_address >> 20;
AnnaBridge	171:3a7713b1edbc	2488	entry = (base_address & 0xFFF00000) \| descriptor_l1;
AnnaBridge	171:3a7713b1edbc	2489
AnnaBridge	171:3a7713b1edbc	2490	//4 bytes aligned
AnnaBridge	171:3a7713b1edbc	2491	ttb = ttb + offset;
AnnaBridge	171:3a7713b1edbc	2492
AnnaBridge	171:3a7713b1edbc	2493	for (i = 0; i < count; i++ )
AnnaBridge	171:3a7713b1edbc	2494	{
AnnaBridge	171:3a7713b1edbc	2495	//4 bytes aligned
AnnaBridge	171:3a7713b1edbc	2496	*ttb++ = entry;
AnnaBridge	171:3a7713b1edbc	2497	entry += OFFSET_1M;
AnnaBridge	171:3a7713b1edbc	2498	}
AnnaBridge	171:3a7713b1edbc	2499	}
AnnaBridge	171:3a7713b1edbc	2500
AnnaBridge	171:3a7713b1edbc	2501	/** \brief Create a 4k page entry
AnnaBridge	171:3a7713b1edbc	2502
AnnaBridge	171:3a7713b1edbc	2503	\param [in] ttb L1 table base address
AnnaBridge	171:3a7713b1edbc	2504	\param [in] base_address 4k base address
AnnaBridge	171:3a7713b1edbc	2505	\param [in] count Number of 4k pages to create
AnnaBridge	171:3a7713b1edbc	2506	\param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge	171:3a7713b1edbc	2507	\param [in] ttb_l2 L2 table base address
AnnaBridge	171:3a7713b1edbc	2508	\param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge	171:3a7713b1edbc	2509
AnnaBridge	171:3a7713b1edbc	2510	*/
AnnaBridge	171:3a7713b1edbc	2511	__STATIC_INLINE void MMU_TTPage4k(uint32_t ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t ttb_l2, uint32_t descriptor_l2 )
AnnaBridge	171:3a7713b1edbc	2512	{
AnnaBridge	171:3a7713b1edbc	2513
AnnaBridge	171:3a7713b1edbc	2514	uint32_t offset, offset2;
AnnaBridge	171:3a7713b1edbc	2515	uint32_t entry, entry2;
AnnaBridge	171:3a7713b1edbc	2516	uint32_t i;
AnnaBridge	171:3a7713b1edbc	2517
AnnaBridge	171:3a7713b1edbc	2518	offset = base_address >> 20;
AnnaBridge	171:3a7713b1edbc	2519	entry = ((int)ttb_l2 & 0xFFFFFC00) \| descriptor_l1;
AnnaBridge	171:3a7713b1edbc	2520
AnnaBridge	171:3a7713b1edbc	2521	//4 bytes aligned
AnnaBridge	171:3a7713b1edbc	2522	ttb += offset;
AnnaBridge	171:3a7713b1edbc	2523	//create l1_entry
AnnaBridge	171:3a7713b1edbc	2524	*ttb = entry;
AnnaBridge	171:3a7713b1edbc	2525
AnnaBridge	171:3a7713b1edbc	2526	offset2 = (base_address & 0xff000) >> 12;
AnnaBridge	171:3a7713b1edbc	2527	ttb_l2 += offset2;
AnnaBridge	171:3a7713b1edbc	2528	entry2 = (base_address & 0xFFFFF000) \| descriptor_l2;
AnnaBridge	171:3a7713b1edbc	2529	for (i = 0; i < count; i++ )
AnnaBridge	171:3a7713b1edbc	2530	{
AnnaBridge	171:3a7713b1edbc	2531	//4 bytes aligned
AnnaBridge	171:3a7713b1edbc	2532	*ttb_l2++ = entry2;
AnnaBridge	171:3a7713b1edbc	2533	entry2 += OFFSET_4K;
AnnaBridge	171:3a7713b1edbc	2534	}
AnnaBridge	171:3a7713b1edbc	2535	}
AnnaBridge	171:3a7713b1edbc	2536
AnnaBridge	171:3a7713b1edbc	2537	/** \brief Create a 64k page entry
AnnaBridge	171:3a7713b1edbc	2538
AnnaBridge	171:3a7713b1edbc	2539	\param [in] ttb L1 table base address
AnnaBridge	171:3a7713b1edbc	2540	\param [in] base_address 64k base address
AnnaBridge	171:3a7713b1edbc	2541	\param [in] count Number of 64k pages to create
AnnaBridge	171:3a7713b1edbc	2542	\param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge	171:3a7713b1edbc	2543	\param [in] ttb_l2 L2 table base address
AnnaBridge	171:3a7713b1edbc	2544	\param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge	171:3a7713b1edbc	2545
AnnaBridge	171:3a7713b1edbc	2546	*/
AnnaBridge	171:3a7713b1edbc	2547	__STATIC_INLINE void MMU_TTPage64k(uint32_t ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t ttb_l2, uint32_t descriptor_l2 )
AnnaBridge	171:3a7713b1edbc	2548	{
AnnaBridge	171:3a7713b1edbc	2549	uint32_t offset, offset2;
AnnaBridge	171:3a7713b1edbc	2550	uint32_t entry, entry2;
AnnaBridge	171:3a7713b1edbc	2551	uint32_t i,j;
AnnaBridge	171:3a7713b1edbc	2552
AnnaBridge	171:3a7713b1edbc	2553
AnnaBridge	171:3a7713b1edbc	2554	offset = base_address >> 20;
AnnaBridge	171:3a7713b1edbc	2555	entry = ((int)ttb_l2 & 0xFFFFFC00) \| descriptor_l1;
AnnaBridge	171:3a7713b1edbc	2556
AnnaBridge	171:3a7713b1edbc	2557	//4 bytes aligned
AnnaBridge	171:3a7713b1edbc	2558	ttb += offset;
AnnaBridge	171:3a7713b1edbc	2559	//create l1_entry
AnnaBridge	171:3a7713b1edbc	2560	*ttb = entry;
AnnaBridge	171:3a7713b1edbc	2561
AnnaBridge	171:3a7713b1edbc	2562	offset2 = (base_address & 0xff000) >> 12;
AnnaBridge	171:3a7713b1edbc	2563	ttb_l2 += offset2;
AnnaBridge	171:3a7713b1edbc	2564	entry2 = (base_address & 0xFFFF0000) \| descriptor_l2;
AnnaBridge	171:3a7713b1edbc	2565	for (i = 0; i < count; i++ )
AnnaBridge	171:3a7713b1edbc	2566	{
AnnaBridge	171:3a7713b1edbc	2567	//create 16 entries
AnnaBridge	171:3a7713b1edbc	2568	for (j = 0; j < 16; j++)
AnnaBridge	171:3a7713b1edbc	2569	{
AnnaBridge	171:3a7713b1edbc	2570	//4 bytes aligned
AnnaBridge	171:3a7713b1edbc	2571	*ttb_l2++ = entry2;
AnnaBridge	171:3a7713b1edbc	2572	}
AnnaBridge	171:3a7713b1edbc	2573	entry2 += OFFSET_64K;
AnnaBridge	171:3a7713b1edbc	2574	}
AnnaBridge	171:3a7713b1edbc	2575	}
AnnaBridge	171:3a7713b1edbc	2576
AnnaBridge	171:3a7713b1edbc	2577	/** \brief Enable MMU
AnnaBridge	171:3a7713b1edbc	2578	*/
AnnaBridge	171:3a7713b1edbc	2579	__STATIC_INLINE void MMU_Enable(void)
AnnaBridge	171:3a7713b1edbc	2580	{
AnnaBridge	171:3a7713b1edbc	2581	// Set M bit 0 to enable the MMU
AnnaBridge	171:3a7713b1edbc	2582	// Set AFE bit to enable simplified access permissions model
AnnaBridge	171:3a7713b1edbc	2583	// Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge	171:3a7713b1edbc	2584	__set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) \| 1 \| (1 << 29));
AnnaBridge	171:3a7713b1edbc	2585	__ISB();
AnnaBridge	171:3a7713b1edbc	2586	}
AnnaBridge	171:3a7713b1edbc	2587
AnnaBridge	171:3a7713b1edbc	2588	/** \brief Disable MMU
AnnaBridge	171:3a7713b1edbc	2589	*/
AnnaBridge	171:3a7713b1edbc	2590	__STATIC_INLINE void MMU_Disable(void)
AnnaBridge	171:3a7713b1edbc	2591	{
AnnaBridge	171:3a7713b1edbc	2592	// Clear M bit 0 to disable the MMU
AnnaBridge	171:3a7713b1edbc	2593	__set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge	171:3a7713b1edbc	2594	__ISB();
AnnaBridge	171:3a7713b1edbc	2595	}
AnnaBridge	171:3a7713b1edbc	2596
AnnaBridge	171:3a7713b1edbc	2597	/** \brief Invalidate entire unified TLB
AnnaBridge	171:3a7713b1edbc	2598	*/
AnnaBridge	171:3a7713b1edbc	2599
AnnaBridge	171:3a7713b1edbc	2600	__STATIC_INLINE void MMU_InvalidateTLB(void)
AnnaBridge	171:3a7713b1edbc	2601	{
AnnaBridge	171:3a7713b1edbc	2602	__set_TLBIALL(0);
AnnaBridge	171:3a7713b1edbc	2603	__DSB(); //ensure completion of the invalidation
AnnaBridge	171:3a7713b1edbc	2604	__ISB(); //ensure instruction fetch path sees new state
AnnaBridge	171:3a7713b1edbc	2605	}
AnnaBridge	171:3a7713b1edbc	2606
AnnaBridge	171:3a7713b1edbc	2607
AnnaBridge	171:3a7713b1edbc	2608	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	2609	}
AnnaBridge	171:3a7713b1edbc	2610	#endif
AnnaBridge	171:3a7713b1edbc	2611
AnnaBridge	171:3a7713b1edbc	2612	#endif /* __CORE_CA_H_DEPENDANT */
AnnaBridge	171:3a7713b1edbc	2613
AnnaBridge	171:3a7713b1edbc	2614	#endif /* __CMSIS_GENERIC */