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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_GR_LYCHEE/TOOLCHAIN_ARM_STD/MBRZA1LU.sct@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 161:aa5281ff4a02 1 #! armcc -E
AnnaBridge 161:aa5281ff4a02 2 ;**************************************************
AnnaBridge 161:aa5281ff4a02 3 ; Copyright (c) 2017 ARM Ltd. All rights reserved.
AnnaBridge 161:aa5281ff4a02 4 ;**************************************************
AnnaBridge 161:aa5281ff4a02 5
AnnaBridge 161:aa5281ff4a02 6 ; Scatter-file for RTX Example on Versatile Express
AnnaBridge 161:aa5281ff4a02 7
AnnaBridge 161:aa5281ff4a02 8 ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
AnnaBridge 161:aa5281ff4a02 9
AnnaBridge 171:3a7713b1edbc 10 #define __RAM_BASE 0x20000000
AnnaBridge 171:3a7713b1edbc 11 #define __RAM_SIZE 0x00300000
AnnaBridge 171:3a7713b1edbc 12 #define __NC_RAM_SIZE 0x00100000
AnnaBridge 171:3a7713b1edbc 13 #define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE)
AnnaBridge 171:3a7713b1edbc 14 #define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
AnnaBridge 171:3a7713b1edbc 15
AnnaBridge 171:3a7713b1edbc 16 #define __UND_STACK_SIZE 0x00000100
AnnaBridge 171:3a7713b1edbc 17 #define __SVC_STACK_SIZE 0x00008000
AnnaBridge 171:3a7713b1edbc 18 #define __ABT_STACK_SIZE 0x00000100
AnnaBridge 171:3a7713b1edbc 19 #define __FIQ_STACK_SIZE 0x00000100
AnnaBridge 171:3a7713b1edbc 20 #define __IRQ_STACK_SIZE 0x0000F000
AnnaBridge 171:3a7713b1edbc 21 #define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
AnnaBridge 171:3a7713b1edbc 22
AnnaBridge 171:3a7713b1edbc 23 #define __TTB_BASE 0x20000000
AnnaBridge 171:3a7713b1edbc 24 #define __TTB_SIZE 0x00004000
AnnaBridge 161:aa5281ff4a02 25
AnnaBridge 170:e95d10626187 26 #if !defined(MBED_APP_START)
AnnaBridge 170:e95d10626187 27 #define MBED_APP_START 0x18000000
AnnaBridge 170:e95d10626187 28 #endif
AnnaBridge 170:e95d10626187 29
AnnaBridge 170:e95d10626187 30 #if !defined(MBED_APP_SIZE)
AnnaBridge 170:e95d10626187 31 #define MBED_APP_SIZE 0x800000
AnnaBridge 170:e95d10626187 32 #endif
AnnaBridge 170:e95d10626187 33
AnnaBridge 161:aa5281ff4a02 34 LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM
AnnaBridge 161:aa5281ff4a02 35 {
AnnaBridge 161:aa5281ff4a02 36 TTB +0 EMPTY 0x4000
AnnaBridge 161:aa5281ff4a02 37 { } ; Level-1 Translation Table for MMU
AnnaBridge 161:aa5281ff4a02 38 }
AnnaBridge 161:aa5281ff4a02 39
AnnaBridge 170:e95d10626187 40 LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region
AnnaBridge 161:aa5281ff4a02 41 {
AnnaBridge 170:e95d10626187 42 #if (MBED_APP_START == 0x18000000)
AnnaBridge 170:e95d10626187 43 BOOT_LOADER_BEGIN MBED_APP_START FIXED
AnnaBridge 161:aa5281ff4a02 44 {
AnnaBridge 161:aa5281ff4a02 45 * (BOOT_LOADER)
AnnaBridge 161:aa5281ff4a02 46 }
AnnaBridge 161:aa5281ff4a02 47
AnnaBridge 170:e95d10626187 48 VECTORS (MBED_APP_START + 0x4000) FIXED
AnnaBridge 161:aa5281ff4a02 49 {
AnnaBridge 161:aa5281ff4a02 50 * (RESET, +FIRST) ; Vector table and other startup code
AnnaBridge 161:aa5281ff4a02 51 * (InRoot$$Sections) ; All (library) code that must be in a root region
AnnaBridge 161:aa5281ff4a02 52 * (+RO-CODE) ; Application RO code (.text)
AnnaBridge 161:aa5281ff4a02 53 }
AnnaBridge 170:e95d10626187 54 #else
AnnaBridge 170:e95d10626187 55 VECTORS MBED_APP_START FIXED
AnnaBridge 170:e95d10626187 56 {
AnnaBridge 170:e95d10626187 57 * (RESET, +FIRST) ; Vector table and other startup code
AnnaBridge 170:e95d10626187 58 * (InRoot$$Sections) ; All (library) code that must be in a root region
AnnaBridge 170:e95d10626187 59 * (+RO-CODE) ; Application RO code (.text)
AnnaBridge 170:e95d10626187 60 }
AnnaBridge 170:e95d10626187 61 #endif
AnnaBridge 161:aa5281ff4a02 62
AnnaBridge 161:aa5281ff4a02 63 RO_DATA +0
AnnaBridge 161:aa5281ff4a02 64 { * (+RO-DATA) } ; Application RO data (.constdata)
AnnaBridge 161:aa5281ff4a02 65
AnnaBridge 170:e95d10626187 66 RAM_CODE 0x20020000
AnnaBridge 170:e95d10626187 67 { * (RAM_CODE) } ; Application RAM_CODE
AnnaBridge 170:e95d10626187 68
AnnaBridge 171:3a7713b1edbc 69 RW_DATA +0 ALIGN 0x8
AnnaBridge 161:aa5281ff4a02 70 { * (+RW) } ; Application RW data (.data)
AnnaBridge 161:aa5281ff4a02 71
AnnaBridge 161:aa5281ff4a02 72 RW_IRAM1 +0 ALIGN 0x10
AnnaBridge 161:aa5281ff4a02 73 { * (+ZI) } ; Application ZI data (.bss)
AnnaBridge 161:aa5281ff4a02 74
AnnaBridge 172:65be27845400 75 ARM_LIB_HEAP +0 ALIGN 0x8
AnnaBridge 161:aa5281ff4a02 76 { * (HEAP) } ; Application heap area (HEAP)
AnnaBridge 161:aa5281ff4a02 77
AnnaBridge 161:aa5281ff4a02 78 ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
AnnaBridge 161:aa5281ff4a02 79 { }
AnnaBridge 161:aa5281ff4a02 80
AnnaBridge 161:aa5281ff4a02 81 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
AnnaBridge 161:aa5281ff4a02 82 ; RAM-NC : Internal non-cached RAM region
AnnaBridge 161:aa5281ff4a02 83 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
AnnaBridge 161:aa5281ff4a02 84
AnnaBridge 161:aa5281ff4a02 85 RW_DATA_NC __DATA_NC_BASE __NC_RAM_SIZE
AnnaBridge 161:aa5281ff4a02 86 { * (NC_DATA) } ; Application RW data Non cached area
AnnaBridge 161:aa5281ff4a02 87
AnnaBridge 161:aa5281ff4a02 88 ZI_DATA_NC +0
AnnaBridge 161:aa5281ff4a02 89 { * (NC_BSS) } ; Application ZI data Non cached area
AnnaBridge 161:aa5281ff4a02 90 }
AnnaBridge 161:aa5281ff4a02 91