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TARGET_FF_LPC546XX/TOOLCHAIN_GCC_ARM/fsl_spifi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 3 * Copyright 2016-2017 NXP
AnnaBridge 171:3a7713b1edbc 4 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 172:65be27845400 6 * SPDX-License-Identifier: BSD-3-Clause
AnnaBridge 171:3a7713b1edbc 7 */
AnnaBridge 171:3a7713b1edbc 8 #ifndef _FSL_SPIFI_H_
AnnaBridge 171:3a7713b1edbc 9 #define _FSL_SPIFI_H_
AnnaBridge 171:3a7713b1edbc 10
AnnaBridge 171:3a7713b1edbc 11 #include "fsl_common.h"
AnnaBridge 171:3a7713b1edbc 12
AnnaBridge 171:3a7713b1edbc 13 /*!
AnnaBridge 171:3a7713b1edbc 14 * @addtogroup spifi
AnnaBridge 171:3a7713b1edbc 15 * @{
AnnaBridge 171:3a7713b1edbc 16 */
AnnaBridge 171:3a7713b1edbc 17
AnnaBridge 171:3a7713b1edbc 18 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 19 * Definitions
AnnaBridge 171:3a7713b1edbc 20 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 21
AnnaBridge 171:3a7713b1edbc 22 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 23 /*@{*/
AnnaBridge 172:65be27845400 24 /*! @brief SPIFI driver version 2.0.2. */
AnnaBridge 172:65be27845400 25 #define FSL_SPIFI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
AnnaBridge 171:3a7713b1edbc 26 /*@}*/
AnnaBridge 171:3a7713b1edbc 27
AnnaBridge 171:3a7713b1edbc 28 /*! @brief Status structure of SPIFI.*/
AnnaBridge 171:3a7713b1edbc 29 enum _status_t
AnnaBridge 171:3a7713b1edbc 30 {
AnnaBridge 171:3a7713b1edbc 31 kStatus_SPIFI_Idle = MAKE_STATUS(kStatusGroup_SPIFI, 0), /*!< SPIFI is in idle state */
AnnaBridge 171:3a7713b1edbc 32 kStatus_SPIFI_Busy = MAKE_STATUS(kStatusGroup_SPIFI, 1), /*!< SPIFI is busy */
AnnaBridge 171:3a7713b1edbc 33 kStatus_SPIFI_Error = MAKE_STATUS(kStatusGroup_SPIFI, 2), /*!< Error occurred during SPIFI transfer */
AnnaBridge 171:3a7713b1edbc 34 };
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /*! @brief SPIFI interrupt source */
AnnaBridge 171:3a7713b1edbc 37 typedef enum _spifi_interrupt_enable
AnnaBridge 171:3a7713b1edbc 38 {
AnnaBridge 171:3a7713b1edbc 39 kSPIFI_CommandFinishInterruptEnable = SPIFI_CTRL_INTEN_MASK, /*!< Interrupt while command finished */
AnnaBridge 171:3a7713b1edbc 40 } spifi_interrupt_enable_t;
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /*! @brief SPIFI SPI mode select */
AnnaBridge 171:3a7713b1edbc 43 typedef enum _spifi_spi_mode
AnnaBridge 171:3a7713b1edbc 44 {
AnnaBridge 171:3a7713b1edbc 45 kSPIFI_SPISckLow = 0x0U, /*!< SCK low after last bit of command, keeps low while CS high */
AnnaBridge 171:3a7713b1edbc 46 kSPIFI_SPISckHigh = 0x1U /*!< SCK high after last bit of command and while CS high */
AnnaBridge 171:3a7713b1edbc 47 } spifi_spi_mode_t;
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /*! @brief SPIFI dual mode select */
AnnaBridge 171:3a7713b1edbc 50 typedef enum _spifi_dual_mode
AnnaBridge 171:3a7713b1edbc 51 {
AnnaBridge 171:3a7713b1edbc 52 kSPIFI_QuadMode = 0x0U, /*!< SPIFI uses IO3:0 */
AnnaBridge 171:3a7713b1edbc 53 kSPIFI_DualMode = 0x1U /*!< SPIFI uses IO1:0 */
AnnaBridge 171:3a7713b1edbc 54 } spifi_dual_mode_t;
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /*! @brief SPIFI data direction */
AnnaBridge 171:3a7713b1edbc 57 typedef enum _spifi_data_direction
AnnaBridge 171:3a7713b1edbc 58 {
AnnaBridge 171:3a7713b1edbc 59 kSPIFI_DataInput = 0x0U, /*!< Data input from serial flash. */
AnnaBridge 171:3a7713b1edbc 60 kSPIFI_DataOutput = 0x1U /*!< Data output to serial flash. */
AnnaBridge 171:3a7713b1edbc 61 } spifi_data_direction_t;
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 /*! @brief SPIFI command opcode format */
AnnaBridge 171:3a7713b1edbc 64 typedef enum _spifi_command_format
AnnaBridge 171:3a7713b1edbc 65 {
AnnaBridge 171:3a7713b1edbc 66 kSPIFI_CommandAllSerial = 0x0, /*!< All fields of command are serial. */
AnnaBridge 171:3a7713b1edbc 67 kSPIFI_CommandDataQuad = 0x1U, /*!< Only data field is dual/quad, others are serial. */
AnnaBridge 171:3a7713b1edbc 68 kSPIFI_CommandOpcodeSerial = 0x2U, /*!< Only opcode field is serial, others are quad/dual. */
AnnaBridge 171:3a7713b1edbc 69 kSPIFI_CommandAllQuad = 0x3U /*!< All fields of command are dual/quad mode. */
AnnaBridge 171:3a7713b1edbc 70 } spifi_command_format_t;
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 /*! @brief SPIFI command type */
AnnaBridge 171:3a7713b1edbc 73 typedef enum _spifi_command_type
AnnaBridge 171:3a7713b1edbc 74 {
AnnaBridge 171:3a7713b1edbc 75 kSPIFI_CommandOpcodeOnly = 0x1U, /*!< Command only have opcode, no address field */
AnnaBridge 171:3a7713b1edbc 76 kSPIFI_CommandOpcodeAddrOneByte = 0x2U, /*!< Command have opcode and also one byte address field */
AnnaBridge 171:3a7713b1edbc 77 kSPIFI_CommandOpcodeAddrTwoBytes = 0x3U, /*!< Command have opcode and also two bytes address field */
AnnaBridge 171:3a7713b1edbc 78 kSPIFI_CommandOpcodeAddrThreeBytes = 0x4U, /*!< Command have opcode and also three bytes address field. */
AnnaBridge 171:3a7713b1edbc 79 kSPIFI_CommandOpcodeAddrFourBytes = 0x5U, /*!< Command have opcode and also four bytes address field */
AnnaBridge 171:3a7713b1edbc 80 kSPIFI_CommandNoOpcodeAddrThreeBytes = 0x6U, /*!< Command have no opcode and three bytes address field */
AnnaBridge 171:3a7713b1edbc 81 kSPIFI_CommandNoOpcodeAddrFourBytes = 0x7U /*!< Command have no opcode and four bytes address field */
AnnaBridge 171:3a7713b1edbc 82 } spifi_command_type_t;
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 /*! @brief SPIFI status flags */
AnnaBridge 171:3a7713b1edbc 85 enum _spifi_status_flags
AnnaBridge 171:3a7713b1edbc 86 {
AnnaBridge 171:3a7713b1edbc 87 kSPIFI_MemoryCommandWriteFinished = SPIFI_STAT_MCINIT_MASK, /*!< Memory command write finished */
AnnaBridge 171:3a7713b1edbc 88 kSPIFI_CommandWriteFinished = SPIFI_STAT_CMD_MASK, /*!< Command write finished */
AnnaBridge 171:3a7713b1edbc 89 kSPIFI_InterruptRequest = SPIFI_STAT_INTRQ_MASK /*!< CMD flag from 1 to 0, means command execute finished */
AnnaBridge 171:3a7713b1edbc 90 };
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 /*! @brief SPIFI command structure */
AnnaBridge 171:3a7713b1edbc 93 typedef struct _spifi_command
AnnaBridge 171:3a7713b1edbc 94 {
AnnaBridge 171:3a7713b1edbc 95 uint16_t dataLen; /*!< How many data bytes are needed in this command. */
AnnaBridge 171:3a7713b1edbc 96 bool isPollMode; /*!< For command need to read data from serial flash */
AnnaBridge 171:3a7713b1edbc 97 spifi_data_direction_t direction; /*!< Data direction of this command. */
AnnaBridge 171:3a7713b1edbc 98 uint8_t intermediateBytes; /*!< How many intermediate bytes needed */
AnnaBridge 171:3a7713b1edbc 99 spifi_command_format_t format; /*!< Command format */
AnnaBridge 171:3a7713b1edbc 100 spifi_command_type_t type; /*!< Command type */
AnnaBridge 171:3a7713b1edbc 101 uint8_t opcode; /*!< Command opcode value */
AnnaBridge 171:3a7713b1edbc 102 } spifi_command_t;
AnnaBridge 171:3a7713b1edbc 103
AnnaBridge 171:3a7713b1edbc 104 /*!
AnnaBridge 171:3a7713b1edbc 105 * @brief SPIFI region configuration structure.
AnnaBridge 171:3a7713b1edbc 106 */
AnnaBridge 171:3a7713b1edbc 107 typedef struct _spifi_config
AnnaBridge 171:3a7713b1edbc 108 {
AnnaBridge 171:3a7713b1edbc 109 uint16_t timeout; /*!< SPI transfer timeout, the unit is SCK cycles */
AnnaBridge 171:3a7713b1edbc 110 uint8_t csHighTime; /*!< CS high time cycles */
AnnaBridge 171:3a7713b1edbc 111 bool disablePrefetch; /*!< True means SPIFI will not attempt a speculative prefetch. */
AnnaBridge 171:3a7713b1edbc 112 bool disableCachePrefech; /*!< Disable prefetch of cache line */
AnnaBridge 171:3a7713b1edbc 113 bool isFeedbackClock; /*!< Is data sample uses feedback clock. */
AnnaBridge 171:3a7713b1edbc 114 spifi_spi_mode_t spiMode; /*!< SPIFI spi mode select */
AnnaBridge 171:3a7713b1edbc 115 bool isReadFullClockCycle; /*!< If enable read full clock cycle. */
AnnaBridge 171:3a7713b1edbc 116 spifi_dual_mode_t dualMode; /*!< SPIFI dual mode, dual or quad. */
AnnaBridge 171:3a7713b1edbc 117 } spifi_config_t;
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 /*! @brief Transfer structure for SPIFI */
AnnaBridge 171:3a7713b1edbc 120 typedef struct _spifi_transfer
AnnaBridge 171:3a7713b1edbc 121 {
AnnaBridge 171:3a7713b1edbc 122 uint8_t *data; /*!< Pointer to data to transmit */
AnnaBridge 171:3a7713b1edbc 123 size_t dataSize; /*!< Bytes to be transmit */
AnnaBridge 171:3a7713b1edbc 124 } spifi_transfer_t;
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 127 * API
AnnaBridge 171:3a7713b1edbc 128 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 131 extern "C" {
AnnaBridge 171:3a7713b1edbc 132 #endif /* _cplusplus */
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 /*!
AnnaBridge 171:3a7713b1edbc 135 * @name Initialization and deinitialization
AnnaBridge 171:3a7713b1edbc 136 * @{
AnnaBridge 171:3a7713b1edbc 137 */
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 /*!
AnnaBridge 172:65be27845400 140 * @brief Get the SPIFI instance from peripheral base address.
AnnaBridge 172:65be27845400 141 *
AnnaBridge 172:65be27845400 142 * @param base SPIFI peripheral base address.
AnnaBridge 172:65be27845400 143 * @return SPIFI instance.
AnnaBridge 172:65be27845400 144 */
AnnaBridge 172:65be27845400 145 uint32_t SPIFI_GetInstance(SPIFI_Type *base);
AnnaBridge 172:65be27845400 146
AnnaBridge 172:65be27845400 147 /*!
AnnaBridge 171:3a7713b1edbc 148 * @brief Initializes the SPIFI with the user configuration structure.
AnnaBridge 171:3a7713b1edbc 149 *
AnnaBridge 171:3a7713b1edbc 150 * This function configures the SPIFI module with the user-defined configuration.
AnnaBridge 171:3a7713b1edbc 151 *
AnnaBridge 171:3a7713b1edbc 152 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 153 * @param config The pointer to the configuration structure.
AnnaBridge 171:3a7713b1edbc 154 */
AnnaBridge 171:3a7713b1edbc 155 void SPIFI_Init(SPIFI_Type *base, const spifi_config_t *config);
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 /*!
AnnaBridge 171:3a7713b1edbc 158 * @brief Get SPIFI default configure settings.
AnnaBridge 171:3a7713b1edbc 159 *
AnnaBridge 171:3a7713b1edbc 160 * @param config SPIFI config structure pointer.
AnnaBridge 171:3a7713b1edbc 161 */
AnnaBridge 171:3a7713b1edbc 162 void SPIFI_GetDefaultConfig(spifi_config_t *config);
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 /*!
AnnaBridge 171:3a7713b1edbc 165 * @brief Deinitializes the SPIFI regions.
AnnaBridge 171:3a7713b1edbc 166 *
AnnaBridge 171:3a7713b1edbc 167 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 168 */
AnnaBridge 171:3a7713b1edbc 169 void SPIFI_Deinit(SPIFI_Type *base);
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 /* @}*/
AnnaBridge 171:3a7713b1edbc 172
AnnaBridge 171:3a7713b1edbc 173 /*!
AnnaBridge 171:3a7713b1edbc 174 * @name Basic Control Operations
AnnaBridge 171:3a7713b1edbc 175 * @{
AnnaBridge 171:3a7713b1edbc 176 */
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 /*!
AnnaBridge 171:3a7713b1edbc 179 * @brief Set SPIFI flash command.
AnnaBridge 171:3a7713b1edbc 180 *
AnnaBridge 171:3a7713b1edbc 181 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 182 * @param cmd SPIFI command structure pointer.
AnnaBridge 171:3a7713b1edbc 183 */
AnnaBridge 171:3a7713b1edbc 184 void SPIFI_SetCommand(SPIFI_Type *base, spifi_command_t *cmd);
AnnaBridge 171:3a7713b1edbc 185
AnnaBridge 171:3a7713b1edbc 186 /*!
AnnaBridge 171:3a7713b1edbc 187 * @brief Set SPIFI command address.
AnnaBridge 171:3a7713b1edbc 188 *
AnnaBridge 171:3a7713b1edbc 189 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 190 * @param addr Address value for the command.
AnnaBridge 171:3a7713b1edbc 191 */
AnnaBridge 171:3a7713b1edbc 192 static inline void SPIFI_SetCommandAddress(SPIFI_Type *base, uint32_t addr)
AnnaBridge 171:3a7713b1edbc 193 {
AnnaBridge 171:3a7713b1edbc 194 base->ADDR = addr;
AnnaBridge 171:3a7713b1edbc 195 }
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 /*!
AnnaBridge 171:3a7713b1edbc 198 * @brief Set SPIFI intermediate data.
AnnaBridge 171:3a7713b1edbc 199 *
AnnaBridge 171:3a7713b1edbc 200 * Before writing a command wihch needs specific intermediate value, users shall call this function to write it.
AnnaBridge 171:3a7713b1edbc 201 * The main use of this function for current serial flash is to select no-opcode mode and cancelling this mode. As
AnnaBridge 171:3a7713b1edbc 202 * dummy cycle do not care about the value, no need to call this function.
AnnaBridge 171:3a7713b1edbc 203 *
AnnaBridge 171:3a7713b1edbc 204 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 205 * @param val Intermediate data.
AnnaBridge 171:3a7713b1edbc 206 */
AnnaBridge 171:3a7713b1edbc 207 static inline void SPIFI_SetIntermediateData(SPIFI_Type *base, uint32_t val)
AnnaBridge 171:3a7713b1edbc 208 {
AnnaBridge 171:3a7713b1edbc 209 base->IDATA = val;
AnnaBridge 171:3a7713b1edbc 210 }
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 /*!
AnnaBridge 171:3a7713b1edbc 213 * @brief Set SPIFI Cache limit value.
AnnaBridge 171:3a7713b1edbc 214 *
AnnaBridge 171:3a7713b1edbc 215 * SPIFI includes caching of prevously-accessed data to improve performance. Software can write an address to this
AnnaBridge 171:3a7713b1edbc 216 * function, to prevent such caching at and above the address.
AnnaBridge 171:3a7713b1edbc 217 *
AnnaBridge 171:3a7713b1edbc 218 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 219 * @param val Zero-based upper limit of cacheable memory.
AnnaBridge 171:3a7713b1edbc 220 */
AnnaBridge 171:3a7713b1edbc 221 static inline void SPIFI_SetCacheLimit(SPIFI_Type *base, uint32_t val)
AnnaBridge 171:3a7713b1edbc 222 {
AnnaBridge 171:3a7713b1edbc 223 base->CLIMIT = val;
AnnaBridge 171:3a7713b1edbc 224 }
AnnaBridge 171:3a7713b1edbc 225
AnnaBridge 171:3a7713b1edbc 226 /*!
AnnaBridge 171:3a7713b1edbc 227 * @brief Reset the command field of SPIFI.
AnnaBridge 171:3a7713b1edbc 228 *
AnnaBridge 171:3a7713b1edbc 229 * This function is used to abort the current command or memory mode.
AnnaBridge 171:3a7713b1edbc 230 *
AnnaBridge 171:3a7713b1edbc 231 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 232 */
AnnaBridge 171:3a7713b1edbc 233 static inline void SPIFI_ResetCommand(SPIFI_Type *base)
AnnaBridge 171:3a7713b1edbc 234 {
AnnaBridge 171:3a7713b1edbc 235 base->STAT = SPIFI_STAT_RESET_MASK;
AnnaBridge 171:3a7713b1edbc 236 /* Wait for the RESET flag cleared by HW */
AnnaBridge 171:3a7713b1edbc 237 while (base->STAT & SPIFI_STAT_RESET_MASK)
AnnaBridge 171:3a7713b1edbc 238 {
AnnaBridge 171:3a7713b1edbc 239 }
AnnaBridge 171:3a7713b1edbc 240 }
AnnaBridge 171:3a7713b1edbc 241
AnnaBridge 171:3a7713b1edbc 242 /*!
AnnaBridge 171:3a7713b1edbc 243 * @brief Set SPIFI flash AHB read command.
AnnaBridge 171:3a7713b1edbc 244 *
AnnaBridge 171:3a7713b1edbc 245 * Call this function means SPIFI enters to memory mode, while users need to use command, a SPIFI_ResetCommand shall
AnnaBridge 171:3a7713b1edbc 246 * be called.
AnnaBridge 171:3a7713b1edbc 247 *
AnnaBridge 171:3a7713b1edbc 248 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 249 * @param cmd SPIFI command structure pointer.
AnnaBridge 171:3a7713b1edbc 250 */
AnnaBridge 171:3a7713b1edbc 251 void SPIFI_SetMemoryCommand(SPIFI_Type *base, spifi_command_t *cmd);
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 /*!
AnnaBridge 171:3a7713b1edbc 254 * @brief Enable SPIFI interrupt.
AnnaBridge 171:3a7713b1edbc 255 *
AnnaBridge 171:3a7713b1edbc 256 * The interrupt is triggered only in command mode, and it means the command now is finished.
AnnaBridge 171:3a7713b1edbc 257 *
AnnaBridge 171:3a7713b1edbc 258 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 259 * @param mask SPIFI interrupt enable mask. It is a logic OR of members the
AnnaBridge 171:3a7713b1edbc 260 * enumeration :: spifi_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 261 */
AnnaBridge 171:3a7713b1edbc 262 static inline void SPIFI_EnableInterrupt(SPIFI_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 263 {
AnnaBridge 171:3a7713b1edbc 264 base->CTRL |= mask;
AnnaBridge 171:3a7713b1edbc 265 }
AnnaBridge 171:3a7713b1edbc 266
AnnaBridge 171:3a7713b1edbc 267 /*!
AnnaBridge 171:3a7713b1edbc 268 * @brief Disable SPIFI interrupt.
AnnaBridge 171:3a7713b1edbc 269 *
AnnaBridge 171:3a7713b1edbc 270 * The interrupt is triggered only in command mode, and it means the command now is finished.
AnnaBridge 171:3a7713b1edbc 271 *
AnnaBridge 171:3a7713b1edbc 272 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 273 * @param mask SPIFI interrupt enable mask. It is a logic OR of members the
AnnaBridge 171:3a7713b1edbc 274 * enumeration :: spifi_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 275 */
AnnaBridge 171:3a7713b1edbc 276 static inline void SPIFI_DisableInterrupt(SPIFI_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 277 {
AnnaBridge 171:3a7713b1edbc 278 base->CTRL &= ~mask;
AnnaBridge 171:3a7713b1edbc 279 }
AnnaBridge 171:3a7713b1edbc 280
AnnaBridge 171:3a7713b1edbc 281 /*!
AnnaBridge 171:3a7713b1edbc 282 * @name Status
AnnaBridge 171:3a7713b1edbc 283 * @{
AnnaBridge 171:3a7713b1edbc 284 */
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 /*!
AnnaBridge 171:3a7713b1edbc 287 * @brief Get the status of all interrupt flags for SPIFI.
AnnaBridge 171:3a7713b1edbc 288 *
AnnaBridge 171:3a7713b1edbc 289 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 290 * @return SPIFI flag status
AnnaBridge 171:3a7713b1edbc 291 */
AnnaBridge 171:3a7713b1edbc 292 static inline uint32_t SPIFI_GetStatusFlag(SPIFI_Type *base)
AnnaBridge 171:3a7713b1edbc 293 {
AnnaBridge 171:3a7713b1edbc 294 return base->STAT;
AnnaBridge 171:3a7713b1edbc 295 }
AnnaBridge 171:3a7713b1edbc 296
AnnaBridge 171:3a7713b1edbc 297 /* @}*/
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 /*!
AnnaBridge 171:3a7713b1edbc 300 * @brief Enable or disable DMA request for SPIFI.
AnnaBridge 171:3a7713b1edbc 301 *
AnnaBridge 171:3a7713b1edbc 302 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 303 * @param enable True means enable DMA and false means disable DMA.
AnnaBridge 171:3a7713b1edbc 304 */
AnnaBridge 171:3a7713b1edbc 305 static inline void SPIFI_EnableDMA(SPIFI_Type *base, bool enable)
AnnaBridge 171:3a7713b1edbc 306 {
AnnaBridge 171:3a7713b1edbc 307 if (enable)
AnnaBridge 171:3a7713b1edbc 308 {
AnnaBridge 171:3a7713b1edbc 309 base->CTRL |= SPIFI_CTRL_DMAEN_MASK;
AnnaBridge 171:3a7713b1edbc 310 }
AnnaBridge 171:3a7713b1edbc 311 else
AnnaBridge 171:3a7713b1edbc 312 {
AnnaBridge 171:3a7713b1edbc 313 base->CTRL &= ~SPIFI_CTRL_DMAEN_MASK;
AnnaBridge 171:3a7713b1edbc 314 }
AnnaBridge 171:3a7713b1edbc 315 }
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 /*!
AnnaBridge 171:3a7713b1edbc 318 * @brief Gets the SPIFI data register address.
AnnaBridge 171:3a7713b1edbc 319 *
AnnaBridge 171:3a7713b1edbc 320 * This API is used to provide a transfer address for the SPIFI DMA transfer configuration.
AnnaBridge 171:3a7713b1edbc 321 *
AnnaBridge 171:3a7713b1edbc 322 * @param base SPIFI base pointer
AnnaBridge 171:3a7713b1edbc 323 * @return data register address
AnnaBridge 171:3a7713b1edbc 324 */
AnnaBridge 171:3a7713b1edbc 325 static inline uint32_t SPIFI_GetDataRegisterAddress(SPIFI_Type *base)
AnnaBridge 171:3a7713b1edbc 326 {
AnnaBridge 171:3a7713b1edbc 327 return (uint32_t)(&(base->DATA));
AnnaBridge 171:3a7713b1edbc 328 }
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 /*!
AnnaBridge 171:3a7713b1edbc 331 * @brief Write a word data in address of SPIFI.
AnnaBridge 171:3a7713b1edbc 332 *
AnnaBridge 171:3a7713b1edbc 333 * Users can write a page or at least a word data into SPIFI address.
AnnaBridge 171:3a7713b1edbc 334 *
AnnaBridge 171:3a7713b1edbc 335 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 336 * @param data Data need be write.
AnnaBridge 171:3a7713b1edbc 337 */
AnnaBridge 171:3a7713b1edbc 338 static inline void SPIFI_WriteData(SPIFI_Type *base, uint32_t data)
AnnaBridge 171:3a7713b1edbc 339 {
AnnaBridge 171:3a7713b1edbc 340 base->DATA = data;
AnnaBridge 171:3a7713b1edbc 341 }
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 /*!
AnnaBridge 172:65be27845400 344 * @brief Write a byte data in address of SPIFI.
AnnaBridge 172:65be27845400 345 *
AnnaBridge 172:65be27845400 346 * Users can write a byte data into SPIFI address.
AnnaBridge 172:65be27845400 347 *
AnnaBridge 172:65be27845400 348 * @param base SPIFI peripheral base address.
AnnaBridge 172:65be27845400 349 * @param data Data need be write.
AnnaBridge 172:65be27845400 350 */
AnnaBridge 172:65be27845400 351 static inline void SPIFI_WriteDataByte(SPIFI_Type *base, uint8_t data)
AnnaBridge 172:65be27845400 352 {
AnnaBridge 172:65be27845400 353 *((volatile uint8_t *)(&(base->DATA))) = data;
AnnaBridge 172:65be27845400 354 }
AnnaBridge 172:65be27845400 355
AnnaBridge 172:65be27845400 356 /*!
AnnaBridge 172:65be27845400 357 * @brief Write a halfword data in address of SPIFI.
AnnaBridge 172:65be27845400 358 *
AnnaBridge 172:65be27845400 359 * Users can write a halfword data into SPIFI address.
AnnaBridge 172:65be27845400 360 *
AnnaBridge 172:65be27845400 361 * @param base SPIFI peripheral base address.
AnnaBridge 172:65be27845400 362 * @param data Data need be write.
AnnaBridge 172:65be27845400 363 */
AnnaBridge 172:65be27845400 364 void SPIFI_WriteDataHalfword(SPIFI_Type *base, uint16_t data);
AnnaBridge 172:65be27845400 365
AnnaBridge 172:65be27845400 366 /*!
AnnaBridge 171:3a7713b1edbc 367 * @brief Read data from serial flash.
AnnaBridge 171:3a7713b1edbc 368 *
AnnaBridge 171:3a7713b1edbc 369 * Users should notice before call this function, the data length field in command register shall larger
AnnaBridge 171:3a7713b1edbc 370 * than 4, otherwise a hardfault will happen.
AnnaBridge 171:3a7713b1edbc 371 *
AnnaBridge 171:3a7713b1edbc 372 * @param base SPIFI peripheral base address.
AnnaBridge 171:3a7713b1edbc 373 * @return Data input from flash.
AnnaBridge 171:3a7713b1edbc 374 */
AnnaBridge 171:3a7713b1edbc 375 static inline uint32_t SPIFI_ReadData(SPIFI_Type *base)
AnnaBridge 171:3a7713b1edbc 376 {
AnnaBridge 171:3a7713b1edbc 377 return base->DATA;
AnnaBridge 171:3a7713b1edbc 378 }
AnnaBridge 171:3a7713b1edbc 379
AnnaBridge 172:65be27845400 380 /*!
AnnaBridge 172:65be27845400 381 * @brief Read a byte data from serial flash.
AnnaBridge 172:65be27845400 382 *
AnnaBridge 172:65be27845400 383 * @param base SPIFI peripheral base address.
AnnaBridge 172:65be27845400 384 * @return Data input from flash.
AnnaBridge 172:65be27845400 385 */
AnnaBridge 172:65be27845400 386 static inline uint8_t SPIFI_ReadDataByte(SPIFI_Type *base)
AnnaBridge 172:65be27845400 387 {
AnnaBridge 172:65be27845400 388 return *((volatile uint8_t *)(&(base->DATA)));
AnnaBridge 172:65be27845400 389 }
AnnaBridge 172:65be27845400 390
AnnaBridge 172:65be27845400 391 /*!
AnnaBridge 172:65be27845400 392 * @brief Read a halfword data from serial flash.
AnnaBridge 172:65be27845400 393 *
AnnaBridge 172:65be27845400 394 * @param base SPIFI peripheral base address.
AnnaBridge 172:65be27845400 395 * @return Data input from flash.
AnnaBridge 172:65be27845400 396 */
AnnaBridge 172:65be27845400 397 uint16_t SPIFI_ReadDataHalfword(SPIFI_Type *base);
AnnaBridge 172:65be27845400 398
AnnaBridge 171:3a7713b1edbc 399 /* @} */
AnnaBridge 171:3a7713b1edbc 400
AnnaBridge 171:3a7713b1edbc 401 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 402 }
AnnaBridge 171:3a7713b1edbc 403 #endif
AnnaBridge 171:3a7713b1edbc 404
AnnaBridge 171:3a7713b1edbc 405 /*! @}*/
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 #endif /* _FSL_SPIFI_H_ */