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TARGET_FF_LPC546XX/TOOLCHAIN_GCC_ARM/fsl_dma.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * The Clear BSD License
AnnaBridge 171:3a7713b1edbc 3 * Copyright (c) 2016, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 4 * Copyright 2016-2017 NXP
AnnaBridge 171:3a7713b1edbc 5 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 6 *
AnnaBridge 171:3a7713b1edbc 7 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 8 * are permitted (subject to the limitations in the disclaimer below) provided
AnnaBridge 171:3a7713b1edbc 9 * that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 12 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 15 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 16 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * o Neither the name of the copyright holder nor the names of its
AnnaBridge 171:3a7713b1edbc 19 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 20 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
AnnaBridge 171:3a7713b1edbc 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 33 */
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35 #ifndef _FSL_DMA_H_
AnnaBridge 171:3a7713b1edbc 36 #define _FSL_DMA_H_
AnnaBridge 171:3a7713b1edbc 37
AnnaBridge 171:3a7713b1edbc 38 #include "fsl_common.h"
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 /*!
AnnaBridge 171:3a7713b1edbc 41 * @addtogroup dma
AnnaBridge 171:3a7713b1edbc 42 * @{
AnnaBridge 171:3a7713b1edbc 43 */
AnnaBridge 171:3a7713b1edbc 44
AnnaBridge 171:3a7713b1edbc 45 /*! @file */
AnnaBridge 171:3a7713b1edbc 46 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 47 * Definitions
AnnaBridge 171:3a7713b1edbc 48 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52 /*! @brief DMA driver version */
AnnaBridge 171:3a7713b1edbc 53 #define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
AnnaBridge 171:3a7713b1edbc 54 /*@}*/
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 #define DMA_MAX_TRANSFER_COUNT 0x400
AnnaBridge 171:3a7713b1edbc 57
AnnaBridge 171:3a7713b1edbc 58 /* Channel group consists of 32 channels. channel_group = (channel / 32) */
AnnaBridge 171:3a7713b1edbc 59 #define DMA_CHANNEL_GROUP(channel) (((uint8_t)channel) >> 5U)
AnnaBridge 171:3a7713b1edbc 60 /* Channel index in channel group. channel_index = (channel % 32) */
AnnaBridge 171:3a7713b1edbc 61 #define DMA_CHANNEL_INDEX(channel) (((uint8_t)channel) & 0x1F)
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 /*! @brief DMA descriptor structure */
AnnaBridge 171:3a7713b1edbc 64 typedef struct _dma_descriptor
AnnaBridge 171:3a7713b1edbc 65 {
AnnaBridge 171:3a7713b1edbc 66 uint32_t xfercfg; /*!< Transfer configuration */
AnnaBridge 171:3a7713b1edbc 67 void *srcEndAddr; /*!< Last source address of DMA transfer */
AnnaBridge 171:3a7713b1edbc 68 void *dstEndAddr; /*!< Last destination address of DMA transfer */
AnnaBridge 171:3a7713b1edbc 69 void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */
AnnaBridge 171:3a7713b1edbc 70 } dma_descriptor_t;
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 /*! @brief DMA transfer configuration */
AnnaBridge 171:3a7713b1edbc 73 typedef struct _dma_xfercfg
AnnaBridge 171:3a7713b1edbc 74 {
AnnaBridge 171:3a7713b1edbc 75 bool valid; /*!< Descriptor is ready to transfer */
AnnaBridge 171:3a7713b1edbc 76 bool reload; /*!< Reload channel configuration register after
AnnaBridge 171:3a7713b1edbc 77 current descriptor is exhausted */
AnnaBridge 171:3a7713b1edbc 78 bool swtrig; /*!< Perform software trigger. Transfer if fired
AnnaBridge 171:3a7713b1edbc 79 when 'valid' is set */
AnnaBridge 171:3a7713b1edbc 80 bool clrtrig; /*!< Clear trigger */
AnnaBridge 171:3a7713b1edbc 81 bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */
AnnaBridge 171:3a7713b1edbc 82 bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */
AnnaBridge 171:3a7713b1edbc 83 uint8_t byteWidth; /*!< Byte width of data to transfer */
AnnaBridge 171:3a7713b1edbc 84 uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */
AnnaBridge 171:3a7713b1edbc 85 uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */
AnnaBridge 171:3a7713b1edbc 86 uint16_t transferCount; /*!< Number of transfers */
AnnaBridge 171:3a7713b1edbc 87 } dma_xfercfg_t;
AnnaBridge 171:3a7713b1edbc 88
AnnaBridge 171:3a7713b1edbc 89 /*! @brief DMA channel priority */
AnnaBridge 171:3a7713b1edbc 90 typedef enum _dma_priority
AnnaBridge 171:3a7713b1edbc 91 {
AnnaBridge 171:3a7713b1edbc 92 kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */
AnnaBridge 171:3a7713b1edbc 93 kDMA_ChannelPriority1, /*!< Channel priority 1 */
AnnaBridge 171:3a7713b1edbc 94 kDMA_ChannelPriority2, /*!< Channel priority 2 */
AnnaBridge 171:3a7713b1edbc 95 kDMA_ChannelPriority3, /*!< Channel priority 3 */
AnnaBridge 171:3a7713b1edbc 96 kDMA_ChannelPriority4, /*!< Channel priority 4 */
AnnaBridge 171:3a7713b1edbc 97 kDMA_ChannelPriority5, /*!< Channel priority 5 */
AnnaBridge 171:3a7713b1edbc 98 kDMA_ChannelPriority6, /*!< Channel priority 6 */
AnnaBridge 171:3a7713b1edbc 99 kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */
AnnaBridge 171:3a7713b1edbc 100 } dma_priority_t;
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 /*! @brief DMA interrupt flags */
AnnaBridge 171:3a7713b1edbc 103 typedef enum _dma_int
AnnaBridge 171:3a7713b1edbc 104 {
AnnaBridge 171:3a7713b1edbc 105 kDMA_IntA, /*!< DMA interrupt flag A */
AnnaBridge 171:3a7713b1edbc 106 kDMA_IntB, /*!< DMA interrupt flag B */
AnnaBridge 171:3a7713b1edbc 107 kDMA_IntError, /*!< DMA interrupt flag error */
AnnaBridge 171:3a7713b1edbc 108 } dma_irq_t;
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 /*! @brief DMA trigger type*/
AnnaBridge 171:3a7713b1edbc 111 typedef enum _dma_trigger_type
AnnaBridge 171:3a7713b1edbc 112 {
AnnaBridge 171:3a7713b1edbc 113 kDMA_NoTrigger = 0, /*!< Trigger is disabled */
AnnaBridge 171:3a7713b1edbc 114 kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */
AnnaBridge 171:3a7713b1edbc 115 kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) |
AnnaBridge 171:3a7713b1edbc 116 DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */
AnnaBridge 171:3a7713b1edbc 117 kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */
AnnaBridge 171:3a7713b1edbc 118 kDMA_RisingEdgeTrigger =
AnnaBridge 171:3a7713b1edbc 119 DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */
AnnaBridge 171:3a7713b1edbc 120 } dma_trigger_type_t;
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 /*! @brief DMA trigger burst */
AnnaBridge 171:3a7713b1edbc 123 typedef enum _dma_trigger_burst
AnnaBridge 171:3a7713b1edbc 124 {
AnnaBridge 171:3a7713b1edbc 125 kDMA_SingleTransfer = 0, /*!< Single transfer */
AnnaBridge 171:3a7713b1edbc 126 kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */
AnnaBridge 171:3a7713b1edbc 127 kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */
AnnaBridge 171:3a7713b1edbc 128 kDMA_EdgeBurstTransfer2 =
AnnaBridge 171:3a7713b1edbc 129 DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */
AnnaBridge 171:3a7713b1edbc 130 kDMA_EdgeBurstTransfer4 =
AnnaBridge 171:3a7713b1edbc 131 DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */
AnnaBridge 171:3a7713b1edbc 132 kDMA_EdgeBurstTransfer8 =
AnnaBridge 171:3a7713b1edbc 133 DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */
AnnaBridge 171:3a7713b1edbc 134 kDMA_EdgeBurstTransfer16 =
AnnaBridge 171:3a7713b1edbc 135 DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */
AnnaBridge 171:3a7713b1edbc 136 kDMA_EdgeBurstTransfer32 =
AnnaBridge 171:3a7713b1edbc 137 DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */
AnnaBridge 171:3a7713b1edbc 138 kDMA_EdgeBurstTransfer64 =
AnnaBridge 171:3a7713b1edbc 139 DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */
AnnaBridge 171:3a7713b1edbc 140 kDMA_EdgeBurstTransfer128 =
AnnaBridge 171:3a7713b1edbc 141 DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */
AnnaBridge 171:3a7713b1edbc 142 kDMA_EdgeBurstTransfer256 =
AnnaBridge 171:3a7713b1edbc 143 DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */
AnnaBridge 171:3a7713b1edbc 144 kDMA_EdgeBurstTransfer512 =
AnnaBridge 171:3a7713b1edbc 145 DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */
AnnaBridge 171:3a7713b1edbc 146 kDMA_EdgeBurstTransfer1024 =
AnnaBridge 171:3a7713b1edbc 147 DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */
AnnaBridge 171:3a7713b1edbc 148 } dma_trigger_burst_t;
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 /*! @brief DMA burst wrapping */
AnnaBridge 171:3a7713b1edbc 151 typedef enum _dma_burst_wrap
AnnaBridge 171:3a7713b1edbc 152 {
AnnaBridge 171:3a7713b1edbc 153 kDMA_NoWrap = 0, /*!< Wrapping is disabled */
AnnaBridge 171:3a7713b1edbc 154 kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */
AnnaBridge 171:3a7713b1edbc 155 kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */
AnnaBridge 171:3a7713b1edbc 156 kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) |
AnnaBridge 171:3a7713b1edbc 157 DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */
AnnaBridge 171:3a7713b1edbc 158 } dma_burst_wrap_t;
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /*! @brief DMA transfer type */
AnnaBridge 171:3a7713b1edbc 161 typedef enum _dma_transfer_type
AnnaBridge 171:3a7713b1edbc 162 {
AnnaBridge 171:3a7713b1edbc 163 kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */
AnnaBridge 171:3a7713b1edbc 164 kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */
AnnaBridge 171:3a7713b1edbc 165 kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/
AnnaBridge 171:3a7713b1edbc 166 kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */
AnnaBridge 171:3a7713b1edbc 167 } dma_transfer_type_t;
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 /*! @brief DMA channel trigger */
AnnaBridge 171:3a7713b1edbc 170 typedef struct _dma_channel_trigger
AnnaBridge 171:3a7713b1edbc 171 {
AnnaBridge 171:3a7713b1edbc 172 dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */
AnnaBridge 171:3a7713b1edbc 173 dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */
AnnaBridge 171:3a7713b1edbc 174 dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */
AnnaBridge 171:3a7713b1edbc 175 } dma_channel_trigger_t;
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 /*! @brief DMA transfer status */
AnnaBridge 171:3a7713b1edbc 178 enum _dma_transfer_status
AnnaBridge 171:3a7713b1edbc 179 {
AnnaBridge 171:3a7713b1edbc 180 kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the
AnnaBridge 171:3a7713b1edbc 181 transfer request. */
AnnaBridge 171:3a7713b1edbc 182 };
AnnaBridge 171:3a7713b1edbc 183
AnnaBridge 171:3a7713b1edbc 184 /*! @brief DMA transfer configuration */
AnnaBridge 171:3a7713b1edbc 185 typedef struct _dma_transfer_config
AnnaBridge 171:3a7713b1edbc 186 {
AnnaBridge 171:3a7713b1edbc 187 uint8_t *srcAddr; /*!< Source data address */
AnnaBridge 171:3a7713b1edbc 188 uint8_t *dstAddr; /*!< Destination data address */
AnnaBridge 171:3a7713b1edbc 189 uint8_t *nextDesc; /*!< Chain custom descriptor */
AnnaBridge 171:3a7713b1edbc 190 dma_xfercfg_t xfercfg; /*!< Transfer options */
AnnaBridge 171:3a7713b1edbc 191 bool isPeriph; /*!< DMA transfer is driven by peripheral */
AnnaBridge 171:3a7713b1edbc 192 } dma_transfer_config_t;
AnnaBridge 171:3a7713b1edbc 193
AnnaBridge 171:3a7713b1edbc 194 /*! @brief Callback for DMA */
AnnaBridge 171:3a7713b1edbc 195 struct _dma_handle;
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 /*! @brief Define Callback function for DMA. */
AnnaBridge 171:3a7713b1edbc 198 typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode);
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 /*! @brief DMA transfer handle structure */
AnnaBridge 171:3a7713b1edbc 201 typedef struct _dma_handle
AnnaBridge 171:3a7713b1edbc 202 {
AnnaBridge 171:3a7713b1edbc 203 dma_callback callback; /*!< Callback function. Invoked when transfer
AnnaBridge 171:3a7713b1edbc 204 of descriptor with interrupt flag finishes */
AnnaBridge 171:3a7713b1edbc 205 void *userData; /*!< Callback function parameter */
AnnaBridge 171:3a7713b1edbc 206 DMA_Type *base; /*!< DMA peripheral base address */
AnnaBridge 171:3a7713b1edbc 207 uint8_t channel; /*!< DMA channel number */
AnnaBridge 171:3a7713b1edbc 208 } dma_handle_t;
AnnaBridge 171:3a7713b1edbc 209
AnnaBridge 171:3a7713b1edbc 210 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 211 * APIs
AnnaBridge 171:3a7713b1edbc 212 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 213 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 214 extern "C" {
AnnaBridge 171:3a7713b1edbc 215 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 /*!
AnnaBridge 171:3a7713b1edbc 218 * @name DMA initialization and De-initialization
AnnaBridge 171:3a7713b1edbc 219 * @{
AnnaBridge 171:3a7713b1edbc 220 */
AnnaBridge 171:3a7713b1edbc 221
AnnaBridge 171:3a7713b1edbc 222 /*!
AnnaBridge 171:3a7713b1edbc 223 * @brief Initializes DMA peripheral.
AnnaBridge 171:3a7713b1edbc 224 *
AnnaBridge 171:3a7713b1edbc 225 * This function enable the DMA clock, set descriptor table and
AnnaBridge 171:3a7713b1edbc 226 * enable DMA peripheral.
AnnaBridge 171:3a7713b1edbc 227 *
AnnaBridge 171:3a7713b1edbc 228 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 229 */
AnnaBridge 171:3a7713b1edbc 230 void DMA_Init(DMA_Type *base);
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232 /*!
AnnaBridge 171:3a7713b1edbc 233 * @brief Deinitializes DMA peripheral.
AnnaBridge 171:3a7713b1edbc 234 *
AnnaBridge 171:3a7713b1edbc 235 * This function gates the DMA clock.
AnnaBridge 171:3a7713b1edbc 236 *
AnnaBridge 171:3a7713b1edbc 237 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 238 */
AnnaBridge 171:3a7713b1edbc 239 void DMA_Deinit(DMA_Type *base);
AnnaBridge 171:3a7713b1edbc 240
AnnaBridge 171:3a7713b1edbc 241 /* @} */
AnnaBridge 171:3a7713b1edbc 242 /*!
AnnaBridge 171:3a7713b1edbc 243 * @name DMA Channel Operation
AnnaBridge 171:3a7713b1edbc 244 * @{
AnnaBridge 171:3a7713b1edbc 245 */
AnnaBridge 171:3a7713b1edbc 246
AnnaBridge 171:3a7713b1edbc 247 /*!
AnnaBridge 171:3a7713b1edbc 248 * @brief Return whether DMA channel is processing transfer
AnnaBridge 171:3a7713b1edbc 249 *
AnnaBridge 171:3a7713b1edbc 250 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 251 * @param channel DMA channel number.
AnnaBridge 171:3a7713b1edbc 252 * @return True for active state, false otherwise.
AnnaBridge 171:3a7713b1edbc 253 */
AnnaBridge 171:3a7713b1edbc 254 static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)
AnnaBridge 171:3a7713b1edbc 255 {
AnnaBridge 171:3a7713b1edbc 256 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
AnnaBridge 171:3a7713b1edbc 257 return (base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false;
AnnaBridge 171:3a7713b1edbc 258 }
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260 /*!
AnnaBridge 171:3a7713b1edbc 261 * @brief Enables the interrupt source for the DMA transfer.
AnnaBridge 171:3a7713b1edbc 262 *
AnnaBridge 171:3a7713b1edbc 263 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 264 * @param channel DMA channel number.
AnnaBridge 171:3a7713b1edbc 265 */
AnnaBridge 171:3a7713b1edbc 266 static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel)
AnnaBridge 171:3a7713b1edbc 267 {
AnnaBridge 171:3a7713b1edbc 268 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
AnnaBridge 171:3a7713b1edbc 269 base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(channel);
AnnaBridge 171:3a7713b1edbc 270 }
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 /*!
AnnaBridge 171:3a7713b1edbc 273 * @brief Disables the interrupt source for the DMA transfer.
AnnaBridge 171:3a7713b1edbc 274 *
AnnaBridge 171:3a7713b1edbc 275 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 276 * @param channel DMA channel number.
AnnaBridge 171:3a7713b1edbc 277 */
AnnaBridge 171:3a7713b1edbc 278 static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel)
AnnaBridge 171:3a7713b1edbc 279 {
AnnaBridge 171:3a7713b1edbc 280 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
AnnaBridge 171:3a7713b1edbc 281 base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENCLR |= 1U << DMA_CHANNEL_INDEX(channel);
AnnaBridge 171:3a7713b1edbc 282 }
AnnaBridge 171:3a7713b1edbc 283
AnnaBridge 171:3a7713b1edbc 284 /*!
AnnaBridge 171:3a7713b1edbc 285 * @brief Enable DMA channel.
AnnaBridge 171:3a7713b1edbc 286 *
AnnaBridge 171:3a7713b1edbc 287 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 288 * @param channel DMA channel number.
AnnaBridge 171:3a7713b1edbc 289 */
AnnaBridge 171:3a7713b1edbc 290 static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel)
AnnaBridge 171:3a7713b1edbc 291 {
AnnaBridge 171:3a7713b1edbc 292 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
AnnaBridge 171:3a7713b1edbc 293 base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLESET |= 1U << DMA_CHANNEL_INDEX(channel);
AnnaBridge 171:3a7713b1edbc 294 }
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 /*!
AnnaBridge 171:3a7713b1edbc 297 * @brief Disable DMA channel.
AnnaBridge 171:3a7713b1edbc 298 *
AnnaBridge 171:3a7713b1edbc 299 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 300 * @param channel DMA channel number.
AnnaBridge 171:3a7713b1edbc 301 */
AnnaBridge 171:3a7713b1edbc 302 static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel)
AnnaBridge 171:3a7713b1edbc 303 {
AnnaBridge 171:3a7713b1edbc 304 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
AnnaBridge 171:3a7713b1edbc 305 base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLECLR |= 1U << DMA_CHANNEL_INDEX(channel);
AnnaBridge 171:3a7713b1edbc 306 }
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 /*!
AnnaBridge 171:3a7713b1edbc 309 * @brief Set PERIPHREQEN of channel configuration register.
AnnaBridge 171:3a7713b1edbc 310 *
AnnaBridge 171:3a7713b1edbc 311 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 312 * @param channel DMA channel number.
AnnaBridge 171:3a7713b1edbc 313 */
AnnaBridge 171:3a7713b1edbc 314 static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel)
AnnaBridge 171:3a7713b1edbc 315 {
AnnaBridge 171:3a7713b1edbc 316 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
AnnaBridge 171:3a7713b1edbc 317 base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
AnnaBridge 171:3a7713b1edbc 318 }
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 /*!
AnnaBridge 171:3a7713b1edbc 321 * @brief Get PERIPHREQEN value of channel configuration register.
AnnaBridge 171:3a7713b1edbc 322 *
AnnaBridge 171:3a7713b1edbc 323 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 324 * @param channel DMA channel number.
AnnaBridge 171:3a7713b1edbc 325 * @return True for enabled PeriphRq, false for disabled.
AnnaBridge 171:3a7713b1edbc 326 */
AnnaBridge 171:3a7713b1edbc 327 static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)
AnnaBridge 171:3a7713b1edbc 328 {
AnnaBridge 171:3a7713b1edbc 329 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
AnnaBridge 171:3a7713b1edbc 330 base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
AnnaBridge 171:3a7713b1edbc 331 }
AnnaBridge 171:3a7713b1edbc 332
AnnaBridge 171:3a7713b1edbc 333 /*!
AnnaBridge 171:3a7713b1edbc 334 * @brief Set trigger settings of DMA channel.
AnnaBridge 171:3a7713b1edbc 335 *
AnnaBridge 171:3a7713b1edbc 336 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 337 * @param channel DMA channel number.
AnnaBridge 171:3a7713b1edbc 338 * @param trigger trigger configuration.
AnnaBridge 171:3a7713b1edbc 339 */
AnnaBridge 171:3a7713b1edbc 340 void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger);
AnnaBridge 171:3a7713b1edbc 341
AnnaBridge 171:3a7713b1edbc 342 /*!
AnnaBridge 171:3a7713b1edbc 343 * @brief Gets the remaining bytes of the current DMA descriptor transfer.
AnnaBridge 171:3a7713b1edbc 344 *
AnnaBridge 171:3a7713b1edbc 345 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 346 * @param channel DMA channel number.
AnnaBridge 171:3a7713b1edbc 347 * @return The number of bytes which have not been transferred yet.
AnnaBridge 171:3a7713b1edbc 348 */
AnnaBridge 171:3a7713b1edbc 349 uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 /*!
AnnaBridge 171:3a7713b1edbc 352 * @brief Set priority of channel configuration register.
AnnaBridge 171:3a7713b1edbc 353 *
AnnaBridge 171:3a7713b1edbc 354 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 355 * @param channel DMA channel number.
AnnaBridge 171:3a7713b1edbc 356 * @param priority Channel priority value.
AnnaBridge 171:3a7713b1edbc 357 */
AnnaBridge 171:3a7713b1edbc 358 static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority)
AnnaBridge 171:3a7713b1edbc 359 {
AnnaBridge 171:3a7713b1edbc 360 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
AnnaBridge 171:3a7713b1edbc 361 base->CHANNEL[channel].CFG =
AnnaBridge 171:3a7713b1edbc 362 (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority);
AnnaBridge 171:3a7713b1edbc 363 }
AnnaBridge 171:3a7713b1edbc 364
AnnaBridge 171:3a7713b1edbc 365 /*!
AnnaBridge 171:3a7713b1edbc 366 * @brief Get priority of channel configuration register.
AnnaBridge 171:3a7713b1edbc 367 *
AnnaBridge 171:3a7713b1edbc 368 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 369 * @param channel DMA channel number.
AnnaBridge 171:3a7713b1edbc 370 * @return Channel priority value.
AnnaBridge 171:3a7713b1edbc 371 */
AnnaBridge 171:3a7713b1edbc 372 static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel)
AnnaBridge 171:3a7713b1edbc 373 {
AnnaBridge 171:3a7713b1edbc 374 assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
AnnaBridge 171:3a7713b1edbc 375 return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >>
AnnaBridge 171:3a7713b1edbc 376 DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
AnnaBridge 171:3a7713b1edbc 377 }
AnnaBridge 171:3a7713b1edbc 378
AnnaBridge 171:3a7713b1edbc 379 /*!
AnnaBridge 171:3a7713b1edbc 380 * @brief Create application specific DMA descriptor
AnnaBridge 171:3a7713b1edbc 381 * to be used in a chain in transfer
AnnaBridge 171:3a7713b1edbc 382 *
AnnaBridge 171:3a7713b1edbc 383 * @param desc DMA descriptor address.
AnnaBridge 171:3a7713b1edbc 384 * @param xfercfg Transfer configuration for DMA descriptor.
AnnaBridge 171:3a7713b1edbc 385 * @param srcAddr Address of last item to transmit
AnnaBridge 171:3a7713b1edbc 386 * @param dstAddr Address of last item to receive.
AnnaBridge 171:3a7713b1edbc 387 * @param nextDesc Address of next descriptor in chain.
AnnaBridge 171:3a7713b1edbc 388 */
AnnaBridge 171:3a7713b1edbc 389 void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc);
AnnaBridge 171:3a7713b1edbc 390
AnnaBridge 171:3a7713b1edbc 391 /* @} */
AnnaBridge 171:3a7713b1edbc 392
AnnaBridge 171:3a7713b1edbc 393 /*!
AnnaBridge 171:3a7713b1edbc 394 * @name DMA Transactional Operation
AnnaBridge 171:3a7713b1edbc 395 * @{
AnnaBridge 171:3a7713b1edbc 396 */
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 /*!
AnnaBridge 171:3a7713b1edbc 399 * @brief Abort running transfer by handle.
AnnaBridge 171:3a7713b1edbc 400 *
AnnaBridge 171:3a7713b1edbc 401 * This function aborts DMA transfer specified by handle.
AnnaBridge 171:3a7713b1edbc 402 *
AnnaBridge 171:3a7713b1edbc 403 * @param handle DMA handle pointer.
AnnaBridge 171:3a7713b1edbc 404 */
AnnaBridge 171:3a7713b1edbc 405 void DMA_AbortTransfer(dma_handle_t *handle);
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 /*!
AnnaBridge 171:3a7713b1edbc 408 * @brief Creates the DMA handle.
AnnaBridge 171:3a7713b1edbc 409 *
AnnaBridge 171:3a7713b1edbc 410 * This function is called if using transaction API for DMA. This function
AnnaBridge 171:3a7713b1edbc 411 * initializes the internal state of DMA handle.
AnnaBridge 171:3a7713b1edbc 412 *
AnnaBridge 171:3a7713b1edbc 413 * @param handle DMA handle pointer. The DMA handle stores callback function and
AnnaBridge 171:3a7713b1edbc 414 * parameters.
AnnaBridge 171:3a7713b1edbc 415 * @param base DMA peripheral base address.
AnnaBridge 171:3a7713b1edbc 416 * @param channel DMA channel number.
AnnaBridge 171:3a7713b1edbc 417 */
AnnaBridge 171:3a7713b1edbc 418 void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel);
AnnaBridge 171:3a7713b1edbc 419
AnnaBridge 171:3a7713b1edbc 420 /*!
AnnaBridge 171:3a7713b1edbc 421 * @brief Installs a callback function for the DMA transfer.
AnnaBridge 171:3a7713b1edbc 422 *
AnnaBridge 171:3a7713b1edbc 423 * This callback is called in DMA IRQ handler. Use the callback to do something after
AnnaBridge 171:3a7713b1edbc 424 * the current major loop transfer completes.
AnnaBridge 171:3a7713b1edbc 425 *
AnnaBridge 171:3a7713b1edbc 426 * @param handle DMA handle pointer.
AnnaBridge 171:3a7713b1edbc 427 * @param callback DMA callback function pointer.
AnnaBridge 171:3a7713b1edbc 428 * @param userData Parameter for callback function.
AnnaBridge 171:3a7713b1edbc 429 */
AnnaBridge 171:3a7713b1edbc 430 void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData);
AnnaBridge 171:3a7713b1edbc 431
AnnaBridge 171:3a7713b1edbc 432 /*!
AnnaBridge 171:3a7713b1edbc 433 * @brief Prepares the DMA transfer structure.
AnnaBridge 171:3a7713b1edbc 434 *
AnnaBridge 171:3a7713b1edbc 435 * This function prepares the transfer configuration structure according to the user input.
AnnaBridge 171:3a7713b1edbc 436 *
AnnaBridge 171:3a7713b1edbc 437 * @param config The user configuration structure of type dma_transfer_t.
AnnaBridge 171:3a7713b1edbc 438 * @param srcAddr DMA transfer source address.
AnnaBridge 171:3a7713b1edbc 439 * @param dstAddr DMA transfer destination address.
AnnaBridge 171:3a7713b1edbc 440 * @param byteWidth DMA transfer destination address width(bytes).
AnnaBridge 171:3a7713b1edbc 441 * @param transferBytes DMA transfer bytes to be transferred.
AnnaBridge 171:3a7713b1edbc 442 * @param type DMA transfer type.
AnnaBridge 171:3a7713b1edbc 443 * @param nextDesc Chain custom descriptor to transfer.
AnnaBridge 171:3a7713b1edbc 444 * @note The data address and the data width must be consistent. For example, if the SRC
AnnaBridge 171:3a7713b1edbc 445 * is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
AnnaBridge 171:3a7713b1edbc 446 * source address error(SAE).
AnnaBridge 171:3a7713b1edbc 447 */
AnnaBridge 171:3a7713b1edbc 448 void DMA_PrepareTransfer(dma_transfer_config_t *config,
AnnaBridge 171:3a7713b1edbc 449 void *srcAddr,
AnnaBridge 171:3a7713b1edbc 450 void *dstAddr,
AnnaBridge 171:3a7713b1edbc 451 uint32_t byteWidth,
AnnaBridge 171:3a7713b1edbc 452 uint32_t transferBytes,
AnnaBridge 171:3a7713b1edbc 453 dma_transfer_type_t type,
AnnaBridge 171:3a7713b1edbc 454 void *nextDesc);
AnnaBridge 171:3a7713b1edbc 455
AnnaBridge 171:3a7713b1edbc 456 /*!
AnnaBridge 171:3a7713b1edbc 457 * @brief Submits the DMA transfer request.
AnnaBridge 171:3a7713b1edbc 458 *
AnnaBridge 171:3a7713b1edbc 459 * This function submits the DMA transfer request according to the transfer configuration structure.
AnnaBridge 171:3a7713b1edbc 460 * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
AnnaBridge 171:3a7713b1edbc 461 * a TCD and enables scatter/gather feature to process it in the next time.
AnnaBridge 171:3a7713b1edbc 462 *
AnnaBridge 171:3a7713b1edbc 463 * @param handle DMA handle pointer.
AnnaBridge 171:3a7713b1edbc 464 * @param config Pointer to DMA transfer configuration structure.
AnnaBridge 171:3a7713b1edbc 465 * @retval kStatus_DMA_Success It means submit transfer request succeed.
AnnaBridge 171:3a7713b1edbc 466 * @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
AnnaBridge 171:3a7713b1edbc 467 * @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
AnnaBridge 171:3a7713b1edbc 468 */
AnnaBridge 171:3a7713b1edbc 469 status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config);
AnnaBridge 171:3a7713b1edbc 470
AnnaBridge 171:3a7713b1edbc 471 /*!
AnnaBridge 171:3a7713b1edbc 472 * @brief DMA start transfer.
AnnaBridge 171:3a7713b1edbc 473 *
AnnaBridge 171:3a7713b1edbc 474 * This function enables the channel request. User can call this function after submitting the transfer request
AnnaBridge 171:3a7713b1edbc 475 * or before submitting the transfer request.
AnnaBridge 171:3a7713b1edbc 476 *
AnnaBridge 171:3a7713b1edbc 477 * @param handle DMA handle pointer.
AnnaBridge 171:3a7713b1edbc 478 */
AnnaBridge 171:3a7713b1edbc 479 void DMA_StartTransfer(dma_handle_t *handle);
AnnaBridge 171:3a7713b1edbc 480
AnnaBridge 171:3a7713b1edbc 481 /*!
AnnaBridge 171:3a7713b1edbc 482 * @brief DMA IRQ handler for descriptor transfer complete.
AnnaBridge 171:3a7713b1edbc 483 *
AnnaBridge 171:3a7713b1edbc 484 * This function clears the channel major interrupt flag and call
AnnaBridge 171:3a7713b1edbc 485 * the callback function if it is not NULL.
AnnaBridge 171:3a7713b1edbc 486 */
AnnaBridge 171:3a7713b1edbc 487 void DMA_HandleIRQ(void);
AnnaBridge 171:3a7713b1edbc 488
AnnaBridge 171:3a7713b1edbc 489 /* @} */
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 492 }
AnnaBridge 171:3a7713b1edbc 493 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 /* @} */
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 #endif /*_FSL_DMA_H_*/