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TARGET_FF_LPC546XX/TOOLCHAIN_ARM_STD/fsl_clock.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * The Clear BSD License
AnnaBridge 171:3a7713b1edbc 3 * Copyright (c) 2016, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 4 * Copyright (c) 2016 - 2017 , NXP
AnnaBridge 171:3a7713b1edbc 5 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 6 *
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 9 * are permitted (subject to the limitations in the disclaimer below) provided
AnnaBridge 171:3a7713b1edbc 10 * that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 13 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 16 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 17 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * o Neither the name ofcopyright holder nor the names of its
AnnaBridge 171:3a7713b1edbc 20 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 21 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 22 *
AnnaBridge 171:3a7713b1edbc 23 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
AnnaBridge 171:3a7713b1edbc 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 28 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 31 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 33 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 #ifndef _FSL_CLOCK_H_
AnnaBridge 171:3a7713b1edbc 37 #define _FSL_CLOCK_H_
AnnaBridge 171:3a7713b1edbc 38
AnnaBridge 171:3a7713b1edbc 39 #include "fsl_device_registers.h"
AnnaBridge 171:3a7713b1edbc 40 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 41 #include <stdbool.h>
AnnaBridge 171:3a7713b1edbc 42 #include <assert.h>
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /*! @addtogroup clock */
AnnaBridge 171:3a7713b1edbc 45 /*! @{ */
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /*! @file */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 50 * Definitions
AnnaBridge 171:3a7713b1edbc 51 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 54 /*@{*/
AnnaBridge 171:3a7713b1edbc 55 /*! @brief CLOCK driver version 2.0.0. */
AnnaBridge 171:3a7713b1edbc 56 #define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
AnnaBridge 171:3a7713b1edbc 57 /*@}*/
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 /*! @brief Configure whether driver controls clock
AnnaBridge 171:3a7713b1edbc 60 *
AnnaBridge 171:3a7713b1edbc 61 * When set to 0, peripheral drivers will enable clock in initialize function
AnnaBridge 171:3a7713b1edbc 62 * and disable clock in de-initialize function. When set to 1, peripheral
AnnaBridge 171:3a7713b1edbc 63 * driver will not control the clock, application could contol the clock out of
AnnaBridge 171:3a7713b1edbc 64 * the driver.
AnnaBridge 171:3a7713b1edbc 65 *
AnnaBridge 171:3a7713b1edbc 66 * @note All drivers share this feature switcher. If it is set to 1, application
AnnaBridge 171:3a7713b1edbc 67 * should handle clock enable and disable for all drivers.
AnnaBridge 171:3a7713b1edbc 68 */
AnnaBridge 171:3a7713b1edbc 69 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
AnnaBridge 171:3a7713b1edbc 70 #define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
AnnaBridge 171:3a7713b1edbc 71 #endif
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /*!
AnnaBridge 171:3a7713b1edbc 74 * @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
AnnaBridge 171:3a7713b1edbc 75 *
AnnaBridge 171:3a7713b1edbc 76 * Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
AnnaBridge 171:3a7713b1edbc 77 * would cache the recent calulation and accelerate the execution to get the
AnnaBridge 171:3a7713b1edbc 78 * right settings.
AnnaBridge 171:3a7713b1edbc 79 */
AnnaBridge 171:3a7713b1edbc 80 #ifndef CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT
AnnaBridge 171:3a7713b1edbc 81 #define CLOCK_USR_CFG_PLL_CONFIG_CACHE_COUNT 2U
AnnaBridge 171:3a7713b1edbc 82 #endif
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 /*! @brief Clock ip name array for ROM. */
AnnaBridge 171:3a7713b1edbc 85 #define ADC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 86 { \
AnnaBridge 171:3a7713b1edbc 87 kCLOCK_Adc0 \
AnnaBridge 171:3a7713b1edbc 88 }
AnnaBridge 171:3a7713b1edbc 89 /*! @brief Clock ip name array for ROM. */
AnnaBridge 171:3a7713b1edbc 90 #define ROM_CLOCKS \
AnnaBridge 171:3a7713b1edbc 91 { \
AnnaBridge 171:3a7713b1edbc 92 kCLOCK_Rom \
AnnaBridge 171:3a7713b1edbc 93 }
AnnaBridge 171:3a7713b1edbc 94 /*! @brief Clock ip name array for SRAM. */
AnnaBridge 171:3a7713b1edbc 95 #define SRAM_CLOCKS \
AnnaBridge 171:3a7713b1edbc 96 { \
AnnaBridge 171:3a7713b1edbc 97 kCLOCK_Sram1, kCLOCK_Sram2, kCLOCK_Sram3 \
AnnaBridge 171:3a7713b1edbc 98 }
AnnaBridge 171:3a7713b1edbc 99 /*! @brief Clock ip name array for FLASH. */
AnnaBridge 171:3a7713b1edbc 100 #define FLASH_CLOCKS \
AnnaBridge 171:3a7713b1edbc 101 { \
AnnaBridge 171:3a7713b1edbc 102 kCLOCK_Flash \
AnnaBridge 171:3a7713b1edbc 103 }
AnnaBridge 171:3a7713b1edbc 104 /*! @brief Clock ip name array for FMC. */
AnnaBridge 171:3a7713b1edbc 105 #define FMC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 106 { \
AnnaBridge 171:3a7713b1edbc 107 kCLOCK_Fmc \
AnnaBridge 171:3a7713b1edbc 108 }
AnnaBridge 171:3a7713b1edbc 109 /*! @brief Clock ip name array for EEPROM. */
AnnaBridge 171:3a7713b1edbc 110 #define EEPROM_CLOCKS \
AnnaBridge 171:3a7713b1edbc 111 { \
AnnaBridge 171:3a7713b1edbc 112 kCLOCK_Eeprom \
AnnaBridge 171:3a7713b1edbc 113 }
AnnaBridge 171:3a7713b1edbc 114 /*! @brief Clock ip name array for SPIFI. */
AnnaBridge 171:3a7713b1edbc 115 #define SPIFI_CLOCKS \
AnnaBridge 171:3a7713b1edbc 116 { \
AnnaBridge 171:3a7713b1edbc 117 kCLOCK_Spifi \
AnnaBridge 171:3a7713b1edbc 118 }
AnnaBridge 171:3a7713b1edbc 119 /*! @brief Clock ip name array for INPUTMUX. */
AnnaBridge 171:3a7713b1edbc 120 #define INPUTMUX_CLOCKS \
AnnaBridge 171:3a7713b1edbc 121 { \
AnnaBridge 171:3a7713b1edbc 122 kCLOCK_InputMux \
AnnaBridge 171:3a7713b1edbc 123 }
AnnaBridge 171:3a7713b1edbc 124 /*! @brief Clock ip name array for IOCON. */
AnnaBridge 171:3a7713b1edbc 125 #define IOCON_CLOCKS \
AnnaBridge 171:3a7713b1edbc 126 { \
AnnaBridge 171:3a7713b1edbc 127 kCLOCK_Iocon \
AnnaBridge 171:3a7713b1edbc 128 }
AnnaBridge 171:3a7713b1edbc 129 /*! @brief Clock ip name array for GPIO. */
AnnaBridge 171:3a7713b1edbc 130 #define GPIO_CLOCKS \
AnnaBridge 171:3a7713b1edbc 131 { \
AnnaBridge 171:3a7713b1edbc 132 kCLOCK_Gpio0,kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
AnnaBridge 171:3a7713b1edbc 133 }
AnnaBridge 171:3a7713b1edbc 134 /*! @brief Clock ip name array for PINT. */
AnnaBridge 171:3a7713b1edbc 135 #define PINT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 136 { \
AnnaBridge 171:3a7713b1edbc 137 kCLOCK_Pint \
AnnaBridge 171:3a7713b1edbc 138 }
AnnaBridge 171:3a7713b1edbc 139 /*! @brief Clock ip name array for GINT. */
AnnaBridge 171:3a7713b1edbc 140 #define GINT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 141 { \
AnnaBridge 171:3a7713b1edbc 142 kCLOCK_Gint, kCLOCK_Gint \
AnnaBridge 171:3a7713b1edbc 143 }
AnnaBridge 171:3a7713b1edbc 144 /*! @brief Clock ip name array for DMA. */
AnnaBridge 171:3a7713b1edbc 145 #define DMA_CLOCKS \
AnnaBridge 171:3a7713b1edbc 146 { \
AnnaBridge 171:3a7713b1edbc 147 kCLOCK_Dma \
AnnaBridge 171:3a7713b1edbc 148 }
AnnaBridge 171:3a7713b1edbc 149 /*! @brief Clock ip name array for CRC. */
AnnaBridge 171:3a7713b1edbc 150 #define CRC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 151 { \
AnnaBridge 171:3a7713b1edbc 152 kCLOCK_Crc \
AnnaBridge 171:3a7713b1edbc 153 }
AnnaBridge 171:3a7713b1edbc 154 /*! @brief Clock ip name array for WWDT. */
AnnaBridge 171:3a7713b1edbc 155 #define WWDT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 156 { \
AnnaBridge 171:3a7713b1edbc 157 kCLOCK_Wwdt \
AnnaBridge 171:3a7713b1edbc 158 }
AnnaBridge 171:3a7713b1edbc 159 /*! @brief Clock ip name array for RTC. */
AnnaBridge 171:3a7713b1edbc 160 #define RTC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 161 { \
AnnaBridge 171:3a7713b1edbc 162 kCLOCK_Rtc \
AnnaBridge 171:3a7713b1edbc 163 }
AnnaBridge 171:3a7713b1edbc 164 /*! @brief Clock ip name array for ADC0. */
AnnaBridge 171:3a7713b1edbc 165 #define ADC0_CLOCKS \
AnnaBridge 171:3a7713b1edbc 166 { \
AnnaBridge 171:3a7713b1edbc 167 kCLOCK_Adc0 \
AnnaBridge 171:3a7713b1edbc 168 }
AnnaBridge 171:3a7713b1edbc 169 /*! @brief Clock ip name array for MRT. */
AnnaBridge 171:3a7713b1edbc 170 #define MRT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 171 { \
AnnaBridge 171:3a7713b1edbc 172 kCLOCK_Mrt \
AnnaBridge 171:3a7713b1edbc 173 }
AnnaBridge 171:3a7713b1edbc 174 /*! @brief Clock ip name array for RIT. */
AnnaBridge 171:3a7713b1edbc 175 #define RIT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 176 { \
AnnaBridge 171:3a7713b1edbc 177 kCLOCK_Rit \
AnnaBridge 171:3a7713b1edbc 178 }
AnnaBridge 171:3a7713b1edbc 179 /*! @brief Clock ip name array for SCT0. */
AnnaBridge 171:3a7713b1edbc 180 #define SCT_CLOCKS \
AnnaBridge 171:3a7713b1edbc 181 { \
AnnaBridge 171:3a7713b1edbc 182 kCLOCK_Sct0 \
AnnaBridge 171:3a7713b1edbc 183 }
AnnaBridge 171:3a7713b1edbc 184 /*! @brief Clock ip name array for MCAN. */
AnnaBridge 171:3a7713b1edbc 185 #define MCAN_CLOCKS \
AnnaBridge 171:3a7713b1edbc 186 { \
AnnaBridge 171:3a7713b1edbc 187 kCLOCK_Mcan0, kCLOCK_Mcan1 \
AnnaBridge 171:3a7713b1edbc 188 }
AnnaBridge 171:3a7713b1edbc 189 /*! @brief Clock ip name array for UTICK. */
AnnaBridge 171:3a7713b1edbc 190 #define UTICK_CLOCKS \
AnnaBridge 171:3a7713b1edbc 191 { \
AnnaBridge 171:3a7713b1edbc 192 kCLOCK_Utick \
AnnaBridge 171:3a7713b1edbc 193 }
AnnaBridge 171:3a7713b1edbc 194 /*! @brief Clock ip name array for FLEXCOMM. */
AnnaBridge 171:3a7713b1edbc 195 #define FLEXCOMM_CLOCKS \
AnnaBridge 171:3a7713b1edbc 196 { \
AnnaBridge 171:3a7713b1edbc 197 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, \
AnnaBridge 171:3a7713b1edbc 198 kCLOCK_FlexComm4, kCLOCK_FlexComm5, kCLOCK_FlexComm6, kCLOCK_FlexComm7, \
AnnaBridge 171:3a7713b1edbc 199 kCLOCK_FlexComm8, kCLOCK_FlexComm9 \
AnnaBridge 171:3a7713b1edbc 200 }
AnnaBridge 171:3a7713b1edbc 201 /*! @brief Clock ip name array for LPUART. */
AnnaBridge 171:3a7713b1edbc 202 #define LPUART_CLOCKS \
AnnaBridge 171:3a7713b1edbc 203 { \
AnnaBridge 171:3a7713b1edbc 204 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
AnnaBridge 171:3a7713b1edbc 205 kCLOCK_MinUart6, kCLOCK_MinUart7, kCLOCK_MinUart8,kCLOCK_MinUart9 \
AnnaBridge 171:3a7713b1edbc 206 }
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 /*! @brief Clock ip name array for BI2C. */
AnnaBridge 171:3a7713b1edbc 209 #define BI2C_CLOCKS \
AnnaBridge 171:3a7713b1edbc 210 { \
AnnaBridge 171:3a7713b1edbc 211 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7, \
AnnaBridge 171:3a7713b1edbc 212 kCLOCK_BI2c8, kCLOCK_BI2c9 \
AnnaBridge 171:3a7713b1edbc 213 }
AnnaBridge 171:3a7713b1edbc 214 /*! @brief Clock ip name array for LSPI. */
AnnaBridge 171:3a7713b1edbc 215 #define LPSI_CLOCKS \
AnnaBridge 171:3a7713b1edbc 216 { \
AnnaBridge 171:3a7713b1edbc 217 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7, \
AnnaBridge 171:3a7713b1edbc 218 kCLOCK_LSpi8, kCLOCK_LSpi9 \
AnnaBridge 171:3a7713b1edbc 219 }
AnnaBridge 171:3a7713b1edbc 220 /*! @brief Clock ip name array for FLEXI2S. */
AnnaBridge 171:3a7713b1edbc 221 #define FLEXI2S_CLOCKS \
AnnaBridge 171:3a7713b1edbc 222 { \
AnnaBridge 171:3a7713b1edbc 223 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
AnnaBridge 171:3a7713b1edbc 224 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7, kCLOCK_FlexI2s8, kCLOCK_FlexI2s9 \
AnnaBridge 171:3a7713b1edbc 225 }
AnnaBridge 171:3a7713b1edbc 226 /*! @brief Clock ip name array for DMIC. */
AnnaBridge 171:3a7713b1edbc 227 #define DMIC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 228 { \
AnnaBridge 171:3a7713b1edbc 229 kCLOCK_DMic \
AnnaBridge 171:3a7713b1edbc 230 }
AnnaBridge 171:3a7713b1edbc 231 /*! @brief Clock ip name array for CT32B. */
AnnaBridge 171:3a7713b1edbc 232 #define CTIMER_CLOCKS \
AnnaBridge 171:3a7713b1edbc 233 { \
AnnaBridge 171:3a7713b1edbc 234 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
AnnaBridge 171:3a7713b1edbc 235 }
AnnaBridge 171:3a7713b1edbc 236 /*! @brief Clock ip name array for LCD. */
AnnaBridge 171:3a7713b1edbc 237 #define LCD_CLOCKS \
AnnaBridge 171:3a7713b1edbc 238 { \
AnnaBridge 171:3a7713b1edbc 239 kCLOCK_Lcd \
AnnaBridge 171:3a7713b1edbc 240 }
AnnaBridge 171:3a7713b1edbc 241 /*! @brief Clock ip name array for SDIO. */
AnnaBridge 171:3a7713b1edbc 242 #define SDIO_CLOCKS \
AnnaBridge 171:3a7713b1edbc 243 { \
AnnaBridge 171:3a7713b1edbc 244 kCLOCK_Sdio \
AnnaBridge 171:3a7713b1edbc 245 }
AnnaBridge 171:3a7713b1edbc 246 /*! @brief Clock ip name array for USBRAM. */
AnnaBridge 171:3a7713b1edbc 247 #define USBRAM_CLOCKS \
AnnaBridge 171:3a7713b1edbc 248 { \
AnnaBridge 171:3a7713b1edbc 249 kCLOCK_UsbRam1 \
AnnaBridge 171:3a7713b1edbc 250 }
AnnaBridge 171:3a7713b1edbc 251 /*! @brief Clock ip name array for EMC. */
AnnaBridge 171:3a7713b1edbc 252 #define EMC_CLOCKS \
AnnaBridge 171:3a7713b1edbc 253 { \
AnnaBridge 171:3a7713b1edbc 254 kCLOCK_Emc \
AnnaBridge 171:3a7713b1edbc 255 }
AnnaBridge 171:3a7713b1edbc 256 /*! @brief Clock ip name array for ETH. */
AnnaBridge 171:3a7713b1edbc 257 #define ETH_CLOCKS \
AnnaBridge 171:3a7713b1edbc 258 { \
AnnaBridge 171:3a7713b1edbc 259 kCLOCK_Eth \
AnnaBridge 171:3a7713b1edbc 260 }
AnnaBridge 171:3a7713b1edbc 261 /*! @brief Clock ip name array for AES. */
AnnaBridge 171:3a7713b1edbc 262 #define AES_CLOCKS \
AnnaBridge 171:3a7713b1edbc 263 { \
AnnaBridge 171:3a7713b1edbc 264 kCLOCK_Aes \
AnnaBridge 171:3a7713b1edbc 265 }
AnnaBridge 171:3a7713b1edbc 266 /*! @brief Clock ip name array for OTP. */
AnnaBridge 171:3a7713b1edbc 267 #define OTP_CLOCKS \
AnnaBridge 171:3a7713b1edbc 268 { \
AnnaBridge 171:3a7713b1edbc 269 kCLOCK_Otp \
AnnaBridge 171:3a7713b1edbc 270 }
AnnaBridge 171:3a7713b1edbc 271 /*! @brief Clock ip name array for RNG. */
AnnaBridge 171:3a7713b1edbc 272 #define RNG_CLOCKS \
AnnaBridge 171:3a7713b1edbc 273 { \
AnnaBridge 171:3a7713b1edbc 274 kCLOCK_Rng \
AnnaBridge 171:3a7713b1edbc 275 }
AnnaBridge 171:3a7713b1edbc 276 /*! @brief Clock ip name array for USBHMR0. */
AnnaBridge 171:3a7713b1edbc 277 #define USBHMR0_CLOCKS \
AnnaBridge 171:3a7713b1edbc 278 { \
AnnaBridge 171:3a7713b1edbc 279 kCLOCK_Usbhmr0 \
AnnaBridge 171:3a7713b1edbc 280 }
AnnaBridge 171:3a7713b1edbc 281 /*! @brief Clock ip name array for USBHSL0. */
AnnaBridge 171:3a7713b1edbc 282 #define USBHSL0_CLOCKS \
AnnaBridge 171:3a7713b1edbc 283 { \
AnnaBridge 171:3a7713b1edbc 284 kCLOCK_Usbhsl0 \
AnnaBridge 171:3a7713b1edbc 285 }
AnnaBridge 171:3a7713b1edbc 286 /*! @brief Clock ip name array for SHA0. */
AnnaBridge 171:3a7713b1edbc 287 #define SHA0_CLOCKS \
AnnaBridge 171:3a7713b1edbc 288 { \
AnnaBridge 171:3a7713b1edbc 289 kCLOCK_Sha0 \
AnnaBridge 171:3a7713b1edbc 290 }
AnnaBridge 171:3a7713b1edbc 291 /*! @brief Clock ip name array for SMARTCARD. */
AnnaBridge 171:3a7713b1edbc 292 #define SMARTCARD_CLOCKS \
AnnaBridge 171:3a7713b1edbc 293 { \
AnnaBridge 171:3a7713b1edbc 294 kCLOCK_SmartCard0, kCLOCK_SmartCard1 \
AnnaBridge 171:3a7713b1edbc 295 }
AnnaBridge 171:3a7713b1edbc 296 /*! @brief Clock ip name array for USBD. */
AnnaBridge 171:3a7713b1edbc 297 #define USBD_CLOCKS \
AnnaBridge 171:3a7713b1edbc 298 { \
AnnaBridge 171:3a7713b1edbc 299 kCLOCK_Usbd0, kCLOCK_Usbh1, kCLOCK_Usbd1 \
AnnaBridge 171:3a7713b1edbc 300 }
AnnaBridge 171:3a7713b1edbc 301 /*! @brief Clock ip name array for USBH. */
AnnaBridge 171:3a7713b1edbc 302 #define USBH_CLOCKS \
AnnaBridge 171:3a7713b1edbc 303 { \
AnnaBridge 171:3a7713b1edbc 304 kCLOCK_Usbh1 \
AnnaBridge 171:3a7713b1edbc 305 }
AnnaBridge 171:3a7713b1edbc 306 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
AnnaBridge 171:3a7713b1edbc 307 /*------------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 308 clock_ip_name_t definition:
AnnaBridge 171:3a7713b1edbc 309 ------------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 310
AnnaBridge 171:3a7713b1edbc 311 #define CLK_GATE_REG_OFFSET_SHIFT 8U
AnnaBridge 171:3a7713b1edbc 312 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
AnnaBridge 171:3a7713b1edbc 313 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
AnnaBridge 171:3a7713b1edbc 314 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
AnnaBridge 171:3a7713b1edbc 315
AnnaBridge 171:3a7713b1edbc 316 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
AnnaBridge 171:3a7713b1edbc 317 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
AnnaBridge 171:3a7713b1edbc 318 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
AnnaBridge 171:3a7713b1edbc 321 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
AnnaBridge 171:3a7713b1edbc 322
AnnaBridge 171:3a7713b1edbc 323 #define AHB_CLK_CTRL0 0
AnnaBridge 171:3a7713b1edbc 324 #define AHB_CLK_CTRL1 1
AnnaBridge 171:3a7713b1edbc 325 #define AHB_CLK_CTRL2 2
AnnaBridge 171:3a7713b1edbc 326 #define ASYNC_CLK_CTRL0 3
AnnaBridge 171:3a7713b1edbc 327
AnnaBridge 171:3a7713b1edbc 328 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
AnnaBridge 171:3a7713b1edbc 329 typedef enum _clock_ip_name
AnnaBridge 171:3a7713b1edbc 330 {
AnnaBridge 171:3a7713b1edbc 331 kCLOCK_IpInvalid = 0U,
AnnaBridge 171:3a7713b1edbc 332 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
AnnaBridge 171:3a7713b1edbc 333 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
AnnaBridge 171:3a7713b1edbc 334 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
AnnaBridge 171:3a7713b1edbc 335 kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5),
AnnaBridge 171:3a7713b1edbc 336 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
AnnaBridge 171:3a7713b1edbc 337 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
AnnaBridge 171:3a7713b1edbc 338 kCLOCK_Eeprom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 9),
AnnaBridge 171:3a7713b1edbc 339 kCLOCK_Spifi = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 10),
AnnaBridge 171:3a7713b1edbc 340 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
AnnaBridge 171:3a7713b1edbc 341 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
AnnaBridge 171:3a7713b1edbc 342 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
AnnaBridge 171:3a7713b1edbc 343 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
AnnaBridge 171:3a7713b1edbc 344 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
AnnaBridge 171:3a7713b1edbc 345 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
AnnaBridge 171:3a7713b1edbc 346 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
AnnaBridge 171:3a7713b1edbc 347 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
AnnaBridge 171:3a7713b1edbc 348 kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
AnnaBridge 171:3a7713b1edbc 349 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
AnnaBridge 171:3a7713b1edbc 350 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
AnnaBridge 171:3a7713b1edbc 351 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
AnnaBridge 171:3a7713b1edbc 352 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
AnnaBridge 171:3a7713b1edbc 353 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
AnnaBridge 171:3a7713b1edbc 354 kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
AnnaBridge 171:3a7713b1edbc 355 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
AnnaBridge 171:3a7713b1edbc 356 kCLOCK_Mcan0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 7),
AnnaBridge 171:3a7713b1edbc 357 kCLOCK_Mcan1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 8),
AnnaBridge 171:3a7713b1edbc 358 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
AnnaBridge 171:3a7713b1edbc 359 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
AnnaBridge 171:3a7713b1edbc 360 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
AnnaBridge 171:3a7713b1edbc 361 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
AnnaBridge 171:3a7713b1edbc 362 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
AnnaBridge 171:3a7713b1edbc 363 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
AnnaBridge 171:3a7713b1edbc 364 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
AnnaBridge 171:3a7713b1edbc 365 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
AnnaBridge 171:3a7713b1edbc 366 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
AnnaBridge 171:3a7713b1edbc 367 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
AnnaBridge 171:3a7713b1edbc 368 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
AnnaBridge 171:3a7713b1edbc 369 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
AnnaBridge 171:3a7713b1edbc 370 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
AnnaBridge 171:3a7713b1edbc 371 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
AnnaBridge 171:3a7713b1edbc 372 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
AnnaBridge 171:3a7713b1edbc 373 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
AnnaBridge 171:3a7713b1edbc 374 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
AnnaBridge 171:3a7713b1edbc 375 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
AnnaBridge 171:3a7713b1edbc 376 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
AnnaBridge 171:3a7713b1edbc 377 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
AnnaBridge 171:3a7713b1edbc 378 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
AnnaBridge 171:3a7713b1edbc 379 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
AnnaBridge 171:3a7713b1edbc 380 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
AnnaBridge 171:3a7713b1edbc 381 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
AnnaBridge 171:3a7713b1edbc 382 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
AnnaBridge 171:3a7713b1edbc 383 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
AnnaBridge 171:3a7713b1edbc 384 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
AnnaBridge 171:3a7713b1edbc 385 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
AnnaBridge 171:3a7713b1edbc 386 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
AnnaBridge 171:3a7713b1edbc 387 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
AnnaBridge 171:3a7713b1edbc 388 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
AnnaBridge 171:3a7713b1edbc 389 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
AnnaBridge 171:3a7713b1edbc 390 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
AnnaBridge 171:3a7713b1edbc 391 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
AnnaBridge 171:3a7713b1edbc 392 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
AnnaBridge 171:3a7713b1edbc 393 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
AnnaBridge 171:3a7713b1edbc 394 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
AnnaBridge 171:3a7713b1edbc 395 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
AnnaBridge 171:3a7713b1edbc 396 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
AnnaBridge 171:3a7713b1edbc 397 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
AnnaBridge 171:3a7713b1edbc 398 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
AnnaBridge 171:3a7713b1edbc 399 kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
AnnaBridge 171:3a7713b1edbc 400 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
AnnaBridge 171:3a7713b1edbc 401 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
AnnaBridge 171:3a7713b1edbc 402 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
AnnaBridge 171:3a7713b1edbc 403 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
AnnaBridge 171:3a7713b1edbc 404 kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
AnnaBridge 171:3a7713b1edbc 405 kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
AnnaBridge 171:3a7713b1edbc 406 kCLOCK_Lcd = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2),
AnnaBridge 171:3a7713b1edbc 407 kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3),
AnnaBridge 171:3a7713b1edbc 408 kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4),
AnnaBridge 171:3a7713b1edbc 409 kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5),
AnnaBridge 171:3a7713b1edbc 410 kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6),
AnnaBridge 171:3a7713b1edbc 411 kCLOCK_Emc = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7),
AnnaBridge 171:3a7713b1edbc 412 kCLOCK_Eth = CLK_GATE_DEFINE(AHB_CLK_CTRL2,8),
AnnaBridge 171:3a7713b1edbc 413 kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9),
AnnaBridge 171:3a7713b1edbc 414 kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10),
AnnaBridge 171:3a7713b1edbc 415 kCLOCK_Aes = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 11),
AnnaBridge 171:3a7713b1edbc 416 kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12),
AnnaBridge 171:3a7713b1edbc 417 kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13),
AnnaBridge 171:3a7713b1edbc 418 kCLOCK_FlexComm8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
AnnaBridge 171:3a7713b1edbc 419 kCLOCK_FlexComm9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
AnnaBridge 171:3a7713b1edbc 420 kCLOCK_MinUart8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
AnnaBridge 171:3a7713b1edbc 421 kCLOCK_MinUart9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
AnnaBridge 171:3a7713b1edbc 422 kCLOCK_LSpi8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
AnnaBridge 171:3a7713b1edbc 423 kCLOCK_LSpi9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
AnnaBridge 171:3a7713b1edbc 424 kCLOCK_BI2c8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
AnnaBridge 171:3a7713b1edbc 425 kCLOCK_BI2c9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
AnnaBridge 171:3a7713b1edbc 426 kCLOCK_FlexI2s8 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14),
AnnaBridge 171:3a7713b1edbc 427 kCLOCK_FlexI2s9 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15),
AnnaBridge 171:3a7713b1edbc 428 kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16),
AnnaBridge 171:3a7713b1edbc 429 kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17),
AnnaBridge 171:3a7713b1edbc 430 kCLOCK_Sha0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18),
AnnaBridge 171:3a7713b1edbc 431 kCLOCK_SmartCard0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19),
AnnaBridge 171:3a7713b1edbc 432 kCLOCK_SmartCard1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20),
AnnaBridge 171:3a7713b1edbc 433
AnnaBridge 171:3a7713b1edbc 434 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
AnnaBridge 171:3a7713b1edbc 435 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
AnnaBridge 171:3a7713b1edbc 436 } clock_ip_name_t;
AnnaBridge 171:3a7713b1edbc 437
AnnaBridge 171:3a7713b1edbc 438 /*! @brief Clock name used to get clock frequency. */
AnnaBridge 171:3a7713b1edbc 439 typedef enum _clock_name
AnnaBridge 171:3a7713b1edbc 440 {
AnnaBridge 171:3a7713b1edbc 441 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
AnnaBridge 171:3a7713b1edbc 442 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
AnnaBridge 171:3a7713b1edbc 443 kCLOCK_ClockOut, /*!< CLOCKOUT */
AnnaBridge 171:3a7713b1edbc 444 kCLOCK_FroHf, /*!< FRO48/96 */
AnnaBridge 171:3a7713b1edbc 445 kCLOCK_SpiFi, /*!< SPIFI */
AnnaBridge 171:3a7713b1edbc 446 kCLOCK_Adc, /*!< ADC */
AnnaBridge 171:3a7713b1edbc 447 kCLOCK_Usb0, /*!< USB0 */
AnnaBridge 171:3a7713b1edbc 448 kCLOCK_Usb1, /*!< USB1 */
AnnaBridge 171:3a7713b1edbc 449 kCLOCK_UsbPll, /*!< USB1 PLL */
AnnaBridge 171:3a7713b1edbc 450 kCLOCK_Mclk, /*!< MCLK */
AnnaBridge 171:3a7713b1edbc 451 kCLOCK_Sct, /*!< SCT */
AnnaBridge 171:3a7713b1edbc 452 kCLOCK_SDio, /*!< SDIO */
AnnaBridge 171:3a7713b1edbc 453 kCLOCK_EMC, /*!< EMC */
AnnaBridge 171:3a7713b1edbc 454 kCLOCK_LCD, /*!< LCD */
AnnaBridge 171:3a7713b1edbc 455 kCLOCK_MCAN0, /*!< MCAN0 */
AnnaBridge 171:3a7713b1edbc 456 kCLOCK_MCAN1, /*!< MCAN1 */
AnnaBridge 171:3a7713b1edbc 457 kCLOCK_Fro12M, /*!< FRO12M */
AnnaBridge 171:3a7713b1edbc 458 kCLOCK_ExtClk, /*!< External Clock */
AnnaBridge 171:3a7713b1edbc 459 kCLOCK_PllOut, /*!< PLL Output */
AnnaBridge 171:3a7713b1edbc 460 kCLOCK_UsbClk, /*!< USB input */
AnnaBridge 171:3a7713b1edbc 461 kClock_WdtOsc, /*!< Watchdog Oscillator */
AnnaBridge 171:3a7713b1edbc 462 kCLOCK_Frg, /*!< Frg Clock */
AnnaBridge 171:3a7713b1edbc 463 kCLOCK_Dmic, /*!< Digital Mic clock */
AnnaBridge 171:3a7713b1edbc 464 kCLOCK_AsyncApbClk, /*!< Async APB clock */
AnnaBridge 171:3a7713b1edbc 465 kCLOCK_FlexI2S, /*!< FlexI2S clock */
AnnaBridge 171:3a7713b1edbc 466 kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */
AnnaBridge 171:3a7713b1edbc 467 kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */
AnnaBridge 171:3a7713b1edbc 468 kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */
AnnaBridge 171:3a7713b1edbc 469 kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */
AnnaBridge 171:3a7713b1edbc 470 kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */
AnnaBridge 171:3a7713b1edbc 471 kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */
AnnaBridge 171:3a7713b1edbc 472 kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */
AnnaBridge 171:3a7713b1edbc 473 kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */
AnnaBridge 171:3a7713b1edbc 474 kCLOCK_Flexcomm8, /*!< Flexcomm8Clock */
AnnaBridge 171:3a7713b1edbc 475 kCLOCK_Flexcomm9, /*!< Flexcomm9Clock */
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 } clock_name_t;
AnnaBridge 171:3a7713b1edbc 478
AnnaBridge 171:3a7713b1edbc 479 /**
AnnaBridge 171:3a7713b1edbc 480 * Clock source selections for the asynchronous APB clock
AnnaBridge 171:3a7713b1edbc 481 */
AnnaBridge 171:3a7713b1edbc 482 typedef enum _async_clock_src
AnnaBridge 171:3a7713b1edbc 483 {
AnnaBridge 171:3a7713b1edbc 484 kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
AnnaBridge 171:3a7713b1edbc 485 kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */
AnnaBridge 171:3a7713b1edbc 486 kCLOCK_AsyncAudioPllClk,
AnnaBridge 171:3a7713b1edbc 487 kCLOCK_AsyncI2cClkFc6,
AnnaBridge 171:3a7713b1edbc 488
AnnaBridge 171:3a7713b1edbc 489 } async_clock_src_t;
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 /*! @brief Clock Mux Switches
AnnaBridge 171:3a7713b1edbc 492 * The encoding is as follows each connection identified is 64bits wide
AnnaBridge 171:3a7713b1edbc 493 * starting from LSB upwards
AnnaBridge 171:3a7713b1edbc 494 *
AnnaBridge 171:3a7713b1edbc 495 * [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]*
AnnaBridge 171:3a7713b1edbc 496 *
AnnaBridge 171:3a7713b1edbc 497 */
AnnaBridge 171:3a7713b1edbc 498
AnnaBridge 171:3a7713b1edbc 499 #define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8))
AnnaBridge 171:3a7713b1edbc 500 #define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20))
AnnaBridge 171:3a7713b1edbc 501 #define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32))
AnnaBridge 171:3a7713b1edbc 502 #define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44))
AnnaBridge 171:3a7713b1edbc 503 #define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56))
AnnaBridge 171:3a7713b1edbc 504
AnnaBridge 171:3a7713b1edbc 505 #define CM_MAINCLKSELA 0
AnnaBridge 171:3a7713b1edbc 506 #define CM_MAINCLKSELB 1
AnnaBridge 171:3a7713b1edbc 507 #define CM_CLKOUTCLKSELA 2
AnnaBridge 171:3a7713b1edbc 508 #define CM_SYSPLLCLKSEL 4
AnnaBridge 171:3a7713b1edbc 509 #define CM_AUDPLLCLKSEL 6
AnnaBridge 171:3a7713b1edbc 510 #define CM_SPIFICLKSEL 8
AnnaBridge 171:3a7713b1edbc 511 #define CM_ADCASYNCCLKSEL 9
AnnaBridge 171:3a7713b1edbc 512 #define CM_USB0CLKSEL 10
AnnaBridge 171:3a7713b1edbc 513 #define CM_USB1CLKSEL 11
AnnaBridge 171:3a7713b1edbc 514 #define CM_FXCOMCLKSEL0 12
AnnaBridge 171:3a7713b1edbc 515 #define CM_FXCOMCLKSEL1 13
AnnaBridge 171:3a7713b1edbc 516 #define CM_FXCOMCLKSEL2 14
AnnaBridge 171:3a7713b1edbc 517 #define CM_FXCOMCLKSEL3 15
AnnaBridge 171:3a7713b1edbc 518 #define CM_FXCOMCLKSEL4 16
AnnaBridge 171:3a7713b1edbc 519 #define CM_FXCOMCLKSEL5 17
AnnaBridge 171:3a7713b1edbc 520 #define CM_FXCOMCLKSEL6 18
AnnaBridge 171:3a7713b1edbc 521 #define CM_FXCOMCLKSEL7 19
AnnaBridge 171:3a7713b1edbc 522 #define CM_FXCOMCLKSEL8 20
AnnaBridge 171:3a7713b1edbc 523 #define CM_FXCOMCLKSEL9 21
AnnaBridge 171:3a7713b1edbc 524 #define CM_MCLKCLKSEL 24
AnnaBridge 171:3a7713b1edbc 525 #define CM_FRGCLKSEL 26
AnnaBridge 171:3a7713b1edbc 526 #define CM_DMICCLKSEL 27
AnnaBridge 171:3a7713b1edbc 527 #define CM_SCTCLKSEL 28
AnnaBridge 171:3a7713b1edbc 528 #define CM_LCDCLKSEL 29
AnnaBridge 171:3a7713b1edbc 529 #define CM_SDIOCLKSEL 30
AnnaBridge 171:3a7713b1edbc 530
AnnaBridge 171:3a7713b1edbc 531 #define CM_ASYNCAPB 31
AnnaBridge 171:3a7713b1edbc 532
AnnaBridge 171:3a7713b1edbc 533 typedef enum _clock_attach_id
AnnaBridge 171:3a7713b1edbc 534 {
AnnaBridge 171:3a7713b1edbc 535
AnnaBridge 171:3a7713b1edbc 536 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0),
AnnaBridge 171:3a7713b1edbc 537 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0),
AnnaBridge 171:3a7713b1edbc 538 kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0),
AnnaBridge 171:3a7713b1edbc 539 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0),
AnnaBridge 171:3a7713b1edbc 540 kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2),
AnnaBridge 171:3a7713b1edbc 541 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3),
AnnaBridge 171:3a7713b1edbc 542
AnnaBridge 171:3a7713b1edbc 543 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
AnnaBridge 171:3a7713b1edbc 544 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
AnnaBridge 171:3a7713b1edbc 545 kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
AnnaBridge 171:3a7713b1edbc 546 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
AnnaBridge 171:3a7713b1edbc 547 kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
AnnaBridge 171:3a7713b1edbc 548 kUSB_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
AnnaBridge 171:3a7713b1edbc 549 kAUDIO_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
AnnaBridge 171:3a7713b1edbc 550 kOSC32K_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
AnnaBridge 171:3a7713b1edbc 551
AnnaBridge 171:3a7713b1edbc 552 kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
AnnaBridge 171:3a7713b1edbc 553 kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
AnnaBridge 171:3a7713b1edbc 554 kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
AnnaBridge 171:3a7713b1edbc 555 kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
AnnaBridge 171:3a7713b1edbc 556 kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 kFRO12M_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 0),
AnnaBridge 171:3a7713b1edbc 559 kEXT_CLK_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 1),
AnnaBridge 171:3a7713b1edbc 560 kNONE_to_AUDIO_PLL = MUX_A(CM_AUDPLLCLKSEL, 7),
AnnaBridge 171:3a7713b1edbc 561
AnnaBridge 171:3a7713b1edbc 562 kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),
AnnaBridge 171:3a7713b1edbc 563 kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),
AnnaBridge 171:3a7713b1edbc 564 kUSB_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 2),
AnnaBridge 171:3a7713b1edbc 565 kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),
AnnaBridge 171:3a7713b1edbc 566 kAUDIO_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 4),
AnnaBridge 171:3a7713b1edbc 567 kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),
AnnaBridge 171:3a7713b1edbc 568
AnnaBridge 171:3a7713b1edbc 569 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
AnnaBridge 171:3a7713b1edbc 570 kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
AnnaBridge 171:3a7713b1edbc 571 kUSB_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
AnnaBridge 171:3a7713b1edbc 572 kAUDIO_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3),
AnnaBridge 171:3a7713b1edbc 573 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
AnnaBridge 171:3a7713b1edbc 574
AnnaBridge 171:3a7713b1edbc 575 kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0),
AnnaBridge 171:3a7713b1edbc 576 kSYS_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1),
AnnaBridge 171:3a7713b1edbc 577 kUSB_PLL_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 2),
AnnaBridge 171:3a7713b1edbc 578 kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7),
AnnaBridge 171:3a7713b1edbc 579
AnnaBridge 171:3a7713b1edbc 580 kFRO_HF_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 0),
AnnaBridge 171:3a7713b1edbc 581 kSYS_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 1),
AnnaBridge 171:3a7713b1edbc 582 kUSB_PLL_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 2),
AnnaBridge 171:3a7713b1edbc 583 kNONE_to_USB1_CLK = MUX_A(CM_USB1CLKSEL, 7),
AnnaBridge 171:3a7713b1edbc 584
AnnaBridge 171:3a7713b1edbc 585 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
AnnaBridge 171:3a7713b1edbc 586 kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
AnnaBridge 171:3a7713b1edbc 587 kAUDIO_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
AnnaBridge 171:3a7713b1edbc 588 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
AnnaBridge 171:3a7713b1edbc 589 kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
AnnaBridge 171:3a7713b1edbc 590 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
AnnaBridge 171:3a7713b1edbc 591
AnnaBridge 171:3a7713b1edbc 592 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
AnnaBridge 171:3a7713b1edbc 593 kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
AnnaBridge 171:3a7713b1edbc 594 kAUDIO_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
AnnaBridge 171:3a7713b1edbc 595 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
AnnaBridge 171:3a7713b1edbc 596 kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
AnnaBridge 171:3a7713b1edbc 597 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
AnnaBridge 171:3a7713b1edbc 598
AnnaBridge 171:3a7713b1edbc 599 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
AnnaBridge 171:3a7713b1edbc 600 kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
AnnaBridge 171:3a7713b1edbc 601 kAUDIO_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
AnnaBridge 171:3a7713b1edbc 602 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
AnnaBridge 171:3a7713b1edbc 603 kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
AnnaBridge 171:3a7713b1edbc 604 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
AnnaBridge 171:3a7713b1edbc 605
AnnaBridge 171:3a7713b1edbc 606 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
AnnaBridge 171:3a7713b1edbc 607 kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
AnnaBridge 171:3a7713b1edbc 608 kAUDIO_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
AnnaBridge 171:3a7713b1edbc 609 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
AnnaBridge 171:3a7713b1edbc 610 kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
AnnaBridge 171:3a7713b1edbc 611 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
AnnaBridge 171:3a7713b1edbc 612
AnnaBridge 171:3a7713b1edbc 613 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
AnnaBridge 171:3a7713b1edbc 614 kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
AnnaBridge 171:3a7713b1edbc 615 kAUDIO_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
AnnaBridge 171:3a7713b1edbc 616 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
AnnaBridge 171:3a7713b1edbc 617 kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
AnnaBridge 171:3a7713b1edbc 618 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
AnnaBridge 171:3a7713b1edbc 619
AnnaBridge 171:3a7713b1edbc 620 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
AnnaBridge 171:3a7713b1edbc 621 kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
AnnaBridge 171:3a7713b1edbc 622 kAUDIO_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
AnnaBridge 171:3a7713b1edbc 623 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
AnnaBridge 171:3a7713b1edbc 624 kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
AnnaBridge 171:3a7713b1edbc 625 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
AnnaBridge 171:3a7713b1edbc 626
AnnaBridge 171:3a7713b1edbc 627 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
AnnaBridge 171:3a7713b1edbc 628 kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
AnnaBridge 171:3a7713b1edbc 629 kAUDIO_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
AnnaBridge 171:3a7713b1edbc 630 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
AnnaBridge 171:3a7713b1edbc 631 kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
AnnaBridge 171:3a7713b1edbc 632 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
AnnaBridge 171:3a7713b1edbc 633
AnnaBridge 171:3a7713b1edbc 634 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
AnnaBridge 171:3a7713b1edbc 635 kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
AnnaBridge 171:3a7713b1edbc 636 kAUDIO_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
AnnaBridge 171:3a7713b1edbc 637 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
AnnaBridge 171:3a7713b1edbc 638 kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
AnnaBridge 171:3a7713b1edbc 639 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
AnnaBridge 171:3a7713b1edbc 640
AnnaBridge 171:3a7713b1edbc 641 kFRO12M_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 0),
AnnaBridge 171:3a7713b1edbc 642 kFRO_HF_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 1),
AnnaBridge 171:3a7713b1edbc 643 kAUDIO_PLL_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 2),
AnnaBridge 171:3a7713b1edbc 644 kMCLK_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 3),
AnnaBridge 171:3a7713b1edbc 645 kFRG_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 4),
AnnaBridge 171:3a7713b1edbc 646 kNONE_to_FLEXCOMM8 = MUX_A(CM_FXCOMCLKSEL8, 7),
AnnaBridge 171:3a7713b1edbc 647
AnnaBridge 171:3a7713b1edbc 648 kFRO12M_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 0),
AnnaBridge 171:3a7713b1edbc 649 kFRO_HF_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 1),
AnnaBridge 171:3a7713b1edbc 650 kAUDIO_PLL_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 2),
AnnaBridge 171:3a7713b1edbc 651 kMCLK_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 3),
AnnaBridge 171:3a7713b1edbc 652 kFRG_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 4),
AnnaBridge 171:3a7713b1edbc 653 kNONE_to_FLEXCOMM9 = MUX_A(CM_FXCOMCLKSEL9, 7),
AnnaBridge 171:3a7713b1edbc 654
AnnaBridge 171:3a7713b1edbc 655 kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0),
AnnaBridge 171:3a7713b1edbc 656 kAUDIO_PLL_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1),
AnnaBridge 171:3a7713b1edbc 657 kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7),
AnnaBridge 171:3a7713b1edbc 658
AnnaBridge 171:3a7713b1edbc 659 kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
AnnaBridge 171:3a7713b1edbc 660 kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
AnnaBridge 171:3a7713b1edbc 661 kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
AnnaBridge 171:3a7713b1edbc 662 kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
AnnaBridge 171:3a7713b1edbc 663 kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
AnnaBridge 171:3a7713b1edbc 664
AnnaBridge 171:3a7713b1edbc 665 kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
AnnaBridge 171:3a7713b1edbc 666 kFRO_HF_DIV_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
AnnaBridge 171:3a7713b1edbc 667 kAUDIO_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),
AnnaBridge 171:3a7713b1edbc 668 kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),
AnnaBridge 171:3a7713b1edbc 669 kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),
AnnaBridge 171:3a7713b1edbc 670
AnnaBridge 171:3a7713b1edbc 671 kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0),
AnnaBridge 171:3a7713b1edbc 672 kSYS_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1),
AnnaBridge 171:3a7713b1edbc 673 kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2),
AnnaBridge 171:3a7713b1edbc 674 kAUDIO_PLL_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3),
AnnaBridge 171:3a7713b1edbc 675 kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7),
AnnaBridge 171:3a7713b1edbc 676
AnnaBridge 171:3a7713b1edbc 677 kMCLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0),
AnnaBridge 171:3a7713b1edbc 678 kSYS_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1),
AnnaBridge 171:3a7713b1edbc 679 kUSB_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 2),
AnnaBridge 171:3a7713b1edbc 680 kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
AnnaBridge 171:3a7713b1edbc 681 kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4),
AnnaBridge 171:3a7713b1edbc 682 kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
AnnaBridge 171:3a7713b1edbc 683
AnnaBridge 171:3a7713b1edbc 684 kMCLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
AnnaBridge 171:3a7713b1edbc 685 kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1),
AnnaBridge 171:3a7713b1edbc 686 kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2),
AnnaBridge 171:3a7713b1edbc 687 kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3),
AnnaBridge 171:3a7713b1edbc 688
AnnaBridge 171:3a7713b1edbc 689 kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
AnnaBridge 171:3a7713b1edbc 690 kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
AnnaBridge 171:3a7713b1edbc 691 kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2),
AnnaBridge 171:3a7713b1edbc 692 kI2C_CLK_FC6_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 3),
AnnaBridge 171:3a7713b1edbc 693 kNONE_to_NONE = 0x80000000U,
AnnaBridge 171:3a7713b1edbc 694 } clock_attach_id_t;
AnnaBridge 171:3a7713b1edbc 695
AnnaBridge 171:3a7713b1edbc 696 /* Clock dividers */
AnnaBridge 171:3a7713b1edbc 697 typedef enum _clock_div_name
AnnaBridge 171:3a7713b1edbc 698 {
AnnaBridge 171:3a7713b1edbc 699 kCLOCK_DivSystickClk = 0,
AnnaBridge 171:3a7713b1edbc 700 kCLOCK_DivArmTrClkDiv = 1,
AnnaBridge 171:3a7713b1edbc 701 kCLOCK_DivCan0Clk = 2,
AnnaBridge 171:3a7713b1edbc 702 kCLOCK_DivCan1Clk = 3,
AnnaBridge 171:3a7713b1edbc 703 kCLOCK_DivSmartCard0Clk = 4,
AnnaBridge 171:3a7713b1edbc 704 kCLOCK_DivSmartCard1Clk = 5,
AnnaBridge 171:3a7713b1edbc 705 kCLOCK_DivAhbClk = 32,
AnnaBridge 171:3a7713b1edbc 706 kCLOCK_DivClkOut = 33,
AnnaBridge 171:3a7713b1edbc 707 kCLOCK_DivFrohfClk = 34,
AnnaBridge 171:3a7713b1edbc 708 kCLOCK_DivSpifiClk = 36,
AnnaBridge 171:3a7713b1edbc 709 kCLOCK_DivAdcAsyncClk = 37,
AnnaBridge 171:3a7713b1edbc 710 kCLOCK_DivUsb0Clk = 38,
AnnaBridge 171:3a7713b1edbc 711 kCLOCK_DivUsb1Clk = 39,
AnnaBridge 171:3a7713b1edbc 712 kCLOCK_DivFrg = 40,
AnnaBridge 171:3a7713b1edbc 713 kCLOCK_DivDmicClk = 42,
AnnaBridge 171:3a7713b1edbc 714 kCLOCK_DivMClk = 43,
AnnaBridge 171:3a7713b1edbc 715 kCLOCK_DivLcdClk = 44,
AnnaBridge 171:3a7713b1edbc 716 kCLOCK_DivSctClk = 45,
AnnaBridge 171:3a7713b1edbc 717 kCLOCK_DivEmcClk = 46,
AnnaBridge 171:3a7713b1edbc 718 kCLOCK_DivSdioClk = 47
AnnaBridge 171:3a7713b1edbc 719 } clock_div_name_t;
AnnaBridge 171:3a7713b1edbc 720
AnnaBridge 171:3a7713b1edbc 721 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 722 * API
AnnaBridge 171:3a7713b1edbc 723 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 724
AnnaBridge 171:3a7713b1edbc 725 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 726 extern "C" {
AnnaBridge 171:3a7713b1edbc 727 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 728
AnnaBridge 171:3a7713b1edbc 729 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
AnnaBridge 171:3a7713b1edbc 730 {
AnnaBridge 171:3a7713b1edbc 731 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
AnnaBridge 171:3a7713b1edbc 732 if (index < 3)
AnnaBridge 171:3a7713b1edbc 733 {
AnnaBridge 171:3a7713b1edbc 734 SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
AnnaBridge 171:3a7713b1edbc 735 }
AnnaBridge 171:3a7713b1edbc 736 else
AnnaBridge 171:3a7713b1edbc 737 {
AnnaBridge 171:3a7713b1edbc 738 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(1);
AnnaBridge 171:3a7713b1edbc 739 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
AnnaBridge 171:3a7713b1edbc 740 }
AnnaBridge 171:3a7713b1edbc 741 }
AnnaBridge 171:3a7713b1edbc 742
AnnaBridge 171:3a7713b1edbc 743 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
AnnaBridge 171:3a7713b1edbc 744 {
AnnaBridge 171:3a7713b1edbc 745 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
AnnaBridge 171:3a7713b1edbc 746 if (index < 3)
AnnaBridge 171:3a7713b1edbc 747 {
AnnaBridge 171:3a7713b1edbc 748 SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
AnnaBridge 171:3a7713b1edbc 749 }
AnnaBridge 171:3a7713b1edbc 750 else
AnnaBridge 171:3a7713b1edbc 751 {
AnnaBridge 171:3a7713b1edbc 752 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
AnnaBridge 171:3a7713b1edbc 753 SYSCON->ASYNCAPBCTRL = SYSCON_ASYNCAPBCTRL_ENABLE(0);
AnnaBridge 171:3a7713b1edbc 754
AnnaBridge 171:3a7713b1edbc 755 }
AnnaBridge 171:3a7713b1edbc 756 }
AnnaBridge 171:3a7713b1edbc 757 /**
AnnaBridge 171:3a7713b1edbc 758 * @brief FLASH Access time definitions
AnnaBridge 171:3a7713b1edbc 759 */
AnnaBridge 171:3a7713b1edbc 760 typedef enum _clock_flashtim
AnnaBridge 171:3a7713b1edbc 761 {
AnnaBridge 171:3a7713b1edbc 762 kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clocks */
AnnaBridge 171:3a7713b1edbc 763 kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */
AnnaBridge 171:3a7713b1edbc 764 kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */
AnnaBridge 171:3a7713b1edbc 765 kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */
AnnaBridge 171:3a7713b1edbc 766 kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */
AnnaBridge 171:3a7713b1edbc 767 kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */
AnnaBridge 171:3a7713b1edbc 768 kCLOCK_Flash7Cycle, /*!< Flash accesses use 7 CPU clocks */
AnnaBridge 171:3a7713b1edbc 769 kCLOCK_Flash8Cycle, /*!< Flash accesses use 8 CPU clocks */
AnnaBridge 171:3a7713b1edbc 770 kCLOCK_Flash9Cycle /*!< Flash accesses use 9 CPU clocks */
AnnaBridge 171:3a7713b1edbc 771 } clock_flashtim_t;
AnnaBridge 171:3a7713b1edbc 772
AnnaBridge 171:3a7713b1edbc 773 /**
AnnaBridge 171:3a7713b1edbc 774 * @brief Set FLASH memory access time in clocks
AnnaBridge 171:3a7713b1edbc 775 * @param clks : Clock cycles for FLASH access
AnnaBridge 171:3a7713b1edbc 776 * @return Nothing
AnnaBridge 171:3a7713b1edbc 777 */
AnnaBridge 171:3a7713b1edbc 778 static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)
AnnaBridge 171:3a7713b1edbc 779 {
AnnaBridge 171:3a7713b1edbc 780 uint32_t tmp;
AnnaBridge 171:3a7713b1edbc 781
AnnaBridge 171:3a7713b1edbc 782 tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);
AnnaBridge 171:3a7713b1edbc 783
AnnaBridge 171:3a7713b1edbc 784 /* Don't alter lower bits */
AnnaBridge 171:3a7713b1edbc 785 SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);
AnnaBridge 171:3a7713b1edbc 786 }
AnnaBridge 171:3a7713b1edbc 787
AnnaBridge 171:3a7713b1edbc 788 /**
AnnaBridge 171:3a7713b1edbc 789 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
AnnaBridge 171:3a7713b1edbc 790 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
AnnaBridge 171:3a7713b1edbc 791 * enabled.
AnnaBridge 171:3a7713b1edbc 792 * @param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ)
AnnaBridge 171:3a7713b1edbc 793 * @return returns success or fail status.
AnnaBridge 171:3a7713b1edbc 794 */
AnnaBridge 171:3a7713b1edbc 795 status_t CLOCK_SetupFROClocking(uint32_t iFreq);
AnnaBridge 171:3a7713b1edbc 796 /**
AnnaBridge 171:3a7713b1edbc 797 * @brief Configure the clock selection muxes.
AnnaBridge 171:3a7713b1edbc 798 * @param connection : Clock to be configured.
AnnaBridge 171:3a7713b1edbc 799 * @return Nothing
AnnaBridge 171:3a7713b1edbc 800 */
AnnaBridge 171:3a7713b1edbc 801 void CLOCK_AttachClk(clock_attach_id_t connection);
AnnaBridge 171:3a7713b1edbc 802 /**
AnnaBridge 171:3a7713b1edbc 803 * @brief Setup peripheral clock dividers.
AnnaBridge 171:3a7713b1edbc 804 * @param div_name : Clock divider name
AnnaBridge 171:3a7713b1edbc 805 * @param divided_by_value: Value to be divided
AnnaBridge 171:3a7713b1edbc 806 * @param reset : Whether to reset the divider counter.
AnnaBridge 171:3a7713b1edbc 807 * @return Nothing
AnnaBridge 171:3a7713b1edbc 808 */
AnnaBridge 171:3a7713b1edbc 809 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
AnnaBridge 171:3a7713b1edbc 810 /**
AnnaBridge 171:3a7713b1edbc 811 * @brief Set the flash wait states for the input freuqency.
AnnaBridge 171:3a7713b1edbc 812 * @param iFreq : Input frequency
AnnaBridge 171:3a7713b1edbc 813 * @return Nothing
AnnaBridge 171:3a7713b1edbc 814 */
AnnaBridge 171:3a7713b1edbc 815 void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
AnnaBridge 171:3a7713b1edbc 816 /*! @brief Return Frequency of selected clock
AnnaBridge 171:3a7713b1edbc 817 * @return Frequency of selected clock
AnnaBridge 171:3a7713b1edbc 818 */
AnnaBridge 171:3a7713b1edbc 819 uint32_t CLOCK_GetFreq(clock_name_t clockName);
AnnaBridge 171:3a7713b1edbc 820 /*! @brief Return Frequency of FRO 12MHz
AnnaBridge 171:3a7713b1edbc 821 * @return Frequency of FRO 12MHz
AnnaBridge 171:3a7713b1edbc 822 */
AnnaBridge 171:3a7713b1edbc 823 uint32_t CLOCK_GetFro12MFreq(void);
AnnaBridge 171:3a7713b1edbc 824 /*! @brief Return Frequency of ClockOut
AnnaBridge 171:3a7713b1edbc 825 * @return Frequency of ClockOut
AnnaBridge 171:3a7713b1edbc 826 */
AnnaBridge 171:3a7713b1edbc 827 uint32_t CLOCK_GetClockOutClkFreq(void);
AnnaBridge 171:3a7713b1edbc 828 /*! @brief Return Frequency of Spifi Clock
AnnaBridge 171:3a7713b1edbc 829 * @return Frequency of Spifi.
AnnaBridge 171:3a7713b1edbc 830 */
AnnaBridge 171:3a7713b1edbc 831 uint32_t CLOCK_GetSpifiClkFreq(void);
AnnaBridge 171:3a7713b1edbc 832 /*! @brief Return Frequency of Adc Clock
AnnaBridge 171:3a7713b1edbc 833 * @return Frequency of Adc Clock.
AnnaBridge 171:3a7713b1edbc 834 */
AnnaBridge 171:3a7713b1edbc 835 uint32_t CLOCK_GetAdcClkFreq(void);
AnnaBridge 171:3a7713b1edbc 836 /*! @brief Return Frequency of Usb0 Clock
AnnaBridge 171:3a7713b1edbc 837 * @return Frequency of Usb0 Clock.
AnnaBridge 171:3a7713b1edbc 838 */
AnnaBridge 171:3a7713b1edbc 839 uint32_t CLOCK_GetUsb0ClkFreq(void);
AnnaBridge 171:3a7713b1edbc 840 /*! @brief Return Frequency of Usb1 Clock
AnnaBridge 171:3a7713b1edbc 841 * @return Frequency of Usb1 Clock.
AnnaBridge 171:3a7713b1edbc 842 */
AnnaBridge 171:3a7713b1edbc 843 uint32_t CLOCK_GetUsb1ClkFreq(void);
AnnaBridge 171:3a7713b1edbc 844 /*! @brief Return Frequency of MClk Clock
AnnaBridge 171:3a7713b1edbc 845 * @return Frequency of MClk Clock.
AnnaBridge 171:3a7713b1edbc 846 */
AnnaBridge 171:3a7713b1edbc 847 uint32_t CLOCK_GetMclkClkFreq(void);
AnnaBridge 171:3a7713b1edbc 848 /*! @brief Return Frequency of SCTimer Clock
AnnaBridge 171:3a7713b1edbc 849 * @return Frequency of SCTimer Clock.
AnnaBridge 171:3a7713b1edbc 850 */
AnnaBridge 171:3a7713b1edbc 851 uint32_t CLOCK_GetSctClkFreq(void);
AnnaBridge 171:3a7713b1edbc 852 /*! @brief Return Frequency of SDIO Clock
AnnaBridge 171:3a7713b1edbc 853 * @return Frequency of SDIO Clock.
AnnaBridge 171:3a7713b1edbc 854 */
AnnaBridge 171:3a7713b1edbc 855 uint32_t CLOCK_GetSdioClkFreq(void);
AnnaBridge 171:3a7713b1edbc 856 /*! @brief Return Frequency of LCD Clock
AnnaBridge 171:3a7713b1edbc 857 * @return Frequency of LCD Clock.
AnnaBridge 171:3a7713b1edbc 858 */
AnnaBridge 171:3a7713b1edbc 859 uint32_t CLOCK_GetLcdClkFreq(void);
AnnaBridge 171:3a7713b1edbc 860 /*! @brief Return Frequency of LCD CLKIN Clock
AnnaBridge 171:3a7713b1edbc 861 * @return Frequency of LCD CLKIN Clock.
AnnaBridge 171:3a7713b1edbc 862 */
AnnaBridge 171:3a7713b1edbc 863 uint32_t CLOCK_GetLcdClkIn(void);
AnnaBridge 171:3a7713b1edbc 864 /*! @brief Return Frequency of External Clock
AnnaBridge 171:3a7713b1edbc 865 * @return Frequency of External Clock. If no external clock is used returns 0.
AnnaBridge 171:3a7713b1edbc 866 */
AnnaBridge 171:3a7713b1edbc 867 uint32_t CLOCK_GetExtClkFreq(void);
AnnaBridge 171:3a7713b1edbc 868 /*! @brief Return Frequency of Watchdog Oscillator
AnnaBridge 171:3a7713b1edbc 869 * @return Frequency of Watchdog Oscillator
AnnaBridge 171:3a7713b1edbc 870 */
AnnaBridge 171:3a7713b1edbc 871 uint32_t CLOCK_GetWdtOscFreq(void);
AnnaBridge 171:3a7713b1edbc 872 /*! @brief Return Frequency of High-Freq output of FRO
AnnaBridge 171:3a7713b1edbc 873 * @return Frequency of High-Freq output of FRO
AnnaBridge 171:3a7713b1edbc 874 */
AnnaBridge 171:3a7713b1edbc 875 uint32_t CLOCK_GetFroHfFreq(void);
AnnaBridge 171:3a7713b1edbc 876 /*! @brief Return Frequency of PLL
AnnaBridge 171:3a7713b1edbc 877 * @return Frequency of PLL
AnnaBridge 171:3a7713b1edbc 878 */
AnnaBridge 171:3a7713b1edbc 879 uint32_t CLOCK_GetPllOutFreq(void);
AnnaBridge 171:3a7713b1edbc 880 /*! @brief Return Frequency of USB PLL
AnnaBridge 171:3a7713b1edbc 881 * @return Frequency of PLL
AnnaBridge 171:3a7713b1edbc 882 */
AnnaBridge 171:3a7713b1edbc 883 uint32_t CLOCK_GetUsbPllOutFreq(void);
AnnaBridge 171:3a7713b1edbc 884 /*! @brief Return Frequency of AUDIO PLL
AnnaBridge 171:3a7713b1edbc 885 * @return Frequency of PLL
AnnaBridge 171:3a7713b1edbc 886 */
AnnaBridge 171:3a7713b1edbc 887 uint32_t CLOCK_GetAudioPllOutFreq(void);
AnnaBridge 171:3a7713b1edbc 888 /*! @brief Return Frequency of 32kHz osc
AnnaBridge 171:3a7713b1edbc 889 * @return Frequency of 32kHz osc
AnnaBridge 171:3a7713b1edbc 890 */
AnnaBridge 171:3a7713b1edbc 891 uint32_t CLOCK_GetOsc32KFreq(void);
AnnaBridge 171:3a7713b1edbc 892 /*! @brief Return Frequency of Core System
AnnaBridge 171:3a7713b1edbc 893 * @return Frequency of Core System
AnnaBridge 171:3a7713b1edbc 894 */
AnnaBridge 171:3a7713b1edbc 895 uint32_t CLOCK_GetCoreSysClkFreq(void);
AnnaBridge 171:3a7713b1edbc 896 /*! @brief Return Frequency of I2S MCLK Clock
AnnaBridge 171:3a7713b1edbc 897 * @return Frequency of I2S MCLK Clock
AnnaBridge 171:3a7713b1edbc 898 */
AnnaBridge 171:3a7713b1edbc 899 uint32_t CLOCK_GetI2SMClkFreq(void);
AnnaBridge 171:3a7713b1edbc 900 /*! @brief Return Frequency of Flexcomm functional Clock
AnnaBridge 171:3a7713b1edbc 901 * @return Frequency of Flexcomm functional Clock
AnnaBridge 171:3a7713b1edbc 902 */
AnnaBridge 171:3a7713b1edbc 903 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
AnnaBridge 171:3a7713b1edbc 904 /*! @brief Return Asynchronous APB Clock source
AnnaBridge 171:3a7713b1edbc 905 * @return Asynchronous APB CLock source
AnnaBridge 171:3a7713b1edbc 906 */
AnnaBridge 171:3a7713b1edbc 907 __STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
AnnaBridge 171:3a7713b1edbc 908 {
AnnaBridge 171:3a7713b1edbc 909 return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3);
AnnaBridge 171:3a7713b1edbc 910 }
AnnaBridge 171:3a7713b1edbc 911 /*! @brief Return Frequency of Asynchronous APB Clock
AnnaBridge 171:3a7713b1edbc 912 * @return Frequency of Asynchronous APB Clock Clock
AnnaBridge 171:3a7713b1edbc 913 */
AnnaBridge 171:3a7713b1edbc 914 uint32_t CLOCK_GetAsyncApbClkFreq(void);
AnnaBridge 171:3a7713b1edbc 915 /*! @brief Return Audio PLL input clock rate
AnnaBridge 171:3a7713b1edbc 916 * @return Audio PLL input clock rate
AnnaBridge 171:3a7713b1edbc 917 */
AnnaBridge 171:3a7713b1edbc 918 uint32_t CLOCK_GetAudioPLLInClockRate(void);
AnnaBridge 171:3a7713b1edbc 919 /*! @brief Return System PLL input clock rate
AnnaBridge 171:3a7713b1edbc 920 * @return System PLL input clock rate
AnnaBridge 171:3a7713b1edbc 921 */
AnnaBridge 171:3a7713b1edbc 922 uint32_t CLOCK_GetSystemPLLInClockRate(void);
AnnaBridge 171:3a7713b1edbc 923
AnnaBridge 171:3a7713b1edbc 924 /*! @brief Return System PLL output clock rate
AnnaBridge 171:3a7713b1edbc 925 * @param recompute : Forces a PLL rate recomputation if true
AnnaBridge 171:3a7713b1edbc 926 * @return System PLL output clock rate
AnnaBridge 171:3a7713b1edbc 927 * @note The PLL rate is cached in the driver in a variable as
AnnaBridge 171:3a7713b1edbc 928 * the rate computation function can take some time to perform. It
AnnaBridge 171:3a7713b1edbc 929 * is recommended to use 'false' with the 'recompute' parameter.
AnnaBridge 171:3a7713b1edbc 930 */
AnnaBridge 171:3a7713b1edbc 931 uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
AnnaBridge 171:3a7713b1edbc 932
AnnaBridge 171:3a7713b1edbc 933 /*! @brief Return System AUDIO PLL output clock rate
AnnaBridge 171:3a7713b1edbc 934 * @param recompute : Forces a AUDIO PLL rate recomputation if true
AnnaBridge 171:3a7713b1edbc 935 * @return System AUDIO PLL output clock rate
AnnaBridge 171:3a7713b1edbc 936 * @note The AUDIO PLL rate is cached in the driver in a variable as
AnnaBridge 171:3a7713b1edbc 937 * the rate computation function can take some time to perform. It
AnnaBridge 171:3a7713b1edbc 938 * is recommended to use 'false' with the 'recompute' parameter.
AnnaBridge 171:3a7713b1edbc 939 */
AnnaBridge 171:3a7713b1edbc 940 uint32_t CLOCK_GetAudioPLLOutClockRate(bool recompute);
AnnaBridge 171:3a7713b1edbc 941
AnnaBridge 171:3a7713b1edbc 942 /*! @brief Return System USB PLL output clock rate
AnnaBridge 171:3a7713b1edbc 943 * @param recompute : Forces a USB PLL rate recomputation if true
AnnaBridge 171:3a7713b1edbc 944 * @return System USB PLL output clock rate
AnnaBridge 171:3a7713b1edbc 945 * @note The USB PLL rate is cached in the driver in a variable as
AnnaBridge 171:3a7713b1edbc 946 * the rate computation function can take some time to perform. It
AnnaBridge 171:3a7713b1edbc 947 * is recommended to use 'false' with the 'recompute' parameter.
AnnaBridge 171:3a7713b1edbc 948 */
AnnaBridge 171:3a7713b1edbc 949 uint32_t CLOCK_GetUSbPLLOutClockRate(bool recompute);
AnnaBridge 171:3a7713b1edbc 950
AnnaBridge 171:3a7713b1edbc 951 /*! @brief Enables and disables PLL bypass mode
AnnaBridge 171:3a7713b1edbc 952 * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
AnnaBridge 171:3a7713b1edbc 953 * @return System PLL output clock rate
AnnaBridge 171:3a7713b1edbc 954 */
AnnaBridge 171:3a7713b1edbc 955 __STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
AnnaBridge 171:3a7713b1edbc 956 {
AnnaBridge 171:3a7713b1edbc 957 if (bypass)
AnnaBridge 171:3a7713b1edbc 958 {
AnnaBridge 171:3a7713b1edbc 959 SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
AnnaBridge 171:3a7713b1edbc 960 }
AnnaBridge 171:3a7713b1edbc 961 else
AnnaBridge 171:3a7713b1edbc 962 {
AnnaBridge 171:3a7713b1edbc 963 SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
AnnaBridge 171:3a7713b1edbc 964 }
AnnaBridge 171:3a7713b1edbc 965 }
AnnaBridge 171:3a7713b1edbc 966
AnnaBridge 171:3a7713b1edbc 967 /*! @brief Check if PLL is locked or not
AnnaBridge 171:3a7713b1edbc 968 * @return true if the PLL is locked, false if not locked
AnnaBridge 171:3a7713b1edbc 969 */
AnnaBridge 171:3a7713b1edbc 970 __STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
AnnaBridge 171:3a7713b1edbc 971 {
AnnaBridge 171:3a7713b1edbc 972 return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0);
AnnaBridge 171:3a7713b1edbc 973 }
AnnaBridge 171:3a7713b1edbc 974
AnnaBridge 171:3a7713b1edbc 975 /*! @brief Check if USB PLL is locked or not
AnnaBridge 171:3a7713b1edbc 976 * @return true if the USB PLL is locked, false if not locked
AnnaBridge 171:3a7713b1edbc 977 */
AnnaBridge 171:3a7713b1edbc 978 __STATIC_INLINE bool CLOCK_IsUsbPLLLocked(void)
AnnaBridge 171:3a7713b1edbc 979 {
AnnaBridge 171:3a7713b1edbc 980 return (bool)((SYSCON->USBPLLSTAT & SYSCON_USBPLLSTAT_LOCK_MASK) != 0);
AnnaBridge 171:3a7713b1edbc 981 }
AnnaBridge 171:3a7713b1edbc 982
AnnaBridge 171:3a7713b1edbc 983 /*! @brief Check if AUDIO PLL is locked or not
AnnaBridge 171:3a7713b1edbc 984 * @return true if the AUDIO PLL is locked, false if not locked
AnnaBridge 171:3a7713b1edbc 985 */
AnnaBridge 171:3a7713b1edbc 986 __STATIC_INLINE bool CLOCK_IsAudioPLLLocked(void)
AnnaBridge 171:3a7713b1edbc 987 {
AnnaBridge 171:3a7713b1edbc 988 return (bool)((SYSCON->AUDPLLSTAT & SYSCON_AUDPLLSTAT_LOCK_MASK) != 0);
AnnaBridge 171:3a7713b1edbc 989 }
AnnaBridge 171:3a7713b1edbc 990
AnnaBridge 171:3a7713b1edbc 991 /*! @brief Enables and disables SYS OSC
AnnaBridge 171:3a7713b1edbc 992 * @brief enable : true to enable SYS OSC, false to disable SYS OSC
AnnaBridge 171:3a7713b1edbc 993 */
AnnaBridge 171:3a7713b1edbc 994 __STATIC_INLINE void CLOCK_Enable_SysOsc(bool enable)
AnnaBridge 171:3a7713b1edbc 995 {
AnnaBridge 171:3a7713b1edbc 996 if(enable)
AnnaBridge 171:3a7713b1edbc 997 {
AnnaBridge 171:3a7713b1edbc 998 SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
AnnaBridge 171:3a7713b1edbc 999 SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
AnnaBridge 171:3a7713b1edbc 1000 }
AnnaBridge 171:3a7713b1edbc 1001
AnnaBridge 171:3a7713b1edbc 1002 else
AnnaBridge 171:3a7713b1edbc 1003 {
AnnaBridge 171:3a7713b1edbc 1004 SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
AnnaBridge 171:3a7713b1edbc 1005 SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
AnnaBridge 171:3a7713b1edbc 1006
AnnaBridge 171:3a7713b1edbc 1007 }
AnnaBridge 171:3a7713b1edbc 1008 }
AnnaBridge 171:3a7713b1edbc 1009
AnnaBridge 171:3a7713b1edbc 1010 /*! @brief Store the current PLL rate
AnnaBridge 171:3a7713b1edbc 1011 * @param rate: Current rate of the PLL
AnnaBridge 171:3a7713b1edbc 1012 * @return Nothing
AnnaBridge 171:3a7713b1edbc 1013 **/
AnnaBridge 171:3a7713b1edbc 1014 void CLOCK_SetStoredPLLClockRate(uint32_t rate);
AnnaBridge 171:3a7713b1edbc 1015
AnnaBridge 171:3a7713b1edbc 1016 /*! @brief Store the current AUDIO PLL rate
AnnaBridge 171:3a7713b1edbc 1017 * @param rate: Current rate of the PLL
AnnaBridge 171:3a7713b1edbc 1018 * @return Nothing
AnnaBridge 171:3a7713b1edbc 1019 **/
AnnaBridge 171:3a7713b1edbc 1020 void CLOCK_SetStoredAudioPLLClockRate(uint32_t rate);
AnnaBridge 171:3a7713b1edbc 1021
AnnaBridge 171:3a7713b1edbc 1022 /*! @brief PLL configuration structure flags for 'flags' field
AnnaBridge 171:3a7713b1edbc 1023 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
AnnaBridge 171:3a7713b1edbc 1024 *
AnnaBridge 171:3a7713b1edbc 1025 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
AnnaBridge 171:3a7713b1edbc 1026 * configuration structure must be assigned with the expected PLL frequency. If the
AnnaBridge 171:3a7713b1edbc 1027 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
AnnaBridge 171:3a7713b1edbc 1028 * function and the driver will determine the PLL rate from the currently selected
AnnaBridge 171:3a7713b1edbc 1029 * PLL source. This flag might be used to configure the PLL input clock more accurately
AnnaBridge 171:3a7713b1edbc 1030 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
AnnaBridge 171:3a7713b1edbc 1031 *
AnnaBridge 171:3a7713b1edbc 1032 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
AnnaBridge 171:3a7713b1edbc 1033 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
AnnaBridge 171:3a7713b1edbc 1034 * are not used.<br>
AnnaBridge 171:3a7713b1edbc 1035 */
AnnaBridge 171:3a7713b1edbc 1036 #define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */
AnnaBridge 171:3a7713b1edbc 1037 #define PLL_CONFIGFLAG_FORCENOFRACT \
AnnaBridge 171:3a7713b1edbc 1038 (1 \
AnnaBridge 171:3a7713b1edbc 1039 << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \
AnnaBridge 171:3a7713b1edbc 1040 \ \ \ \
AnnaBridge 171:3a7713b1edbc 1041 \ \ \ \ \ \
AnnaBridge 171:3a7713b1edbc 1042 \ \ \ \ \ \ \ \
AnnaBridge 171:3a7713b1edbc 1043 hardware */
AnnaBridge 171:3a7713b1edbc 1044
AnnaBridge 171:3a7713b1edbc 1045 /*! @brief PLL configuration structure
AnnaBridge 171:3a7713b1edbc 1046 *
AnnaBridge 171:3a7713b1edbc 1047 * This structure can be used to configure the settings for a PLL
AnnaBridge 171:3a7713b1edbc 1048 * setup structure. Fill in the desired configuration for the PLL
AnnaBridge 171:3a7713b1edbc 1049 * and call the PLL setup function to fill in a PLL setup structure.
AnnaBridge 171:3a7713b1edbc 1050 */
AnnaBridge 171:3a7713b1edbc 1051 typedef struct _pll_config
AnnaBridge 171:3a7713b1edbc 1052 {
AnnaBridge 171:3a7713b1edbc 1053 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
AnnaBridge 171:3a7713b1edbc 1054 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
AnnaBridge 171:3a7713b1edbc 1055 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
AnnaBridge 171:3a7713b1edbc 1056 } pll_config_t;
AnnaBridge 171:3a7713b1edbc 1057
AnnaBridge 171:3a7713b1edbc 1058 /*! @brief PLL setup structure flags for 'flags' field
AnnaBridge 171:3a7713b1edbc 1059 * These flags control how the PLL setup function sets up the PLL
AnnaBridge 171:3a7713b1edbc 1060 */
AnnaBridge 171:3a7713b1edbc 1061 #define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */
AnnaBridge 171:3a7713b1edbc 1062 #define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
AnnaBridge 171:3a7713b1edbc 1063 #define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */
AnnaBridge 171:3a7713b1edbc 1064
AnnaBridge 171:3a7713b1edbc 1065 /*! @brief PLL setup structure
AnnaBridge 171:3a7713b1edbc 1066 * This structure can be used to pre-build a PLL setup configuration
AnnaBridge 171:3a7713b1edbc 1067 * at run-time and quickly set the PLL to the configuration. It can be
AnnaBridge 171:3a7713b1edbc 1068 * populated with the PLL setup function. If powering up or waiting
AnnaBridge 171:3a7713b1edbc 1069 * for PLL lock, the PLL input clock source should be configured prior
AnnaBridge 171:3a7713b1edbc 1070 * to PLL setup.
AnnaBridge 171:3a7713b1edbc 1071 */
AnnaBridge 171:3a7713b1edbc 1072 typedef struct _pll_setup
AnnaBridge 171:3a7713b1edbc 1073 {
AnnaBridge 171:3a7713b1edbc 1074 uint32_t pllctrl; /*!< PLL control register SYSPLLCTRL */
AnnaBridge 171:3a7713b1edbc 1075 uint32_t pllndec; /*!< PLL NDEC register SYSPLLNDEC */
AnnaBridge 171:3a7713b1edbc 1076 uint32_t pllpdec; /*!< PLL PDEC register SYSPLLPDEC */
AnnaBridge 171:3a7713b1edbc 1077 uint32_t pllmdec; /*!< PLL MDEC registers SYSPLLPDEC */
AnnaBridge 171:3a7713b1edbc 1078 uint32_t pllRate; /*!< Acutal PLL rate */
AnnaBridge 171:3a7713b1edbc 1079 uint32_t audpllfrac; /*!< only aduio PLL has this function*/
AnnaBridge 171:3a7713b1edbc 1080 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
AnnaBridge 171:3a7713b1edbc 1081 } pll_setup_t;
AnnaBridge 171:3a7713b1edbc 1082
AnnaBridge 171:3a7713b1edbc 1083 /*! @brief PLL status definitions
AnnaBridge 171:3a7713b1edbc 1084 */
AnnaBridge 171:3a7713b1edbc 1085 typedef enum _pll_error
AnnaBridge 171:3a7713b1edbc 1086 {
AnnaBridge 171:3a7713b1edbc 1087 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
AnnaBridge 171:3a7713b1edbc 1088 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
AnnaBridge 171:3a7713b1edbc 1089 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
AnnaBridge 171:3a7713b1edbc 1090 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
AnnaBridge 171:3a7713b1edbc 1091 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
AnnaBridge 171:3a7713b1edbc 1092 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Requested output rate isn't possible */
AnnaBridge 171:3a7713b1edbc 1093 kStatus_PLL_CCOTooLow = MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Requested CCO rate isn't possible */
AnnaBridge 171:3a7713b1edbc 1094 kStatus_PLL_CCOTooHigh = MAKE_STATUS(kStatusGroup_Generic, 7) /*!< Requested CCO rate isn't possible */
AnnaBridge 171:3a7713b1edbc 1095 } pll_error_t;
AnnaBridge 171:3a7713b1edbc 1096
AnnaBridge 171:3a7713b1edbc 1097 /*! @brief USB clock source definition. */
AnnaBridge 171:3a7713b1edbc 1098 typedef enum _clock_usb_src
AnnaBridge 171:3a7713b1edbc 1099 {
AnnaBridge 171:3a7713b1edbc 1100 kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */
AnnaBridge 171:3a7713b1edbc 1101 kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */
AnnaBridge 171:3a7713b1edbc 1102 kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
AnnaBridge 171:3a7713b1edbc 1103 kCLOCK_UsbSrcUsbPll = (uint32_t)kCLOCK_UsbPll, /*!< Use USB PLL clock. */
AnnaBridge 171:3a7713b1edbc 1104
AnnaBridge 171:3a7713b1edbc 1105 kCLOCK_UsbSrcNone = SYSCON_USB0CLKSEL_SEL(7) /*!< Use None, this may be selected in order to reduce power when no output is needed.. */
AnnaBridge 171:3a7713b1edbc 1106 } clock_usb_src_t;
AnnaBridge 171:3a7713b1edbc 1107
AnnaBridge 171:3a7713b1edbc 1108 /*! @brief USB PDEL Divider. */
AnnaBridge 171:3a7713b1edbc 1109 typedef enum _usb_pll_psel
AnnaBridge 171:3a7713b1edbc 1110 {
AnnaBridge 171:3a7713b1edbc 1111 pSel_Divide_1 = 0U,
AnnaBridge 171:3a7713b1edbc 1112 pSel_Divide_2,
AnnaBridge 171:3a7713b1edbc 1113 pSel_Divide_4,
AnnaBridge 171:3a7713b1edbc 1114 pSel_Divide_8
AnnaBridge 171:3a7713b1edbc 1115 }usb_pll_psel;
AnnaBridge 171:3a7713b1edbc 1116
AnnaBridge 171:3a7713b1edbc 1117 /*! @brief PLL setup structure
AnnaBridge 171:3a7713b1edbc 1118 * This structure can be used to pre-build a USB PLL setup configuration
AnnaBridge 171:3a7713b1edbc 1119 * at run-time and quickly set the usb PLL to the configuration. It can be
AnnaBridge 171:3a7713b1edbc 1120 * populated with the USB PLL setup function. If powering up or waiting
AnnaBridge 171:3a7713b1edbc 1121 * for USB PLL lock, the PLL input clock source should be configured prior
AnnaBridge 171:3a7713b1edbc 1122 * to USB PLL setup.
AnnaBridge 171:3a7713b1edbc 1123 */
AnnaBridge 171:3a7713b1edbc 1124 typedef struct _usb_pll_setup
AnnaBridge 171:3a7713b1edbc 1125 {
AnnaBridge 171:3a7713b1edbc 1126 uint8_t msel; /*!< USB PLL control register msel:1U-256U */
AnnaBridge 171:3a7713b1edbc 1127 uint8_t psel; /*!< USB PLL control register psel:only support inter 1U 2U 4U 8U */
AnnaBridge 171:3a7713b1edbc 1128 uint8_t nsel; /*!< USB PLL control register nsel:only suppoet inter 1U 2U 3U 4U */
AnnaBridge 171:3a7713b1edbc 1129 bool direct; /*!< USB PLL CCO output control */
AnnaBridge 171:3a7713b1edbc 1130 bool bypass; /*!< USB PLL inout clock bypass control */
AnnaBridge 171:3a7713b1edbc 1131 bool fbsel; /*!< USB PLL ineter mode and non-integer mode control*/
AnnaBridge 171:3a7713b1edbc 1132 uint32_t inputRate; /*!< USB PLL input rate */
AnnaBridge 171:3a7713b1edbc 1133 } usb_pll_setup_t;
AnnaBridge 171:3a7713b1edbc 1134
AnnaBridge 171:3a7713b1edbc 1135 /*! @brief Return System PLL output clock rate from setup structure
AnnaBridge 171:3a7713b1edbc 1136 * @param pSetup : Pointer to a PLL setup structure
AnnaBridge 171:3a7713b1edbc 1137 * @return System PLL output clock rate the setup structure will generate
AnnaBridge 171:3a7713b1edbc 1138 */
AnnaBridge 171:3a7713b1edbc 1139 uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
AnnaBridge 171:3a7713b1edbc 1140
AnnaBridge 171:3a7713b1edbc 1141 /*! @brief Return System AUDIO PLL output clock rate from setup structure
AnnaBridge 171:3a7713b1edbc 1142 * @param pSetup : Pointer to a PLL setup structure
AnnaBridge 171:3a7713b1edbc 1143 * @return System PLL output clock rate the setup structure will generate
AnnaBridge 171:3a7713b1edbc 1144 */
AnnaBridge 171:3a7713b1edbc 1145 uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
AnnaBridge 171:3a7713b1edbc 1146
AnnaBridge 171:3a7713b1edbc 1147 /*! @brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure
AnnaBridge 171:3a7713b1edbc 1148 * @param pSetup : Pointer to a PLL setup structure
AnnaBridge 171:3a7713b1edbc 1149 * @return System PLL output clock rate the setup structure will generate
AnnaBridge 171:3a7713b1edbc 1150 */
AnnaBridge 171:3a7713b1edbc 1151 uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup);
AnnaBridge 171:3a7713b1edbc 1152
AnnaBridge 171:3a7713b1edbc 1153 /*! @brief Return System USB PLL output clock rate from setup structure
AnnaBridge 171:3a7713b1edbc 1154 * @param pSetup : Pointer to a PLL setup structure
AnnaBridge 171:3a7713b1edbc 1155 * @return System PLL output clock rate the setup structure will generate
AnnaBridge 171:3a7713b1edbc 1156 */
AnnaBridge 171:3a7713b1edbc 1157 uint32_t CLOCK_GetUsbPLLOutFromSetup(const usb_pll_setup_t *pSetup);
AnnaBridge 171:3a7713b1edbc 1158
AnnaBridge 171:3a7713b1edbc 1159 /*! @brief Set PLL output based on the passed PLL setup data
AnnaBridge 171:3a7713b1edbc 1160 * @param pControl : Pointer to populated PLL control structure to generate setup with
AnnaBridge 171:3a7713b1edbc 1161 * @param pSetup : Pointer to PLL setup structure to be filled
AnnaBridge 171:3a7713b1edbc 1162 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
AnnaBridge 171:3a7713b1edbc 1163 * @note Actual frequency for setup may vary from the desired frequency based on the
AnnaBridge 171:3a7713b1edbc 1164 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
AnnaBridge 171:3a7713b1edbc 1165 */
AnnaBridge 171:3a7713b1edbc 1166 pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
AnnaBridge 171:3a7713b1edbc 1167
AnnaBridge 171:3a7713b1edbc 1168 /*! @brief Set AUDIO PLL output based on the passed AUDIO PLL setup data
AnnaBridge 171:3a7713b1edbc 1169 * @param pControl : Pointer to populated PLL control structure to generate setup with
AnnaBridge 171:3a7713b1edbc 1170 * @param pSetup : Pointer to PLL setup structure to be filled
AnnaBridge 171:3a7713b1edbc 1171 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
AnnaBridge 171:3a7713b1edbc 1172 * @note Actual frequency for setup may vary from the desired frequency based on the
AnnaBridge 171:3a7713b1edbc 1173 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
AnnaBridge 171:3a7713b1edbc 1174 */
AnnaBridge 171:3a7713b1edbc 1175 pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
AnnaBridge 171:3a7713b1edbc 1176
AnnaBridge 171:3a7713b1edbc 1177 /*! @brief Set PLL output from PLL setup structure (precise frequency)
AnnaBridge 171:3a7713b1edbc 1178 * @param pSetup : Pointer to populated PLL setup structure
AnnaBridge 171:3a7713b1edbc 1179 * @param flagcfg : Flag configuration for PLL config structure
AnnaBridge 171:3a7713b1edbc 1180 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
AnnaBridge 171:3a7713b1edbc 1181 * @note This function will power off the PLL, setup the PLL with the
AnnaBridge 171:3a7713b1edbc 1182 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
AnnaBridge 171:3a7713b1edbc 1183 * and adjust system voltages to the new PLL rate. The function will not
AnnaBridge 171:3a7713b1edbc 1184 * alter any source clocks (ie, main systen clock) that may use the PLL,
AnnaBridge 171:3a7713b1edbc 1185 * so these should be setup prior to and after exiting the function.
AnnaBridge 171:3a7713b1edbc 1186 */
AnnaBridge 171:3a7713b1edbc 1187 pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
AnnaBridge 171:3a7713b1edbc 1188
AnnaBridge 171:3a7713b1edbc 1189 /*! @brief Set AUDIO PLL output from AUDIOPLL setup structure (precise frequency)
AnnaBridge 171:3a7713b1edbc 1190 * @param pSetup : Pointer to populated PLL setup structure
AnnaBridge 171:3a7713b1edbc 1191 * @param flagcfg : Flag configuration for PLL config structure
AnnaBridge 171:3a7713b1edbc 1192 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
AnnaBridge 171:3a7713b1edbc 1193 * @note This function will power off the PLL, setup the PLL with the
AnnaBridge 171:3a7713b1edbc 1194 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
AnnaBridge 171:3a7713b1edbc 1195 * and adjust system voltages to the new AUDIOPLL rate. The function will not
AnnaBridge 171:3a7713b1edbc 1196 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
AnnaBridge 171:3a7713b1edbc 1197 * so these should be setup prior to and after exiting the function.
AnnaBridge 171:3a7713b1edbc 1198 */
AnnaBridge 171:3a7713b1edbc 1199 pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
AnnaBridge 171:3a7713b1edbc 1200
AnnaBridge 171:3a7713b1edbc 1201 /*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise frequency)
AnnaBridge 171:3a7713b1edbc 1202 * @param pSetup : Pointer to populated PLL setup structure
AnnaBridge 171:3a7713b1edbc 1203 * @param flagcfg : Flag configuration for PLL config structure
AnnaBridge 171:3a7713b1edbc 1204 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
AnnaBridge 171:3a7713b1edbc 1205 * @note This function will power off the PLL, setup the PLL with the
AnnaBridge 171:3a7713b1edbc 1206 * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
AnnaBridge 171:3a7713b1edbc 1207 * and adjust system voltages to the new AUDIOPLL rate. The function will not
AnnaBridge 171:3a7713b1edbc 1208 * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
AnnaBridge 171:3a7713b1edbc 1209 * so these should be setup prior to and after exiting the function.
AnnaBridge 171:3a7713b1edbc 1210 */
AnnaBridge 171:3a7713b1edbc 1211 pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg);
AnnaBridge 171:3a7713b1edbc 1212
AnnaBridge 171:3a7713b1edbc 1213 /**
AnnaBridge 171:3a7713b1edbc 1214 * @brief Set PLL output from PLL setup structure (precise frequency)
AnnaBridge 171:3a7713b1edbc 1215 * @param pSetup : Pointer to populated PLL setup structure
AnnaBridge 171:3a7713b1edbc 1216 * @return kStatus_PLL_Success on success, or PLL setup error code
AnnaBridge 171:3a7713b1edbc 1217 * @note This function will power off the PLL, setup the PLL with the
AnnaBridge 171:3a7713b1edbc 1218 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
AnnaBridge 171:3a7713b1edbc 1219 * and adjust system voltages to the new PLL rate. The function will not
AnnaBridge 171:3a7713b1edbc 1220 * alter any source clocks (ie, main systen clock) that may use the PLL,
AnnaBridge 171:3a7713b1edbc 1221 * so these should be setup prior to and after exiting the function.
AnnaBridge 171:3a7713b1edbc 1222 */
AnnaBridge 171:3a7713b1edbc 1223 pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
AnnaBridge 171:3a7713b1edbc 1224
AnnaBridge 171:3a7713b1edbc 1225 /**
AnnaBridge 171:3a7713b1edbc 1226 * @brief Set Audio PLL output from Audio PLL setup structure (precise frequency)
AnnaBridge 171:3a7713b1edbc 1227 * @param pSetup : Pointer to populated PLL setup structure
AnnaBridge 171:3a7713b1edbc 1228 * @return kStatus_PLL_Success on success, or Audio PLL setup error code
AnnaBridge 171:3a7713b1edbc 1229 * @note This function will power off the PLL, setup the Audio PLL with the
AnnaBridge 171:3a7713b1edbc 1230 * new setup data, and then optionally powerup the PLL, wait for Audio PLL lock,
AnnaBridge 171:3a7713b1edbc 1231 * and adjust system voltages to the new PLL rate. The function will not
AnnaBridge 171:3a7713b1edbc 1232 * alter any source clocks (ie, main systen clock) that may use the Audio PLL,
AnnaBridge 171:3a7713b1edbc 1233 * so these should be setup prior to and after exiting the function.
AnnaBridge 171:3a7713b1edbc 1234 */
AnnaBridge 171:3a7713b1edbc 1235 pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup);
AnnaBridge 171:3a7713b1edbc 1236
AnnaBridge 171:3a7713b1edbc 1237 /**
AnnaBridge 171:3a7713b1edbc 1238 * @brief Set USB PLL output from USB PLL setup structure (precise frequency)
AnnaBridge 171:3a7713b1edbc 1239 * @param pSetup : Pointer to populated USB PLL setup structure
AnnaBridge 171:3a7713b1edbc 1240 * @return kStatus_PLL_Success on success, or USB PLL setup error code
AnnaBridge 171:3a7713b1edbc 1241 * @note This function will power off the USB PLL, setup the PLL with the
AnnaBridge 171:3a7713b1edbc 1242 * new setup data, and then optionally powerup the USB PLL, wait for USB PLL lock,
AnnaBridge 171:3a7713b1edbc 1243 * and adjust system voltages to the new USB PLL rate. The function will not
AnnaBridge 171:3a7713b1edbc 1244 * alter any source clocks (ie, usb pll clock) that may use the USB PLL,
AnnaBridge 171:3a7713b1edbc 1245 * so these should be setup prior to and after exiting the function.
AnnaBridge 171:3a7713b1edbc 1246 */
AnnaBridge 171:3a7713b1edbc 1247 pll_error_t CLOCK_SetUsbPLLFreq(const usb_pll_setup_t *pSetup);
AnnaBridge 171:3a7713b1edbc 1248
AnnaBridge 171:3a7713b1edbc 1249 /*! @brief Set PLL output based on the multiplier and input frequency
AnnaBridge 171:3a7713b1edbc 1250 * @param multiply_by : multiplier
AnnaBridge 171:3a7713b1edbc 1251 * @param input_freq : Clock input frequency of the PLL
AnnaBridge 171:3a7713b1edbc 1252 * @return Nothing
AnnaBridge 171:3a7713b1edbc 1253 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
AnnaBridge 171:3a7713b1edbc 1254 * function does not disable or enable PLL power, wait for PLL lock,
AnnaBridge 171:3a7713b1edbc 1255 * or adjust system voltages. These must be done in the application.
AnnaBridge 171:3a7713b1edbc 1256 * The function will not alter any source clocks (ie, main systen clock)
AnnaBridge 171:3a7713b1edbc 1257 * that may use the PLL, so these should be setup prior to and after
AnnaBridge 171:3a7713b1edbc 1258 * exiting the function.
AnnaBridge 171:3a7713b1edbc 1259 */
AnnaBridge 171:3a7713b1edbc 1260 void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
AnnaBridge 171:3a7713b1edbc 1261
AnnaBridge 171:3a7713b1edbc 1262 /*! @brief Disable USB clock.
AnnaBridge 171:3a7713b1edbc 1263 *
AnnaBridge 171:3a7713b1edbc 1264 * Disable USB clock.
AnnaBridge 171:3a7713b1edbc 1265 */
AnnaBridge 171:3a7713b1edbc 1266 static inline void CLOCK_DisableUsbDevicefs0Clock(clock_ip_name_t clk)
AnnaBridge 171:3a7713b1edbc 1267 {
AnnaBridge 171:3a7713b1edbc 1268 CLOCK_DisableClock(clk);
AnnaBridge 171:3a7713b1edbc 1269 }
AnnaBridge 171:3a7713b1edbc 1270
AnnaBridge 171:3a7713b1edbc 1271 /*! @brief Enable USB Device FS clock.
AnnaBridge 171:3a7713b1edbc 1272 * @param src : clock source
AnnaBridge 171:3a7713b1edbc 1273 * @param freq: clock frequency
AnnaBridge 171:3a7713b1edbc 1274 * Enable USB Device Full Speed clock.
AnnaBridge 171:3a7713b1edbc 1275 */
AnnaBridge 171:3a7713b1edbc 1276 bool CLOCK_EnableUsbfs0DeviceClock(clock_usb_src_t src, uint32_t freq);
AnnaBridge 171:3a7713b1edbc 1277
AnnaBridge 171:3a7713b1edbc 1278 /*! @brief Enable USB HOST FS clock.
AnnaBridge 171:3a7713b1edbc 1279 * @param src : clock source
AnnaBridge 171:3a7713b1edbc 1280 * @param freq: clock frequency
AnnaBridge 171:3a7713b1edbc 1281 * Enable USB HOST Full Speed clock.
AnnaBridge 171:3a7713b1edbc 1282 */
AnnaBridge 171:3a7713b1edbc 1283 bool CLOCK_EnableUsbfs0HostClock(clock_usb_src_t src, uint32_t freq);
AnnaBridge 171:3a7713b1edbc 1284
AnnaBridge 171:3a7713b1edbc 1285 /*! @brief Enable USB Device HS clock.
AnnaBridge 171:3a7713b1edbc 1286 * @param src : clock source
AnnaBridge 171:3a7713b1edbc 1287 * @param freq: clock frequency
AnnaBridge 171:3a7713b1edbc 1288 * Enable USB Device High Speed clock.
AnnaBridge 171:3a7713b1edbc 1289 */
AnnaBridge 171:3a7713b1edbc 1290 bool CLOCK_EnableUsbhs0DeviceClock(clock_usb_src_t src, uint32_t freq);
AnnaBridge 171:3a7713b1edbc 1291
AnnaBridge 171:3a7713b1edbc 1292 /*! @brief Enable USB HOST HS clock.
AnnaBridge 171:3a7713b1edbc 1293 * @param src : clock source
AnnaBridge 171:3a7713b1edbc 1294 * @param freq: clock frequency
AnnaBridge 171:3a7713b1edbc 1295 * Enable USB HOST High Speed clock.
AnnaBridge 171:3a7713b1edbc 1296 */
AnnaBridge 171:3a7713b1edbc 1297 bool CLOCK_EnableUsbhs0HostClock(clock_usb_src_t src, uint32_t freq);
AnnaBridge 171:3a7713b1edbc 1298
AnnaBridge 171:3a7713b1edbc 1299 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 1300 }
AnnaBridge 171:3a7713b1edbc 1301 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 1302
AnnaBridge 171:3a7713b1edbc 1303 /*! @} */
AnnaBridge 171:3a7713b1edbc 1304
AnnaBridge 171:3a7713b1edbc 1305 #endif /* _FSL_CLOCK_H_ */