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TARGET_ELMO_F411RE/TOOLCHAIN_GCC_ARM/stm32f4xx_ll_spi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/**
AnnaBridge	145:64910690c574	2	******************************************************************************
AnnaBridge	145:64910690c574	3	* @file stm32f4xx_ll_spi.h
AnnaBridge	145:64910690c574	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @brief Header file of SPI LL module.
AnnaBridge	145:64910690c574	6	******************************************************************************
AnnaBridge	145:64910690c574	7	* @attention
AnnaBridge	145:64910690c574	8	*
AnnaBridge	145:64910690c574	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	145:64910690c574	10	*
AnnaBridge	145:64910690c574	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	145:64910690c574	12	* are permitted provided that the following conditions are met:
AnnaBridge	145:64910690c574	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	145:64910690c574	14	* this list of conditions and the following disclaimer.
AnnaBridge	145:64910690c574	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	145:64910690c574	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	145:64910690c574	17	* and/or other materials provided with the distribution.
AnnaBridge	145:64910690c574	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	145:64910690c574	19	* may be used to endorse or promote products derived from this software
AnnaBridge	145:64910690c574	20	* without specific prior written permission.
AnnaBridge	145:64910690c574	21	*
AnnaBridge	145:64910690c574	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	145:64910690c574	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	145:64910690c574	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	145:64910690c574	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	145:64910690c574	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	145:64910690c574	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	145:64910690c574	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	145:64910690c574	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	145:64910690c574	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	145:64910690c574	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	145:64910690c574	32	*
AnnaBridge	145:64910690c574	33	******************************************************************************
AnnaBridge	145:64910690c574	34	*/
AnnaBridge	145:64910690c574	35
AnnaBridge	145:64910690c574	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	145:64910690c574	37	#ifndef __STM32F4xx_LL_SPI_H
AnnaBridge	145:64910690c574	38	#define __STM32F4xx_LL_SPI_H
AnnaBridge	145:64910690c574	39
AnnaBridge	145:64910690c574	40	#ifdef __cplusplus
AnnaBridge	145:64910690c574	41	extern "C" {
AnnaBridge	145:64910690c574	42	#endif
AnnaBridge	145:64910690c574	43
AnnaBridge	145:64910690c574	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	145:64910690c574	45	#include "stm32f4xx.h"
AnnaBridge	145:64910690c574	46
AnnaBridge	145:64910690c574	47	/** @addtogroup STM32F4xx_LL_Driver
AnnaBridge	145:64910690c574	48	* @{
AnnaBridge	145:64910690c574	49	*/
AnnaBridge	145:64910690c574	50
AnnaBridge	145:64910690c574	51	#if defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) \|\| defined (SPI4) \|\| defined (SPI5) \|\| defined(SPI6)
AnnaBridge	145:64910690c574	52
AnnaBridge	145:64910690c574	53	/** @defgroup SPI_LL SPI
AnnaBridge	145:64910690c574	54	* @{
AnnaBridge	145:64910690c574	55	*/
AnnaBridge	145:64910690c574	56
AnnaBridge	145:64910690c574	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	145:64910690c574	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	59	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	60
AnnaBridge	145:64910690c574	61	/* Exported types ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	62	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	63	/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
AnnaBridge	145:64910690c574	64	* @{
AnnaBridge	145:64910690c574	65	*/
AnnaBridge	145:64910690c574	66
AnnaBridge	145:64910690c574	67	/**
AnnaBridge	145:64910690c574	68	* @brief SPI Init structures definition
AnnaBridge	145:64910690c574	69	*/
AnnaBridge	145:64910690c574	70	typedef struct
AnnaBridge	145:64910690c574	71	{
AnnaBridge	145:64910690c574	72	uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
AnnaBridge	145:64910690c574	73	This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
AnnaBridge	145:64910690c574	74
AnnaBridge	145:64910690c574	75	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
AnnaBridge	145:64910690c574	76
AnnaBridge	145:64910690c574	77	uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
AnnaBridge	145:64910690c574	78	This parameter can be a value of @ref SPI_LL_EC_MODE.
AnnaBridge	145:64910690c574	79
AnnaBridge	145:64910690c574	80	This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
AnnaBridge	145:64910690c574	81
AnnaBridge	145:64910690c574	82	uint32_t DataWidth; /*!< Specifies the SPI data width.
AnnaBridge	145:64910690c574	83	This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
AnnaBridge	145:64910690c574	84
AnnaBridge	145:64910690c574	85	This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
AnnaBridge	145:64910690c574	86
AnnaBridge	145:64910690c574	87	uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge	145:64910690c574	88	This parameter can be a value of @ref SPI_LL_EC_POLARITY.
AnnaBridge	145:64910690c574	89
AnnaBridge	145:64910690c574	90	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
AnnaBridge	145:64910690c574	91
AnnaBridge	145:64910690c574	92	uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge	145:64910690c574	93	This parameter can be a value of @ref SPI_LL_EC_PHASE.
AnnaBridge	145:64910690c574	94
AnnaBridge	145:64910690c574	95	This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
AnnaBridge	145:64910690c574	96
AnnaBridge	145:64910690c574	97	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
AnnaBridge	145:64910690c574	98	This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
AnnaBridge	145:64910690c574	99
AnnaBridge	145:64910690c574	100	This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
AnnaBridge	145:64910690c574	101
AnnaBridge	145:64910690c574	102	uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
AnnaBridge	145:64910690c574	103	This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
AnnaBridge	145:64910690c574	104	@note The communication clock is derived from the master clock. The slave clock does not need to be set.
AnnaBridge	145:64910690c574	105
AnnaBridge	145:64910690c574	106	This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
AnnaBridge	145:64910690c574	107
AnnaBridge	145:64910690c574	108	uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge	145:64910690c574	109	This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
AnnaBridge	145:64910690c574	110
AnnaBridge	145:64910690c574	111	This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
AnnaBridge	145:64910690c574	112
AnnaBridge	145:64910690c574	113	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge	145:64910690c574	114	This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
AnnaBridge	145:64910690c574	115
AnnaBridge	145:64910690c574	116	This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
AnnaBridge	145:64910690c574	117
AnnaBridge	145:64910690c574	118	uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	145:64910690c574	119	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
AnnaBridge	145:64910690c574	120
AnnaBridge	145:64910690c574	121	This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
AnnaBridge	145:64910690c574	122
AnnaBridge	145:64910690c574	123	} LL_SPI_InitTypeDef;
AnnaBridge	145:64910690c574	124
AnnaBridge	145:64910690c574	125	/**
AnnaBridge	145:64910690c574	126	* @}
AnnaBridge	145:64910690c574	127	*/
AnnaBridge	145:64910690c574	128	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	129
AnnaBridge	145:64910690c574	130	/* Exported constants --------------------------------------------------------*/
AnnaBridge	145:64910690c574	131	/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
AnnaBridge	145:64910690c574	132	* @{
AnnaBridge	145:64910690c574	133	*/
AnnaBridge	145:64910690c574	134
AnnaBridge	145:64910690c574	135	/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	145:64910690c574	136	* @brief Flags defines which can be used with LL_SPI_ReadReg function
AnnaBridge	145:64910690c574	137	* @{
AnnaBridge	145:64910690c574	138	*/
AnnaBridge	145:64910690c574	139	#define LL_SPI_SR_RXNE SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	145:64910690c574	140	#define LL_SPI_SR_TXE SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	145:64910690c574	141	#define LL_SPI_SR_BSY SPI_SR_BSY /!< Busy flag /
AnnaBridge	145:64910690c574	142	#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /!< CRC error flag /
AnnaBridge	145:64910690c574	143	#define LL_SPI_SR_MODF SPI_SR_MODF /!< Mode fault flag /
AnnaBridge	145:64910690c574	144	#define LL_SPI_SR_OVR SPI_SR_OVR /!< Overrun flag /
AnnaBridge	145:64910690c574	145	#define LL_SPI_SR_FRE SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	145:64910690c574	146	/**
AnnaBridge	145:64910690c574	147	* @}
AnnaBridge	145:64910690c574	148	*/
AnnaBridge	145:64910690c574	149
AnnaBridge	145:64910690c574	150	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	145:64910690c574	151	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	145:64910690c574	152	* @{
AnnaBridge	145:64910690c574	153	*/
AnnaBridge	145:64910690c574	154	#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	145:64910690c574	155	#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	145:64910690c574	156	#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	145:64910690c574	157	/**
AnnaBridge	145:64910690c574	158	* @}
AnnaBridge	145:64910690c574	159	*/
AnnaBridge	145:64910690c574	160
AnnaBridge	145:64910690c574	161	/** @defgroup SPI_LL_EC_MODE Operation Mode
AnnaBridge	145:64910690c574	162	* @{
AnnaBridge	145:64910690c574	163	*/
AnnaBridge	145:64910690c574	164	#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR \| SPI_CR1_SSI) /!< Master configuration /
AnnaBridge	145:64910690c574	165	#define LL_SPI_MODE_SLAVE 0x00000000U /!< Slave configuration /
AnnaBridge	145:64910690c574	166	/**
AnnaBridge	145:64910690c574	167	* @}
AnnaBridge	145:64910690c574	168	*/
AnnaBridge	145:64910690c574	169
AnnaBridge	145:64910690c574	170	/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
AnnaBridge	145:64910690c574	171	* @{
AnnaBridge	145:64910690c574	172	*/
AnnaBridge	145:64910690c574	173	#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /!< Motorola mode. Used as default value /
AnnaBridge	145:64910690c574	174	#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /!< TI mode /
AnnaBridge	145:64910690c574	175	/**
AnnaBridge	145:64910690c574	176	* @}
AnnaBridge	145:64910690c574	177	*/
AnnaBridge	145:64910690c574	178
AnnaBridge	145:64910690c574	179	/** @defgroup SPI_LL_EC_PHASE Clock Phase
AnnaBridge	145:64910690c574	180	* @{
AnnaBridge	145:64910690c574	181	*/
AnnaBridge	145:64910690c574	182	#define LL_SPI_PHASE_1EDGE 0x00000000U /!< First clock transition is the first data capture edge /
AnnaBridge	145:64910690c574	183	#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /!< Second clock transition is the first data capture edge /
AnnaBridge	145:64910690c574	184	/**
AnnaBridge	145:64910690c574	185	* @}
AnnaBridge	145:64910690c574	186	*/
AnnaBridge	145:64910690c574	187
AnnaBridge	145:64910690c574	188	/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
AnnaBridge	145:64910690c574	189	* @{
AnnaBridge	145:64910690c574	190	*/
AnnaBridge	145:64910690c574	191	#define LL_SPI_POLARITY_LOW 0x00000000U /!< Clock to 0 when idle /
AnnaBridge	145:64910690c574	192	#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /!< Clock to 1 when idle /
AnnaBridge	145:64910690c574	193	/**
AnnaBridge	145:64910690c574	194	* @}
AnnaBridge	145:64910690c574	195	*/
AnnaBridge	145:64910690c574	196
AnnaBridge	145:64910690c574	197	/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
AnnaBridge	145:64910690c574	198	* @{
AnnaBridge	145:64910690c574	199	*/
AnnaBridge	145:64910690c574	200	#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /!< BaudRate control equal to fPCLK/2 /
AnnaBridge	145:64910690c574	201	#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/4 /
AnnaBridge	145:64910690c574	202	#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/8 /
AnnaBridge	145:64910690c574	203	#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/16 /
AnnaBridge	145:64910690c574	204	#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /!< BaudRate control equal to fPCLK/32 /
AnnaBridge	145:64910690c574	205	#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/64 /
AnnaBridge	145:64910690c574	206	#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 \| SPI_CR1_BR_1) /!< BaudRate control equal to fPCLK/128 /
AnnaBridge	145:64910690c574	207	#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 \| SPI_CR1_BR_1 \| SPI_CR1_BR_0) /!< BaudRate control equal to fPCLK/256 /
AnnaBridge	145:64910690c574	208	/**
AnnaBridge	145:64910690c574	209	* @}
AnnaBridge	145:64910690c574	210	*/
AnnaBridge	145:64910690c574	211
AnnaBridge	145:64910690c574	212	/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
AnnaBridge	145:64910690c574	213	* @{
AnnaBridge	145:64910690c574	214	*/
AnnaBridge	145:64910690c574	215	#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /!< Data is transmitted/received with the LSB first /
AnnaBridge	145:64910690c574	216	#define LL_SPI_MSB_FIRST 0x00000000U /!< Data is transmitted/received with the MSB first /
AnnaBridge	145:64910690c574	217	/**
AnnaBridge	145:64910690c574	218	* @}
AnnaBridge	145:64910690c574	219	*/
AnnaBridge	145:64910690c574	220
AnnaBridge	145:64910690c574	221	/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
AnnaBridge	145:64910690c574	222	* @{
AnnaBridge	145:64910690c574	223	*/
AnnaBridge	145:64910690c574	224	#define LL_SPI_FULL_DUPLEX 0x00000000U /!< Full-Duplex mode. Rx and Tx transfer on 2 lines /
AnnaBridge	145:64910690c574	225	#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /!< Simplex Rx mode. Rx transfer only on 1 line /
AnnaBridge	145:64910690c574	226	#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /!< Half-Duplex Rx mode. Rx transfer on 1 line /
AnnaBridge	145:64910690c574	227	#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE) /!< Half-Duplex Tx mode. Tx transfer on 1 line /
AnnaBridge	145:64910690c574	228	/**
AnnaBridge	145:64910690c574	229	* @}
AnnaBridge	145:64910690c574	230	*/
AnnaBridge	145:64910690c574	231
AnnaBridge	145:64910690c574	232	/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
AnnaBridge	145:64910690c574	233	* @{
AnnaBridge	145:64910690c574	234	*/
AnnaBridge	145:64910690c574	235	#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /!< NSS managed internally. NSS pin not used and free /
AnnaBridge	145:64910690c574	236	#define LL_SPI_NSS_HARD_INPUT 0x00000000U /!< NSS pin used in Input. Only used in Master mode /
AnnaBridge	145:64910690c574	237	#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /!< NSS pin used in Output. Only used in Slave mode as chip select /
AnnaBridge	145:64910690c574	238	/**
AnnaBridge	145:64910690c574	239	* @}
AnnaBridge	145:64910690c574	240	*/
AnnaBridge	145:64910690c574	241
AnnaBridge	145:64910690c574	242	/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
AnnaBridge	145:64910690c574	243	* @{
AnnaBridge	145:64910690c574	244	*/
AnnaBridge	145:64910690c574	245	#define LL_SPI_DATAWIDTH_8BIT 0x00000000U /!< Data length for SPI transfer: 8 bits /
AnnaBridge	145:64910690c574	246	#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /!< Data length for SPI transfer: 16 bits /
AnnaBridge	145:64910690c574	247	/**
AnnaBridge	145:64910690c574	248	* @}
AnnaBridge	145:64910690c574	249	*/
AnnaBridge	145:64910690c574	250	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	251
AnnaBridge	145:64910690c574	252	/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
AnnaBridge	145:64910690c574	253	* @{
AnnaBridge	145:64910690c574	254	*/
AnnaBridge	145:64910690c574	255	#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /!< CRC calculation disabled /
AnnaBridge	145:64910690c574	256	#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /!< CRC calculation enabled /
AnnaBridge	145:64910690c574	257	/**
AnnaBridge	145:64910690c574	258	* @}
AnnaBridge	145:64910690c574	259	*/
AnnaBridge	145:64910690c574	260	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	261
AnnaBridge	145:64910690c574	262	/**
AnnaBridge	145:64910690c574	263	* @}
AnnaBridge	145:64910690c574	264	*/
AnnaBridge	145:64910690c574	265
AnnaBridge	145:64910690c574	266	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	267	/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
AnnaBridge	145:64910690c574	268	* @{
AnnaBridge	145:64910690c574	269	*/
AnnaBridge	145:64910690c574	270
AnnaBridge	145:64910690c574	271	/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	145:64910690c574	272	* @{
AnnaBridge	145:64910690c574	273	*/
AnnaBridge	145:64910690c574	274
AnnaBridge	145:64910690c574	275	/**
AnnaBridge	145:64910690c574	276	* @brief Write a value in SPI register
AnnaBridge	145:64910690c574	277	* @param __INSTANCE__ SPI Instance
AnnaBridge	145:64910690c574	278	* @param __REG__ Register to be written
AnnaBridge	145:64910690c574	279	* @param __VALUE__ Value to be written in the register
AnnaBridge	145:64910690c574	280	* @retval None
AnnaBridge	145:64910690c574	281	*/
AnnaBridge	145:64910690c574	282	#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	145:64910690c574	283
AnnaBridge	145:64910690c574	284	/**
AnnaBridge	145:64910690c574	285	* @brief Read a value in SPI register
AnnaBridge	145:64910690c574	286	* @param __INSTANCE__ SPI Instance
AnnaBridge	145:64910690c574	287	* @param __REG__ Register to be read
AnnaBridge	145:64910690c574	288	* @retval Register value
AnnaBridge	145:64910690c574	289	*/
AnnaBridge	145:64910690c574	290	#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	145:64910690c574	291	/**
AnnaBridge	145:64910690c574	292	* @}
AnnaBridge	145:64910690c574	293	*/
AnnaBridge	145:64910690c574	294
AnnaBridge	145:64910690c574	295	/**
AnnaBridge	145:64910690c574	296	* @}
AnnaBridge	145:64910690c574	297	*/
AnnaBridge	145:64910690c574	298
AnnaBridge	145:64910690c574	299	/* Exported functions --------------------------------------------------------*/
AnnaBridge	145:64910690c574	300	/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
AnnaBridge	145:64910690c574	301	* @{
AnnaBridge	145:64910690c574	302	*/
AnnaBridge	145:64910690c574	303
AnnaBridge	145:64910690c574	304	/** @defgroup SPI_LL_EF_Configuration Configuration
AnnaBridge	145:64910690c574	305	* @{
AnnaBridge	145:64910690c574	306	*/
AnnaBridge	145:64910690c574	307
AnnaBridge	145:64910690c574	308	/**
AnnaBridge	145:64910690c574	309	* @brief Enable SPI peripheral
AnnaBridge	145:64910690c574	310	* @rmtoll CR1 SPE LL_SPI_Enable
AnnaBridge	145:64910690c574	311	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	312	* @retval None
AnnaBridge	145:64910690c574	313	*/
AnnaBridge	145:64910690c574	314	__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	315	{
AnnaBridge	145:64910690c574	316	SET_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	145:64910690c574	317	}
AnnaBridge	145:64910690c574	318
AnnaBridge	145:64910690c574	319	/**
AnnaBridge	145:64910690c574	320	* @brief Disable SPI peripheral
AnnaBridge	145:64910690c574	321	* @note When disabling the SPI, follow the procedure described in the Reference Manual.
AnnaBridge	145:64910690c574	322	* @rmtoll CR1 SPE LL_SPI_Disable
AnnaBridge	145:64910690c574	323	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	324	* @retval None
AnnaBridge	145:64910690c574	325	*/
AnnaBridge	145:64910690c574	326	__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	327	{
AnnaBridge	145:64910690c574	328	CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	145:64910690c574	329	}
AnnaBridge	145:64910690c574	330
AnnaBridge	145:64910690c574	331	/**
AnnaBridge	145:64910690c574	332	* @brief Check if SPI peripheral is enabled
AnnaBridge	145:64910690c574	333	* @rmtoll CR1 SPE LL_SPI_IsEnabled
AnnaBridge	145:64910690c574	334	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	335	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	336	*/
AnnaBridge	145:64910690c574	337	__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	338	{
AnnaBridge	145:64910690c574	339	return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE));
AnnaBridge	145:64910690c574	340	}
AnnaBridge	145:64910690c574	341
AnnaBridge	145:64910690c574	342	/**
AnnaBridge	145:64910690c574	343	* @brief Set SPI operation mode to Master or Slave
AnnaBridge	145:64910690c574	344	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	145:64910690c574	345	* @rmtoll CR1 MSTR LL_SPI_SetMode\n
AnnaBridge	145:64910690c574	346	* CR1 SSI LL_SPI_SetMode
AnnaBridge	145:64910690c574	347	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	348	* @param Mode This parameter can be one of the following values:
AnnaBridge	145:64910690c574	349	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	145:64910690c574	350	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	145:64910690c574	351	* @retval None
AnnaBridge	145:64910690c574	352	*/
AnnaBridge	145:64910690c574	353	__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	145:64910690c574	354	{
AnnaBridge	145:64910690c574	355	MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI, Mode);
AnnaBridge	145:64910690c574	356	}
AnnaBridge	145:64910690c574	357
AnnaBridge	145:64910690c574	358	/**
AnnaBridge	145:64910690c574	359	* @brief Get SPI operation mode (Master or Slave)
AnnaBridge	145:64910690c574	360	* @rmtoll CR1 MSTR LL_SPI_GetMode\n
AnnaBridge	145:64910690c574	361	* CR1 SSI LL_SPI_GetMode
AnnaBridge	145:64910690c574	362	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	363	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	364	* @arg @ref LL_SPI_MODE_MASTER
AnnaBridge	145:64910690c574	365	* @arg @ref LL_SPI_MODE_SLAVE
AnnaBridge	145:64910690c574	366	*/
AnnaBridge	145:64910690c574	367	__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	368	{
AnnaBridge	145:64910690c574	369	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR \| SPI_CR1_SSI));
AnnaBridge	145:64910690c574	370	}
AnnaBridge	145:64910690c574	371
AnnaBridge	145:64910690c574	372	/**
AnnaBridge	145:64910690c574	373	* @brief Set serial protocol used
AnnaBridge	145:64910690c574	374	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	375	* @rmtoll CR2 FRF LL_SPI_SetStandard
AnnaBridge	145:64910690c574	376	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	377	* @param Standard This parameter can be one of the following values:
AnnaBridge	145:64910690c574	378	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	145:64910690c574	379	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	145:64910690c574	380	* @retval None
AnnaBridge	145:64910690c574	381	*/
AnnaBridge	145:64910690c574	382	__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	145:64910690c574	383	{
AnnaBridge	145:64910690c574	384	MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
AnnaBridge	145:64910690c574	385	}
AnnaBridge	145:64910690c574	386
AnnaBridge	145:64910690c574	387	/**
AnnaBridge	145:64910690c574	388	* @brief Get serial protocol used
AnnaBridge	145:64910690c574	389	* @rmtoll CR2 FRF LL_SPI_GetStandard
AnnaBridge	145:64910690c574	390	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	391	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	392	* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
AnnaBridge	145:64910690c574	393	* @arg @ref LL_SPI_PROTOCOL_TI
AnnaBridge	145:64910690c574	394	*/
AnnaBridge	145:64910690c574	395	__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	396	{
AnnaBridge	145:64910690c574	397	return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
AnnaBridge	145:64910690c574	398	}
AnnaBridge	145:64910690c574	399
AnnaBridge	145:64910690c574	400	/**
AnnaBridge	145:64910690c574	401	* @brief Set clock phase
AnnaBridge	145:64910690c574	402	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	145:64910690c574	403	* This bit is not used in SPI TI mode.
AnnaBridge	145:64910690c574	404	* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
AnnaBridge	145:64910690c574	405	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	406	* @param ClockPhase This parameter can be one of the following values:
AnnaBridge	145:64910690c574	407	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	145:64910690c574	408	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	145:64910690c574	409	* @retval None
AnnaBridge	145:64910690c574	410	*/
AnnaBridge	145:64910690c574	411	__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
AnnaBridge	145:64910690c574	412	{
AnnaBridge	145:64910690c574	413	MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
AnnaBridge	145:64910690c574	414	}
AnnaBridge	145:64910690c574	415
AnnaBridge	145:64910690c574	416	/**
AnnaBridge	145:64910690c574	417	* @brief Get clock phase
AnnaBridge	145:64910690c574	418	* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
AnnaBridge	145:64910690c574	419	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	420	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	421	* @arg @ref LL_SPI_PHASE_1EDGE
AnnaBridge	145:64910690c574	422	* @arg @ref LL_SPI_PHASE_2EDGE
AnnaBridge	145:64910690c574	423	*/
AnnaBridge	145:64910690c574	424	__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	425	{
AnnaBridge	145:64910690c574	426	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
AnnaBridge	145:64910690c574	427	}
AnnaBridge	145:64910690c574	428
AnnaBridge	145:64910690c574	429	/**
AnnaBridge	145:64910690c574	430	* @brief Set clock polarity
AnnaBridge	145:64910690c574	431	* @note This bit should not be changed when communication is ongoing.
AnnaBridge	145:64910690c574	432	* This bit is not used in SPI TI mode.
AnnaBridge	145:64910690c574	433	* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
AnnaBridge	145:64910690c574	434	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	435	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	145:64910690c574	436	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	145:64910690c574	437	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	145:64910690c574	438	* @retval None
AnnaBridge	145:64910690c574	439	*/
AnnaBridge	145:64910690c574	440	__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	145:64910690c574	441	{
AnnaBridge	145:64910690c574	442	MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
AnnaBridge	145:64910690c574	443	}
AnnaBridge	145:64910690c574	444
AnnaBridge	145:64910690c574	445	/**
AnnaBridge	145:64910690c574	446	* @brief Get clock polarity
AnnaBridge	145:64910690c574	447	* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
AnnaBridge	145:64910690c574	448	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	449	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	450	* @arg @ref LL_SPI_POLARITY_LOW
AnnaBridge	145:64910690c574	451	* @arg @ref LL_SPI_POLARITY_HIGH
AnnaBridge	145:64910690c574	452	*/
AnnaBridge	145:64910690c574	453	__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	454	{
AnnaBridge	145:64910690c574	455	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
AnnaBridge	145:64910690c574	456	}
AnnaBridge	145:64910690c574	457
AnnaBridge	145:64910690c574	458	/**
AnnaBridge	145:64910690c574	459	* @brief Set baud rate prescaler
AnnaBridge	145:64910690c574	460	* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
AnnaBridge	145:64910690c574	461	* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
AnnaBridge	145:64910690c574	462	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	463	* @param BaudRate This parameter can be one of the following values:
AnnaBridge	145:64910690c574	464	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	145:64910690c574	465	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	145:64910690c574	466	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	145:64910690c574	467	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	145:64910690c574	468	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	145:64910690c574	469	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	145:64910690c574	470	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	145:64910690c574	471	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	145:64910690c574	472	* @retval None
AnnaBridge	145:64910690c574	473	*/
AnnaBridge	145:64910690c574	474	__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
AnnaBridge	145:64910690c574	475	{
AnnaBridge	145:64910690c574	476	MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
AnnaBridge	145:64910690c574	477	}
AnnaBridge	145:64910690c574	478
AnnaBridge	145:64910690c574	479	/**
AnnaBridge	145:64910690c574	480	* @brief Get baud rate prescaler
AnnaBridge	145:64910690c574	481	* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
AnnaBridge	145:64910690c574	482	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	483	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	484	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
AnnaBridge	145:64910690c574	485	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
AnnaBridge	145:64910690c574	486	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
AnnaBridge	145:64910690c574	487	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
AnnaBridge	145:64910690c574	488	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
AnnaBridge	145:64910690c574	489	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
AnnaBridge	145:64910690c574	490	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
AnnaBridge	145:64910690c574	491	* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
AnnaBridge	145:64910690c574	492	*/
AnnaBridge	145:64910690c574	493	__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	494	{
AnnaBridge	145:64910690c574	495	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
AnnaBridge	145:64910690c574	496	}
AnnaBridge	145:64910690c574	497
AnnaBridge	145:64910690c574	498	/**
AnnaBridge	145:64910690c574	499	* @brief Set transfer bit order
AnnaBridge	145:64910690c574	500	* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
AnnaBridge	145:64910690c574	501	* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
AnnaBridge	145:64910690c574	502	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	503	* @param BitOrder This parameter can be one of the following values:
AnnaBridge	145:64910690c574	504	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	145:64910690c574	505	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	145:64910690c574	506	* @retval None
AnnaBridge	145:64910690c574	507	*/
AnnaBridge	145:64910690c574	508	__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
AnnaBridge	145:64910690c574	509	{
AnnaBridge	145:64910690c574	510	MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
AnnaBridge	145:64910690c574	511	}
AnnaBridge	145:64910690c574	512
AnnaBridge	145:64910690c574	513	/**
AnnaBridge	145:64910690c574	514	* @brief Get transfer bit order
AnnaBridge	145:64910690c574	515	* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
AnnaBridge	145:64910690c574	516	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	517	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	518	* @arg @ref LL_SPI_LSB_FIRST
AnnaBridge	145:64910690c574	519	* @arg @ref LL_SPI_MSB_FIRST
AnnaBridge	145:64910690c574	520	*/
AnnaBridge	145:64910690c574	521	__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	522	{
AnnaBridge	145:64910690c574	523	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
AnnaBridge	145:64910690c574	524	}
AnnaBridge	145:64910690c574	525
AnnaBridge	145:64910690c574	526	/**
AnnaBridge	145:64910690c574	527	* @brief Set transfer direction mode
AnnaBridge	145:64910690c574	528	* @note For Half-Duplex mode, Rx Direction is set by default.
AnnaBridge	145:64910690c574	529	* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
AnnaBridge	145:64910690c574	530	* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
AnnaBridge	145:64910690c574	531	* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
AnnaBridge	145:64910690c574	532	* CR1 BIDIOE LL_SPI_SetTransferDirection
AnnaBridge	145:64910690c574	533	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	534	* @param TransferDirection This parameter can be one of the following values:
AnnaBridge	145:64910690c574	535	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	145:64910690c574	536	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	145:64910690c574	537	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	145:64910690c574	538	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	145:64910690c574	539	* @retval None
AnnaBridge	145:64910690c574	540	*/
AnnaBridge	145:64910690c574	541	__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
AnnaBridge	145:64910690c574	542	{
AnnaBridge	145:64910690c574	543	MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE, TransferDirection);
AnnaBridge	145:64910690c574	544	}
AnnaBridge	145:64910690c574	545
AnnaBridge	145:64910690c574	546	/**
AnnaBridge	145:64910690c574	547	* @brief Get transfer direction mode
AnnaBridge	145:64910690c574	548	* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
AnnaBridge	145:64910690c574	549	* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
AnnaBridge	145:64910690c574	550	* CR1 BIDIOE LL_SPI_GetTransferDirection
AnnaBridge	145:64910690c574	551	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	552	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	553	* @arg @ref LL_SPI_FULL_DUPLEX
AnnaBridge	145:64910690c574	554	* @arg @ref LL_SPI_SIMPLEX_RX
AnnaBridge	145:64910690c574	555	* @arg @ref LL_SPI_HALF_DUPLEX_RX
AnnaBridge	145:64910690c574	556	* @arg @ref LL_SPI_HALF_DUPLEX_TX
AnnaBridge	145:64910690c574	557	*/
AnnaBridge	145:64910690c574	558	__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	559	{
AnnaBridge	145:64910690c574	560	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY \| SPI_CR1_BIDIMODE \| SPI_CR1_BIDIOE));
AnnaBridge	145:64910690c574	561	}
AnnaBridge	145:64910690c574	562
AnnaBridge	145:64910690c574	563	/**
AnnaBridge	145:64910690c574	564	* @brief Set frame data width
AnnaBridge	145:64910690c574	565	* @rmtoll CR1 DFF LL_SPI_SetDataWidth
AnnaBridge	145:64910690c574	566	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	567	* @param DataWidth This parameter can be one of the following values:
AnnaBridge	145:64910690c574	568	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	145:64910690c574	569	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	145:64910690c574	570	* @retval None
AnnaBridge	145:64910690c574	571	*/
AnnaBridge	145:64910690c574	572	__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
AnnaBridge	145:64910690c574	573	{
AnnaBridge	145:64910690c574	574	MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
AnnaBridge	145:64910690c574	575	}
AnnaBridge	145:64910690c574	576
AnnaBridge	145:64910690c574	577	/**
AnnaBridge	145:64910690c574	578	* @brief Get frame data width
AnnaBridge	145:64910690c574	579	* @rmtoll CR1 DFF LL_SPI_GetDataWidth
AnnaBridge	145:64910690c574	580	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	581	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	582	* @arg @ref LL_SPI_DATAWIDTH_8BIT
AnnaBridge	145:64910690c574	583	* @arg @ref LL_SPI_DATAWIDTH_16BIT
AnnaBridge	145:64910690c574	584	*/
AnnaBridge	145:64910690c574	585	__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	586	{
AnnaBridge	145:64910690c574	587	return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
AnnaBridge	145:64910690c574	588	}
AnnaBridge	145:64910690c574	589
AnnaBridge	145:64910690c574	590	/**
AnnaBridge	145:64910690c574	591	* @}
AnnaBridge	145:64910690c574	592	*/
AnnaBridge	145:64910690c574	593
AnnaBridge	145:64910690c574	594	/** @defgroup SPI_LL_EF_CRC_Management CRC Management
AnnaBridge	145:64910690c574	595	* @{
AnnaBridge	145:64910690c574	596	*/
AnnaBridge	145:64910690c574	597
AnnaBridge	145:64910690c574	598	/**
AnnaBridge	145:64910690c574	599	* @brief Enable CRC
AnnaBridge	145:64910690c574	600	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	601	* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
AnnaBridge	145:64910690c574	602	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	603	* @retval None
AnnaBridge	145:64910690c574	604	*/
AnnaBridge	145:64910690c574	605	__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	606	{
AnnaBridge	145:64910690c574	607	SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	145:64910690c574	608	}
AnnaBridge	145:64910690c574	609
AnnaBridge	145:64910690c574	610	/**
AnnaBridge	145:64910690c574	611	* @brief Disable CRC
AnnaBridge	145:64910690c574	612	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	613	* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
AnnaBridge	145:64910690c574	614	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	615	* @retval None
AnnaBridge	145:64910690c574	616	*/
AnnaBridge	145:64910690c574	617	__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	618	{
AnnaBridge	145:64910690c574	619	CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
AnnaBridge	145:64910690c574	620	}
AnnaBridge	145:64910690c574	621
AnnaBridge	145:64910690c574	622	/**
AnnaBridge	145:64910690c574	623	* @brief Check if CRC is enabled
AnnaBridge	145:64910690c574	624	* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
AnnaBridge	145:64910690c574	625	* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
AnnaBridge	145:64910690c574	626	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	627	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	628	*/
AnnaBridge	145:64910690c574	629	__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	630	{
AnnaBridge	145:64910690c574	631	return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN));
AnnaBridge	145:64910690c574	632	}
AnnaBridge	145:64910690c574	633
AnnaBridge	145:64910690c574	634	/**
AnnaBridge	145:64910690c574	635	* @brief Set CRCNext to transfer CRC on the line
AnnaBridge	145:64910690c574	636	* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
AnnaBridge	145:64910690c574	637	* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
AnnaBridge	145:64910690c574	638	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	639	* @retval None
AnnaBridge	145:64910690c574	640	*/
AnnaBridge	145:64910690c574	641	__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	642	{
AnnaBridge	145:64910690c574	643	SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
AnnaBridge	145:64910690c574	644	}
AnnaBridge	145:64910690c574	645
AnnaBridge	145:64910690c574	646	/**
AnnaBridge	145:64910690c574	647	* @brief Set polynomial for CRC calculation
AnnaBridge	145:64910690c574	648	* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
AnnaBridge	145:64910690c574	649	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	650	* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	145:64910690c574	651	* @retval None
AnnaBridge	145:64910690c574	652	*/
AnnaBridge	145:64910690c574	653	__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
AnnaBridge	145:64910690c574	654	{
AnnaBridge	145:64910690c574	655	WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
AnnaBridge	145:64910690c574	656	}
AnnaBridge	145:64910690c574	657
AnnaBridge	145:64910690c574	658	/**
AnnaBridge	145:64910690c574	659	* @brief Get polynomial for CRC calculation
AnnaBridge	145:64910690c574	660	* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
AnnaBridge	145:64910690c574	661	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	662	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	145:64910690c574	663	*/
AnnaBridge	145:64910690c574	664	__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	665	{
AnnaBridge	145:64910690c574	666	return (uint32_t)(READ_REG(SPIx->CRCPR));
AnnaBridge	145:64910690c574	667	}
AnnaBridge	145:64910690c574	668
AnnaBridge	145:64910690c574	669	/**
AnnaBridge	145:64910690c574	670	* @brief Get Rx CRC
AnnaBridge	145:64910690c574	671	* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
AnnaBridge	145:64910690c574	672	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	673	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	145:64910690c574	674	*/
AnnaBridge	145:64910690c574	675	__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	676	{
AnnaBridge	145:64910690c574	677	return (uint32_t)(READ_REG(SPIx->RXCRCR));
AnnaBridge	145:64910690c574	678	}
AnnaBridge	145:64910690c574	679
AnnaBridge	145:64910690c574	680	/**
AnnaBridge	145:64910690c574	681	* @brief Get Tx CRC
AnnaBridge	145:64910690c574	682	* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
AnnaBridge	145:64910690c574	683	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	684	* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
AnnaBridge	145:64910690c574	685	*/
AnnaBridge	145:64910690c574	686	__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	687	{
AnnaBridge	145:64910690c574	688	return (uint32_t)(READ_REG(SPIx->TXCRCR));
AnnaBridge	145:64910690c574	689	}
AnnaBridge	145:64910690c574	690
AnnaBridge	145:64910690c574	691	/**
AnnaBridge	145:64910690c574	692	* @}
AnnaBridge	145:64910690c574	693	*/
AnnaBridge	145:64910690c574	694
AnnaBridge	145:64910690c574	695	/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
AnnaBridge	145:64910690c574	696	* @{
AnnaBridge	145:64910690c574	697	*/
AnnaBridge	145:64910690c574	698
AnnaBridge	145:64910690c574	699	/**
AnnaBridge	145:64910690c574	700	* @brief Set NSS mode
AnnaBridge	145:64910690c574	701	* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
AnnaBridge	145:64910690c574	702	* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
AnnaBridge	145:64910690c574	703	* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
AnnaBridge	145:64910690c574	704	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	705	* @param NSS This parameter can be one of the following values:
AnnaBridge	145:64910690c574	706	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	145:64910690c574	707	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	145:64910690c574	708	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	145:64910690c574	709	* @retval None
AnnaBridge	145:64910690c574	710	*/
AnnaBridge	145:64910690c574	711	__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
AnnaBridge	145:64910690c574	712	{
AnnaBridge	145:64910690c574	713	MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
AnnaBridge	145:64910690c574	714	MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
AnnaBridge	145:64910690c574	715	}
AnnaBridge	145:64910690c574	716
AnnaBridge	145:64910690c574	717	/**
AnnaBridge	145:64910690c574	718	* @brief Get NSS mode
AnnaBridge	145:64910690c574	719	* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
AnnaBridge	145:64910690c574	720	* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
AnnaBridge	145:64910690c574	721	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	722	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	723	* @arg @ref LL_SPI_NSS_SOFT
AnnaBridge	145:64910690c574	724	* @arg @ref LL_SPI_NSS_HARD_INPUT
AnnaBridge	145:64910690c574	725	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
AnnaBridge	145:64910690c574	726	*/
AnnaBridge	145:64910690c574	727	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	728	{
AnnaBridge	145:64910690c574	729	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
AnnaBridge	145:64910690c574	730	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
AnnaBridge	145:64910690c574	731	return (Ssm \| Ssoe);
AnnaBridge	145:64910690c574	732	}
AnnaBridge	145:64910690c574	733
AnnaBridge	145:64910690c574	734	/**
AnnaBridge	145:64910690c574	735	* @}
AnnaBridge	145:64910690c574	736	*/
AnnaBridge	145:64910690c574	737
AnnaBridge	145:64910690c574	738	/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
AnnaBridge	145:64910690c574	739	* @{
AnnaBridge	145:64910690c574	740	*/
AnnaBridge	145:64910690c574	741
AnnaBridge	145:64910690c574	742	/**
AnnaBridge	145:64910690c574	743	* @brief Check if Rx buffer is not empty
AnnaBridge	145:64910690c574	744	* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
AnnaBridge	145:64910690c574	745	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	746	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	747	*/
AnnaBridge	145:64910690c574	748	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	749	{
AnnaBridge	145:64910690c574	750	return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE));
AnnaBridge	145:64910690c574	751	}
AnnaBridge	145:64910690c574	752
AnnaBridge	145:64910690c574	753	/**
AnnaBridge	145:64910690c574	754	* @brief Check if Tx buffer is empty
AnnaBridge	145:64910690c574	755	* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
AnnaBridge	145:64910690c574	756	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	757	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	758	*/
AnnaBridge	145:64910690c574	759	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	760	{
AnnaBridge	145:64910690c574	761	return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE));
AnnaBridge	145:64910690c574	762	}
AnnaBridge	145:64910690c574	763
AnnaBridge	145:64910690c574	764	/**
AnnaBridge	145:64910690c574	765	* @brief Get CRC error flag
AnnaBridge	145:64910690c574	766	* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
AnnaBridge	145:64910690c574	767	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	768	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	769	*/
AnnaBridge	145:64910690c574	770	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	771	{
AnnaBridge	145:64910690c574	772	return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR));
AnnaBridge	145:64910690c574	773	}
AnnaBridge	145:64910690c574	774
AnnaBridge	145:64910690c574	775	/**
AnnaBridge	145:64910690c574	776	* @brief Get mode fault error flag
AnnaBridge	145:64910690c574	777	* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
AnnaBridge	145:64910690c574	778	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	779	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	780	*/
AnnaBridge	145:64910690c574	781	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	782	{
AnnaBridge	145:64910690c574	783	return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF));
AnnaBridge	145:64910690c574	784	}
AnnaBridge	145:64910690c574	785
AnnaBridge	145:64910690c574	786	/**
AnnaBridge	145:64910690c574	787	* @brief Get overrun error flag
AnnaBridge	145:64910690c574	788	* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
AnnaBridge	145:64910690c574	789	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	790	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	791	*/
AnnaBridge	145:64910690c574	792	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	793	{
AnnaBridge	145:64910690c574	794	return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR));
AnnaBridge	145:64910690c574	795	}
AnnaBridge	145:64910690c574	796
AnnaBridge	145:64910690c574	797	/**
AnnaBridge	145:64910690c574	798	* @brief Get busy flag
AnnaBridge	145:64910690c574	799	* @note The BSY flag is cleared under any one of the following conditions:
AnnaBridge	145:64910690c574	800	* -When the SPI is correctly disabled
AnnaBridge	145:64910690c574	801	* -When a fault is detected in Master mode (MODF bit set to 1)
AnnaBridge	145:64910690c574	802	* -In Master mode, when it finishes a data transmission and no new data is ready to be
AnnaBridge	145:64910690c574	803	* sent
AnnaBridge	145:64910690c574	804	* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
AnnaBridge	145:64910690c574	805	* each data transfer.
AnnaBridge	145:64910690c574	806	* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
AnnaBridge	145:64910690c574	807	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	808	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	809	*/
AnnaBridge	145:64910690c574	810	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	811	{
AnnaBridge	145:64910690c574	812	return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY));
AnnaBridge	145:64910690c574	813	}
AnnaBridge	145:64910690c574	814
AnnaBridge	145:64910690c574	815	/**
AnnaBridge	145:64910690c574	816	* @brief Get frame format error flag
AnnaBridge	145:64910690c574	817	* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
AnnaBridge	145:64910690c574	818	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	819	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	820	*/
AnnaBridge	145:64910690c574	821	__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	822	{
AnnaBridge	145:64910690c574	823	return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE));
AnnaBridge	145:64910690c574	824	}
AnnaBridge	145:64910690c574	825
AnnaBridge	145:64910690c574	826	/**
AnnaBridge	145:64910690c574	827	* @brief Clear CRC error flag
AnnaBridge	145:64910690c574	828	* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
AnnaBridge	145:64910690c574	829	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	830	* @retval None
AnnaBridge	145:64910690c574	831	*/
AnnaBridge	145:64910690c574	832	__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	833	{
AnnaBridge	145:64910690c574	834	CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
AnnaBridge	145:64910690c574	835	}
AnnaBridge	145:64910690c574	836
AnnaBridge	145:64910690c574	837	/**
AnnaBridge	145:64910690c574	838	* @brief Clear mode fault error flag
AnnaBridge	145:64910690c574	839	* @note Clearing this flag is done by a read access to the SPIx_SR
AnnaBridge	145:64910690c574	840	* register followed by a write access to the SPIx_CR1 register
AnnaBridge	145:64910690c574	841	* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
AnnaBridge	145:64910690c574	842	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	843	* @retval None
AnnaBridge	145:64910690c574	844	*/
AnnaBridge	145:64910690c574	845	__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	846	{
AnnaBridge	145:64910690c574	847	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	848	tmpreg = SPIx->SR;
AnnaBridge	145:64910690c574	849	(void) tmpreg;
AnnaBridge	145:64910690c574	850	tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
AnnaBridge	145:64910690c574	851	(void) tmpreg;
AnnaBridge	145:64910690c574	852	}
AnnaBridge	145:64910690c574	853
AnnaBridge	145:64910690c574	854	/**
AnnaBridge	145:64910690c574	855	* @brief Clear overrun error flag
AnnaBridge	145:64910690c574	856	* @note Clearing this flag is done by a read access to the SPIx_DR
AnnaBridge	145:64910690c574	857	* register followed by a read access to the SPIx_SR register
AnnaBridge	145:64910690c574	858	* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
AnnaBridge	145:64910690c574	859	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	860	* @retval None
AnnaBridge	145:64910690c574	861	*/
AnnaBridge	145:64910690c574	862	__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	863	{
AnnaBridge	145:64910690c574	864	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	865	tmpreg = SPIx->DR;
AnnaBridge	145:64910690c574	866	(void) tmpreg;
AnnaBridge	145:64910690c574	867	tmpreg = SPIx->SR;
AnnaBridge	145:64910690c574	868	(void) tmpreg;
AnnaBridge	145:64910690c574	869	}
AnnaBridge	145:64910690c574	870
AnnaBridge	145:64910690c574	871	/**
AnnaBridge	145:64910690c574	872	* @brief Clear frame format error flag
AnnaBridge	145:64910690c574	873	* @note Clearing this flag is done by reading SPIx_SR register
AnnaBridge	145:64910690c574	874	* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
AnnaBridge	145:64910690c574	875	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	876	* @retval None
AnnaBridge	145:64910690c574	877	*/
AnnaBridge	145:64910690c574	878	__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	879	{
AnnaBridge	145:64910690c574	880	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	881	tmpreg = SPIx->SR;
AnnaBridge	145:64910690c574	882	(void) tmpreg;
AnnaBridge	145:64910690c574	883	}
AnnaBridge	145:64910690c574	884
AnnaBridge	145:64910690c574	885	/**
AnnaBridge	145:64910690c574	886	* @}
AnnaBridge	145:64910690c574	887	*/
AnnaBridge	145:64910690c574	888
AnnaBridge	145:64910690c574	889	/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
AnnaBridge	145:64910690c574	890	* @{
AnnaBridge	145:64910690c574	891	*/
AnnaBridge	145:64910690c574	892
AnnaBridge	145:64910690c574	893	/**
AnnaBridge	145:64910690c574	894	* @brief Enable error interrupt
AnnaBridge	145:64910690c574	895	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	145:64910690c574	896	* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
AnnaBridge	145:64910690c574	897	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	898	* @retval None
AnnaBridge	145:64910690c574	899	*/
AnnaBridge	145:64910690c574	900	__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	901	{
AnnaBridge	145:64910690c574	902	SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	145:64910690c574	903	}
AnnaBridge	145:64910690c574	904
AnnaBridge	145:64910690c574	905	/**
AnnaBridge	145:64910690c574	906	* @brief Enable Rx buffer not empty interrupt
AnnaBridge	145:64910690c574	907	* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
AnnaBridge	145:64910690c574	908	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	909	* @retval None
AnnaBridge	145:64910690c574	910	*/
AnnaBridge	145:64910690c574	911	__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	912	{
AnnaBridge	145:64910690c574	913	SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	145:64910690c574	914	}
AnnaBridge	145:64910690c574	915
AnnaBridge	145:64910690c574	916	/**
AnnaBridge	145:64910690c574	917	* @brief Enable Tx buffer empty interrupt
AnnaBridge	145:64910690c574	918	* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
AnnaBridge	145:64910690c574	919	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	920	* @retval None
AnnaBridge	145:64910690c574	921	*/
AnnaBridge	145:64910690c574	922	__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	923	{
AnnaBridge	145:64910690c574	924	SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	145:64910690c574	925	}
AnnaBridge	145:64910690c574	926
AnnaBridge	145:64910690c574	927	/**
AnnaBridge	145:64910690c574	928	* @brief Disable error interrupt
AnnaBridge	145:64910690c574	929	* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
AnnaBridge	145:64910690c574	930	* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
AnnaBridge	145:64910690c574	931	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	932	* @retval None
AnnaBridge	145:64910690c574	933	*/
AnnaBridge	145:64910690c574	934	__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	935	{
AnnaBridge	145:64910690c574	936	CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
AnnaBridge	145:64910690c574	937	}
AnnaBridge	145:64910690c574	938
AnnaBridge	145:64910690c574	939	/**
AnnaBridge	145:64910690c574	940	* @brief Disable Rx buffer not empty interrupt
AnnaBridge	145:64910690c574	941	* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
AnnaBridge	145:64910690c574	942	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	943	* @retval None
AnnaBridge	145:64910690c574	944	*/
AnnaBridge	145:64910690c574	945	__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	946	{
AnnaBridge	145:64910690c574	947	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
AnnaBridge	145:64910690c574	948	}
AnnaBridge	145:64910690c574	949
AnnaBridge	145:64910690c574	950	/**
AnnaBridge	145:64910690c574	951	* @brief Disable Tx buffer empty interrupt
AnnaBridge	145:64910690c574	952	* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
AnnaBridge	145:64910690c574	953	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	954	* @retval None
AnnaBridge	145:64910690c574	955	*/
AnnaBridge	145:64910690c574	956	__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	957	{
AnnaBridge	145:64910690c574	958	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
AnnaBridge	145:64910690c574	959	}
AnnaBridge	145:64910690c574	960
AnnaBridge	145:64910690c574	961	/**
AnnaBridge	145:64910690c574	962	* @brief Check if error interrupt is enabled
AnnaBridge	145:64910690c574	963	* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
AnnaBridge	145:64910690c574	964	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	965	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	966	*/
AnnaBridge	145:64910690c574	967	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	968	{
AnnaBridge	145:64910690c574	969	return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE));
AnnaBridge	145:64910690c574	970	}
AnnaBridge	145:64910690c574	971
AnnaBridge	145:64910690c574	972	/**
AnnaBridge	145:64910690c574	973	* @brief Check if Rx buffer not empty interrupt is enabled
AnnaBridge	145:64910690c574	974	* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
AnnaBridge	145:64910690c574	975	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	976	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	977	*/
AnnaBridge	145:64910690c574	978	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	979	{
AnnaBridge	145:64910690c574	980	return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE));
AnnaBridge	145:64910690c574	981	}
AnnaBridge	145:64910690c574	982
AnnaBridge	145:64910690c574	983	/**
AnnaBridge	145:64910690c574	984	* @brief Check if Tx buffer empty interrupt
AnnaBridge	145:64910690c574	985	* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
AnnaBridge	145:64910690c574	986	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	987	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	988	*/
AnnaBridge	145:64910690c574	989	__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	990	{
AnnaBridge	145:64910690c574	991	return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE));
AnnaBridge	145:64910690c574	992	}
AnnaBridge	145:64910690c574	993
AnnaBridge	145:64910690c574	994	/**
AnnaBridge	145:64910690c574	995	* @}
AnnaBridge	145:64910690c574	996	*/
AnnaBridge	145:64910690c574	997
AnnaBridge	145:64910690c574	998	/** @defgroup SPI_LL_EF_DMA_Management DMA Management
AnnaBridge	145:64910690c574	999	* @{
AnnaBridge	145:64910690c574	1000	*/
AnnaBridge	145:64910690c574	1001
AnnaBridge	145:64910690c574	1002	/**
AnnaBridge	145:64910690c574	1003	* @brief Enable DMA Rx
AnnaBridge	145:64910690c574	1004	* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
AnnaBridge	145:64910690c574	1005	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1006	* @retval None
AnnaBridge	145:64910690c574	1007	*/
AnnaBridge	145:64910690c574	1008	__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1009	{
AnnaBridge	145:64910690c574	1010	SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	145:64910690c574	1011	}
AnnaBridge	145:64910690c574	1012
AnnaBridge	145:64910690c574	1013	/**
AnnaBridge	145:64910690c574	1014	* @brief Disable DMA Rx
AnnaBridge	145:64910690c574	1015	* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
AnnaBridge	145:64910690c574	1016	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1017	* @retval None
AnnaBridge	145:64910690c574	1018	*/
AnnaBridge	145:64910690c574	1019	__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1020	{
AnnaBridge	145:64910690c574	1021	CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
AnnaBridge	145:64910690c574	1022	}
AnnaBridge	145:64910690c574	1023
AnnaBridge	145:64910690c574	1024	/**
AnnaBridge	145:64910690c574	1025	* @brief Check if DMA Rx is enabled
AnnaBridge	145:64910690c574	1026	* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
AnnaBridge	145:64910690c574	1027	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1028	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1029	*/
AnnaBridge	145:64910690c574	1030	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1031	{
AnnaBridge	145:64910690c574	1032	return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN));
AnnaBridge	145:64910690c574	1033	}
AnnaBridge	145:64910690c574	1034
AnnaBridge	145:64910690c574	1035	/**
AnnaBridge	145:64910690c574	1036	* @brief Enable DMA Tx
AnnaBridge	145:64910690c574	1037	* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
AnnaBridge	145:64910690c574	1038	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1039	* @retval None
AnnaBridge	145:64910690c574	1040	*/
AnnaBridge	145:64910690c574	1041	__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1042	{
AnnaBridge	145:64910690c574	1043	SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	145:64910690c574	1044	}
AnnaBridge	145:64910690c574	1045
AnnaBridge	145:64910690c574	1046	/**
AnnaBridge	145:64910690c574	1047	* @brief Disable DMA Tx
AnnaBridge	145:64910690c574	1048	* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
AnnaBridge	145:64910690c574	1049	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1050	* @retval None
AnnaBridge	145:64910690c574	1051	*/
AnnaBridge	145:64910690c574	1052	__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1053	{
AnnaBridge	145:64910690c574	1054	CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
AnnaBridge	145:64910690c574	1055	}
AnnaBridge	145:64910690c574	1056
AnnaBridge	145:64910690c574	1057	/**
AnnaBridge	145:64910690c574	1058	* @brief Check if DMA Tx is enabled
AnnaBridge	145:64910690c574	1059	* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
AnnaBridge	145:64910690c574	1060	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1061	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1062	*/
AnnaBridge	145:64910690c574	1063	__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1064	{
AnnaBridge	145:64910690c574	1065	return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN));
AnnaBridge	145:64910690c574	1066	}
AnnaBridge	145:64910690c574	1067
AnnaBridge	145:64910690c574	1068	/**
AnnaBridge	145:64910690c574	1069	* @brief Get the data register address used for DMA transfer
AnnaBridge	145:64910690c574	1070	* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
AnnaBridge	145:64910690c574	1071	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1072	* @retval Address of data register
AnnaBridge	145:64910690c574	1073	*/
AnnaBridge	145:64910690c574	1074	__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1075	{
AnnaBridge	145:64910690c574	1076	return (uint32_t) & (SPIx->DR);
AnnaBridge	145:64910690c574	1077	}
AnnaBridge	145:64910690c574	1078
AnnaBridge	145:64910690c574	1079	/**
AnnaBridge	145:64910690c574	1080	* @}
AnnaBridge	145:64910690c574	1081	*/
AnnaBridge	145:64910690c574	1082
AnnaBridge	145:64910690c574	1083	/** @defgroup SPI_LL_EF_DATA_Management DATA Management
AnnaBridge	145:64910690c574	1084	* @{
AnnaBridge	145:64910690c574	1085	*/
AnnaBridge	145:64910690c574	1086
AnnaBridge	145:64910690c574	1087	/**
AnnaBridge	145:64910690c574	1088	* @brief Read 8-Bits in the data register
AnnaBridge	145:64910690c574	1089	* @rmtoll DR DR LL_SPI_ReceiveData8
AnnaBridge	145:64910690c574	1090	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1091	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	145:64910690c574	1092	*/
AnnaBridge	145:64910690c574	1093	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1094	{
AnnaBridge	145:64910690c574	1095	return (uint8_t)(READ_REG(SPIx->DR));
AnnaBridge	145:64910690c574	1096	}
AnnaBridge	145:64910690c574	1097
AnnaBridge	145:64910690c574	1098	/**
AnnaBridge	145:64910690c574	1099	* @brief Read 16-Bits in the data register
AnnaBridge	145:64910690c574	1100	* @rmtoll DR DR LL_SPI_ReceiveData16
AnnaBridge	145:64910690c574	1101	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1102	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	145:64910690c574	1103	*/
AnnaBridge	145:64910690c574	1104	__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1105	{
AnnaBridge	145:64910690c574	1106	return (uint16_t)(READ_REG(SPIx->DR));
AnnaBridge	145:64910690c574	1107	}
AnnaBridge	145:64910690c574	1108
AnnaBridge	145:64910690c574	1109	/**
AnnaBridge	145:64910690c574	1110	* @brief Write 8-Bits in the data register
AnnaBridge	145:64910690c574	1111	* @rmtoll DR DR LL_SPI_TransmitData8
AnnaBridge	145:64910690c574	1112	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1113	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	145:64910690c574	1114	* @retval None
AnnaBridge	145:64910690c574	1115	*/
AnnaBridge	145:64910690c574	1116	__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
AnnaBridge	145:64910690c574	1117	{
AnnaBridge	145:64910690c574	1118	SPIx->DR = TxData;
AnnaBridge	145:64910690c574	1119	}
AnnaBridge	145:64910690c574	1120
AnnaBridge	145:64910690c574	1121	/**
AnnaBridge	145:64910690c574	1122	* @brief Write 16-Bits in the data register
AnnaBridge	145:64910690c574	1123	* @rmtoll DR DR LL_SPI_TransmitData16
AnnaBridge	145:64910690c574	1124	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1125	* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	145:64910690c574	1126	* @retval None
AnnaBridge	145:64910690c574	1127	*/
AnnaBridge	145:64910690c574	1128	__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	145:64910690c574	1129	{
AnnaBridge	145:64910690c574	1130	SPIx->DR = TxData;
AnnaBridge	145:64910690c574	1131	}
AnnaBridge	145:64910690c574	1132
AnnaBridge	145:64910690c574	1133	/**
AnnaBridge	145:64910690c574	1134	* @}
AnnaBridge	145:64910690c574	1135	*/
AnnaBridge	145:64910690c574	1136	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	1137	/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	145:64910690c574	1138	* @{
AnnaBridge	145:64910690c574	1139	*/
AnnaBridge	145:64910690c574	1140
AnnaBridge	145:64910690c574	1141	ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	145:64910690c574	1142	ErrorStatus LL_SPI_Init(SPI_TypeDef SPIx, LL_SPI_InitTypeDef SPI_InitStruct);
AnnaBridge	145:64910690c574	1143	void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
AnnaBridge	145:64910690c574	1144
AnnaBridge	145:64910690c574	1145	/**
AnnaBridge	145:64910690c574	1146	* @}
AnnaBridge	145:64910690c574	1147	*/
AnnaBridge	145:64910690c574	1148	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	1149	/**
AnnaBridge	145:64910690c574	1150	* @}
AnnaBridge	145:64910690c574	1151	*/
AnnaBridge	145:64910690c574	1152
AnnaBridge	145:64910690c574	1153	/**
AnnaBridge	145:64910690c574	1154	* @}
AnnaBridge	145:64910690c574	1155	*/
AnnaBridge	145:64910690c574	1156
AnnaBridge	145:64910690c574	1157	/** @defgroup I2S_LL I2S
AnnaBridge	145:64910690c574	1158	* @{
AnnaBridge	145:64910690c574	1159	*/
AnnaBridge	145:64910690c574	1160
AnnaBridge	145:64910690c574	1161	/* Private variables ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	1162	/* Private constants ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	1163	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	1164
AnnaBridge	145:64910690c574	1165	/* Exported types ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	1166	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	1167	/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
AnnaBridge	145:64910690c574	1168	* @{
AnnaBridge	145:64910690c574	1169	*/
AnnaBridge	145:64910690c574	1170
AnnaBridge	145:64910690c574	1171	/**
AnnaBridge	145:64910690c574	1172	* @brief I2S Init structure definition
AnnaBridge	145:64910690c574	1173	*/
AnnaBridge	145:64910690c574	1174
AnnaBridge	145:64910690c574	1175	typedef struct
AnnaBridge	145:64910690c574	1176	{
AnnaBridge	145:64910690c574	1177	uint32_t Mode; /*!< Specifies the I2S operating mode.
AnnaBridge	145:64910690c574	1178	This parameter can be a value of @ref I2S_LL_EC_MODE
AnnaBridge	145:64910690c574	1179
AnnaBridge	145:64910690c574	1180	This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
AnnaBridge	145:64910690c574	1181
AnnaBridge	145:64910690c574	1182	uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
AnnaBridge	145:64910690c574	1183	This parameter can be a value of @ref I2S_LL_EC_STANDARD
AnnaBridge	145:64910690c574	1184
AnnaBridge	145:64910690c574	1185	This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
AnnaBridge	145:64910690c574	1186
AnnaBridge	145:64910690c574	1187
AnnaBridge	145:64910690c574	1188	uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
AnnaBridge	145:64910690c574	1189	This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
AnnaBridge	145:64910690c574	1190
AnnaBridge	145:64910690c574	1191	This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
AnnaBridge	145:64910690c574	1192
AnnaBridge	145:64910690c574	1193
AnnaBridge	145:64910690c574	1194	uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
AnnaBridge	145:64910690c574	1195	This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
AnnaBridge	145:64910690c574	1196
AnnaBridge	145:64910690c574	1197	This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
AnnaBridge	145:64910690c574	1198
AnnaBridge	145:64910690c574	1199
AnnaBridge	145:64910690c574	1200	uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
AnnaBridge	145:64910690c574	1201	This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
AnnaBridge	145:64910690c574	1202
AnnaBridge	145:64910690c574	1203	Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
AnnaBridge	145:64910690c574	1204	and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
AnnaBridge	145:64910690c574	1205
AnnaBridge	145:64910690c574	1206
AnnaBridge	145:64910690c574	1207	uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
AnnaBridge	145:64910690c574	1208	This parameter can be a value of @ref I2S_LL_EC_POLARITY
AnnaBridge	145:64910690c574	1209
AnnaBridge	145:64910690c574	1210	This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
AnnaBridge	145:64910690c574	1211
AnnaBridge	145:64910690c574	1212	} LL_I2S_InitTypeDef;
AnnaBridge	145:64910690c574	1213
AnnaBridge	145:64910690c574	1214	/**
AnnaBridge	145:64910690c574	1215	* @}
AnnaBridge	145:64910690c574	1216	*/
AnnaBridge	145:64910690c574	1217	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	145:64910690c574	1218
AnnaBridge	145:64910690c574	1219	/* Exported constants --------------------------------------------------------*/
AnnaBridge	145:64910690c574	1220	/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
AnnaBridge	145:64910690c574	1221	* @{
AnnaBridge	145:64910690c574	1222	*/
AnnaBridge	145:64910690c574	1223
AnnaBridge	145:64910690c574	1224	/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	145:64910690c574	1225	* @brief Flags defines which can be used with LL_I2S_ReadReg function
AnnaBridge	145:64910690c574	1226	* @{
AnnaBridge	145:64910690c574	1227	*/
AnnaBridge	145:64910690c574	1228	#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /!< Rx buffer not empty flag /
AnnaBridge	145:64910690c574	1229	#define LL_I2S_SR_TXE LL_SPI_SR_TXE /!< Tx buffer empty flag /
AnnaBridge	145:64910690c574	1230	#define LL_I2S_SR_BSY LL_SPI_SR_BSY /!< Busy flag /
AnnaBridge	145:64910690c574	1231	#define LL_I2S_SR_UDR SPI_SR_UDR /!< Underrun flag /
AnnaBridge	145:64910690c574	1232	#define LL_I2S_SR_OVR LL_SPI_SR_OVR /!< Overrun flag /
AnnaBridge	145:64910690c574	1233	#define LL_I2S_SR_FRE LL_SPI_SR_FRE /!< TI mode frame format error flag /
AnnaBridge	145:64910690c574	1234	/**
AnnaBridge	145:64910690c574	1235	* @}
AnnaBridge	145:64910690c574	1236	*/
AnnaBridge	145:64910690c574	1237
AnnaBridge	145:64910690c574	1238	/** @defgroup SPI_LL_EC_IT IT Defines
AnnaBridge	145:64910690c574	1239	* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
AnnaBridge	145:64910690c574	1240	* @{
AnnaBridge	145:64910690c574	1241	*/
AnnaBridge	145:64910690c574	1242	#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /!< Rx buffer not empty interrupt enable /
AnnaBridge	145:64910690c574	1243	#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /!< Tx buffer empty interrupt enable /
AnnaBridge	145:64910690c574	1244	#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /!< Error interrupt enable /
AnnaBridge	145:64910690c574	1245	/**
AnnaBridge	145:64910690c574	1246	* @}
AnnaBridge	145:64910690c574	1247	*/
AnnaBridge	145:64910690c574	1248
AnnaBridge	145:64910690c574	1249	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
AnnaBridge	145:64910690c574	1250	* @{
AnnaBridge	145:64910690c574	1251	*/
AnnaBridge	145:64910690c574	1252	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /
AnnaBridge	145:64910690c574	1253	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	145:64910690c574	1254	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /
AnnaBridge	145:64910690c574	1255	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /
AnnaBridge	145:64910690c574	1256	/**
AnnaBridge	145:64910690c574	1257	* @}
AnnaBridge	145:64910690c574	1258	*/
AnnaBridge	145:64910690c574	1259
AnnaBridge	145:64910690c574	1260	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
AnnaBridge	145:64910690c574	1261	* @{
AnnaBridge	145:64910690c574	1262	*/
AnnaBridge	145:64910690c574	1263	#define LL_I2S_POLARITY_LOW 0x00000000U /!< Clock steady state is low level /
AnnaBridge	145:64910690c574	1264	#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /!< Clock steady state is high level /
AnnaBridge	145:64910690c574	1265	/**
AnnaBridge	145:64910690c574	1266	* @}
AnnaBridge	145:64910690c574	1267	*/
AnnaBridge	145:64910690c574	1268
AnnaBridge	145:64910690c574	1269	/** @defgroup I2S_LL_EC_STANDARD I2s Standard
AnnaBridge	145:64910690c574	1270	* @{
AnnaBridge	145:64910690c574	1271	*/
AnnaBridge	145:64910690c574	1272	#define LL_I2S_STANDARD_PHILIPS 0x00000000U /!< I2S standard philips /
AnnaBridge	145:64910690c574	1273	#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /!< MSB justified standard (left justified) /
AnnaBridge	145:64910690c574	1274	#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /!< LSB justified standard (right justified) /
AnnaBridge	145:64910690c574	1275	#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1) /!< PCM standard, short frame synchronization /
AnnaBridge	145:64910690c574	1276	#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 \| SPI_I2SCFGR_I2SSTD_1 \| SPI_I2SCFGR_PCMSYNC) /!< PCM standard, long frame synchronization /
AnnaBridge	145:64910690c574	1277	/**
AnnaBridge	145:64910690c574	1278	* @}
AnnaBridge	145:64910690c574	1279	*/
AnnaBridge	145:64910690c574	1280
AnnaBridge	145:64910690c574	1281	/** @defgroup I2S_LL_EC_MODE Operation Mode
AnnaBridge	145:64910690c574	1282	* @{
AnnaBridge	145:64910690c574	1283	*/
AnnaBridge	145:64910690c574	1284	#define LL_I2S_MODE_SLAVE_TX 0x00000000U /!< Slave Tx configuration /
AnnaBridge	145:64910690c574	1285	#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /!< Slave Rx configuration /
AnnaBridge	145:64910690c574	1286	#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /!< Master Tx configuration /
AnnaBridge	145:64910690c574	1287	#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 \| SPI_I2SCFGR_I2SCFG_1) /!< Master Rx configuration /
AnnaBridge	145:64910690c574	1288	/**
AnnaBridge	145:64910690c574	1289	* @}
AnnaBridge	145:64910690c574	1290	*/
AnnaBridge	145:64910690c574	1291
AnnaBridge	145:64910690c574	1292	/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
AnnaBridge	145:64910690c574	1293	* @{
AnnaBridge	145:64910690c574	1294	*/
AnnaBridge	145:64910690c574	1295	#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /!< Odd factor: Real divider value is = I2SDIV 2 */
AnnaBridge	145:64910690c574	1296	#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /!< Odd factor: Real divider value is = (I2SDIV 2)+1 */
AnnaBridge	145:64910690c574	1297	/**
AnnaBridge	145:64910690c574	1298	* @}
AnnaBridge	145:64910690c574	1299	*/
AnnaBridge	145:64910690c574	1300
AnnaBridge	145:64910690c574	1301	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	1302
AnnaBridge	145:64910690c574	1303	/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
AnnaBridge	145:64910690c574	1304	* @{
AnnaBridge	145:64910690c574	1305	*/
AnnaBridge	145:64910690c574	1306	#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /!< Master clock output is disabled /
AnnaBridge	145:64910690c574	1307	#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /!< Master clock output is enabled /
AnnaBridge	145:64910690c574	1308	/**
AnnaBridge	145:64910690c574	1309	* @}
AnnaBridge	145:64910690c574	1310	*/
AnnaBridge	145:64910690c574	1311
AnnaBridge	145:64910690c574	1312	/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
AnnaBridge	145:64910690c574	1313	* @{
AnnaBridge	145:64910690c574	1314	*/
AnnaBridge	145:64910690c574	1315
AnnaBridge	145:64910690c574	1316	#define LL_I2S_AUDIOFREQ_192K 192000U /!< Audio Frequency configuration 192000 Hz /
AnnaBridge	145:64910690c574	1317	#define LL_I2S_AUDIOFREQ_96K 96000U /!< Audio Frequency configuration 96000 Hz /
AnnaBridge	145:64910690c574	1318	#define LL_I2S_AUDIOFREQ_48K 48000U /!< Audio Frequency configuration 48000 Hz /
AnnaBridge	145:64910690c574	1319	#define LL_I2S_AUDIOFREQ_44K 44100U /!< Audio Frequency configuration 44100 Hz /
AnnaBridge	145:64910690c574	1320	#define LL_I2S_AUDIOFREQ_32K 32000U /!< Audio Frequency configuration 32000 Hz /
AnnaBridge	145:64910690c574	1321	#define LL_I2S_AUDIOFREQ_22K 22050U /!< Audio Frequency configuration 22050 Hz /
AnnaBridge	145:64910690c574	1322	#define LL_I2S_AUDIOFREQ_16K 16000U /!< Audio Frequency configuration 16000 Hz /
AnnaBridge	145:64910690c574	1323	#define LL_I2S_AUDIOFREQ_11K 11025U /!< Audio Frequency configuration 11025 Hz /
AnnaBridge	145:64910690c574	1324	#define LL_I2S_AUDIOFREQ_8K 8000U /!< Audio Frequency configuration 8000 Hz /
AnnaBridge	145:64910690c574	1325	#define LL_I2S_AUDIOFREQ_DEFAULT 2U /!< Audio Freq not specified. Register I2SDIV = 2 /
AnnaBridge	145:64910690c574	1326	/**
AnnaBridge	145:64910690c574	1327	* @}
AnnaBridge	145:64910690c574	1328	*/
AnnaBridge	145:64910690c574	1329	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	1330
AnnaBridge	145:64910690c574	1331	/**
AnnaBridge	145:64910690c574	1332	* @}
AnnaBridge	145:64910690c574	1333	*/
AnnaBridge	145:64910690c574	1334
AnnaBridge	145:64910690c574	1335	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	1336	/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
AnnaBridge	145:64910690c574	1337	* @{
AnnaBridge	145:64910690c574	1338	*/
AnnaBridge	145:64910690c574	1339
AnnaBridge	145:64910690c574	1340	/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	145:64910690c574	1341	* @{
AnnaBridge	145:64910690c574	1342	*/
AnnaBridge	145:64910690c574	1343
AnnaBridge	145:64910690c574	1344	/**
AnnaBridge	145:64910690c574	1345	* @brief Write a value in I2S register
AnnaBridge	145:64910690c574	1346	* @param __INSTANCE__ I2S Instance
AnnaBridge	145:64910690c574	1347	* @param __REG__ Register to be written
AnnaBridge	145:64910690c574	1348	* @param __VALUE__ Value to be written in the register
AnnaBridge	145:64910690c574	1349	* @retval None
AnnaBridge	145:64910690c574	1350	*/
AnnaBridge	145:64910690c574	1351	#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	145:64910690c574	1352
AnnaBridge	145:64910690c574	1353	/**
AnnaBridge	145:64910690c574	1354	* @brief Read a value in I2S register
AnnaBridge	145:64910690c574	1355	* @param __INSTANCE__ I2S Instance
AnnaBridge	145:64910690c574	1356	* @param __REG__ Register to be read
AnnaBridge	145:64910690c574	1357	* @retval Register value
AnnaBridge	145:64910690c574	1358	*/
AnnaBridge	145:64910690c574	1359	#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	145:64910690c574	1360	/**
AnnaBridge	145:64910690c574	1361	* @}
AnnaBridge	145:64910690c574	1362	*/
AnnaBridge	145:64910690c574	1363
AnnaBridge	145:64910690c574	1364	/**
AnnaBridge	145:64910690c574	1365	* @}
AnnaBridge	145:64910690c574	1366	*/
AnnaBridge	145:64910690c574	1367
AnnaBridge	145:64910690c574	1368
AnnaBridge	145:64910690c574	1369	/* Exported functions --------------------------------------------------------*/
AnnaBridge	145:64910690c574	1370
AnnaBridge	145:64910690c574	1371	/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
AnnaBridge	145:64910690c574	1372	* @{
AnnaBridge	145:64910690c574	1373	*/
AnnaBridge	145:64910690c574	1374
AnnaBridge	145:64910690c574	1375	/** @defgroup I2S_LL_EF_Configuration Configuration
AnnaBridge	145:64910690c574	1376	* @{
AnnaBridge	145:64910690c574	1377	*/
AnnaBridge	145:64910690c574	1378
AnnaBridge	145:64910690c574	1379	/**
AnnaBridge	145:64910690c574	1380	* @brief Select I2S mode and Enable I2S peripheral
AnnaBridge	145:64910690c574	1381	* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
AnnaBridge	145:64910690c574	1382	* I2SCFGR I2SE LL_I2S_Enable
AnnaBridge	145:64910690c574	1383	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1384	* @retval None
AnnaBridge	145:64910690c574	1385	*/
AnnaBridge	145:64910690c574	1386	__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1387	{
AnnaBridge	145:64910690c574	1388	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	145:64910690c574	1389	}
AnnaBridge	145:64910690c574	1390
AnnaBridge	145:64910690c574	1391	/**
AnnaBridge	145:64910690c574	1392	* @brief Disable I2S peripheral
AnnaBridge	145:64910690c574	1393	* @rmtoll I2SCFGR I2SE LL_I2S_Disable
AnnaBridge	145:64910690c574	1394	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1395	* @retval None
AnnaBridge	145:64910690c574	1396	*/
AnnaBridge	145:64910690c574	1397	__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1398	{
AnnaBridge	145:64910690c574	1399	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD \| SPI_I2SCFGR_I2SE);
AnnaBridge	145:64910690c574	1400	}
AnnaBridge	145:64910690c574	1401
AnnaBridge	145:64910690c574	1402	/**
AnnaBridge	145:64910690c574	1403	* @brief Check if I2S peripheral is enabled
AnnaBridge	145:64910690c574	1404	* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
AnnaBridge	145:64910690c574	1405	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1406	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1407	*/
AnnaBridge	145:64910690c574	1408	__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1409	{
AnnaBridge	145:64910690c574	1410	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE));
AnnaBridge	145:64910690c574	1411	}
AnnaBridge	145:64910690c574	1412
AnnaBridge	145:64910690c574	1413	/**
AnnaBridge	145:64910690c574	1414	* @brief Set I2S data frame length
AnnaBridge	145:64910690c574	1415	* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
AnnaBridge	145:64910690c574	1416	* I2SCFGR CHLEN LL_I2S_SetDataFormat
AnnaBridge	145:64910690c574	1417	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1418	* @param DataFormat This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1419	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	145:64910690c574	1420	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	145:64910690c574	1421	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	145:64910690c574	1422	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	145:64910690c574	1423	* @retval None
AnnaBridge	145:64910690c574	1424	*/
AnnaBridge	145:64910690c574	1425	__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
AnnaBridge	145:64910690c574	1426	{
AnnaBridge	145:64910690c574	1427	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN, DataFormat);
AnnaBridge	145:64910690c574	1428	}
AnnaBridge	145:64910690c574	1429
AnnaBridge	145:64910690c574	1430	/**
AnnaBridge	145:64910690c574	1431	* @brief Get I2S data frame length
AnnaBridge	145:64910690c574	1432	* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
AnnaBridge	145:64910690c574	1433	* I2SCFGR CHLEN LL_I2S_GetDataFormat
AnnaBridge	145:64910690c574	1434	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1435	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1436	* @arg @ref LL_I2S_DATAFORMAT_16B
AnnaBridge	145:64910690c574	1437	* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
AnnaBridge	145:64910690c574	1438	* @arg @ref LL_I2S_DATAFORMAT_24B
AnnaBridge	145:64910690c574	1439	* @arg @ref LL_I2S_DATAFORMAT_32B
AnnaBridge	145:64910690c574	1440	*/
AnnaBridge	145:64910690c574	1441	__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1442	{
AnnaBridge	145:64910690c574	1443	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN \| SPI_I2SCFGR_CHLEN));
AnnaBridge	145:64910690c574	1444	}
AnnaBridge	145:64910690c574	1445
AnnaBridge	145:64910690c574	1446	/**
AnnaBridge	145:64910690c574	1447	* @brief Set I2S clock polarity
AnnaBridge	145:64910690c574	1448	* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
AnnaBridge	145:64910690c574	1449	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1450	* @param ClockPolarity This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1451	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	145:64910690c574	1452	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	145:64910690c574	1453	* @retval None
AnnaBridge	145:64910690c574	1454	*/
AnnaBridge	145:64910690c574	1455	__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
AnnaBridge	145:64910690c574	1456	{
AnnaBridge	145:64910690c574	1457	SET_BIT(SPIx->I2SCFGR, ClockPolarity);
AnnaBridge	145:64910690c574	1458	}
AnnaBridge	145:64910690c574	1459
AnnaBridge	145:64910690c574	1460	/**
AnnaBridge	145:64910690c574	1461	* @brief Get I2S clock polarity
AnnaBridge	145:64910690c574	1462	* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
AnnaBridge	145:64910690c574	1463	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1464	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1465	* @arg @ref LL_I2S_POLARITY_LOW
AnnaBridge	145:64910690c574	1466	* @arg @ref LL_I2S_POLARITY_HIGH
AnnaBridge	145:64910690c574	1467	*/
AnnaBridge	145:64910690c574	1468	__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1469	{
AnnaBridge	145:64910690c574	1470	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
AnnaBridge	145:64910690c574	1471	}
AnnaBridge	145:64910690c574	1472
AnnaBridge	145:64910690c574	1473	/**
AnnaBridge	145:64910690c574	1474	* @brief Set I2S standard protocol
AnnaBridge	145:64910690c574	1475	* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
AnnaBridge	145:64910690c574	1476	* I2SCFGR PCMSYNC LL_I2S_SetStandard
AnnaBridge	145:64910690c574	1477	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1478	* @param Standard This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1479	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	145:64910690c574	1480	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	145:64910690c574	1481	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	145:64910690c574	1482	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	145:64910690c574	1483	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	145:64910690c574	1484	* @retval None
AnnaBridge	145:64910690c574	1485	*/
AnnaBridge	145:64910690c574	1486	__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
AnnaBridge	145:64910690c574	1487	{
AnnaBridge	145:64910690c574	1488	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC, Standard);
AnnaBridge	145:64910690c574	1489	}
AnnaBridge	145:64910690c574	1490
AnnaBridge	145:64910690c574	1491	/**
AnnaBridge	145:64910690c574	1492	* @brief Get I2S standard protocol
AnnaBridge	145:64910690c574	1493	* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
AnnaBridge	145:64910690c574	1494	* I2SCFGR PCMSYNC LL_I2S_GetStandard
AnnaBridge	145:64910690c574	1495	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1496	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1497	* @arg @ref LL_I2S_STANDARD_PHILIPS
AnnaBridge	145:64910690c574	1498	* @arg @ref LL_I2S_STANDARD_MSB
AnnaBridge	145:64910690c574	1499	* @arg @ref LL_I2S_STANDARD_LSB
AnnaBridge	145:64910690c574	1500	* @arg @ref LL_I2S_STANDARD_PCM_SHORT
AnnaBridge	145:64910690c574	1501	* @arg @ref LL_I2S_STANDARD_PCM_LONG
AnnaBridge	145:64910690c574	1502	*/
AnnaBridge	145:64910690c574	1503	__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1504	{
AnnaBridge	145:64910690c574	1505	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD \| SPI_I2SCFGR_PCMSYNC));
AnnaBridge	145:64910690c574	1506	}
AnnaBridge	145:64910690c574	1507
AnnaBridge	145:64910690c574	1508	/**
AnnaBridge	145:64910690c574	1509	* @brief Set I2S transfer mode
AnnaBridge	145:64910690c574	1510	* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
AnnaBridge	145:64910690c574	1511	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1512	* @param Mode This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1513	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	145:64910690c574	1514	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	145:64910690c574	1515	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	145:64910690c574	1516	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	145:64910690c574	1517	* @retval None
AnnaBridge	145:64910690c574	1518	*/
AnnaBridge	145:64910690c574	1519	__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
AnnaBridge	145:64910690c574	1520	{
AnnaBridge	145:64910690c574	1521	MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
AnnaBridge	145:64910690c574	1522	}
AnnaBridge	145:64910690c574	1523
AnnaBridge	145:64910690c574	1524	/**
AnnaBridge	145:64910690c574	1525	* @brief Get I2S transfer mode
AnnaBridge	145:64910690c574	1526	* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
AnnaBridge	145:64910690c574	1527	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1528	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1529	* @arg @ref LL_I2S_MODE_SLAVE_TX
AnnaBridge	145:64910690c574	1530	* @arg @ref LL_I2S_MODE_SLAVE_RX
AnnaBridge	145:64910690c574	1531	* @arg @ref LL_I2S_MODE_MASTER_TX
AnnaBridge	145:64910690c574	1532	* @arg @ref LL_I2S_MODE_MASTER_RX
AnnaBridge	145:64910690c574	1533	*/
AnnaBridge	145:64910690c574	1534	__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1535	{
AnnaBridge	145:64910690c574	1536	return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
AnnaBridge	145:64910690c574	1537	}
AnnaBridge	145:64910690c574	1538
AnnaBridge	145:64910690c574	1539	/**
AnnaBridge	145:64910690c574	1540	* @brief Set I2S linear prescaler
AnnaBridge	145:64910690c574	1541	* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
AnnaBridge	145:64910690c574	1542	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1543	* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	145:64910690c574	1544	* @retval None
AnnaBridge	145:64910690c574	1545	*/
AnnaBridge	145:64910690c574	1546	__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
AnnaBridge	145:64910690c574	1547	{
AnnaBridge	145:64910690c574	1548	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
AnnaBridge	145:64910690c574	1549	}
AnnaBridge	145:64910690c574	1550
AnnaBridge	145:64910690c574	1551	/**
AnnaBridge	145:64910690c574	1552	* @brief Get I2S linear prescaler
AnnaBridge	145:64910690c574	1553	* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
AnnaBridge	145:64910690c574	1554	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1555	* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
AnnaBridge	145:64910690c574	1556	*/
AnnaBridge	145:64910690c574	1557	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1558	{
AnnaBridge	145:64910690c574	1559	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
AnnaBridge	145:64910690c574	1560	}
AnnaBridge	145:64910690c574	1561
AnnaBridge	145:64910690c574	1562	/**
AnnaBridge	145:64910690c574	1563	* @brief Set I2S parity prescaler
AnnaBridge	145:64910690c574	1564	* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
AnnaBridge	145:64910690c574	1565	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1566	* @param PrescalerParity This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1567	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	145:64910690c574	1568	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	145:64910690c574	1569	* @retval None
AnnaBridge	145:64910690c574	1570	*/
AnnaBridge	145:64910690c574	1571	__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
AnnaBridge	145:64910690c574	1572	{
AnnaBridge	145:64910690c574	1573	MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
AnnaBridge	145:64910690c574	1574	}
AnnaBridge	145:64910690c574	1575
AnnaBridge	145:64910690c574	1576	/**
AnnaBridge	145:64910690c574	1577	* @brief Get I2S parity prescaler
AnnaBridge	145:64910690c574	1578	* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
AnnaBridge	145:64910690c574	1579	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1580	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1581	* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
AnnaBridge	145:64910690c574	1582	* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
AnnaBridge	145:64910690c574	1583	*/
AnnaBridge	145:64910690c574	1584	__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1585	{
AnnaBridge	145:64910690c574	1586	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
AnnaBridge	145:64910690c574	1587	}
AnnaBridge	145:64910690c574	1588
AnnaBridge	145:64910690c574	1589	/**
AnnaBridge	145:64910690c574	1590	* @brief Enable the master clock ouput (Pin MCK)
AnnaBridge	145:64910690c574	1591	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
AnnaBridge	145:64910690c574	1592	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1593	* @retval None
AnnaBridge	145:64910690c574	1594	*/
AnnaBridge	145:64910690c574	1595	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1596	{
AnnaBridge	145:64910690c574	1597	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	145:64910690c574	1598	}
AnnaBridge	145:64910690c574	1599
AnnaBridge	145:64910690c574	1600	/**
AnnaBridge	145:64910690c574	1601	* @brief Disable the master clock ouput (Pin MCK)
AnnaBridge	145:64910690c574	1602	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
AnnaBridge	145:64910690c574	1603	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1604	* @retval None
AnnaBridge	145:64910690c574	1605	*/
AnnaBridge	145:64910690c574	1606	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1607	{
AnnaBridge	145:64910690c574	1608	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
AnnaBridge	145:64910690c574	1609	}
AnnaBridge	145:64910690c574	1610
AnnaBridge	145:64910690c574	1611	/**
AnnaBridge	145:64910690c574	1612	* @brief Check if the master clock ouput (Pin MCK) is enabled
AnnaBridge	145:64910690c574	1613	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
AnnaBridge	145:64910690c574	1614	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1615	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1616	*/
AnnaBridge	145:64910690c574	1617	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1618	{
AnnaBridge	145:64910690c574	1619	return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE));
AnnaBridge	145:64910690c574	1620	}
AnnaBridge	145:64910690c574	1621
AnnaBridge	145:64910690c574	1622	#if defined(SPI_I2SCFGR_ASTRTEN)
AnnaBridge	145:64910690c574	1623	/**
AnnaBridge	145:64910690c574	1624	* @brief Enable asynchronous start
AnnaBridge	145:64910690c574	1625	* @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
AnnaBridge	145:64910690c574	1626	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1627	* @retval None
AnnaBridge	145:64910690c574	1628	*/
AnnaBridge	145:64910690c574	1629	__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1630	{
AnnaBridge	145:64910690c574	1631	SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
AnnaBridge	145:64910690c574	1632	}
AnnaBridge	145:64910690c574	1633
AnnaBridge	145:64910690c574	1634	/**
AnnaBridge	145:64910690c574	1635	* @brief Disable asynchronous start
AnnaBridge	145:64910690c574	1636	* @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
AnnaBridge	145:64910690c574	1637	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1638	* @retval None
AnnaBridge	145:64910690c574	1639	*/
AnnaBridge	145:64910690c574	1640	__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1641	{
AnnaBridge	145:64910690c574	1642	CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
AnnaBridge	145:64910690c574	1643	}
AnnaBridge	145:64910690c574	1644
AnnaBridge	145:64910690c574	1645	/**
AnnaBridge	145:64910690c574	1646	* @brief Check if asynchronous start is enabled
AnnaBridge	145:64910690c574	1647	* @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
AnnaBridge	145:64910690c574	1648	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1649	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1650	*/
AnnaBridge	145:64910690c574	1651	__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1652	{
AnnaBridge	145:64910690c574	1653	return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN));
AnnaBridge	145:64910690c574	1654	}
AnnaBridge	145:64910690c574	1655	#endif /* SPI_I2SCFGR_ASTRTEN */
AnnaBridge	145:64910690c574	1656
AnnaBridge	145:64910690c574	1657	/**
AnnaBridge	145:64910690c574	1658	* @}
AnnaBridge	145:64910690c574	1659	*/
AnnaBridge	145:64910690c574	1660
AnnaBridge	145:64910690c574	1661	/** @defgroup I2S_LL_EF_FLAG FLAG Management
AnnaBridge	145:64910690c574	1662	* @{
AnnaBridge	145:64910690c574	1663	*/
AnnaBridge	145:64910690c574	1664
AnnaBridge	145:64910690c574	1665	/**
AnnaBridge	145:64910690c574	1666	* @brief Check if Rx buffer is not empty
AnnaBridge	145:64910690c574	1667	* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
AnnaBridge	145:64910690c574	1668	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1669	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1670	*/
AnnaBridge	145:64910690c574	1671	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1672	{
AnnaBridge	145:64910690c574	1673	return LL_SPI_IsActiveFlag_RXNE(SPIx);
AnnaBridge	145:64910690c574	1674	}
AnnaBridge	145:64910690c574	1675
AnnaBridge	145:64910690c574	1676	/**
AnnaBridge	145:64910690c574	1677	* @brief Check if Tx buffer is empty
AnnaBridge	145:64910690c574	1678	* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
AnnaBridge	145:64910690c574	1679	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1680	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1681	*/
AnnaBridge	145:64910690c574	1682	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1683	{
AnnaBridge	145:64910690c574	1684	return LL_SPI_IsActiveFlag_TXE(SPIx);
AnnaBridge	145:64910690c574	1685	}
AnnaBridge	145:64910690c574	1686
AnnaBridge	145:64910690c574	1687	/**
AnnaBridge	145:64910690c574	1688	* @brief Get busy flag
AnnaBridge	145:64910690c574	1689	* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
AnnaBridge	145:64910690c574	1690	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1691	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1692	*/
AnnaBridge	145:64910690c574	1693	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1694	{
AnnaBridge	145:64910690c574	1695	return LL_SPI_IsActiveFlag_BSY(SPIx);
AnnaBridge	145:64910690c574	1696	}
AnnaBridge	145:64910690c574	1697
AnnaBridge	145:64910690c574	1698	/**
AnnaBridge	145:64910690c574	1699	* @brief Get overrun error flag
AnnaBridge	145:64910690c574	1700	* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
AnnaBridge	145:64910690c574	1701	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1702	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1703	*/
AnnaBridge	145:64910690c574	1704	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1705	{
AnnaBridge	145:64910690c574	1706	return LL_SPI_IsActiveFlag_OVR(SPIx);
AnnaBridge	145:64910690c574	1707	}
AnnaBridge	145:64910690c574	1708
AnnaBridge	145:64910690c574	1709	/**
AnnaBridge	145:64910690c574	1710	* @brief Get underrun error flag
AnnaBridge	145:64910690c574	1711	* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
AnnaBridge	145:64910690c574	1712	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1713	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1714	*/
AnnaBridge	145:64910690c574	1715	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1716	{
AnnaBridge	145:64910690c574	1717	return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR));
AnnaBridge	145:64910690c574	1718	}
AnnaBridge	145:64910690c574	1719
AnnaBridge	145:64910690c574	1720	/**
AnnaBridge	145:64910690c574	1721	* @brief Get frame format error flag
AnnaBridge	145:64910690c574	1722	* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
AnnaBridge	145:64910690c574	1723	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1724	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1725	*/
AnnaBridge	145:64910690c574	1726	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1727	{
AnnaBridge	145:64910690c574	1728	return LL_SPI_IsActiveFlag_FRE(SPIx);
AnnaBridge	145:64910690c574	1729	}
AnnaBridge	145:64910690c574	1730
AnnaBridge	145:64910690c574	1731	/**
AnnaBridge	145:64910690c574	1732	* @brief Get channel side flag.
AnnaBridge	145:64910690c574	1733	* @note 0: Channel Left has to be transmitted or has been received\n
AnnaBridge	145:64910690c574	1734	* 1: Channel Right has to be transmitted or has been received\n
AnnaBridge	145:64910690c574	1735	* It has no significance in PCM mode.
AnnaBridge	145:64910690c574	1736	* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
AnnaBridge	145:64910690c574	1737	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1738	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1739	*/
AnnaBridge	145:64910690c574	1740	__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1741	{
AnnaBridge	145:64910690c574	1742	return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE));
AnnaBridge	145:64910690c574	1743	}
AnnaBridge	145:64910690c574	1744
AnnaBridge	145:64910690c574	1745	/**
AnnaBridge	145:64910690c574	1746	* @brief Clear overrun error flag
AnnaBridge	145:64910690c574	1747	* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
AnnaBridge	145:64910690c574	1748	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1749	* @retval None
AnnaBridge	145:64910690c574	1750	*/
AnnaBridge	145:64910690c574	1751	__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1752	{
AnnaBridge	145:64910690c574	1753	LL_SPI_ClearFlag_OVR(SPIx);
AnnaBridge	145:64910690c574	1754	}
AnnaBridge	145:64910690c574	1755
AnnaBridge	145:64910690c574	1756	/**
AnnaBridge	145:64910690c574	1757	* @brief Clear underrun error flag
AnnaBridge	145:64910690c574	1758	* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
AnnaBridge	145:64910690c574	1759	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1760	* @retval None
AnnaBridge	145:64910690c574	1761	*/
AnnaBridge	145:64910690c574	1762	__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1763	{
AnnaBridge	145:64910690c574	1764	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1765	tmpreg = SPIx->SR;
AnnaBridge	145:64910690c574	1766	(void)tmpreg;
AnnaBridge	145:64910690c574	1767	}
AnnaBridge	145:64910690c574	1768
AnnaBridge	145:64910690c574	1769	/**
AnnaBridge	145:64910690c574	1770	* @brief Clear frame format error flag
AnnaBridge	145:64910690c574	1771	* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
AnnaBridge	145:64910690c574	1772	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1773	* @retval None
AnnaBridge	145:64910690c574	1774	*/
AnnaBridge	145:64910690c574	1775	__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1776	{
AnnaBridge	145:64910690c574	1777	LL_SPI_ClearFlag_FRE(SPIx);
AnnaBridge	145:64910690c574	1778	}
AnnaBridge	145:64910690c574	1779
AnnaBridge	145:64910690c574	1780	/**
AnnaBridge	145:64910690c574	1781	* @}
AnnaBridge	145:64910690c574	1782	*/
AnnaBridge	145:64910690c574	1783
AnnaBridge	145:64910690c574	1784	/** @defgroup I2S_LL_EF_IT Interrupt Management
AnnaBridge	145:64910690c574	1785	* @{
AnnaBridge	145:64910690c574	1786	*/
AnnaBridge	145:64910690c574	1787
AnnaBridge	145:64910690c574	1788	/**
AnnaBridge	145:64910690c574	1789	* @brief Enable error IT
AnnaBridge	145:64910690c574	1790	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	145:64910690c574	1791	* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
AnnaBridge	145:64910690c574	1792	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1793	* @retval None
AnnaBridge	145:64910690c574	1794	*/
AnnaBridge	145:64910690c574	1795	__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1796	{
AnnaBridge	145:64910690c574	1797	LL_SPI_EnableIT_ERR(SPIx);
AnnaBridge	145:64910690c574	1798	}
AnnaBridge	145:64910690c574	1799
AnnaBridge	145:64910690c574	1800	/**
AnnaBridge	145:64910690c574	1801	* @brief Enable Rx buffer not empty IT
AnnaBridge	145:64910690c574	1802	* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
AnnaBridge	145:64910690c574	1803	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1804	* @retval None
AnnaBridge	145:64910690c574	1805	*/
AnnaBridge	145:64910690c574	1806	__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1807	{
AnnaBridge	145:64910690c574	1808	LL_SPI_EnableIT_RXNE(SPIx);
AnnaBridge	145:64910690c574	1809	}
AnnaBridge	145:64910690c574	1810
AnnaBridge	145:64910690c574	1811	/**
AnnaBridge	145:64910690c574	1812	* @brief Enable Tx buffer empty IT
AnnaBridge	145:64910690c574	1813	* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
AnnaBridge	145:64910690c574	1814	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1815	* @retval None
AnnaBridge	145:64910690c574	1816	*/
AnnaBridge	145:64910690c574	1817	__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1818	{
AnnaBridge	145:64910690c574	1819	LL_SPI_EnableIT_TXE(SPIx);
AnnaBridge	145:64910690c574	1820	}
AnnaBridge	145:64910690c574	1821
AnnaBridge	145:64910690c574	1822	/**
AnnaBridge	145:64910690c574	1823	* @brief Disable error IT
AnnaBridge	145:64910690c574	1824	* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
AnnaBridge	145:64910690c574	1825	* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
AnnaBridge	145:64910690c574	1826	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1827	* @retval None
AnnaBridge	145:64910690c574	1828	*/
AnnaBridge	145:64910690c574	1829	__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1830	{
AnnaBridge	145:64910690c574	1831	LL_SPI_DisableIT_ERR(SPIx);
AnnaBridge	145:64910690c574	1832	}
AnnaBridge	145:64910690c574	1833
AnnaBridge	145:64910690c574	1834	/**
AnnaBridge	145:64910690c574	1835	* @brief Disable Rx buffer not empty IT
AnnaBridge	145:64910690c574	1836	* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
AnnaBridge	145:64910690c574	1837	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1838	* @retval None
AnnaBridge	145:64910690c574	1839	*/
AnnaBridge	145:64910690c574	1840	__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1841	{
AnnaBridge	145:64910690c574	1842	LL_SPI_DisableIT_RXNE(SPIx);
AnnaBridge	145:64910690c574	1843	}
AnnaBridge	145:64910690c574	1844
AnnaBridge	145:64910690c574	1845	/**
AnnaBridge	145:64910690c574	1846	* @brief Disable Tx buffer empty IT
AnnaBridge	145:64910690c574	1847	* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
AnnaBridge	145:64910690c574	1848	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1849	* @retval None
AnnaBridge	145:64910690c574	1850	*/
AnnaBridge	145:64910690c574	1851	__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1852	{
AnnaBridge	145:64910690c574	1853	LL_SPI_DisableIT_TXE(SPIx);
AnnaBridge	145:64910690c574	1854	}
AnnaBridge	145:64910690c574	1855
AnnaBridge	145:64910690c574	1856	/**
AnnaBridge	145:64910690c574	1857	* @brief Check if ERR IT is enabled
AnnaBridge	145:64910690c574	1858	* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
AnnaBridge	145:64910690c574	1859	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1860	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1861	*/
AnnaBridge	145:64910690c574	1862	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1863	{
AnnaBridge	145:64910690c574	1864	return LL_SPI_IsEnabledIT_ERR(SPIx);
AnnaBridge	145:64910690c574	1865	}
AnnaBridge	145:64910690c574	1866
AnnaBridge	145:64910690c574	1867	/**
AnnaBridge	145:64910690c574	1868	* @brief Check if RXNE IT is enabled
AnnaBridge	145:64910690c574	1869	* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
AnnaBridge	145:64910690c574	1870	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1871	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1872	*/
AnnaBridge	145:64910690c574	1873	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1874	{
AnnaBridge	145:64910690c574	1875	return LL_SPI_IsEnabledIT_RXNE(SPIx);
AnnaBridge	145:64910690c574	1876	}
AnnaBridge	145:64910690c574	1877
AnnaBridge	145:64910690c574	1878	/**
AnnaBridge	145:64910690c574	1879	* @brief Check if TXE IT is enabled
AnnaBridge	145:64910690c574	1880	* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
AnnaBridge	145:64910690c574	1881	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1882	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1883	*/
AnnaBridge	145:64910690c574	1884	__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1885	{
AnnaBridge	145:64910690c574	1886	return LL_SPI_IsEnabledIT_TXE(SPIx);
AnnaBridge	145:64910690c574	1887	}
AnnaBridge	145:64910690c574	1888
AnnaBridge	145:64910690c574	1889	/**
AnnaBridge	145:64910690c574	1890	* @}
AnnaBridge	145:64910690c574	1891	*/
AnnaBridge	145:64910690c574	1892
AnnaBridge	145:64910690c574	1893	/** @defgroup I2S_LL_EF_DMA DMA Management
AnnaBridge	145:64910690c574	1894	* @{
AnnaBridge	145:64910690c574	1895	*/
AnnaBridge	145:64910690c574	1896
AnnaBridge	145:64910690c574	1897	/**
AnnaBridge	145:64910690c574	1898	* @brief Enable DMA Rx
AnnaBridge	145:64910690c574	1899	* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
AnnaBridge	145:64910690c574	1900	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1901	* @retval None
AnnaBridge	145:64910690c574	1902	*/
AnnaBridge	145:64910690c574	1903	__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1904	{
AnnaBridge	145:64910690c574	1905	LL_SPI_EnableDMAReq_RX(SPIx);
AnnaBridge	145:64910690c574	1906	}
AnnaBridge	145:64910690c574	1907
AnnaBridge	145:64910690c574	1908	/**
AnnaBridge	145:64910690c574	1909	* @brief Disable DMA Rx
AnnaBridge	145:64910690c574	1910	* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
AnnaBridge	145:64910690c574	1911	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1912	* @retval None
AnnaBridge	145:64910690c574	1913	*/
AnnaBridge	145:64910690c574	1914	__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1915	{
AnnaBridge	145:64910690c574	1916	LL_SPI_DisableDMAReq_RX(SPIx);
AnnaBridge	145:64910690c574	1917	}
AnnaBridge	145:64910690c574	1918
AnnaBridge	145:64910690c574	1919	/**
AnnaBridge	145:64910690c574	1920	* @brief Check if DMA Rx is enabled
AnnaBridge	145:64910690c574	1921	* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
AnnaBridge	145:64910690c574	1922	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1923	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1924	*/
AnnaBridge	145:64910690c574	1925	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1926	{
AnnaBridge	145:64910690c574	1927	return LL_SPI_IsEnabledDMAReq_RX(SPIx);
AnnaBridge	145:64910690c574	1928	}
AnnaBridge	145:64910690c574	1929
AnnaBridge	145:64910690c574	1930	/**
AnnaBridge	145:64910690c574	1931	* @brief Enable DMA Tx
AnnaBridge	145:64910690c574	1932	* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
AnnaBridge	145:64910690c574	1933	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1934	* @retval None
AnnaBridge	145:64910690c574	1935	*/
AnnaBridge	145:64910690c574	1936	__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1937	{
AnnaBridge	145:64910690c574	1938	LL_SPI_EnableDMAReq_TX(SPIx);
AnnaBridge	145:64910690c574	1939	}
AnnaBridge	145:64910690c574	1940
AnnaBridge	145:64910690c574	1941	/**
AnnaBridge	145:64910690c574	1942	* @brief Disable DMA Tx
AnnaBridge	145:64910690c574	1943	* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
AnnaBridge	145:64910690c574	1944	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1945	* @retval None
AnnaBridge	145:64910690c574	1946	*/
AnnaBridge	145:64910690c574	1947	__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1948	{
AnnaBridge	145:64910690c574	1949	LL_SPI_DisableDMAReq_TX(SPIx);
AnnaBridge	145:64910690c574	1950	}
AnnaBridge	145:64910690c574	1951
AnnaBridge	145:64910690c574	1952	/**
AnnaBridge	145:64910690c574	1953	* @brief Check if DMA Tx is enabled
AnnaBridge	145:64910690c574	1954	* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
AnnaBridge	145:64910690c574	1955	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1956	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1957	*/
AnnaBridge	145:64910690c574	1958	__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1959	{
AnnaBridge	145:64910690c574	1960	return LL_SPI_IsEnabledDMAReq_TX(SPIx);
AnnaBridge	145:64910690c574	1961	}
AnnaBridge	145:64910690c574	1962
AnnaBridge	145:64910690c574	1963	/**
AnnaBridge	145:64910690c574	1964	* @}
AnnaBridge	145:64910690c574	1965	*/
AnnaBridge	145:64910690c574	1966
AnnaBridge	145:64910690c574	1967	/** @defgroup I2S_LL_EF_DATA DATA Management
AnnaBridge	145:64910690c574	1968	* @{
AnnaBridge	145:64910690c574	1969	*/
AnnaBridge	145:64910690c574	1970
AnnaBridge	145:64910690c574	1971	/**
AnnaBridge	145:64910690c574	1972	* @brief Read 16-Bits in data register
AnnaBridge	145:64910690c574	1973	* @rmtoll DR DR LL_I2S_ReceiveData16
AnnaBridge	145:64910690c574	1974	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1975	* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	145:64910690c574	1976	*/
AnnaBridge	145:64910690c574	1977	__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
AnnaBridge	145:64910690c574	1978	{
AnnaBridge	145:64910690c574	1979	return LL_SPI_ReceiveData16(SPIx);
AnnaBridge	145:64910690c574	1980	}
AnnaBridge	145:64910690c574	1981
AnnaBridge	145:64910690c574	1982	/**
AnnaBridge	145:64910690c574	1983	* @brief Write 16-Bits in data register
AnnaBridge	145:64910690c574	1984	* @rmtoll DR DR LL_I2S_TransmitData16
AnnaBridge	145:64910690c574	1985	* @param SPIx SPI Instance
AnnaBridge	145:64910690c574	1986	* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
AnnaBridge	145:64910690c574	1987	* @retval None
AnnaBridge	145:64910690c574	1988	*/
AnnaBridge	145:64910690c574	1989	__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
AnnaBridge	145:64910690c574	1990	{
AnnaBridge	145:64910690c574	1991	LL_SPI_TransmitData16(SPIx, TxData);
AnnaBridge	145:64910690c574	1992	}
AnnaBridge	145:64910690c574	1993
AnnaBridge	145:64910690c574	1994	/**
AnnaBridge	145:64910690c574	1995	* @}
AnnaBridge	145:64910690c574	1996	*/
AnnaBridge	145:64910690c574	1997
AnnaBridge	145:64910690c574	1998	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	1999	/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	145:64910690c574	2000	* @{
AnnaBridge	145:64910690c574	2001	*/
AnnaBridge	145:64910690c574	2002
AnnaBridge	145:64910690c574	2003	ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
AnnaBridge	145:64910690c574	2004	ErrorStatus LL_I2S_Init(SPI_TypeDef SPIx, LL_I2S_InitTypeDef I2S_InitStruct);
AnnaBridge	145:64910690c574	2005	void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
AnnaBridge	145:64910690c574	2006	void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
AnnaBridge	145:64910690c574	2007	#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
AnnaBridge	145:64910690c574	2008	ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef I2Sxext, LL_I2S_InitTypeDef I2S_InitStruct);
AnnaBridge	145:64910690c574	2009	#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
AnnaBridge	145:64910690c574	2010
AnnaBridge	145:64910690c574	2011	/**
AnnaBridge	145:64910690c574	2012	* @}
AnnaBridge	145:64910690c574	2013	*/
AnnaBridge	145:64910690c574	2014	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	2015
AnnaBridge	145:64910690c574	2016	/**
AnnaBridge	145:64910690c574	2017	* @}
AnnaBridge	145:64910690c574	2018	*/
AnnaBridge	145:64910690c574	2019
AnnaBridge	145:64910690c574	2020	/**
AnnaBridge	145:64910690c574	2021	* @}
AnnaBridge	145:64910690c574	2022	*/
AnnaBridge	145:64910690c574	2023
AnnaBridge	145:64910690c574	2024	#endif /* defined (SPI1) \|\| defined (SPI2) \|\| defined (SPI3) \|\| defined (SPI4) \|\| defined (SPI5) \|\| defined(SPI6) */
AnnaBridge	145:64910690c574	2025
AnnaBridge	145:64910690c574	2026	/**
AnnaBridge	145:64910690c574	2027	* @}
AnnaBridge	145:64910690c574	2028	*/
AnnaBridge	145:64910690c574	2029
AnnaBridge	145:64910690c574	2030	#ifdef __cplusplus
AnnaBridge	145:64910690c574	2031	}
AnnaBridge	145:64910690c574	2032	#endif
AnnaBridge	145:64910690c574	2033
AnnaBridge	145:64910690c574	2034	#endif /* __STM32F4xx_LL_SPI_H */
AnnaBridge	145:64910690c574	2035
AnnaBridge	145:64910690c574	2036	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/