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TARGET_ELMO_F411RE/TOOLCHAIN_GCC_ARM/stm32f4xx_ll_sdmmc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
Anna Bridge	160:5571c4ff569f	1	/**
Anna Bridge	160:5571c4ff569f	2	******************************************************************************
Anna Bridge	160:5571c4ff569f	3	* @file stm32f4xx_ll_sdmmc.h
Anna Bridge	160:5571c4ff569f	4	* @author MCD Application Team
Anna Bridge	160:5571c4ff569f	5	* @brief Header file of SDMMC HAL module.
Anna Bridge	160:5571c4ff569f	6	******************************************************************************
Anna Bridge	160:5571c4ff569f	7	* @attention
Anna Bridge	160:5571c4ff569f	8	*
Anna Bridge	160:5571c4ff569f	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
Anna Bridge	160:5571c4ff569f	10	*
Anna Bridge	160:5571c4ff569f	11	* Redistribution and use in source and binary forms, with or without modification,
Anna Bridge	160:5571c4ff569f	12	* are permitted provided that the following conditions are met:
Anna Bridge	160:5571c4ff569f	13	* 1. Redistributions of source code must retain the above copyright notice,
Anna Bridge	160:5571c4ff569f	14	* this list of conditions and the following disclaimer.
Anna Bridge	160:5571c4ff569f	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
Anna Bridge	160:5571c4ff569f	16	* this list of conditions and the following disclaimer in the documentation
Anna Bridge	160:5571c4ff569f	17	* and/or other materials provided with the distribution.
Anna Bridge	160:5571c4ff569f	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Anna Bridge	160:5571c4ff569f	19	* may be used to endorse or promote products derived from this software
Anna Bridge	160:5571c4ff569f	20	* without specific prior written permission.
Anna Bridge	160:5571c4ff569f	21	*
Anna Bridge	160:5571c4ff569f	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Anna Bridge	160:5571c4ff569f	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Anna Bridge	160:5571c4ff569f	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Anna Bridge	160:5571c4ff569f	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Anna Bridge	160:5571c4ff569f	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Anna Bridge	160:5571c4ff569f	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Anna Bridge	160:5571c4ff569f	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Anna Bridge	160:5571c4ff569f	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Anna Bridge	160:5571c4ff569f	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Anna Bridge	160:5571c4ff569f	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Anna Bridge	160:5571c4ff569f	32	*
Anna Bridge	160:5571c4ff569f	33	******************************************************************************
Anna Bridge	160:5571c4ff569f	34	*/
Anna Bridge	160:5571c4ff569f	35
Anna Bridge	160:5571c4ff569f	36	/* Define to prevent recursive inclusion -------------------------------------*/
Anna Bridge	160:5571c4ff569f	37	#ifndef __STM32F4xx_LL_SDMMC_H
Anna Bridge	160:5571c4ff569f	38	#define __STM32F4xx_LL_SDMMC_H
Anna Bridge	160:5571c4ff569f	39
Anna Bridge	160:5571c4ff569f	40	#ifdef __cplusplus
Anna Bridge	160:5571c4ff569f	41	extern "C" {
Anna Bridge	160:5571c4ff569f	42	#endif
Anna Bridge	160:5571c4ff569f	43
Anna Bridge	160:5571c4ff569f	44	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| \
Anna Bridge	160:5571c4ff569f	45	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| \
Anna Bridge	160:5571c4ff569f	46	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE) \|\| defined(STM32F446xx) \|\| \
Anna Bridge	160:5571c4ff569f	47	defined(STM32F469xx) \|\| defined(STM32F479xx) \|\| defined(STM32F412Zx) \|\| defined(STM32F412Vx) \|\| \
Anna Bridge	160:5571c4ff569f	48	defined(STM32F412Rx) \|\| defined(STM32F412Cx) \|\| defined(STM32F413xx) \|\| defined(STM32F423xx)
Anna Bridge	160:5571c4ff569f	49
Anna Bridge	160:5571c4ff569f	50	/* Includes ------------------------------------------------------------------*/
Anna Bridge	160:5571c4ff569f	51	#include "stm32f4xx_hal_def.h"
Anna Bridge	160:5571c4ff569f	52
Anna Bridge	160:5571c4ff569f	53	/** @addtogroup STM32F4xx_Driver
Anna Bridge	160:5571c4ff569f	54	* @{
Anna Bridge	160:5571c4ff569f	55	*/
Anna Bridge	160:5571c4ff569f	56
Anna Bridge	160:5571c4ff569f	57	/** @addtogroup SDMMC_LL
Anna Bridge	160:5571c4ff569f	58	* @{
Anna Bridge	160:5571c4ff569f	59	*/
Anna Bridge	160:5571c4ff569f	60
Anna Bridge	160:5571c4ff569f	61	/* Exported types ------------------------------------------------------------*/
Anna Bridge	160:5571c4ff569f	62	/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
Anna Bridge	160:5571c4ff569f	63	* @{
Anna Bridge	160:5571c4ff569f	64	*/
Anna Bridge	160:5571c4ff569f	65
Anna Bridge	160:5571c4ff569f	66	/**
Anna Bridge	160:5571c4ff569f	67	* @brief SDMMC Configuration Structure definition
Anna Bridge	160:5571c4ff569f	68	*/
Anna Bridge	160:5571c4ff569f	69	typedef struct
Anna Bridge	160:5571c4ff569f	70	{
Anna Bridge	160:5571c4ff569f	71	uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
Anna Bridge	160:5571c4ff569f	72	This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
Anna Bridge	160:5571c4ff569f	73
Anna Bridge	160:5571c4ff569f	74	uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
Anna Bridge	160:5571c4ff569f	75	enabled or disabled.
Anna Bridge	160:5571c4ff569f	76	This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
Anna Bridge	160:5571c4ff569f	77
Anna Bridge	160:5571c4ff569f	78	uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
Anna Bridge	160:5571c4ff569f	79	disabled when the bus is idle.
Anna Bridge	160:5571c4ff569f	80	This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
Anna Bridge	160:5571c4ff569f	81
Anna Bridge	160:5571c4ff569f	82	uint32_t BusWide; /*!< Specifies the SDMMC bus width.
Anna Bridge	160:5571c4ff569f	83	This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
Anna Bridge	160:5571c4ff569f	84
Anna Bridge	160:5571c4ff569f	85	uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
Anna Bridge	160:5571c4ff569f	86	This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
Anna Bridge	160:5571c4ff569f	87
Anna Bridge	160:5571c4ff569f	88	uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
Anna Bridge	160:5571c4ff569f	89	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
Anna Bridge	160:5571c4ff569f	90
Anna Bridge	160:5571c4ff569f	91	}SDIO_InitTypeDef;
Anna Bridge	160:5571c4ff569f	92
Anna Bridge	160:5571c4ff569f	93
Anna Bridge	160:5571c4ff569f	94	/**
Anna Bridge	160:5571c4ff569f	95	* @brief SDMMC Command Control structure
Anna Bridge	160:5571c4ff569f	96	*/
Anna Bridge	160:5571c4ff569f	97	typedef struct
Anna Bridge	160:5571c4ff569f	98	{
Anna Bridge	160:5571c4ff569f	99	uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
Anna Bridge	160:5571c4ff569f	100	to a card as part of a command message. If a command
Anna Bridge	160:5571c4ff569f	101	contains an argument, it must be loaded into this register
Anna Bridge	160:5571c4ff569f	102	before writing the command to the command register. */
Anna Bridge	160:5571c4ff569f	103
Anna Bridge	160:5571c4ff569f	104	uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
Anna Bridge	160:5571c4ff569f	105	Max_Data = 64 */
Anna Bridge	160:5571c4ff569f	106
Anna Bridge	160:5571c4ff569f	107	uint32_t Response; /*!< Specifies the SDMMC response type.
Anna Bridge	160:5571c4ff569f	108	This parameter can be a value of @ref SDMMC_LL_Response_Type */
Anna Bridge	160:5571c4ff569f	109
Anna Bridge	160:5571c4ff569f	110	uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
Anna Bridge	160:5571c4ff569f	111	enabled or disabled.
Anna Bridge	160:5571c4ff569f	112	This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
Anna Bridge	160:5571c4ff569f	113
Anna Bridge	160:5571c4ff569f	114	uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
Anna Bridge	160:5571c4ff569f	115	is enabled or disabled.
Anna Bridge	160:5571c4ff569f	116	This parameter can be a value of @ref SDMMC_LL_CPSM_State */
Anna Bridge	160:5571c4ff569f	117	}SDIO_CmdInitTypeDef;
Anna Bridge	160:5571c4ff569f	118
Anna Bridge	160:5571c4ff569f	119
Anna Bridge	160:5571c4ff569f	120	/**
Anna Bridge	160:5571c4ff569f	121	* @brief SDMMC Data Control structure
Anna Bridge	160:5571c4ff569f	122	*/
Anna Bridge	160:5571c4ff569f	123	typedef struct
Anna Bridge	160:5571c4ff569f	124	{
Anna Bridge	160:5571c4ff569f	125	uint32_t DataTimeOut; /!< Specifies the data timeout period in card bus clock periods. /
Anna Bridge	160:5571c4ff569f	126
Anna Bridge	160:5571c4ff569f	127	uint32_t DataLength; /!< Specifies the number of data bytes to be transferred. /
Anna Bridge	160:5571c4ff569f	128
Anna Bridge	160:5571c4ff569f	129	uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
Anna Bridge	160:5571c4ff569f	130	This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
Anna Bridge	160:5571c4ff569f	131
Anna Bridge	160:5571c4ff569f	132	uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
Anna Bridge	160:5571c4ff569f	133	is a read or write.
Anna Bridge	160:5571c4ff569f	134	This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
Anna Bridge	160:5571c4ff569f	135
Anna Bridge	160:5571c4ff569f	136	uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
Anna Bridge	160:5571c4ff569f	137	This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
Anna Bridge	160:5571c4ff569f	138
Anna Bridge	160:5571c4ff569f	139	uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
Anna Bridge	160:5571c4ff569f	140	is enabled or disabled.
Anna Bridge	160:5571c4ff569f	141	This parameter can be a value of @ref SDMMC_LL_DPSM_State */
Anna Bridge	160:5571c4ff569f	142	}SDIO_DataInitTypeDef;
Anna Bridge	160:5571c4ff569f	143
Anna Bridge	160:5571c4ff569f	144	/**
Anna Bridge	160:5571c4ff569f	145	* @}
Anna Bridge	160:5571c4ff569f	146	*/
Anna Bridge	160:5571c4ff569f	147
Anna Bridge	160:5571c4ff569f	148	/* Exported constants --------------------------------------------------------*/
Anna Bridge	160:5571c4ff569f	149	/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
Anna Bridge	160:5571c4ff569f	150	* @{
Anna Bridge	160:5571c4ff569f	151	*/
Anna Bridge	160:5571c4ff569f	152	#define SDMMC_ERROR_NONE 0x00000000U /!< No error /
Anna Bridge	160:5571c4ff569f	153	#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /!< Command response received (but CRC check failed) /
Anna Bridge	160:5571c4ff569f	154	#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /!< Data block sent/received (CRC check failed) /
Anna Bridge	160:5571c4ff569f	155	#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /!< Command response timeout /
Anna Bridge	160:5571c4ff569f	156	#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /!< Data timeout /
Anna Bridge	160:5571c4ff569f	157	#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /!< Transmit FIFO underrun /
Anna Bridge	160:5571c4ff569f	158	#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /!< Receive FIFO overrun /
Anna Bridge	160:5571c4ff569f	159	#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /!< Misaligned address /
Anna Bridge	160:5571c4ff569f	160	#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the
Anna Bridge	160:5571c4ff569f	161	number of transferred bytes does not match the block length */
Anna Bridge	160:5571c4ff569f	162	#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /!< An error in the sequence of erase command occurs /
Anna Bridge	160:5571c4ff569f	163	#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /!< An invalid selection for erase groups /
Anna Bridge	160:5571c4ff569f	164	#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /!< Attempt to program a write protect block /
Anna Bridge	160:5571c4ff569f	165	#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock
Anna Bridge	160:5571c4ff569f	166	command or if there was an attempt to access a locked card */
Anna Bridge	160:5571c4ff569f	167	#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /!< CRC check of the previous command failed /
Anna Bridge	160:5571c4ff569f	168	#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /!< Command is not legal for the card state /
Anna Bridge	160:5571c4ff569f	169	#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /!< Card internal ECC was applied but failed to correct the data /
Anna Bridge	160:5571c4ff569f	170	#define SDMMC_ERROR_CC_ERR 0x00008000U /!< Internal card controller error /
Anna Bridge	160:5571c4ff569f	171	#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /!< General or unknown error /
Anna Bridge	160:5571c4ff569f	172	#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /!< The card could not sustain data reading in stream rmode /
Anna Bridge	160:5571c4ff569f	173	#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /!< The card could not sustain data programming in stream mode /
Anna Bridge	160:5571c4ff569f	174	#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /!< CID/CSD overwrite error /
Anna Bridge	160:5571c4ff569f	175	#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /!< Only partial address space was erased /
Anna Bridge	160:5571c4ff569f	176	#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /!< Command has been executed without using internal ECC /
Anna Bridge	160:5571c4ff569f	177	#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out
Anna Bridge	160:5571c4ff569f	178	of erase sequence command was received */
Anna Bridge	160:5571c4ff569f	179	#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /!< Error in sequence of authentication /
Anna Bridge	160:5571c4ff569f	180	#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /!< Error in case of invalid voltage range /
Anna Bridge	160:5571c4ff569f	181	#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /!< Error when addressed block is out of range /
Anna Bridge	160:5571c4ff569f	182	#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /!< Error when command request is not applicable /
Anna Bridge	160:5571c4ff569f	183	#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /!< the used parameter is not valid /
Anna Bridge	160:5571c4ff569f	184	#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /!< Error when feature is not insupported /
Anna Bridge	160:5571c4ff569f	185	#define SDMMC_ERROR_BUSY 0x20000000U /!< Error when transfer process is busy /
Anna Bridge	160:5571c4ff569f	186	#define SDMMC_ERROR_DMA 0x40000000U /!< Error while DMA transfer /
Anna Bridge	160:5571c4ff569f	187	#define SDMMC_ERROR_TIMEOUT 0x80000000U /!< Timeout error /
Anna Bridge	160:5571c4ff569f	188
Anna Bridge	160:5571c4ff569f	189	/**
Anna Bridge	160:5571c4ff569f	190	* @brief SDMMC Commands Index
Anna Bridge	160:5571c4ff569f	191	*/
Anna Bridge	160:5571c4ff569f	192	#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /!< Resets the SD memory card. /
Anna Bridge	160:5571c4ff569f	193	#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /!< Sends host capacity support information and activates the card's initialization process. /
Anna Bridge	160:5571c4ff569f	194	#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /!< Asks any card connected to the host to send the CID numbers on the CMD line. /
Anna Bridge	160:5571c4ff569f	195	#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /!< Asks the card to publish a new relative address (RCA). /
Anna Bridge	160:5571c4ff569f	196	#define SDMMC_CMD_SET_DSR ((uint8_t)4) /!< Programs the DSR of all cards. /
Anna Bridge	160:5571c4ff569f	197	#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
Anna Bridge	160:5571c4ff569f	198	operating condition register (OCR) content in the response on the CMD line. */
Anna Bridge	160:5571c4ff569f	199	#define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /!< Checks switchable function (mode 0) and switch card function (mode 1). /
Anna Bridge	160:5571c4ff569f	200	#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /!< Selects the card by its own relative address and gets deselected by any other address /
Anna Bridge	160:5571c4ff569f	201	#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
Anna Bridge	160:5571c4ff569f	202	and asks the card whether card supports voltage. */
Anna Bridge	160:5571c4ff569f	203	#define SDMMC_CMD_SEND_CSD ((uint8_t)9) /!< Addressed card sends its card specific data (CSD) on the CMD line. /
Anna Bridge	160:5571c4ff569f	204	#define SDMMC_CMD_SEND_CID ((uint8_t)10) /!< Addressed card sends its card identification (CID) on the CMD line. /
Anna Bridge	160:5571c4ff569f	205	#define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /!< SD card doesn't support it. /
Anna Bridge	160:5571c4ff569f	206	#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /!< Forces the card to stop transmission. /
Anna Bridge	160:5571c4ff569f	207	#define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /!< Addressed card sends its status register. /
Anna Bridge	160:5571c4ff569f	208	#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /!< Reserved /
Anna Bridge	160:5571c4ff569f	209	#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /!< Sends an addressed card into the inactive state. /
Anna Bridge	160:5571c4ff569f	210	#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands
Anna Bridge	160:5571c4ff569f	211	(read, write, lock). Default block length is fixed to 512 Bytes. Not effective
Anna Bridge	160:5571c4ff569f	212	for SDHS and SDXC. */
Anna Bridge	160:5571c4ff569f	213	#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
Anna Bridge	160:5571c4ff569f	214	fixed 512 bytes in case of SDHC and SDXC. */
Anna Bridge	160:5571c4ff569f	215	#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by
Anna Bridge	160:5571c4ff569f	216	STOP_TRANSMISSION command. */
Anna Bridge	160:5571c4ff569f	217	#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /!< 64 bytes tuning pattern is sent for SDR50 and SDR104. /
Anna Bridge	160:5571c4ff569f	218	#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /!< Speed class control command. /
Anna Bridge	160:5571c4ff569f	219	#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /!< Specify block count for CMD18 and CMD25. /
Anna Bridge	160:5571c4ff569f	220	#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
Anna Bridge	160:5571c4ff569f	221	fixed 512 bytes in case of SDHC and SDXC. */
Anna Bridge	160:5571c4ff569f	222	#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. /
Anna Bridge	160:5571c4ff569f	223	#define SDMMC_CMD_PROG_CID ((uint8_t)26) /!< Reserved for manufacturers. /
Anna Bridge	160:5571c4ff569f	224	#define SDMMC_CMD_PROG_CSD ((uint8_t)27) /!< Programming of the programmable bits of the CSD. /
Anna Bridge	160:5571c4ff569f	225	#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /!< Sets the write protection bit of the addressed group. /
Anna Bridge	160:5571c4ff569f	226	#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /!< Clears the write protection bit of the addressed group. /
Anna Bridge	160:5571c4ff569f	227	#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /!< Asks the card to send the status of the write protection bits. /
Anna Bridge	160:5571c4ff569f	228	#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /!< Sets the address of the first write block to be erased. (For SD card only). /
Anna Bridge	160:5571c4ff569f	229	#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /!< Sets the address of the last write block of the continuous range to be erased. /
Anna Bridge	160:5571c4ff569f	230	#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command
Anna Bridge	160:5571c4ff569f	231	system set by switch function command (CMD6). */
Anna Bridge	160:5571c4ff569f	232	#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased.
Anna Bridge	160:5571c4ff569f	233	Reserved for each command system set by switch function command (CMD6). */
Anna Bridge	160:5571c4ff569f	234	#define SDMMC_CMD_ERASE ((uint8_t)38) /!< Reserved for SD security applications. /
Anna Bridge	160:5571c4ff569f	235	#define SDMMC_CMD_FAST_IO ((uint8_t)39) /!< SD card doesn't support it (Reserved). /
Anna Bridge	160:5571c4ff569f	236	#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /!< SD card doesn't support it (Reserved). /
Anna Bridge	160:5571c4ff569f	237	#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
Anna Bridge	160:5571c4ff569f	238	the SET_BLOCK_LEN command. */
Anna Bridge	160:5571c4ff569f	239	#define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather
Anna Bridge	160:5571c4ff569f	240	than a standard command. */
Anna Bridge	160:5571c4ff569f	241	#define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card
Anna Bridge	160:5571c4ff569f	242	for general purpose/application specific commands. */
Anna Bridge	160:5571c4ff569f	243	#define SDMMC_CMD_NO_CMD ((uint8_t)64) /!< No command /
Anna Bridge	160:5571c4ff569f	244
Anna Bridge	160:5571c4ff569f	245	/**
Anna Bridge	160:5571c4ff569f	246	* @brief Following commands are SD Card Specific commands.
Anna Bridge	160:5571c4ff569f	247	* SDMMC_APP_CMD should be sent before sending these commands.
Anna Bridge	160:5571c4ff569f	248	*/
Anna Bridge	160:5571c4ff569f	249	#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
Anna Bridge	160:5571c4ff569f	250	widths are given in SCR register. */
Anna Bridge	160:5571c4ff569f	251	#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /!< (ACMD13) Sends the SD status. /
Anna Bridge	160:5571c4ff569f	252	#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
Anna Bridge	160:5571c4ff569f	253	32bit+CRC data block. */
Anna Bridge	160:5571c4ff569f	254	#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
Anna Bridge	160:5571c4ff569f	255	send its operating condition register (OCR) content in the response on the CMD line. */
Anna Bridge	160:5571c4ff569f	256	#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card /
Anna Bridge	160:5571c4ff569f	257	#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /!< Reads the SD Configuration Register (SCR). /
Anna Bridge	160:5571c4ff569f	258	#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /!< For SD I/O card only, reserved for security specification. /
Anna Bridge	160:5571c4ff569f	259	#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /!< For SD I/O card only, reserved for security specification. /
Anna Bridge	160:5571c4ff569f	260
Anna Bridge	160:5571c4ff569f	261	/**
Anna Bridge	160:5571c4ff569f	262	* @brief Following commands are SD Card Specific security commands.
Anna Bridge	160:5571c4ff569f	263	* SDMMC_CMD_APP_CMD should be sent before sending these commands.
Anna Bridge	160:5571c4ff569f	264	*/
Anna Bridge	160:5571c4ff569f	265	#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43)
Anna Bridge	160:5571c4ff569f	266	#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44)
Anna Bridge	160:5571c4ff569f	267	#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45)
Anna Bridge	160:5571c4ff569f	268	#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46)
Anna Bridge	160:5571c4ff569f	269	#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47)
Anna Bridge	160:5571c4ff569f	270	#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48)
Anna Bridge	160:5571c4ff569f	271	#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18)
Anna Bridge	160:5571c4ff569f	272	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25)
Anna Bridge	160:5571c4ff569f	273	#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38)
Anna Bridge	160:5571c4ff569f	274	#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49)
Anna Bridge	160:5571c4ff569f	275	#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48)
Anna Bridge	160:5571c4ff569f	276
Anna Bridge	160:5571c4ff569f	277	/**
Anna Bridge	160:5571c4ff569f	278	* @brief Masks for errors Card Status R1 (OCR Register)
Anna Bridge	160:5571c4ff569f	279	*/
Anna Bridge	160:5571c4ff569f	280	#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U
Anna Bridge	160:5571c4ff569f	281	#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U
Anna Bridge	160:5571c4ff569f	282	#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U
Anna Bridge	160:5571c4ff569f	283	#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U
Anna Bridge	160:5571c4ff569f	284	#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U
Anna Bridge	160:5571c4ff569f	285	#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U
Anna Bridge	160:5571c4ff569f	286	#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U
Anna Bridge	160:5571c4ff569f	287	#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U
Anna Bridge	160:5571c4ff569f	288	#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U
Anna Bridge	160:5571c4ff569f	289	#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U
Anna Bridge	160:5571c4ff569f	290	#define SDMMC_OCR_CC_ERROR 0x00100000U
Anna Bridge	160:5571c4ff569f	291	#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U
Anna Bridge	160:5571c4ff569f	292	#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U
Anna Bridge	160:5571c4ff569f	293	#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U
Anna Bridge	160:5571c4ff569f	294	#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U
Anna Bridge	160:5571c4ff569f	295	#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U
Anna Bridge	160:5571c4ff569f	296	#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U
Anna Bridge	160:5571c4ff569f	297	#define SDMMC_OCR_ERASE_RESET 0x00002000U
Anna Bridge	160:5571c4ff569f	298	#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U
Anna Bridge	160:5571c4ff569f	299	#define SDMMC_OCR_ERRORBITS 0xFDFFE008U
Anna Bridge	160:5571c4ff569f	300
Anna Bridge	160:5571c4ff569f	301	/**
Anna Bridge	160:5571c4ff569f	302	* @brief Masks for R6 Response
Anna Bridge	160:5571c4ff569f	303	*/
Anna Bridge	160:5571c4ff569f	304	#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U
Anna Bridge	160:5571c4ff569f	305	#define SDMMC_R6_ILLEGAL_CMD 0x00004000U
Anna Bridge	160:5571c4ff569f	306	#define SDMMC_R6_COM_CRC_FAILED 0x00008000U
Anna Bridge	160:5571c4ff569f	307
Anna Bridge	160:5571c4ff569f	308	#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U
Anna Bridge	160:5571c4ff569f	309	#define SDMMC_HIGH_CAPACITY 0x40000000U
Anna Bridge	160:5571c4ff569f	310	#define SDMMC_STD_CAPACITY 0x00000000U
Anna Bridge	160:5571c4ff569f	311	#define SDMMC_CHECK_PATTERN 0x000001AAU
Anna Bridge	160:5571c4ff569f	312
Anna Bridge	160:5571c4ff569f	313	#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU
Anna Bridge	160:5571c4ff569f	314
Anna Bridge	160:5571c4ff569f	315	#define SDMMC_MAX_TRIAL 0x0000FFFFU
Anna Bridge	160:5571c4ff569f	316
Anna Bridge	160:5571c4ff569f	317	#define SDMMC_ALLZERO 0x00000000U
Anna Bridge	160:5571c4ff569f	318
Anna Bridge	160:5571c4ff569f	319	#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U
Anna Bridge	160:5571c4ff569f	320	#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U
Anna Bridge	160:5571c4ff569f	321	#define SDMMC_CARD_LOCKED 0x02000000U
Anna Bridge	160:5571c4ff569f	322
Anna Bridge	160:5571c4ff569f	323	#define SDMMC_DATATIMEOUT 0xFFFFFFFFU
Anna Bridge	160:5571c4ff569f	324
Anna Bridge	160:5571c4ff569f	325	#define SDMMC_0TO7BITS 0x000000FFU
Anna Bridge	160:5571c4ff569f	326	#define SDMMC_8TO15BITS 0x0000FF00U
Anna Bridge	160:5571c4ff569f	327	#define SDMMC_16TO23BITS 0x00FF0000U
Anna Bridge	160:5571c4ff569f	328	#define SDMMC_24TO31BITS 0xFF000000U
Anna Bridge	160:5571c4ff569f	329	#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU
Anna Bridge	160:5571c4ff569f	330
Anna Bridge	160:5571c4ff569f	331	#define SDMMC_HALFFIFO 0x00000008U
Anna Bridge	160:5571c4ff569f	332	#define SDMMC_HALFFIFOBYTES 0x00000020U
Anna Bridge	160:5571c4ff569f	333
Anna Bridge	160:5571c4ff569f	334	/**
Anna Bridge	160:5571c4ff569f	335	* @brief Command Class supported
Anna Bridge	160:5571c4ff569f	336	*/
Anna Bridge	160:5571c4ff569f	337	#define SDIO_CCCC_ERASE 0x00000020U
Anna Bridge	160:5571c4ff569f	338
Anna Bridge	160:5571c4ff569f	339	#define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */
Anna Bridge	160:5571c4ff569f	340	#define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */
Anna Bridge	160:5571c4ff569f	341
Anna Bridge	160:5571c4ff569f	342
Anna Bridge	160:5571c4ff569f	343	/** @defgroup SDIO_LL_Clock_Edge Clock Edge
Anna Bridge	160:5571c4ff569f	344	* @{
Anna Bridge	160:5571c4ff569f	345	*/
Anna Bridge	160:5571c4ff569f	346	#define SDIO_CLOCK_EDGE_RISING 0x00000000U
Anna Bridge	160:5571c4ff569f	347	#define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
Anna Bridge	160:5571c4ff569f	348
Anna Bridge	160:5571c4ff569f	349	#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) \|\| \
Anna Bridge	160:5571c4ff569f	350	((EDGE) == SDIO_CLOCK_EDGE_FALLING))
Anna Bridge	160:5571c4ff569f	351	/**
Anna Bridge	160:5571c4ff569f	352	* @}
Anna Bridge	160:5571c4ff569f	353	*/
Anna Bridge	160:5571c4ff569f	354
Anna Bridge	160:5571c4ff569f	355	/** @defgroup SDIO_LL_Clock_Bypass Clock Bypass
Anna Bridge	160:5571c4ff569f	356	* @{
Anna Bridge	160:5571c4ff569f	357	*/
Anna Bridge	160:5571c4ff569f	358	#define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U
Anna Bridge	160:5571c4ff569f	359	#define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
Anna Bridge	160:5571c4ff569f	360
Anna Bridge	160:5571c4ff569f	361	#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) \|\| \
Anna Bridge	160:5571c4ff569f	362	((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
Anna Bridge	160:5571c4ff569f	363	/**
Anna Bridge	160:5571c4ff569f	364	* @}
Anna Bridge	160:5571c4ff569f	365	*/
Anna Bridge	160:5571c4ff569f	366
Anna Bridge	160:5571c4ff569f	367	/** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving
Anna Bridge	160:5571c4ff569f	368	* @{
Anna Bridge	160:5571c4ff569f	369	*/
Anna Bridge	160:5571c4ff569f	370	#define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U
Anna Bridge	160:5571c4ff569f	371	#define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
Anna Bridge	160:5571c4ff569f	372
Anna Bridge	160:5571c4ff569f	373	#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) \|\| \
Anna Bridge	160:5571c4ff569f	374	((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
Anna Bridge	160:5571c4ff569f	375	/**
Anna Bridge	160:5571c4ff569f	376	* @}
Anna Bridge	160:5571c4ff569f	377	*/
Anna Bridge	160:5571c4ff569f	378
Anna Bridge	160:5571c4ff569f	379	/** @defgroup SDIO_LL_Bus_Wide Bus Width
Anna Bridge	160:5571c4ff569f	380	* @{
Anna Bridge	160:5571c4ff569f	381	*/
Anna Bridge	160:5571c4ff569f	382	#define SDIO_BUS_WIDE_1B 0x00000000U
Anna Bridge	160:5571c4ff569f	383	#define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
Anna Bridge	160:5571c4ff569f	384	#define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
Anna Bridge	160:5571c4ff569f	385
Anna Bridge	160:5571c4ff569f	386	#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) \|\| \
Anna Bridge	160:5571c4ff569f	387	((WIDE) == SDIO_BUS_WIDE_4B) \|\| \
Anna Bridge	160:5571c4ff569f	388	((WIDE) == SDIO_BUS_WIDE_8B))
Anna Bridge	160:5571c4ff569f	389	/**
Anna Bridge	160:5571c4ff569f	390	* @}
Anna Bridge	160:5571c4ff569f	391	*/
Anna Bridge	160:5571c4ff569f	392
Anna Bridge	160:5571c4ff569f	393	/** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control
Anna Bridge	160:5571c4ff569f	394	* @{
Anna Bridge	160:5571c4ff569f	395	*/
Anna Bridge	160:5571c4ff569f	396	#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U
Anna Bridge	160:5571c4ff569f	397	#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
Anna Bridge	160:5571c4ff569f	398
Anna Bridge	160:5571c4ff569f	399	#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) \|\| \
Anna Bridge	160:5571c4ff569f	400	((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
Anna Bridge	160:5571c4ff569f	401	/**
Anna Bridge	160:5571c4ff569f	402	* @}
Anna Bridge	160:5571c4ff569f	403	*/
Anna Bridge	160:5571c4ff569f	404
Anna Bridge	160:5571c4ff569f	405	/** @defgroup SDIO_LL_Clock_Division Clock Division
Anna Bridge	160:5571c4ff569f	406	* @{
Anna Bridge	160:5571c4ff569f	407	*/
Anna Bridge	160:5571c4ff569f	408	#define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFFU)
Anna Bridge	160:5571c4ff569f	409	/**
Anna Bridge	160:5571c4ff569f	410	* @}
Anna Bridge	160:5571c4ff569f	411	*/
Anna Bridge	160:5571c4ff569f	412
Anna Bridge	160:5571c4ff569f	413	/** @defgroup SDIO_LL_Command_Index Command Index
Anna Bridge	160:5571c4ff569f	414	* @{
Anna Bridge	160:5571c4ff569f	415	*/
Anna Bridge	160:5571c4ff569f	416	#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U)
Anna Bridge	160:5571c4ff569f	417	/**
Anna Bridge	160:5571c4ff569f	418	* @}
Anna Bridge	160:5571c4ff569f	419	*/
Anna Bridge	160:5571c4ff569f	420
Anna Bridge	160:5571c4ff569f	421	/** @defgroup SDIO_LL_Response_Type Response Type
Anna Bridge	160:5571c4ff569f	422	* @{
Anna Bridge	160:5571c4ff569f	423	*/
Anna Bridge	160:5571c4ff569f	424	#define SDIO_RESPONSE_NO 0x00000000U
Anna Bridge	160:5571c4ff569f	425	#define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
Anna Bridge	160:5571c4ff569f	426	#define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
Anna Bridge	160:5571c4ff569f	427
Anna Bridge	160:5571c4ff569f	428	#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) \|\| \
Anna Bridge	160:5571c4ff569f	429	((RESPONSE) == SDIO_RESPONSE_SHORT) \|\| \
Anna Bridge	160:5571c4ff569f	430	((RESPONSE) == SDIO_RESPONSE_LONG))
Anna Bridge	160:5571c4ff569f	431	/**
Anna Bridge	160:5571c4ff569f	432	* @}
Anna Bridge	160:5571c4ff569f	433	*/
Anna Bridge	160:5571c4ff569f	434
Anna Bridge	160:5571c4ff569f	435	/** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt
Anna Bridge	160:5571c4ff569f	436	* @{
Anna Bridge	160:5571c4ff569f	437	*/
Anna Bridge	160:5571c4ff569f	438	#define SDIO_WAIT_NO 0x00000000U
Anna Bridge	160:5571c4ff569f	439	#define SDIO_WAIT_IT SDIO_CMD_WAITINT
Anna Bridge	160:5571c4ff569f	440	#define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
Anna Bridge	160:5571c4ff569f	441
Anna Bridge	160:5571c4ff569f	442	#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) \|\| \
Anna Bridge	160:5571c4ff569f	443	((WAIT) == SDIO_WAIT_IT) \|\| \
Anna Bridge	160:5571c4ff569f	444	((WAIT) == SDIO_WAIT_PEND))
Anna Bridge	160:5571c4ff569f	445	/**
Anna Bridge	160:5571c4ff569f	446	* @}
Anna Bridge	160:5571c4ff569f	447	*/
Anna Bridge	160:5571c4ff569f	448
Anna Bridge	160:5571c4ff569f	449	/** @defgroup SDIO_LL_CPSM_State CPSM State
Anna Bridge	160:5571c4ff569f	450	* @{
Anna Bridge	160:5571c4ff569f	451	*/
Anna Bridge	160:5571c4ff569f	452	#define SDIO_CPSM_DISABLE 0x00000000U
Anna Bridge	160:5571c4ff569f	453	#define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
Anna Bridge	160:5571c4ff569f	454
Anna Bridge	160:5571c4ff569f	455	#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) \|\| \
Anna Bridge	160:5571c4ff569f	456	((CPSM) == SDIO_CPSM_ENABLE))
Anna Bridge	160:5571c4ff569f	457	/**
Anna Bridge	160:5571c4ff569f	458	* @}
Anna Bridge	160:5571c4ff569f	459	*/
Anna Bridge	160:5571c4ff569f	460
Anna Bridge	160:5571c4ff569f	461	/** @defgroup SDIO_LL_Response_Registers Response Register
Anna Bridge	160:5571c4ff569f	462	* @{
Anna Bridge	160:5571c4ff569f	463	*/
Anna Bridge	160:5571c4ff569f	464	#define SDIO_RESP1 0x00000000U
Anna Bridge	160:5571c4ff569f	465	#define SDIO_RESP2 0x00000004U
Anna Bridge	160:5571c4ff569f	466	#define SDIO_RESP3 0x00000008U
Anna Bridge	160:5571c4ff569f	467	#define SDIO_RESP4 0x0000000CU
Anna Bridge	160:5571c4ff569f	468
Anna Bridge	160:5571c4ff569f	469	#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) \|\| \
Anna Bridge	160:5571c4ff569f	470	((RESP) == SDIO_RESP2) \|\| \
Anna Bridge	160:5571c4ff569f	471	((RESP) == SDIO_RESP3) \|\| \
Anna Bridge	160:5571c4ff569f	472	((RESP) == SDIO_RESP4))
Anna Bridge	160:5571c4ff569f	473	/**
Anna Bridge	160:5571c4ff569f	474	* @}
Anna Bridge	160:5571c4ff569f	475	*/
Anna Bridge	160:5571c4ff569f	476
Anna Bridge	160:5571c4ff569f	477	/** @defgroup SDIO_LL_Data_Length Data Lenght
Anna Bridge	160:5571c4ff569f	478	* @{
Anna Bridge	160:5571c4ff569f	479	*/
Anna Bridge	160:5571c4ff569f	480	#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)
Anna Bridge	160:5571c4ff569f	481	/**
Anna Bridge	160:5571c4ff569f	482	* @}
Anna Bridge	160:5571c4ff569f	483	*/
Anna Bridge	160:5571c4ff569f	484
Anna Bridge	160:5571c4ff569f	485	/** @defgroup SDIO_LL_Data_Block_Size Data Block Size
Anna Bridge	160:5571c4ff569f	486	* @{
Anna Bridge	160:5571c4ff569f	487	*/
Anna Bridge	160:5571c4ff569f	488	#define SDIO_DATABLOCK_SIZE_1B 0x00000000U
Anna Bridge	160:5571c4ff569f	489	#define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
Anna Bridge	160:5571c4ff569f	490	#define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
Anna Bridge	160:5571c4ff569f	491	#define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1)
Anna Bridge	160:5571c4ff569f	492	#define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
Anna Bridge	160:5571c4ff569f	493	#define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2)
Anna Bridge	160:5571c4ff569f	494	#define SDIO_DATABLOCK_SIZE_64B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
Anna Bridge	160:5571c4ff569f	495	#define SDIO_DATABLOCK_SIZE_128B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2)
Anna Bridge	160:5571c4ff569f	496	#define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
Anna Bridge	160:5571c4ff569f	497	#define SDIO_DATABLOCK_SIZE_512B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_3)
Anna Bridge	160:5571c4ff569f	498	#define SDIO_DATABLOCK_SIZE_1024B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
Anna Bridge	160:5571c4ff569f	499	#define SDIO_DATABLOCK_SIZE_2048B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_3)
Anna Bridge	160:5571c4ff569f	500	#define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
Anna Bridge	160:5571c4ff569f	501	#define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
Anna Bridge	160:5571c4ff569f	502	#define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1\|SDIO_DCTRL_DBLOCKSIZE_2\|SDIO_DCTRL_DBLOCKSIZE_3)
Anna Bridge	160:5571c4ff569f	503
Anna Bridge	160:5571c4ff569f	504	#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) \|\| \
Anna Bridge	160:5571c4ff569f	505	((SIZE) == SDIO_DATABLOCK_SIZE_2B) \|\| \
Anna Bridge	160:5571c4ff569f	506	((SIZE) == SDIO_DATABLOCK_SIZE_4B) \|\| \
Anna Bridge	160:5571c4ff569f	507	((SIZE) == SDIO_DATABLOCK_SIZE_8B) \|\| \
Anna Bridge	160:5571c4ff569f	508	((SIZE) == SDIO_DATABLOCK_SIZE_16B) \|\| \
Anna Bridge	160:5571c4ff569f	509	((SIZE) == SDIO_DATABLOCK_SIZE_32B) \|\| \
Anna Bridge	160:5571c4ff569f	510	((SIZE) == SDIO_DATABLOCK_SIZE_64B) \|\| \
Anna Bridge	160:5571c4ff569f	511	((SIZE) == SDIO_DATABLOCK_SIZE_128B) \|\| \
Anna Bridge	160:5571c4ff569f	512	((SIZE) == SDIO_DATABLOCK_SIZE_256B) \|\| \
Anna Bridge	160:5571c4ff569f	513	((SIZE) == SDIO_DATABLOCK_SIZE_512B) \|\| \
Anna Bridge	160:5571c4ff569f	514	((SIZE) == SDIO_DATABLOCK_SIZE_1024B) \|\| \
Anna Bridge	160:5571c4ff569f	515	((SIZE) == SDIO_DATABLOCK_SIZE_2048B) \|\| \
Anna Bridge	160:5571c4ff569f	516	((SIZE) == SDIO_DATABLOCK_SIZE_4096B) \|\| \
Anna Bridge	160:5571c4ff569f	517	((SIZE) == SDIO_DATABLOCK_SIZE_8192B) \|\| \
Anna Bridge	160:5571c4ff569f	518	((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
Anna Bridge	160:5571c4ff569f	519	/**
Anna Bridge	160:5571c4ff569f	520	* @}
Anna Bridge	160:5571c4ff569f	521	*/
Anna Bridge	160:5571c4ff569f	522
Anna Bridge	160:5571c4ff569f	523	/** @defgroup SDIO_LL_Transfer_Direction Transfer Direction
Anna Bridge	160:5571c4ff569f	524	* @{
Anna Bridge	160:5571c4ff569f	525	*/
Anna Bridge	160:5571c4ff569f	526	#define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U
Anna Bridge	160:5571c4ff569f	527	#define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
Anna Bridge	160:5571c4ff569f	528
Anna Bridge	160:5571c4ff569f	529	#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) \|\| \
Anna Bridge	160:5571c4ff569f	530	((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
Anna Bridge	160:5571c4ff569f	531	/**
Anna Bridge	160:5571c4ff569f	532	* @}
Anna Bridge	160:5571c4ff569f	533	*/
Anna Bridge	160:5571c4ff569f	534
Anna Bridge	160:5571c4ff569f	535	/** @defgroup SDIO_LL_Transfer_Type Transfer Type
Anna Bridge	160:5571c4ff569f	536	* @{
Anna Bridge	160:5571c4ff569f	537	*/
Anna Bridge	160:5571c4ff569f	538	#define SDIO_TRANSFER_MODE_BLOCK 0x00000000U
Anna Bridge	160:5571c4ff569f	539	#define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
Anna Bridge	160:5571c4ff569f	540
Anna Bridge	160:5571c4ff569f	541	#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) \|\| \
Anna Bridge	160:5571c4ff569f	542	((MODE) == SDIO_TRANSFER_MODE_STREAM))
Anna Bridge	160:5571c4ff569f	543	/**
Anna Bridge	160:5571c4ff569f	544	* @}
Anna Bridge	160:5571c4ff569f	545	*/
Anna Bridge	160:5571c4ff569f	546
Anna Bridge	160:5571c4ff569f	547	/** @defgroup SDIO_LL_DPSM_State DPSM State
Anna Bridge	160:5571c4ff569f	548	* @{
Anna Bridge	160:5571c4ff569f	549	*/
Anna Bridge	160:5571c4ff569f	550	#define SDIO_DPSM_DISABLE 0x00000000U
Anna Bridge	160:5571c4ff569f	551	#define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
Anna Bridge	160:5571c4ff569f	552
Anna Bridge	160:5571c4ff569f	553	#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) \|\|\
Anna Bridge	160:5571c4ff569f	554	((DPSM) == SDIO_DPSM_ENABLE))
Anna Bridge	160:5571c4ff569f	555	/**
Anna Bridge	160:5571c4ff569f	556	* @}
Anna Bridge	160:5571c4ff569f	557	*/
Anna Bridge	160:5571c4ff569f	558
Anna Bridge	160:5571c4ff569f	559	/** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode
Anna Bridge	160:5571c4ff569f	560	* @{
Anna Bridge	160:5571c4ff569f	561	*/
Anna Bridge	160:5571c4ff569f	562	#define SDIO_READ_WAIT_MODE_DATA2 0x00000000U
Anna Bridge	160:5571c4ff569f	563	#define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD)
Anna Bridge	160:5571c4ff569f	564
Anna Bridge	160:5571c4ff569f	565	#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) \|\| \
Anna Bridge	160:5571c4ff569f	566	((MODE) == SDIO_READ_WAIT_MODE_DATA2))
Anna Bridge	160:5571c4ff569f	567	/**
Anna Bridge	160:5571c4ff569f	568	* @}
Anna Bridge	160:5571c4ff569f	569	*/
Anna Bridge	160:5571c4ff569f	570
Anna Bridge	160:5571c4ff569f	571	/** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources
Anna Bridge	160:5571c4ff569f	572	* @{
Anna Bridge	160:5571c4ff569f	573	*/
Anna Bridge	160:5571c4ff569f	574	#define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
Anna Bridge	160:5571c4ff569f	575	#define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
Anna Bridge	160:5571c4ff569f	576	#define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
Anna Bridge	160:5571c4ff569f	577	#define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
Anna Bridge	160:5571c4ff569f	578	#define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
Anna Bridge	160:5571c4ff569f	579	#define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
Anna Bridge	160:5571c4ff569f	580	#define SDIO_IT_CMDREND SDIO_STA_CMDREND
Anna Bridge	160:5571c4ff569f	581	#define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
Anna Bridge	160:5571c4ff569f	582	#define SDIO_IT_DATAEND SDIO_STA_DATAEND
Anna Bridge	160:5571c4ff569f	583	#define SDIO_IT_STBITERR SDIO_STA_STBITERR
Anna Bridge	160:5571c4ff569f	584	#define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
Anna Bridge	160:5571c4ff569f	585	#define SDIO_IT_CMDACT SDIO_STA_CMDACT
Anna Bridge	160:5571c4ff569f	586	#define SDIO_IT_TXACT SDIO_STA_TXACT
Anna Bridge	160:5571c4ff569f	587	#define SDIO_IT_RXACT SDIO_STA_RXACT
Anna Bridge	160:5571c4ff569f	588	#define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
Anna Bridge	160:5571c4ff569f	589	#define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
Anna Bridge	160:5571c4ff569f	590	#define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
Anna Bridge	160:5571c4ff569f	591	#define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
Anna Bridge	160:5571c4ff569f	592	#define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
Anna Bridge	160:5571c4ff569f	593	#define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
Anna Bridge	160:5571c4ff569f	594	#define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
Anna Bridge	160:5571c4ff569f	595	#define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
Anna Bridge	160:5571c4ff569f	596	#define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
Anna Bridge	160:5571c4ff569f	597	#define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
Anna Bridge	160:5571c4ff569f	598	/**
Anna Bridge	160:5571c4ff569f	599	* @}
Anna Bridge	160:5571c4ff569f	600	*/
Anna Bridge	160:5571c4ff569f	601
Anna Bridge	160:5571c4ff569f	602	/** @defgroup SDIO_LL_Flags Flags
Anna Bridge	160:5571c4ff569f	603	* @{
Anna Bridge	160:5571c4ff569f	604	*/
Anna Bridge	160:5571c4ff569f	605	#define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
Anna Bridge	160:5571c4ff569f	606	#define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
Anna Bridge	160:5571c4ff569f	607	#define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
Anna Bridge	160:5571c4ff569f	608	#define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
Anna Bridge	160:5571c4ff569f	609	#define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
Anna Bridge	160:5571c4ff569f	610	#define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
Anna Bridge	160:5571c4ff569f	611	#define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
Anna Bridge	160:5571c4ff569f	612	#define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
Anna Bridge	160:5571c4ff569f	613	#define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
Anna Bridge	160:5571c4ff569f	614	#define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
Anna Bridge	160:5571c4ff569f	615	#define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
Anna Bridge	160:5571c4ff569f	616	#define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
Anna Bridge	160:5571c4ff569f	617	#define SDIO_FLAG_TXACT SDIO_STA_TXACT
Anna Bridge	160:5571c4ff569f	618	#define SDIO_FLAG_RXACT SDIO_STA_RXACT
Anna Bridge	160:5571c4ff569f	619	#define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
Anna Bridge	160:5571c4ff569f	620	#define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
Anna Bridge	160:5571c4ff569f	621	#define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
Anna Bridge	160:5571c4ff569f	622	#define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
Anna Bridge	160:5571c4ff569f	623	#define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
Anna Bridge	160:5571c4ff569f	624	#define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
Anna Bridge	160:5571c4ff569f	625	#define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
Anna Bridge	160:5571c4ff569f	626	#define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
Anna Bridge	160:5571c4ff569f	627	#define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
Anna Bridge	160:5571c4ff569f	628	#define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
Anna Bridge	160:5571c4ff569f	629	#define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL \| SDIO_FLAG_DCRCFAIL \| SDIO_FLAG_CTIMEOUT \|\
Anna Bridge	160:5571c4ff569f	630	SDIO_FLAG_DTIMEOUT \| SDIO_FLAG_TXUNDERR \| SDIO_FLAG_RXOVERR \|\
Anna Bridge	160:5571c4ff569f	631	SDIO_FLAG_CMDREND \| SDIO_FLAG_CMDSENT \| SDIO_FLAG_DATAEND \|\
Anna Bridge	160:5571c4ff569f	632	SDIO_FLAG_DBCKEND))
Anna Bridge	160:5571c4ff569f	633	/**
Anna Bridge	160:5571c4ff569f	634	* @}
Anna Bridge	160:5571c4ff569f	635	*/
Anna Bridge	160:5571c4ff569f	636
Anna Bridge	160:5571c4ff569f	637	/**
Anna Bridge	160:5571c4ff569f	638	* @}
Anna Bridge	160:5571c4ff569f	639	*/
Anna Bridge	160:5571c4ff569f	640
Anna Bridge	160:5571c4ff569f	641	/* Exported macro ------------------------------------------------------------*/
Anna Bridge	160:5571c4ff569f	642	/** @defgroup SDIO_LL_Exported_macros SDIO_LL Exported Macros
Anna Bridge	160:5571c4ff569f	643	* @{
Anna Bridge	160:5571c4ff569f	644	*/
Anna Bridge	160:5571c4ff569f	645
Anna Bridge	160:5571c4ff569f	646	/** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
Anna Bridge	160:5571c4ff569f	647	* @{
Anna Bridge	160:5571c4ff569f	648	*/
Anna Bridge	160:5571c4ff569f	649	/* ------------ SDIO registers bit address in the alias region -------------- */
Anna Bridge	160:5571c4ff569f	650	#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
Anna Bridge	160:5571c4ff569f	651
Anna Bridge	160:5571c4ff569f	652	/* --- CLKCR Register ---*/
Anna Bridge	160:5571c4ff569f	653	/* Alias word address of CLKEN bit */
Anna Bridge	160:5571c4ff569f	654	#define CLKCR_OFFSET (SDIO_OFFSET + 0x04U)
Anna Bridge	160:5571c4ff569f	655	#define CLKEN_BITNUMBER 0x08U
Anna Bridge	160:5571c4ff569f	656	#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
Anna Bridge	160:5571c4ff569f	657
Anna Bridge	160:5571c4ff569f	658	/* --- CMD Register ---*/
Anna Bridge	160:5571c4ff569f	659	/* Alias word address of SDIOSUSPEND bit */
Anna Bridge	160:5571c4ff569f	660	#define CMD_OFFSET (SDIO_OFFSET + 0x0CU)
Anna Bridge	160:5571c4ff569f	661	#define SDIOSUSPEND_BITNUMBER 0x0BU
Anna Bridge	160:5571c4ff569f	662	#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
Anna Bridge	160:5571c4ff569f	663
Anna Bridge	160:5571c4ff569f	664	/* Alias word address of ENCMDCOMPL bit */
Anna Bridge	160:5571c4ff569f	665	#define ENCMDCOMPL_BITNUMBER 0x0CU
Anna Bridge	160:5571c4ff569f	666	#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
Anna Bridge	160:5571c4ff569f	667
Anna Bridge	160:5571c4ff569f	668	/* Alias word address of NIEN bit */
Anna Bridge	160:5571c4ff569f	669	#define NIEN_BITNUMBER 0x0DU
Anna Bridge	160:5571c4ff569f	670	#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
Anna Bridge	160:5571c4ff569f	671
Anna Bridge	160:5571c4ff569f	672	/* Alias word address of ATACMD bit */
Anna Bridge	160:5571c4ff569f	673	#define ATACMD_BITNUMBER 0x0EU
Anna Bridge	160:5571c4ff569f	674	#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
Anna Bridge	160:5571c4ff569f	675
Anna Bridge	160:5571c4ff569f	676	/* --- DCTRL Register ---*/
Anna Bridge	160:5571c4ff569f	677	/* Alias word address of DMAEN bit */
Anna Bridge	160:5571c4ff569f	678	#define DCTRL_OFFSET (SDIO_OFFSET + 0x2CU)
Anna Bridge	160:5571c4ff569f	679	#define DMAEN_BITNUMBER 0x03U
Anna Bridge	160:5571c4ff569f	680	#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
Anna Bridge	160:5571c4ff569f	681
Anna Bridge	160:5571c4ff569f	682	/* Alias word address of RWSTART bit */
Anna Bridge	160:5571c4ff569f	683	#define RWSTART_BITNUMBER 0x08U
Anna Bridge	160:5571c4ff569f	684	#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
Anna Bridge	160:5571c4ff569f	685
Anna Bridge	160:5571c4ff569f	686	/* Alias word address of RWSTOP bit */
Anna Bridge	160:5571c4ff569f	687	#define RWSTOP_BITNUMBER 0x09U
Anna Bridge	160:5571c4ff569f	688	#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
Anna Bridge	160:5571c4ff569f	689
Anna Bridge	160:5571c4ff569f	690	/* Alias word address of RWMOD bit */
Anna Bridge	160:5571c4ff569f	691	#define RWMOD_BITNUMBER 0x0AU
Anna Bridge	160:5571c4ff569f	692	#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
Anna Bridge	160:5571c4ff569f	693
Anna Bridge	160:5571c4ff569f	694	/* Alias word address of SDIOEN bit */
Anna Bridge	160:5571c4ff569f	695	#define SDIOEN_BITNUMBER 0x0BU
Anna Bridge	160:5571c4ff569f	696	#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))
Anna Bridge	160:5571c4ff569f	697	/**
Anna Bridge	160:5571c4ff569f	698	* @}
Anna Bridge	160:5571c4ff569f	699	*/
Anna Bridge	160:5571c4ff569f	700
Anna Bridge	160:5571c4ff569f	701	/** @defgroup SDIO_LL_Register Bits And Addresses Definitions
Anna Bridge	160:5571c4ff569f	702	* @brief SDIO_LL registers bit address in the alias region
Anna Bridge	160:5571c4ff569f	703	* @{
Anna Bridge	160:5571c4ff569f	704	*/
Anna Bridge	160:5571c4ff569f	705	/* ---------------------- SDIO registers bit mask --------------------------- */
Anna Bridge	160:5571c4ff569f	706	/* --- CLKCR Register ---*/
Anna Bridge	160:5571c4ff569f	707	/* CLKCR register clear mask */
Anna Bridge	160:5571c4ff569f	708	#define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV \| SDIO_CLKCR_PWRSAV \|\
Anna Bridge	160:5571c4ff569f	709	SDIO_CLKCR_BYPASS \| SDIO_CLKCR_WIDBUS \|\
Anna Bridge	160:5571c4ff569f	710	SDIO_CLKCR_NEGEDGE \| SDIO_CLKCR_HWFC_EN))
Anna Bridge	160:5571c4ff569f	711
Anna Bridge	160:5571c4ff569f	712	/* --- DCTRL Register ---*/
Anna Bridge	160:5571c4ff569f	713	/* SDIO DCTRL Clear Mask */
Anna Bridge	160:5571c4ff569f	714	#define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN \| SDIO_DCTRL_DTDIR \|\
Anna Bridge	160:5571c4ff569f	715	SDIO_DCTRL_DTMODE \| SDIO_DCTRL_DBLOCKSIZE))
Anna Bridge	160:5571c4ff569f	716
Anna Bridge	160:5571c4ff569f	717	/* --- CMD Register ---*/
Anna Bridge	160:5571c4ff569f	718	/* CMD Register clear mask */
Anna Bridge	160:5571c4ff569f	719	#define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX \| SDIO_CMD_WAITRESP \|\
Anna Bridge	160:5571c4ff569f	720	SDIO_CMD_WAITINT \| SDIO_CMD_WAITPEND \|\
Anna Bridge	160:5571c4ff569f	721	SDIO_CMD_CPSMEN \| SDIO_CMD_SDIOSUSPEND))
Anna Bridge	160:5571c4ff569f	722
Anna Bridge	160:5571c4ff569f	723	/* SDIO Initialization Frequency (400KHz max) */
Anna Bridge	160:5571c4ff569f	724	#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
Anna Bridge	160:5571c4ff569f	725
Anna Bridge	160:5571c4ff569f	726	/* SDIO Data Transfer Frequency (25MHz max) */
Anna Bridge	160:5571c4ff569f	727	#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
Anna Bridge	160:5571c4ff569f	728
Anna Bridge	160:5571c4ff569f	729	/**
Anna Bridge	160:5571c4ff569f	730	* @}
Anna Bridge	160:5571c4ff569f	731	*/
Anna Bridge	160:5571c4ff569f	732
Anna Bridge	160:5571c4ff569f	733	/** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration
Anna Bridge	160:5571c4ff569f	734	* @brief macros to handle interrupts and specific clock configurations
Anna Bridge	160:5571c4ff569f	735	* @{
Anna Bridge	160:5571c4ff569f	736	*/
Anna Bridge	160:5571c4ff569f	737
Anna Bridge	160:5571c4ff569f	738	/**
Anna Bridge	160:5571c4ff569f	739	* @brief Enable the SDIO device.
AnnaBridge	163:e59c8e839560	740	* @param __INSTANCE__ SDIO Instance
Anna Bridge	160:5571c4ff569f	741	* @retval None
Anna Bridge	160:5571c4ff569f	742	*/
Anna Bridge	160:5571c4ff569f	743	#define __SDIO_ENABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = ENABLE)
Anna Bridge	160:5571c4ff569f	744
Anna Bridge	160:5571c4ff569f	745	/**
Anna Bridge	160:5571c4ff569f	746	* @brief Disable the SDIO device.
AnnaBridge	163:e59c8e839560	747	* @param __INSTANCE__ SDIO Instance
Anna Bridge	160:5571c4ff569f	748	* @retval None
Anna Bridge	160:5571c4ff569f	749	*/
Anna Bridge	160:5571c4ff569f	750	#define __SDIO_DISABLE(__INSTANCE__) ((__IO uint32_t )CLKCR_CLKEN_BB = DISABLE)
Anna Bridge	160:5571c4ff569f	751
Anna Bridge	160:5571c4ff569f	752	/**
Anna Bridge	160:5571c4ff569f	753	* @brief Enable the SDIO DMA transfer.
AnnaBridge	163:e59c8e839560	754	* @param __INSTANCE__ SDIO Instance
Anna Bridge	160:5571c4ff569f	755	* @retval None
Anna Bridge	160:5571c4ff569f	756	*/
Anna Bridge	160:5571c4ff569f	757	#define __SDIO_DMA_ENABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = ENABLE)
Anna Bridge	160:5571c4ff569f	758	/**
Anna Bridge	160:5571c4ff569f	759	* @brief Disable the SDIO DMA transfer.
AnnaBridge	163:e59c8e839560	760	* @param __INSTANCE__ SDIO Instance
Anna Bridge	160:5571c4ff569f	761	* @retval None
Anna Bridge	160:5571c4ff569f	762	*/
Anna Bridge	160:5571c4ff569f	763	#define __SDIO_DMA_DISABLE(__INSTANCE__) ((__IO uint32_t )DCTRL_DMAEN_BB = DISABLE)
Anna Bridge	160:5571c4ff569f	764
Anna Bridge	160:5571c4ff569f	765	/**
Anna Bridge	160:5571c4ff569f	766	* @brief Enable the SDIO device interrupt.
AnnaBridge	163:e59c8e839560	767	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	163:e59c8e839560	768	* @param __INTERRUPT__ specifies the SDIO interrupt sources to be enabled.
Anna Bridge	160:5571c4ff569f	769	* This parameter can be one or a combination of the following values:
Anna Bridge	160:5571c4ff569f	770	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
Anna Bridge	160:5571c4ff569f	771	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
Anna Bridge	160:5571c4ff569f	772	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
Anna Bridge	160:5571c4ff569f	773	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
Anna Bridge	160:5571c4ff569f	774	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
Anna Bridge	160:5571c4ff569f	775	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
Anna Bridge	160:5571c4ff569f	776	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
Anna Bridge	160:5571c4ff569f	777	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
Anna Bridge	160:5571c4ff569f	778	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
Anna Bridge	160:5571c4ff569f	779	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
Anna Bridge	160:5571c4ff569f	780	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
Anna Bridge	160:5571c4ff569f	781	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
Anna Bridge	160:5571c4ff569f	782	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
Anna Bridge	160:5571c4ff569f	783	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
Anna Bridge	160:5571c4ff569f	784	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
Anna Bridge	160:5571c4ff569f	785	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
Anna Bridge	160:5571c4ff569f	786	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
Anna Bridge	160:5571c4ff569f	787	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
Anna Bridge	160:5571c4ff569f	788	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
Anna Bridge	160:5571c4ff569f	789	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
Anna Bridge	160:5571c4ff569f	790	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
Anna Bridge	160:5571c4ff569f	791	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
Anna Bridge	160:5571c4ff569f	792	* @retval None
Anna Bridge	160:5571c4ff569f	793	*/
Anna Bridge	160:5571c4ff569f	794	#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK \|= (__INTERRUPT__))
Anna Bridge	160:5571c4ff569f	795
Anna Bridge	160:5571c4ff569f	796	/**
Anna Bridge	160:5571c4ff569f	797	* @brief Disable the SDIO device interrupt.
AnnaBridge	163:e59c8e839560	798	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	163:e59c8e839560	799	* @param __INTERRUPT__ specifies the SDIO interrupt sources to be disabled.
Anna Bridge	160:5571c4ff569f	800	* This parameter can be one or a combination of the following values:
Anna Bridge	160:5571c4ff569f	801	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
Anna Bridge	160:5571c4ff569f	802	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
Anna Bridge	160:5571c4ff569f	803	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
Anna Bridge	160:5571c4ff569f	804	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
Anna Bridge	160:5571c4ff569f	805	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
Anna Bridge	160:5571c4ff569f	806	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
Anna Bridge	160:5571c4ff569f	807	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
Anna Bridge	160:5571c4ff569f	808	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
Anna Bridge	160:5571c4ff569f	809	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
Anna Bridge	160:5571c4ff569f	810	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
Anna Bridge	160:5571c4ff569f	811	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
Anna Bridge	160:5571c4ff569f	812	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
Anna Bridge	160:5571c4ff569f	813	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
Anna Bridge	160:5571c4ff569f	814	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
Anna Bridge	160:5571c4ff569f	815	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
Anna Bridge	160:5571c4ff569f	816	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
Anna Bridge	160:5571c4ff569f	817	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
Anna Bridge	160:5571c4ff569f	818	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
Anna Bridge	160:5571c4ff569f	819	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
Anna Bridge	160:5571c4ff569f	820	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
Anna Bridge	160:5571c4ff569f	821	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
Anna Bridge	160:5571c4ff569f	822	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
Anna Bridge	160:5571c4ff569f	823	* @retval None
Anna Bridge	160:5571c4ff569f	824	*/
Anna Bridge	160:5571c4ff569f	825	#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
Anna Bridge	160:5571c4ff569f	826
Anna Bridge	160:5571c4ff569f	827	/**
Anna Bridge	160:5571c4ff569f	828	* @brief Checks whether the specified SDIO flag is set or not.
AnnaBridge	163:e59c8e839560	829	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	163:e59c8e839560	830	* @param __FLAG__ specifies the flag to check.
Anna Bridge	160:5571c4ff569f	831	* This parameter can be one of the following values:
Anna Bridge	160:5571c4ff569f	832	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
Anna Bridge	160:5571c4ff569f	833	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
Anna Bridge	160:5571c4ff569f	834	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
Anna Bridge	160:5571c4ff569f	835	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
Anna Bridge	160:5571c4ff569f	836	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
Anna Bridge	160:5571c4ff569f	837	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
Anna Bridge	160:5571c4ff569f	838	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
Anna Bridge	160:5571c4ff569f	839	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
Anna Bridge	160:5571c4ff569f	840	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
Anna Bridge	160:5571c4ff569f	841	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
Anna Bridge	160:5571c4ff569f	842	* @arg SDIO_FLAG_CMDACT: Command transfer in progress
Anna Bridge	160:5571c4ff569f	843	* @arg SDIO_FLAG_TXACT: Data transmit in progress
Anna Bridge	160:5571c4ff569f	844	* @arg SDIO_FLAG_RXACT: Data receive in progress
Anna Bridge	160:5571c4ff569f	845	* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
Anna Bridge	160:5571c4ff569f	846	* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
Anna Bridge	160:5571c4ff569f	847	* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
Anna Bridge	160:5571c4ff569f	848	* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
Anna Bridge	160:5571c4ff569f	849	* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
Anna Bridge	160:5571c4ff569f	850	* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
Anna Bridge	160:5571c4ff569f	851	* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
Anna Bridge	160:5571c4ff569f	852	* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
Anna Bridge	160:5571c4ff569f	853	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
Anna Bridge	160:5571c4ff569f	854	* @retval The new state of SDIO_FLAG (SET or RESET).
Anna Bridge	160:5571c4ff569f	855	*/
Anna Bridge	160:5571c4ff569f	856	#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
Anna Bridge	160:5571c4ff569f	857
Anna Bridge	160:5571c4ff569f	858
Anna Bridge	160:5571c4ff569f	859	/**
Anna Bridge	160:5571c4ff569f	860	* @brief Clears the SDIO pending flags.
AnnaBridge	163:e59c8e839560	861	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	163:e59c8e839560	862	* @param __FLAG__ specifies the flag to clear.
Anna Bridge	160:5571c4ff569f	863	* This parameter can be one or a combination of the following values:
Anna Bridge	160:5571c4ff569f	864	* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
Anna Bridge	160:5571c4ff569f	865	* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
Anna Bridge	160:5571c4ff569f	866	* @arg SDIO_FLAG_CTIMEOUT: Command response timeout
Anna Bridge	160:5571c4ff569f	867	* @arg SDIO_FLAG_DTIMEOUT: Data timeout
Anna Bridge	160:5571c4ff569f	868	* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
Anna Bridge	160:5571c4ff569f	869	* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
Anna Bridge	160:5571c4ff569f	870	* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
Anna Bridge	160:5571c4ff569f	871	* @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
Anna Bridge	160:5571c4ff569f	872	* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
Anna Bridge	160:5571c4ff569f	873	* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
Anna Bridge	160:5571c4ff569f	874	* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
Anna Bridge	160:5571c4ff569f	875	* @retval None
Anna Bridge	160:5571c4ff569f	876	*/
Anna Bridge	160:5571c4ff569f	877	#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
Anna Bridge	160:5571c4ff569f	878
Anna Bridge	160:5571c4ff569f	879	/**
Anna Bridge	160:5571c4ff569f	880	* @brief Checks whether the specified SDIO interrupt has occurred or not.
AnnaBridge	163:e59c8e839560	881	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	163:e59c8e839560	882	* @param __INTERRUPT__ specifies the SDIO interrupt source to check.
Anna Bridge	160:5571c4ff569f	883	* This parameter can be one of the following values:
Anna Bridge	160:5571c4ff569f	884	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
Anna Bridge	160:5571c4ff569f	885	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
Anna Bridge	160:5571c4ff569f	886	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
Anna Bridge	160:5571c4ff569f	887	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
Anna Bridge	160:5571c4ff569f	888	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
Anna Bridge	160:5571c4ff569f	889	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
Anna Bridge	160:5571c4ff569f	890	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
Anna Bridge	160:5571c4ff569f	891	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
Anna Bridge	160:5571c4ff569f	892	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
Anna Bridge	160:5571c4ff569f	893	* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
Anna Bridge	160:5571c4ff569f	894	* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
Anna Bridge	160:5571c4ff569f	895	* @arg SDIO_IT_TXACT: Data transmit in progress interrupt
Anna Bridge	160:5571c4ff569f	896	* @arg SDIO_IT_RXACT: Data receive in progress interrupt
Anna Bridge	160:5571c4ff569f	897	* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
Anna Bridge	160:5571c4ff569f	898	* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
Anna Bridge	160:5571c4ff569f	899	* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
Anna Bridge	160:5571c4ff569f	900	* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
Anna Bridge	160:5571c4ff569f	901	* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
Anna Bridge	160:5571c4ff569f	902	* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
Anna Bridge	160:5571c4ff569f	903	* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
Anna Bridge	160:5571c4ff569f	904	* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
Anna Bridge	160:5571c4ff569f	905	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
Anna Bridge	160:5571c4ff569f	906	* @retval The new state of SDIO_IT (SET or RESET).
Anna Bridge	160:5571c4ff569f	907	*/
Anna Bridge	160:5571c4ff569f	908	#define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
Anna Bridge	160:5571c4ff569f	909
Anna Bridge	160:5571c4ff569f	910	/**
Anna Bridge	160:5571c4ff569f	911	* @brief Clears the SDIO's interrupt pending bits.
AnnaBridge	163:e59c8e839560	912	* @param __INSTANCE__ Pointer to SDIO register base
AnnaBridge	163:e59c8e839560	913	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
Anna Bridge	160:5571c4ff569f	914	* This parameter can be one or a combination of the following values:
Anna Bridge	160:5571c4ff569f	915	* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
Anna Bridge	160:5571c4ff569f	916	* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
Anna Bridge	160:5571c4ff569f	917	* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
Anna Bridge	160:5571c4ff569f	918	* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
Anna Bridge	160:5571c4ff569f	919	* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
Anna Bridge	160:5571c4ff569f	920	* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
Anna Bridge	160:5571c4ff569f	921	* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
Anna Bridge	160:5571c4ff569f	922	* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
Anna Bridge	160:5571c4ff569f	923	* @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
Anna Bridge	160:5571c4ff569f	924	* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
Anna Bridge	160:5571c4ff569f	925	* @retval None
Anna Bridge	160:5571c4ff569f	926	*/
Anna Bridge	160:5571c4ff569f	927	#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
Anna Bridge	160:5571c4ff569f	928
Anna Bridge	160:5571c4ff569f	929	/**
Anna Bridge	160:5571c4ff569f	930	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	163:e59c8e839560	931	* @param __INSTANCE__ Pointer to SDIO register base
Anna Bridge	160:5571c4ff569f	932	* @retval None
Anna Bridge	160:5571c4ff569f	933	*/
Anna Bridge	160:5571c4ff569f	934	#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = ENABLE)
Anna Bridge	160:5571c4ff569f	935
Anna Bridge	160:5571c4ff569f	936	/**
Anna Bridge	160:5571c4ff569f	937	* @brief Disable Start the SD I/O Read Wait operations.
AnnaBridge	163:e59c8e839560	938	* @param __INSTANCE__ Pointer to SDIO register base
Anna Bridge	160:5571c4ff569f	939	* @retval None
Anna Bridge	160:5571c4ff569f	940	*/
Anna Bridge	160:5571c4ff569f	941	#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTART_BB = DISABLE)
Anna Bridge	160:5571c4ff569f	942
Anna Bridge	160:5571c4ff569f	943	/**
Anna Bridge	160:5571c4ff569f	944	* @brief Enable Start the SD I/O Read Wait operation.
AnnaBridge	163:e59c8e839560	945	* @param __INSTANCE__ Pointer to SDIO register base
Anna Bridge	160:5571c4ff569f	946	* @retval None
Anna Bridge	160:5571c4ff569f	947	*/
Anna Bridge	160:5571c4ff569f	948	#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = ENABLE)
Anna Bridge	160:5571c4ff569f	949
Anna Bridge	160:5571c4ff569f	950	/**
Anna Bridge	160:5571c4ff569f	951	* @brief Disable Stop the SD I/O Read Wait operations.
AnnaBridge	163:e59c8e839560	952	* @param __INSTANCE__ Pointer to SDIO register base
Anna Bridge	160:5571c4ff569f	953	* @retval None
Anna Bridge	160:5571c4ff569f	954	*/
Anna Bridge	160:5571c4ff569f	955	#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_RWSTOP_BB = DISABLE)
Anna Bridge	160:5571c4ff569f	956
Anna Bridge	160:5571c4ff569f	957	/**
Anna Bridge	160:5571c4ff569f	958	* @brief Enable the SD I/O Mode Operation.
AnnaBridge	163:e59c8e839560	959	* @param __INSTANCE__ Pointer to SDIO register base
Anna Bridge	160:5571c4ff569f	960	* @retval None
Anna Bridge	160:5571c4ff569f	961	*/
Anna Bridge	160:5571c4ff569f	962	#define __SDIO_OPERATION_ENABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = ENABLE)
Anna Bridge	160:5571c4ff569f	963
Anna Bridge	160:5571c4ff569f	964	/**
Anna Bridge	160:5571c4ff569f	965	* @brief Disable the SD I/O Mode Operation.
AnnaBridge	163:e59c8e839560	966	* @param __INSTANCE__ Pointer to SDIO register base
Anna Bridge	160:5571c4ff569f	967	* @retval None
Anna Bridge	160:5571c4ff569f	968	*/
Anna Bridge	160:5571c4ff569f	969	#define __SDIO_OPERATION_DISABLE(__INSTANCE__) ((__IO uint32_t ) DCTRL_SDIOEN_BB = DISABLE)
Anna Bridge	160:5571c4ff569f	970
Anna Bridge	160:5571c4ff569f	971	/**
Anna Bridge	160:5571c4ff569f	972	* @brief Enable the SD I/O Suspend command sending.
AnnaBridge	163:e59c8e839560	973	* @param __INSTANCE__ Pointer to SDIO register base
Anna Bridge	160:5571c4ff569f	974	* @retval None
Anna Bridge	160:5571c4ff569f	975	*/
Anna Bridge	160:5571c4ff569f	976	#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = ENABLE)
Anna Bridge	160:5571c4ff569f	977
Anna Bridge	160:5571c4ff569f	978	/**
Anna Bridge	160:5571c4ff569f	979	* @brief Disable the SD I/O Suspend command sending.
AnnaBridge	163:e59c8e839560	980	* @param __INSTANCE__ Pointer to SDIO register base
Anna Bridge	160:5571c4ff569f	981	* @retval None
Anna Bridge	160:5571c4ff569f	982	*/
Anna Bridge	160:5571c4ff569f	983	#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__IO uint32_t ) CMD_SDIOSUSPEND_BB = DISABLE)
Anna Bridge	160:5571c4ff569f	984
Anna Bridge	160:5571c4ff569f	985	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx) \|\| defined(STM32F417xx) \|\|\
Anna Bridge	160:5571c4ff569f	986	defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Anna Bridge	160:5571c4ff569f	987	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
Anna Bridge	160:5571c4ff569f	988	/**
Anna Bridge	160:5571c4ff569f	989	* @brief Enable the command completion signal.
Anna Bridge	160:5571c4ff569f	990	* @retval None
Anna Bridge	160:5571c4ff569f	991	*/
Anna Bridge	160:5571c4ff569f	992	#define __SDIO_CEATA_CMD_COMPLETION_ENABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = ENABLE)
Anna Bridge	160:5571c4ff569f	993
Anna Bridge	160:5571c4ff569f	994	/**
Anna Bridge	160:5571c4ff569f	995	* @brief Disable the command completion signal.
Anna Bridge	160:5571c4ff569f	996	* @retval None
Anna Bridge	160:5571c4ff569f	997	*/
Anna Bridge	160:5571c4ff569f	998	#define __SDIO_CEATA_CMD_COMPLETION_DISABLE() ((__IO uint32_t ) CMD_ENCMDCOMPL_BB = DISABLE)
Anna Bridge	160:5571c4ff569f	999
Anna Bridge	160:5571c4ff569f	1000	/**
Anna Bridge	160:5571c4ff569f	1001	* @brief Enable the CE-ATA interrupt.
Anna Bridge	160:5571c4ff569f	1002	* @retval None
Anna Bridge	160:5571c4ff569f	1003	*/
Anna Bridge	160:5571c4ff569f	1004	#define __SDIO_CEATA_ENABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)0U)
Anna Bridge	160:5571c4ff569f	1005
Anna Bridge	160:5571c4ff569f	1006	/**
Anna Bridge	160:5571c4ff569f	1007	* @brief Disable the CE-ATA interrupt.
Anna Bridge	160:5571c4ff569f	1008	* @retval None
Anna Bridge	160:5571c4ff569f	1009	*/
Anna Bridge	160:5571c4ff569f	1010	#define __SDIO_CEATA_DISABLE_IT() ((__IO uint32_t ) CMD_NIEN_BB = (uint32_t)1U)
Anna Bridge	160:5571c4ff569f	1011
Anna Bridge	160:5571c4ff569f	1012	/**
Anna Bridge	160:5571c4ff569f	1013	* @brief Enable send CE-ATA command (CMD61).
Anna Bridge	160:5571c4ff569f	1014	* @retval None
Anna Bridge	160:5571c4ff569f	1015	*/
Anna Bridge	160:5571c4ff569f	1016	#define __SDIO_CEATA_SENDCMD_ENABLE() ((__IO uint32_t ) CMD_ATACMD_BB = ENABLE)
Anna Bridge	160:5571c4ff569f	1017
Anna Bridge	160:5571c4ff569f	1018	/**
Anna Bridge	160:5571c4ff569f	1019	* @brief Disable send CE-ATA command (CMD61).
Anna Bridge	160:5571c4ff569f	1020	* @retval None
Anna Bridge	160:5571c4ff569f	1021	*/
Anna Bridge	160:5571c4ff569f	1022	#define __SDIO_CEATA_SENDCMD_DISABLE() ((__IO uint32_t ) CMD_ATACMD_BB = DISABLE)
Anna Bridge	160:5571c4ff569f	1023	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\|\
Anna Bridge	160:5571c4ff569f	1024	STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Anna Bridge	160:5571c4ff569f	1025
Anna Bridge	160:5571c4ff569f	1026	/**
Anna Bridge	160:5571c4ff569f	1027	* @}
Anna Bridge	160:5571c4ff569f	1028	*/
Anna Bridge	160:5571c4ff569f	1029
Anna Bridge	160:5571c4ff569f	1030	/**
Anna Bridge	160:5571c4ff569f	1031	* @}
Anna Bridge	160:5571c4ff569f	1032	*/
Anna Bridge	160:5571c4ff569f	1033
Anna Bridge	160:5571c4ff569f	1034	/* Exported functions --------------------------------------------------------*/
Anna Bridge	160:5571c4ff569f	1035	/** @addtogroup SDMMC_LL_Exported_Functions
Anna Bridge	160:5571c4ff569f	1036	* @{
Anna Bridge	160:5571c4ff569f	1037	*/
Anna Bridge	160:5571c4ff569f	1038
Anna Bridge	160:5571c4ff569f	1039	/* Initialization/de-initialization functions **********************************/
Anna Bridge	160:5571c4ff569f	1040	/** @addtogroup HAL_SDMMC_LL_Group1
Anna Bridge	160:5571c4ff569f	1041	* @{
Anna Bridge	160:5571c4ff569f	1042	*/
Anna Bridge	160:5571c4ff569f	1043	HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
Anna Bridge	160:5571c4ff569f	1044	/**
Anna Bridge	160:5571c4ff569f	1045	* @}
Anna Bridge	160:5571c4ff569f	1046	*/
Anna Bridge	160:5571c4ff569f	1047
Anna Bridge	160:5571c4ff569f	1048	/* I/O operation functions *****************************************************/
Anna Bridge	160:5571c4ff569f	1049	/** @addtogroup HAL_SDMMC_LL_Group2
Anna Bridge	160:5571c4ff569f	1050	* @{
Anna Bridge	160:5571c4ff569f	1051	*/
Anna Bridge	160:5571c4ff569f	1052	uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1053	HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef SDIOx, uint32_t pWriteData);
Anna Bridge	160:5571c4ff569f	1054	/**
Anna Bridge	160:5571c4ff569f	1055	* @}
Anna Bridge	160:5571c4ff569f	1056	*/
Anna Bridge	160:5571c4ff569f	1057
Anna Bridge	160:5571c4ff569f	1058	/* Peripheral Control functions ************************************************/
Anna Bridge	160:5571c4ff569f	1059	/** @addtogroup HAL_SDMMC_LL_Group3
Anna Bridge	160:5571c4ff569f	1060	* @{
Anna Bridge	160:5571c4ff569f	1061	*/
Anna Bridge	160:5571c4ff569f	1062	HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1063	HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1064	uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1065
Anna Bridge	160:5571c4ff569f	1066	/* Command path state machine (CPSM) management functions */
Anna Bridge	160:5571c4ff569f	1067	HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef SDIOx, SDIO_CmdInitTypeDef Command);
Anna Bridge	160:5571c4ff569f	1068	uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1069	uint32_t SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
Anna Bridge	160:5571c4ff569f	1070
Anna Bridge	160:5571c4ff569f	1071	/* Data path state machine (DPSM) management functions */
Anna Bridge	160:5571c4ff569f	1072	HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef SDIOx, SDIO_DataInitTypeDef Data);
Anna Bridge	160:5571c4ff569f	1073	uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1074	uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1075
Anna Bridge	160:5571c4ff569f	1076	/* SDMMC Cards mode management functions */
Anna Bridge	160:5571c4ff569f	1077	HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
Anna Bridge	160:5571c4ff569f	1078
Anna Bridge	160:5571c4ff569f	1079	/* SDMMC Commands management functions */
Anna Bridge	160:5571c4ff569f	1080	uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
Anna Bridge	160:5571c4ff569f	1081	uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
Anna Bridge	160:5571c4ff569f	1082	uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
Anna Bridge	160:5571c4ff569f	1083	uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
Anna Bridge	160:5571c4ff569f	1084	uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
Anna Bridge	160:5571c4ff569f	1085	uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
Anna Bridge	160:5571c4ff569f	1086	uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
Anna Bridge	160:5571c4ff569f	1087	uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1088	uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1089	uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
Anna Bridge	160:5571c4ff569f	1090	uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1091	uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1092	uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
Anna Bridge	160:5571c4ff569f	1093	uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType);
Anna Bridge	160:5571c4ff569f	1094	uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
Anna Bridge	160:5571c4ff569f	1095	uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1096	uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1097	uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
Anna Bridge	160:5571c4ff569f	1098	uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef SDIOx, uint16_t pRCA);
Anna Bridge	160:5571c4ff569f	1099	uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
Anna Bridge	160:5571c4ff569f	1100	uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
Anna Bridge	160:5571c4ff569f	1101
Anna Bridge	160:5571c4ff569f	1102	uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
Anna Bridge	160:5571c4ff569f	1103	uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
Anna Bridge	160:5571c4ff569f	1104	uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
Anna Bridge	160:5571c4ff569f	1105	uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
Anna Bridge	160:5571c4ff569f	1106
Anna Bridge	160:5571c4ff569f	1107	/**
Anna Bridge	160:5571c4ff569f	1108	* @}
Anna Bridge	160:5571c4ff569f	1109	*/
Anna Bridge	160:5571c4ff569f	1110
Anna Bridge	160:5571c4ff569f	1111	/**
Anna Bridge	160:5571c4ff569f	1112	* @}
Anna Bridge	160:5571c4ff569f	1113	*/
Anna Bridge	160:5571c4ff569f	1114
Anna Bridge	160:5571c4ff569f	1115	/**
Anna Bridge	160:5571c4ff569f	1116	* @}
Anna Bridge	160:5571c4ff569f	1117	*/
Anna Bridge	160:5571c4ff569f	1118
Anna Bridge	160:5571c4ff569f	1119	/**
Anna Bridge	160:5571c4ff569f	1120	* @}
Anna Bridge	160:5571c4ff569f	1121	*/
Anna Bridge	160:5571c4ff569f	1122
Anna Bridge	160:5571c4ff569f	1123	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\|
Anna Bridge	160:5571c4ff569f	1124	STM32F401xC \|\| STM32F401xE \|\| STM32F411xE \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx \|\| STM32F412Zx \|\| STM32F412Vx \|\|
Anna Bridge	160:5571c4ff569f	1125	STM32F412Rx \|\| STM32F412Cx \|\| STM32F413xx \|\| STM32F423xx */
Anna Bridge	160:5571c4ff569f	1126
Anna Bridge	160:5571c4ff569f	1127	#ifdef __cplusplus
Anna Bridge	160:5571c4ff569f	1128	}
Anna Bridge	160:5571c4ff569f	1129	#endif
Anna Bridge	160:5571c4ff569f	1130
Anna Bridge	160:5571c4ff569f	1131	#endif /* __STM32F4xx_LL_SDMMC_H */
Anna Bridge	160:5571c4ff569f	1132
Anna Bridge	160:5571c4ff569f	1133	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/