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TARGET_ELMO_F411RE/TOOLCHAIN_GCC_ARM/stm32f4xx_hal_dsi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	161:aa5281ff4a02	1	/**
AnnaBridge	161:aa5281ff4a02	2	******************************************************************************
AnnaBridge	161:aa5281ff4a02	3	* @file stm32f4xx_hal_dsi.h
AnnaBridge	161:aa5281ff4a02	4	* @author MCD Application Team
AnnaBridge	161:aa5281ff4a02	5	* @brief Header file of DSI HAL module.
AnnaBridge	161:aa5281ff4a02	6	******************************************************************************
AnnaBridge	161:aa5281ff4a02	7	* @attention
AnnaBridge	161:aa5281ff4a02	8	*
AnnaBridge	161:aa5281ff4a02	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	161:aa5281ff4a02	10	*
AnnaBridge	161:aa5281ff4a02	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	161:aa5281ff4a02	12	* are permitted provided that the following conditions are met:
AnnaBridge	161:aa5281ff4a02	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	161:aa5281ff4a02	14	* this list of conditions and the following disclaimer.
AnnaBridge	161:aa5281ff4a02	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	161:aa5281ff4a02	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	161:aa5281ff4a02	17	* and/or other materials provided with the distribution.
AnnaBridge	161:aa5281ff4a02	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	161:aa5281ff4a02	19	* may be used to endorse or promote products derived from this software
AnnaBridge	161:aa5281ff4a02	20	* without specific prior written permission.
AnnaBridge	161:aa5281ff4a02	21	*
AnnaBridge	161:aa5281ff4a02	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	161:aa5281ff4a02	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	161:aa5281ff4a02	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	161:aa5281ff4a02	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	161:aa5281ff4a02	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	161:aa5281ff4a02	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	161:aa5281ff4a02	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	161:aa5281ff4a02	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	161:aa5281ff4a02	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	161:aa5281ff4a02	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	161:aa5281ff4a02	32	*
AnnaBridge	161:aa5281ff4a02	33	******************************************************************************
AnnaBridge	161:aa5281ff4a02	34	*/
AnnaBridge	161:aa5281ff4a02	35
AnnaBridge	161:aa5281ff4a02	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	161:aa5281ff4a02	37	#ifndef __STM32F4xx_HAL_DSI_H
AnnaBridge	161:aa5281ff4a02	38	#define __STM32F4xx_HAL_DSI_H
AnnaBridge	161:aa5281ff4a02	39
AnnaBridge	161:aa5281ff4a02	40	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	41	extern "C" {
AnnaBridge	161:aa5281ff4a02	42	#endif
AnnaBridge	161:aa5281ff4a02	43
AnnaBridge	163:e59c8e839560	44	#if defined(DSI)
AnnaBridge	161:aa5281ff4a02	45	/* Includes ------------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	46	#include "stm32f4xx_hal_def.h"
AnnaBridge	161:aa5281ff4a02	47
AnnaBridge	161:aa5281ff4a02	48	/** @addtogroup STM32F4xx_HAL_Driver
AnnaBridge	161:aa5281ff4a02	49	* @{
AnnaBridge	161:aa5281ff4a02	50	*/
AnnaBridge	161:aa5281ff4a02	51
AnnaBridge	161:aa5281ff4a02	52	/** @defgroup DSI DSI
AnnaBridge	161:aa5281ff4a02	53	* @brief DSI HAL module driver
AnnaBridge	161:aa5281ff4a02	54	* @{
AnnaBridge	163:e59c8e839560	55	*/
AnnaBridge	161:aa5281ff4a02	56
AnnaBridge	161:aa5281ff4a02	57	/* Exported types ------------------------------------------------------------*/
AnnaBridge	163:e59c8e839560	58	/**
AnnaBridge	161:aa5281ff4a02	59	* @brief DSI Init Structure definition
AnnaBridge	161:aa5281ff4a02	60	*/
AnnaBridge	161:aa5281ff4a02	61	typedef struct
AnnaBridge	161:aa5281ff4a02	62	{
AnnaBridge	161:aa5281ff4a02	63	uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control
AnnaBridge	161:aa5281ff4a02	64	This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */
AnnaBridge	161:aa5281ff4a02	65
AnnaBridge	161:aa5281ff4a02	66	uint32_t TXEscapeCkdiv; /*!< TX Escape clock division
AnnaBridge	161:aa5281ff4a02	67	The values 0 and 1 stop the TX_ESC clock generation */
AnnaBridge	161:aa5281ff4a02	68
AnnaBridge	161:aa5281ff4a02	69	uint32_t NumberOfLanes; /*!< Number of lanes
AnnaBridge	161:aa5281ff4a02	70	This parameter can be any value of @ref DSI_Number_Of_Lanes */
AnnaBridge	161:aa5281ff4a02	71
AnnaBridge	161:aa5281ff4a02	72	}DSI_InitTypeDef;
AnnaBridge	161:aa5281ff4a02	73
AnnaBridge	163:e59c8e839560	74	/**
AnnaBridge	163:e59c8e839560	75	* @brief DSI PLL Clock structure definition
AnnaBridge	161:aa5281ff4a02	76	*/
AnnaBridge	161:aa5281ff4a02	77	typedef struct
AnnaBridge	161:aa5281ff4a02	78	{
AnnaBridge	161:aa5281ff4a02	79	uint32_t PLLNDIV; /*!< PLL Loop Division Factor
AnnaBridge	161:aa5281ff4a02	80	This parameter must be a value between 10 and 125 */
AnnaBridge	161:aa5281ff4a02	81
AnnaBridge	161:aa5281ff4a02	82	uint32_t PLLIDF; /*!< PLL Input Division Factor
AnnaBridge	161:aa5281ff4a02	83	This parameter can be any value of @ref DSI_PLL_IDF */
AnnaBridge	161:aa5281ff4a02	84
AnnaBridge	161:aa5281ff4a02	85	uint32_t PLLODF; /*!< PLL Output Division Factor
AnnaBridge	161:aa5281ff4a02	86	This parameter can be any value of @ref DSI_PLL_ODF */
AnnaBridge	161:aa5281ff4a02	87
AnnaBridge	161:aa5281ff4a02	88	}DSI_PLLInitTypeDef;
AnnaBridge	161:aa5281ff4a02	89
AnnaBridge	163:e59c8e839560	90	/**
AnnaBridge	161:aa5281ff4a02	91	* @brief DSI Video mode configuration
AnnaBridge	161:aa5281ff4a02	92	*/
AnnaBridge	163:e59c8e839560	93	typedef struct
AnnaBridge	161:aa5281ff4a02	94	{
AnnaBridge	161:aa5281ff4a02	95	uint32_t VirtualChannelID; /!< Virtual channel ID /
AnnaBridge	163:e59c8e839560	96
AnnaBridge	161:aa5281ff4a02	97	uint32_t ColorCoding; /*!< Color coding for LTDC interface
AnnaBridge	161:aa5281ff4a02	98	This parameter can be any value of @ref DSI_Color_Coding */
AnnaBridge	163:e59c8e839560	99
AnnaBridge	161:aa5281ff4a02	100	uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
AnnaBridge	161:aa5281ff4a02	101	18-bit configuration).
AnnaBridge	161:aa5281ff4a02	102	This parameter can be any value of @ref DSI_LooselyPacked */
AnnaBridge	163:e59c8e839560	103
AnnaBridge	161:aa5281ff4a02	104	uint32_t Mode; /*!< Video mode type
AnnaBridge	161:aa5281ff4a02	105	This parameter can be any value of @ref DSI_Video_Mode_Type */
AnnaBridge	163:e59c8e839560	106
AnnaBridge	161:aa5281ff4a02	107	uint32_t PacketSize; /!< Video packet size /
AnnaBridge	163:e59c8e839560	108
AnnaBridge	161:aa5281ff4a02	109	uint32_t NumberOfChunks; /!< Number of chunks /
AnnaBridge	163:e59c8e839560	110
AnnaBridge	161:aa5281ff4a02	111	uint32_t NullPacketSize; /!< Null packet size /
AnnaBridge	163:e59c8e839560	112
AnnaBridge	161:aa5281ff4a02	113	uint32_t HSPolarity; /*!< HSYNC pin polarity
AnnaBridge	161:aa5281ff4a02	114	This parameter can be any value of @ref DSI_HSYNC_Polarity */
AnnaBridge	163:e59c8e839560	115
AnnaBridge	161:aa5281ff4a02	116	uint32_t VSPolarity; /*!< VSYNC pin polarity
AnnaBridge	161:aa5281ff4a02	117	This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
AnnaBridge	163:e59c8e839560	118
AnnaBridge	161:aa5281ff4a02	119	uint32_t DEPolarity; /*!< Data Enable pin polarity
AnnaBridge	161:aa5281ff4a02	120	This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
AnnaBridge	163:e59c8e839560	121
AnnaBridge	161:aa5281ff4a02	122	uint32_t HorizontalSyncActive; /!< Horizontal synchronism active duration (in lane byte clock cycles) /
AnnaBridge	163:e59c8e839560	123
AnnaBridge	161:aa5281ff4a02	124	uint32_t HorizontalBackPorch; /!< Horizontal back-porch duration (in lane byte clock cycles) /
AnnaBridge	163:e59c8e839560	125
AnnaBridge	161:aa5281ff4a02	126	uint32_t HorizontalLine; /!< Horizontal line duration (in lane byte clock cycles) /
AnnaBridge	163:e59c8e839560	127
AnnaBridge	161:aa5281ff4a02	128	uint32_t VerticalSyncActive; /!< Vertical synchronism active duration /
AnnaBridge	163:e59c8e839560	129
AnnaBridge	161:aa5281ff4a02	130	uint32_t VerticalBackPorch; /!< Vertical back-porch duration /
AnnaBridge	163:e59c8e839560	131
AnnaBridge	161:aa5281ff4a02	132	uint32_t VerticalFrontPorch; /!< Vertical front-porch duration /
AnnaBridge	163:e59c8e839560	133
AnnaBridge	161:aa5281ff4a02	134	uint32_t VerticalActive; /!< Vertical active duration /
AnnaBridge	163:e59c8e839560	135
AnnaBridge	161:aa5281ff4a02	136	uint32_t LPCommandEnable; /*!< Low-power command enable
AnnaBridge	161:aa5281ff4a02	137	This parameter can be any value of @ref DSI_LP_Command */
AnnaBridge	163:e59c8e839560	138
AnnaBridge	161:aa5281ff4a02	139	uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
AnnaBridge	161:aa5281ff4a02	140	can fit in a line during VSA, VBP and VFP regions */
AnnaBridge	163:e59c8e839560	141
AnnaBridge	161:aa5281ff4a02	142	uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
AnnaBridge	161:aa5281ff4a02	143	can fit in a line during VACT region */
AnnaBridge	163:e59c8e839560	144
AnnaBridge	161:aa5281ff4a02	145	uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
AnnaBridge	161:aa5281ff4a02	146	This parameter can be any value of @ref DSI_LP_HFP */
AnnaBridge	163:e59c8e839560	147
AnnaBridge	161:aa5281ff4a02	148	uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
AnnaBridge	161:aa5281ff4a02	149	This parameter can be any value of @ref DSI_LP_HBP */
AnnaBridge	163:e59c8e839560	150
AnnaBridge	161:aa5281ff4a02	151	uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
AnnaBridge	161:aa5281ff4a02	152	This parameter can be any value of @ref DSI_LP_VACT */
AnnaBridge	163:e59c8e839560	153
AnnaBridge	161:aa5281ff4a02	154	uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
AnnaBridge	161:aa5281ff4a02	155	This parameter can be any value of @ref DSI_LP_VFP */
AnnaBridge	163:e59c8e839560	156
AnnaBridge	161:aa5281ff4a02	157	uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
AnnaBridge	161:aa5281ff4a02	158	This parameter can be any value of @ref DSI_LP_VBP */
AnnaBridge	163:e59c8e839560	159
AnnaBridge	161:aa5281ff4a02	160	uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
AnnaBridge	161:aa5281ff4a02	161	This parameter can be any value of @ref DSI_LP_VSYNC */
AnnaBridge	163:e59c8e839560	162
AnnaBridge	161:aa5281ff4a02	163	uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
AnnaBridge	161:aa5281ff4a02	164	This parameter can be any value of @ref DSI_FBTA_acknowledge */
AnnaBridge	163:e59c8e839560	165
AnnaBridge	161:aa5281ff4a02	166	}DSI_VidCfgTypeDef;
AnnaBridge	161:aa5281ff4a02	167
AnnaBridge	163:e59c8e839560	168	/**
AnnaBridge	161:aa5281ff4a02	169	* @brief DSI Adapted command mode configuration
AnnaBridge	161:aa5281ff4a02	170	*/
AnnaBridge	163:e59c8e839560	171	typedef struct
AnnaBridge	161:aa5281ff4a02	172	{
AnnaBridge	161:aa5281ff4a02	173	uint32_t VirtualChannelID; /!< Virtual channel ID /
AnnaBridge	161:aa5281ff4a02	174
AnnaBridge	161:aa5281ff4a02	175	uint32_t ColorCoding; /*!< Color coding for LTDC interface
AnnaBridge	161:aa5281ff4a02	176	This parameter can be any value of @ref DSI_Color_Coding */
AnnaBridge	161:aa5281ff4a02	177
AnnaBridge	163:e59c8e839560	178	uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
AnnaBridge	161:aa5281ff4a02	179	pixels. This parameter can be any value between 0x00 and 0xFFFFU */
AnnaBridge	161:aa5281ff4a02	180
AnnaBridge	161:aa5281ff4a02	181	uint32_t TearingEffectSource; /*!< Tearing effect source
AnnaBridge	161:aa5281ff4a02	182	This parameter can be any value of @ref DSI_TearingEffectSource */
AnnaBridge	161:aa5281ff4a02	183
AnnaBridge	161:aa5281ff4a02	184	uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity
AnnaBridge	161:aa5281ff4a02	185	This parameter can be any value of @ref DSI_TearingEffectPolarity */
AnnaBridge	161:aa5281ff4a02	186
AnnaBridge	161:aa5281ff4a02	187	uint32_t HSPolarity; /*!< HSYNC pin polarity
AnnaBridge	161:aa5281ff4a02	188	This parameter can be any value of @ref DSI_HSYNC_Polarity */
AnnaBridge	161:aa5281ff4a02	189
AnnaBridge	161:aa5281ff4a02	190	uint32_t VSPolarity; /*!< VSYNC pin polarity
AnnaBridge	161:aa5281ff4a02	191	This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
AnnaBridge	161:aa5281ff4a02	192
AnnaBridge	161:aa5281ff4a02	193	uint32_t DEPolarity; /*!< Data Enable pin polarity
AnnaBridge	161:aa5281ff4a02	194	This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
AnnaBridge	161:aa5281ff4a02	195
AnnaBridge	161:aa5281ff4a02	196	uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted
AnnaBridge	161:aa5281ff4a02	197	This parameter can be any value of @ref DSI_Vsync_Polarity */
AnnaBridge	161:aa5281ff4a02	198
AnnaBridge	161:aa5281ff4a02	199	uint32_t AutomaticRefresh; /*!< Automatic refresh mode
AnnaBridge	161:aa5281ff4a02	200	This parameter can be any value of @ref DSI_AutomaticRefresh */
AnnaBridge	161:aa5281ff4a02	201
AnnaBridge	161:aa5281ff4a02	202	uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable
AnnaBridge	161:aa5281ff4a02	203	This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */
AnnaBridge	161:aa5281ff4a02	204
AnnaBridge	161:aa5281ff4a02	205	}DSI_CmdCfgTypeDef;
AnnaBridge	161:aa5281ff4a02	206
AnnaBridge	163:e59c8e839560	207	/**
AnnaBridge	161:aa5281ff4a02	208	* @brief DSI command transmission mode configuration
AnnaBridge	161:aa5281ff4a02	209	*/
AnnaBridge	163:e59c8e839560	210	typedef struct
AnnaBridge	161:aa5281ff4a02	211	{
AnnaBridge	161:aa5281ff4a02	212	uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
AnnaBridge	161:aa5281ff4a02	213	This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
AnnaBridge	161:aa5281ff4a02	214
AnnaBridge	161:aa5281ff4a02	215	uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission
AnnaBridge	161:aa5281ff4a02	216	This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */
AnnaBridge	161:aa5281ff4a02	217
AnnaBridge	161:aa5281ff4a02	218	uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission
AnnaBridge	161:aa5281ff4a02	219	This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */
AnnaBridge	161:aa5281ff4a02	220
AnnaBridge	161:aa5281ff4a02	221	uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission
AnnaBridge	161:aa5281ff4a02	222	This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */
AnnaBridge	161:aa5281ff4a02	223
AnnaBridge	161:aa5281ff4a02	224	uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission
AnnaBridge	161:aa5281ff4a02	225	This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */
AnnaBridge	161:aa5281ff4a02	226
AnnaBridge	161:aa5281ff4a02	227	uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission
AnnaBridge	161:aa5281ff4a02	228	This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */
AnnaBridge	161:aa5281ff4a02	229
AnnaBridge	161:aa5281ff4a02	230	uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission
AnnaBridge	161:aa5281ff4a02	231	This parameter can be any value of @ref DSI_LP_LPGenLongWrite */
AnnaBridge	161:aa5281ff4a02	232
AnnaBridge	161:aa5281ff4a02	233	uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission
AnnaBridge	161:aa5281ff4a02	234	This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */
AnnaBridge	161:aa5281ff4a02	235
AnnaBridge	161:aa5281ff4a02	236	uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission
AnnaBridge	161:aa5281ff4a02	237	This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */
AnnaBridge	161:aa5281ff4a02	238
AnnaBridge	161:aa5281ff4a02	239	uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission
AnnaBridge	161:aa5281ff4a02	240	This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */
AnnaBridge	161:aa5281ff4a02	241
AnnaBridge	161:aa5281ff4a02	242	uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission
AnnaBridge	161:aa5281ff4a02	243	This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */
AnnaBridge	161:aa5281ff4a02	244
AnnaBridge	161:aa5281ff4a02	245	uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission
AnnaBridge	161:aa5281ff4a02	246	This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */
AnnaBridge	161:aa5281ff4a02	247
AnnaBridge	161:aa5281ff4a02	248	uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable
AnnaBridge	161:aa5281ff4a02	249	This parameter can be any value of @ref DSI_AcknowledgeRequest */
AnnaBridge	161:aa5281ff4a02	250
AnnaBridge	161:aa5281ff4a02	251	}DSI_LPCmdTypeDef;
AnnaBridge	161:aa5281ff4a02	252
AnnaBridge	163:e59c8e839560	253	/**
AnnaBridge	161:aa5281ff4a02	254	* @brief DSI PHY Timings definition
AnnaBridge	161:aa5281ff4a02	255	*/
AnnaBridge	163:e59c8e839560	256	typedef struct
AnnaBridge	161:aa5281ff4a02	257	{
AnnaBridge	161:aa5281ff4a02	258	uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
AnnaBridge	161:aa5281ff4a02	259	to low-power transmission */
AnnaBridge	161:aa5281ff4a02	260
AnnaBridge	161:aa5281ff4a02	261	uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power
AnnaBridge	161:aa5281ff4a02	262	to high-speed transmission */
AnnaBridge	161:aa5281ff4a02	263
AnnaBridge	161:aa5281ff4a02	264	uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed
AnnaBridge	161:aa5281ff4a02	265	to low-power transmission */
AnnaBridge	161:aa5281ff4a02	266
AnnaBridge	161:aa5281ff4a02	267	uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power
AnnaBridge	161:aa5281ff4a02	268	to high-speed transmission */
AnnaBridge	161:aa5281ff4a02	269
AnnaBridge	161:aa5281ff4a02	270	uint32_t DataLaneMaxReadTime; /!< The maximum time required to perform a read command /
AnnaBridge	161:aa5281ff4a02	271
AnnaBridge	161:aa5281ff4a02	272	uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the
AnnaBridge	161:aa5281ff4a02	273	Stop state */
AnnaBridge	161:aa5281ff4a02	274
AnnaBridge	161:aa5281ff4a02	275	}DSI_PHY_TimerTypeDef;
AnnaBridge	161:aa5281ff4a02	276
AnnaBridge	163:e59c8e839560	277	/**
AnnaBridge	161:aa5281ff4a02	278	* @brief DSI HOST Timeouts definition
AnnaBridge	161:aa5281ff4a02	279	*/
AnnaBridge	163:e59c8e839560	280	typedef struct
AnnaBridge	161:aa5281ff4a02	281	{
AnnaBridge	161:aa5281ff4a02	282	uint32_t TimeoutCkdiv; /!< Time-out clock division /
AnnaBridge	161:aa5281ff4a02	283
AnnaBridge	161:aa5281ff4a02	284	uint32_t HighSpeedTransmissionTimeout; /!< High-speed transmission time-out /
AnnaBridge	161:aa5281ff4a02	285
AnnaBridge	161:aa5281ff4a02	286	uint32_t LowPowerReceptionTimeout; /!< Low-power reception time-out /
AnnaBridge	161:aa5281ff4a02	287
AnnaBridge	161:aa5281ff4a02	288	uint32_t HighSpeedReadTimeout; /!< High-speed read time-out /
AnnaBridge	161:aa5281ff4a02	289
AnnaBridge	161:aa5281ff4a02	290	uint32_t LowPowerReadTimeout; /!< Low-power read time-out /
AnnaBridge	161:aa5281ff4a02	291
AnnaBridge	161:aa5281ff4a02	292	uint32_t HighSpeedWriteTimeout; /!< High-speed write time-out /
AnnaBridge	161:aa5281ff4a02	293
AnnaBridge	161:aa5281ff4a02	294	uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode
AnnaBridge	161:aa5281ff4a02	295	This parameter can be any value of @ref DSI_HS_PrespMode */
AnnaBridge	161:aa5281ff4a02	296
AnnaBridge	161:aa5281ff4a02	297	uint32_t LowPowerWriteTimeout; /!< Low-speed write time-out /
AnnaBridge	161:aa5281ff4a02	298
AnnaBridge	161:aa5281ff4a02	299	uint32_t BTATimeout; /!< BTA time-out /
AnnaBridge	161:aa5281ff4a02	300
AnnaBridge	161:aa5281ff4a02	301	}DSI_HOST_TimeoutTypeDef;
AnnaBridge	161:aa5281ff4a02	302
AnnaBridge	161:aa5281ff4a02	303	/**
AnnaBridge	161:aa5281ff4a02	304	* @brief DSI States Structure definition
AnnaBridge	161:aa5281ff4a02	305	*/
AnnaBridge	163:e59c8e839560	306	typedef enum
AnnaBridge	161:aa5281ff4a02	307	{
AnnaBridge	161:aa5281ff4a02	308	HAL_DSI_STATE_RESET = 0x00U,
AnnaBridge	161:aa5281ff4a02	309	HAL_DSI_STATE_READY = 0x01U,
AnnaBridge	161:aa5281ff4a02	310	HAL_DSI_STATE_ERROR = 0x02U,
AnnaBridge	161:aa5281ff4a02	311	HAL_DSI_STATE_BUSY = 0x03U,
AnnaBridge	161:aa5281ff4a02	312	HAL_DSI_STATE_TIMEOUT = 0x04U
AnnaBridge	161:aa5281ff4a02	313	}HAL_DSI_StateTypeDef;
AnnaBridge	161:aa5281ff4a02	314
AnnaBridge	161:aa5281ff4a02	315	/**
AnnaBridge	161:aa5281ff4a02	316	* @brief DSI Handle Structure definition
AnnaBridge	161:aa5281ff4a02	317	*/
AnnaBridge	161:aa5281ff4a02	318	typedef struct
AnnaBridge	161:aa5281ff4a02	319	{
AnnaBridge	161:aa5281ff4a02	320	DSI_TypeDef Instance; /!< Register base address */
AnnaBridge	161:aa5281ff4a02	321	DSI_InitTypeDef Init; /!< DSI required parameters /
AnnaBridge	161:aa5281ff4a02	322	HAL_LockTypeDef Lock; /!< DSI peripheral status /
AnnaBridge	161:aa5281ff4a02	323	__IO HAL_DSI_StateTypeDef State; /!< DSI communication state /
AnnaBridge	161:aa5281ff4a02	324	__IO uint32_t ErrorCode; /!< DSI Error code /
AnnaBridge	161:aa5281ff4a02	325	uint32_t ErrorMsk; /!< DSI Error monitoring mask /
AnnaBridge	161:aa5281ff4a02	326	}DSI_HandleTypeDef;
AnnaBridge	161:aa5281ff4a02	327
AnnaBridge	161:aa5281ff4a02	328	/* Exported constants --------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	329	/** @defgroup DSI_DCS_Command DSI DCS Command
AnnaBridge	161:aa5281ff4a02	330	* @{
AnnaBridge	161:aa5281ff4a02	331	*/
AnnaBridge	161:aa5281ff4a02	332	#define DSI_ENTER_IDLE_MODE 0x39U
AnnaBridge	161:aa5281ff4a02	333	#define DSI_ENTER_INVERT_MODE 0x21U
AnnaBridge	161:aa5281ff4a02	334	#define DSI_ENTER_NORMAL_MODE 0x13U
AnnaBridge	161:aa5281ff4a02	335	#define DSI_ENTER_PARTIAL_MODE 0x12U
AnnaBridge	161:aa5281ff4a02	336	#define DSI_ENTER_SLEEP_MODE 0x10U
AnnaBridge	161:aa5281ff4a02	337	#define DSI_EXIT_IDLE_MODE 0x38U
AnnaBridge	161:aa5281ff4a02	338	#define DSI_EXIT_INVERT_MODE 0x20U
AnnaBridge	161:aa5281ff4a02	339	#define DSI_EXIT_SLEEP_MODE 0x11U
AnnaBridge	161:aa5281ff4a02	340	#define DSI_GET_3D_CONTROL 0x3FU
AnnaBridge	161:aa5281ff4a02	341	#define DSI_GET_ADDRESS_MODE 0x0BU
AnnaBridge	161:aa5281ff4a02	342	#define DSI_GET_BLUE_CHANNEL 0x08U
AnnaBridge	161:aa5281ff4a02	343	#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU
AnnaBridge	161:aa5281ff4a02	344	#define DSI_GET_DISPLAY_MODE 0x0DU
AnnaBridge	161:aa5281ff4a02	345	#define DSI_GET_GREEN_CHANNEL 0x07U
AnnaBridge	161:aa5281ff4a02	346	#define DSI_GET_PIXEL_FORMAT 0x0CU
AnnaBridge	161:aa5281ff4a02	347	#define DSI_GET_POWER_MODE 0x0AU
AnnaBridge	161:aa5281ff4a02	348	#define DSI_GET_RED_CHANNEL 0x06U
AnnaBridge	161:aa5281ff4a02	349	#define DSI_GET_SCANLINE 0x45U
AnnaBridge	161:aa5281ff4a02	350	#define DSI_GET_SIGNAL_MODE 0x0EU
AnnaBridge	161:aa5281ff4a02	351	#define DSI_NOP 0x00U
AnnaBridge	161:aa5281ff4a02	352	#define DSI_READ_DDB_CONTINUE 0xA8U
AnnaBridge	161:aa5281ff4a02	353	#define DSI_READ_DDB_START 0xA1U
AnnaBridge	161:aa5281ff4a02	354	#define DSI_READ_MEMORY_CONTINUE 0x3EU
AnnaBridge	161:aa5281ff4a02	355	#define DSI_READ_MEMORY_START 0x2EU
AnnaBridge	161:aa5281ff4a02	356	#define DSI_SET_3D_CONTROL 0x3DU
AnnaBridge	161:aa5281ff4a02	357	#define DSI_SET_ADDRESS_MODE 0x36U
AnnaBridge	161:aa5281ff4a02	358	#define DSI_SET_COLUMN_ADDRESS 0x2AU
AnnaBridge	161:aa5281ff4a02	359	#define DSI_SET_DISPLAY_OFF 0x28U
AnnaBridge	161:aa5281ff4a02	360	#define DSI_SET_DISPLAY_ON 0x29U
AnnaBridge	161:aa5281ff4a02	361	#define DSI_SET_GAMMA_CURVE 0x26U
AnnaBridge	161:aa5281ff4a02	362	#define DSI_SET_PAGE_ADDRESS 0x2BU
AnnaBridge	161:aa5281ff4a02	363	#define DSI_SET_PARTIAL_COLUMNS 0x31U
AnnaBridge	161:aa5281ff4a02	364	#define DSI_SET_PARTIAL_ROWS 0x30U
AnnaBridge	161:aa5281ff4a02	365	#define DSI_SET_PIXEL_FORMAT 0x3AU
AnnaBridge	161:aa5281ff4a02	366	#define DSI_SET_SCROLL_AREA 0x33U
AnnaBridge	161:aa5281ff4a02	367	#define DSI_SET_SCROLL_START 0x37U
AnnaBridge	161:aa5281ff4a02	368	#define DSI_SET_TEAR_OFF 0x34U
AnnaBridge	161:aa5281ff4a02	369	#define DSI_SET_TEAR_ON 0x35U
AnnaBridge	161:aa5281ff4a02	370	#define DSI_SET_TEAR_SCANLINE 0x44U
AnnaBridge	161:aa5281ff4a02	371	#define DSI_SET_VSYNC_TIMING 0x40U
AnnaBridge	161:aa5281ff4a02	372	#define DSI_SOFT_RESET 0x01U
AnnaBridge	161:aa5281ff4a02	373	#define DSI_WRITE_LUT 0x2DU
AnnaBridge	161:aa5281ff4a02	374	#define DSI_WRITE_MEMORY_CONTINUE 0x3CU
AnnaBridge	161:aa5281ff4a02	375	#define DSI_WRITE_MEMORY_START 0x2CU
AnnaBridge	161:aa5281ff4a02	376	/**
AnnaBridge	161:aa5281ff4a02	377	* @}
AnnaBridge	161:aa5281ff4a02	378	*/
AnnaBridge	161:aa5281ff4a02	379
AnnaBridge	161:aa5281ff4a02	380	/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type
AnnaBridge	161:aa5281ff4a02	381	* @{
AnnaBridge	161:aa5281ff4a02	382	*/
AnnaBridge	161:aa5281ff4a02	383	#define DSI_VID_MODE_NB_PULSES 0U
AnnaBridge	161:aa5281ff4a02	384	#define DSI_VID_MODE_NB_EVENTS 1U
AnnaBridge	161:aa5281ff4a02	385	#define DSI_VID_MODE_BURST 2U
AnnaBridge	161:aa5281ff4a02	386	/**
AnnaBridge	161:aa5281ff4a02	387	* @}
AnnaBridge	161:aa5281ff4a02	388	*/
AnnaBridge	161:aa5281ff4a02	389
AnnaBridge	161:aa5281ff4a02	390	/** @defgroup DSI_Color_Mode DSI Color Mode
AnnaBridge	161:aa5281ff4a02	391	* @{
AnnaBridge	161:aa5281ff4a02	392	*/
AnnaBridge	161:aa5281ff4a02	393	#define DSI_COLOR_MODE_FULL 0x00000000U
AnnaBridge	161:aa5281ff4a02	394	#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM
AnnaBridge	161:aa5281ff4a02	395	/**
AnnaBridge	161:aa5281ff4a02	396	* @}
AnnaBridge	161:aa5281ff4a02	397	*/
AnnaBridge	161:aa5281ff4a02	398
AnnaBridge	161:aa5281ff4a02	399	/** @defgroup DSI_ShutDown DSI ShutDown
AnnaBridge	161:aa5281ff4a02	400	* @{
AnnaBridge	161:aa5281ff4a02	401	*/
AnnaBridge	161:aa5281ff4a02	402	#define DSI_DISPLAY_ON 0x00000000U
AnnaBridge	161:aa5281ff4a02	403	#define DSI_DISPLAY_OFF DSI_WCR_SHTDN
AnnaBridge	161:aa5281ff4a02	404	/**
AnnaBridge	161:aa5281ff4a02	405	* @}
AnnaBridge	161:aa5281ff4a02	406	*/
AnnaBridge	161:aa5281ff4a02	407
AnnaBridge	161:aa5281ff4a02	408	/** @defgroup DSI_LP_Command DSI LP Command
AnnaBridge	161:aa5281ff4a02	409	* @{
AnnaBridge	161:aa5281ff4a02	410	*/
AnnaBridge	161:aa5281ff4a02	411	#define DSI_LP_COMMAND_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	412	#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE
AnnaBridge	161:aa5281ff4a02	413	/**
AnnaBridge	161:aa5281ff4a02	414	* @}
AnnaBridge	161:aa5281ff4a02	415	*/
AnnaBridge	161:aa5281ff4a02	416
AnnaBridge	161:aa5281ff4a02	417	/** @defgroup DSI_LP_HFP DSI LP HFP
AnnaBridge	161:aa5281ff4a02	418	* @{
AnnaBridge	161:aa5281ff4a02	419	*/
AnnaBridge	161:aa5281ff4a02	420	#define DSI_LP_HFP_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	421	#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE
AnnaBridge	161:aa5281ff4a02	422	/**
AnnaBridge	161:aa5281ff4a02	423	* @}
AnnaBridge	161:aa5281ff4a02	424	*/
AnnaBridge	161:aa5281ff4a02	425
AnnaBridge	161:aa5281ff4a02	426	/** @defgroup DSI_LP_HBP DSI LP HBP
AnnaBridge	161:aa5281ff4a02	427	* @{
AnnaBridge	161:aa5281ff4a02	428	*/
AnnaBridge	161:aa5281ff4a02	429	#define DSI_LP_HBP_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	430	#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE
AnnaBridge	161:aa5281ff4a02	431	/**
AnnaBridge	161:aa5281ff4a02	432	* @}
AnnaBridge	161:aa5281ff4a02	433	*/
AnnaBridge	161:aa5281ff4a02	434
AnnaBridge	161:aa5281ff4a02	435	/** @defgroup DSI_LP_VACT DSI LP VACT
AnnaBridge	161:aa5281ff4a02	436	* @{
AnnaBridge	161:aa5281ff4a02	437	*/
AnnaBridge	161:aa5281ff4a02	438	#define DSI_LP_VACT_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	439	#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE
AnnaBridge	161:aa5281ff4a02	440	/**
AnnaBridge	161:aa5281ff4a02	441	* @}
AnnaBridge	161:aa5281ff4a02	442	*/
AnnaBridge	161:aa5281ff4a02	443
AnnaBridge	161:aa5281ff4a02	444	/** @defgroup DSI_LP_VFP DSI LP VFP
AnnaBridge	161:aa5281ff4a02	445	* @{
AnnaBridge	161:aa5281ff4a02	446	*/
AnnaBridge	161:aa5281ff4a02	447	#define DSI_LP_VFP_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	448	#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE
AnnaBridge	161:aa5281ff4a02	449	/**
AnnaBridge	161:aa5281ff4a02	450	* @}
AnnaBridge	161:aa5281ff4a02	451	*/
AnnaBridge	161:aa5281ff4a02	452
AnnaBridge	161:aa5281ff4a02	453	/** @defgroup DSI_LP_VBP DSI LP VBP
AnnaBridge	161:aa5281ff4a02	454	* @{
AnnaBridge	161:aa5281ff4a02	455	*/
AnnaBridge	161:aa5281ff4a02	456	#define DSI_LP_VBP_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	457	#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE
AnnaBridge	161:aa5281ff4a02	458	/**
AnnaBridge	161:aa5281ff4a02	459	* @}
AnnaBridge	161:aa5281ff4a02	460	*/
AnnaBridge	161:aa5281ff4a02	461
AnnaBridge	161:aa5281ff4a02	462	/** @defgroup DSI_LP_VSYNC DSI LP VSYNC
AnnaBridge	161:aa5281ff4a02	463	* @{
AnnaBridge	161:aa5281ff4a02	464	*/
AnnaBridge	161:aa5281ff4a02	465	#define DSI_LP_VSYNC_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	466	#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE
AnnaBridge	161:aa5281ff4a02	467	/**
AnnaBridge	161:aa5281ff4a02	468	* @}
AnnaBridge	161:aa5281ff4a02	469	*/
AnnaBridge	161:aa5281ff4a02	470
AnnaBridge	161:aa5281ff4a02	471	/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge
AnnaBridge	161:aa5281ff4a02	472	* @{
AnnaBridge	161:aa5281ff4a02	473	*/
AnnaBridge	161:aa5281ff4a02	474	#define DSI_FBTAA_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	475	#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE
AnnaBridge	161:aa5281ff4a02	476	/**
AnnaBridge	161:aa5281ff4a02	477	* @}
AnnaBridge	161:aa5281ff4a02	478	*/
AnnaBridge	161:aa5281ff4a02	479
AnnaBridge	161:aa5281ff4a02	480	/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source
AnnaBridge	161:aa5281ff4a02	481	* @{
AnnaBridge	161:aa5281ff4a02	482	*/
AnnaBridge	161:aa5281ff4a02	483	#define DSI_TE_DSILINK 0x00000000U
AnnaBridge	161:aa5281ff4a02	484	#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC
AnnaBridge	161:aa5281ff4a02	485	/**
AnnaBridge	161:aa5281ff4a02	486	* @}
AnnaBridge	161:aa5281ff4a02	487	*/
AnnaBridge	161:aa5281ff4a02	488
AnnaBridge	161:aa5281ff4a02	489	/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity
AnnaBridge	161:aa5281ff4a02	490	* @{
AnnaBridge	161:aa5281ff4a02	491	*/
AnnaBridge	161:aa5281ff4a02	492	#define DSI_TE_RISING_EDGE 0x00000000U
AnnaBridge	161:aa5281ff4a02	493	#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL
AnnaBridge	161:aa5281ff4a02	494	/**
AnnaBridge	161:aa5281ff4a02	495	* @}
AnnaBridge	161:aa5281ff4a02	496	*/
AnnaBridge	161:aa5281ff4a02	497
AnnaBridge	161:aa5281ff4a02	498	/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity
AnnaBridge	161:aa5281ff4a02	499	* @{
AnnaBridge	161:aa5281ff4a02	500	*/
AnnaBridge	161:aa5281ff4a02	501	#define DSI_VSYNC_FALLING 0x00000000U
AnnaBridge	161:aa5281ff4a02	502	#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL
AnnaBridge	161:aa5281ff4a02	503	/**
AnnaBridge	161:aa5281ff4a02	504	* @}
AnnaBridge	161:aa5281ff4a02	505	*/
AnnaBridge	161:aa5281ff4a02	506
AnnaBridge	161:aa5281ff4a02	507	/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh
AnnaBridge	161:aa5281ff4a02	508	* @{
AnnaBridge	161:aa5281ff4a02	509	*/
AnnaBridge	161:aa5281ff4a02	510	#define DSI_AR_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	511	#define DSI_AR_ENABLE DSI_WCFGR_AR
AnnaBridge	161:aa5281ff4a02	512	/**
AnnaBridge	161:aa5281ff4a02	513	* @}
AnnaBridge	161:aa5281ff4a02	514	*/
AnnaBridge	161:aa5281ff4a02	515
AnnaBridge	161:aa5281ff4a02	516	/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request
AnnaBridge	161:aa5281ff4a02	517	* @{
AnnaBridge	161:aa5281ff4a02	518	*/
AnnaBridge	161:aa5281ff4a02	519	#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	520	#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE
AnnaBridge	161:aa5281ff4a02	521	/**
AnnaBridge	161:aa5281ff4a02	522	* @}
AnnaBridge	161:aa5281ff4a02	523	*/
AnnaBridge	161:aa5281ff4a02	524
AnnaBridge	161:aa5281ff4a02	525	/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request
AnnaBridge	161:aa5281ff4a02	526	* @{
AnnaBridge	161:aa5281ff4a02	527	*/
AnnaBridge	161:aa5281ff4a02	528	#define DSI_ACKNOWLEDGE_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	529	#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE
AnnaBridge	161:aa5281ff4a02	530	/**
AnnaBridge	161:aa5281ff4a02	531	* @}
AnnaBridge	161:aa5281ff4a02	532	*/
AnnaBridge	161:aa5281ff4a02	533
AnnaBridge	161:aa5281ff4a02	534	/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP
AnnaBridge	161:aa5281ff4a02	535	* @{
AnnaBridge	161:aa5281ff4a02	536	*/
AnnaBridge	161:aa5281ff4a02	537	#define DSI_LP_GSW0P_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	538	#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX
AnnaBridge	161:aa5281ff4a02	539	/**
AnnaBridge	161:aa5281ff4a02	540	* @}
AnnaBridge	161:aa5281ff4a02	541	*/
AnnaBridge	161:aa5281ff4a02	542
AnnaBridge	161:aa5281ff4a02	543	/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP
AnnaBridge	161:aa5281ff4a02	544	* @{
AnnaBridge	161:aa5281ff4a02	545	*/
AnnaBridge	161:aa5281ff4a02	546	#define DSI_LP_GSW1P_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	547	#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX
AnnaBridge	161:aa5281ff4a02	548	/**
AnnaBridge	161:aa5281ff4a02	549	* @}
AnnaBridge	161:aa5281ff4a02	550	*/
AnnaBridge	161:aa5281ff4a02	551
AnnaBridge	161:aa5281ff4a02	552	/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP
AnnaBridge	161:aa5281ff4a02	553	* @{
AnnaBridge	161:aa5281ff4a02	554	*/
AnnaBridge	161:aa5281ff4a02	555	#define DSI_LP_GSW2P_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	556	#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX
AnnaBridge	161:aa5281ff4a02	557	/**
AnnaBridge	161:aa5281ff4a02	558	* @}
AnnaBridge	161:aa5281ff4a02	559	*/
AnnaBridge	161:aa5281ff4a02	560
AnnaBridge	161:aa5281ff4a02	561	/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP
AnnaBridge	161:aa5281ff4a02	562	* @{
AnnaBridge	161:aa5281ff4a02	563	*/
AnnaBridge	161:aa5281ff4a02	564	#define DSI_LP_GSR0P_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	565	#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX
AnnaBridge	161:aa5281ff4a02	566	/**
AnnaBridge	161:aa5281ff4a02	567	* @}
AnnaBridge	161:aa5281ff4a02	568	*/
AnnaBridge	161:aa5281ff4a02	569
AnnaBridge	161:aa5281ff4a02	570	/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP
AnnaBridge	161:aa5281ff4a02	571	* @{
AnnaBridge	161:aa5281ff4a02	572	*/
AnnaBridge	161:aa5281ff4a02	573	#define DSI_LP_GSR1P_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	574	#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX
AnnaBridge	161:aa5281ff4a02	575	/**
AnnaBridge	161:aa5281ff4a02	576	* @}
AnnaBridge	161:aa5281ff4a02	577	*/
AnnaBridge	161:aa5281ff4a02	578
AnnaBridge	161:aa5281ff4a02	579	/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP
AnnaBridge	161:aa5281ff4a02	580	* @{
AnnaBridge	161:aa5281ff4a02	581	*/
AnnaBridge	161:aa5281ff4a02	582	#define DSI_LP_GSR2P_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	583	#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX
AnnaBridge	161:aa5281ff4a02	584	/**
AnnaBridge	161:aa5281ff4a02	585	* @}
AnnaBridge	161:aa5281ff4a02	586	*/
AnnaBridge	161:aa5281ff4a02	587
AnnaBridge	161:aa5281ff4a02	588	/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite
AnnaBridge	161:aa5281ff4a02	589	* @{
AnnaBridge	161:aa5281ff4a02	590	*/
AnnaBridge	161:aa5281ff4a02	591	#define DSI_LP_GLW_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	592	#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX
AnnaBridge	161:aa5281ff4a02	593	/**
AnnaBridge	161:aa5281ff4a02	594	* @}
AnnaBridge	161:aa5281ff4a02	595	*/
AnnaBridge	161:aa5281ff4a02	596
AnnaBridge	161:aa5281ff4a02	597	/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP
AnnaBridge	161:aa5281ff4a02	598	* @{
AnnaBridge	161:aa5281ff4a02	599	*/
AnnaBridge	161:aa5281ff4a02	600	#define DSI_LP_DSW0P_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	601	#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX
AnnaBridge	161:aa5281ff4a02	602	/**
AnnaBridge	161:aa5281ff4a02	603	* @}
AnnaBridge	161:aa5281ff4a02	604	*/
AnnaBridge	161:aa5281ff4a02	605
AnnaBridge	161:aa5281ff4a02	606	/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP
AnnaBridge	161:aa5281ff4a02	607	* @{
AnnaBridge	161:aa5281ff4a02	608	*/
AnnaBridge	161:aa5281ff4a02	609	#define DSI_LP_DSW1P_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	610	#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX
AnnaBridge	161:aa5281ff4a02	611	/**
AnnaBridge	161:aa5281ff4a02	612	* @}
AnnaBridge	161:aa5281ff4a02	613	*/
AnnaBridge	161:aa5281ff4a02	614
AnnaBridge	161:aa5281ff4a02	615	/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP
AnnaBridge	161:aa5281ff4a02	616	* @{
AnnaBridge	161:aa5281ff4a02	617	*/
AnnaBridge	161:aa5281ff4a02	618	#define DSI_LP_DSR0P_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	619	#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX
AnnaBridge	161:aa5281ff4a02	620	/**
AnnaBridge	161:aa5281ff4a02	621	* @}
AnnaBridge	161:aa5281ff4a02	622	*/
AnnaBridge	161:aa5281ff4a02	623
AnnaBridge	161:aa5281ff4a02	624	/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write
AnnaBridge	161:aa5281ff4a02	625	* @{
AnnaBridge	161:aa5281ff4a02	626	*/
AnnaBridge	161:aa5281ff4a02	627	#define DSI_LP_DLW_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	628	#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX
AnnaBridge	161:aa5281ff4a02	629	/**
AnnaBridge	161:aa5281ff4a02	630	* @}
AnnaBridge	161:aa5281ff4a02	631	*/
AnnaBridge	161:aa5281ff4a02	632
AnnaBridge	161:aa5281ff4a02	633	/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet
AnnaBridge	161:aa5281ff4a02	634	* @{
AnnaBridge	161:aa5281ff4a02	635	*/
AnnaBridge	161:aa5281ff4a02	636	#define DSI_LP_MRDP_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	637	#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS
AnnaBridge	161:aa5281ff4a02	638	/**
AnnaBridge	161:aa5281ff4a02	639	* @}
AnnaBridge	161:aa5281ff4a02	640	*/
AnnaBridge	161:aa5281ff4a02	641
AnnaBridge	161:aa5281ff4a02	642	/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode
AnnaBridge	161:aa5281ff4a02	643	* @{
AnnaBridge	161:aa5281ff4a02	644	*/
AnnaBridge	161:aa5281ff4a02	645	#define DSI_HS_PM_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	646	#define DSI_HS_PM_ENABLE DSI_TCCR3_PM
AnnaBridge	161:aa5281ff4a02	647	/**
AnnaBridge	161:aa5281ff4a02	648	* @}
AnnaBridge	161:aa5281ff4a02	649	*/
AnnaBridge	161:aa5281ff4a02	650
AnnaBridge	161:aa5281ff4a02	651
AnnaBridge	161:aa5281ff4a02	652	/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control
AnnaBridge	161:aa5281ff4a02	653	* @{
AnnaBridge	161:aa5281ff4a02	654	*/
AnnaBridge	161:aa5281ff4a02	655	#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	656	#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR
AnnaBridge	161:aa5281ff4a02	657	/**
AnnaBridge	161:aa5281ff4a02	658	* @}
AnnaBridge	161:aa5281ff4a02	659	*/
AnnaBridge	161:aa5281ff4a02	660
AnnaBridge	161:aa5281ff4a02	661	/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes
AnnaBridge	161:aa5281ff4a02	662	* @{
AnnaBridge	161:aa5281ff4a02	663	*/
AnnaBridge	161:aa5281ff4a02	664	#define DSI_ONE_DATA_LANE 0U
AnnaBridge	161:aa5281ff4a02	665	#define DSI_TWO_DATA_LANES 1U
AnnaBridge	161:aa5281ff4a02	666	/**
AnnaBridge	161:aa5281ff4a02	667	* @}
AnnaBridge	161:aa5281ff4a02	668	*/
AnnaBridge	161:aa5281ff4a02	669
AnnaBridge	161:aa5281ff4a02	670	/** @defgroup DSI_FlowControl DSI Flow Control
AnnaBridge	161:aa5281ff4a02	671	* @{
AnnaBridge	161:aa5281ff4a02	672	*/
AnnaBridge	161:aa5281ff4a02	673	#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE
AnnaBridge	161:aa5281ff4a02	674	#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE
AnnaBridge	161:aa5281ff4a02	675	#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE
AnnaBridge	161:aa5281ff4a02	676	#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE
AnnaBridge	161:aa5281ff4a02	677	#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE
AnnaBridge	161:aa5281ff4a02	678	#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX \| DSI_FLOW_CONTROL_ECC_RX \| \
AnnaBridge	161:aa5281ff4a02	679	DSI_FLOW_CONTROL_BTA \| DSI_FLOW_CONTROL_EOTP_RX \| \
AnnaBridge	161:aa5281ff4a02	680	DSI_FLOW_CONTROL_EOTP_TX)
AnnaBridge	161:aa5281ff4a02	681	/**
AnnaBridge	161:aa5281ff4a02	682	* @}
AnnaBridge	161:aa5281ff4a02	683	*/
AnnaBridge	161:aa5281ff4a02	684
AnnaBridge	161:aa5281ff4a02	685	/** @defgroup DSI_Color_Coding DSI Color Coding
AnnaBridge	161:aa5281ff4a02	686	* @{
AnnaBridge	161:aa5281ff4a02	687	*/
AnnaBridge	161:aa5281ff4a02	688	#define DSI_RGB565 0x00000000U /!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration /
AnnaBridge	161:aa5281ff4a02	689	#define DSI_RGB666 0x00000003U /!< The value 0x00000004 can also be used for the RGB666 color mode configuration /
AnnaBridge	161:aa5281ff4a02	690	#define DSI_RGB888 0x00000005U
AnnaBridge	161:aa5281ff4a02	691	/**
AnnaBridge	161:aa5281ff4a02	692	* @}
AnnaBridge	161:aa5281ff4a02	693	*/
AnnaBridge	161:aa5281ff4a02	694
AnnaBridge	161:aa5281ff4a02	695	/** @defgroup DSI_LooselyPacked DSI Loosely Packed
AnnaBridge	161:aa5281ff4a02	696	* @{
AnnaBridge	161:aa5281ff4a02	697	*/
AnnaBridge	161:aa5281ff4a02	698	#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE
AnnaBridge	161:aa5281ff4a02	699	#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U
AnnaBridge	161:aa5281ff4a02	700	/**
AnnaBridge	161:aa5281ff4a02	701	* @}
AnnaBridge	161:aa5281ff4a02	702	*/
AnnaBridge	161:aa5281ff4a02	703
AnnaBridge	161:aa5281ff4a02	704	/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity
AnnaBridge	161:aa5281ff4a02	705	* @{
AnnaBridge	161:aa5281ff4a02	706	*/
AnnaBridge	161:aa5281ff4a02	707	#define DSI_HSYNC_ACTIVE_HIGH 0x00000000U
AnnaBridge	161:aa5281ff4a02	708	#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP
AnnaBridge	161:aa5281ff4a02	709	/**
AnnaBridge	161:aa5281ff4a02	710	* @}
AnnaBridge	161:aa5281ff4a02	711	*/
AnnaBridge	161:aa5281ff4a02	712
AnnaBridge	161:aa5281ff4a02	713	/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity
AnnaBridge	161:aa5281ff4a02	714	* @{
AnnaBridge	161:aa5281ff4a02	715	*/
AnnaBridge	161:aa5281ff4a02	716	#define DSI_VSYNC_ACTIVE_HIGH 0x00000000U
AnnaBridge	161:aa5281ff4a02	717	#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP
AnnaBridge	161:aa5281ff4a02	718	/**
AnnaBridge	161:aa5281ff4a02	719	* @}
AnnaBridge	161:aa5281ff4a02	720	*/
AnnaBridge	161:aa5281ff4a02	721
AnnaBridge	161:aa5281ff4a02	722	/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity
AnnaBridge	161:aa5281ff4a02	723	* @{
AnnaBridge	161:aa5281ff4a02	724	*/
AnnaBridge	161:aa5281ff4a02	725	#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U
AnnaBridge	161:aa5281ff4a02	726	#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP
AnnaBridge	161:aa5281ff4a02	727	/**
AnnaBridge	161:aa5281ff4a02	728	* @}
AnnaBridge	161:aa5281ff4a02	729	*/
AnnaBridge	161:aa5281ff4a02	730
AnnaBridge	161:aa5281ff4a02	731	/** @defgroup DSI_PLL_IDF DSI PLL IDF
AnnaBridge	161:aa5281ff4a02	732	* @{
AnnaBridge	161:aa5281ff4a02	733	*/
AnnaBridge	161:aa5281ff4a02	734	#define DSI_PLL_IN_DIV1 0x00000001U
AnnaBridge	161:aa5281ff4a02	735	#define DSI_PLL_IN_DIV2 0x00000002U
AnnaBridge	161:aa5281ff4a02	736	#define DSI_PLL_IN_DIV3 0x00000003U
AnnaBridge	161:aa5281ff4a02	737	#define DSI_PLL_IN_DIV4 0x00000004U
AnnaBridge	161:aa5281ff4a02	738	#define DSI_PLL_IN_DIV5 0x00000005U
AnnaBridge	161:aa5281ff4a02	739	#define DSI_PLL_IN_DIV6 0x00000006U
AnnaBridge	161:aa5281ff4a02	740	#define DSI_PLL_IN_DIV7 0x00000007U
AnnaBridge	161:aa5281ff4a02	741	/**
AnnaBridge	161:aa5281ff4a02	742	* @}
AnnaBridge	161:aa5281ff4a02	743	*/
AnnaBridge	161:aa5281ff4a02	744
AnnaBridge	161:aa5281ff4a02	745	/** @defgroup DSI_PLL_ODF DSI PLL ODF
AnnaBridge	161:aa5281ff4a02	746	* @{
AnnaBridge	161:aa5281ff4a02	747	*/
AnnaBridge	161:aa5281ff4a02	748	#define DSI_PLL_OUT_DIV1 0x00000000U
AnnaBridge	161:aa5281ff4a02	749	#define DSI_PLL_OUT_DIV2 0x00000001U
AnnaBridge	161:aa5281ff4a02	750	#define DSI_PLL_OUT_DIV4 0x00000002U
AnnaBridge	161:aa5281ff4a02	751	#define DSI_PLL_OUT_DIV8 0x00000003U
AnnaBridge	161:aa5281ff4a02	752	/**
AnnaBridge	161:aa5281ff4a02	753	* @}
AnnaBridge	161:aa5281ff4a02	754	*/
AnnaBridge	161:aa5281ff4a02	755
AnnaBridge	161:aa5281ff4a02	756	/** @defgroup DSI_Flags DSI Flags
AnnaBridge	161:aa5281ff4a02	757	* @{
AnnaBridge	161:aa5281ff4a02	758	*/
AnnaBridge	161:aa5281ff4a02	759	#define DSI_FLAG_TE DSI_WISR_TEIF
AnnaBridge	161:aa5281ff4a02	760	#define DSI_FLAG_ER DSI_WISR_ERIF
AnnaBridge	161:aa5281ff4a02	761	#define DSI_FLAG_BUSY DSI_WISR_BUSY
AnnaBridge	161:aa5281ff4a02	762	#define DSI_FLAG_PLLLS DSI_WISR_PLLLS
AnnaBridge	161:aa5281ff4a02	763	#define DSI_FLAG_PLLL DSI_WISR_PLLLIF
AnnaBridge	161:aa5281ff4a02	764	#define DSI_FLAG_PLLU DSI_WISR_PLLUIF
AnnaBridge	161:aa5281ff4a02	765	#define DSI_FLAG_RRS DSI_WISR_RRS
AnnaBridge	161:aa5281ff4a02	766	#define DSI_FLAG_RR DSI_WISR_RRIF
AnnaBridge	161:aa5281ff4a02	767	/**
AnnaBridge	161:aa5281ff4a02	768	* @}
AnnaBridge	161:aa5281ff4a02	769	*/
AnnaBridge	161:aa5281ff4a02	770
AnnaBridge	161:aa5281ff4a02	771	/** @defgroup DSI_Interrupts DSI Interrupts
AnnaBridge	161:aa5281ff4a02	772	* @{
AnnaBridge	161:aa5281ff4a02	773	*/
AnnaBridge	161:aa5281ff4a02	774	#define DSI_IT_TE DSI_WIER_TEIE
AnnaBridge	161:aa5281ff4a02	775	#define DSI_IT_ER DSI_WIER_ERIE
AnnaBridge	161:aa5281ff4a02	776	#define DSI_IT_PLLL DSI_WIER_PLLLIE
AnnaBridge	161:aa5281ff4a02	777	#define DSI_IT_PLLU DSI_WIER_PLLUIE
AnnaBridge	161:aa5281ff4a02	778	#define DSI_IT_RR DSI_WIER_RRIE
AnnaBridge	161:aa5281ff4a02	779	/**
AnnaBridge	161:aa5281ff4a02	780	* @}
AnnaBridge	161:aa5281ff4a02	781	*/
AnnaBridge	161:aa5281ff4a02	782
AnnaBridge	161:aa5281ff4a02	783	/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type
AnnaBridge	161:aa5281ff4a02	784	* @{
AnnaBridge	161:aa5281ff4a02	785	*/
AnnaBridge	161:aa5281ff4a02	786	#define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /!< DCS short write, no parameters /
AnnaBridge	161:aa5281ff4a02	787	#define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /!< DCS short write, one parameter /
AnnaBridge	161:aa5281ff4a02	788	#define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /!< Generic short write, no parameters /
AnnaBridge	161:aa5281ff4a02	789	#define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /!< Generic short write, one parameter /
AnnaBridge	161:aa5281ff4a02	790	#define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /!< Generic short write, two parameters /
AnnaBridge	161:aa5281ff4a02	791	/**
AnnaBridge	161:aa5281ff4a02	792	* @}
AnnaBridge	161:aa5281ff4a02	793	*/
AnnaBridge	161:aa5281ff4a02	794
AnnaBridge	161:aa5281ff4a02	795	/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type
AnnaBridge	161:aa5281ff4a02	796	* @{
AnnaBridge	161:aa5281ff4a02	797	*/
AnnaBridge	161:aa5281ff4a02	798	#define DSI_DCS_LONG_PKT_WRITE 0x00000039U /!< DCS long write /
AnnaBridge	161:aa5281ff4a02	799	#define DSI_GEN_LONG_PKT_WRITE 0x00000029U /!< Generic long write /
AnnaBridge	161:aa5281ff4a02	800	/**
AnnaBridge	161:aa5281ff4a02	801	* @}
AnnaBridge	161:aa5281ff4a02	802	*/
AnnaBridge	161:aa5281ff4a02	803
AnnaBridge	161:aa5281ff4a02	804	/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type
AnnaBridge	161:aa5281ff4a02	805	* @{
AnnaBridge	161:aa5281ff4a02	806	*/
AnnaBridge	161:aa5281ff4a02	807	#define DSI_DCS_SHORT_PKT_READ 0x00000006U /!< DCS short read /
AnnaBridge	161:aa5281ff4a02	808	#define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /!< Generic short read, no parameters /
AnnaBridge	161:aa5281ff4a02	809	#define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /!< Generic short read, one parameter /
AnnaBridge	161:aa5281ff4a02	810	#define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /!< Generic short read, two parameters /
AnnaBridge	161:aa5281ff4a02	811	/**
AnnaBridge	161:aa5281ff4a02	812	* @}
AnnaBridge	161:aa5281ff4a02	813	*/
AnnaBridge	161:aa5281ff4a02	814
AnnaBridge	161:aa5281ff4a02	815	/** @defgroup DSI_Error_Data_Type DSI Error Data Type
AnnaBridge	161:aa5281ff4a02	816	* @{
AnnaBridge	161:aa5281ff4a02	817	*/
AnnaBridge	161:aa5281ff4a02	818	#define HAL_DSI_ERROR_NONE 0U
AnnaBridge	161:aa5281ff4a02	819	#define HAL_DSI_ERROR_ACK 0x00000001U /!< acknowledge errors /
AnnaBridge	161:aa5281ff4a02	820	#define HAL_DSI_ERROR_PHY 0x00000002U /!< PHY related errors /
AnnaBridge	161:aa5281ff4a02	821	#define HAL_DSI_ERROR_TX 0x00000004U /!< transmission error /
AnnaBridge	161:aa5281ff4a02	822	#define HAL_DSI_ERROR_RX 0x00000008U /!< reception error /
AnnaBridge	161:aa5281ff4a02	823	#define HAL_DSI_ERROR_ECC 0x00000010U /!< ECC errors /
AnnaBridge	161:aa5281ff4a02	824	#define HAL_DSI_ERROR_CRC 0x00000020U /!< CRC error /
AnnaBridge	161:aa5281ff4a02	825	#define HAL_DSI_ERROR_PSE 0x00000040U /!< Packet Size error /
AnnaBridge	161:aa5281ff4a02	826	#define HAL_DSI_ERROR_EOT 0x00000080U /!< End Of Transmission error /
AnnaBridge	161:aa5281ff4a02	827	#define HAL_DSI_ERROR_OVF 0x00000100U /!< FIFO overflow error /
AnnaBridge	161:aa5281ff4a02	828	#define HAL_DSI_ERROR_GEN 0x00000200U /!< Generic FIFO related errors /
AnnaBridge	161:aa5281ff4a02	829	/**
AnnaBridge	161:aa5281ff4a02	830	* @}
AnnaBridge	161:aa5281ff4a02	831	*/
AnnaBridge	161:aa5281ff4a02	832
AnnaBridge	161:aa5281ff4a02	833	/** @defgroup DSI_Lane_Group DSI Lane Group
AnnaBridge	161:aa5281ff4a02	834	* @{
AnnaBridge	161:aa5281ff4a02	835	*/
AnnaBridge	161:aa5281ff4a02	836	#define DSI_CLOCK_LANE 0x00000000U
AnnaBridge	161:aa5281ff4a02	837	#define DSI_DATA_LANES 0x00000001U
AnnaBridge	161:aa5281ff4a02	838	/**
AnnaBridge	161:aa5281ff4a02	839	* @}
AnnaBridge	161:aa5281ff4a02	840	*/
AnnaBridge	161:aa5281ff4a02	841
AnnaBridge	161:aa5281ff4a02	842	/** @defgroup DSI_Communication_Delay DSI Communication Delay
AnnaBridge	161:aa5281ff4a02	843	* @{
AnnaBridge	161:aa5281ff4a02	844	*/
AnnaBridge	161:aa5281ff4a02	845	#define DSI_SLEW_RATE_HSTX 0x00000000U
AnnaBridge	161:aa5281ff4a02	846	#define DSI_SLEW_RATE_LPTX 0x00000001U
AnnaBridge	161:aa5281ff4a02	847	#define DSI_HS_DELAY 0x00000002U
AnnaBridge	161:aa5281ff4a02	848	/**
AnnaBridge	161:aa5281ff4a02	849	* @}
AnnaBridge	161:aa5281ff4a02	850	*/
AnnaBridge	161:aa5281ff4a02	851
AnnaBridge	161:aa5281ff4a02	852	/** @defgroup DSI_CustomLane DSI CustomLane
AnnaBridge	161:aa5281ff4a02	853	* @{
AnnaBridge	161:aa5281ff4a02	854	*/
AnnaBridge	161:aa5281ff4a02	855	#define DSI_SWAP_LANE_PINS 0x00000000U
AnnaBridge	161:aa5281ff4a02	856	#define DSI_INVERT_HS_SIGNAL 0x00000001U
AnnaBridge	161:aa5281ff4a02	857	/**
AnnaBridge	161:aa5281ff4a02	858	* @}
AnnaBridge	161:aa5281ff4a02	859	*/
AnnaBridge	161:aa5281ff4a02	860
AnnaBridge	161:aa5281ff4a02	861	/** @defgroup DSI_Lane_Select DSI Lane Select
AnnaBridge	161:aa5281ff4a02	862	* @{
AnnaBridge	161:aa5281ff4a02	863	*/
AnnaBridge	163:e59c8e839560	864	#define DSI_CLK_LANE 0x00000000U
AnnaBridge	161:aa5281ff4a02	865	#define DSI_DATA_LANE0 0x00000001U
AnnaBridge	161:aa5281ff4a02	866	#define DSI_DATA_LANE1 0x00000002U
AnnaBridge	161:aa5281ff4a02	867	/**
AnnaBridge	161:aa5281ff4a02	868	* @}
AnnaBridge	161:aa5281ff4a02	869	*/
AnnaBridge	161:aa5281ff4a02	870
AnnaBridge	161:aa5281ff4a02	871	/** @defgroup DSI_PHY_Timing DSI PHY Timing
AnnaBridge	161:aa5281ff4a02	872	* @{
AnnaBridge	161:aa5281ff4a02	873	*/
AnnaBridge	161:aa5281ff4a02	874	#define DSI_TCLK_POST 0x00000000U
AnnaBridge	161:aa5281ff4a02	875	#define DSI_TLPX_CLK 0x00000001U
AnnaBridge	161:aa5281ff4a02	876	#define DSI_THS_EXIT 0x00000002U
AnnaBridge	161:aa5281ff4a02	877	#define DSI_TLPX_DATA 0x00000003U
AnnaBridge	161:aa5281ff4a02	878	#define DSI_THS_ZERO 0x00000004U
AnnaBridge	161:aa5281ff4a02	879	#define DSI_THS_TRAIL 0x00000005U
AnnaBridge	161:aa5281ff4a02	880	#define DSI_THS_PREPARE 0x00000006U
AnnaBridge	161:aa5281ff4a02	881	#define DSI_TCLK_ZERO 0x00000007U
AnnaBridge	161:aa5281ff4a02	882	#define DSI_TCLK_PREPARE 0x00000008U
AnnaBridge	161:aa5281ff4a02	883	/**
AnnaBridge	161:aa5281ff4a02	884	* @}
AnnaBridge	161:aa5281ff4a02	885	*/
AnnaBridge	161:aa5281ff4a02	886
AnnaBridge	161:aa5281ff4a02	887	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	888	/**
AnnaBridge	161:aa5281ff4a02	889	* @brief Enables the DSI host.
AnnaBridge	163:e59c8e839560	890	* @param __HANDLE__ DSI handle
AnnaBridge	161:aa5281ff4a02	891	* @retval None.
AnnaBridge	161:aa5281ff4a02	892	*/
AnnaBridge	163:e59c8e839560	893	#define __HAL_DSI_ENABLE(__HANDLE__) do { \
AnnaBridge	163:e59c8e839560	894	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	895	SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
AnnaBridge	163:e59c8e839560	896	/* Delay after an DSI Host enabling */ \
AnnaBridge	163:e59c8e839560	897	tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
AnnaBridge	163:e59c8e839560	898	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	899	}while(0U)
AnnaBridge	161:aa5281ff4a02	900
AnnaBridge	161:aa5281ff4a02	901	/**
AnnaBridge	161:aa5281ff4a02	902	* @brief Disables the DSI host.
AnnaBridge	163:e59c8e839560	903	* @param __HANDLE__ DSI handle
AnnaBridge	161:aa5281ff4a02	904	* @retval None.
AnnaBridge	161:aa5281ff4a02	905	*/
AnnaBridge	163:e59c8e839560	906	#define __HAL_DSI_DISABLE(__HANDLE__) do { \
AnnaBridge	163:e59c8e839560	907	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	908	CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
AnnaBridge	163:e59c8e839560	909	/* Delay after an DSI Host disabling */ \
AnnaBridge	163:e59c8e839560	910	tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
AnnaBridge	163:e59c8e839560	911	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	912	}while(0U)
AnnaBridge	161:aa5281ff4a02	913
AnnaBridge	161:aa5281ff4a02	914	/**
AnnaBridge	161:aa5281ff4a02	915	* @brief Enables the DSI wrapper.
AnnaBridge	163:e59c8e839560	916	* @param __HANDLE__ DSI handle
AnnaBridge	161:aa5281ff4a02	917	* @retval None.
AnnaBridge	161:aa5281ff4a02	918	*/
AnnaBridge	163:e59c8e839560	919	#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
AnnaBridge	163:e59c8e839560	920	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	921	SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
AnnaBridge	163:e59c8e839560	922	/* Delay after an DSI warpper enabling */ \
AnnaBridge	163:e59c8e839560	923	tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
AnnaBridge	163:e59c8e839560	924	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	925	}while(0U)
AnnaBridge	161:aa5281ff4a02	926
AnnaBridge	161:aa5281ff4a02	927	/**
AnnaBridge	161:aa5281ff4a02	928	* @brief Disable the DSI wrapper.
AnnaBridge	163:e59c8e839560	929	* @param __HANDLE__ DSI handle
AnnaBridge	161:aa5281ff4a02	930	* @retval None.
AnnaBridge	161:aa5281ff4a02	931	*/
AnnaBridge	163:e59c8e839560	932	#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
AnnaBridge	163:e59c8e839560	933	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	934	CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
AnnaBridge	163:e59c8e839560	935	/* Delay after an DSI warpper disabling*/ \
AnnaBridge	163:e59c8e839560	936	tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
AnnaBridge	163:e59c8e839560	937	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	938	}while(0U)
AnnaBridge	161:aa5281ff4a02	939
AnnaBridge	161:aa5281ff4a02	940	/**
AnnaBridge	161:aa5281ff4a02	941	* @brief Enables the DSI PLL.
AnnaBridge	163:e59c8e839560	942	* @param __HANDLE__ DSI handle
AnnaBridge	161:aa5281ff4a02	943	* @retval None.
AnnaBridge	161:aa5281ff4a02	944	*/
AnnaBridge	163:e59c8e839560	945	#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
AnnaBridge	163:e59c8e839560	946	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	947	SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
AnnaBridge	163:e59c8e839560	948	/* Delay after an DSI PLL enabling */ \
AnnaBridge	163:e59c8e839560	949	tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
AnnaBridge	163:e59c8e839560	950	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	951	}while(0U)
AnnaBridge	161:aa5281ff4a02	952
AnnaBridge	161:aa5281ff4a02	953	/**
AnnaBridge	161:aa5281ff4a02	954	* @brief Disables the DSI PLL.
AnnaBridge	163:e59c8e839560	955	* @param __HANDLE__ DSI handle
AnnaBridge	161:aa5281ff4a02	956	* @retval None.
AnnaBridge	161:aa5281ff4a02	957	*/
AnnaBridge	163:e59c8e839560	958	#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
AnnaBridge	163:e59c8e839560	959	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	960	CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
AnnaBridge	163:e59c8e839560	961	/* Delay after an DSI PLL disabling */ \
AnnaBridge	163:e59c8e839560	962	tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
AnnaBridge	163:e59c8e839560	963	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	964	}while(0U)
AnnaBridge	161:aa5281ff4a02	965
AnnaBridge	161:aa5281ff4a02	966	/**
AnnaBridge	161:aa5281ff4a02	967	* @brief Enables the DSI regulator.
AnnaBridge	163:e59c8e839560	968	* @param __HANDLE__ DSI handle
AnnaBridge	161:aa5281ff4a02	969	* @retval None.
AnnaBridge	161:aa5281ff4a02	970	*/
AnnaBridge	163:e59c8e839560	971	#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
AnnaBridge	163:e59c8e839560	972	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	973	SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
AnnaBridge	163:e59c8e839560	974	/* Delay after an DSI regulator enabling */ \
AnnaBridge	163:e59c8e839560	975	tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
AnnaBridge	163:e59c8e839560	976	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	977	}while(0U)
AnnaBridge	161:aa5281ff4a02	978
AnnaBridge	161:aa5281ff4a02	979	/**
AnnaBridge	161:aa5281ff4a02	980	* @brief Disables the DSI regulator.
AnnaBridge	163:e59c8e839560	981	* @param __HANDLE__ DSI handle
AnnaBridge	161:aa5281ff4a02	982	* @retval None.
AnnaBridge	161:aa5281ff4a02	983	*/
AnnaBridge	163:e59c8e839560	984	#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
AnnaBridge	163:e59c8e839560	985	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	163:e59c8e839560	986	CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
AnnaBridge	163:e59c8e839560	987	/* Delay after an DSI regulator disabling */ \
AnnaBridge	163:e59c8e839560	988	tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
AnnaBridge	163:e59c8e839560	989	UNUSED(tmpreg); \
AnnaBridge	163:e59c8e839560	990	}while(0U)
AnnaBridge	161:aa5281ff4a02	991
AnnaBridge	161:aa5281ff4a02	992	/**
AnnaBridge	161:aa5281ff4a02	993	* @brief Get the DSI pending flags.
AnnaBridge	163:e59c8e839560	994	* @param __HANDLE__ DSI handle.
AnnaBridge	163:e59c8e839560	995	* @param __FLAG__ Get the specified flag.
AnnaBridge	161:aa5281ff4a02	996	* This parameter can be any combination of the following values:
AnnaBridge	163:e59c8e839560	997	* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
AnnaBridge	163:e59c8e839560	998	* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
AnnaBridge	161:aa5281ff4a02	999	* @arg DSI_FLAG_BUSY : Busy Flag
AnnaBridge	161:aa5281ff4a02	1000	* @arg DSI_FLAG_PLLLS: PLL Lock Status
AnnaBridge	161:aa5281ff4a02	1001	* @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
AnnaBridge	161:aa5281ff4a02	1002	* @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
AnnaBridge	161:aa5281ff4a02	1003	* @arg DSI_FLAG_RRS : Regulator Ready Flag
AnnaBridge	161:aa5281ff4a02	1004	* @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
AnnaBridge	161:aa5281ff4a02	1005	* @retval The state of FLAG (SET or RESET).
AnnaBridge	161:aa5281ff4a02	1006	*/
AnnaBridge	161:aa5281ff4a02	1007	#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))
AnnaBridge	161:aa5281ff4a02	1008
AnnaBridge	161:aa5281ff4a02	1009	/**
AnnaBridge	161:aa5281ff4a02	1010	* @brief Clears the DSI pending flags.
AnnaBridge	163:e59c8e839560	1011	* @param __HANDLE__ DSI handle.
AnnaBridge	163:e59c8e839560	1012	* @param __FLAG__ specifies the flag to clear.
AnnaBridge	161:aa5281ff4a02	1013	* This parameter can be any combination of the following values:
AnnaBridge	163:e59c8e839560	1014	* @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
AnnaBridge	163:e59c8e839560	1015	* @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
AnnaBridge	161:aa5281ff4a02	1016	* @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
AnnaBridge	161:aa5281ff4a02	1017	* @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
AnnaBridge	161:aa5281ff4a02	1018	* @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
AnnaBridge	161:aa5281ff4a02	1019	* @retval None
AnnaBridge	161:aa5281ff4a02	1020	*/
AnnaBridge	161:aa5281ff4a02	1021	#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))
AnnaBridge	161:aa5281ff4a02	1022
AnnaBridge	161:aa5281ff4a02	1023	/**
AnnaBridge	161:aa5281ff4a02	1024	* @brief Enables the specified DSI interrupts.
AnnaBridge	163:e59c8e839560	1025	* @param __HANDLE__ DSI handle.
AnnaBridge	163:e59c8e839560	1026	* @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled.
AnnaBridge	161:aa5281ff4a02	1027	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	1028	* @arg DSI_IT_TE : Tearing Effect Interrupt
AnnaBridge	161:aa5281ff4a02	1029	* @arg DSI_IT_ER : End of Refresh Interrupt
AnnaBridge	161:aa5281ff4a02	1030	* @arg DSI_IT_PLLL: PLL Lock Interrupt
AnnaBridge	161:aa5281ff4a02	1031	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
AnnaBridge	161:aa5281ff4a02	1032	* @arg DSI_IT_RR : Regulator Ready Interrupt
AnnaBridge	161:aa5281ff4a02	1033	* @retval None
AnnaBridge	161:aa5281ff4a02	1034	*/
AnnaBridge	161:aa5281ff4a02	1035	#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER \|= (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1036
AnnaBridge	161:aa5281ff4a02	1037	/**
AnnaBridge	161:aa5281ff4a02	1038	* @brief Disables the specified DSI interrupts.
AnnaBridge	163:e59c8e839560	1039	* @param __HANDLE__ DSI handle
AnnaBridge	163:e59c8e839560	1040	* @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled.
AnnaBridge	161:aa5281ff4a02	1041	* This parameter can be any combination of the following values:
AnnaBridge	161:aa5281ff4a02	1042	* @arg DSI_IT_TE : Tearing Effect Interrupt
AnnaBridge	161:aa5281ff4a02	1043	* @arg DSI_IT_ER : End of Refresh Interrupt
AnnaBridge	161:aa5281ff4a02	1044	* @arg DSI_IT_PLLL: PLL Lock Interrupt
AnnaBridge	161:aa5281ff4a02	1045	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
AnnaBridge	161:aa5281ff4a02	1046	* @arg DSI_IT_RR : Regulator Ready Interrupt
AnnaBridge	161:aa5281ff4a02	1047	* @retval None
AnnaBridge	161:aa5281ff4a02	1048	*/
AnnaBridge	161:aa5281ff4a02	1049	#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1050
AnnaBridge	161:aa5281ff4a02	1051	/**
AnnaBridge	163:e59c8e839560	1052	* @brief Checks whether the specified DSI interrupt source is enabled or not.
AnnaBridge	163:e59c8e839560	1053	* @param __HANDLE__ DSI handle
AnnaBridge	163:e59c8e839560	1054	* @param __INTERRUPT__ specifies the DSI interrupt source to check.
AnnaBridge	161:aa5281ff4a02	1055	* This parameter can be one of the following values:
AnnaBridge	161:aa5281ff4a02	1056	* @arg DSI_IT_TE : Tearing Effect Interrupt
AnnaBridge	161:aa5281ff4a02	1057	* @arg DSI_IT_ER : End of Refresh Interrupt
AnnaBridge	161:aa5281ff4a02	1058	* @arg DSI_IT_PLLL: PLL Lock Interrupt
AnnaBridge	161:aa5281ff4a02	1059	* @arg DSI_IT_PLLU: PLL Unlock Interrupt
AnnaBridge	161:aa5281ff4a02	1060	* @arg DSI_IT_RR : Regulator Ready Interrupt
AnnaBridge	161:aa5281ff4a02	1061	* @retval The state of INTERRUPT (SET or RESET).
AnnaBridge	161:aa5281ff4a02	1062	*/
AnnaBridge	161:aa5281ff4a02	1063	#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))
AnnaBridge	161:aa5281ff4a02	1064
AnnaBridge	161:aa5281ff4a02	1065	/* Exported functions --------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	1066	/** @defgroup DSI_Exported_Functions DSI Exported Functions
AnnaBridge	161:aa5281ff4a02	1067	* @{
AnnaBridge	161:aa5281ff4a02	1068	*/
AnnaBridge	161:aa5281ff4a02	1069	HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef hdsi, DSI_PLLInitTypeDef PLLInit);
AnnaBridge	161:aa5281ff4a02	1070	HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1071	void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1072	void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1073
AnnaBridge	161:aa5281ff4a02	1074	void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1075	void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1076	void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1077	void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1078
AnnaBridge	161:aa5281ff4a02	1079	HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);
AnnaBridge	161:aa5281ff4a02	1080	HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef hdsi, DSI_VidCfgTypeDef VidCfg);
AnnaBridge	161:aa5281ff4a02	1081	HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef hdsi, DSI_CmdCfgTypeDef CmdCfg);
AnnaBridge	161:aa5281ff4a02	1082	HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef hdsi, DSI_LPCmdTypeDef LPCmd);
AnnaBridge	161:aa5281ff4a02	1083	HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);
AnnaBridge	161:aa5281ff4a02	1084	HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef hdsi, DSI_PHY_TimerTypeDef PhyTimers);
AnnaBridge	161:aa5281ff4a02	1085	HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef hdsi, DSI_HOST_TimeoutTypeDef HostTimeouts);
AnnaBridge	161:aa5281ff4a02	1086	HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1087	HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1088	HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1089	HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);
AnnaBridge	161:aa5281ff4a02	1090	HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);
AnnaBridge	161:aa5281ff4a02	1091	HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
AnnaBridge	161:aa5281ff4a02	1092	uint32_t ChannelID,
AnnaBridge	161:aa5281ff4a02	1093	uint32_t Mode,
AnnaBridge	161:aa5281ff4a02	1094	uint32_t Param1,
AnnaBridge	161:aa5281ff4a02	1095	uint32_t Param2);
AnnaBridge	161:aa5281ff4a02	1096	HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
AnnaBridge	161:aa5281ff4a02	1097	uint32_t ChannelID,
AnnaBridge	161:aa5281ff4a02	1098	uint32_t Mode,
AnnaBridge	161:aa5281ff4a02	1099	uint32_t NbParams,
AnnaBridge	161:aa5281ff4a02	1100	uint32_t Param1,
AnnaBridge	161:aa5281ff4a02	1101	uint8_t* ParametersTable);
AnnaBridge	161:aa5281ff4a02	1102	HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
AnnaBridge	161:aa5281ff4a02	1103	uint32_t ChannelNbr,
AnnaBridge	161:aa5281ff4a02	1104	uint8_t* Array,
AnnaBridge	161:aa5281ff4a02	1105	uint32_t Size,
AnnaBridge	161:aa5281ff4a02	1106	uint32_t Mode,
AnnaBridge	161:aa5281ff4a02	1107	uint32_t DCSCmd,
AnnaBridge	161:aa5281ff4a02	1108	uint8_t* ParametersTable);
AnnaBridge	161:aa5281ff4a02	1109	HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1110	HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1111	HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1112	HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1113
AnnaBridge	161:aa5281ff4a02	1114	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);
AnnaBridge	161:aa5281ff4a02	1115	HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1116
AnnaBridge	161:aa5281ff4a02	1117	HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value);
AnnaBridge	161:aa5281ff4a02	1118	HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);
AnnaBridge	161:aa5281ff4a02	1119	HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	161:aa5281ff4a02	1120	HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State);
AnnaBridge	161:aa5281ff4a02	1121	HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value);
AnnaBridge	161:aa5281ff4a02	1122	HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);
AnnaBridge	161:aa5281ff4a02	1123	HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	161:aa5281ff4a02	1124	HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	161:aa5281ff4a02	1125	HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	161:aa5281ff4a02	1126	HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);
AnnaBridge	161:aa5281ff4a02	1127
AnnaBridge	161:aa5281ff4a02	1128	uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1129	HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);
AnnaBridge	161:aa5281ff4a02	1130	HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);
AnnaBridge	161:aa5281ff4a02	1131	/**
AnnaBridge	161:aa5281ff4a02	1132	* @}
AnnaBridge	161:aa5281ff4a02	1133	*/
AnnaBridge	161:aa5281ff4a02	1134
AnnaBridge	161:aa5281ff4a02	1135	/* Private types -------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	1136	/** @defgroup DSI_Private_Types DSI Private Types
AnnaBridge	161:aa5281ff4a02	1137	* @{
AnnaBridge	161:aa5281ff4a02	1138	*/
AnnaBridge	161:aa5281ff4a02	1139
AnnaBridge	161:aa5281ff4a02	1140	/**
AnnaBridge	161:aa5281ff4a02	1141	* @}
AnnaBridge	163:e59c8e839560	1142	*/
AnnaBridge	161:aa5281ff4a02	1143
AnnaBridge	161:aa5281ff4a02	1144	/* Private defines -----------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	1145	/** @defgroup DSI_Private_Defines DSI Private Defines
AnnaBridge	161:aa5281ff4a02	1146	* @{
AnnaBridge	161:aa5281ff4a02	1147	*/
AnnaBridge	161:aa5281ff4a02	1148
AnnaBridge	161:aa5281ff4a02	1149	/**
AnnaBridge	161:aa5281ff4a02	1150	* @}
AnnaBridge	163:e59c8e839560	1151	*/
AnnaBridge	163:e59c8e839560	1152
AnnaBridge	161:aa5281ff4a02	1153	/* Private variables ---------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	1154	/** @defgroup DSI_Private_Variables DSI Private Variables
AnnaBridge	161:aa5281ff4a02	1155	* @{
AnnaBridge	161:aa5281ff4a02	1156	*/
AnnaBridge	161:aa5281ff4a02	1157
AnnaBridge	161:aa5281ff4a02	1158	/**
AnnaBridge	161:aa5281ff4a02	1159	* @}
AnnaBridge	163:e59c8e839560	1160	*/
AnnaBridge	161:aa5281ff4a02	1161
AnnaBridge	161:aa5281ff4a02	1162	/* Private constants ---------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	1163	/** @defgroup DSI_Private_Constants DSI Private Constants
AnnaBridge	161:aa5281ff4a02	1164	* @{
AnnaBridge	161:aa5281ff4a02	1165	*/
AnnaBridge	163:e59c8e839560	1166	#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /!< Maximum return packet configuration /
AnnaBridge	161:aa5281ff4a02	1167	/**
AnnaBridge	161:aa5281ff4a02	1168	* @}
AnnaBridge	163:e59c8e839560	1169	*/
AnnaBridge	161:aa5281ff4a02	1170
AnnaBridge	161:aa5281ff4a02	1171	/* Private macros ------------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	1172	/** @defgroup DSI_Private_Macros DSI Private Macros
AnnaBridge	161:aa5281ff4a02	1173	* @{
AnnaBridge	161:aa5281ff4a02	1174	*/
AnnaBridge	161:aa5281ff4a02	1175	#define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U))
AnnaBridge	161:aa5281ff4a02	1176	#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) \|\| \
AnnaBridge	161:aa5281ff4a02	1177	((IDF) == DSI_PLL_IN_DIV2) \|\| \
AnnaBridge	161:aa5281ff4a02	1178	((IDF) == DSI_PLL_IN_DIV3) \|\| \
AnnaBridge	161:aa5281ff4a02	1179	((IDF) == DSI_PLL_IN_DIV4) \|\| \
AnnaBridge	161:aa5281ff4a02	1180	((IDF) == DSI_PLL_IN_DIV5) \|\| \
AnnaBridge	161:aa5281ff4a02	1181	((IDF) == DSI_PLL_IN_DIV6) \|\| \
AnnaBridge	161:aa5281ff4a02	1182	((IDF) == DSI_PLL_IN_DIV7))
AnnaBridge	161:aa5281ff4a02	1183	#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) \|\| \
AnnaBridge	161:aa5281ff4a02	1184	((ODF) == DSI_PLL_OUT_DIV2) \|\| \
AnnaBridge	161:aa5281ff4a02	1185	((ODF) == DSI_PLL_OUT_DIV4) \|\| \
AnnaBridge	161:aa5281ff4a02	1186	((ODF) == DSI_PLL_OUT_DIV8))
AnnaBridge	161:aa5281ff4a02	1187	#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) \|\| ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))
AnnaBridge	161:aa5281ff4a02	1188	#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) \|\| ((NumberOfLanes) == DSI_TWO_DATA_LANES))
AnnaBridge	161:aa5281ff4a02	1189	#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) \| DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)
AnnaBridge	161:aa5281ff4a02	1190	#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U)
AnnaBridge	161:aa5281ff4a02	1191	#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) \|\| ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))
AnnaBridge	161:aa5281ff4a02	1192	#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) \|\| ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))
AnnaBridge	161:aa5281ff4a02	1193	#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) \|\| ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))
AnnaBridge	161:aa5281ff4a02	1194	#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) \|\| ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))
AnnaBridge	161:aa5281ff4a02	1195	#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) \|\| \
AnnaBridge	161:aa5281ff4a02	1196	((VideoModeType) == DSI_VID_MODE_NB_EVENTS) \|\| \
AnnaBridge	161:aa5281ff4a02	1197	((VideoModeType) == DSI_VID_MODE_BURST))
AnnaBridge	161:aa5281ff4a02	1198	#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) \|\| ((ColorMode) == DSI_COLOR_MODE_EIGHT))
AnnaBridge	161:aa5281ff4a02	1199	#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) \|\| ((ShutDown) == DSI_DISPLAY_OFF))
AnnaBridge	161:aa5281ff4a02	1200	#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) \|\| ((LPCommand) == DSI_LP_COMMAND_ENABLE))
AnnaBridge	161:aa5281ff4a02	1201	#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) \|\| ((LPHFP) == DSI_LP_HFP_ENABLE))
AnnaBridge	161:aa5281ff4a02	1202	#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) \|\| ((LPHBP) == DSI_LP_HBP_ENABLE))
AnnaBridge	161:aa5281ff4a02	1203	#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) \|\| ((LPVActive) == DSI_LP_VACT_ENABLE))
AnnaBridge	161:aa5281ff4a02	1204	#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) \|\| ((LPVFP) == DSI_LP_VFP_ENABLE))
AnnaBridge	161:aa5281ff4a02	1205	#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) \|\| ((LPVBP) == DSI_LP_VBP_ENABLE))
AnnaBridge	161:aa5281ff4a02	1206	#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) \|\| ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))
AnnaBridge	161:aa5281ff4a02	1207	#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) \|\| ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))
AnnaBridge	161:aa5281ff4a02	1208	#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) \|\| ((TESource) == DSI_TE_EXTERNAL))
AnnaBridge	161:aa5281ff4a02	1209	#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) \|\| ((TEPolarity) == DSI_TE_FALLING_EDGE))
AnnaBridge	161:aa5281ff4a02	1210	#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) \|\| ((AutomaticRefresh) == DSI_AR_ENABLE))
AnnaBridge	161:aa5281ff4a02	1211	#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) \|\| ((VSPolarity) == DSI_VSYNC_RISING))
AnnaBridge	161:aa5281ff4a02	1212	#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) \|\| ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))
AnnaBridge	161:aa5281ff4a02	1213	#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) \|\| ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))
AnnaBridge	161:aa5281ff4a02	1214	#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) \|\| ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))
AnnaBridge	161:aa5281ff4a02	1215	#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) \|\| ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))
AnnaBridge	161:aa5281ff4a02	1216	#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) \|\| ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))
AnnaBridge	161:aa5281ff4a02	1217	#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) \|\| ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))
AnnaBridge	161:aa5281ff4a02	1218	#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) \|\| ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))
AnnaBridge	161:aa5281ff4a02	1219	#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) \|\| ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))
AnnaBridge	161:aa5281ff4a02	1220	#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) \|\| ((LP_GLW) == DSI_LP_GLW_ENABLE))
AnnaBridge	161:aa5281ff4a02	1221	#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) \|\| ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))
AnnaBridge	161:aa5281ff4a02	1222	#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) \|\| ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))
AnnaBridge	161:aa5281ff4a02	1223	#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) \|\| ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))
AnnaBridge	161:aa5281ff4a02	1224	#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) \|\| ((LP_DLW) == DSI_LP_DLW_ENABLE))
AnnaBridge	161:aa5281ff4a02	1225	#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) \|\| ((LP_MRDP) == DSI_LP_MRDP_ENABLE))
AnnaBridge	161:aa5281ff4a02	1226	#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) \|\| \
AnnaBridge	161:aa5281ff4a02	1227	((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) \|\| \
AnnaBridge	161:aa5281ff4a02	1228	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) \|\| \
AnnaBridge	161:aa5281ff4a02	1229	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) \|\| \
AnnaBridge	161:aa5281ff4a02	1230	((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))
AnnaBridge	161:aa5281ff4a02	1231	#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) \|\| \
AnnaBridge	161:aa5281ff4a02	1232	((MODE) == DSI_GEN_LONG_PKT_WRITE))
AnnaBridge	161:aa5281ff4a02	1233	#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) \|\| \
AnnaBridge	161:aa5281ff4a02	1234	((MODE) == DSI_GEN_SHORT_PKT_READ_P0) \|\| \
AnnaBridge	161:aa5281ff4a02	1235	((MODE) == DSI_GEN_SHORT_PKT_READ_P1) \|\| \
AnnaBridge	161:aa5281ff4a02	1236	((MODE) == DSI_GEN_SHORT_PKT_READ_P2))
AnnaBridge	161:aa5281ff4a02	1237	#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) \|\| ((CommDelay) == DSI_SLEW_RATE_LPTX) \|\| ((CommDelay) == DSI_HS_DELAY))
AnnaBridge	161:aa5281ff4a02	1238	#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) \|\| ((Lane) == DSI_DATA_LANES))
AnnaBridge	161:aa5281ff4a02	1239	#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) \|\| ((CustomLane) == DSI_INVERT_HS_SIGNAL))
AnnaBridge	161:aa5281ff4a02	1240	#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) \|\| ((Lane) == DSI_DATA_LANE0) \|\| ((Lane) == DSI_DATA_LANE1))
AnnaBridge	161:aa5281ff4a02	1241	#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) \|\| \
AnnaBridge	161:aa5281ff4a02	1242	((Timing) == DSI_TLPX_CLK ) \|\| \
AnnaBridge	161:aa5281ff4a02	1243	((Timing) == DSI_THS_EXIT ) \|\| \
AnnaBridge	161:aa5281ff4a02	1244	((Timing) == DSI_TLPX_DATA ) \|\| \
AnnaBridge	161:aa5281ff4a02	1245	((Timing) == DSI_THS_ZERO ) \|\| \
AnnaBridge	161:aa5281ff4a02	1246	((Timing) == DSI_THS_TRAIL ) \|\| \
AnnaBridge	161:aa5281ff4a02	1247	((Timing) == DSI_THS_PREPARE ) \|\| \
AnnaBridge	161:aa5281ff4a02	1248	((Timing) == DSI_TCLK_ZERO ) \|\| \
AnnaBridge	161:aa5281ff4a02	1249	((Timing) == DSI_TCLK_PREPARE))
AnnaBridge	161:aa5281ff4a02	1250
AnnaBridge	161:aa5281ff4a02	1251	/**
AnnaBridge	161:aa5281ff4a02	1252	* @}
AnnaBridge	163:e59c8e839560	1253	*/
AnnaBridge	161:aa5281ff4a02	1254
AnnaBridge	161:aa5281ff4a02	1255	/* Private functions prototypes ----------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	1256	/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
AnnaBridge	161:aa5281ff4a02	1257	* @{
AnnaBridge	161:aa5281ff4a02	1258	*/
AnnaBridge	161:aa5281ff4a02	1259
AnnaBridge	161:aa5281ff4a02	1260	/**
AnnaBridge	161:aa5281ff4a02	1261	* @}
AnnaBridge	161:aa5281ff4a02	1262	*/
AnnaBridge	161:aa5281ff4a02	1263
AnnaBridge	161:aa5281ff4a02	1264	/* Private functions ---------------------------------------------------------*/
AnnaBridge	161:aa5281ff4a02	1265	/** @defgroup DSI_Private_Functions DSI Private Functions
AnnaBridge	161:aa5281ff4a02	1266	* @{
AnnaBridge	161:aa5281ff4a02	1267	*/
AnnaBridge	161:aa5281ff4a02	1268
AnnaBridge	161:aa5281ff4a02	1269	/**
AnnaBridge	161:aa5281ff4a02	1270	* @}
AnnaBridge	161:aa5281ff4a02	1271	*/
AnnaBridge	161:aa5281ff4a02	1272
AnnaBridge	161:aa5281ff4a02	1273	/**
AnnaBridge	161:aa5281ff4a02	1274	* @}
AnnaBridge	161:aa5281ff4a02	1275	*/
AnnaBridge	161:aa5281ff4a02	1276
AnnaBridge	161:aa5281ff4a02	1277	/**
AnnaBridge	161:aa5281ff4a02	1278	* @}
AnnaBridge	161:aa5281ff4a02	1279	*/
AnnaBridge	163:e59c8e839560	1280	#endif /* DSI */
AnnaBridge	163:e59c8e839560	1281
AnnaBridge	161:aa5281ff4a02	1282	#ifdef __cplusplus
AnnaBridge	161:aa5281ff4a02	1283	}
AnnaBridge	161:aa5281ff4a02	1284	#endif
AnnaBridge	161:aa5281ff4a02	1285
AnnaBridge	161:aa5281ff4a02	1286	#endif /* __STM32F4xx_HAL_DSI_H */
AnnaBridge	161:aa5281ff4a02	1287
AnnaBridge	161:aa5281ff4a02	1288	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/