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TARGET_EFM32WG_STK3800/TOOLCHAIN_IAR/efm32wg_fpueh.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32wg_fpueh.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32WG_FPUEH register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32WG_FPUEH
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32WG_FPUEH Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 44 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 171:3a7713b1edbc 45 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 171:3a7713b1edbc 46 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 47 } FPUEH_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 50 * @defgroup EFM32WG_FPUEH_BitFields
AnnaBridge 171:3a7713b1edbc 51 * @{
AnnaBridge 171:3a7713b1edbc 52 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54 /* Bit fields for FPUEH IF */
AnnaBridge 171:3a7713b1edbc 55 #define _FPUEH_IF_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 56 #define _FPUEH_IF_MASK 0x0000003FUL /**< Mask for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 57 #define FPUEH_IF_FPIOC (0x1UL << 0) /**< FPU invalid operation */
AnnaBridge 171:3a7713b1edbc 58 #define _FPUEH_IF_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
AnnaBridge 171:3a7713b1edbc 59 #define _FPUEH_IF_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
AnnaBridge 171:3a7713b1edbc 60 #define _FPUEH_IF_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 61 #define FPUEH_IF_FPIOC_DEFAULT (_FPUEH_IF_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 62 #define FPUEH_IF_FPDZC (0x1UL << 1) /**< FPU divide-by-zero exception */
AnnaBridge 171:3a7713b1edbc 63 #define _FPUEH_IF_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
AnnaBridge 171:3a7713b1edbc 64 #define _FPUEH_IF_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
AnnaBridge 171:3a7713b1edbc 65 #define _FPUEH_IF_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 66 #define FPUEH_IF_FPDZC_DEFAULT (_FPUEH_IF_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 67 #define FPUEH_IF_FPUFC (0x1UL << 2) /**< FPU underflow exception */
AnnaBridge 171:3a7713b1edbc 68 #define _FPUEH_IF_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
AnnaBridge 171:3a7713b1edbc 69 #define _FPUEH_IF_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
AnnaBridge 171:3a7713b1edbc 70 #define _FPUEH_IF_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 71 #define FPUEH_IF_FPUFC_DEFAULT (_FPUEH_IF_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 72 #define FPUEH_IF_FPOFC (0x1UL << 3) /**< FPU overflow exception */
AnnaBridge 171:3a7713b1edbc 73 #define _FPUEH_IF_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
AnnaBridge 171:3a7713b1edbc 74 #define _FPUEH_IF_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
AnnaBridge 171:3a7713b1edbc 75 #define _FPUEH_IF_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 76 #define FPUEH_IF_FPOFC_DEFAULT (_FPUEH_IF_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 77 #define FPUEH_IF_FPIDC (0x1UL << 4) /**< FPU input denormal exception */
AnnaBridge 171:3a7713b1edbc 78 #define _FPUEH_IF_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
AnnaBridge 171:3a7713b1edbc 79 #define _FPUEH_IF_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
AnnaBridge 171:3a7713b1edbc 80 #define _FPUEH_IF_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 81 #define FPUEH_IF_FPIDC_DEFAULT (_FPUEH_IF_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 82 #define FPUEH_IF_FPIXC (0x1UL << 5) /**< FPU inexact exception */
AnnaBridge 171:3a7713b1edbc 83 #define _FPUEH_IF_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
AnnaBridge 171:3a7713b1edbc 84 #define _FPUEH_IF_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
AnnaBridge 171:3a7713b1edbc 85 #define _FPUEH_IF_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 86 #define FPUEH_IF_FPIXC_DEFAULT (_FPUEH_IF_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IF */
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 /* Bit fields for FPUEH IFS */
AnnaBridge 171:3a7713b1edbc 89 #define _FPUEH_IFS_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 90 #define _FPUEH_IFS_MASK 0x0000003FUL /**< Mask for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 91 #define FPUEH_IFS_FPIOC (0x1UL << 0) /**< Set FPIOC Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 92 #define _FPUEH_IFS_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
AnnaBridge 171:3a7713b1edbc 93 #define _FPUEH_IFS_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
AnnaBridge 171:3a7713b1edbc 94 #define _FPUEH_IFS_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 95 #define FPUEH_IFS_FPIOC_DEFAULT (_FPUEH_IFS_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 96 #define FPUEH_IFS_FPDZC (0x1UL << 1) /**< Set FPDZC Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 97 #define _FPUEH_IFS_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
AnnaBridge 171:3a7713b1edbc 98 #define _FPUEH_IFS_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
AnnaBridge 171:3a7713b1edbc 99 #define _FPUEH_IFS_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 100 #define FPUEH_IFS_FPDZC_DEFAULT (_FPUEH_IFS_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 101 #define FPUEH_IFS_FPUFC (0x1UL << 2) /**< Set FPUFC Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 102 #define _FPUEH_IFS_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
AnnaBridge 171:3a7713b1edbc 103 #define _FPUEH_IFS_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
AnnaBridge 171:3a7713b1edbc 104 #define _FPUEH_IFS_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 105 #define FPUEH_IFS_FPUFC_DEFAULT (_FPUEH_IFS_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 106 #define FPUEH_IFS_FPOFC (0x1UL << 3) /**< Set FPOFC Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 107 #define _FPUEH_IFS_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
AnnaBridge 171:3a7713b1edbc 108 #define _FPUEH_IFS_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
AnnaBridge 171:3a7713b1edbc 109 #define _FPUEH_IFS_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 110 #define FPUEH_IFS_FPOFC_DEFAULT (_FPUEH_IFS_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 111 #define FPUEH_IFS_FPIDC (0x1UL << 4) /**< Set FPIDC Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 112 #define _FPUEH_IFS_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
AnnaBridge 171:3a7713b1edbc 113 #define _FPUEH_IFS_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
AnnaBridge 171:3a7713b1edbc 114 #define _FPUEH_IFS_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 115 #define FPUEH_IFS_FPIDC_DEFAULT (_FPUEH_IFS_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 116 #define FPUEH_IFS_FPIXC (0x1UL << 5) /**< Set FPIXC Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 117 #define _FPUEH_IFS_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
AnnaBridge 171:3a7713b1edbc 118 #define _FPUEH_IFS_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
AnnaBridge 171:3a7713b1edbc 119 #define _FPUEH_IFS_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 120 #define FPUEH_IFS_FPIXC_DEFAULT (_FPUEH_IFS_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFS */
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 /* Bit fields for FPUEH IFC */
AnnaBridge 171:3a7713b1edbc 123 #define _FPUEH_IFC_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 124 #define _FPUEH_IFC_MASK 0x0000003FUL /**< Mask for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 125 #define FPUEH_IFC_FPIOC (0x1UL << 0) /**< Clear FPIOC Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 126 #define _FPUEH_IFC_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
AnnaBridge 171:3a7713b1edbc 127 #define _FPUEH_IFC_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
AnnaBridge 171:3a7713b1edbc 128 #define _FPUEH_IFC_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 129 #define FPUEH_IFC_FPIOC_DEFAULT (_FPUEH_IFC_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 130 #define FPUEH_IFC_FPDZC (0x1UL << 1) /**< Clear FPDZC Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 131 #define _FPUEH_IFC_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
AnnaBridge 171:3a7713b1edbc 132 #define _FPUEH_IFC_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
AnnaBridge 171:3a7713b1edbc 133 #define _FPUEH_IFC_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 134 #define FPUEH_IFC_FPDZC_DEFAULT (_FPUEH_IFC_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 135 #define FPUEH_IFC_FPUFC (0x1UL << 2) /**< Clear FPUFC Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 136 #define _FPUEH_IFC_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
AnnaBridge 171:3a7713b1edbc 137 #define _FPUEH_IFC_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
AnnaBridge 171:3a7713b1edbc 138 #define _FPUEH_IFC_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 139 #define FPUEH_IFC_FPUFC_DEFAULT (_FPUEH_IFC_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 140 #define FPUEH_IFC_FPOFC (0x1UL << 3) /**< Clear FPOFC Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 141 #define _FPUEH_IFC_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
AnnaBridge 171:3a7713b1edbc 142 #define _FPUEH_IFC_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
AnnaBridge 171:3a7713b1edbc 143 #define _FPUEH_IFC_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 144 #define FPUEH_IFC_FPOFC_DEFAULT (_FPUEH_IFC_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 145 #define FPUEH_IFC_FPIDC (0x1UL << 4) /**< Clear FPIDC Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 146 #define _FPUEH_IFC_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
AnnaBridge 171:3a7713b1edbc 147 #define _FPUEH_IFC_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
AnnaBridge 171:3a7713b1edbc 148 #define _FPUEH_IFC_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 149 #define FPUEH_IFC_FPIDC_DEFAULT (_FPUEH_IFC_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 150 #define FPUEH_IFC_FPIXC (0x1UL << 5) /**< Clear FPIXC Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 151 #define _FPUEH_IFC_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
AnnaBridge 171:3a7713b1edbc 152 #define _FPUEH_IFC_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
AnnaBridge 171:3a7713b1edbc 153 #define _FPUEH_IFC_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 154 #define FPUEH_IFC_FPIXC_DEFAULT (_FPUEH_IFC_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IFC */
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 /* Bit fields for FPUEH IEN */
AnnaBridge 171:3a7713b1edbc 157 #define _FPUEH_IEN_RESETVALUE 0x00000000UL /**< Default value for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 158 #define _FPUEH_IEN_MASK 0x0000003FUL /**< Mask for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 159 #define FPUEH_IEN_FPIOC (0x1UL << 0) /**< FPIOC Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 160 #define _FPUEH_IEN_FPIOC_SHIFT 0 /**< Shift value for FPUEH_FPIOC */
AnnaBridge 171:3a7713b1edbc 161 #define _FPUEH_IEN_FPIOC_MASK 0x1UL /**< Bit mask for FPUEH_FPIOC */
AnnaBridge 171:3a7713b1edbc 162 #define _FPUEH_IEN_FPIOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 163 #define FPUEH_IEN_FPIOC_DEFAULT (_FPUEH_IEN_FPIOC_DEFAULT << 0) /**< Shifted mode DEFAULT for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 164 #define FPUEH_IEN_FPDZC (0x1UL << 1) /**< FPDZC Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 165 #define _FPUEH_IEN_FPDZC_SHIFT 1 /**< Shift value for FPUEH_FPDZC */
AnnaBridge 171:3a7713b1edbc 166 #define _FPUEH_IEN_FPDZC_MASK 0x2UL /**< Bit mask for FPUEH_FPDZC */
AnnaBridge 171:3a7713b1edbc 167 #define _FPUEH_IEN_FPDZC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 168 #define FPUEH_IEN_FPDZC_DEFAULT (_FPUEH_IEN_FPDZC_DEFAULT << 1) /**< Shifted mode DEFAULT for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 169 #define FPUEH_IEN_FPUFC (0x1UL << 2) /**< FPUFC Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 170 #define _FPUEH_IEN_FPUFC_SHIFT 2 /**< Shift value for FPUEH_FPUFC */
AnnaBridge 171:3a7713b1edbc 171 #define _FPUEH_IEN_FPUFC_MASK 0x4UL /**< Bit mask for FPUEH_FPUFC */
AnnaBridge 171:3a7713b1edbc 172 #define _FPUEH_IEN_FPUFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 173 #define FPUEH_IEN_FPUFC_DEFAULT (_FPUEH_IEN_FPUFC_DEFAULT << 2) /**< Shifted mode DEFAULT for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 174 #define FPUEH_IEN_FPOFC (0x1UL << 3) /**< FPOFC Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 175 #define _FPUEH_IEN_FPOFC_SHIFT 3 /**< Shift value for FPUEH_FPOFC */
AnnaBridge 171:3a7713b1edbc 176 #define _FPUEH_IEN_FPOFC_MASK 0x8UL /**< Bit mask for FPUEH_FPOFC */
AnnaBridge 171:3a7713b1edbc 177 #define _FPUEH_IEN_FPOFC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 178 #define FPUEH_IEN_FPOFC_DEFAULT (_FPUEH_IEN_FPOFC_DEFAULT << 3) /**< Shifted mode DEFAULT for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 179 #define FPUEH_IEN_FPIDC (0x1UL << 4) /**< FPIDC Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 180 #define _FPUEH_IEN_FPIDC_SHIFT 4 /**< Shift value for FPUEH_FPIDC */
AnnaBridge 171:3a7713b1edbc 181 #define _FPUEH_IEN_FPIDC_MASK 0x10UL /**< Bit mask for FPUEH_FPIDC */
AnnaBridge 171:3a7713b1edbc 182 #define _FPUEH_IEN_FPIDC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 183 #define FPUEH_IEN_FPIDC_DEFAULT (_FPUEH_IEN_FPIDC_DEFAULT << 4) /**< Shifted mode DEFAULT for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 184 #define FPUEH_IEN_FPIXC (0x1UL << 5) /**< FPIXC Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 185 #define _FPUEH_IEN_FPIXC_SHIFT 5 /**< Shift value for FPUEH_FPIXC */
AnnaBridge 171:3a7713b1edbc 186 #define _FPUEH_IEN_FPIXC_MASK 0x20UL /**< Bit mask for FPUEH_FPIXC */
AnnaBridge 171:3a7713b1edbc 187 #define _FPUEH_IEN_FPIXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 188 #define FPUEH_IEN_FPIXC_DEFAULT (_FPUEH_IEN_FPIXC_DEFAULT << 5) /**< Shifted mode DEFAULT for FPUEH_IEN */
AnnaBridge 171:3a7713b1edbc 189
AnnaBridge 171:3a7713b1edbc 190 /** @} End of group EFM32WG_FPUEH */
AnnaBridge 171:3a7713b1edbc 191 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 192