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TARGET_EFM32WG_STK3800/TOOLCHAIN_ARM_STD/efm32wg_pcnt.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 2 | * @file efm32wg_pcnt.h |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @brief EFM32WG_PCNT register and bit field definitions |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @version 5.1.2 |
| AnnaBridge | 171:3a7713b1edbc | 5 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 6 | * @section License |
| AnnaBridge | 171:3a7713b1edbc | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| AnnaBridge | 171:3a7713b1edbc | 8 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 9 | * |
| AnnaBridge | 171:3a7713b1edbc | 10 | * Permission is granted to anyone to use this software for any purpose, |
| AnnaBridge | 171:3a7713b1edbc | 11 | * including commercial applications, and to alter it and redistribute it |
| AnnaBridge | 171:3a7713b1edbc | 12 | * freely, subject to the following restrictions: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * |
| AnnaBridge | 171:3a7713b1edbc | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| AnnaBridge | 171:3a7713b1edbc | 15 | * claim that you wrote the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| AnnaBridge | 171:3a7713b1edbc | 17 | * misrepresented as being the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| AnnaBridge | 171:3a7713b1edbc | 19 | * |
| AnnaBridge | 171:3a7713b1edbc | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| AnnaBridge | 171:3a7713b1edbc | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| AnnaBridge | 171:3a7713b1edbc | 23 | * kind, including, but not limited to, any implied warranties of |
| AnnaBridge | 171:3a7713b1edbc | 24 | * merchantability or fitness for any particular purpose or warranties against |
| AnnaBridge | 171:3a7713b1edbc | 25 | * infringement of any proprietary rights of a third party. |
| AnnaBridge | 171:3a7713b1edbc | 26 | * |
| AnnaBridge | 171:3a7713b1edbc | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| AnnaBridge | 171:3a7713b1edbc | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| AnnaBridge | 171:3a7713b1edbc | 29 | * any third party, arising from your use of this Software. |
| AnnaBridge | 171:3a7713b1edbc | 30 | * |
| AnnaBridge | 171:3a7713b1edbc | 31 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 32 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 33 | * @addtogroup Parts |
| AnnaBridge | 171:3a7713b1edbc | 34 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 35 | ******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 36 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 37 | * @defgroup EFM32WG_PCNT |
| AnnaBridge | 171:3a7713b1edbc | 38 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 39 | * @brief EFM32WG_PCNT Register Declaration |
| AnnaBridge | 171:3a7713b1edbc | 40 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 41 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 42 | { |
| AnnaBridge | 171:3a7713b1edbc | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 44 | __IOM uint32_t CMD; /**< Command Register */ |
| AnnaBridge | 171:3a7713b1edbc | 45 | __IM uint32_t STATUS; /**< Status Register */ |
| AnnaBridge | 171:3a7713b1edbc | 46 | __IM uint32_t CNT; /**< Counter Value Register */ |
| AnnaBridge | 171:3a7713b1edbc | 47 | __IM uint32_t TOP; /**< Top Value Register */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | __IOM uint32_t TOPB; /**< Top Value Buffer Register */ |
| AnnaBridge | 171:3a7713b1edbc | 49 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| AnnaBridge | 171:3a7713b1edbc | 51 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | __IOM uint32_t ROUTE; /**< I/O Routing Register */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | |
| AnnaBridge | 171:3a7713b1edbc | 55 | __IOM uint32_t FREEZE; /**< Freeze Register */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | |
| AnnaBridge | 171:3a7713b1edbc | 58 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 59 | __IOM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | __IOM uint32_t INPUT; /**< PCNT Input Register */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | } PCNT_TypeDef; /** @} */ |
| AnnaBridge | 171:3a7713b1edbc | 62 | |
| AnnaBridge | 171:3a7713b1edbc | 63 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 64 | * @defgroup EFM32WG_PCNT_BitFields |
| AnnaBridge | 171:3a7713b1edbc | 65 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 66 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 67 | |
| AnnaBridge | 171:3a7713b1edbc | 68 | /* Bit fields for PCNT CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | #define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 70 | #define _PCNT_CTRL_MASK 0x0000CF3FUL /**< Mask for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | #define _PCNT_CTRL_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | #define _PCNT_CTRL_MODE_MASK 0x3UL /**< Bit mask for PCNT_MODE */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | #define _PCNT_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | #define _PCNT_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | #define _PCNT_CTRL_MODE_OVSSINGLE 0x00000001UL /**< Mode OVSSINGLE for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | #define _PCNT_CTRL_MODE_EXTCLKSINGLE 0x00000002UL /**< Mode EXTCLKSINGLE for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | #define _PCNT_CTRL_MODE_EXTCLKQUAD 0x00000003UL /**< Mode EXTCLKQUAD for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | #define PCNT_CTRL_MODE_DEFAULT (_PCNT_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | #define PCNT_CTRL_MODE_DISABLE (_PCNT_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | #define PCNT_CTRL_MODE_OVSSINGLE (_PCNT_CTRL_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | #define PCNT_CTRL_MODE_EXTCLKSINGLE (_PCNT_CTRL_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | #define PCNT_CTRL_MODE_EXTCLKQUAD (_PCNT_CTRL_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | #define PCNT_CTRL_CNTDIR (0x1UL << 2) /**< Non-Quadrature Mode Counter Direction Control */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | #define _PCNT_CTRL_CNTDIR_SHIFT 2 /**< Shift value for PCNT_CNTDIR */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | #define _PCNT_CTRL_CNTDIR_MASK 0x4UL /**< Bit mask for PCNT_CNTDIR */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | #define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | #define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | #define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | #define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | #define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 2) /**< Shifted mode UP for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | #define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 2) /**< Shifted mode DOWN for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | #define PCNT_CTRL_EDGE (0x1UL << 3) /**< Edge Select */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define _PCNT_CTRL_EDGE_SHIFT 3 /**< Shift value for PCNT_EDGE */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define _PCNT_CTRL_EDGE_MASK 0x8UL /**< Bit mask for PCNT_EDGE */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | #define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | #define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 3) /**< Shifted mode POS for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 3) /**< Shifted mode NEG for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | #define PCNT_CTRL_FILT (0x1UL << 4) /**< Enable Digital Pulse Width Filter */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | #define _PCNT_CTRL_FILT_SHIFT 4 /**< Shift value for PCNT_FILT */ |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define _PCNT_CTRL_FILT_MASK 0x10UL /**< Bit mask for PCNT_FILT */ |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define _PCNT_CTRL_FILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define PCNT_CTRL_FILT_DEFAULT (_PCNT_CTRL_FILT_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define PCNT_CTRL_RSTEN (0x1UL << 5) /**< Enable PCNT Clock Domain Reset */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define _PCNT_CTRL_RSTEN_SHIFT 5 /**< Shift value for PCNT_RSTEN */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define _PCNT_CTRL_RSTEN_MASK 0x20UL /**< Bit mask for PCNT_RSTEN */ |
| AnnaBridge | 171:3a7713b1edbc | 109 | #define _PCNT_CTRL_RSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | #define PCNT_CTRL_RSTEN_DEFAULT (_PCNT_CTRL_RSTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | #define PCNT_CTRL_HYST (0x1UL << 8) /**< Enable Hysteresis */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | #define _PCNT_CTRL_HYST_SHIFT 8 /**< Shift value for PCNT_HYST */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define _PCNT_CTRL_HYST_MASK 0x100UL /**< Bit mask for PCNT_HYST */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define _PCNT_CTRL_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define PCNT_CTRL_HYST_DEFAULT (_PCNT_CTRL_HYST_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define PCNT_CTRL_S1CDIR (0x1UL << 9) /**< Count direction determined by S1 */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define _PCNT_CTRL_S1CDIR_SHIFT 9 /**< Shift value for PCNT_S1CDIR */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define _PCNT_CTRL_S1CDIR_MASK 0x200UL /**< Bit mask for PCNT_S1CDIR */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define _PCNT_CTRL_CNTEV_SHIFT 10 /**< Shift value for PCNT_CNTEV */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define _PCNT_CTRL_CNTEV_MASK 0xC00UL /**< Bit mask for PCNT_CNTEV */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | #define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | #define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 125 | #define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 126 | #define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define _PCNT_CTRL_CNTEV_NONE 0x00000003UL /**< Mode NONE for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 10) /**< Shifted mode BOTH for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 10) /**< Shifted mode UP for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 10) /**< Shifted mode DOWN for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define PCNT_CTRL_CNTEV_NONE (_PCNT_CTRL_CNTEV_NONE << 10) /**< Shifted mode NONE for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define _PCNT_CTRL_AUXCNTEV_SHIFT 14 /**< Shift value for PCNT_AUXCNTEV */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define _PCNT_CTRL_AUXCNTEV_MASK 0xC000UL /**< Bit mask for PCNT_AUXCNTEV */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define _PCNT_CTRL_AUXCNTEV_NONE 0x00000000UL /**< Mode NONE for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | #define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000003UL /**< Mode BOTH for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 14) /**< Shifted mode DEFAULT for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define PCNT_CTRL_AUXCNTEV_NONE (_PCNT_CTRL_AUXCNTEV_NONE << 14) /**< Shifted mode NONE for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 14) /**< Shifted mode UP for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 14) /**< Shifted mode DOWN for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 14) /**< Shifted mode BOTH for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | |
| AnnaBridge | 171:3a7713b1edbc | 146 | /* Bit fields for PCNT CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define _PCNT_CMD_MASK 0x00000003UL /**< Mask for PCNT_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | #define PCNT_CMD_LCNTIM (0x1UL << 0) /**< Load CNT Immediately */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | #define _PCNT_CMD_LCNTIM_SHIFT 0 /**< Shift value for PCNT_LCNTIM */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define _PCNT_CMD_LCNTIM_MASK 0x1UL /**< Bit mask for PCNT_LCNTIM */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define PCNT_CMD_LTOPBIM (0x1UL << 1) /**< Load TOPB Immediately */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define _PCNT_CMD_LTOPBIM_SHIFT 1 /**< Shift value for PCNT_LTOPBIM */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define _PCNT_CMD_LTOPBIM_MASK 0x2UL /**< Bit mask for PCNT_LTOPBIM */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define _PCNT_CMD_LTOPBIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define PCNT_CMD_LTOPBIM_DEFAULT (_PCNT_CMD_LTOPBIM_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | |
| AnnaBridge | 171:3a7713b1edbc | 160 | /* Bit fields for PCNT STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define _PCNT_STATUS_MASK 0x00000001UL /**< Mask for PCNT_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | |
| AnnaBridge | 171:3a7713b1edbc | 173 | /* Bit fields for PCNT CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | #define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | |
| AnnaBridge | 171:3a7713b1edbc | 181 | /* Bit fields for PCNT TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | |
| AnnaBridge | 171:3a7713b1edbc | 189 | /* Bit fields for PCNT TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | #define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | |
| AnnaBridge | 171:3a7713b1edbc | 197 | /* Bit fields for PCNT IF */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | #define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | #define _PCNT_IF_MASK 0x0000000FUL /**< Mask for PCNT_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | #define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | #define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | #define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define PCNT_IF_AUXOF (0x1UL << 3) /**< Overflow Interrupt Read Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | |
| AnnaBridge | 171:3a7713b1edbc | 221 | /* Bit fields for PCNT IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define _PCNT_IFS_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define _PCNT_IFS_MASK 0x0000000FUL /**< Mask for PCNT_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define PCNT_IFS_UF (0x1UL << 0) /**< Underflow interrupt set */ |
| AnnaBridge | 171:3a7713b1edbc | 225 | #define _PCNT_IFS_UF_SHIFT 0 /**< Shift value for PCNT_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define _PCNT_IFS_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define _PCNT_IFS_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define PCNT_IFS_UF_DEFAULT (_PCNT_IFS_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define PCNT_IFS_OF (0x1UL << 1) /**< Overflow Interrupt Set */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define _PCNT_IFS_OF_SHIFT 1 /**< Shift value for PCNT_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define _PCNT_IFS_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define _PCNT_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define PCNT_IFS_OF_DEFAULT (_PCNT_IFS_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define PCNT_IFS_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Set */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define _PCNT_IFS_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define _PCNT_IFS_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define _PCNT_IFS_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define PCNT_IFS_DIRCNG_DEFAULT (_PCNT_IFS_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define PCNT_IFS_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Set */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define _PCNT_IFS_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define _PCNT_IFS_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define _PCNT_IFS_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define PCNT_IFS_AUXOF_DEFAULT (_PCNT_IFS_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | |
| AnnaBridge | 171:3a7713b1edbc | 245 | /* Bit fields for PCNT IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define _PCNT_IFC_RESETVALUE 0x00000000UL /**< Default value for PCNT_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define _PCNT_IFC_MASK 0x0000000FUL /**< Mask for PCNT_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define PCNT_IFC_UF (0x1UL << 0) /**< Underflow Interrupt Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define _PCNT_IFC_UF_SHIFT 0 /**< Shift value for PCNT_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define _PCNT_IFC_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define _PCNT_IFC_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define PCNT_IFC_UF_DEFAULT (_PCNT_IFC_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define PCNT_IFC_OF (0x1UL << 1) /**< Overflow Interrupt Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define _PCNT_IFC_OF_SHIFT 1 /**< Shift value for PCNT_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define _PCNT_IFC_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define _PCNT_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define PCNT_IFC_OF_DEFAULT (_PCNT_IFC_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define PCNT_IFC_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define _PCNT_IFC_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define _PCNT_IFC_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define _PCNT_IFC_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | #define PCNT_IFC_DIRCNG_DEFAULT (_PCNT_IFC_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | #define PCNT_IFC_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Clear */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | #define _PCNT_IFC_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 265 | #define _PCNT_IFC_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define _PCNT_IFC_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define PCNT_IFC_AUXOF_DEFAULT (_PCNT_IFC_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | |
| AnnaBridge | 171:3a7713b1edbc | 269 | /* Bit fields for PCNT IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define _PCNT_IEN_MASK 0x0000000FUL /**< Mask for PCNT_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define PCNT_IEN_UF (0x1UL << 0) /**< Underflow Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define PCNT_IEN_OF (0x1UL << 1) /**< Overflow Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define PCNT_IEN_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define PCNT_IEN_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | |
| AnnaBridge | 171:3a7713b1edbc | 293 | /* Bit fields for PCNT ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define _PCNT_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PCNT_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define _PCNT_ROUTE_MASK 0x00000700UL /**< Mask for PCNT_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define _PCNT_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PCNT_LOCATION */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define _PCNT_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PCNT_LOCATION */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define _PCNT_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PCNT_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define _PCNT_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define _PCNT_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PCNT_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | #define _PCNT_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for PCNT_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define _PCNT_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for PCNT_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define PCNT_ROUTE_LOCATION_LOC0 (_PCNT_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PCNT_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define PCNT_ROUTE_LOCATION_DEFAULT (_PCNT_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define PCNT_ROUTE_LOCATION_LOC1 (_PCNT_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PCNT_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define PCNT_ROUTE_LOCATION_LOC2 (_PCNT_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for PCNT_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define PCNT_ROUTE_LOCATION_LOC3 (_PCNT_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for PCNT_ROUTE */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | |
| AnnaBridge | 171:3a7713b1edbc | 309 | /* Bit fields for PCNT FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define _PCNT_FREEZE_RESETVALUE 0x00000000UL /**< Default value for PCNT_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define _PCNT_FREEZE_MASK 0x00000001UL /**< Mask for PCNT_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define PCNT_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define _PCNT_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for PCNT_REGFREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define _PCNT_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for PCNT_REGFREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define _PCNT_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define _PCNT_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for PCNT_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define _PCNT_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for PCNT_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define PCNT_FREEZE_REGFREEZE_DEFAULT (_PCNT_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define PCNT_FREEZE_REGFREEZE_UPDATE (_PCNT_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for PCNT_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define PCNT_FREEZE_REGFREEZE_FREEZE (_PCNT_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for PCNT_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | |
| AnnaBridge | 171:3a7713b1edbc | 322 | /* Bit fields for PCNT SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | #define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 324 | #define _PCNT_SYNCBUSY_MASK 0x00000007UL /**< Mask for PCNT_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 330 | #define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 331 | #define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define PCNT_SYNCBUSY_TOPB (0x1UL << 2) /**< TOPB Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define _PCNT_SYNCBUSY_TOPB_SHIFT 2 /**< Shift value for PCNT_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define _PCNT_SYNCBUSY_TOPB_MASK 0x4UL /**< Bit mask for PCNT_TOPB */ |
| AnnaBridge | 171:3a7713b1edbc | 338 | #define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | |
| AnnaBridge | 171:3a7713b1edbc | 341 | /* Bit fields for PCNT AUXCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 342 | #define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | #define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | |
| AnnaBridge | 171:3a7713b1edbc | 349 | /* Bit fields for PCNT INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define _PCNT_INPUT_RESETVALUE 0x00000000UL /**< Default value for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define _PCNT_INPUT_MASK 0x000007DFUL /**< Mask for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define _PCNT_INPUT_S0PRSSEL_SHIFT 0 /**< Shift value for PCNT_S0PRSSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define _PCNT_INPUT_S0PRSSEL_MASK 0xFUL /**< Bit mask for PCNT_S0PRSSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define _PCNT_INPUT_S0PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define _PCNT_INPUT_S0PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define _PCNT_INPUT_S0PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define _PCNT_INPUT_S0PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define _PCNT_INPUT_S0PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define _PCNT_INPUT_S0PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define _PCNT_INPUT_S0PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define _PCNT_INPUT_S0PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define _PCNT_INPUT_S0PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define _PCNT_INPUT_S0PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | #define _PCNT_INPUT_S0PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define _PCNT_INPUT_S0PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define _PCNT_INPUT_S0PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 367 | #define PCNT_INPUT_S0PRSSEL_DEFAULT (_PCNT_INPUT_S0PRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define PCNT_INPUT_S0PRSSEL_PRSCH0 (_PCNT_INPUT_S0PRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 369 | #define PCNT_INPUT_S0PRSSEL_PRSCH1 (_PCNT_INPUT_S0PRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define PCNT_INPUT_S0PRSSEL_PRSCH2 (_PCNT_INPUT_S0PRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define PCNT_INPUT_S0PRSSEL_PRSCH3 (_PCNT_INPUT_S0PRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define PCNT_INPUT_S0PRSSEL_PRSCH4 (_PCNT_INPUT_S0PRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | #define PCNT_INPUT_S0PRSSEL_PRSCH5 (_PCNT_INPUT_S0PRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 374 | #define PCNT_INPUT_S0PRSSEL_PRSCH6 (_PCNT_INPUT_S0PRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define PCNT_INPUT_S0PRSSEL_PRSCH7 (_PCNT_INPUT_S0PRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 376 | #define PCNT_INPUT_S0PRSSEL_PRSCH8 (_PCNT_INPUT_S0PRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | #define PCNT_INPUT_S0PRSSEL_PRSCH9 (_PCNT_INPUT_S0PRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 378 | #define PCNT_INPUT_S0PRSSEL_PRSCH10 (_PCNT_INPUT_S0PRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 379 | #define PCNT_INPUT_S0PRSSEL_PRSCH11 (_PCNT_INPUT_S0PRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define PCNT_INPUT_S0PRSEN (0x1UL << 4) /**< S0IN PRS Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define _PCNT_INPUT_S0PRSEN_SHIFT 4 /**< Shift value for PCNT_S0PRSEN */ |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define _PCNT_INPUT_S0PRSEN_MASK 0x10UL /**< Bit mask for PCNT_S0PRSEN */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define _PCNT_INPUT_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define PCNT_INPUT_S0PRSEN_DEFAULT (_PCNT_INPUT_S0PRSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define _PCNT_INPUT_S1PRSSEL_SHIFT 6 /**< Shift value for PCNT_S1PRSSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define _PCNT_INPUT_S1PRSSEL_MASK 0x3C0UL /**< Bit mask for PCNT_S1PRSSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define _PCNT_INPUT_S1PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | #define _PCNT_INPUT_S1PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define _PCNT_INPUT_S1PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define _PCNT_INPUT_S1PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define _PCNT_INPUT_S1PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 392 | #define _PCNT_INPUT_S1PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | #define _PCNT_INPUT_S1PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 394 | #define _PCNT_INPUT_S1PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | #define _PCNT_INPUT_S1PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define _PCNT_INPUT_S1PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define _PCNT_INPUT_S1PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define _PCNT_INPUT_S1PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define _PCNT_INPUT_S1PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define PCNT_INPUT_S1PRSSEL_DEFAULT (_PCNT_INPUT_S1PRSSEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define PCNT_INPUT_S1PRSSEL_PRSCH0 (_PCNT_INPUT_S1PRSSEL_PRSCH0 << 6) /**< Shifted mode PRSCH0 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define PCNT_INPUT_S1PRSSEL_PRSCH1 (_PCNT_INPUT_S1PRSSEL_PRSCH1 << 6) /**< Shifted mode PRSCH1 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define PCNT_INPUT_S1PRSSEL_PRSCH2 (_PCNT_INPUT_S1PRSSEL_PRSCH2 << 6) /**< Shifted mode PRSCH2 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 404 | #define PCNT_INPUT_S1PRSSEL_PRSCH3 (_PCNT_INPUT_S1PRSSEL_PRSCH3 << 6) /**< Shifted mode PRSCH3 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | #define PCNT_INPUT_S1PRSSEL_PRSCH4 (_PCNT_INPUT_S1PRSSEL_PRSCH4 << 6) /**< Shifted mode PRSCH4 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define PCNT_INPUT_S1PRSSEL_PRSCH5 (_PCNT_INPUT_S1PRSSEL_PRSCH5 << 6) /**< Shifted mode PRSCH5 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define PCNT_INPUT_S1PRSSEL_PRSCH6 (_PCNT_INPUT_S1PRSSEL_PRSCH6 << 6) /**< Shifted mode PRSCH6 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define PCNT_INPUT_S1PRSSEL_PRSCH7 (_PCNT_INPUT_S1PRSSEL_PRSCH7 << 6) /**< Shifted mode PRSCH7 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 409 | #define PCNT_INPUT_S1PRSSEL_PRSCH8 (_PCNT_INPUT_S1PRSSEL_PRSCH8 << 6) /**< Shifted mode PRSCH8 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 410 | #define PCNT_INPUT_S1PRSSEL_PRSCH9 (_PCNT_INPUT_S1PRSSEL_PRSCH9 << 6) /**< Shifted mode PRSCH9 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 411 | #define PCNT_INPUT_S1PRSSEL_PRSCH10 (_PCNT_INPUT_S1PRSSEL_PRSCH10 << 6) /**< Shifted mode PRSCH10 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define PCNT_INPUT_S1PRSSEL_PRSCH11 (_PCNT_INPUT_S1PRSSEL_PRSCH11 << 6) /**< Shifted mode PRSCH11 for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define PCNT_INPUT_S1PRSEN (0x1UL << 10) /**< S1IN PRS Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define _PCNT_INPUT_S1PRSEN_SHIFT 10 /**< Shift value for PCNT_S1PRSEN */ |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define _PCNT_INPUT_S1PRSEN_MASK 0x400UL /**< Bit mask for PCNT_S1PRSEN */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define _PCNT_INPUT_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define PCNT_INPUT_S1PRSEN_DEFAULT (_PCNT_INPUT_S1PRSEN_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_INPUT */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | |
| AnnaBridge | 171:3a7713b1edbc | 419 | /** @} End of group EFM32WG_PCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | /** @} End of group Parts */ |
| AnnaBridge | 171:3a7713b1edbc | 421 |
