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TARGET_EFM32WG_STK3800/TOOLCHAIN_ARM_STD/efm32wg_msc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32wg_msc.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32WG_MSC register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32WG_MSC
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32WG_MSC Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IOM uint32_t CTRL; /**< Memory System Control Register */
AnnaBridge 171:3a7713b1edbc 44 __IOM uint32_t READCTRL; /**< Read Control Register */
AnnaBridge 171:3a7713b1edbc 45 __IOM uint32_t WRITECTRL; /**< Write Control Register */
AnnaBridge 171:3a7713b1edbc 46 __IOM uint32_t WRITECMD; /**< Write Command Register */
AnnaBridge 171:3a7713b1edbc 47 __IOM uint32_t ADDRB; /**< Page Erase/Write Address Buffer */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 uint32_t RESERVED0[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 50 __IOM uint32_t WDATA; /**< Write Data Register */
AnnaBridge 171:3a7713b1edbc 51 __IM uint32_t STATUS; /**< Status Register */
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 uint32_t RESERVED1[3]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 54 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 55 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 171:3a7713b1edbc 56 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 171:3a7713b1edbc 57 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 58 __IOM uint32_t LOCK; /**< Configuration Lock Register */
AnnaBridge 171:3a7713b1edbc 59 __IOM uint32_t CMD; /**< Command Register */
AnnaBridge 171:3a7713b1edbc 60 __IM uint32_t CACHEHITS; /**< Cache Hits Performance Counter */
AnnaBridge 171:3a7713b1edbc 61 __IM uint32_t CACHEMISSES; /**< Cache Misses Performance Counter */
AnnaBridge 171:3a7713b1edbc 62 uint32_t RESERVED2[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 63 __IOM uint32_t TIMEBASE; /**< Flash Write and Erase Timebase */
AnnaBridge 171:3a7713b1edbc 64 __IOM uint32_t MASSLOCK; /**< Mass Erase Lock Register */
AnnaBridge 171:3a7713b1edbc 65 } MSC_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 68 * @defgroup EFM32WG_MSC_BitFields
AnnaBridge 171:3a7713b1edbc 69 * @{
AnnaBridge 171:3a7713b1edbc 70 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 /* Bit fields for MSC CTRL */
AnnaBridge 171:3a7713b1edbc 73 #define _MSC_CTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_CTRL */
AnnaBridge 171:3a7713b1edbc 74 #define _MSC_CTRL_MASK 0x00000001UL /**< Mask for MSC_CTRL */
AnnaBridge 171:3a7713b1edbc 75 #define MSC_CTRL_BUSFAULT (0x1UL << 0) /**< Bus Fault Response Enable */
AnnaBridge 171:3a7713b1edbc 76 #define _MSC_CTRL_BUSFAULT_SHIFT 0 /**< Shift value for MSC_BUSFAULT */
AnnaBridge 171:3a7713b1edbc 77 #define _MSC_CTRL_BUSFAULT_MASK 0x1UL /**< Bit mask for MSC_BUSFAULT */
AnnaBridge 171:3a7713b1edbc 78 #define _MSC_CTRL_BUSFAULT_GENERATE 0x00000000UL /**< Mode GENERATE for MSC_CTRL */
AnnaBridge 171:3a7713b1edbc 79 #define _MSC_CTRL_BUSFAULT_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_CTRL */
AnnaBridge 171:3a7713b1edbc 80 #define _MSC_CTRL_BUSFAULT_IGNORE 0x00000001UL /**< Mode IGNORE for MSC_CTRL */
AnnaBridge 171:3a7713b1edbc 81 #define MSC_CTRL_BUSFAULT_GENERATE (_MSC_CTRL_BUSFAULT_GENERATE << 0) /**< Shifted mode GENERATE for MSC_CTRL */
AnnaBridge 171:3a7713b1edbc 82 #define MSC_CTRL_BUSFAULT_DEFAULT (_MSC_CTRL_BUSFAULT_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CTRL */
AnnaBridge 171:3a7713b1edbc 83 #define MSC_CTRL_BUSFAULT_IGNORE (_MSC_CTRL_BUSFAULT_IGNORE << 0) /**< Shifted mode IGNORE for MSC_CTRL */
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 /* Bit fields for MSC READCTRL */
AnnaBridge 171:3a7713b1edbc 86 #define _MSC_READCTRL_RESETVALUE 0x00000001UL /**< Default value for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 87 #define _MSC_READCTRL_MASK 0x000300FFUL /**< Mask for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 88 #define _MSC_READCTRL_MODE_SHIFT 0 /**< Shift value for MSC_MODE */
AnnaBridge 171:3a7713b1edbc 89 #define _MSC_READCTRL_MODE_MASK 0x7UL /**< Bit mask for MSC_MODE */
AnnaBridge 171:3a7713b1edbc 90 #define _MSC_READCTRL_MODE_WS0 0x00000000UL /**< Mode WS0 for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 91 #define _MSC_READCTRL_MODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 92 #define _MSC_READCTRL_MODE_WS1 0x00000001UL /**< Mode WS1 for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 93 #define _MSC_READCTRL_MODE_WS0SCBTP 0x00000002UL /**< Mode WS0SCBTP for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 94 #define _MSC_READCTRL_MODE_WS1SCBTP 0x00000003UL /**< Mode WS1SCBTP for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 95 #define _MSC_READCTRL_MODE_WS2 0x00000004UL /**< Mode WS2 for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 96 #define _MSC_READCTRL_MODE_WS2SCBTP 0x00000005UL /**< Mode WS2SCBTP for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 97 #define MSC_READCTRL_MODE_WS0 (_MSC_READCTRL_MODE_WS0 << 0) /**< Shifted mode WS0 for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 98 #define MSC_READCTRL_MODE_DEFAULT (_MSC_READCTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 99 #define MSC_READCTRL_MODE_WS1 (_MSC_READCTRL_MODE_WS1 << 0) /**< Shifted mode WS1 for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 100 #define MSC_READCTRL_MODE_WS0SCBTP (_MSC_READCTRL_MODE_WS0SCBTP << 0) /**< Shifted mode WS0SCBTP for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 101 #define MSC_READCTRL_MODE_WS1SCBTP (_MSC_READCTRL_MODE_WS1SCBTP << 0) /**< Shifted mode WS1SCBTP for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 102 #define MSC_READCTRL_MODE_WS2 (_MSC_READCTRL_MODE_WS2 << 0) /**< Shifted mode WS2 for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 103 #define MSC_READCTRL_MODE_WS2SCBTP (_MSC_READCTRL_MODE_WS2SCBTP << 0) /**< Shifted mode WS2SCBTP for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 104 #define MSC_READCTRL_IFCDIS (0x1UL << 3) /**< Internal Flash Cache Disable */
AnnaBridge 171:3a7713b1edbc 105 #define _MSC_READCTRL_IFCDIS_SHIFT 3 /**< Shift value for MSC_IFCDIS */
AnnaBridge 171:3a7713b1edbc 106 #define _MSC_READCTRL_IFCDIS_MASK 0x8UL /**< Bit mask for MSC_IFCDIS */
AnnaBridge 171:3a7713b1edbc 107 #define _MSC_READCTRL_IFCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 108 #define MSC_READCTRL_IFCDIS_DEFAULT (_MSC_READCTRL_IFCDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 109 #define MSC_READCTRL_AIDIS (0x1UL << 4) /**< Automatic Invalidate Disable */
AnnaBridge 171:3a7713b1edbc 110 #define _MSC_READCTRL_AIDIS_SHIFT 4 /**< Shift value for MSC_AIDIS */
AnnaBridge 171:3a7713b1edbc 111 #define _MSC_READCTRL_AIDIS_MASK 0x10UL /**< Bit mask for MSC_AIDIS */
AnnaBridge 171:3a7713b1edbc 112 #define _MSC_READCTRL_AIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 113 #define MSC_READCTRL_AIDIS_DEFAULT (_MSC_READCTRL_AIDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 114 #define MSC_READCTRL_ICCDIS (0x1UL << 5) /**< Interrupt Context Cache Disable */
AnnaBridge 171:3a7713b1edbc 115 #define _MSC_READCTRL_ICCDIS_SHIFT 5 /**< Shift value for MSC_ICCDIS */
AnnaBridge 171:3a7713b1edbc 116 #define _MSC_READCTRL_ICCDIS_MASK 0x20UL /**< Bit mask for MSC_ICCDIS */
AnnaBridge 171:3a7713b1edbc 117 #define _MSC_READCTRL_ICCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 118 #define MSC_READCTRL_ICCDIS_DEFAULT (_MSC_READCTRL_ICCDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 119 #define MSC_READCTRL_EBICDIS (0x1UL << 6) /**< External Bus Interface Cache Disable */
AnnaBridge 171:3a7713b1edbc 120 #define _MSC_READCTRL_EBICDIS_SHIFT 6 /**< Shift value for MSC_EBICDIS */
AnnaBridge 171:3a7713b1edbc 121 #define _MSC_READCTRL_EBICDIS_MASK 0x40UL /**< Bit mask for MSC_EBICDIS */
AnnaBridge 171:3a7713b1edbc 122 #define _MSC_READCTRL_EBICDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 123 #define MSC_READCTRL_EBICDIS_DEFAULT (_MSC_READCTRL_EBICDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 124 #define MSC_READCTRL_RAMCEN (0x1UL << 7) /**< RAM Cache Enable */
AnnaBridge 171:3a7713b1edbc 125 #define _MSC_READCTRL_RAMCEN_SHIFT 7 /**< Shift value for MSC_RAMCEN */
AnnaBridge 171:3a7713b1edbc 126 #define _MSC_READCTRL_RAMCEN_MASK 0x80UL /**< Bit mask for MSC_RAMCEN */
AnnaBridge 171:3a7713b1edbc 127 #define _MSC_READCTRL_RAMCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 128 #define MSC_READCTRL_RAMCEN_DEFAULT (_MSC_READCTRL_RAMCEN_DEFAULT << 7) /**< Shifted mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 129 #define _MSC_READCTRL_BUSSTRATEGY_SHIFT 16 /**< Shift value for MSC_BUSSTRATEGY */
AnnaBridge 171:3a7713b1edbc 130 #define _MSC_READCTRL_BUSSTRATEGY_MASK 0x30000UL /**< Bit mask for MSC_BUSSTRATEGY */
AnnaBridge 171:3a7713b1edbc 131 #define _MSC_READCTRL_BUSSTRATEGY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 132 #define _MSC_READCTRL_BUSSTRATEGY_CPU 0x00000000UL /**< Mode CPU for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 133 #define _MSC_READCTRL_BUSSTRATEGY_DMA 0x00000001UL /**< Mode DMA for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 134 #define _MSC_READCTRL_BUSSTRATEGY_DMAEM1 0x00000002UL /**< Mode DMAEM1 for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 135 #define _MSC_READCTRL_BUSSTRATEGY_NONE 0x00000003UL /**< Mode NONE for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 136 #define MSC_READCTRL_BUSSTRATEGY_DEFAULT (_MSC_READCTRL_BUSSTRATEGY_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 137 #define MSC_READCTRL_BUSSTRATEGY_CPU (_MSC_READCTRL_BUSSTRATEGY_CPU << 16) /**< Shifted mode CPU for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 138 #define MSC_READCTRL_BUSSTRATEGY_DMA (_MSC_READCTRL_BUSSTRATEGY_DMA << 16) /**< Shifted mode DMA for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 139 #define MSC_READCTRL_BUSSTRATEGY_DMAEM1 (_MSC_READCTRL_BUSSTRATEGY_DMAEM1 << 16) /**< Shifted mode DMAEM1 for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 140 #define MSC_READCTRL_BUSSTRATEGY_NONE (_MSC_READCTRL_BUSSTRATEGY_NONE << 16) /**< Shifted mode NONE for MSC_READCTRL */
AnnaBridge 171:3a7713b1edbc 141
AnnaBridge 171:3a7713b1edbc 142 /* Bit fields for MSC WRITECTRL */
AnnaBridge 171:3a7713b1edbc 143 #define _MSC_WRITECTRL_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECTRL */
AnnaBridge 171:3a7713b1edbc 144 #define _MSC_WRITECTRL_MASK 0x00000003UL /**< Mask for MSC_WRITECTRL */
AnnaBridge 171:3a7713b1edbc 145 #define MSC_WRITECTRL_WREN (0x1UL << 0) /**< Enable Write/Erase Controller */
AnnaBridge 171:3a7713b1edbc 146 #define _MSC_WRITECTRL_WREN_SHIFT 0 /**< Shift value for MSC_WREN */
AnnaBridge 171:3a7713b1edbc 147 #define _MSC_WRITECTRL_WREN_MASK 0x1UL /**< Bit mask for MSC_WREN */
AnnaBridge 171:3a7713b1edbc 148 #define _MSC_WRITECTRL_WREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
AnnaBridge 171:3a7713b1edbc 149 #define MSC_WRITECTRL_WREN_DEFAULT (_MSC_WRITECTRL_WREN_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
AnnaBridge 171:3a7713b1edbc 150 #define MSC_WRITECTRL_IRQERASEABORT (0x1UL << 1) /**< Abort Page Erase on Interrupt */
AnnaBridge 171:3a7713b1edbc 151 #define _MSC_WRITECTRL_IRQERASEABORT_SHIFT 1 /**< Shift value for MSC_IRQERASEABORT */
AnnaBridge 171:3a7713b1edbc 152 #define _MSC_WRITECTRL_IRQERASEABORT_MASK 0x2UL /**< Bit mask for MSC_IRQERASEABORT */
AnnaBridge 171:3a7713b1edbc 153 #define _MSC_WRITECTRL_IRQERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECTRL */
AnnaBridge 171:3a7713b1edbc 154 #define MSC_WRITECTRL_IRQERASEABORT_DEFAULT (_MSC_WRITECTRL_IRQERASEABORT_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECTRL */
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 /* Bit fields for MSC WRITECMD */
AnnaBridge 171:3a7713b1edbc 157 #define _MSC_WRITECMD_RESETVALUE 0x00000000UL /**< Default value for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 158 #define _MSC_WRITECMD_MASK 0x0000113FUL /**< Mask for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 159 #define MSC_WRITECMD_LADDRIM (0x1UL << 0) /**< Load MSC_ADDRB into ADDR */
AnnaBridge 171:3a7713b1edbc 160 #define _MSC_WRITECMD_LADDRIM_SHIFT 0 /**< Shift value for MSC_LADDRIM */
AnnaBridge 171:3a7713b1edbc 161 #define _MSC_WRITECMD_LADDRIM_MASK 0x1UL /**< Bit mask for MSC_LADDRIM */
AnnaBridge 171:3a7713b1edbc 162 #define _MSC_WRITECMD_LADDRIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 163 #define MSC_WRITECMD_LADDRIM_DEFAULT (_MSC_WRITECMD_LADDRIM_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 164 #define MSC_WRITECMD_ERASEPAGE (0x1UL << 1) /**< Erase Page */
AnnaBridge 171:3a7713b1edbc 165 #define _MSC_WRITECMD_ERASEPAGE_SHIFT 1 /**< Shift value for MSC_ERASEPAGE */
AnnaBridge 171:3a7713b1edbc 166 #define _MSC_WRITECMD_ERASEPAGE_MASK 0x2UL /**< Bit mask for MSC_ERASEPAGE */
AnnaBridge 171:3a7713b1edbc 167 #define _MSC_WRITECMD_ERASEPAGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 168 #define MSC_WRITECMD_ERASEPAGE_DEFAULT (_MSC_WRITECMD_ERASEPAGE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 169 #define MSC_WRITECMD_WRITEEND (0x1UL << 2) /**< End Write Mode */
AnnaBridge 171:3a7713b1edbc 170 #define _MSC_WRITECMD_WRITEEND_SHIFT 2 /**< Shift value for MSC_WRITEEND */
AnnaBridge 171:3a7713b1edbc 171 #define _MSC_WRITECMD_WRITEEND_MASK 0x4UL /**< Bit mask for MSC_WRITEEND */
AnnaBridge 171:3a7713b1edbc 172 #define _MSC_WRITECMD_WRITEEND_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 173 #define MSC_WRITECMD_WRITEEND_DEFAULT (_MSC_WRITECMD_WRITEEND_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 174 #define MSC_WRITECMD_WRITEONCE (0x1UL << 3) /**< Word Write-Once Trigger */
AnnaBridge 171:3a7713b1edbc 175 #define _MSC_WRITECMD_WRITEONCE_SHIFT 3 /**< Shift value for MSC_WRITEONCE */
AnnaBridge 171:3a7713b1edbc 176 #define _MSC_WRITECMD_WRITEONCE_MASK 0x8UL /**< Bit mask for MSC_WRITEONCE */
AnnaBridge 171:3a7713b1edbc 177 #define _MSC_WRITECMD_WRITEONCE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 178 #define MSC_WRITECMD_WRITEONCE_DEFAULT (_MSC_WRITECMD_WRITEONCE_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 179 #define MSC_WRITECMD_WRITETRIG (0x1UL << 4) /**< Word Write Sequence Trigger */
AnnaBridge 171:3a7713b1edbc 180 #define _MSC_WRITECMD_WRITETRIG_SHIFT 4 /**< Shift value for MSC_WRITETRIG */
AnnaBridge 171:3a7713b1edbc 181 #define _MSC_WRITECMD_WRITETRIG_MASK 0x10UL /**< Bit mask for MSC_WRITETRIG */
AnnaBridge 171:3a7713b1edbc 182 #define _MSC_WRITECMD_WRITETRIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 183 #define MSC_WRITECMD_WRITETRIG_DEFAULT (_MSC_WRITECMD_WRITETRIG_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 184 #define MSC_WRITECMD_ERASEABORT (0x1UL << 5) /**< Abort erase sequence */
AnnaBridge 171:3a7713b1edbc 185 #define _MSC_WRITECMD_ERASEABORT_SHIFT 5 /**< Shift value for MSC_ERASEABORT */
AnnaBridge 171:3a7713b1edbc 186 #define _MSC_WRITECMD_ERASEABORT_MASK 0x20UL /**< Bit mask for MSC_ERASEABORT */
AnnaBridge 171:3a7713b1edbc 187 #define _MSC_WRITECMD_ERASEABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 188 #define MSC_WRITECMD_ERASEABORT_DEFAULT (_MSC_WRITECMD_ERASEABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 189 #define MSC_WRITECMD_ERASEMAIN0 (0x1UL << 8) /**< Mass erase region 0 */
AnnaBridge 171:3a7713b1edbc 190 #define _MSC_WRITECMD_ERASEMAIN0_SHIFT 8 /**< Shift value for MSC_ERASEMAIN0 */
AnnaBridge 171:3a7713b1edbc 191 #define _MSC_WRITECMD_ERASEMAIN0_MASK 0x100UL /**< Bit mask for MSC_ERASEMAIN0 */
AnnaBridge 171:3a7713b1edbc 192 #define _MSC_WRITECMD_ERASEMAIN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 193 #define MSC_WRITECMD_ERASEMAIN0_DEFAULT (_MSC_WRITECMD_ERASEMAIN0_DEFAULT << 8) /**< Shifted mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 194 #define MSC_WRITECMD_CLEARWDATA (0x1UL << 12) /**< Clear WDATA state */
AnnaBridge 171:3a7713b1edbc 195 #define _MSC_WRITECMD_CLEARWDATA_SHIFT 12 /**< Shift value for MSC_CLEARWDATA */
AnnaBridge 171:3a7713b1edbc 196 #define _MSC_WRITECMD_CLEARWDATA_MASK 0x1000UL /**< Bit mask for MSC_CLEARWDATA */
AnnaBridge 171:3a7713b1edbc 197 #define _MSC_WRITECMD_CLEARWDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 198 #define MSC_WRITECMD_CLEARWDATA_DEFAULT (_MSC_WRITECMD_CLEARWDATA_DEFAULT << 12) /**< Shifted mode DEFAULT for MSC_WRITECMD */
AnnaBridge 171:3a7713b1edbc 199
AnnaBridge 171:3a7713b1edbc 200 /* Bit fields for MSC ADDRB */
AnnaBridge 171:3a7713b1edbc 201 #define _MSC_ADDRB_RESETVALUE 0x00000000UL /**< Default value for MSC_ADDRB */
AnnaBridge 171:3a7713b1edbc 202 #define _MSC_ADDRB_MASK 0xFFFFFFFFUL /**< Mask for MSC_ADDRB */
AnnaBridge 171:3a7713b1edbc 203 #define _MSC_ADDRB_ADDRB_SHIFT 0 /**< Shift value for MSC_ADDRB */
AnnaBridge 171:3a7713b1edbc 204 #define _MSC_ADDRB_ADDRB_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_ADDRB */
AnnaBridge 171:3a7713b1edbc 205 #define _MSC_ADDRB_ADDRB_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_ADDRB */
AnnaBridge 171:3a7713b1edbc 206 #define MSC_ADDRB_ADDRB_DEFAULT (_MSC_ADDRB_ADDRB_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_ADDRB */
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 /* Bit fields for MSC WDATA */
AnnaBridge 171:3a7713b1edbc 209 #define _MSC_WDATA_RESETVALUE 0x00000000UL /**< Default value for MSC_WDATA */
AnnaBridge 171:3a7713b1edbc 210 #define _MSC_WDATA_MASK 0xFFFFFFFFUL /**< Mask for MSC_WDATA */
AnnaBridge 171:3a7713b1edbc 211 #define _MSC_WDATA_WDATA_SHIFT 0 /**< Shift value for MSC_WDATA */
AnnaBridge 171:3a7713b1edbc 212 #define _MSC_WDATA_WDATA_MASK 0xFFFFFFFFUL /**< Bit mask for MSC_WDATA */
AnnaBridge 171:3a7713b1edbc 213 #define _MSC_WDATA_WDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_WDATA */
AnnaBridge 171:3a7713b1edbc 214 #define MSC_WDATA_WDATA_DEFAULT (_MSC_WDATA_WDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_WDATA */
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 /* Bit fields for MSC STATUS */
AnnaBridge 171:3a7713b1edbc 217 #define _MSC_STATUS_RESETVALUE 0x00000008UL /**< Default value for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 218 #define _MSC_STATUS_MASK 0x0000007FUL /**< Mask for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 219 #define MSC_STATUS_BUSY (0x1UL << 0) /**< Erase/Write Busy */
AnnaBridge 171:3a7713b1edbc 220 #define _MSC_STATUS_BUSY_SHIFT 0 /**< Shift value for MSC_BUSY */
AnnaBridge 171:3a7713b1edbc 221 #define _MSC_STATUS_BUSY_MASK 0x1UL /**< Bit mask for MSC_BUSY */
AnnaBridge 171:3a7713b1edbc 222 #define _MSC_STATUS_BUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 223 #define MSC_STATUS_BUSY_DEFAULT (_MSC_STATUS_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 224 #define MSC_STATUS_LOCKED (0x1UL << 1) /**< Access Locked */
AnnaBridge 171:3a7713b1edbc 225 #define _MSC_STATUS_LOCKED_SHIFT 1 /**< Shift value for MSC_LOCKED */
AnnaBridge 171:3a7713b1edbc 226 #define _MSC_STATUS_LOCKED_MASK 0x2UL /**< Bit mask for MSC_LOCKED */
AnnaBridge 171:3a7713b1edbc 227 #define _MSC_STATUS_LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 228 #define MSC_STATUS_LOCKED_DEFAULT (_MSC_STATUS_LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 229 #define MSC_STATUS_INVADDR (0x1UL << 2) /**< Invalid Write Address or Erase Page */
AnnaBridge 171:3a7713b1edbc 230 #define _MSC_STATUS_INVADDR_SHIFT 2 /**< Shift value for MSC_INVADDR */
AnnaBridge 171:3a7713b1edbc 231 #define _MSC_STATUS_INVADDR_MASK 0x4UL /**< Bit mask for MSC_INVADDR */
AnnaBridge 171:3a7713b1edbc 232 #define _MSC_STATUS_INVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 233 #define MSC_STATUS_INVADDR_DEFAULT (_MSC_STATUS_INVADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 234 #define MSC_STATUS_WDATAREADY (0x1UL << 3) /**< WDATA Write Ready */
AnnaBridge 171:3a7713b1edbc 235 #define _MSC_STATUS_WDATAREADY_SHIFT 3 /**< Shift value for MSC_WDATAREADY */
AnnaBridge 171:3a7713b1edbc 236 #define _MSC_STATUS_WDATAREADY_MASK 0x8UL /**< Bit mask for MSC_WDATAREADY */
AnnaBridge 171:3a7713b1edbc 237 #define _MSC_STATUS_WDATAREADY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 238 #define MSC_STATUS_WDATAREADY_DEFAULT (_MSC_STATUS_WDATAREADY_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 239 #define MSC_STATUS_WORDTIMEOUT (0x1UL << 4) /**< Flash Write Word Timeout */
AnnaBridge 171:3a7713b1edbc 240 #define _MSC_STATUS_WORDTIMEOUT_SHIFT 4 /**< Shift value for MSC_WORDTIMEOUT */
AnnaBridge 171:3a7713b1edbc 241 #define _MSC_STATUS_WORDTIMEOUT_MASK 0x10UL /**< Bit mask for MSC_WORDTIMEOUT */
AnnaBridge 171:3a7713b1edbc 242 #define _MSC_STATUS_WORDTIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 243 #define MSC_STATUS_WORDTIMEOUT_DEFAULT (_MSC_STATUS_WORDTIMEOUT_DEFAULT << 4) /**< Shifted mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 244 #define MSC_STATUS_ERASEABORTED (0x1UL << 5) /**< The Current Flash Erase Operation Aborted */
AnnaBridge 171:3a7713b1edbc 245 #define _MSC_STATUS_ERASEABORTED_SHIFT 5 /**< Shift value for MSC_ERASEABORTED */
AnnaBridge 171:3a7713b1edbc 246 #define _MSC_STATUS_ERASEABORTED_MASK 0x20UL /**< Bit mask for MSC_ERASEABORTED */
AnnaBridge 171:3a7713b1edbc 247 #define _MSC_STATUS_ERASEABORTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 248 #define MSC_STATUS_ERASEABORTED_DEFAULT (_MSC_STATUS_ERASEABORTED_DEFAULT << 5) /**< Shifted mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 249 #define MSC_STATUS_PCRUNNING (0x1UL << 6) /**< Performance Counters Running */
AnnaBridge 171:3a7713b1edbc 250 #define _MSC_STATUS_PCRUNNING_SHIFT 6 /**< Shift value for MSC_PCRUNNING */
AnnaBridge 171:3a7713b1edbc 251 #define _MSC_STATUS_PCRUNNING_MASK 0x40UL /**< Bit mask for MSC_PCRUNNING */
AnnaBridge 171:3a7713b1edbc 252 #define _MSC_STATUS_PCRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 253 #define MSC_STATUS_PCRUNNING_DEFAULT (_MSC_STATUS_PCRUNNING_DEFAULT << 6) /**< Shifted mode DEFAULT for MSC_STATUS */
AnnaBridge 171:3a7713b1edbc 254
AnnaBridge 171:3a7713b1edbc 255 /* Bit fields for MSC IF */
AnnaBridge 171:3a7713b1edbc 256 #define _MSC_IF_RESETVALUE 0x00000000UL /**< Default value for MSC_IF */
AnnaBridge 171:3a7713b1edbc 257 #define _MSC_IF_MASK 0x0000000FUL /**< Mask for MSC_IF */
AnnaBridge 171:3a7713b1edbc 258 #define MSC_IF_ERASE (0x1UL << 0) /**< Erase Done Interrupt Read Flag */
AnnaBridge 171:3a7713b1edbc 259 #define _MSC_IF_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
AnnaBridge 171:3a7713b1edbc 260 #define _MSC_IF_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
AnnaBridge 171:3a7713b1edbc 261 #define _MSC_IF_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
AnnaBridge 171:3a7713b1edbc 262 #define MSC_IF_ERASE_DEFAULT (_MSC_IF_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IF */
AnnaBridge 171:3a7713b1edbc 263 #define MSC_IF_WRITE (0x1UL << 1) /**< Write Done Interrupt Read Flag */
AnnaBridge 171:3a7713b1edbc 264 #define _MSC_IF_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
AnnaBridge 171:3a7713b1edbc 265 #define _MSC_IF_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
AnnaBridge 171:3a7713b1edbc 266 #define _MSC_IF_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
AnnaBridge 171:3a7713b1edbc 267 #define MSC_IF_WRITE_DEFAULT (_MSC_IF_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IF */
AnnaBridge 171:3a7713b1edbc 268 #define MSC_IF_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 269 #define _MSC_IF_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
AnnaBridge 171:3a7713b1edbc 270 #define _MSC_IF_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
AnnaBridge 171:3a7713b1edbc 271 #define _MSC_IF_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
AnnaBridge 171:3a7713b1edbc 272 #define MSC_IF_CHOF_DEFAULT (_MSC_IF_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IF */
AnnaBridge 171:3a7713b1edbc 273 #define MSC_IF_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 274 #define _MSC_IF_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
AnnaBridge 171:3a7713b1edbc 275 #define _MSC_IF_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
AnnaBridge 171:3a7713b1edbc 276 #define _MSC_IF_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IF */
AnnaBridge 171:3a7713b1edbc 277 #define MSC_IF_CMOF_DEFAULT (_MSC_IF_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IF */
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279 /* Bit fields for MSC IFS */
AnnaBridge 171:3a7713b1edbc 280 #define _MSC_IFS_RESETVALUE 0x00000000UL /**< Default value for MSC_IFS */
AnnaBridge 171:3a7713b1edbc 281 #define _MSC_IFS_MASK 0x0000000FUL /**< Mask for MSC_IFS */
AnnaBridge 171:3a7713b1edbc 282 #define MSC_IFS_ERASE (0x1UL << 0) /**< Erase Done Interrupt Set */
AnnaBridge 171:3a7713b1edbc 283 #define _MSC_IFS_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
AnnaBridge 171:3a7713b1edbc 284 #define _MSC_IFS_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
AnnaBridge 171:3a7713b1edbc 285 #define _MSC_IFS_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
AnnaBridge 171:3a7713b1edbc 286 #define MSC_IFS_ERASE_DEFAULT (_MSC_IFS_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFS */
AnnaBridge 171:3a7713b1edbc 287 #define MSC_IFS_WRITE (0x1UL << 1) /**< Write Done Interrupt Set */
AnnaBridge 171:3a7713b1edbc 288 #define _MSC_IFS_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
AnnaBridge 171:3a7713b1edbc 289 #define _MSC_IFS_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
AnnaBridge 171:3a7713b1edbc 290 #define _MSC_IFS_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
AnnaBridge 171:3a7713b1edbc 291 #define MSC_IFS_WRITE_DEFAULT (_MSC_IFS_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFS */
AnnaBridge 171:3a7713b1edbc 292 #define MSC_IFS_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Set */
AnnaBridge 171:3a7713b1edbc 293 #define _MSC_IFS_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
AnnaBridge 171:3a7713b1edbc 294 #define _MSC_IFS_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
AnnaBridge 171:3a7713b1edbc 295 #define _MSC_IFS_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
AnnaBridge 171:3a7713b1edbc 296 #define MSC_IFS_CHOF_DEFAULT (_MSC_IFS_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFS */
AnnaBridge 171:3a7713b1edbc 297 #define MSC_IFS_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Set */
AnnaBridge 171:3a7713b1edbc 298 #define _MSC_IFS_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
AnnaBridge 171:3a7713b1edbc 299 #define _MSC_IFS_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
AnnaBridge 171:3a7713b1edbc 300 #define _MSC_IFS_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFS */
AnnaBridge 171:3a7713b1edbc 301 #define MSC_IFS_CMOF_DEFAULT (_MSC_IFS_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFS */
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 /* Bit fields for MSC IFC */
AnnaBridge 171:3a7713b1edbc 304 #define _MSC_IFC_RESETVALUE 0x00000000UL /**< Default value for MSC_IFC */
AnnaBridge 171:3a7713b1edbc 305 #define _MSC_IFC_MASK 0x0000000FUL /**< Mask for MSC_IFC */
AnnaBridge 171:3a7713b1edbc 306 #define MSC_IFC_ERASE (0x1UL << 0) /**< Erase Done Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 307 #define _MSC_IFC_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
AnnaBridge 171:3a7713b1edbc 308 #define _MSC_IFC_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
AnnaBridge 171:3a7713b1edbc 309 #define _MSC_IFC_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
AnnaBridge 171:3a7713b1edbc 310 #define MSC_IFC_ERASE_DEFAULT (_MSC_IFC_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IFC */
AnnaBridge 171:3a7713b1edbc 311 #define MSC_IFC_WRITE (0x1UL << 1) /**< Write Done Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 312 #define _MSC_IFC_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
AnnaBridge 171:3a7713b1edbc 313 #define _MSC_IFC_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
AnnaBridge 171:3a7713b1edbc 314 #define _MSC_IFC_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
AnnaBridge 171:3a7713b1edbc 315 #define MSC_IFC_WRITE_DEFAULT (_MSC_IFC_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IFC */
AnnaBridge 171:3a7713b1edbc 316 #define MSC_IFC_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 317 #define _MSC_IFC_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
AnnaBridge 171:3a7713b1edbc 318 #define _MSC_IFC_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
AnnaBridge 171:3a7713b1edbc 319 #define _MSC_IFC_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
AnnaBridge 171:3a7713b1edbc 320 #define MSC_IFC_CHOF_DEFAULT (_MSC_IFC_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IFC */
AnnaBridge 171:3a7713b1edbc 321 #define MSC_IFC_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 322 #define _MSC_IFC_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
AnnaBridge 171:3a7713b1edbc 323 #define _MSC_IFC_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
AnnaBridge 171:3a7713b1edbc 324 #define _MSC_IFC_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IFC */
AnnaBridge 171:3a7713b1edbc 325 #define MSC_IFC_CMOF_DEFAULT (_MSC_IFC_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IFC */
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 /* Bit fields for MSC IEN */
AnnaBridge 171:3a7713b1edbc 328 #define _MSC_IEN_RESETVALUE 0x00000000UL /**< Default value for MSC_IEN */
AnnaBridge 171:3a7713b1edbc 329 #define _MSC_IEN_MASK 0x0000000FUL /**< Mask for MSC_IEN */
AnnaBridge 171:3a7713b1edbc 330 #define MSC_IEN_ERASE (0x1UL << 0) /**< Erase Done Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 331 #define _MSC_IEN_ERASE_SHIFT 0 /**< Shift value for MSC_ERASE */
AnnaBridge 171:3a7713b1edbc 332 #define _MSC_IEN_ERASE_MASK 0x1UL /**< Bit mask for MSC_ERASE */
AnnaBridge 171:3a7713b1edbc 333 #define _MSC_IEN_ERASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
AnnaBridge 171:3a7713b1edbc 334 #define MSC_IEN_ERASE_DEFAULT (_MSC_IEN_ERASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_IEN */
AnnaBridge 171:3a7713b1edbc 335 #define MSC_IEN_WRITE (0x1UL << 1) /**< Write Done Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 336 #define _MSC_IEN_WRITE_SHIFT 1 /**< Shift value for MSC_WRITE */
AnnaBridge 171:3a7713b1edbc 337 #define _MSC_IEN_WRITE_MASK 0x2UL /**< Bit mask for MSC_WRITE */
AnnaBridge 171:3a7713b1edbc 338 #define _MSC_IEN_WRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
AnnaBridge 171:3a7713b1edbc 339 #define MSC_IEN_WRITE_DEFAULT (_MSC_IEN_WRITE_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_IEN */
AnnaBridge 171:3a7713b1edbc 340 #define MSC_IEN_CHOF (0x1UL << 2) /**< Cache Hits Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 341 #define _MSC_IEN_CHOF_SHIFT 2 /**< Shift value for MSC_CHOF */
AnnaBridge 171:3a7713b1edbc 342 #define _MSC_IEN_CHOF_MASK 0x4UL /**< Bit mask for MSC_CHOF */
AnnaBridge 171:3a7713b1edbc 343 #define _MSC_IEN_CHOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
AnnaBridge 171:3a7713b1edbc 344 #define MSC_IEN_CHOF_DEFAULT (_MSC_IEN_CHOF_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_IEN */
AnnaBridge 171:3a7713b1edbc 345 #define MSC_IEN_CMOF (0x1UL << 3) /**< Cache Misses Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 346 #define _MSC_IEN_CMOF_SHIFT 3 /**< Shift value for MSC_CMOF */
AnnaBridge 171:3a7713b1edbc 347 #define _MSC_IEN_CMOF_MASK 0x8UL /**< Bit mask for MSC_CMOF */
AnnaBridge 171:3a7713b1edbc 348 #define _MSC_IEN_CMOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_IEN */
AnnaBridge 171:3a7713b1edbc 349 #define MSC_IEN_CMOF_DEFAULT (_MSC_IEN_CMOF_DEFAULT << 3) /**< Shifted mode DEFAULT for MSC_IEN */
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 /* Bit fields for MSC LOCK */
AnnaBridge 171:3a7713b1edbc 352 #define _MSC_LOCK_RESETVALUE 0x00000000UL /**< Default value for MSC_LOCK */
AnnaBridge 171:3a7713b1edbc 353 #define _MSC_LOCK_MASK 0x0000FFFFUL /**< Mask for MSC_LOCK */
AnnaBridge 171:3a7713b1edbc 354 #define _MSC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
AnnaBridge 171:3a7713b1edbc 355 #define _MSC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
AnnaBridge 171:3a7713b1edbc 356 #define _MSC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_LOCK */
AnnaBridge 171:3a7713b1edbc 357 #define _MSC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_LOCK */
AnnaBridge 171:3a7713b1edbc 358 #define _MSC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_LOCK */
AnnaBridge 171:3a7713b1edbc 359 #define _MSC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_LOCK */
AnnaBridge 171:3a7713b1edbc 360 #define _MSC_LOCK_LOCKKEY_UNLOCK 0x00001B71UL /**< Mode UNLOCK for MSC_LOCK */
AnnaBridge 171:3a7713b1edbc 361 #define MSC_LOCK_LOCKKEY_DEFAULT (_MSC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_LOCK */
AnnaBridge 171:3a7713b1edbc 362 #define MSC_LOCK_LOCKKEY_LOCK (_MSC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_LOCK */
AnnaBridge 171:3a7713b1edbc 363 #define MSC_LOCK_LOCKKEY_UNLOCKED (_MSC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_LOCK */
AnnaBridge 171:3a7713b1edbc 364 #define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_LOCK */
AnnaBridge 171:3a7713b1edbc 365 #define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_LOCK */
AnnaBridge 171:3a7713b1edbc 366
AnnaBridge 171:3a7713b1edbc 367 /* Bit fields for MSC CMD */
AnnaBridge 171:3a7713b1edbc 368 #define _MSC_CMD_RESETVALUE 0x00000000UL /**< Default value for MSC_CMD */
AnnaBridge 171:3a7713b1edbc 369 #define _MSC_CMD_MASK 0x00000007UL /**< Mask for MSC_CMD */
AnnaBridge 171:3a7713b1edbc 370 #define MSC_CMD_INVCACHE (0x1UL << 0) /**< Invalidate Instruction Cache */
AnnaBridge 171:3a7713b1edbc 371 #define _MSC_CMD_INVCACHE_SHIFT 0 /**< Shift value for MSC_INVCACHE */
AnnaBridge 171:3a7713b1edbc 372 #define _MSC_CMD_INVCACHE_MASK 0x1UL /**< Bit mask for MSC_INVCACHE */
AnnaBridge 171:3a7713b1edbc 373 #define _MSC_CMD_INVCACHE_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
AnnaBridge 171:3a7713b1edbc 374 #define MSC_CMD_INVCACHE_DEFAULT (_MSC_CMD_INVCACHE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CMD */
AnnaBridge 171:3a7713b1edbc 375 #define MSC_CMD_STARTPC (0x1UL << 1) /**< Start Performance Counters */
AnnaBridge 171:3a7713b1edbc 376 #define _MSC_CMD_STARTPC_SHIFT 1 /**< Shift value for MSC_STARTPC */
AnnaBridge 171:3a7713b1edbc 377 #define _MSC_CMD_STARTPC_MASK 0x2UL /**< Bit mask for MSC_STARTPC */
AnnaBridge 171:3a7713b1edbc 378 #define _MSC_CMD_STARTPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
AnnaBridge 171:3a7713b1edbc 379 #define MSC_CMD_STARTPC_DEFAULT (_MSC_CMD_STARTPC_DEFAULT << 1) /**< Shifted mode DEFAULT for MSC_CMD */
AnnaBridge 171:3a7713b1edbc 380 #define MSC_CMD_STOPPC (0x1UL << 2) /**< Stop Performance Counters */
AnnaBridge 171:3a7713b1edbc 381 #define _MSC_CMD_STOPPC_SHIFT 2 /**< Shift value for MSC_STOPPC */
AnnaBridge 171:3a7713b1edbc 382 #define _MSC_CMD_STOPPC_MASK 0x4UL /**< Bit mask for MSC_STOPPC */
AnnaBridge 171:3a7713b1edbc 383 #define _MSC_CMD_STOPPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CMD */
AnnaBridge 171:3a7713b1edbc 384 #define MSC_CMD_STOPPC_DEFAULT (_MSC_CMD_STOPPC_DEFAULT << 2) /**< Shifted mode DEFAULT for MSC_CMD */
AnnaBridge 171:3a7713b1edbc 385
AnnaBridge 171:3a7713b1edbc 386 /* Bit fields for MSC CACHEHITS */
AnnaBridge 171:3a7713b1edbc 387 #define _MSC_CACHEHITS_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEHITS */
AnnaBridge 171:3a7713b1edbc 388 #define _MSC_CACHEHITS_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEHITS */
AnnaBridge 171:3a7713b1edbc 389 #define _MSC_CACHEHITS_CACHEHITS_SHIFT 0 /**< Shift value for MSC_CACHEHITS */
AnnaBridge 171:3a7713b1edbc 390 #define _MSC_CACHEHITS_CACHEHITS_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEHITS */
AnnaBridge 171:3a7713b1edbc 391 #define _MSC_CACHEHITS_CACHEHITS_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEHITS */
AnnaBridge 171:3a7713b1edbc 392 #define MSC_CACHEHITS_CACHEHITS_DEFAULT (_MSC_CACHEHITS_CACHEHITS_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEHITS */
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394 /* Bit fields for MSC CACHEMISSES */
AnnaBridge 171:3a7713b1edbc 395 #define _MSC_CACHEMISSES_RESETVALUE 0x00000000UL /**< Default value for MSC_CACHEMISSES */
AnnaBridge 171:3a7713b1edbc 396 #define _MSC_CACHEMISSES_MASK 0x000FFFFFUL /**< Mask for MSC_CACHEMISSES */
AnnaBridge 171:3a7713b1edbc 397 #define _MSC_CACHEMISSES_CACHEMISSES_SHIFT 0 /**< Shift value for MSC_CACHEMISSES */
AnnaBridge 171:3a7713b1edbc 398 #define _MSC_CACHEMISSES_CACHEMISSES_MASK 0xFFFFFUL /**< Bit mask for MSC_CACHEMISSES */
AnnaBridge 171:3a7713b1edbc 399 #define _MSC_CACHEMISSES_CACHEMISSES_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_CACHEMISSES */
AnnaBridge 171:3a7713b1edbc 400 #define MSC_CACHEMISSES_CACHEMISSES_DEFAULT (_MSC_CACHEMISSES_CACHEMISSES_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_CACHEMISSES */
AnnaBridge 171:3a7713b1edbc 401
AnnaBridge 171:3a7713b1edbc 402 /* Bit fields for MSC TIMEBASE */
AnnaBridge 171:3a7713b1edbc 403 #define _MSC_TIMEBASE_RESETVALUE 0x00000010UL /**< Default value for MSC_TIMEBASE */
AnnaBridge 171:3a7713b1edbc 404 #define _MSC_TIMEBASE_MASK 0x0001003FUL /**< Mask for MSC_TIMEBASE */
AnnaBridge 171:3a7713b1edbc 405 #define _MSC_TIMEBASE_BASE_SHIFT 0 /**< Shift value for MSC_BASE */
AnnaBridge 171:3a7713b1edbc 406 #define _MSC_TIMEBASE_BASE_MASK 0x3FUL /**< Bit mask for MSC_BASE */
AnnaBridge 171:3a7713b1edbc 407 #define _MSC_TIMEBASE_BASE_DEFAULT 0x00000010UL /**< Mode DEFAULT for MSC_TIMEBASE */
AnnaBridge 171:3a7713b1edbc 408 #define MSC_TIMEBASE_BASE_DEFAULT (_MSC_TIMEBASE_BASE_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_TIMEBASE */
AnnaBridge 171:3a7713b1edbc 409 #define MSC_TIMEBASE_PERIOD (0x1UL << 16) /**< Sets the timebase period */
AnnaBridge 171:3a7713b1edbc 410 #define _MSC_TIMEBASE_PERIOD_SHIFT 16 /**< Shift value for MSC_PERIOD */
AnnaBridge 171:3a7713b1edbc 411 #define _MSC_TIMEBASE_PERIOD_MASK 0x10000UL /**< Bit mask for MSC_PERIOD */
AnnaBridge 171:3a7713b1edbc 412 #define _MSC_TIMEBASE_PERIOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for MSC_TIMEBASE */
AnnaBridge 171:3a7713b1edbc 413 #define _MSC_TIMEBASE_PERIOD_1US 0x00000000UL /**< Mode 1US for MSC_TIMEBASE */
AnnaBridge 171:3a7713b1edbc 414 #define _MSC_TIMEBASE_PERIOD_5US 0x00000001UL /**< Mode 5US for MSC_TIMEBASE */
AnnaBridge 171:3a7713b1edbc 415 #define MSC_TIMEBASE_PERIOD_DEFAULT (_MSC_TIMEBASE_PERIOD_DEFAULT << 16) /**< Shifted mode DEFAULT for MSC_TIMEBASE */
AnnaBridge 171:3a7713b1edbc 416 #define MSC_TIMEBASE_PERIOD_1US (_MSC_TIMEBASE_PERIOD_1US << 16) /**< Shifted mode 1US for MSC_TIMEBASE */
AnnaBridge 171:3a7713b1edbc 417 #define MSC_TIMEBASE_PERIOD_5US (_MSC_TIMEBASE_PERIOD_5US << 16) /**< Shifted mode 5US for MSC_TIMEBASE */
AnnaBridge 171:3a7713b1edbc 418
AnnaBridge 171:3a7713b1edbc 419 /* Bit fields for MSC MASSLOCK */
AnnaBridge 171:3a7713b1edbc 420 #define _MSC_MASSLOCK_RESETVALUE 0x00000001UL /**< Default value for MSC_MASSLOCK */
AnnaBridge 171:3a7713b1edbc 421 #define _MSC_MASSLOCK_MASK 0x0000FFFFUL /**< Mask for MSC_MASSLOCK */
AnnaBridge 171:3a7713b1edbc 422 #define _MSC_MASSLOCK_LOCKKEY_SHIFT 0 /**< Shift value for MSC_LOCKKEY */
AnnaBridge 171:3a7713b1edbc 423 #define _MSC_MASSLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for MSC_LOCKKEY */
AnnaBridge 171:3a7713b1edbc 424 #define _MSC_MASSLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for MSC_MASSLOCK */
AnnaBridge 171:3a7713b1edbc 425 #define _MSC_MASSLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for MSC_MASSLOCK */
AnnaBridge 171:3a7713b1edbc 426 #define _MSC_MASSLOCK_LOCKKEY_DEFAULT 0x00000001UL /**< Mode DEFAULT for MSC_MASSLOCK */
AnnaBridge 171:3a7713b1edbc 427 #define _MSC_MASSLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for MSC_MASSLOCK */
AnnaBridge 171:3a7713b1edbc 428 #define _MSC_MASSLOCK_LOCKKEY_UNLOCK 0x0000631AUL /**< Mode UNLOCK for MSC_MASSLOCK */
AnnaBridge 171:3a7713b1edbc 429 #define MSC_MASSLOCK_LOCKKEY_LOCK (_MSC_MASSLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for MSC_MASSLOCK */
AnnaBridge 171:3a7713b1edbc 430 #define MSC_MASSLOCK_LOCKKEY_UNLOCKED (_MSC_MASSLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for MSC_MASSLOCK */
AnnaBridge 171:3a7713b1edbc 431 #define MSC_MASSLOCK_LOCKKEY_DEFAULT (_MSC_MASSLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for MSC_MASSLOCK */
AnnaBridge 171:3a7713b1edbc 432 #define MSC_MASSLOCK_LOCKKEY_LOCKED (_MSC_MASSLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for MSC_MASSLOCK */
AnnaBridge 171:3a7713b1edbc 433 #define MSC_MASSLOCK_LOCKKEY_UNLOCK (_MSC_MASSLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for MSC_MASSLOCK */
AnnaBridge 171:3a7713b1edbc 434
AnnaBridge 171:3a7713b1edbc 435 /** @} End of group EFM32WG_MSC */
AnnaBridge 171:3a7713b1edbc 436 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 437