mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_EFM32WG_STK3800/TOOLCHAIN_ARM_MICRO/efm32wg_i2c.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32wg_i2c.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32WG_I2C register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32WG_I2C
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32WG_I2C Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IOM uint32_t CTRL; /**< Control Register */
AnnaBridge 171:3a7713b1edbc 44 __IOM uint32_t CMD; /**< Command Register */
AnnaBridge 171:3a7713b1edbc 45 __IM uint32_t STATE; /**< State Register */
AnnaBridge 171:3a7713b1edbc 46 __IM uint32_t STATUS; /**< Status Register */
AnnaBridge 171:3a7713b1edbc 47 __IOM uint32_t CLKDIV; /**< Clock Division Register */
AnnaBridge 171:3a7713b1edbc 48 __IOM uint32_t SADDR; /**< Slave Address Register */
AnnaBridge 171:3a7713b1edbc 49 __IOM uint32_t SADDRMASK; /**< Slave Address Mask Register */
AnnaBridge 171:3a7713b1edbc 50 __IM uint32_t RXDATA; /**< Receive Buffer Data Register */
AnnaBridge 171:3a7713b1edbc 51 __IM uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */
AnnaBridge 171:3a7713b1edbc 52 __IOM uint32_t TXDATA; /**< Transmit Buffer Data Register */
AnnaBridge 171:3a7713b1edbc 53 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 54 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 171:3a7713b1edbc 55 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 171:3a7713b1edbc 56 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 57 __IOM uint32_t ROUTE; /**< I/O Routing Register */
AnnaBridge 171:3a7713b1edbc 58 } I2C_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 61 * @defgroup EFM32WG_I2C_BitFields
AnnaBridge 171:3a7713b1edbc 62 * @{
AnnaBridge 171:3a7713b1edbc 63 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 /* Bit fields for I2C CTRL */
AnnaBridge 171:3a7713b1edbc 66 #define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 67 #define _I2C_CTRL_MASK 0x0007B37FUL /**< Mask for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 68 #define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */
AnnaBridge 171:3a7713b1edbc 69 #define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */
AnnaBridge 171:3a7713b1edbc 70 #define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */
AnnaBridge 171:3a7713b1edbc 71 #define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 72 #define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 73 #define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */
AnnaBridge 171:3a7713b1edbc 74 #define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */
AnnaBridge 171:3a7713b1edbc 75 #define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */
AnnaBridge 171:3a7713b1edbc 76 #define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 77 #define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 78 #define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */
AnnaBridge 171:3a7713b1edbc 79 #define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */
AnnaBridge 171:3a7713b1edbc 80 #define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */
AnnaBridge 171:3a7713b1edbc 81 #define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 82 #define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 83 #define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */
AnnaBridge 171:3a7713b1edbc 84 #define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */
AnnaBridge 171:3a7713b1edbc 85 #define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */
AnnaBridge 171:3a7713b1edbc 86 #define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 87 #define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 88 #define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */
AnnaBridge 171:3a7713b1edbc 89 #define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */
AnnaBridge 171:3a7713b1edbc 90 #define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */
AnnaBridge 171:3a7713b1edbc 91 #define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 92 #define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 93 #define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */
AnnaBridge 171:3a7713b1edbc 94 #define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */
AnnaBridge 171:3a7713b1edbc 95 #define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */
AnnaBridge 171:3a7713b1edbc 96 #define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 97 #define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 98 #define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */
AnnaBridge 171:3a7713b1edbc 99 #define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */
AnnaBridge 171:3a7713b1edbc 100 #define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */
AnnaBridge 171:3a7713b1edbc 101 #define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 102 #define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 103 #define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */
AnnaBridge 171:3a7713b1edbc 104 #define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */
AnnaBridge 171:3a7713b1edbc 105 #define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 106 #define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 107 #define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 108 #define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 109 #define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 110 #define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 111 #define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 112 #define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 113 #define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */
AnnaBridge 171:3a7713b1edbc 114 #define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */
AnnaBridge 171:3a7713b1edbc 115 #define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 116 #define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 117 #define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 118 #define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 119 #define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 120 #define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 121 #define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 122 #define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 123 #define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 124 #define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 125 #define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */
AnnaBridge 171:3a7713b1edbc 126 #define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */
AnnaBridge 171:3a7713b1edbc 127 #define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */
AnnaBridge 171:3a7713b1edbc 128 #define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 129 #define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 130 #define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */
AnnaBridge 171:3a7713b1edbc 131 #define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */
AnnaBridge 171:3a7713b1edbc 132 #define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 133 #define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 134 #define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 135 #define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 136 #define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 137 #define _I2C_CTRL_CLTO_320PPC 0x00000004UL /**< Mode 320PPC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 138 #define _I2C_CTRL_CLTO_1024PPC 0x00000005UL /**< Mode 1024PPC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 139 #define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 140 #define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 141 #define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 142 #define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 143 #define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 144 #define I2C_CTRL_CLTO_320PPC (_I2C_CTRL_CLTO_320PPC << 16) /**< Shifted mode 320PPC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 145 #define I2C_CTRL_CLTO_1024PPC (_I2C_CTRL_CLTO_1024PPC << 16) /**< Shifted mode 1024PPC for I2C_CTRL */
AnnaBridge 171:3a7713b1edbc 146
AnnaBridge 171:3a7713b1edbc 147 /* Bit fields for I2C CMD */
AnnaBridge 171:3a7713b1edbc 148 #define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 149 #define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 150 #define I2C_CMD_START (0x1UL << 0) /**< Send start condition */
AnnaBridge 171:3a7713b1edbc 151 #define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */
AnnaBridge 171:3a7713b1edbc 152 #define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */
AnnaBridge 171:3a7713b1edbc 153 #define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 154 #define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 155 #define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */
AnnaBridge 171:3a7713b1edbc 156 #define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */
AnnaBridge 171:3a7713b1edbc 157 #define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */
AnnaBridge 171:3a7713b1edbc 158 #define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 159 #define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 160 #define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */
AnnaBridge 171:3a7713b1edbc 161 #define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */
AnnaBridge 171:3a7713b1edbc 162 #define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */
AnnaBridge 171:3a7713b1edbc 163 #define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 164 #define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 165 #define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */
AnnaBridge 171:3a7713b1edbc 166 #define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */
AnnaBridge 171:3a7713b1edbc 167 #define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */
AnnaBridge 171:3a7713b1edbc 168 #define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 169 #define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 170 #define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */
AnnaBridge 171:3a7713b1edbc 171 #define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */
AnnaBridge 171:3a7713b1edbc 172 #define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */
AnnaBridge 171:3a7713b1edbc 173 #define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 174 #define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 175 #define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */
AnnaBridge 171:3a7713b1edbc 176 #define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */
AnnaBridge 171:3a7713b1edbc 177 #define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */
AnnaBridge 171:3a7713b1edbc 178 #define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 179 #define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 180 #define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */
AnnaBridge 171:3a7713b1edbc 181 #define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */
AnnaBridge 171:3a7713b1edbc 182 #define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */
AnnaBridge 171:3a7713b1edbc 183 #define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 184 #define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 185 #define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */
AnnaBridge 171:3a7713b1edbc 186 #define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */
AnnaBridge 171:3a7713b1edbc 187 #define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */
AnnaBridge 171:3a7713b1edbc 188 #define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 189 #define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 /* Bit fields for I2C STATE */
AnnaBridge 171:3a7713b1edbc 192 #define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 193 #define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 194 #define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */
AnnaBridge 171:3a7713b1edbc 195 #define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */
AnnaBridge 171:3a7713b1edbc 196 #define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */
AnnaBridge 171:3a7713b1edbc 197 #define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 198 #define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 199 #define I2C_STATE_MASTER (0x1UL << 1) /**< Master */
AnnaBridge 171:3a7713b1edbc 200 #define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */
AnnaBridge 171:3a7713b1edbc 201 #define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */
AnnaBridge 171:3a7713b1edbc 202 #define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 203 #define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 204 #define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */
AnnaBridge 171:3a7713b1edbc 205 #define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */
AnnaBridge 171:3a7713b1edbc 206 #define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */
AnnaBridge 171:3a7713b1edbc 207 #define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 208 #define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 209 #define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */
AnnaBridge 171:3a7713b1edbc 210 #define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */
AnnaBridge 171:3a7713b1edbc 211 #define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */
AnnaBridge 171:3a7713b1edbc 212 #define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 213 #define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 214 #define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */
AnnaBridge 171:3a7713b1edbc 215 #define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */
AnnaBridge 171:3a7713b1edbc 216 #define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */
AnnaBridge 171:3a7713b1edbc 217 #define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 218 #define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 219 #define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 220 #define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 221 #define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 222 #define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 223 #define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 224 #define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 225 #define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 226 #define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 227 #define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 228 #define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 229 #define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 230 #define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 231 #define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 232 #define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 233 #define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 234 #define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 235 #define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 236 #define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */
AnnaBridge 171:3a7713b1edbc 237
AnnaBridge 171:3a7713b1edbc 238 /* Bit fields for I2C STATUS */
AnnaBridge 171:3a7713b1edbc 239 #define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 240 #define _I2C_STATUS_MASK 0x000001FFUL /**< Mask for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 241 #define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */
AnnaBridge 171:3a7713b1edbc 242 #define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */
AnnaBridge 171:3a7713b1edbc 243 #define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */
AnnaBridge 171:3a7713b1edbc 244 #define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 245 #define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 246 #define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */
AnnaBridge 171:3a7713b1edbc 247 #define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */
AnnaBridge 171:3a7713b1edbc 248 #define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */
AnnaBridge 171:3a7713b1edbc 249 #define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 250 #define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 251 #define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */
AnnaBridge 171:3a7713b1edbc 252 #define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */
AnnaBridge 171:3a7713b1edbc 253 #define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */
AnnaBridge 171:3a7713b1edbc 254 #define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 255 #define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 256 #define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */
AnnaBridge 171:3a7713b1edbc 257 #define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */
AnnaBridge 171:3a7713b1edbc 258 #define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */
AnnaBridge 171:3a7713b1edbc 259 #define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 260 #define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 261 #define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */
AnnaBridge 171:3a7713b1edbc 262 #define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */
AnnaBridge 171:3a7713b1edbc 263 #define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */
AnnaBridge 171:3a7713b1edbc 264 #define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 265 #define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 266 #define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */
AnnaBridge 171:3a7713b1edbc 267 #define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */
AnnaBridge 171:3a7713b1edbc 268 #define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */
AnnaBridge 171:3a7713b1edbc 269 #define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 270 #define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 271 #define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */
AnnaBridge 171:3a7713b1edbc 272 #define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */
AnnaBridge 171:3a7713b1edbc 273 #define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */
AnnaBridge 171:3a7713b1edbc 274 #define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 275 #define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 276 #define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */
AnnaBridge 171:3a7713b1edbc 277 #define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */
AnnaBridge 171:3a7713b1edbc 278 #define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */
AnnaBridge 171:3a7713b1edbc 279 #define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 280 #define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 281 #define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */
AnnaBridge 171:3a7713b1edbc 282 #define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */
AnnaBridge 171:3a7713b1edbc 283 #define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */
AnnaBridge 171:3a7713b1edbc 284 #define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 285 #define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 /* Bit fields for I2C CLKDIV */
AnnaBridge 171:3a7713b1edbc 288 #define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */
AnnaBridge 171:3a7713b1edbc 289 #define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */
AnnaBridge 171:3a7713b1edbc 290 #define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */
AnnaBridge 171:3a7713b1edbc 291 #define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */
AnnaBridge 171:3a7713b1edbc 292 #define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */
AnnaBridge 171:3a7713b1edbc 293 #define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 /* Bit fields for I2C SADDR */
AnnaBridge 171:3a7713b1edbc 296 #define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */
AnnaBridge 171:3a7713b1edbc 297 #define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */
AnnaBridge 171:3a7713b1edbc 298 #define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */
AnnaBridge 171:3a7713b1edbc 299 #define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */
AnnaBridge 171:3a7713b1edbc 300 #define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */
AnnaBridge 171:3a7713b1edbc 301 #define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 /* Bit fields for I2C SADDRMASK */
AnnaBridge 171:3a7713b1edbc 304 #define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */
AnnaBridge 171:3a7713b1edbc 305 #define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */
AnnaBridge 171:3a7713b1edbc 306 #define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */
AnnaBridge 171:3a7713b1edbc 307 #define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */
AnnaBridge 171:3a7713b1edbc 308 #define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */
AnnaBridge 171:3a7713b1edbc 309 #define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */
AnnaBridge 171:3a7713b1edbc 310
AnnaBridge 171:3a7713b1edbc 311 /* Bit fields for I2C RXDATA */
AnnaBridge 171:3a7713b1edbc 312 #define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */
AnnaBridge 171:3a7713b1edbc 313 #define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */
AnnaBridge 171:3a7713b1edbc 314 #define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */
AnnaBridge 171:3a7713b1edbc 315 #define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */
AnnaBridge 171:3a7713b1edbc 316 #define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */
AnnaBridge 171:3a7713b1edbc 317 #define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319 /* Bit fields for I2C RXDATAP */
AnnaBridge 171:3a7713b1edbc 320 #define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */
AnnaBridge 171:3a7713b1edbc 321 #define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */
AnnaBridge 171:3a7713b1edbc 322 #define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */
AnnaBridge 171:3a7713b1edbc 323 #define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */
AnnaBridge 171:3a7713b1edbc 324 #define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */
AnnaBridge 171:3a7713b1edbc 325 #define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 /* Bit fields for I2C TXDATA */
AnnaBridge 171:3a7713b1edbc 328 #define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */
AnnaBridge 171:3a7713b1edbc 329 #define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */
AnnaBridge 171:3a7713b1edbc 330 #define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */
AnnaBridge 171:3a7713b1edbc 331 #define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */
AnnaBridge 171:3a7713b1edbc 332 #define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */
AnnaBridge 171:3a7713b1edbc 333 #define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */
AnnaBridge 171:3a7713b1edbc 334
AnnaBridge 171:3a7713b1edbc 335 /* Bit fields for I2C IF */
AnnaBridge 171:3a7713b1edbc 336 #define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */
AnnaBridge 171:3a7713b1edbc 337 #define _I2C_IF_MASK 0x0001FFFFUL /**< Mask for I2C_IF */
AnnaBridge 171:3a7713b1edbc 338 #define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 339 #define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */
AnnaBridge 171:3a7713b1edbc 340 #define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */
AnnaBridge 171:3a7713b1edbc 341 #define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 342 #define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 343 #define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 344 #define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
AnnaBridge 171:3a7713b1edbc 345 #define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
AnnaBridge 171:3a7713b1edbc 346 #define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 347 #define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 348 #define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 349 #define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
AnnaBridge 171:3a7713b1edbc 350 #define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
AnnaBridge 171:3a7713b1edbc 351 #define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 352 #define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 353 #define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 354 #define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
AnnaBridge 171:3a7713b1edbc 355 #define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
AnnaBridge 171:3a7713b1edbc 356 #define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 357 #define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 358 #define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 359 #define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
AnnaBridge 171:3a7713b1edbc 360 #define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
AnnaBridge 171:3a7713b1edbc 361 #define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 362 #define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 363 #define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 364 #define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
AnnaBridge 171:3a7713b1edbc 365 #define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
AnnaBridge 171:3a7713b1edbc 366 #define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 367 #define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 368 #define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 369 #define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
AnnaBridge 171:3a7713b1edbc 370 #define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
AnnaBridge 171:3a7713b1edbc 371 #define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 372 #define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 373 #define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 374 #define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
AnnaBridge 171:3a7713b1edbc 375 #define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
AnnaBridge 171:3a7713b1edbc 376 #define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 377 #define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 378 #define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 379 #define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
AnnaBridge 171:3a7713b1edbc 380 #define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
AnnaBridge 171:3a7713b1edbc 381 #define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 382 #define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 383 #define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 384 #define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
AnnaBridge 171:3a7713b1edbc 385 #define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
AnnaBridge 171:3a7713b1edbc 386 #define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 387 #define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 388 #define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 389 #define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
AnnaBridge 171:3a7713b1edbc 390 #define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
AnnaBridge 171:3a7713b1edbc 391 #define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 392 #define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 393 #define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 394 #define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
AnnaBridge 171:3a7713b1edbc 395 #define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
AnnaBridge 171:3a7713b1edbc 396 #define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 397 #define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 398 #define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 399 #define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
AnnaBridge 171:3a7713b1edbc 400 #define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
AnnaBridge 171:3a7713b1edbc 401 #define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 402 #define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 403 #define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 404 #define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
AnnaBridge 171:3a7713b1edbc 405 #define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
AnnaBridge 171:3a7713b1edbc 406 #define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 407 #define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 408 #define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 409 #define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
AnnaBridge 171:3a7713b1edbc 410 #define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
AnnaBridge 171:3a7713b1edbc 411 #define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 412 #define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 413 #define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 414 #define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
AnnaBridge 171:3a7713b1edbc 415 #define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
AnnaBridge 171:3a7713b1edbc 416 #define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 417 #define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 418 #define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 419 #define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
AnnaBridge 171:3a7713b1edbc 420 #define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
AnnaBridge 171:3a7713b1edbc 421 #define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 422 #define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */
AnnaBridge 171:3a7713b1edbc 423
AnnaBridge 171:3a7713b1edbc 424 /* Bit fields for I2C IFS */
AnnaBridge 171:3a7713b1edbc 425 #define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 426 #define _I2C_IFS_MASK 0x0001FFCFUL /**< Mask for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 427 #define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 428 #define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */
AnnaBridge 171:3a7713b1edbc 429 #define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */
AnnaBridge 171:3a7713b1edbc 430 #define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 431 #define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 432 #define I2C_IFS_RSTART (0x1UL << 1) /**< Set Repeated START Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 433 #define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
AnnaBridge 171:3a7713b1edbc 434 #define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
AnnaBridge 171:3a7713b1edbc 435 #define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 436 #define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 437 #define I2C_IFS_ADDR (0x1UL << 2) /**< Set Address Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 438 #define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
AnnaBridge 171:3a7713b1edbc 439 #define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
AnnaBridge 171:3a7713b1edbc 440 #define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 441 #define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 442 #define I2C_IFS_TXC (0x1UL << 3) /**< Set Transfer Completed Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 443 #define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
AnnaBridge 171:3a7713b1edbc 444 #define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
AnnaBridge 171:3a7713b1edbc 445 #define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 446 #define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 447 #define I2C_IFS_ACK (0x1UL << 6) /**< Set Acknowledge Received Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 448 #define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
AnnaBridge 171:3a7713b1edbc 449 #define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
AnnaBridge 171:3a7713b1edbc 450 #define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 451 #define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 452 #define I2C_IFS_NACK (0x1UL << 7) /**< Set Not Acknowledge Received Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 453 #define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
AnnaBridge 171:3a7713b1edbc 454 #define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
AnnaBridge 171:3a7713b1edbc 455 #define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 456 #define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 457 #define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 458 #define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
AnnaBridge 171:3a7713b1edbc 459 #define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
AnnaBridge 171:3a7713b1edbc 460 #define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 461 #define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 462 #define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set Arbitration Lost Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 463 #define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
AnnaBridge 171:3a7713b1edbc 464 #define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
AnnaBridge 171:3a7713b1edbc 465 #define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 466 #define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 467 #define I2C_IFS_BUSERR (0x1UL << 10) /**< Set Bus Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 468 #define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
AnnaBridge 171:3a7713b1edbc 469 #define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
AnnaBridge 171:3a7713b1edbc 470 #define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 471 #define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 472 #define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set Bus Held Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 473 #define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
AnnaBridge 171:3a7713b1edbc 474 #define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
AnnaBridge 171:3a7713b1edbc 475 #define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 476 #define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 477 #define I2C_IFS_TXOF (0x1UL << 12) /**< Set Transmit Buffer Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 478 #define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
AnnaBridge 171:3a7713b1edbc 479 #define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
AnnaBridge 171:3a7713b1edbc 480 #define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 481 #define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 482 #define I2C_IFS_RXUF (0x1UL << 13) /**< Set Receive Buffer Underflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 483 #define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
AnnaBridge 171:3a7713b1edbc 484 #define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
AnnaBridge 171:3a7713b1edbc 485 #define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 486 #define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 487 #define I2C_IFS_BITO (0x1UL << 14) /**< Set Bus Idle Timeout Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 488 #define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
AnnaBridge 171:3a7713b1edbc 489 #define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
AnnaBridge 171:3a7713b1edbc 490 #define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 491 #define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 492 #define I2C_IFS_CLTO (0x1UL << 15) /**< Set Clock Low Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 493 #define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
AnnaBridge 171:3a7713b1edbc 494 #define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
AnnaBridge 171:3a7713b1edbc 495 #define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 496 #define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 497 #define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 498 #define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
AnnaBridge 171:3a7713b1edbc 499 #define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
AnnaBridge 171:3a7713b1edbc 500 #define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 501 #define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */
AnnaBridge 171:3a7713b1edbc 502
AnnaBridge 171:3a7713b1edbc 503 /* Bit fields for I2C IFC */
AnnaBridge 171:3a7713b1edbc 504 #define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 505 #define _I2C_IFC_MASK 0x0001FFCFUL /**< Mask for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 506 #define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 507 #define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */
AnnaBridge 171:3a7713b1edbc 508 #define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */
AnnaBridge 171:3a7713b1edbc 509 #define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 510 #define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 511 #define I2C_IFC_RSTART (0x1UL << 1) /**< Clear Repeated START Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 512 #define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
AnnaBridge 171:3a7713b1edbc 513 #define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
AnnaBridge 171:3a7713b1edbc 514 #define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 515 #define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 516 #define I2C_IFC_ADDR (0x1UL << 2) /**< Clear Address Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 517 #define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
AnnaBridge 171:3a7713b1edbc 518 #define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
AnnaBridge 171:3a7713b1edbc 519 #define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 520 #define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 521 #define I2C_IFC_TXC (0x1UL << 3) /**< Clear Transfer Completed Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 522 #define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
AnnaBridge 171:3a7713b1edbc 523 #define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
AnnaBridge 171:3a7713b1edbc 524 #define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 525 #define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 526 #define I2C_IFC_ACK (0x1UL << 6) /**< Clear Acknowledge Received Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 527 #define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
AnnaBridge 171:3a7713b1edbc 528 #define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
AnnaBridge 171:3a7713b1edbc 529 #define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 530 #define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 531 #define I2C_IFC_NACK (0x1UL << 7) /**< Clear Not Acknowledge Received Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 532 #define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
AnnaBridge 171:3a7713b1edbc 533 #define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
AnnaBridge 171:3a7713b1edbc 534 #define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 535 #define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 536 #define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 537 #define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
AnnaBridge 171:3a7713b1edbc 538 #define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
AnnaBridge 171:3a7713b1edbc 539 #define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 540 #define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 541 #define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear Arbitration Lost Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 542 #define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
AnnaBridge 171:3a7713b1edbc 543 #define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
AnnaBridge 171:3a7713b1edbc 544 #define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 545 #define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 546 #define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear Bus Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 547 #define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
AnnaBridge 171:3a7713b1edbc 548 #define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
AnnaBridge 171:3a7713b1edbc 549 #define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 550 #define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 551 #define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear Bus Held Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 552 #define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
AnnaBridge 171:3a7713b1edbc 553 #define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
AnnaBridge 171:3a7713b1edbc 554 #define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 555 #define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 556 #define I2C_IFC_TXOF (0x1UL << 12) /**< Clear Transmit Buffer Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 557 #define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
AnnaBridge 171:3a7713b1edbc 558 #define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
AnnaBridge 171:3a7713b1edbc 559 #define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 560 #define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 561 #define I2C_IFC_RXUF (0x1UL << 13) /**< Clear Receive Buffer Underflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 562 #define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
AnnaBridge 171:3a7713b1edbc 563 #define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
AnnaBridge 171:3a7713b1edbc 564 #define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 565 #define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 566 #define I2C_IFC_BITO (0x1UL << 14) /**< Clear Bus Idle Timeout Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 567 #define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
AnnaBridge 171:3a7713b1edbc 568 #define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
AnnaBridge 171:3a7713b1edbc 569 #define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 570 #define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 571 #define I2C_IFC_CLTO (0x1UL << 15) /**< Clear Clock Low Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 572 #define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
AnnaBridge 171:3a7713b1edbc 573 #define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
AnnaBridge 171:3a7713b1edbc 574 #define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 575 #define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 576 #define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 577 #define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
AnnaBridge 171:3a7713b1edbc 578 #define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
AnnaBridge 171:3a7713b1edbc 579 #define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 580 #define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */
AnnaBridge 171:3a7713b1edbc 581
AnnaBridge 171:3a7713b1edbc 582 /* Bit fields for I2C IEN */
AnnaBridge 171:3a7713b1edbc 583 #define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 584 #define _I2C_IEN_MASK 0x0001FFFFUL /**< Mask for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 585 #define I2C_IEN_START (0x1UL << 0) /**< START Condition Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 586 #define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */
AnnaBridge 171:3a7713b1edbc 587 #define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */
AnnaBridge 171:3a7713b1edbc 588 #define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 589 #define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 590 #define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 591 #define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */
AnnaBridge 171:3a7713b1edbc 592 #define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */
AnnaBridge 171:3a7713b1edbc 593 #define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 594 #define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 595 #define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 596 #define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */
AnnaBridge 171:3a7713b1edbc 597 #define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */
AnnaBridge 171:3a7713b1edbc 598 #define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 599 #define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 600 #define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 601 #define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */
AnnaBridge 171:3a7713b1edbc 602 #define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */
AnnaBridge 171:3a7713b1edbc 603 #define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 604 #define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 605 #define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer level Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 606 #define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */
AnnaBridge 171:3a7713b1edbc 607 #define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */
AnnaBridge 171:3a7713b1edbc 608 #define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 609 #define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 610 #define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 611 #define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */
AnnaBridge 171:3a7713b1edbc 612 #define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */
AnnaBridge 171:3a7713b1edbc 613 #define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 614 #define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 615 #define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 616 #define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */
AnnaBridge 171:3a7713b1edbc 617 #define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */
AnnaBridge 171:3a7713b1edbc 618 #define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 619 #define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 620 #define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 621 #define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */
AnnaBridge 171:3a7713b1edbc 622 #define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */
AnnaBridge 171:3a7713b1edbc 623 #define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 624 #define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 625 #define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 626 #define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */
AnnaBridge 171:3a7713b1edbc 627 #define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */
AnnaBridge 171:3a7713b1edbc 628 #define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 629 #define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 630 #define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 631 #define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */
AnnaBridge 171:3a7713b1edbc 632 #define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */
AnnaBridge 171:3a7713b1edbc 633 #define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 634 #define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 635 #define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 636 #define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */
AnnaBridge 171:3a7713b1edbc 637 #define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */
AnnaBridge 171:3a7713b1edbc 638 #define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 639 #define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 640 #define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 641 #define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */
AnnaBridge 171:3a7713b1edbc 642 #define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */
AnnaBridge 171:3a7713b1edbc 643 #define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 644 #define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 645 #define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 646 #define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */
AnnaBridge 171:3a7713b1edbc 647 #define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */
AnnaBridge 171:3a7713b1edbc 648 #define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 649 #define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 650 #define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 651 #define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */
AnnaBridge 171:3a7713b1edbc 652 #define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */
AnnaBridge 171:3a7713b1edbc 653 #define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 654 #define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 655 #define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 656 #define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */
AnnaBridge 171:3a7713b1edbc 657 #define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */
AnnaBridge 171:3a7713b1edbc 658 #define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 659 #define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 660 #define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 661 #define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */
AnnaBridge 171:3a7713b1edbc 662 #define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */
AnnaBridge 171:3a7713b1edbc 663 #define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 664 #define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 665 #define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 666 #define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */
AnnaBridge 171:3a7713b1edbc 667 #define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */
AnnaBridge 171:3a7713b1edbc 668 #define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 669 #define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */
AnnaBridge 171:3a7713b1edbc 670
AnnaBridge 171:3a7713b1edbc 671 /* Bit fields for I2C ROUTE */
AnnaBridge 171:3a7713b1edbc 672 #define _I2C_ROUTE_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 673 #define _I2C_ROUTE_MASK 0x00000703UL /**< Mask for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 674 #define I2C_ROUTE_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */
AnnaBridge 171:3a7713b1edbc 675 #define _I2C_ROUTE_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */
AnnaBridge 171:3a7713b1edbc 676 #define _I2C_ROUTE_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */
AnnaBridge 171:3a7713b1edbc 677 #define _I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 678 #define I2C_ROUTE_SDAPEN_DEFAULT (_I2C_ROUTE_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 679 #define I2C_ROUTE_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */
AnnaBridge 171:3a7713b1edbc 680 #define _I2C_ROUTE_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */
AnnaBridge 171:3a7713b1edbc 681 #define _I2C_ROUTE_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */
AnnaBridge 171:3a7713b1edbc 682 #define _I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 683 #define I2C_ROUTE_SCLPEN_DEFAULT (_I2C_ROUTE_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 684 #define _I2C_ROUTE_LOCATION_SHIFT 8 /**< Shift value for I2C_LOCATION */
AnnaBridge 171:3a7713b1edbc 685 #define _I2C_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for I2C_LOCATION */
AnnaBridge 171:3a7713b1edbc 686 #define _I2C_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 687 #define _I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 688 #define _I2C_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 689 #define _I2C_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 690 #define _I2C_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 691 #define _I2C_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 692 #define _I2C_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 693 #define _I2C_ROUTE_LOCATION_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 694 #define I2C_ROUTE_LOCATION_LOC0 (_I2C_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 695 #define I2C_ROUTE_LOCATION_DEFAULT (_I2C_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 696 #define I2C_ROUTE_LOCATION_LOC1 (_I2C_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 697 #define I2C_ROUTE_LOCATION_LOC2 (_I2C_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 698 #define I2C_ROUTE_LOCATION_LOC3 (_I2C_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 699 #define I2C_ROUTE_LOCATION_LOC4 (_I2C_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 700 #define I2C_ROUTE_LOCATION_LOC5 (_I2C_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 701 #define I2C_ROUTE_LOCATION_LOC6 (_I2C_ROUTE_LOCATION_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTE */
AnnaBridge 171:3a7713b1edbc 702
AnnaBridge 171:3a7713b1edbc 703 /** @} End of group EFM32WG_I2C */
AnnaBridge 171:3a7713b1edbc 704 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 705