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TARGET_EFM32PG12_STK3402/TOOLCHAIN_IAR/efm32pg12b_emu.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 2 | * @file efm32pg12b_emu.h |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @brief EFM32PG12B_EMU register and bit field definitions |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @version 5.1.2 |
| AnnaBridge | 171:3a7713b1edbc | 5 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 6 | * @section License |
| AnnaBridge | 171:3a7713b1edbc | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| AnnaBridge | 171:3a7713b1edbc | 8 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 9 | * |
| AnnaBridge | 171:3a7713b1edbc | 10 | * Permission is granted to anyone to use this software for any purpose, |
| AnnaBridge | 171:3a7713b1edbc | 11 | * including commercial applications, and to alter it and redistribute it |
| AnnaBridge | 171:3a7713b1edbc | 12 | * freely, subject to the following restrictions: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * |
| AnnaBridge | 171:3a7713b1edbc | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| AnnaBridge | 171:3a7713b1edbc | 15 | * claim that you wrote the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| AnnaBridge | 171:3a7713b1edbc | 17 | * misrepresented as being the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| AnnaBridge | 171:3a7713b1edbc | 19 | * |
| AnnaBridge | 171:3a7713b1edbc | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| AnnaBridge | 171:3a7713b1edbc | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| AnnaBridge | 171:3a7713b1edbc | 23 | * kind, including, but not limited to, any implied warranties of |
| AnnaBridge | 171:3a7713b1edbc | 24 | * merchantability or fitness for any particular purpose or warranties against |
| AnnaBridge | 171:3a7713b1edbc | 25 | * infringement of any proprietary rights of a third party. |
| AnnaBridge | 171:3a7713b1edbc | 26 | * |
| AnnaBridge | 171:3a7713b1edbc | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| AnnaBridge | 171:3a7713b1edbc | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| AnnaBridge | 171:3a7713b1edbc | 29 | * any third party, arising from your use of this Software. |
| AnnaBridge | 171:3a7713b1edbc | 30 | * |
| AnnaBridge | 171:3a7713b1edbc | 31 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 32 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 33 | * @addtogroup Parts |
| AnnaBridge | 171:3a7713b1edbc | 34 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 35 | ******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 36 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 37 | * @defgroup EFM32PG12B_EMU |
| AnnaBridge | 171:3a7713b1edbc | 38 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 39 | * @brief EFM32PG12B_EMU Register Declaration |
| AnnaBridge | 171:3a7713b1edbc | 40 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 41 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 42 | { |
| AnnaBridge | 171:3a7713b1edbc | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 44 | __IM uint32_t STATUS; /**< Status Register */ |
| AnnaBridge | 171:3a7713b1edbc | 45 | __IOM uint32_t LOCK; /**< Configuration Lock Register */ |
| AnnaBridge | 171:3a7713b1edbc | 46 | __IOM uint32_t RAM0CTRL; /**< Memory Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 47 | __IOM uint32_t CMD; /**< Command Register */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | |
| AnnaBridge | 171:3a7713b1edbc | 49 | uint32_t RESERVED0[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 50 | __IOM uint32_t EM4CTRL; /**< EM4 Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 51 | __IOM uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | __IM uint32_t TEMP; /**< Value of last temperature measurement */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */ |
| AnnaBridge | 171:3a7713b1edbc | 58 | __IOM uint32_t PWRCFG; /**< Power Configuration Register */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | __IOM uint32_t PWRCTRL; /**< Power Control Register. */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | __IOM uint32_t DCDCCTRL; /**< DCDC Control */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | |
| AnnaBridge | 171:3a7713b1edbc | 62 | uint32_t RESERVED1[2]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 63 | __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 64 | __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 65 | __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 66 | __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | |
| AnnaBridge | 171:3a7713b1edbc | 69 | uint32_t RESERVED2[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 70 | __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | |
| AnnaBridge | 171:3a7713b1edbc | 72 | uint32_t RESERVED3[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 73 | __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | |
| AnnaBridge | 171:3a7713b1edbc | 76 | uint32_t RESERVED4[1]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 77 | __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | |
| AnnaBridge | 171:3a7713b1edbc | 79 | uint32_t RESERVED5[5]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 80 | __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | |
| AnnaBridge | 171:3a7713b1edbc | 85 | uint32_t RESERVED6[5]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 86 | __IOM uint32_t RAM1CTRL; /**< Memory Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | __IOM uint32_t RAM2CTRL; /**< Memory Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | |
| AnnaBridge | 171:3a7713b1edbc | 89 | uint32_t RESERVED7[12]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 90 | __IOM uint32_t DCDCLPEM01CFG; /**< Configuration bits for low power mode to be applied during EM01, this field is only relevant if LP mode is used in EM01. */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | |
| AnnaBridge | 171:3a7713b1edbc | 92 | uint32_t RESERVED8[4]; /**< Reserved for future use **/ |
| AnnaBridge | 171:3a7713b1edbc | 93 | __IOM uint32_t EM23PERNORETAINCMD; /**< Clears corresponding bits in EM23PERNORETAINSTATUS unlocking access to peripheral */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | __IM uint32_t EM23PERNORETAINSTATUS; /**< Status indicating if peripherals were powered down in EM23, subsequently locking access to it. */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | __IOM uint32_t EM23PERNORETAINCTRL; /**< When set corresponding peripherals may get powered down in EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | } EMU_TypeDef; /** @} */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | |
| AnnaBridge | 171:3a7713b1edbc | 98 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 99 | * @defgroup EFM32PG12B_EMU_BitFields |
| AnnaBridge | 171:3a7713b1edbc | 100 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 101 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 102 | |
| AnnaBridge | 171:3a7713b1edbc | 103 | /* Bit fields for EMU CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 109 | #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | #define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | #define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically configures Flash, Ram and Frequency to wakeup from EM2 or EM3 at low voltage */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | #define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | #define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 125 | #define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 126 | #define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | #define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | |
| AnnaBridge | 171:3a7713b1edbc | 147 | /* Bit fields for EMU STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | #define _EMU_STATUS_MASK 0x0417011FUL /**< Mask for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | #define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 160 | #define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */ |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define EMU_STATUS_VMONFVDD (0x1UL << 8) /**< VMON VDDFLASH Channel. */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define _EMU_STATUS_VMONFVDD_SHIFT 8 /**< Shift value for EMU_VMONFVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define _EMU_STATUS_VMONFVDD_MASK 0x100UL /**< Bit mask for EMU_VMONFVDD */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define _EMU_STATUS_VMONFVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | #define EMU_STATUS_VMONFVDD_DEFAULT (_EMU_STATUS_VMONFVDD_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | #define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is busy Scaling Voltage */ |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | #define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */ |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | #define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | |
| AnnaBridge | 171:3a7713b1edbc | 210 | /* Bit fields for EMU LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 225 | |
| AnnaBridge | 171:3a7713b1edbc | 226 | /* Bit fields for EMU RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define _EMU_RAM0CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 0x00000008UL /**< Mode BLK4 for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 0x0000000CUL /**< Mode BLK3TO4 for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 0x0000000EUL /**< Mode BLK2TO4 for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 0x0000000FUL /**< Mode BLK1TO4 for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4 << 0) /**< Shifted mode BLK4 for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO4 << 0) /**< Shifted mode BLK3TO4 for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO4 << 0) /**< Shifted mode BLK2TO4 for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO4 << 0) /**< Shifted mode BLK1TO4 for EMU_RAM0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | |
| AnnaBridge | 171:3a7713b1edbc | 244 | /* Bit fields for EMU CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */ |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | |
| AnnaBridge | 171:3a7713b1edbc | 263 | /* Bit fields for EMU EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 265 | #define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */ |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */ |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */ |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | |
| AnnaBridge | 171:3a7713b1edbc | 305 | /* Bit fields for EMU TEMPLIMITS */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */ |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */ |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */ |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temperature */ |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */ |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */ |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | |
| AnnaBridge | 171:3a7713b1edbc | 322 | /* Bit fields for EMU TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | #define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 324 | #define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 329 | |
| AnnaBridge | 171:3a7713b1edbc | 330 | /* Bit fields for EMU IF */ |
| AnnaBridge | 171:3a7713b1edbc | 331 | #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define _EMU_IF_MASK 0xE31FC0FFUL /**< Mask for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */ |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 338 | #define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | #define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 341 | #define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 342 | #define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | #define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */ |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | #define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 367 | #define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */ |
| AnnaBridge | 171:3a7713b1edbc | 369 | #define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | #define EMU_IF_VMONFVDDFALL (0x1UL << 14) /**< VMON VDDFLASH Channel Fall */ |
| AnnaBridge | 171:3a7713b1edbc | 374 | #define _EMU_IF_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define _EMU_IF_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 376 | #define _EMU_IF_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | #define EMU_IF_VMONFVDDFALL_DEFAULT (_EMU_IF_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 378 | #define EMU_IF_VMONFVDDRISE (0x1UL << 15) /**< VMON VDDFLASH Channel Rise */ |
| AnnaBridge | 171:3a7713b1edbc | 379 | #define _EMU_IF_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define _EMU_IF_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define _EMU_IF_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define EMU_IF_VMONFVDDRISE_DEFAULT (_EMU_IF_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */ |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | #define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 392 | #define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | #define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */ |
| AnnaBridge | 171:3a7713b1edbc | 394 | #define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | #define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */ |
| AnnaBridge | 171:3a7713b1edbc | 404 | #define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | #define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */ |
| AnnaBridge | 171:3a7713b1edbc | 409 | #define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ |
| AnnaBridge | 171:3a7713b1edbc | 410 | #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ |
| AnnaBridge | 171:3a7713b1edbc | 411 | #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | #define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */ |
| AnnaBridge | 171:3a7713b1edbc | 419 | #define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | #define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 421 | #define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 422 | #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 423 | #define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */ |
| AnnaBridge | 171:3a7713b1edbc | 424 | #define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ |
| AnnaBridge | 171:3a7713b1edbc | 425 | #define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ |
| AnnaBridge | 171:3a7713b1edbc | 426 | #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 427 | #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 428 | #define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */ |
| AnnaBridge | 171:3a7713b1edbc | 429 | #define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ |
| AnnaBridge | 171:3a7713b1edbc | 430 | #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ |
| AnnaBridge | 171:3a7713b1edbc | 431 | #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 432 | #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 433 | |
| AnnaBridge | 171:3a7713b1edbc | 434 | /* Bit fields for EMU IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 435 | #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | #define _EMU_IFS_MASK 0xE31FC0FFUL /**< Mask for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 437 | #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 439 | #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 440 | #define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | #define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 442 | #define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 444 | #define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 445 | #define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 446 | #define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | #define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 448 | #define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 449 | #define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 450 | #define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 454 | #define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 456 | #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 457 | #define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 458 | #define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 459 | #define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 460 | #define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 461 | #define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 462 | #define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 463 | #define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 464 | #define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 465 | #define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 466 | #define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 467 | #define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 468 | #define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ |
| AnnaBridge | 171:3a7713b1edbc | 469 | #define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ |
| AnnaBridge | 171:3a7713b1edbc | 470 | #define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 471 | #define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 472 | #define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 473 | #define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ |
| AnnaBridge | 171:3a7713b1edbc | 474 | #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ |
| AnnaBridge | 171:3a7713b1edbc | 475 | #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 476 | #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 477 | #define EMU_IFS_VMONFVDDFALL (0x1UL << 14) /**< Set VMONFVDDFALL Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 478 | #define _EMU_IFS_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 479 | #define _EMU_IFS_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 480 | #define _EMU_IFS_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 481 | #define EMU_IFS_VMONFVDDFALL_DEFAULT (_EMU_IFS_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 482 | #define EMU_IFS_VMONFVDDRISE (0x1UL << 15) /**< Set VMONFVDDRISE Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 483 | #define _EMU_IFS_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 484 | #define _EMU_IFS_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 485 | #define _EMU_IFS_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | #define EMU_IFS_VMONFVDDRISE_DEFAULT (_EMU_IFS_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 487 | #define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 488 | #define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 489 | #define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 490 | #define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 491 | #define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 492 | #define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 493 | #define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 494 | #define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 495 | #define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 496 | #define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 497 | #define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 498 | #define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 499 | #define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 500 | #define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 501 | #define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 502 | #define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 503 | #define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 504 | #define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 505 | #define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 506 | #define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 507 | #define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 508 | #define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ |
| AnnaBridge | 171:3a7713b1edbc | 509 | #define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ |
| AnnaBridge | 171:3a7713b1edbc | 510 | #define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 511 | #define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 512 | #define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 513 | #define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ |
| AnnaBridge | 171:3a7713b1edbc | 514 | #define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ |
| AnnaBridge | 171:3a7713b1edbc | 515 | #define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 516 | #define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 517 | #define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 518 | #define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ |
| AnnaBridge | 171:3a7713b1edbc | 519 | #define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ |
| AnnaBridge | 171:3a7713b1edbc | 520 | #define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 521 | #define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 522 | #define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 523 | #define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 524 | #define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 525 | #define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 526 | #define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 527 | #define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 528 | #define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ |
| AnnaBridge | 171:3a7713b1edbc | 529 | #define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ |
| AnnaBridge | 171:3a7713b1edbc | 530 | #define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 531 | #define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 532 | #define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 533 | #define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ |
| AnnaBridge | 171:3a7713b1edbc | 534 | #define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ |
| AnnaBridge | 171:3a7713b1edbc | 535 | #define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 536 | #define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 537 | |
| AnnaBridge | 171:3a7713b1edbc | 538 | /* Bit fields for EMU IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 539 | #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 540 | #define _EMU_IFC_MASK 0xE31FC0FFUL /**< Mask for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 541 | #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 542 | #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 543 | #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 544 | #define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 545 | #define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 546 | #define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 547 | #define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 548 | #define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 549 | #define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 550 | #define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 551 | #define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 552 | #define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 553 | #define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 554 | #define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 555 | #define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 556 | #define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 557 | #define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 558 | #define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 559 | #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 560 | #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 561 | #define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 562 | #define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 563 | #define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 564 | #define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 565 | #define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 566 | #define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 567 | #define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 568 | #define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 569 | #define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 570 | #define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 571 | #define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 572 | #define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ |
| AnnaBridge | 171:3a7713b1edbc | 573 | #define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ |
| AnnaBridge | 171:3a7713b1edbc | 574 | #define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 575 | #define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 576 | #define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 577 | #define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ |
| AnnaBridge | 171:3a7713b1edbc | 578 | #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ |
| AnnaBridge | 171:3a7713b1edbc | 579 | #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 580 | #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 581 | #define EMU_IFC_VMONFVDDFALL (0x1UL << 14) /**< Clear VMONFVDDFALL Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 582 | #define _EMU_IFC_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 583 | #define _EMU_IFC_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 584 | #define _EMU_IFC_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 585 | #define EMU_IFC_VMONFVDDFALL_DEFAULT (_EMU_IFC_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 586 | #define EMU_IFC_VMONFVDDRISE (0x1UL << 15) /**< Clear VMONFVDDRISE Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 587 | #define _EMU_IFC_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 588 | #define _EMU_IFC_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 589 | #define _EMU_IFC_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 590 | #define EMU_IFC_VMONFVDDRISE_DEFAULT (_EMU_IFC_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 591 | #define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 592 | #define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 593 | #define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 594 | #define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 595 | #define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 596 | #define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 597 | #define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 598 | #define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 599 | #define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 600 | #define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 601 | #define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 602 | #define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 603 | #define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 604 | #define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 605 | #define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 606 | #define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 607 | #define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 608 | #define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 609 | #define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 610 | #define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 611 | #define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 612 | #define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ |
| AnnaBridge | 171:3a7713b1edbc | 613 | #define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ |
| AnnaBridge | 171:3a7713b1edbc | 614 | #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 615 | #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 616 | #define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 617 | #define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ |
| AnnaBridge | 171:3a7713b1edbc | 618 | #define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ |
| AnnaBridge | 171:3a7713b1edbc | 619 | #define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 620 | #define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 621 | #define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 622 | #define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ |
| AnnaBridge | 171:3a7713b1edbc | 623 | #define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ |
| AnnaBridge | 171:3a7713b1edbc | 624 | #define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 625 | #define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 626 | #define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 627 | #define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 628 | #define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 629 | #define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 630 | #define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 631 | #define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 632 | #define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ |
| AnnaBridge | 171:3a7713b1edbc | 633 | #define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ |
| AnnaBridge | 171:3a7713b1edbc | 634 | #define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 635 | #define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 636 | #define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 637 | #define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ |
| AnnaBridge | 171:3a7713b1edbc | 638 | #define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ |
| AnnaBridge | 171:3a7713b1edbc | 639 | #define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 640 | #define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 641 | |
| AnnaBridge | 171:3a7713b1edbc | 642 | /* Bit fields for EMU IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 643 | #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 644 | #define _EMU_IEN_MASK 0xE31FC0FFUL /**< Mask for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 645 | #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 646 | #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 647 | #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 648 | #define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 649 | #define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 650 | #define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 651 | #define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 652 | #define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 653 | #define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 654 | #define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 655 | #define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 656 | #define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 657 | #define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 658 | #define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 659 | #define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 660 | #define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 661 | #define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 662 | #define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 663 | #define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 664 | #define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 665 | #define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 666 | #define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 667 | #define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 668 | #define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 669 | #define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 670 | #define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 671 | #define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 672 | #define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 673 | #define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 674 | #define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 675 | #define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 676 | #define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */ |
| AnnaBridge | 171:3a7713b1edbc | 677 | #define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */ |
| AnnaBridge | 171:3a7713b1edbc | 678 | #define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 679 | #define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 680 | #define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 681 | #define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */ |
| AnnaBridge | 171:3a7713b1edbc | 682 | #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */ |
| AnnaBridge | 171:3a7713b1edbc | 683 | #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 684 | #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 685 | #define EMU_IEN_VMONFVDDFALL (0x1UL << 14) /**< VMONFVDDFALL Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 686 | #define _EMU_IEN_VMONFVDDFALL_SHIFT 14 /**< Shift value for EMU_VMONFVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 687 | #define _EMU_IEN_VMONFVDDFALL_MASK 0x4000UL /**< Bit mask for EMU_VMONFVDDFALL */ |
| AnnaBridge | 171:3a7713b1edbc | 688 | #define _EMU_IEN_VMONFVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 689 | #define EMU_IEN_VMONFVDDFALL_DEFAULT (_EMU_IEN_VMONFVDDFALL_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 690 | #define EMU_IEN_VMONFVDDRISE (0x1UL << 15) /**< VMONFVDDRISE Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 691 | #define _EMU_IEN_VMONFVDDRISE_SHIFT 15 /**< Shift value for EMU_VMONFVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 692 | #define _EMU_IEN_VMONFVDDRISE_MASK 0x8000UL /**< Bit mask for EMU_VMONFVDDRISE */ |
| AnnaBridge | 171:3a7713b1edbc | 693 | #define _EMU_IEN_VMONFVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 694 | #define EMU_IEN_VMONFVDDRISE_DEFAULT (_EMU_IEN_VMONFVDDRISE_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 695 | #define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 696 | #define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 697 | #define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 698 | #define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 699 | #define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 700 | #define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 701 | #define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 702 | #define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */ |
| AnnaBridge | 171:3a7713b1edbc | 703 | #define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 704 | #define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 705 | #define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 706 | #define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 707 | #define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 708 | #define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 709 | #define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 710 | #define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 711 | #define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 712 | #define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */ |
| AnnaBridge | 171:3a7713b1edbc | 713 | #define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 714 | #define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 715 | #define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 716 | #define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */ |
| AnnaBridge | 171:3a7713b1edbc | 717 | #define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */ |
| AnnaBridge | 171:3a7713b1edbc | 718 | #define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 719 | #define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 720 | #define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 721 | #define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */ |
| AnnaBridge | 171:3a7713b1edbc | 722 | #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */ |
| AnnaBridge | 171:3a7713b1edbc | 723 | #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 724 | #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 725 | #define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 726 | #define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */ |
| AnnaBridge | 171:3a7713b1edbc | 727 | #define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */ |
| AnnaBridge | 171:3a7713b1edbc | 728 | #define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 729 | #define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 730 | #define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 731 | #define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 732 | #define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */ |
| AnnaBridge | 171:3a7713b1edbc | 733 | #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 734 | #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 735 | #define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 736 | #define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */ |
| AnnaBridge | 171:3a7713b1edbc | 737 | #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */ |
| AnnaBridge | 171:3a7713b1edbc | 738 | #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 739 | #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 740 | #define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 741 | #define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */ |
| AnnaBridge | 171:3a7713b1edbc | 742 | #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */ |
| AnnaBridge | 171:3a7713b1edbc | 743 | #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 744 | #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 745 | |
| AnnaBridge | 171:3a7713b1edbc | 746 | /* Bit fields for EMU PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 747 | #define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 748 | #define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 749 | #define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */ |
| AnnaBridge | 171:3a7713b1edbc | 750 | #define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */ |
| AnnaBridge | 171:3a7713b1edbc | 751 | #define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 752 | #define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 753 | #define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 754 | #define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 755 | #define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 756 | #define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 757 | #define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 758 | #define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 759 | #define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 760 | #define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 761 | |
| AnnaBridge | 171:3a7713b1edbc | 762 | /* Bit fields for EMU PWRCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 763 | #define _EMU_PWRCFG_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 764 | #define _EMU_PWRCFG_MASK 0x0000000FUL /**< Mask for EMU_PWRCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 765 | #define _EMU_PWRCFG_PWRCFG_SHIFT 0 /**< Shift value for EMU_PWRCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 766 | #define _EMU_PWRCFG_PWRCFG_MASK 0xFUL /**< Bit mask for EMU_PWRCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 767 | #define _EMU_PWRCFG_PWRCFG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 768 | #define _EMU_PWRCFG_PWRCFG_UNCONFIGURED 0x00000000UL /**< Mode UNCONFIGURED for EMU_PWRCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 769 | #define _EMU_PWRCFG_PWRCFG_DCDCTODVDD 0x00000002UL /**< Mode DCDCTODVDD for EMU_PWRCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 770 | #define EMU_PWRCFG_PWRCFG_DEFAULT (_EMU_PWRCFG_PWRCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 771 | #define EMU_PWRCFG_PWRCFG_UNCONFIGURED (_EMU_PWRCFG_PWRCFG_UNCONFIGURED << 0) /**< Shifted mode UNCONFIGURED for EMU_PWRCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 772 | #define EMU_PWRCFG_PWRCFG_DCDCTODVDD (_EMU_PWRCFG_PWRCFG_DCDCTODVDD << 0) /**< Shifted mode DCDCTODVDD for EMU_PWRCFG */ |
| AnnaBridge | 171:3a7713b1edbc | 773 | |
| AnnaBridge | 171:3a7713b1edbc | 774 | /* Bit fields for EMU PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 775 | #define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 776 | #define _EMU_PWRCTRL_MASK 0x00001420UL /**< Mask for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 777 | #define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */ |
| AnnaBridge | 171:3a7713b1edbc | 778 | #define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */ |
| AnnaBridge | 171:3a7713b1edbc | 779 | #define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */ |
| AnnaBridge | 171:3a7713b1edbc | 780 | #define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 781 | #define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 782 | #define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 783 | #define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 784 | #define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 785 | #define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 786 | #define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This field selects the input for the regulator. */ |
| AnnaBridge | 171:3a7713b1edbc | 787 | #define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 788 | #define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 789 | #define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 790 | #define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 791 | #define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 792 | #define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 793 | #define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 794 | #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 795 | #define EMU_PWRCTRL_DVDDBODDIS (0x1UL << 12) /**< DVDD BOD Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 796 | #define _EMU_PWRCTRL_DVDDBODDIS_SHIFT 12 /**< Shift value for EMU_DVDDBODDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 797 | #define _EMU_PWRCTRL_DVDDBODDIS_MASK 0x1000UL /**< Bit mask for EMU_DVDDBODDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 798 | #define _EMU_PWRCTRL_DVDDBODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 799 | #define EMU_PWRCTRL_DVDDBODDIS_DEFAULT (_EMU_PWRCTRL_DVDDBODDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_PWRCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 800 | |
| AnnaBridge | 171:3a7713b1edbc | 801 | /* Bit fields for EMU DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 802 | #define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 803 | #define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 804 | #define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 805 | #define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 806 | #define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 807 | #define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 808 | #define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 809 | #define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 810 | #define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 811 | #define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 812 | #define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 813 | #define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 814 | #define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 815 | #define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 816 | #define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 817 | #define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 818 | #define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 819 | #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 820 | #define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 821 | #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 822 | #define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 823 | #define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 824 | #define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 825 | #define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */ |
| AnnaBridge | 171:3a7713b1edbc | 826 | #define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */ |
| AnnaBridge | 171:3a7713b1edbc | 827 | #define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */ |
| AnnaBridge | 171:3a7713b1edbc | 828 | #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 829 | #define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 830 | #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 831 | #define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 832 | #define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 833 | #define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 834 | |
| AnnaBridge | 171:3a7713b1edbc | 835 | /* Bit fields for EMU DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 836 | #define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 837 | #define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 838 | #define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */ |
| AnnaBridge | 171:3a7713b1edbc | 839 | #define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */ |
| AnnaBridge | 171:3a7713b1edbc | 840 | #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */ |
| AnnaBridge | 171:3a7713b1edbc | 841 | #define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 842 | #define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 843 | #define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP mode hysteresis in the state machine control */ |
| AnnaBridge | 171:3a7713b1edbc | 844 | #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 845 | #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 846 | #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 847 | #define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 848 | #define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator threshold on the high side */ |
| AnnaBridge | 171:3a7713b1edbc | 849 | #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */ |
| AnnaBridge | 171:3a7713b1edbc | 850 | #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */ |
| AnnaBridge | 171:3a7713b1edbc | 851 | #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 852 | #define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 853 | #define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC into CCM mode immediately, based on LNFORCECCM */ |
| AnnaBridge | 171:3a7713b1edbc | 854 | #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */ |
| AnnaBridge | 171:3a7713b1edbc | 855 | #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */ |
| AnnaBridge | 171:3a7713b1edbc | 856 | #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 857 | #define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 858 | #define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 859 | #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 860 | #define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 861 | #define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 862 | #define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 863 | #define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */ |
| AnnaBridge | 171:3a7713b1edbc | 864 | #define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 865 | #define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 866 | #define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 867 | #define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 868 | #define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 869 | #define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 870 | #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 871 | #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 872 | #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 873 | #define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 874 | #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 875 | #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 876 | #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 877 | #define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 878 | #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */ |
| AnnaBridge | 171:3a7713b1edbc | 879 | #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */ |
| AnnaBridge | 171:3a7713b1edbc | 880 | #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 881 | #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 882 | #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 883 | #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 884 | #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 885 | #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 886 | #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 887 | #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 888 | #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 889 | #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 890 | |
| AnnaBridge | 171:3a7713b1edbc | 891 | /* Bit fields for EMU DCDCZDETCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 892 | #define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 893 | #define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 894 | #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 895 | #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 896 | #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 897 | #define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 898 | #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */ |
| AnnaBridge | 171:3a7713b1edbc | 899 | #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */ |
| AnnaBridge | 171:3a7713b1edbc | 900 | #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 901 | #define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 902 | |
| AnnaBridge | 171:3a7713b1edbc | 903 | /* Bit fields for EMU DCDCCLIMCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 904 | #define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 905 | #define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 906 | #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */ |
| AnnaBridge | 171:3a7713b1edbc | 907 | #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */ |
| AnnaBridge | 171:3a7713b1edbc | 908 | #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 909 | #define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 910 | #define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 911 | #define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */ |
| AnnaBridge | 171:3a7713b1edbc | 912 | #define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */ |
| AnnaBridge | 171:3a7713b1edbc | 913 | #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 914 | #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 915 | |
| AnnaBridge | 171:3a7713b1edbc | 916 | /* Bit fields for EMU DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 917 | #define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 918 | #define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 919 | #define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */ |
| AnnaBridge | 171:3a7713b1edbc | 920 | #define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */ |
| AnnaBridge | 171:3a7713b1edbc | 921 | #define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 922 | #define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 923 | #define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */ |
| AnnaBridge | 171:3a7713b1edbc | 924 | #define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */ |
| AnnaBridge | 171:3a7713b1edbc | 925 | #define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 926 | #define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 927 | #define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */ |
| AnnaBridge | 171:3a7713b1edbc | 928 | #define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */ |
| AnnaBridge | 171:3a7713b1edbc | 929 | #define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 930 | #define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 931 | #define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */ |
| AnnaBridge | 171:3a7713b1edbc | 932 | #define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */ |
| AnnaBridge | 171:3a7713b1edbc | 933 | #define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 934 | #define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 935 | #define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 936 | #define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 937 | #define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 938 | #define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 939 | #define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */ |
| AnnaBridge | 171:3a7713b1edbc | 940 | #define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */ |
| AnnaBridge | 171:3a7713b1edbc | 941 | #define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 942 | #define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 943 | |
| AnnaBridge | 171:3a7713b1edbc | 944 | /* Bit fields for EMU DCDCLNVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 945 | #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 946 | #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 947 | #define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */ |
| AnnaBridge | 171:3a7713b1edbc | 948 | #define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */ |
| AnnaBridge | 171:3a7713b1edbc | 949 | #define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */ |
| AnnaBridge | 171:3a7713b1edbc | 950 | #define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 951 | #define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 952 | #define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 953 | #define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 954 | #define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 955 | #define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 956 | #define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */ |
| AnnaBridge | 171:3a7713b1edbc | 957 | #define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */ |
| AnnaBridge | 171:3a7713b1edbc | 958 | #define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 959 | #define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 960 | |
| AnnaBridge | 171:3a7713b1edbc | 961 | /* Bit fields for EMU DCDCLPVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 962 | #define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 963 | #define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 964 | #define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */ |
| AnnaBridge | 171:3a7713b1edbc | 965 | #define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */ |
| AnnaBridge | 171:3a7713b1edbc | 966 | #define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */ |
| AnnaBridge | 171:3a7713b1edbc | 967 | #define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 968 | #define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 969 | #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 970 | #define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 971 | #define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 972 | #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 973 | #define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */ |
| AnnaBridge | 171:3a7713b1edbc | 974 | #define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */ |
| AnnaBridge | 171:3a7713b1edbc | 975 | #define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 976 | #define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 977 | |
| AnnaBridge | 171:3a7713b1edbc | 978 | /* Bit fields for EMU DCDCLPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 979 | #define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 980 | #define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 981 | #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */ |
| AnnaBridge | 171:3a7713b1edbc | 982 | #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */ |
| AnnaBridge | 171:3a7713b1edbc | 983 | #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 984 | #define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 985 | #define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP mode duty cycling enable */ |
| AnnaBridge | 171:3a7713b1edbc | 986 | #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */ |
| AnnaBridge | 171:3a7713b1edbc | 987 | #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */ |
| AnnaBridge | 171:3a7713b1edbc | 988 | #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 989 | #define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 990 | #define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */ |
| AnnaBridge | 171:3a7713b1edbc | 991 | #define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */ |
| AnnaBridge | 171:3a7713b1edbc | 992 | #define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 993 | #define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 994 | |
| AnnaBridge | 171:3a7713b1edbc | 995 | /* Bit fields for EMU DCDCLNFREQCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 996 | #define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 997 | #define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 998 | #define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */ |
| AnnaBridge | 171:3a7713b1edbc | 999 | #define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */ |
| AnnaBridge | 171:3a7713b1edbc | 1000 | #define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1001 | #define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1002 | #define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */ |
| AnnaBridge | 171:3a7713b1edbc | 1003 | #define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */ |
| AnnaBridge | 171:3a7713b1edbc | 1004 | #define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1005 | #define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1006 | |
| AnnaBridge | 171:3a7713b1edbc | 1007 | /* Bit fields for EMU DCDCSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1008 | #define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1009 | #define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1010 | #define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */ |
| AnnaBridge | 171:3a7713b1edbc | 1011 | #define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 1012 | #define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 1013 | #define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1014 | #define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */ |
| AnnaBridge | 171:3a7713b1edbc | 1015 | |
| AnnaBridge | 171:3a7713b1edbc | 1016 | /* Bit fields for EMU VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1017 | #define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1018 | #define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1019 | #define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1020 | #define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1021 | #define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1022 | #define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1023 | #define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1024 | #define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ |
| AnnaBridge | 171:3a7713b1edbc | 1025 | #define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1026 | #define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1027 | #define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1028 | #define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1029 | #define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ |
| AnnaBridge | 171:3a7713b1edbc | 1030 | #define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1031 | #define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1032 | #define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1033 | #define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1034 | #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 1035 | #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 1036 | #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1037 | #define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1038 | #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 1039 | #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 1040 | #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1041 | #define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1042 | #define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 1043 | #define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 1044 | #define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1045 | #define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1046 | #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 1047 | #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 1048 | #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1049 | #define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1050 | |
| AnnaBridge | 171:3a7713b1edbc | 1051 | /* Bit fields for EMU VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1052 | #define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1053 | #define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1054 | #define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1055 | #define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1056 | #define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1057 | #define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1058 | #define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1059 | #define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ |
| AnnaBridge | 171:3a7713b1edbc | 1060 | #define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1061 | #define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1062 | #define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1063 | #define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1064 | #define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ |
| AnnaBridge | 171:3a7713b1edbc | 1065 | #define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1066 | #define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1067 | #define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1068 | #define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1069 | #define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 1070 | #define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 1071 | #define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1072 | #define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1073 | #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 1074 | #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 1075 | #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1076 | #define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1077 | |
| AnnaBridge | 171:3a7713b1edbc | 1078 | /* Bit fields for EMU VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1079 | #define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1080 | #define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1081 | #define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1082 | #define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1083 | #define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1084 | #define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1085 | #define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1086 | #define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ |
| AnnaBridge | 171:3a7713b1edbc | 1087 | #define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1088 | #define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1089 | #define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1090 | #define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1091 | #define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ |
| AnnaBridge | 171:3a7713b1edbc | 1092 | #define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1093 | #define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1094 | #define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1095 | #define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1096 | #define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 1097 | #define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 1098 | #define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1099 | #define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1100 | #define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 1101 | #define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 1102 | #define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1103 | #define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1104 | |
| AnnaBridge | 171:3a7713b1edbc | 1105 | /* Bit fields for EMU VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1106 | #define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1107 | #define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1108 | #define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 1109 | #define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1110 | #define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */ |
| AnnaBridge | 171:3a7713b1edbc | 1111 | #define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1112 | #define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1113 | #define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */ |
| AnnaBridge | 171:3a7713b1edbc | 1114 | #define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1115 | #define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1116 | #define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1117 | #define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1118 | #define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */ |
| AnnaBridge | 171:3a7713b1edbc | 1119 | #define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1120 | #define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */ |
| AnnaBridge | 171:3a7713b1edbc | 1121 | #define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1122 | #define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1123 | #define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */ |
| AnnaBridge | 171:3a7713b1edbc | 1124 | #define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1125 | #define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1126 | #define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1127 | #define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1128 | #define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 1129 | #define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */ |
| AnnaBridge | 171:3a7713b1edbc | 1130 | #define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1131 | #define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1132 | #define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 1133 | #define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */ |
| AnnaBridge | 171:3a7713b1edbc | 1134 | #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1135 | #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1136 | |
| AnnaBridge | 171:3a7713b1edbc | 1137 | /* Bit fields for EMU RAM1CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1138 | #define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1139 | #define _EMU_RAM1CTRL_MASK 0x00000003UL /**< Mask for EMU_RAM1CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1140 | #define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ |
| AnnaBridge | 171:3a7713b1edbc | 1141 | #define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0x3UL /**< Bit mask for EMU_RAMPOWERDOWN */ |
| AnnaBridge | 171:3a7713b1edbc | 1142 | #define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1143 | #define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1144 | #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 0x00000002UL /**< Mode BLK1 for EMU_RAM1CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1145 | #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 0x00000003UL /**< Mode BLK0TO1 for EMU_RAM1CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1146 | #define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1147 | #define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1148 | #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1 << 0) /**< Shifted mode BLK1 for EMU_RAM1CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1149 | #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO1 << 0) /**< Shifted mode BLK0TO1 for EMU_RAM1CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1150 | |
| AnnaBridge | 171:3a7713b1edbc | 1151 | /* Bit fields for EMU RAM2CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1152 | #define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1153 | #define _EMU_RAM2CTRL_MASK 0x00000001UL /**< Mask for EMU_RAM2CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1154 | #define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */ |
| AnnaBridge | 171:3a7713b1edbc | 1155 | #define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0x1UL /**< Bit mask for EMU_RAMPOWERDOWN */ |
| AnnaBridge | 171:3a7713b1edbc | 1156 | #define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1157 | #define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1158 | #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK 0x00000001UL /**< Mode BLK for EMU_RAM2CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1159 | #define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1160 | #define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1161 | #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK << 0) /**< Shifted mode BLK for EMU_RAM2CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1162 | |
| AnnaBridge | 171:3a7713b1edbc | 1163 | /* Bit fields for EMU DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1164 | #define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1165 | #define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1166 | #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */ |
| AnnaBridge | 171:3a7713b1edbc | 1167 | #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */ |
| AnnaBridge | 171:3a7713b1edbc | 1168 | #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1169 | #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1170 | #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1171 | #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1172 | #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1173 | #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1174 | #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1175 | #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1176 | #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1177 | #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1178 | #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */ |
| AnnaBridge | 171:3a7713b1edbc | 1179 | #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */ |
| AnnaBridge | 171:3a7713b1edbc | 1180 | #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1181 | #define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */ |
| AnnaBridge | 171:3a7713b1edbc | 1182 | |
| AnnaBridge | 171:3a7713b1edbc | 1183 | /* Bit fields for EMU EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1184 | #define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1185 | #define _EMU_EM23PERNORETAINCMD_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1186 | #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears status bit of ACMP0 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1187 | #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1188 | #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1189 | #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1190 | #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1191 | #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears status bit of ACMP1 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1192 | #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1193 | #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1194 | #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1195 | #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1196 | #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears status bit of PCNT0 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1197 | #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1198 | #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1199 | #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1200 | #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1201 | #define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears status bit of PCNT1 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1202 | #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1203 | #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1204 | #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1205 | #define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1206 | #define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears status bit of PCNT2 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1207 | #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1208 | #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1209 | #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1210 | #define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1211 | #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears status bit of I2C0 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1212 | #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1213 | #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1214 | #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1215 | #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1216 | #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears status bit of I2C1 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1217 | #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1218 | #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1219 | #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1220 | #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1221 | #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears status bit of DAC0 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1222 | #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1223 | #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1224 | #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1225 | #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1226 | #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears status bit of IDAC0 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1227 | #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1228 | #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1229 | #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1230 | #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1231 | #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears status bit of ADC0 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1232 | #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1233 | #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1234 | #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1235 | #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1236 | #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears status bit of LETIMER0 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1237 | #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1238 | #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1239 | #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1240 | #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1241 | #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears status bit of WDOG0 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1242 | #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1243 | #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1244 | #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1245 | #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1246 | #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears status bit of WDOG1 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1247 | #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1248 | #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1249 | #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1250 | #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1251 | #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears status bit of LESENSE0 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1252 | #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1253 | #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1254 | #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1255 | #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1256 | #define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears status bit of CSEN and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1257 | #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1258 | #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1259 | #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1260 | #define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1261 | #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears status bit of LEUART0 and unlocks access to it */ |
| AnnaBridge | 171:3a7713b1edbc | 1262 | #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1263 | #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 1264 | #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1265 | #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1266 | |
| AnnaBridge | 171:3a7713b1edbc | 1267 | /* Bit fields for EMU EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1268 | #define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1269 | #define _EMU_EM23PERNORETAINSTATUS_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1270 | #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates if ACMP0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1271 | #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1272 | #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1273 | #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1274 | #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1275 | #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates if ACMP1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1276 | #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1277 | #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1278 | #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1279 | #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1280 | #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates if PCNT0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1281 | #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1282 | #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1283 | #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1284 | #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1285 | #define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates if PCNT1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1286 | #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1287 | #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1288 | #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1289 | #define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1290 | #define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates if PCNT2 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1291 | #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1292 | #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1293 | #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1294 | #define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1295 | #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates if I2C0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1296 | #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1297 | #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1298 | #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1299 | #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1300 | #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates if I2C1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1301 | #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1302 | #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1303 | #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1304 | #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1305 | #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates if DAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1306 | #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1307 | #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1308 | #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1309 | #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1310 | #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates if IDAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1311 | #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1312 | #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1313 | #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1314 | #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1315 | #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates if ADC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1316 | #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1317 | #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1318 | #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1319 | #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1320 | #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates if LETIMER0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1321 | #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1322 | #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1323 | #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1324 | #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1325 | #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates if WDOG0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1326 | #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1327 | #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1328 | #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1329 | #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1330 | #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates if WDOG1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1331 | #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1332 | #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1333 | #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1334 | #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1335 | #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates if LESENSE0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1336 | #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1337 | #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1338 | #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1339 | #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1340 | #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates if CSEN powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1341 | #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1342 | #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1343 | #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1344 | #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1345 | #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates if LEUART0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */ |
| AnnaBridge | 171:3a7713b1edbc | 1346 | #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1347 | #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */ |
| AnnaBridge | 171:3a7713b1edbc | 1348 | #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1349 | #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 1350 | |
| AnnaBridge | 171:3a7713b1edbc | 1351 | /* Bit fields for EMU EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1352 | #define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1353 | #define _EMU_EM23PERNORETAINCTRL_MASK 0x0000FFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1354 | #define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow power down of ACMP0 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1355 | #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1356 | #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1357 | #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1358 | #define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1359 | #define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow power down of ACMP1 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1360 | #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1361 | #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1362 | #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1363 | #define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1364 | #define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow power down of PCNT0 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1365 | #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1366 | #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1367 | #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1368 | #define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1369 | #define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow power down of PCNT1 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1370 | #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1371 | #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1372 | #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1373 | #define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1374 | #define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow power down of PCNT2 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1375 | #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1376 | #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1377 | #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1378 | #define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1379 | #define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow power down of I2C0 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1380 | #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1381 | #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1382 | #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1383 | #define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1384 | #define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow power down of I2C1 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1385 | #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1386 | #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1387 | #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1388 | #define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1389 | #define EMU_EM23PERNORETAINCTRL_DAC0DIS (0x1UL << 7) /**< Allow power down of DAC0 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1390 | #define _EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT 7 /**< Shift value for EMU_DAC0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1391 | #define _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK 0x80UL /**< Bit mask for EMU_DAC0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1392 | #define _EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1393 | #define EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1394 | #define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow power down of IDAC0 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1395 | #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1396 | #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1397 | #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1398 | #define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1399 | #define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow power down of ADC0 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1400 | #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1401 | #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1402 | #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1403 | #define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1404 | #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow power down of LETIMER0 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1405 | #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1406 | #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1407 | #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1408 | #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1409 | #define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow power down of WDOG0 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1410 | #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1411 | #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1412 | #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1413 | #define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1414 | #define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow power down of WDOG1 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1415 | #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1416 | #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1417 | #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1418 | #define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1419 | #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow power down of LESENSE0 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1420 | #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1421 | #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1422 | #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1423 | #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1424 | #define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow power down of CSEN during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1425 | #define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1426 | #define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1427 | #define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1428 | #define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1429 | #define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow power down of LEUART0 during EM23 */ |
| AnnaBridge | 171:3a7713b1edbc | 1430 | #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1431 | #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */ |
| AnnaBridge | 171:3a7713b1edbc | 1432 | #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1433 | #define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 1434 | |
| AnnaBridge | 171:3a7713b1edbc | 1435 | /** @} End of group EFM32PG12B_EMU */ |
| AnnaBridge | 171:3a7713b1edbc | 1436 | /** @} End of group Parts */ |
| AnnaBridge | 171:3a7713b1edbc | 1437 |
