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TARGET_EFM32PG12_STK3402/TOOLCHAIN_ARM_STD/efm32pg12b_rmu.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32pg12b_rmu.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32PG12B_RMU register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32PG12B_RMU
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32PG12B_RMU Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IOM uint32_t CTRL; /**< Control Register */
AnnaBridge 171:3a7713b1edbc 44 __IM uint32_t RSTCAUSE; /**< Reset Cause Register */
AnnaBridge 171:3a7713b1edbc 45 __IOM uint32_t CMD; /**< Command Register */
AnnaBridge 171:3a7713b1edbc 46 __IOM uint32_t RST; /**< Reset Control Register */
AnnaBridge 171:3a7713b1edbc 47 __IOM uint32_t LOCK; /**< Configuration Lock Register */
AnnaBridge 171:3a7713b1edbc 48 } RMU_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 51 * @defgroup EFM32PG12B_RMU_BitFields
AnnaBridge 171:3a7713b1edbc 52 * @{
AnnaBridge 171:3a7713b1edbc 53 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /* Bit fields for RMU CTRL */
AnnaBridge 171:3a7713b1edbc 56 #define _RMU_CTRL_RESETVALUE 0x00004204UL /**< Default value for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 57 #define _RMU_CTRL_MASK 0x03007777UL /**< Mask for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 58 #define _RMU_CTRL_WDOGRMODE_SHIFT 0 /**< Shift value for RMU_WDOGRMODE */
AnnaBridge 171:3a7713b1edbc 59 #define _RMU_CTRL_WDOGRMODE_MASK 0x7UL /**< Bit mask for RMU_WDOGRMODE */
AnnaBridge 171:3a7713b1edbc 60 #define _RMU_CTRL_WDOGRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 61 #define _RMU_CTRL_WDOGRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 62 #define _RMU_CTRL_WDOGRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 63 #define _RMU_CTRL_WDOGRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 64 #define _RMU_CTRL_WDOGRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 65 #define RMU_CTRL_WDOGRMODE_DISABLED (_RMU_CTRL_WDOGRMODE_DISABLED << 0) /**< Shifted mode DISABLED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 66 #define RMU_CTRL_WDOGRMODE_LIMITED (_RMU_CTRL_WDOGRMODE_LIMITED << 0) /**< Shifted mode LIMITED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 67 #define RMU_CTRL_WDOGRMODE_EXTENDED (_RMU_CTRL_WDOGRMODE_EXTENDED << 0) /**< Shifted mode EXTENDED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 68 #define RMU_CTRL_WDOGRMODE_DEFAULT (_RMU_CTRL_WDOGRMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 69 #define RMU_CTRL_WDOGRMODE_FULL (_RMU_CTRL_WDOGRMODE_FULL << 0) /**< Shifted mode FULL for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 70 #define _RMU_CTRL_LOCKUPRMODE_SHIFT 4 /**< Shift value for RMU_LOCKUPRMODE */
AnnaBridge 171:3a7713b1edbc 71 #define _RMU_CTRL_LOCKUPRMODE_MASK 0x70UL /**< Bit mask for RMU_LOCKUPRMODE */
AnnaBridge 171:3a7713b1edbc 72 #define _RMU_CTRL_LOCKUPRMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 73 #define _RMU_CTRL_LOCKUPRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 74 #define _RMU_CTRL_LOCKUPRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 75 #define _RMU_CTRL_LOCKUPRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 76 #define _RMU_CTRL_LOCKUPRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 77 #define RMU_CTRL_LOCKUPRMODE_DEFAULT (_RMU_CTRL_LOCKUPRMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 78 #define RMU_CTRL_LOCKUPRMODE_DISABLED (_RMU_CTRL_LOCKUPRMODE_DISABLED << 4) /**< Shifted mode DISABLED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 79 #define RMU_CTRL_LOCKUPRMODE_LIMITED (_RMU_CTRL_LOCKUPRMODE_LIMITED << 4) /**< Shifted mode LIMITED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 80 #define RMU_CTRL_LOCKUPRMODE_EXTENDED (_RMU_CTRL_LOCKUPRMODE_EXTENDED << 4) /**< Shifted mode EXTENDED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 81 #define RMU_CTRL_LOCKUPRMODE_FULL (_RMU_CTRL_LOCKUPRMODE_FULL << 4) /**< Shifted mode FULL for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 82 #define _RMU_CTRL_SYSRMODE_SHIFT 8 /**< Shift value for RMU_SYSRMODE */
AnnaBridge 171:3a7713b1edbc 83 #define _RMU_CTRL_SYSRMODE_MASK 0x700UL /**< Bit mask for RMU_SYSRMODE */
AnnaBridge 171:3a7713b1edbc 84 #define _RMU_CTRL_SYSRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 85 #define _RMU_CTRL_SYSRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 86 #define _RMU_CTRL_SYSRMODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 87 #define _RMU_CTRL_SYSRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 88 #define _RMU_CTRL_SYSRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 89 #define RMU_CTRL_SYSRMODE_DISABLED (_RMU_CTRL_SYSRMODE_DISABLED << 8) /**< Shifted mode DISABLED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 90 #define RMU_CTRL_SYSRMODE_LIMITED (_RMU_CTRL_SYSRMODE_LIMITED << 8) /**< Shifted mode LIMITED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 91 #define RMU_CTRL_SYSRMODE_DEFAULT (_RMU_CTRL_SYSRMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 92 #define RMU_CTRL_SYSRMODE_EXTENDED (_RMU_CTRL_SYSRMODE_EXTENDED << 8) /**< Shifted mode EXTENDED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 93 #define RMU_CTRL_SYSRMODE_FULL (_RMU_CTRL_SYSRMODE_FULL << 8) /**< Shifted mode FULL for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 94 #define _RMU_CTRL_PINRMODE_SHIFT 12 /**< Shift value for RMU_PINRMODE */
AnnaBridge 171:3a7713b1edbc 95 #define _RMU_CTRL_PINRMODE_MASK 0x7000UL /**< Bit mask for RMU_PINRMODE */
AnnaBridge 171:3a7713b1edbc 96 #define _RMU_CTRL_PINRMODE_DISABLED 0x00000000UL /**< Mode DISABLED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 97 #define _RMU_CTRL_PINRMODE_LIMITED 0x00000001UL /**< Mode LIMITED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 98 #define _RMU_CTRL_PINRMODE_EXTENDED 0x00000002UL /**< Mode EXTENDED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 99 #define _RMU_CTRL_PINRMODE_DEFAULT 0x00000004UL /**< Mode DEFAULT for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 100 #define _RMU_CTRL_PINRMODE_FULL 0x00000004UL /**< Mode FULL for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 101 #define RMU_CTRL_PINRMODE_DISABLED (_RMU_CTRL_PINRMODE_DISABLED << 12) /**< Shifted mode DISABLED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 102 #define RMU_CTRL_PINRMODE_LIMITED (_RMU_CTRL_PINRMODE_LIMITED << 12) /**< Shifted mode LIMITED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 103 #define RMU_CTRL_PINRMODE_EXTENDED (_RMU_CTRL_PINRMODE_EXTENDED << 12) /**< Shifted mode EXTENDED for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 104 #define RMU_CTRL_PINRMODE_DEFAULT (_RMU_CTRL_PINRMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 105 #define RMU_CTRL_PINRMODE_FULL (_RMU_CTRL_PINRMODE_FULL << 12) /**< Shifted mode FULL for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 106 #define _RMU_CTRL_RESETSTATE_SHIFT 24 /**< Shift value for RMU_RESETSTATE */
AnnaBridge 171:3a7713b1edbc 107 #define _RMU_CTRL_RESETSTATE_MASK 0x3000000UL /**< Bit mask for RMU_RESETSTATE */
AnnaBridge 171:3a7713b1edbc 108 #define _RMU_CTRL_RESETSTATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 109 #define RMU_CTRL_RESETSTATE_DEFAULT (_RMU_CTRL_RESETSTATE_DEFAULT << 24) /**< Shifted mode DEFAULT for RMU_CTRL */
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 /* Bit fields for RMU RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 112 #define _RMU_RSTCAUSE_RESETVALUE 0x00000000UL /**< Default value for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 113 #define _RMU_RSTCAUSE_MASK 0x00010F1DUL /**< Mask for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 114 #define RMU_RSTCAUSE_PORST (0x1UL << 0) /**< Power On Reset */
AnnaBridge 171:3a7713b1edbc 115 #define _RMU_RSTCAUSE_PORST_SHIFT 0 /**< Shift value for RMU_PORST */
AnnaBridge 171:3a7713b1edbc 116 #define _RMU_RSTCAUSE_PORST_MASK 0x1UL /**< Bit mask for RMU_PORST */
AnnaBridge 171:3a7713b1edbc 117 #define _RMU_RSTCAUSE_PORST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 118 #define RMU_RSTCAUSE_PORST_DEFAULT (_RMU_RSTCAUSE_PORST_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 119 #define RMU_RSTCAUSE_AVDDBOD (0x1UL << 2) /**< Brown Out Detector AVDD Reset */
AnnaBridge 171:3a7713b1edbc 120 #define _RMU_RSTCAUSE_AVDDBOD_SHIFT 2 /**< Shift value for RMU_AVDDBOD */
AnnaBridge 171:3a7713b1edbc 121 #define _RMU_RSTCAUSE_AVDDBOD_MASK 0x4UL /**< Bit mask for RMU_AVDDBOD */
AnnaBridge 171:3a7713b1edbc 122 #define _RMU_RSTCAUSE_AVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 123 #define RMU_RSTCAUSE_AVDDBOD_DEFAULT (_RMU_RSTCAUSE_AVDDBOD_DEFAULT << 2) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 124 #define RMU_RSTCAUSE_DVDDBOD (0x1UL << 3) /**< Brown Out Detector DVDD Reset */
AnnaBridge 171:3a7713b1edbc 125 #define _RMU_RSTCAUSE_DVDDBOD_SHIFT 3 /**< Shift value for RMU_DVDDBOD */
AnnaBridge 171:3a7713b1edbc 126 #define _RMU_RSTCAUSE_DVDDBOD_MASK 0x8UL /**< Bit mask for RMU_DVDDBOD */
AnnaBridge 171:3a7713b1edbc 127 #define _RMU_RSTCAUSE_DVDDBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 128 #define RMU_RSTCAUSE_DVDDBOD_DEFAULT (_RMU_RSTCAUSE_DVDDBOD_DEFAULT << 3) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 129 #define RMU_RSTCAUSE_DECBOD (0x1UL << 4) /**< Brown Out Detector Decouple Domain Reset */
AnnaBridge 171:3a7713b1edbc 130 #define _RMU_RSTCAUSE_DECBOD_SHIFT 4 /**< Shift value for RMU_DECBOD */
AnnaBridge 171:3a7713b1edbc 131 #define _RMU_RSTCAUSE_DECBOD_MASK 0x10UL /**< Bit mask for RMU_DECBOD */
AnnaBridge 171:3a7713b1edbc 132 #define _RMU_RSTCAUSE_DECBOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 133 #define RMU_RSTCAUSE_DECBOD_DEFAULT (_RMU_RSTCAUSE_DECBOD_DEFAULT << 4) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 134 #define RMU_RSTCAUSE_EXTRST (0x1UL << 8) /**< External Pin Reset */
AnnaBridge 171:3a7713b1edbc 135 #define _RMU_RSTCAUSE_EXTRST_SHIFT 8 /**< Shift value for RMU_EXTRST */
AnnaBridge 171:3a7713b1edbc 136 #define _RMU_RSTCAUSE_EXTRST_MASK 0x100UL /**< Bit mask for RMU_EXTRST */
AnnaBridge 171:3a7713b1edbc 137 #define _RMU_RSTCAUSE_EXTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 138 #define RMU_RSTCAUSE_EXTRST_DEFAULT (_RMU_RSTCAUSE_EXTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 139 #define RMU_RSTCAUSE_LOCKUPRST (0x1UL << 9) /**< LOCKUP Reset */
AnnaBridge 171:3a7713b1edbc 140 #define _RMU_RSTCAUSE_LOCKUPRST_SHIFT 9 /**< Shift value for RMU_LOCKUPRST */
AnnaBridge 171:3a7713b1edbc 141 #define _RMU_RSTCAUSE_LOCKUPRST_MASK 0x200UL /**< Bit mask for RMU_LOCKUPRST */
AnnaBridge 171:3a7713b1edbc 142 #define _RMU_RSTCAUSE_LOCKUPRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 143 #define RMU_RSTCAUSE_LOCKUPRST_DEFAULT (_RMU_RSTCAUSE_LOCKUPRST_DEFAULT << 9) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 144 #define RMU_RSTCAUSE_SYSREQRST (0x1UL << 10) /**< System Request Reset */
AnnaBridge 171:3a7713b1edbc 145 #define _RMU_RSTCAUSE_SYSREQRST_SHIFT 10 /**< Shift value for RMU_SYSREQRST */
AnnaBridge 171:3a7713b1edbc 146 #define _RMU_RSTCAUSE_SYSREQRST_MASK 0x400UL /**< Bit mask for RMU_SYSREQRST */
AnnaBridge 171:3a7713b1edbc 147 #define _RMU_RSTCAUSE_SYSREQRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 148 #define RMU_RSTCAUSE_SYSREQRST_DEFAULT (_RMU_RSTCAUSE_SYSREQRST_DEFAULT << 10) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 149 #define RMU_RSTCAUSE_WDOGRST (0x1UL << 11) /**< Watchdog Reset */
AnnaBridge 171:3a7713b1edbc 150 #define _RMU_RSTCAUSE_WDOGRST_SHIFT 11 /**< Shift value for RMU_WDOGRST */
AnnaBridge 171:3a7713b1edbc 151 #define _RMU_RSTCAUSE_WDOGRST_MASK 0x800UL /**< Bit mask for RMU_WDOGRST */
AnnaBridge 171:3a7713b1edbc 152 #define _RMU_RSTCAUSE_WDOGRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 153 #define RMU_RSTCAUSE_WDOGRST_DEFAULT (_RMU_RSTCAUSE_WDOGRST_DEFAULT << 11) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 154 #define RMU_RSTCAUSE_EM4RST (0x1UL << 16) /**< EM4 Reset */
AnnaBridge 171:3a7713b1edbc 155 #define _RMU_RSTCAUSE_EM4RST_SHIFT 16 /**< Shift value for RMU_EM4RST */
AnnaBridge 171:3a7713b1edbc 156 #define _RMU_RSTCAUSE_EM4RST_MASK 0x10000UL /**< Bit mask for RMU_EM4RST */
AnnaBridge 171:3a7713b1edbc 157 #define _RMU_RSTCAUSE_EM4RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 158 #define RMU_RSTCAUSE_EM4RST_DEFAULT (_RMU_RSTCAUSE_EM4RST_DEFAULT << 16) /**< Shifted mode DEFAULT for RMU_RSTCAUSE */
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /* Bit fields for RMU CMD */
AnnaBridge 171:3a7713b1edbc 161 #define _RMU_CMD_RESETVALUE 0x00000000UL /**< Default value for RMU_CMD */
AnnaBridge 171:3a7713b1edbc 162 #define _RMU_CMD_MASK 0x00000001UL /**< Mask for RMU_CMD */
AnnaBridge 171:3a7713b1edbc 163 #define RMU_CMD_RCCLR (0x1UL << 0) /**< Reset Cause Clear */
AnnaBridge 171:3a7713b1edbc 164 #define _RMU_CMD_RCCLR_SHIFT 0 /**< Shift value for RMU_RCCLR */
AnnaBridge 171:3a7713b1edbc 165 #define _RMU_CMD_RCCLR_MASK 0x1UL /**< Bit mask for RMU_RCCLR */
AnnaBridge 171:3a7713b1edbc 166 #define _RMU_CMD_RCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_CMD */
AnnaBridge 171:3a7713b1edbc 167 #define RMU_CMD_RCCLR_DEFAULT (_RMU_CMD_RCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_CMD */
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 /* Bit fields for RMU RST */
AnnaBridge 171:3a7713b1edbc 170 #define _RMU_RST_RESETVALUE 0x00000000UL /**< Default value for RMU_RST */
AnnaBridge 171:3a7713b1edbc 171 #define _RMU_RST_MASK 0x00000000UL /**< Mask for RMU_RST */
AnnaBridge 171:3a7713b1edbc 172
AnnaBridge 171:3a7713b1edbc 173 /* Bit fields for RMU LOCK */
AnnaBridge 171:3a7713b1edbc 174 #define _RMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for RMU_LOCK */
AnnaBridge 171:3a7713b1edbc 175 #define _RMU_LOCK_MASK 0x0000FFFFUL /**< Mask for RMU_LOCK */
AnnaBridge 171:3a7713b1edbc 176 #define _RMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for RMU_LOCKKEY */
AnnaBridge 171:3a7713b1edbc 177 #define _RMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for RMU_LOCKKEY */
AnnaBridge 171:3a7713b1edbc 178 #define _RMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for RMU_LOCK */
AnnaBridge 171:3a7713b1edbc 179 #define _RMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for RMU_LOCK */
AnnaBridge 171:3a7713b1edbc 180 #define _RMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for RMU_LOCK */
AnnaBridge 171:3a7713b1edbc 181 #define _RMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for RMU_LOCK */
AnnaBridge 171:3a7713b1edbc 182 #define _RMU_LOCK_LOCKKEY_UNLOCK 0x0000E084UL /**< Mode UNLOCK for RMU_LOCK */
AnnaBridge 171:3a7713b1edbc 183 #define RMU_LOCK_LOCKKEY_DEFAULT (_RMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for RMU_LOCK */
AnnaBridge 171:3a7713b1edbc 184 #define RMU_LOCK_LOCKKEY_LOCK (_RMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for RMU_LOCK */
AnnaBridge 171:3a7713b1edbc 185 #define RMU_LOCK_LOCKKEY_UNLOCKED (_RMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for RMU_LOCK */
AnnaBridge 171:3a7713b1edbc 186 #define RMU_LOCK_LOCKKEY_LOCKED (_RMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for RMU_LOCK */
AnnaBridge 171:3a7713b1edbc 187 #define RMU_LOCK_LOCKKEY_UNLOCK (_RMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for RMU_LOCK */
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /** @} End of group EFM32PG12B_RMU */
AnnaBridge 171:3a7713b1edbc 190 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 191