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TARGET_EFM32LG_STK3600/TOOLCHAIN_IAR/efm32lg_emu.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32lg_emu.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32LG_EMU register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32LG_EMU
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32LG_EMU Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IOM uint32_t CTRL; /**< Control Register */
AnnaBridge 171:3a7713b1edbc 44
AnnaBridge 171:3a7713b1edbc 45 uint32_t RESERVED0[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 46 __IOM uint32_t LOCK; /**< Configuration Lock Register */
AnnaBridge 171:3a7713b1edbc 47
AnnaBridge 171:3a7713b1edbc 48 uint32_t RESERVED1[6]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 49 __IOM uint32_t AUXCTRL; /**< Auxiliary Control Register */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 uint32_t RESERVED2[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 52 __IOM uint32_t EM4CONF; /**< Energy mode 4 configuration register */
AnnaBridge 171:3a7713b1edbc 53 __IOM uint32_t BUCTRL; /**< Backup Power configuration register */
AnnaBridge 171:3a7713b1edbc 54 __IOM uint32_t PWRCONF; /**< Power connection configuration register */
AnnaBridge 171:3a7713b1edbc 55 __IOM uint32_t BUINACT; /**< Backup mode inactive configuration register */
AnnaBridge 171:3a7713b1edbc 56 __IOM uint32_t BUACT; /**< Backup mode active configuration register */
AnnaBridge 171:3a7713b1edbc 57 __IM uint32_t STATUS; /**< Status register */
AnnaBridge 171:3a7713b1edbc 58 __IOM uint32_t ROUTE; /**< I/O Routing Register */
AnnaBridge 171:3a7713b1edbc 59 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 60 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 171:3a7713b1edbc 61 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 171:3a7713b1edbc 62 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 63 __IOM uint32_t BUBODBUVINCAL; /**< BU_VIN Backup BOD calibration */
AnnaBridge 171:3a7713b1edbc 64 __IOM uint32_t BUBODUNREGCAL; /**< Unregulated power Backup BOD calibration */
AnnaBridge 171:3a7713b1edbc 65 } EMU_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 68 * @defgroup EFM32LG_EMU_BitFields
AnnaBridge 171:3a7713b1edbc 69 * @{
AnnaBridge 171:3a7713b1edbc 70 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 /* Bit fields for EMU CTRL */
AnnaBridge 171:3a7713b1edbc 73 #define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
AnnaBridge 171:3a7713b1edbc 74 #define _EMU_CTRL_MASK 0x0000000FUL /**< Mask for EMU_CTRL */
AnnaBridge 171:3a7713b1edbc 75 #define EMU_CTRL_EMVREG (0x1UL << 0) /**< Energy Mode Voltage Regulator Control */
AnnaBridge 171:3a7713b1edbc 76 #define _EMU_CTRL_EMVREG_SHIFT 0 /**< Shift value for EMU_EMVREG */
AnnaBridge 171:3a7713b1edbc 77 #define _EMU_CTRL_EMVREG_MASK 0x1UL /**< Bit mask for EMU_EMVREG */
AnnaBridge 171:3a7713b1edbc 78 #define _EMU_CTRL_EMVREG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
AnnaBridge 171:3a7713b1edbc 79 #define _EMU_CTRL_EMVREG_REDUCED 0x00000000UL /**< Mode REDUCED for EMU_CTRL */
AnnaBridge 171:3a7713b1edbc 80 #define _EMU_CTRL_EMVREG_FULL 0x00000001UL /**< Mode FULL for EMU_CTRL */
AnnaBridge 171:3a7713b1edbc 81 #define EMU_CTRL_EMVREG_DEFAULT (_EMU_CTRL_EMVREG_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CTRL */
AnnaBridge 171:3a7713b1edbc 82 #define EMU_CTRL_EMVREG_REDUCED (_EMU_CTRL_EMVREG_REDUCED << 0) /**< Shifted mode REDUCED for EMU_CTRL */
AnnaBridge 171:3a7713b1edbc 83 #define EMU_CTRL_EMVREG_FULL (_EMU_CTRL_EMVREG_FULL << 0) /**< Shifted mode FULL for EMU_CTRL */
AnnaBridge 171:3a7713b1edbc 84 #define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */
AnnaBridge 171:3a7713b1edbc 85 #define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */
AnnaBridge 171:3a7713b1edbc 86 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */
AnnaBridge 171:3a7713b1edbc 87 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
AnnaBridge 171:3a7713b1edbc 88 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
AnnaBridge 171:3a7713b1edbc 89 #define _EMU_CTRL_EM4CTRL_SHIFT 2 /**< Shift value for EMU_EM4CTRL */
AnnaBridge 171:3a7713b1edbc 90 #define _EMU_CTRL_EM4CTRL_MASK 0xCUL /**< Bit mask for EMU_EM4CTRL */
AnnaBridge 171:3a7713b1edbc 91 #define _EMU_CTRL_EM4CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
AnnaBridge 171:3a7713b1edbc 92 #define EMU_CTRL_EM4CTRL_DEFAULT (_EMU_CTRL_EM4CTRL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */
AnnaBridge 171:3a7713b1edbc 93
AnnaBridge 171:3a7713b1edbc 94 /* Bit fields for EMU LOCK */
AnnaBridge 171:3a7713b1edbc 95 #define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */
AnnaBridge 171:3a7713b1edbc 96 #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */
AnnaBridge 171:3a7713b1edbc 97 #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
AnnaBridge 171:3a7713b1edbc 98 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
AnnaBridge 171:3a7713b1edbc 99 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
AnnaBridge 171:3a7713b1edbc 100 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
AnnaBridge 171:3a7713b1edbc 101 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
AnnaBridge 171:3a7713b1edbc 102 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
AnnaBridge 171:3a7713b1edbc 103 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
AnnaBridge 171:3a7713b1edbc 104 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
AnnaBridge 171:3a7713b1edbc 105 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
AnnaBridge 171:3a7713b1edbc 106 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
AnnaBridge 171:3a7713b1edbc 107 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
AnnaBridge 171:3a7713b1edbc 108 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 /* Bit fields for EMU AUXCTRL */
AnnaBridge 171:3a7713b1edbc 111 #define _EMU_AUXCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_AUXCTRL */
AnnaBridge 171:3a7713b1edbc 112 #define _EMU_AUXCTRL_MASK 0x00000001UL /**< Mask for EMU_AUXCTRL */
AnnaBridge 171:3a7713b1edbc 113 #define EMU_AUXCTRL_HRCCLR (0x1UL << 0) /**< Hard Reset Cause Clear */
AnnaBridge 171:3a7713b1edbc 114 #define _EMU_AUXCTRL_HRCCLR_SHIFT 0 /**< Shift value for EMU_HRCCLR */
AnnaBridge 171:3a7713b1edbc 115 #define _EMU_AUXCTRL_HRCCLR_MASK 0x1UL /**< Bit mask for EMU_HRCCLR */
AnnaBridge 171:3a7713b1edbc 116 #define _EMU_AUXCTRL_HRCCLR_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_AUXCTRL */
AnnaBridge 171:3a7713b1edbc 117 #define EMU_AUXCTRL_HRCCLR_DEFAULT (_EMU_AUXCTRL_HRCCLR_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_AUXCTRL */
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 /* Bit fields for EMU EM4CONF */
AnnaBridge 171:3a7713b1edbc 120 #define _EMU_EM4CONF_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 121 #define _EMU_EM4CONF_MASK 0x0001001FUL /**< Mask for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 122 #define EMU_EM4CONF_VREGEN (0x1UL << 0) /**< EM4 voltage regulator enable */
AnnaBridge 171:3a7713b1edbc 123 #define _EMU_EM4CONF_VREGEN_SHIFT 0 /**< Shift value for EMU_VREGEN */
AnnaBridge 171:3a7713b1edbc 124 #define _EMU_EM4CONF_VREGEN_MASK 0x1UL /**< Bit mask for EMU_VREGEN */
AnnaBridge 171:3a7713b1edbc 125 #define _EMU_EM4CONF_VREGEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 126 #define EMU_EM4CONF_VREGEN_DEFAULT (_EMU_EM4CONF_VREGEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 127 #define EMU_EM4CONF_BURTCWU (0x1UL << 1) /**< Backup RTC EM4 wakeup enable */
AnnaBridge 171:3a7713b1edbc 128 #define _EMU_EM4CONF_BURTCWU_SHIFT 1 /**< Shift value for EMU_BURTCWU */
AnnaBridge 171:3a7713b1edbc 129 #define _EMU_EM4CONF_BURTCWU_MASK 0x2UL /**< Bit mask for EMU_BURTCWU */
AnnaBridge 171:3a7713b1edbc 130 #define _EMU_EM4CONF_BURTCWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 131 #define EMU_EM4CONF_BURTCWU_DEFAULT (_EMU_EM4CONF_BURTCWU_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 132 #define _EMU_EM4CONF_OSC_SHIFT 2 /**< Shift value for EMU_OSC */
AnnaBridge 171:3a7713b1edbc 133 #define _EMU_EM4CONF_OSC_MASK 0xCUL /**< Bit mask for EMU_OSC */
AnnaBridge 171:3a7713b1edbc 134 #define _EMU_EM4CONF_OSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 135 #define _EMU_EM4CONF_OSC_ULFRCO 0x00000000UL /**< Mode ULFRCO for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 136 #define _EMU_EM4CONF_OSC_LFRCO 0x00000001UL /**< Mode LFRCO for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 137 #define _EMU_EM4CONF_OSC_LFXO 0x00000002UL /**< Mode LFXO for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 138 #define EMU_EM4CONF_OSC_DEFAULT (_EMU_EM4CONF_OSC_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 139 #define EMU_EM4CONF_OSC_ULFRCO (_EMU_EM4CONF_OSC_ULFRCO << 2) /**< Shifted mode ULFRCO for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 140 #define EMU_EM4CONF_OSC_LFRCO (_EMU_EM4CONF_OSC_LFRCO << 2) /**< Shifted mode LFRCO for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 141 #define EMU_EM4CONF_OSC_LFXO (_EMU_EM4CONF_OSC_LFXO << 2) /**< Shifted mode LFXO for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 142 #define EMU_EM4CONF_BUBODRSTDIS (0x1UL << 4) /**< Disable reset from Backup BOD in EM4 */
AnnaBridge 171:3a7713b1edbc 143 #define _EMU_EM4CONF_BUBODRSTDIS_SHIFT 4 /**< Shift value for EMU_BUBODRSTDIS */
AnnaBridge 171:3a7713b1edbc 144 #define _EMU_EM4CONF_BUBODRSTDIS_MASK 0x10UL /**< Bit mask for EMU_BUBODRSTDIS */
AnnaBridge 171:3a7713b1edbc 145 #define _EMU_EM4CONF_BUBODRSTDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 146 #define EMU_EM4CONF_BUBODRSTDIS_DEFAULT (_EMU_EM4CONF_BUBODRSTDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 147 #define EMU_EM4CONF_LOCKCONF (0x1UL << 16) /**< EM4 configuration lock enable */
AnnaBridge 171:3a7713b1edbc 148 #define _EMU_EM4CONF_LOCKCONF_SHIFT 16 /**< Shift value for EMU_LOCKCONF */
AnnaBridge 171:3a7713b1edbc 149 #define _EMU_EM4CONF_LOCKCONF_MASK 0x10000UL /**< Bit mask for EMU_LOCKCONF */
AnnaBridge 171:3a7713b1edbc 150 #define _EMU_EM4CONF_LOCKCONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 151 #define EMU_EM4CONF_LOCKCONF_DEFAULT (_EMU_EM4CONF_LOCKCONF_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CONF */
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 /* Bit fields for EMU BUCTRL */
AnnaBridge 171:3a7713b1edbc 154 #define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 155 #define _EMU_BUCTRL_MASK 0x0000006FUL /**< Mask for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 156 #define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable backup mode */
AnnaBridge 171:3a7713b1edbc 157 #define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
AnnaBridge 171:3a7713b1edbc 158 #define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
AnnaBridge 171:3a7713b1edbc 159 #define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 160 #define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 161 #define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable backup mode status export */
AnnaBridge 171:3a7713b1edbc 162 #define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */
AnnaBridge 171:3a7713b1edbc 163 #define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */
AnnaBridge 171:3a7713b1edbc 164 #define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 165 #define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 166 #define EMU_BUCTRL_BODCAL (0x1UL << 2) /**< Enable BOD calibration mode */
AnnaBridge 171:3a7713b1edbc 167 #define _EMU_BUCTRL_BODCAL_SHIFT 2 /**< Shift value for EMU_BODCAL */
AnnaBridge 171:3a7713b1edbc 168 #define _EMU_BUCTRL_BODCAL_MASK 0x4UL /**< Bit mask for EMU_BODCAL */
AnnaBridge 171:3a7713b1edbc 169 #define _EMU_BUCTRL_BODCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 170 #define EMU_BUCTRL_BODCAL_DEFAULT (_EMU_BUCTRL_BODCAL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 171 #define EMU_BUCTRL_BUMODEBODEN (0x1UL << 3) /**< Enable brown out detection on BU_VIN when in backup mode */
AnnaBridge 171:3a7713b1edbc 172 #define _EMU_BUCTRL_BUMODEBODEN_SHIFT 3 /**< Shift value for EMU_BUMODEBODEN */
AnnaBridge 171:3a7713b1edbc 173 #define _EMU_BUCTRL_BUMODEBODEN_MASK 0x8UL /**< Bit mask for EMU_BUMODEBODEN */
AnnaBridge 171:3a7713b1edbc 174 #define _EMU_BUCTRL_BUMODEBODEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 175 #define EMU_BUCTRL_BUMODEBODEN_DEFAULT (_EMU_BUCTRL_BUMODEBODEN_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 176 #define _EMU_BUCTRL_PROBE_SHIFT 5 /**< Shift value for EMU_PROBE */
AnnaBridge 171:3a7713b1edbc 177 #define _EMU_BUCTRL_PROBE_MASK 0x60UL /**< Bit mask for EMU_PROBE */
AnnaBridge 171:3a7713b1edbc 178 #define _EMU_BUCTRL_PROBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 179 #define _EMU_BUCTRL_PROBE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 180 #define _EMU_BUCTRL_PROBE_VDDDREG 0x00000001UL /**< Mode VDDDREG for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 181 #define _EMU_BUCTRL_PROBE_BUIN 0x00000002UL /**< Mode BUIN for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 182 #define _EMU_BUCTRL_PROBE_BUOUT 0x00000003UL /**< Mode BUOUT for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 183 #define EMU_BUCTRL_PROBE_DEFAULT (_EMU_BUCTRL_PROBE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 184 #define EMU_BUCTRL_PROBE_DISABLE (_EMU_BUCTRL_PROBE_DISABLE << 5) /**< Shifted mode DISABLE for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 185 #define EMU_BUCTRL_PROBE_VDDDREG (_EMU_BUCTRL_PROBE_VDDDREG << 5) /**< Shifted mode VDDDREG for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 186 #define EMU_BUCTRL_PROBE_BUIN (_EMU_BUCTRL_PROBE_BUIN << 5) /**< Shifted mode BUIN for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 187 #define EMU_BUCTRL_PROBE_BUOUT (_EMU_BUCTRL_PROBE_BUOUT << 5) /**< Shifted mode BUOUT for EMU_BUCTRL */
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /* Bit fields for EMU PWRCONF */
AnnaBridge 171:3a7713b1edbc 190 #define _EMU_PWRCONF_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 191 #define _EMU_PWRCONF_MASK 0x0000001FUL /**< Mask for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 192 #define EMU_PWRCONF_VOUTWEAK (0x1UL << 0) /**< BU_VOUT weak enable */
AnnaBridge 171:3a7713b1edbc 193 #define _EMU_PWRCONF_VOUTWEAK_SHIFT 0 /**< Shift value for EMU_VOUTWEAK */
AnnaBridge 171:3a7713b1edbc 194 #define _EMU_PWRCONF_VOUTWEAK_MASK 0x1UL /**< Bit mask for EMU_VOUTWEAK */
AnnaBridge 171:3a7713b1edbc 195 #define _EMU_PWRCONF_VOUTWEAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 196 #define EMU_PWRCONF_VOUTWEAK_DEFAULT (_EMU_PWRCONF_VOUTWEAK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 197 #define EMU_PWRCONF_VOUTMED (0x1UL << 1) /**< BU_VOUT medium enable */
AnnaBridge 171:3a7713b1edbc 198 #define _EMU_PWRCONF_VOUTMED_SHIFT 1 /**< Shift value for EMU_VOUTMED */
AnnaBridge 171:3a7713b1edbc 199 #define _EMU_PWRCONF_VOUTMED_MASK 0x2UL /**< Bit mask for EMU_VOUTMED */
AnnaBridge 171:3a7713b1edbc 200 #define _EMU_PWRCONF_VOUTMED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 201 #define EMU_PWRCONF_VOUTMED_DEFAULT (_EMU_PWRCONF_VOUTMED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 202 #define EMU_PWRCONF_VOUTSTRONG (0x1UL << 2) /**< BU_VOUT strong enable */
AnnaBridge 171:3a7713b1edbc 203 #define _EMU_PWRCONF_VOUTSTRONG_SHIFT 2 /**< Shift value for EMU_VOUTSTRONG */
AnnaBridge 171:3a7713b1edbc 204 #define _EMU_PWRCONF_VOUTSTRONG_MASK 0x4UL /**< Bit mask for EMU_VOUTSTRONG */
AnnaBridge 171:3a7713b1edbc 205 #define _EMU_PWRCONF_VOUTSTRONG_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 206 #define EMU_PWRCONF_VOUTSTRONG_DEFAULT (_EMU_PWRCONF_VOUTSTRONG_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 207 #define _EMU_PWRCONF_PWRRES_SHIFT 3 /**< Shift value for EMU_PWRRES */
AnnaBridge 171:3a7713b1edbc 208 #define _EMU_PWRCONF_PWRRES_MASK 0x18UL /**< Bit mask for EMU_PWRRES */
AnnaBridge 171:3a7713b1edbc 209 #define _EMU_PWRCONF_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 210 #define _EMU_PWRCONF_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 211 #define _EMU_PWRCONF_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 212 #define _EMU_PWRCONF_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 213 #define _EMU_PWRCONF_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 214 #define EMU_PWRCONF_PWRRES_DEFAULT (_EMU_PWRCONF_PWRRES_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 215 #define EMU_PWRCONF_PWRRES_RES0 (_EMU_PWRCONF_PWRRES_RES0 << 3) /**< Shifted mode RES0 for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 216 #define EMU_PWRCONF_PWRRES_RES1 (_EMU_PWRCONF_PWRRES_RES1 << 3) /**< Shifted mode RES1 for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 217 #define EMU_PWRCONF_PWRRES_RES2 (_EMU_PWRCONF_PWRRES_RES2 << 3) /**< Shifted mode RES2 for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 218 #define EMU_PWRCONF_PWRRES_RES3 (_EMU_PWRCONF_PWRRES_RES3 << 3) /**< Shifted mode RES3 for EMU_PWRCONF */
AnnaBridge 171:3a7713b1edbc 219
AnnaBridge 171:3a7713b1edbc 220 /* Bit fields for EMU BUINACT */
AnnaBridge 171:3a7713b1edbc 221 #define _EMU_BUINACT_RESETVALUE 0x0000000BUL /**< Default value for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 222 #define _EMU_BUINACT_MASK 0x0000007FUL /**< Mask for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 223 #define _EMU_BUINACT_BUENTHRES_SHIFT 0 /**< Shift value for EMU_BUENTHRES */
AnnaBridge 171:3a7713b1edbc 224 #define _EMU_BUINACT_BUENTHRES_MASK 0x7UL /**< Bit mask for EMU_BUENTHRES */
AnnaBridge 171:3a7713b1edbc 225 #define _EMU_BUINACT_BUENTHRES_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 226 #define EMU_BUINACT_BUENTHRES_DEFAULT (_EMU_BUINACT_BUENTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 227 #define _EMU_BUINACT_BUENRANGE_SHIFT 3 /**< Shift value for EMU_BUENRANGE */
AnnaBridge 171:3a7713b1edbc 228 #define _EMU_BUINACT_BUENRANGE_MASK 0x18UL /**< Bit mask for EMU_BUENRANGE */
AnnaBridge 171:3a7713b1edbc 229 #define _EMU_BUINACT_BUENRANGE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 230 #define EMU_BUINACT_BUENRANGE_DEFAULT (_EMU_BUINACT_BUENRANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 231 #define _EMU_BUINACT_PWRCON_SHIFT 5 /**< Shift value for EMU_PWRCON */
AnnaBridge 171:3a7713b1edbc 232 #define _EMU_BUINACT_PWRCON_MASK 0x60UL /**< Bit mask for EMU_PWRCON */
AnnaBridge 171:3a7713b1edbc 233 #define _EMU_BUINACT_PWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 234 #define _EMU_BUINACT_PWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 235 #define _EMU_BUINACT_PWRCON_BUMAIN 0x00000001UL /**< Mode BUMAIN for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 236 #define _EMU_BUINACT_PWRCON_MAINBU 0x00000002UL /**< Mode MAINBU for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 237 #define _EMU_BUINACT_PWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 238 #define EMU_BUINACT_PWRCON_DEFAULT (_EMU_BUINACT_PWRCON_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 239 #define EMU_BUINACT_PWRCON_NONE (_EMU_BUINACT_PWRCON_NONE << 5) /**< Shifted mode NONE for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 240 #define EMU_BUINACT_PWRCON_BUMAIN (_EMU_BUINACT_PWRCON_BUMAIN << 5) /**< Shifted mode BUMAIN for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 241 #define EMU_BUINACT_PWRCON_MAINBU (_EMU_BUINACT_PWRCON_MAINBU << 5) /**< Shifted mode MAINBU for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 242 #define EMU_BUINACT_PWRCON_NODIODE (_EMU_BUINACT_PWRCON_NODIODE << 5) /**< Shifted mode NODIODE for EMU_BUINACT */
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 /* Bit fields for EMU BUACT */
AnnaBridge 171:3a7713b1edbc 245 #define _EMU_BUACT_RESETVALUE 0x0000000BUL /**< Default value for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 246 #define _EMU_BUACT_MASK 0x0000007FUL /**< Mask for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 247 #define _EMU_BUACT_BUEXTHRES_SHIFT 0 /**< Shift value for EMU_BUEXTHRES */
AnnaBridge 171:3a7713b1edbc 248 #define _EMU_BUACT_BUEXTHRES_MASK 0x7UL /**< Bit mask for EMU_BUEXTHRES */
AnnaBridge 171:3a7713b1edbc 249 #define _EMU_BUACT_BUEXTHRES_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 250 #define EMU_BUACT_BUEXTHRES_DEFAULT (_EMU_BUACT_BUEXTHRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 251 #define _EMU_BUACT_BUEXRANGE_SHIFT 3 /**< Shift value for EMU_BUEXRANGE */
AnnaBridge 171:3a7713b1edbc 252 #define _EMU_BUACT_BUEXRANGE_MASK 0x18UL /**< Bit mask for EMU_BUEXRANGE */
AnnaBridge 171:3a7713b1edbc 253 #define _EMU_BUACT_BUEXRANGE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 254 #define EMU_BUACT_BUEXRANGE_DEFAULT (_EMU_BUACT_BUEXRANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 255 #define _EMU_BUACT_PWRCON_SHIFT 5 /**< Shift value for EMU_PWRCON */
AnnaBridge 171:3a7713b1edbc 256 #define _EMU_BUACT_PWRCON_MASK 0x60UL /**< Bit mask for EMU_PWRCON */
AnnaBridge 171:3a7713b1edbc 257 #define _EMU_BUACT_PWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 258 #define _EMU_BUACT_PWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 259 #define _EMU_BUACT_PWRCON_BUMAIN 0x00000001UL /**< Mode BUMAIN for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 260 #define _EMU_BUACT_PWRCON_MAINBU 0x00000002UL /**< Mode MAINBU for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 261 #define _EMU_BUACT_PWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 262 #define EMU_BUACT_PWRCON_DEFAULT (_EMU_BUACT_PWRCON_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 263 #define EMU_BUACT_PWRCON_NONE (_EMU_BUACT_PWRCON_NONE << 5) /**< Shifted mode NONE for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 264 #define EMU_BUACT_PWRCON_BUMAIN (_EMU_BUACT_PWRCON_BUMAIN << 5) /**< Shifted mode BUMAIN for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 265 #define EMU_BUACT_PWRCON_MAINBU (_EMU_BUACT_PWRCON_MAINBU << 5) /**< Shifted mode MAINBU for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 266 #define EMU_BUACT_PWRCON_NODIODE (_EMU_BUACT_PWRCON_NODIODE << 5) /**< Shifted mode NODIODE for EMU_BUACT */
AnnaBridge 171:3a7713b1edbc 267
AnnaBridge 171:3a7713b1edbc 268 /* Bit fields for EMU STATUS */
AnnaBridge 171:3a7713b1edbc 269 #define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */
AnnaBridge 171:3a7713b1edbc 270 #define _EMU_STATUS_MASK 0x00000001UL /**< Mask for EMU_STATUS */
AnnaBridge 171:3a7713b1edbc 271 #define EMU_STATUS_BURDY (0x1UL << 0) /**< Backup mode ready */
AnnaBridge 171:3a7713b1edbc 272 #define _EMU_STATUS_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */
AnnaBridge 171:3a7713b1edbc 273 #define _EMU_STATUS_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */
AnnaBridge 171:3a7713b1edbc 274 #define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 171:3a7713b1edbc 275 #define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 /* Bit fields for EMU ROUTE */
AnnaBridge 171:3a7713b1edbc 278 #define _EMU_ROUTE_RESETVALUE 0x00000001UL /**< Default value for EMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 279 #define _EMU_ROUTE_MASK 0x00000001UL /**< Mask for EMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 280 #define EMU_ROUTE_BUVINPEN (0x1UL << 0) /**< BU_VIN Pin Enable */
AnnaBridge 171:3a7713b1edbc 281 #define _EMU_ROUTE_BUVINPEN_SHIFT 0 /**< Shift value for EMU_BUVINPEN */
AnnaBridge 171:3a7713b1edbc 282 #define _EMU_ROUTE_BUVINPEN_MASK 0x1UL /**< Bit mask for EMU_BUVINPEN */
AnnaBridge 171:3a7713b1edbc 283 #define _EMU_ROUTE_BUVINPEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 284 #define EMU_ROUTE_BUVINPEN_DEFAULT (_EMU_ROUTE_BUVINPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 /* Bit fields for EMU IF */
AnnaBridge 171:3a7713b1edbc 287 #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */
AnnaBridge 171:3a7713b1edbc 288 #define _EMU_IF_MASK 0x00000001UL /**< Mask for EMU_IF */
AnnaBridge 171:3a7713b1edbc 289 #define EMU_IF_BURDY (0x1UL << 0) /**< Backup functionality ready Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 290 #define _EMU_IF_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */
AnnaBridge 171:3a7713b1edbc 291 #define _EMU_IF_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */
AnnaBridge 171:3a7713b1edbc 292 #define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 171:3a7713b1edbc 293 #define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 /* Bit fields for EMU IFS */
AnnaBridge 171:3a7713b1edbc 296 #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */
AnnaBridge 171:3a7713b1edbc 297 #define _EMU_IFS_MASK 0x00000001UL /**< Mask for EMU_IFS */
AnnaBridge 171:3a7713b1edbc 298 #define EMU_IFS_BURDY (0x1UL << 0) /**< Set Backup functionality ready Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 299 #define _EMU_IFS_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */
AnnaBridge 171:3a7713b1edbc 300 #define _EMU_IFS_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */
AnnaBridge 171:3a7713b1edbc 301 #define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 171:3a7713b1edbc 302 #define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304 /* Bit fields for EMU IFC */
AnnaBridge 171:3a7713b1edbc 305 #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */
AnnaBridge 171:3a7713b1edbc 306 #define _EMU_IFC_MASK 0x00000001UL /**< Mask for EMU_IFC */
AnnaBridge 171:3a7713b1edbc 307 #define EMU_IFC_BURDY (0x1UL << 0) /**< Clear Backup functionality ready Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 308 #define _EMU_IFC_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */
AnnaBridge 171:3a7713b1edbc 309 #define _EMU_IFC_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */
AnnaBridge 171:3a7713b1edbc 310 #define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 171:3a7713b1edbc 311 #define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 171:3a7713b1edbc 312
AnnaBridge 171:3a7713b1edbc 313 /* Bit fields for EMU IEN */
AnnaBridge 171:3a7713b1edbc 314 #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */
AnnaBridge 171:3a7713b1edbc 315 #define _EMU_IEN_MASK 0x00000001UL /**< Mask for EMU_IEN */
AnnaBridge 171:3a7713b1edbc 316 #define EMU_IEN_BURDY (0x1UL << 0) /**< Backup functionality ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 317 #define _EMU_IEN_BURDY_SHIFT 0 /**< Shift value for EMU_BURDY */
AnnaBridge 171:3a7713b1edbc 318 #define _EMU_IEN_BURDY_MASK 0x1UL /**< Bit mask for EMU_BURDY */
AnnaBridge 171:3a7713b1edbc 319 #define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 171:3a7713b1edbc 320 #define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 171:3a7713b1edbc 321
AnnaBridge 171:3a7713b1edbc 322 /* Bit fields for EMU BUBODBUVINCAL */
AnnaBridge 171:3a7713b1edbc 323 #define _EMU_BUBODBUVINCAL_RESETVALUE 0x0000000BUL /**< Default value for EMU_BUBODBUVINCAL */
AnnaBridge 171:3a7713b1edbc 324 #define _EMU_BUBODBUVINCAL_MASK 0x0000001FUL /**< Mask for EMU_BUBODBUVINCAL */
AnnaBridge 171:3a7713b1edbc 325 #define _EMU_BUBODBUVINCAL_THRES_SHIFT 0 /**< Shift value for EMU_THRES */
AnnaBridge 171:3a7713b1edbc 326 #define _EMU_BUBODBUVINCAL_THRES_MASK 0x7UL /**< Bit mask for EMU_THRES */
AnnaBridge 171:3a7713b1edbc 327 #define _EMU_BUBODBUVINCAL_THRES_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_BUBODBUVINCAL */
AnnaBridge 171:3a7713b1edbc 328 #define EMU_BUBODBUVINCAL_THRES_DEFAULT (_EMU_BUBODBUVINCAL_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUBODBUVINCAL */
AnnaBridge 171:3a7713b1edbc 329 #define _EMU_BUBODBUVINCAL_RANGE_SHIFT 3 /**< Shift value for EMU_RANGE */
AnnaBridge 171:3a7713b1edbc 330 #define _EMU_BUBODBUVINCAL_RANGE_MASK 0x18UL /**< Bit mask for EMU_RANGE */
AnnaBridge 171:3a7713b1edbc 331 #define _EMU_BUBODBUVINCAL_RANGE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BUBODBUVINCAL */
AnnaBridge 171:3a7713b1edbc 332 #define EMU_BUBODBUVINCAL_RANGE_DEFAULT (_EMU_BUBODBUVINCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODBUVINCAL */
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334 /* Bit fields for EMU BUBODUNREGCAL */
AnnaBridge 171:3a7713b1edbc 335 #define _EMU_BUBODUNREGCAL_RESETVALUE 0x0000000BUL /**< Default value for EMU_BUBODUNREGCAL */
AnnaBridge 171:3a7713b1edbc 336 #define _EMU_BUBODUNREGCAL_MASK 0x0000001FUL /**< Mask for EMU_BUBODUNREGCAL */
AnnaBridge 171:3a7713b1edbc 337 #define _EMU_BUBODUNREGCAL_THRES_SHIFT 0 /**< Shift value for EMU_THRES */
AnnaBridge 171:3a7713b1edbc 338 #define _EMU_BUBODUNREGCAL_THRES_MASK 0x7UL /**< Bit mask for EMU_THRES */
AnnaBridge 171:3a7713b1edbc 339 #define _EMU_BUBODUNREGCAL_THRES_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_BUBODUNREGCAL */
AnnaBridge 171:3a7713b1edbc 340 #define EMU_BUBODUNREGCAL_THRES_DEFAULT (_EMU_BUBODUNREGCAL_THRES_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
AnnaBridge 171:3a7713b1edbc 341 #define _EMU_BUBODUNREGCAL_RANGE_SHIFT 3 /**< Shift value for EMU_RANGE */
AnnaBridge 171:3a7713b1edbc 342 #define _EMU_BUBODUNREGCAL_RANGE_MASK 0x18UL /**< Bit mask for EMU_RANGE */
AnnaBridge 171:3a7713b1edbc 343 #define _EMU_BUBODUNREGCAL_RANGE_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_BUBODUNREGCAL */
AnnaBridge 171:3a7713b1edbc 344 #define EMU_BUBODUNREGCAL_RANGE_DEFAULT (_EMU_BUBODUNREGCAL_RANGE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_BUBODUNREGCAL */
AnnaBridge 171:3a7713b1edbc 345
AnnaBridge 171:3a7713b1edbc 346 /** @} End of group EFM32LG_EMU */
AnnaBridge 171:3a7713b1edbc 347 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 348