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TARGET_EFM32LG_STK3600/TOOLCHAIN_GCC_ARM/efm32lg_burtc.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 2 | * @file efm32lg_burtc.h |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @brief EFM32LG_BURTC register and bit field definitions |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @version 5.1.2 |
| AnnaBridge | 171:3a7713b1edbc | 5 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 6 | * @section License |
| AnnaBridge | 171:3a7713b1edbc | 7 | * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| AnnaBridge | 171:3a7713b1edbc | 8 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 9 | * |
| AnnaBridge | 171:3a7713b1edbc | 10 | * Permission is granted to anyone to use this software for any purpose, |
| AnnaBridge | 171:3a7713b1edbc | 11 | * including commercial applications, and to alter it and redistribute it |
| AnnaBridge | 171:3a7713b1edbc | 12 | * freely, subject to the following restrictions: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * |
| AnnaBridge | 171:3a7713b1edbc | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| AnnaBridge | 171:3a7713b1edbc | 15 | * claim that you wrote the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| AnnaBridge | 171:3a7713b1edbc | 17 | * misrepresented as being the original software.@n |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| AnnaBridge | 171:3a7713b1edbc | 19 | * |
| AnnaBridge | 171:3a7713b1edbc | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| AnnaBridge | 171:3a7713b1edbc | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| AnnaBridge | 171:3a7713b1edbc | 23 | * kind, including, but not limited to, any implied warranties of |
| AnnaBridge | 171:3a7713b1edbc | 24 | * merchantability or fitness for any particular purpose or warranties against |
| AnnaBridge | 171:3a7713b1edbc | 25 | * infringement of any proprietary rights of a third party. |
| AnnaBridge | 171:3a7713b1edbc | 26 | * |
| AnnaBridge | 171:3a7713b1edbc | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| AnnaBridge | 171:3a7713b1edbc | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| AnnaBridge | 171:3a7713b1edbc | 29 | * any third party, arising from your use of this Software. |
| AnnaBridge | 171:3a7713b1edbc | 30 | * |
| AnnaBridge | 171:3a7713b1edbc | 31 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 32 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 33 | * @addtogroup Parts |
| AnnaBridge | 171:3a7713b1edbc | 34 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 35 | ******************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 36 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 37 | * @defgroup EFM32LG_BURTC |
| AnnaBridge | 171:3a7713b1edbc | 38 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 39 | * @brief EFM32LG_BURTC Register Declaration |
| AnnaBridge | 171:3a7713b1edbc | 40 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 41 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 42 | { |
| AnnaBridge | 171:3a7713b1edbc | 43 | __IOM uint32_t CTRL; /**< Control Register */ |
| AnnaBridge | 171:3a7713b1edbc | 44 | __IOM uint32_t LPMODE; /**< Low power mode configuration */ |
| AnnaBridge | 171:3a7713b1edbc | 45 | __IM uint32_t CNT; /**< Counter Value Register */ |
| AnnaBridge | 171:3a7713b1edbc | 46 | __IOM uint32_t COMP0; /**< Counter Compare Value */ |
| AnnaBridge | 171:3a7713b1edbc | 47 | __IM uint32_t TIMESTAMP; /**< Backup mode timestamp */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | __IOM uint32_t LFXOFDET; /**< LFXO */ |
| AnnaBridge | 171:3a7713b1edbc | 49 | __IM uint32_t STATUS; /**< Status Register */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | __IOM uint32_t CMD; /**< Command Register */ |
| AnnaBridge | 171:3a7713b1edbc | 51 | __IOM uint32_t POWERDOWN; /**< Retention RAM power-down Register */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | __IOM uint32_t LOCK; /**< Configuration Lock Register */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | __IM uint32_t IF; /**< Interrupt Flag Register */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | __IOM uint32_t IFS; /**< Interrupt Flag Set Register */ |
| AnnaBridge | 171:3a7713b1edbc | 55 | __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | __IOM uint32_t IEN; /**< Interrupt Enable Register */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | |
| AnnaBridge | 171:3a7713b1edbc | 58 | __IOM uint32_t FREEZE; /**< Freeze Register */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | |
| AnnaBridge | 171:3a7713b1edbc | 61 | uint32_t RESERVED0[48]; /**< Reserved registers */ |
| AnnaBridge | 171:3a7713b1edbc | 62 | BURTC_RET_TypeDef RET[128]; /**< RetentionReg */ |
| AnnaBridge | 171:3a7713b1edbc | 63 | } BURTC_TypeDef; /** @} */ |
| AnnaBridge | 171:3a7713b1edbc | 64 | |
| AnnaBridge | 171:3a7713b1edbc | 65 | /**************************************************************************//** |
| AnnaBridge | 171:3a7713b1edbc | 66 | * @defgroup EFM32LG_BURTC_BitFields |
| AnnaBridge | 171:3a7713b1edbc | 67 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 68 | *****************************************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 69 | |
| AnnaBridge | 171:3a7713b1edbc | 70 | /* Bit fields for BURTC CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | #define _BURTC_CTRL_RESETVALUE 0x00000008UL /**< Default value for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | #define _BURTC_CTRL_MASK 0x000077FFUL /**< Mask for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | #define _BURTC_CTRL_MODE_SHIFT 0 /**< Shift value for BURTC_MODE */ |
| AnnaBridge | 171:3a7713b1edbc | 74 | #define _BURTC_CTRL_MODE_MASK 0x3UL /**< Bit mask for BURTC_MODE */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | #define _BURTC_CTRL_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 76 | #define _BURTC_CTRL_MODE_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | #define _BURTC_CTRL_MODE_EM2EN 0x00000001UL /**< Mode EM2EN for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | #define _BURTC_CTRL_MODE_EM3EN 0x00000002UL /**< Mode EM3EN for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | #define _BURTC_CTRL_MODE_EM4EN 0x00000003UL /**< Mode EM4EN for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | #define BURTC_CTRL_MODE_DEFAULT (_BURTC_CTRL_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | #define BURTC_CTRL_MODE_DISABLE (_BURTC_CTRL_MODE_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | #define BURTC_CTRL_MODE_EM2EN (_BURTC_CTRL_MODE_EM2EN << 0) /**< Shifted mode EM2EN for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | #define BURTC_CTRL_MODE_EM3EN (_BURTC_CTRL_MODE_EM3EN << 0) /**< Shifted mode EM3EN for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | #define BURTC_CTRL_MODE_EM4EN (_BURTC_CTRL_MODE_EM4EN << 0) /**< Shifted mode EM4EN for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | #define BURTC_CTRL_DEBUGRUN (0x1UL << 2) /**< Debug Mode Run Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | #define _BURTC_CTRL_DEBUGRUN_SHIFT 2 /**< Shift value for BURTC_DEBUGRUN */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | #define _BURTC_CTRL_DEBUGRUN_MASK 0x4UL /**< Bit mask for BURTC_DEBUGRUN */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | #define _BURTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | #define BURTC_CTRL_DEBUGRUN_DEFAULT (_BURTC_CTRL_DEBUGRUN_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | #define BURTC_CTRL_RSTEN (0x1UL << 3) /**< Enable BURTC reset */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | #define _BURTC_CTRL_RSTEN_SHIFT 3 /**< Shift value for BURTC_RSTEN */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | #define _BURTC_CTRL_RSTEN_MASK 0x8UL /**< Bit mask for BURTC_RSTEN */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define _BURTC_CTRL_RSTEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define BURTC_CTRL_RSTEN_DEFAULT (_BURTC_CTRL_RSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define BURTC_CTRL_COMP0TOP (0x1UL << 4) /**< Compare clear enable */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define _BURTC_CTRL_COMP0TOP_SHIFT 4 /**< Shift value for BURTC_COMP0TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | #define _BURTC_CTRL_COMP0TOP_MASK 0x10UL /**< Bit mask for BURTC_COMP0TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define _BURTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | #define BURTC_CTRL_COMP0TOP_DEFAULT (_BURTC_CTRL_COMP0TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define _BURTC_CTRL_LPCOMP_SHIFT 5 /**< Shift value for BURTC_LPCOMP */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | #define _BURTC_CTRL_LPCOMP_MASK 0xE0UL /**< Bit mask for BURTC_LPCOMP */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | #define _BURTC_CTRL_LPCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define _BURTC_CTRL_LPCOMP_IGN0LSB 0x00000000UL /**< Mode IGN0LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define _BURTC_CTRL_LPCOMP_IGN1LSB 0x00000001UL /**< Mode IGN1LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define _BURTC_CTRL_LPCOMP_IGN2LSB 0x00000002UL /**< Mode IGN2LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define _BURTC_CTRL_LPCOMP_IGN3LSB 0x00000003UL /**< Mode IGN3LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define _BURTC_CTRL_LPCOMP_IGN4LSB 0x00000004UL /**< Mode IGN4LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define _BURTC_CTRL_LPCOMP_IGN5LSB 0x00000005UL /**< Mode IGN5LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 109 | #define _BURTC_CTRL_LPCOMP_IGN6LSB 0x00000006UL /**< Mode IGN6LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | #define _BURTC_CTRL_LPCOMP_IGN7LSB 0x00000007UL /**< Mode IGN7LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | #define BURTC_CTRL_LPCOMP_DEFAULT (_BURTC_CTRL_LPCOMP_DEFAULT << 5) /**< Shifted mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | #define BURTC_CTRL_LPCOMP_IGN0LSB (_BURTC_CTRL_LPCOMP_IGN0LSB << 5) /**< Shifted mode IGN0LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define BURTC_CTRL_LPCOMP_IGN1LSB (_BURTC_CTRL_LPCOMP_IGN1LSB << 5) /**< Shifted mode IGN1LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define BURTC_CTRL_LPCOMP_IGN2LSB (_BURTC_CTRL_LPCOMP_IGN2LSB << 5) /**< Shifted mode IGN2LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define BURTC_CTRL_LPCOMP_IGN3LSB (_BURTC_CTRL_LPCOMP_IGN3LSB << 5) /**< Shifted mode IGN3LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define BURTC_CTRL_LPCOMP_IGN4LSB (_BURTC_CTRL_LPCOMP_IGN4LSB << 5) /**< Shifted mode IGN4LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define BURTC_CTRL_LPCOMP_IGN5LSB (_BURTC_CTRL_LPCOMP_IGN5LSB << 5) /**< Shifted mode IGN5LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define BURTC_CTRL_LPCOMP_IGN6LSB (_BURTC_CTRL_LPCOMP_IGN6LSB << 5) /**< Shifted mode IGN6LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define BURTC_CTRL_LPCOMP_IGN7LSB (_BURTC_CTRL_LPCOMP_IGN7LSB << 5) /**< Shifted mode IGN7LSB for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define _BURTC_CTRL_PRESC_SHIFT 8 /**< Shift value for BURTC_PRESC */ |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define _BURTC_CTRL_PRESC_MASK 0x700UL /**< Bit mask for BURTC_PRESC */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define _BURTC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | #define _BURTC_CTRL_PRESC_DIV1 0x00000000UL /**< Mode DIV1 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | #define _BURTC_CTRL_PRESC_DIV2 0x00000001UL /**< Mode DIV2 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 125 | #define _BURTC_CTRL_PRESC_DIV4 0x00000002UL /**< Mode DIV4 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 126 | #define _BURTC_CTRL_PRESC_DIV8 0x00000003UL /**< Mode DIV8 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define _BURTC_CTRL_PRESC_DIV16 0x00000004UL /**< Mode DIV16 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define _BURTC_CTRL_PRESC_DIV32 0x00000005UL /**< Mode DIV32 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define _BURTC_CTRL_PRESC_DIV64 0x00000006UL /**< Mode DIV64 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define _BURTC_CTRL_PRESC_DIV128 0x00000007UL /**< Mode DIV128 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define BURTC_CTRL_PRESC_DEFAULT (_BURTC_CTRL_PRESC_DEFAULT << 8) /**< Shifted mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define BURTC_CTRL_PRESC_DIV1 (_BURTC_CTRL_PRESC_DIV1 << 8) /**< Shifted mode DIV1 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define BURTC_CTRL_PRESC_DIV2 (_BURTC_CTRL_PRESC_DIV2 << 8) /**< Shifted mode DIV2 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define BURTC_CTRL_PRESC_DIV4 (_BURTC_CTRL_PRESC_DIV4 << 8) /**< Shifted mode DIV4 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define BURTC_CTRL_PRESC_DIV8 (_BURTC_CTRL_PRESC_DIV8 << 8) /**< Shifted mode DIV8 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define BURTC_CTRL_PRESC_DIV16 (_BURTC_CTRL_PRESC_DIV16 << 8) /**< Shifted mode DIV16 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define BURTC_CTRL_PRESC_DIV32 (_BURTC_CTRL_PRESC_DIV32 << 8) /**< Shifted mode DIV32 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define BURTC_CTRL_PRESC_DIV64 (_BURTC_CTRL_PRESC_DIV64 << 8) /**< Shifted mode DIV64 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | #define BURTC_CTRL_PRESC_DIV128 (_BURTC_CTRL_PRESC_DIV128 << 8) /**< Shifted mode DIV128 for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define _BURTC_CTRL_CLKSEL_SHIFT 12 /**< Shift value for BURTC_CLKSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define _BURTC_CTRL_CLKSEL_MASK 0x3000UL /**< Bit mask for BURTC_CLKSEL */ |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define _BURTC_CTRL_CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define _BURTC_CTRL_CLKSEL_NONE 0x00000000UL /**< Mode NONE for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define _BURTC_CTRL_CLKSEL_LFRCO 0x00000001UL /**< Mode LFRCO for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define _BURTC_CTRL_CLKSEL_LFXO 0x00000002UL /**< Mode LFXO for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define _BURTC_CTRL_CLKSEL_ULFRCO 0x00000003UL /**< Mode ULFRCO for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define BURTC_CTRL_CLKSEL_DEFAULT (_BURTC_CTRL_CLKSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define BURTC_CTRL_CLKSEL_NONE (_BURTC_CTRL_CLKSEL_NONE << 12) /**< Shifted mode NONE for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | #define BURTC_CTRL_CLKSEL_LFRCO (_BURTC_CTRL_CLKSEL_LFRCO << 12) /**< Shifted mode LFRCO for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | #define BURTC_CTRL_CLKSEL_LFXO (_BURTC_CTRL_CLKSEL_LFXO << 12) /**< Shifted mode LFXO for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define BURTC_CTRL_CLKSEL_ULFRCO (_BURTC_CTRL_CLKSEL_ULFRCO << 12) /**< Shifted mode ULFRCO for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define BURTC_CTRL_BUMODETSEN (0x1UL << 14) /**< Backup mode timestamp enable */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define _BURTC_CTRL_BUMODETSEN_SHIFT 14 /**< Shift value for BURTC_BUMODETSEN */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define _BURTC_CTRL_BUMODETSEN_MASK 0x4000UL /**< Bit mask for BURTC_BUMODETSEN */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define _BURTC_CTRL_BUMODETSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define BURTC_CTRL_BUMODETSEN_DEFAULT (_BURTC_CTRL_BUMODETSEN_DEFAULT << 14) /**< Shifted mode DEFAULT for BURTC_CTRL */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | |
| AnnaBridge | 171:3a7713b1edbc | 158 | /* Bit fields for BURTC LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define _BURTC_LPMODE_RESETVALUE 0x00000000UL /**< Default value for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 160 | #define _BURTC_LPMODE_MASK 0x00000003UL /**< Mask for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define _BURTC_LPMODE_LPMODE_SHIFT 0 /**< Shift value for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define _BURTC_LPMODE_LPMODE_MASK 0x3UL /**< Bit mask for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define _BURTC_LPMODE_LPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define _BURTC_LPMODE_LPMODE_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define _BURTC_LPMODE_LPMODE_ENABLE 0x00000001UL /**< Mode ENABLE for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define _BURTC_LPMODE_LPMODE_BUEN 0x00000002UL /**< Mode BUEN for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define BURTC_LPMODE_LPMODE_DEFAULT (_BURTC_LPMODE_LPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define BURTC_LPMODE_LPMODE_DISABLE (_BURTC_LPMODE_LPMODE_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define BURTC_LPMODE_LPMODE_ENABLE (_BURTC_LPMODE_LPMODE_ENABLE << 0) /**< Shifted mode ENABLE for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define BURTC_LPMODE_LPMODE_BUEN (_BURTC_LPMODE_LPMODE_BUEN << 0) /**< Shifted mode BUEN for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | |
| AnnaBridge | 171:3a7713b1edbc | 172 | /* Bit fields for BURTC CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define _BURTC_CNT_RESETVALUE 0x00000000UL /**< Default value for BURTC_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define _BURTC_CNT_MASK 0xFFFFFFFFUL /**< Mask for BURTC_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define _BURTC_CNT_CNT_SHIFT 0 /**< Shift value for BURTC_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define _BURTC_CNT_CNT_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define _BURTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define BURTC_CNT_CNT_DEFAULT (_BURTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CNT */ |
| AnnaBridge | 171:3a7713b1edbc | 179 | |
| AnnaBridge | 171:3a7713b1edbc | 180 | /* Bit fields for BURTC COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | #define _BURTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define _BURTC_COMP0_MASK 0xFFFFFFFFUL /**< Mask for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define _BURTC_COMP0_COMP0_SHIFT 0 /**< Shift value for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define _BURTC_COMP0_COMP0_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define _BURTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define BURTC_COMP0_COMP0_DEFAULT (_BURTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 187 | |
| AnnaBridge | 171:3a7713b1edbc | 188 | /* Bit fields for BURTC TIMESTAMP */ |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define _BURTC_TIMESTAMP_RESETVALUE 0x00000000UL /**< Default value for BURTC_TIMESTAMP */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define _BURTC_TIMESTAMP_MASK 0xFFFFFFFFUL /**< Mask for BURTC_TIMESTAMP */ |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define _BURTC_TIMESTAMP_TIMESTAMP_SHIFT 0 /**< Shift value for BURTC_TIMESTAMP */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define _BURTC_TIMESTAMP_TIMESTAMP_MASK 0xFFFFFFFFUL /**< Bit mask for BURTC_TIMESTAMP */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define _BURTC_TIMESTAMP_TIMESTAMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_TIMESTAMP */ |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define BURTC_TIMESTAMP_TIMESTAMP_DEFAULT (_BURTC_TIMESTAMP_TIMESTAMP_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_TIMESTAMP */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | |
| AnnaBridge | 171:3a7713b1edbc | 196 | /* Bit fields for BURTC LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define _BURTC_LFXOFDET_RESETVALUE 0x00000000UL /**< Default value for BURTC_LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | #define _BURTC_LFXOFDET_MASK 0x000001F3UL /**< Mask for BURTC_LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | #define _BURTC_LFXOFDET_OSC_SHIFT 0 /**< Shift value for BURTC_OSC */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define _BURTC_LFXOFDET_OSC_MASK 0x3UL /**< Bit mask for BURTC_OSC */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | #define _BURTC_LFXOFDET_OSC_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define _BURTC_LFXOFDET_OSC_DISABLE 0x00000000UL /**< Mode DISABLE for BURTC_LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define _BURTC_LFXOFDET_OSC_LFRCO 0x00000001UL /**< Mode LFRCO for BURTC_LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define _BURTC_LFXOFDET_OSC_ULFRCO 0x00000002UL /**< Mode ULFRCO for BURTC_LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define BURTC_LFXOFDET_OSC_DEFAULT (_BURTC_LFXOFDET_OSC_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define BURTC_LFXOFDET_OSC_DISABLE (_BURTC_LFXOFDET_OSC_DISABLE << 0) /**< Shifted mode DISABLE for BURTC_LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define BURTC_LFXOFDET_OSC_LFRCO (_BURTC_LFXOFDET_OSC_LFRCO << 0) /**< Shifted mode LFRCO for BURTC_LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define BURTC_LFXOFDET_OSC_ULFRCO (_BURTC_LFXOFDET_OSC_ULFRCO << 0) /**< Shifted mode ULFRCO for BURTC_LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | #define _BURTC_LFXOFDET_TOP_SHIFT 4 /**< Shift value for BURTC_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define _BURTC_LFXOFDET_TOP_MASK 0x1F0UL /**< Bit mask for BURTC_TOP */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define _BURTC_LFXOFDET_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define BURTC_LFXOFDET_TOP_DEFAULT (_BURTC_LFXOFDET_TOP_DEFAULT << 4) /**< Shifted mode DEFAULT for BURTC_LFXOFDET */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | |
| AnnaBridge | 171:3a7713b1edbc | 214 | /* Bit fields for BURTC STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define _BURTC_STATUS_RESETVALUE 0x00000000UL /**< Default value for BURTC_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define _BURTC_STATUS_MASK 0x00000007UL /**< Mask for BURTC_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define BURTC_STATUS_LPMODEACT (0x1UL << 0) /**< Low power mode active */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define _BURTC_STATUS_LPMODEACT_SHIFT 0 /**< Shift value for BURTC_LPMODEACT */ |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define _BURTC_STATUS_LPMODEACT_MASK 0x1UL /**< Bit mask for BURTC_LPMODEACT */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define _BURTC_STATUS_LPMODEACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define BURTC_STATUS_LPMODEACT_DEFAULT (_BURTC_STATUS_LPMODEACT_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define BURTC_STATUS_BUMODETS (0x1UL << 1) /**< Timestamp for backup mode entry stored. */ |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define _BURTC_STATUS_BUMODETS_SHIFT 1 /**< Shift value for BURTC_BUMODETS */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define _BURTC_STATUS_BUMODETS_MASK 0x2UL /**< Bit mask for BURTC_BUMODETS */ |
| AnnaBridge | 171:3a7713b1edbc | 225 | #define _BURTC_STATUS_BUMODETS_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define BURTC_STATUS_BUMODETS_DEFAULT (_BURTC_STATUS_BUMODETS_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 227 | #define BURTC_STATUS_RAMWERR (0x1UL << 2) /**< RAM write error. */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define _BURTC_STATUS_RAMWERR_SHIFT 2 /**< Shift value for BURTC_RAMWERR */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define _BURTC_STATUS_RAMWERR_MASK 0x4UL /**< Bit mask for BURTC_RAMWERR */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define _BURTC_STATUS_RAMWERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define BURTC_STATUS_RAMWERR_DEFAULT (_BURTC_STATUS_RAMWERR_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_STATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | |
| AnnaBridge | 171:3a7713b1edbc | 233 | /* Bit fields for BURTC CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define _BURTC_CMD_RESETVALUE 0x00000000UL /**< Default value for BURTC_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define _BURTC_CMD_MASK 0x00000001UL /**< Mask for BURTC_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define BURTC_CMD_CLRSTATUS (0x1UL << 0) /**< Clear BURTC_STATUS register. */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define _BURTC_CMD_CLRSTATUS_SHIFT 0 /**< Shift value for BURTC_CLRSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define _BURTC_CMD_CLRSTATUS_MASK 0x1UL /**< Bit mask for BURTC_CLRSTATUS */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define _BURTC_CMD_CLRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define BURTC_CMD_CLRSTATUS_DEFAULT (_BURTC_CMD_CLRSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_CMD */ |
| AnnaBridge | 171:3a7713b1edbc | 241 | |
| AnnaBridge | 171:3a7713b1edbc | 242 | /* Bit fields for BURTC POWERDOWN */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define _BURTC_POWERDOWN_RESETVALUE 0x00000000UL /**< Default value for BURTC_POWERDOWN */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define _BURTC_POWERDOWN_MASK 0x00000001UL /**< Mask for BURTC_POWERDOWN */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define BURTC_POWERDOWN_RAM (0x1UL << 0) /**< Retention RAM power-down */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define _BURTC_POWERDOWN_RAM_SHIFT 0 /**< Shift value for BURTC_RAM */ |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define _BURTC_POWERDOWN_RAM_MASK 0x1UL /**< Bit mask for BURTC_RAM */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define _BURTC_POWERDOWN_RAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_POWERDOWN */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define BURTC_POWERDOWN_RAM_DEFAULT (_BURTC_POWERDOWN_RAM_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_POWERDOWN */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | |
| AnnaBridge | 171:3a7713b1edbc | 251 | /* Bit fields for BURTC LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define _BURTC_LOCK_RESETVALUE 0x00000000UL /**< Default value for BURTC_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define _BURTC_LOCK_MASK 0x0000FFFFUL /**< Mask for BURTC_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define _BURTC_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for BURTC_LOCKKEY */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define _BURTC_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for BURTC_LOCKKEY */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define _BURTC_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define _BURTC_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for BURTC_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define _BURTC_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for BURTC_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define _BURTC_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for BURTC_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define _BURTC_LOCK_LOCKKEY_UNLOCK 0x0000AEE8UL /**< Mode UNLOCK for BURTC_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define BURTC_LOCK_LOCKKEY_DEFAULT (_BURTC_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | #define BURTC_LOCK_LOCKKEY_LOCK (_BURTC_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for BURTC_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | #define BURTC_LOCK_LOCKKEY_UNLOCKED (_BURTC_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for BURTC_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | #define BURTC_LOCK_LOCKKEY_LOCKED (_BURTC_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for BURTC_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 265 | #define BURTC_LOCK_LOCKKEY_UNLOCK (_BURTC_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for BURTC_LOCK */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | |
| AnnaBridge | 171:3a7713b1edbc | 267 | /* Bit fields for BURTC IF */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define _BURTC_IF_RESETVALUE 0x00000000UL /**< Default value for BURTC_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define _BURTC_IF_MASK 0x00000007UL /**< Mask for BURTC_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define BURTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define _BURTC_IF_OF_SHIFT 0 /**< Shift value for BURTC_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define _BURTC_IF_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define _BURTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | #define BURTC_IF_OF_DEFAULT (_BURTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define BURTC_IF_COMP0 (0x1UL << 1) /**< Compare match Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define _BURTC_IF_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 277 | #define _BURTC_IF_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define _BURTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define BURTC_IF_COMP0_DEFAULT (_BURTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define BURTC_IF_LFXOFAIL (0x1UL << 2) /**< LFXO failure Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define _BURTC_IF_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define _BURTC_IF_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define _BURTC_IF_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define BURTC_IF_LFXOFAIL_DEFAULT (_BURTC_IF_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IF */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | |
| AnnaBridge | 171:3a7713b1edbc | 286 | /* Bit fields for BURTC IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define _BURTC_IFS_RESETVALUE 0x00000000UL /**< Default value for BURTC_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define _BURTC_IFS_MASK 0x00000007UL /**< Mask for BURTC_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define BURTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define _BURTC_IFS_OF_SHIFT 0 /**< Shift value for BURTC_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define _BURTC_IFS_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define _BURTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define BURTC_IFS_OF_DEFAULT (_BURTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define BURTC_IFS_COMP0 (0x1UL << 1) /**< Set compare match Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define _BURTC_IFS_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define _BURTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define _BURTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define BURTC_IFS_COMP0_DEFAULT (_BURTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define BURTC_IFS_LFXOFAIL (0x1UL << 2) /**< Set LFXO fail Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define _BURTC_IFS_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | #define _BURTC_IFS_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define _BURTC_IFS_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define BURTC_IFS_LFXOFAIL_DEFAULT (_BURTC_IFS_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IFS */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | |
| AnnaBridge | 171:3a7713b1edbc | 305 | /* Bit fields for BURTC IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define _BURTC_IFC_RESETVALUE 0x00000000UL /**< Default value for BURTC_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define _BURTC_IFC_MASK 0x00000007UL /**< Mask for BURTC_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define BURTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define _BURTC_IFC_OF_SHIFT 0 /**< Shift value for BURTC_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define _BURTC_IFC_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define _BURTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define BURTC_IFC_OF_DEFAULT (_BURTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define BURTC_IFC_COMP0 (0x1UL << 1) /**< Clear compare match Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define _BURTC_IFC_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define _BURTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | #define _BURTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 317 | #define BURTC_IFC_COMP0_DEFAULT (_BURTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 318 | #define BURTC_IFC_LFXOFAIL (0x1UL << 2) /**< Clear LFXO failure Interrupt Flag */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define _BURTC_IFC_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */ |
| AnnaBridge | 171:3a7713b1edbc | 320 | #define _BURTC_IFC_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define _BURTC_IFC_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 322 | #define BURTC_IFC_LFXOFAIL_DEFAULT (_BURTC_IFC_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IFC */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | |
| AnnaBridge | 171:3a7713b1edbc | 324 | /* Bit fields for BURTC IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define _BURTC_IEN_RESETVALUE 0x00000000UL /**< Default value for BURTC_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define _BURTC_IEN_MASK 0x00000007UL /**< Mask for BURTC_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define BURTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define _BURTC_IEN_OF_SHIFT 0 /**< Shift value for BURTC_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define _BURTC_IEN_OF_MASK 0x1UL /**< Bit mask for BURTC_OF */ |
| AnnaBridge | 171:3a7713b1edbc | 330 | #define _BURTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 331 | #define BURTC_IEN_OF_DEFAULT (_BURTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define BURTC_IEN_COMP0 (0x1UL << 1) /**< Compare match Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define _BURTC_IEN_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define _BURTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define _BURTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define BURTC_IEN_COMP0_DEFAULT (_BURTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | #define BURTC_IEN_LFXOFAIL (0x1UL << 2) /**< LFXO failure Interrupt Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 338 | #define _BURTC_IEN_LFXOFAIL_SHIFT 2 /**< Shift value for BURTC_LFXOFAIL */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define _BURTC_IEN_LFXOFAIL_MASK 0x4UL /**< Bit mask for BURTC_LFXOFAIL */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | #define _BURTC_IEN_LFXOFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 341 | #define BURTC_IEN_LFXOFAIL_DEFAULT (_BURTC_IEN_LFXOFAIL_DEFAULT << 2) /**< Shifted mode DEFAULT for BURTC_IEN */ |
| AnnaBridge | 171:3a7713b1edbc | 342 | |
| AnnaBridge | 171:3a7713b1edbc | 343 | /* Bit fields for BURTC FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define _BURTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for BURTC_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define _BURTC_FREEZE_MASK 0x00000001UL /**< Mask for BURTC_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 346 | #define BURTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define _BURTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for BURTC_REGFREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define _BURTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for BURTC_REGFREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define _BURTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define _BURTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for BURTC_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define _BURTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for BURTC_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define BURTC_FREEZE_REGFREEZE_DEFAULT (_BURTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define BURTC_FREEZE_REGFREEZE_UPDATE (_BURTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for BURTC_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define BURTC_FREEZE_REGFREEZE_FREEZE (_BURTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for BURTC_FREEZE */ |
| AnnaBridge | 171:3a7713b1edbc | 355 | |
| AnnaBridge | 171:3a7713b1edbc | 356 | /* Bit fields for BURTC SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define _BURTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for BURTC_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define _BURTC_SYNCBUSY_MASK 0x00000003UL /**< Mask for BURTC_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define BURTC_SYNCBUSY_LPMODE (0x1UL << 0) /**< LPMODE Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define _BURTC_SYNCBUSY_LPMODE_SHIFT 0 /**< Shift value for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define _BURTC_SYNCBUSY_LPMODE_MASK 0x1UL /**< Bit mask for BURTC_LPMODE */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define _BURTC_SYNCBUSY_LPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define BURTC_SYNCBUSY_LPMODE_DEFAULT (_BURTC_SYNCBUSY_LPMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | #define BURTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< COMP0 Register Busy */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define _BURTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define _BURTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for BURTC_COMP0 */ |
| AnnaBridge | 171:3a7713b1edbc | 367 | #define _BURTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define BURTC_SYNCBUSY_COMP0_DEFAULT (_BURTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for BURTC_SYNCBUSY */ |
| AnnaBridge | 171:3a7713b1edbc | 369 | |
| AnnaBridge | 171:3a7713b1edbc | 370 | /* Bit fields for BURTC RET_REG */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define _BURTC_RET_REG_RESETVALUE 0x00000000UL /**< Default value for BURTC_RET_REG */ |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define _BURTC_RET_REG_MASK 0xFFFFFFFFUL /**< Mask for BURTC_RET_REG */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | #define _BURTC_RET_REG_REG_SHIFT 0 /**< Shift value for REG */ |
| AnnaBridge | 171:3a7713b1edbc | 374 | #define _BURTC_RET_REG_REG_MASK 0xFFFFFFFFUL /**< Bit mask for REG */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define _BURTC_RET_REG_REG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BURTC_RET_REG */ |
| AnnaBridge | 171:3a7713b1edbc | 376 | #define BURTC_RET_REG_REG_DEFAULT (_BURTC_RET_REG_REG_DEFAULT << 0) /**< Shifted mode DEFAULT for BURTC_RET_REG */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | |
| AnnaBridge | 171:3a7713b1edbc | 378 | /** @} End of group EFM32LG_BURTC */ |
| AnnaBridge | 171:3a7713b1edbc | 379 | /** @} End of group Parts */ |
| AnnaBridge | 171:3a7713b1edbc | 380 |
