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TARGET_EFM32LG_STK3600/TOOLCHAIN_ARM_STD/efm32lg_usb.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32lg_usb.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32LG_USB register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32LG_USB
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32LG_USB Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IOM uint32_t CTRL; /**< System Control Register */
AnnaBridge 171:3a7713b1edbc 44 __IM uint32_t STATUS; /**< System Status Register */
AnnaBridge 171:3a7713b1edbc 45 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 46 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 171:3a7713b1edbc 47 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 171:3a7713b1edbc 48 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 49 __IOM uint32_t ROUTE; /**< I/O Routing Register */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 uint32_t RESERVED0[61433]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 52 __IOM uint32_t GOTGCTL; /**< OTG Control and Status Register */
AnnaBridge 171:3a7713b1edbc 53 __IOM uint32_t GOTGINT; /**< OTG Interrupt Register */
AnnaBridge 171:3a7713b1edbc 54 __IOM uint32_t GAHBCFG; /**< AHB Configuration Register */
AnnaBridge 171:3a7713b1edbc 55 __IOM uint32_t GUSBCFG; /**< USB Configuration Register */
AnnaBridge 171:3a7713b1edbc 56 __IOM uint32_t GRSTCTL; /**< Reset Register */
AnnaBridge 171:3a7713b1edbc 57 __IOM uint32_t GINTSTS; /**< Interrupt Register */
AnnaBridge 171:3a7713b1edbc 58 __IOM uint32_t GINTMSK; /**< Interrupt Mask Register */
AnnaBridge 171:3a7713b1edbc 59 __IM uint32_t GRXSTSR; /**< Receive Status Debug Read Register */
AnnaBridge 171:3a7713b1edbc 60 __IM uint32_t GRXSTSP; /**< Receive Status Read and Pop Register */
AnnaBridge 171:3a7713b1edbc 61 __IOM uint32_t GRXFSIZ; /**< Receive FIFO Size Register */
AnnaBridge 171:3a7713b1edbc 62 __IOM uint32_t GNPTXFSIZ; /**< Non-periodic Transmit FIFO Size Register */
AnnaBridge 171:3a7713b1edbc 63 __IM uint32_t GNPTXSTS; /**< Non-periodic Transmit FIFO/Queue Status Register */
AnnaBridge 171:3a7713b1edbc 64 uint32_t RESERVED1[11]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 65 __IOM uint32_t GDFIFOCFG; /**< Global DFIFO Configuration Register */
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 uint32_t RESERVED2[40]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 68 __IOM uint32_t HPTXFSIZ; /**< Host Periodic Transmit FIFO Size Register */
AnnaBridge 171:3a7713b1edbc 69 __IOM uint32_t DIEPTXF1; /**< Device IN Endpoint Transmit FIFO 1 Size Register */
AnnaBridge 171:3a7713b1edbc 70 __IOM uint32_t DIEPTXF2; /**< Device IN Endpoint Transmit FIFO 2 Size Register */
AnnaBridge 171:3a7713b1edbc 71 __IOM uint32_t DIEPTXF3; /**< Device IN Endpoint Transmit FIFO 3 Size Register */
AnnaBridge 171:3a7713b1edbc 72 __IOM uint32_t DIEPTXF4; /**< Device IN Endpoint Transmit FIFO 4 Size Register */
AnnaBridge 171:3a7713b1edbc 73 __IOM uint32_t DIEPTXF5; /**< Device IN Endpoint Transmit FIFO 5 Size Register */
AnnaBridge 171:3a7713b1edbc 74 __IOM uint32_t DIEPTXF6; /**< Device IN Endpoint Transmit FIFO 6 Size Register */
AnnaBridge 171:3a7713b1edbc 75
AnnaBridge 171:3a7713b1edbc 76 uint32_t RESERVED3[185]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 77 __IOM uint32_t HCFG; /**< Host Configuration Register */
AnnaBridge 171:3a7713b1edbc 78 __IOM uint32_t HFIR; /**< Host Frame Interval Register */
AnnaBridge 171:3a7713b1edbc 79 __IM uint32_t HFNUM; /**< Host Frame Number/Frame Time Remaining Register */
AnnaBridge 171:3a7713b1edbc 80 uint32_t RESERVED4[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 81 __IM uint32_t HPTXSTS; /**< Host Periodic Transmit FIFO/Queue Status Register */
AnnaBridge 171:3a7713b1edbc 82 __IM uint32_t HAINT; /**< Host All Channels Interrupt Register */
AnnaBridge 171:3a7713b1edbc 83 __IOM uint32_t HAINTMSK; /**< Host All Channels Interrupt Mask Register */
AnnaBridge 171:3a7713b1edbc 84 uint32_t RESERVED5[9]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 85 __IOM uint32_t HPRT; /**< Host Port Control and Status Register */
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 uint32_t RESERVED6[47]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 88 USB_HC_TypeDef HC[14]; /**< Host Channel Registers */
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 uint32_t RESERVED7[80]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 91 __IOM uint32_t DCFG; /**< Device Configuration Register */
AnnaBridge 171:3a7713b1edbc 92 __IOM uint32_t DCTL; /**< Device Control Register */
AnnaBridge 171:3a7713b1edbc 93 __IM uint32_t DSTS; /**< Device Status Register */
AnnaBridge 171:3a7713b1edbc 94 uint32_t RESERVED8[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 95 __IOM uint32_t DIEPMSK; /**< Device IN Endpoint Common Interrupt Mask Register */
AnnaBridge 171:3a7713b1edbc 96 __IOM uint32_t DOEPMSK; /**< Device OUT Endpoint Common Interrupt Mask Register */
AnnaBridge 171:3a7713b1edbc 97 __IM uint32_t DAINT; /**< Device All Endpoints Interrupt Register */
AnnaBridge 171:3a7713b1edbc 98 __IOM uint32_t DAINTMSK; /**< Device All Endpoints Interrupt Mask Register */
AnnaBridge 171:3a7713b1edbc 99 uint32_t RESERVED9[2]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 100 __IOM uint32_t DVBUSDIS; /**< Device VBUS Discharge Time Register */
AnnaBridge 171:3a7713b1edbc 101 __IOM uint32_t DVBUSPULSE; /**< Device VBUS Pulsing Time Register */
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 uint32_t RESERVED10[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 104 __IOM uint32_t DIEPEMPMSK; /**< Device IN Endpoint FIFO Empty Interrupt Mask Register */
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 uint32_t RESERVED11[50]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 107 __IOM uint32_t DIEP0CTL; /**< Device IN Endpoint 0 Control Register */
AnnaBridge 171:3a7713b1edbc 108 uint32_t RESERVED12[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 109 __IOM uint32_t DIEP0INT; /**< Device IN Endpoint 0 Interrupt Register */
AnnaBridge 171:3a7713b1edbc 110 uint32_t RESERVED13[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 111 __IOM uint32_t DIEP0TSIZ; /**< Device IN Endpoint 0 Transfer Size Register */
AnnaBridge 171:3a7713b1edbc 112 __IOM uint32_t DIEP0DMAADDR; /**< Device IN Endpoint 0 DMA Address Register */
AnnaBridge 171:3a7713b1edbc 113 __IM uint32_t DIEP0TXFSTS; /**< Device IN Endpoint 0 Transmit FIFO Status Register */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 uint32_t RESERVED14[1]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 116 USB_DIEP_TypeDef DIEP[6]; /**< Device IN Endpoint x+1 Registers */
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 uint32_t RESERVED15[72]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 119 __IOM uint32_t DOEP0CTL; /**< Device OUT Endpoint 0 Control Register */
AnnaBridge 171:3a7713b1edbc 120 uint32_t RESERVED16[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 121 __IOM uint32_t DOEP0INT; /**< Device OUT Endpoint 0 Interrupt Register */
AnnaBridge 171:3a7713b1edbc 122 uint32_t RESERVED17[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 123 __IOM uint32_t DOEP0TSIZ; /**< Device OUT Endpoint 0 Transfer Size Register */
AnnaBridge 171:3a7713b1edbc 124 __IOM uint32_t DOEP0DMAADDR; /**< Device OUT Endpoint 0 DMA Address Register */
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 uint32_t RESERVED18[2]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 127 USB_DOEP_TypeDef DOEP[6]; /**< Device OUT Endpoint x+1 Registers */
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129 uint32_t RESERVED19[136]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 130 __IOM uint32_t PCGCCTL; /**< Power and Clock Gating Control Register */
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 uint32_t RESERVED20[127]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 133 __IOM uint32_t FIFO0D[512]; /**< Device EP 0/Host Channel 0 FIFO */
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 uint32_t RESERVED21[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 136 __IOM uint32_t FIFO1D[512]; /**< Device EP 1/Host Channel 1 FIFO */
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138 uint32_t RESERVED22[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 139 __IOM uint32_t FIFO2D[512]; /**< Device EP 2/Host Channel 2 FIFO */
AnnaBridge 171:3a7713b1edbc 140
AnnaBridge 171:3a7713b1edbc 141 uint32_t RESERVED23[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 142 __IOM uint32_t FIFO3D[512]; /**< Device EP 3/Host Channel 3 FIFO */
AnnaBridge 171:3a7713b1edbc 143
AnnaBridge 171:3a7713b1edbc 144 uint32_t RESERVED24[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 145 __IOM uint32_t FIFO4D[512]; /**< Device EP 4/Host Channel 4 FIFO */
AnnaBridge 171:3a7713b1edbc 146
AnnaBridge 171:3a7713b1edbc 147 uint32_t RESERVED25[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 148 __IOM uint32_t FIFO5D[512]; /**< Device EP 5/Host Channel 5 FIFO */
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 uint32_t RESERVED26[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 151 __IOM uint32_t FIFO6D[512]; /**< Device EP 6/Host Channel 6 FIFO */
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 uint32_t RESERVED27[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 154 __IOM uint32_t FIFO7D[512]; /**< Host Channel 7 FIFO */
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 uint32_t RESERVED28[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 157 __IOM uint32_t FIFO8D[512]; /**< Host Channel 8 FIFO */
AnnaBridge 171:3a7713b1edbc 158
AnnaBridge 171:3a7713b1edbc 159 uint32_t RESERVED29[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 160 __IOM uint32_t FIFO9D[512]; /**< Host Channel 9 FIFO */
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 uint32_t RESERVED30[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 163 __IOM uint32_t FIFO10D[512]; /**< Host Channel 10 FIFO */
AnnaBridge 171:3a7713b1edbc 164
AnnaBridge 171:3a7713b1edbc 165 uint32_t RESERVED31[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 166 __IOM uint32_t FIFO11D[512]; /**< Host Channel 11 FIFO */
AnnaBridge 171:3a7713b1edbc 167
AnnaBridge 171:3a7713b1edbc 168 uint32_t RESERVED32[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 169 __IOM uint32_t FIFO12D[512]; /**< Host Channel 12 FIFO */
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 uint32_t RESERVED33[512]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 172 __IOM uint32_t FIFO13D[512]; /**< Host Channel 13 FIFO */
AnnaBridge 171:3a7713b1edbc 173
AnnaBridge 171:3a7713b1edbc 174 uint32_t RESERVED34[17920]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 175 __IOM uint32_t FIFORAM[512]; /**< Direct Access to Data FIFO RAM for Debugging (2 KB) */
AnnaBridge 171:3a7713b1edbc 176 } USB_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 179 * @defgroup EFM32LG_USB_BitFields
AnnaBridge 171:3a7713b1edbc 180 * @{
AnnaBridge 171:3a7713b1edbc 181 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 182
AnnaBridge 171:3a7713b1edbc 183 /* Bit fields for USB CTRL */
AnnaBridge 171:3a7713b1edbc 184 #define _USB_CTRL_RESETVALUE 0x00000000UL /**< Default value for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 185 #define _USB_CTRL_MASK 0x03330003UL /**< Mask for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 186 #define USB_CTRL_VBUSENAP (0x1UL << 0) /**< VBUSEN Active Polarity */
AnnaBridge 171:3a7713b1edbc 187 #define _USB_CTRL_VBUSENAP_SHIFT 0 /**< Shift value for USB_VBUSENAP */
AnnaBridge 171:3a7713b1edbc 188 #define _USB_CTRL_VBUSENAP_MASK 0x1UL /**< Bit mask for USB_VBUSENAP */
AnnaBridge 171:3a7713b1edbc 189 #define _USB_CTRL_VBUSENAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 190 #define _USB_CTRL_VBUSENAP_LOW 0x00000000UL /**< Mode LOW for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 191 #define _USB_CTRL_VBUSENAP_HIGH 0x00000001UL /**< Mode HIGH for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 192 #define USB_CTRL_VBUSENAP_DEFAULT (_USB_CTRL_VBUSENAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 193 #define USB_CTRL_VBUSENAP_LOW (_USB_CTRL_VBUSENAP_LOW << 0) /**< Shifted mode LOW for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 194 #define USB_CTRL_VBUSENAP_HIGH (_USB_CTRL_VBUSENAP_HIGH << 0) /**< Shifted mode HIGH for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 195 #define USB_CTRL_DMPUAP (0x1UL << 1) /**< DMPU Active Polarity */
AnnaBridge 171:3a7713b1edbc 196 #define _USB_CTRL_DMPUAP_SHIFT 1 /**< Shift value for USB_DMPUAP */
AnnaBridge 171:3a7713b1edbc 197 #define _USB_CTRL_DMPUAP_MASK 0x2UL /**< Bit mask for USB_DMPUAP */
AnnaBridge 171:3a7713b1edbc 198 #define _USB_CTRL_DMPUAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 199 #define _USB_CTRL_DMPUAP_LOW 0x00000000UL /**< Mode LOW for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 200 #define _USB_CTRL_DMPUAP_HIGH 0x00000001UL /**< Mode HIGH for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 201 #define USB_CTRL_DMPUAP_DEFAULT (_USB_CTRL_DMPUAP_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 202 #define USB_CTRL_DMPUAP_LOW (_USB_CTRL_DMPUAP_LOW << 1) /**< Shifted mode LOW for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 203 #define USB_CTRL_DMPUAP_HIGH (_USB_CTRL_DMPUAP_HIGH << 1) /**< Shifted mode HIGH for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 204 #define USB_CTRL_VREGDIS (0x1UL << 16) /**< Voltage Regulator Disable */
AnnaBridge 171:3a7713b1edbc 205 #define _USB_CTRL_VREGDIS_SHIFT 16 /**< Shift value for USB_VREGDIS */
AnnaBridge 171:3a7713b1edbc 206 #define _USB_CTRL_VREGDIS_MASK 0x10000UL /**< Bit mask for USB_VREGDIS */
AnnaBridge 171:3a7713b1edbc 207 #define _USB_CTRL_VREGDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 208 #define USB_CTRL_VREGDIS_DEFAULT (_USB_CTRL_VREGDIS_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 209 #define USB_CTRL_VREGOSEN (0x1UL << 17) /**< VREGO Sense Enable */
AnnaBridge 171:3a7713b1edbc 210 #define _USB_CTRL_VREGOSEN_SHIFT 17 /**< Shift value for USB_VREGOSEN */
AnnaBridge 171:3a7713b1edbc 211 #define _USB_CTRL_VREGOSEN_MASK 0x20000UL /**< Bit mask for USB_VREGOSEN */
AnnaBridge 171:3a7713b1edbc 212 #define _USB_CTRL_VREGOSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 213 #define USB_CTRL_VREGOSEN_DEFAULT (_USB_CTRL_VREGOSEN_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 214 #define _USB_CTRL_BIASPROGEM01_SHIFT 20 /**< Shift value for USB_BIASPROGEM01 */
AnnaBridge 171:3a7713b1edbc 215 #define _USB_CTRL_BIASPROGEM01_MASK 0x300000UL /**< Bit mask for USB_BIASPROGEM01 */
AnnaBridge 171:3a7713b1edbc 216 #define _USB_CTRL_BIASPROGEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 217 #define USB_CTRL_BIASPROGEM01_DEFAULT (_USB_CTRL_BIASPROGEM01_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 218 #define _USB_CTRL_BIASPROGEM23_SHIFT 24 /**< Shift value for USB_BIASPROGEM23 */
AnnaBridge 171:3a7713b1edbc 219 #define _USB_CTRL_BIASPROGEM23_MASK 0x3000000UL /**< Bit mask for USB_BIASPROGEM23 */
AnnaBridge 171:3a7713b1edbc 220 #define _USB_CTRL_BIASPROGEM23_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 221 #define USB_CTRL_BIASPROGEM23_DEFAULT (_USB_CTRL_BIASPROGEM23_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_CTRL */
AnnaBridge 171:3a7713b1edbc 222
AnnaBridge 171:3a7713b1edbc 223 /* Bit fields for USB STATUS */
AnnaBridge 171:3a7713b1edbc 224 #define _USB_STATUS_RESETVALUE 0x00000000UL /**< Default value for USB_STATUS */
AnnaBridge 171:3a7713b1edbc 225 #define _USB_STATUS_MASK 0x00000001UL /**< Mask for USB_STATUS */
AnnaBridge 171:3a7713b1edbc 226 #define USB_STATUS_VREGOS (0x1UL << 0) /**< VREGO Sense Output */
AnnaBridge 171:3a7713b1edbc 227 #define _USB_STATUS_VREGOS_SHIFT 0 /**< Shift value for USB_VREGOS */
AnnaBridge 171:3a7713b1edbc 228 #define _USB_STATUS_VREGOS_MASK 0x1UL /**< Bit mask for USB_VREGOS */
AnnaBridge 171:3a7713b1edbc 229 #define _USB_STATUS_VREGOS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_STATUS */
AnnaBridge 171:3a7713b1edbc 230 #define USB_STATUS_VREGOS_DEFAULT (_USB_STATUS_VREGOS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_STATUS */
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232 /* Bit fields for USB IF */
AnnaBridge 171:3a7713b1edbc 233 #define _USB_IF_RESETVALUE 0x00000003UL /**< Default value for USB_IF */
AnnaBridge 171:3a7713b1edbc 234 #define _USB_IF_MASK 0x00000003UL /**< Mask for USB_IF */
AnnaBridge 171:3a7713b1edbc 235 #define USB_IF_VREGOSH (0x1UL << 0) /**< VREGO Sense High Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 236 #define _USB_IF_VREGOSH_SHIFT 0 /**< Shift value for USB_VREGOSH */
AnnaBridge 171:3a7713b1edbc 237 #define _USB_IF_VREGOSH_MASK 0x1UL /**< Bit mask for USB_VREGOSH */
AnnaBridge 171:3a7713b1edbc 238 #define _USB_IF_VREGOSH_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_IF */
AnnaBridge 171:3a7713b1edbc 239 #define USB_IF_VREGOSH_DEFAULT (_USB_IF_VREGOSH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IF */
AnnaBridge 171:3a7713b1edbc 240 #define USB_IF_VREGOSL (0x1UL << 1) /**< VREGO Sense Low Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 241 #define _USB_IF_VREGOSL_SHIFT 1 /**< Shift value for USB_VREGOSL */
AnnaBridge 171:3a7713b1edbc 242 #define _USB_IF_VREGOSL_MASK 0x2UL /**< Bit mask for USB_VREGOSL */
AnnaBridge 171:3a7713b1edbc 243 #define _USB_IF_VREGOSL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_IF */
AnnaBridge 171:3a7713b1edbc 244 #define USB_IF_VREGOSL_DEFAULT (_USB_IF_VREGOSL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IF */
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 /* Bit fields for USB IFS */
AnnaBridge 171:3a7713b1edbc 247 #define _USB_IFS_RESETVALUE 0x00000000UL /**< Default value for USB_IFS */
AnnaBridge 171:3a7713b1edbc 248 #define _USB_IFS_MASK 0x00000003UL /**< Mask for USB_IFS */
AnnaBridge 171:3a7713b1edbc 249 #define USB_IFS_VREGOSH (0x1UL << 0) /**< Set VREGO Sense High Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 250 #define _USB_IFS_VREGOSH_SHIFT 0 /**< Shift value for USB_VREGOSH */
AnnaBridge 171:3a7713b1edbc 251 #define _USB_IFS_VREGOSH_MASK 0x1UL /**< Bit mask for USB_VREGOSH */
AnnaBridge 171:3a7713b1edbc 252 #define _USB_IFS_VREGOSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */
AnnaBridge 171:3a7713b1edbc 253 #define USB_IFS_VREGOSH_DEFAULT (_USB_IFS_VREGOSH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IFS */
AnnaBridge 171:3a7713b1edbc 254 #define USB_IFS_VREGOSL (0x1UL << 1) /**< Set VREGO Sense Low Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 255 #define _USB_IFS_VREGOSL_SHIFT 1 /**< Shift value for USB_VREGOSL */
AnnaBridge 171:3a7713b1edbc 256 #define _USB_IFS_VREGOSL_MASK 0x2UL /**< Bit mask for USB_VREGOSL */
AnnaBridge 171:3a7713b1edbc 257 #define _USB_IFS_VREGOSL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFS */
AnnaBridge 171:3a7713b1edbc 258 #define USB_IFS_VREGOSL_DEFAULT (_USB_IFS_VREGOSL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IFS */
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260 /* Bit fields for USB IFC */
AnnaBridge 171:3a7713b1edbc 261 #define _USB_IFC_RESETVALUE 0x00000000UL /**< Default value for USB_IFC */
AnnaBridge 171:3a7713b1edbc 262 #define _USB_IFC_MASK 0x00000003UL /**< Mask for USB_IFC */
AnnaBridge 171:3a7713b1edbc 263 #define USB_IFC_VREGOSH (0x1UL << 0) /**< Clear VREGO Sense High Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 264 #define _USB_IFC_VREGOSH_SHIFT 0 /**< Shift value for USB_VREGOSH */
AnnaBridge 171:3a7713b1edbc 265 #define _USB_IFC_VREGOSH_MASK 0x1UL /**< Bit mask for USB_VREGOSH */
AnnaBridge 171:3a7713b1edbc 266 #define _USB_IFC_VREGOSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */
AnnaBridge 171:3a7713b1edbc 267 #define USB_IFC_VREGOSH_DEFAULT (_USB_IFC_VREGOSH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IFC */
AnnaBridge 171:3a7713b1edbc 268 #define USB_IFC_VREGOSL (0x1UL << 1) /**< Clear VREGO Sense Low Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 269 #define _USB_IFC_VREGOSL_SHIFT 1 /**< Shift value for USB_VREGOSL */
AnnaBridge 171:3a7713b1edbc 270 #define _USB_IFC_VREGOSL_MASK 0x2UL /**< Bit mask for USB_VREGOSL */
AnnaBridge 171:3a7713b1edbc 271 #define _USB_IFC_VREGOSL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IFC */
AnnaBridge 171:3a7713b1edbc 272 #define USB_IFC_VREGOSL_DEFAULT (_USB_IFC_VREGOSL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IFC */
AnnaBridge 171:3a7713b1edbc 273
AnnaBridge 171:3a7713b1edbc 274 /* Bit fields for USB IEN */
AnnaBridge 171:3a7713b1edbc 275 #define _USB_IEN_RESETVALUE 0x00000000UL /**< Default value for USB_IEN */
AnnaBridge 171:3a7713b1edbc 276 #define _USB_IEN_MASK 0x00000003UL /**< Mask for USB_IEN */
AnnaBridge 171:3a7713b1edbc 277 #define USB_IEN_VREGOSH (0x1UL << 0) /**< VREGO Sense High Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 278 #define _USB_IEN_VREGOSH_SHIFT 0 /**< Shift value for USB_VREGOSH */
AnnaBridge 171:3a7713b1edbc 279 #define _USB_IEN_VREGOSH_MASK 0x1UL /**< Bit mask for USB_VREGOSH */
AnnaBridge 171:3a7713b1edbc 280 #define _USB_IEN_VREGOSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */
AnnaBridge 171:3a7713b1edbc 281 #define USB_IEN_VREGOSH_DEFAULT (_USB_IEN_VREGOSH_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_IEN */
AnnaBridge 171:3a7713b1edbc 282 #define USB_IEN_VREGOSL (0x1UL << 1) /**< VREGO Sense Low Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 283 #define _USB_IEN_VREGOSL_SHIFT 1 /**< Shift value for USB_VREGOSL */
AnnaBridge 171:3a7713b1edbc 284 #define _USB_IEN_VREGOSL_MASK 0x2UL /**< Bit mask for USB_VREGOSL */
AnnaBridge 171:3a7713b1edbc 285 #define _USB_IEN_VREGOSL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_IEN */
AnnaBridge 171:3a7713b1edbc 286 #define USB_IEN_VREGOSL_DEFAULT (_USB_IEN_VREGOSL_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_IEN */
AnnaBridge 171:3a7713b1edbc 287
AnnaBridge 171:3a7713b1edbc 288 /* Bit fields for USB ROUTE */
AnnaBridge 171:3a7713b1edbc 289 #define _USB_ROUTE_RESETVALUE 0x00000000UL /**< Default value for USB_ROUTE */
AnnaBridge 171:3a7713b1edbc 290 #define _USB_ROUTE_MASK 0x00000007UL /**< Mask for USB_ROUTE */
AnnaBridge 171:3a7713b1edbc 291 #define USB_ROUTE_PHYPEN (0x1UL << 0) /**< USB PHY Pin Enable */
AnnaBridge 171:3a7713b1edbc 292 #define _USB_ROUTE_PHYPEN_SHIFT 0 /**< Shift value for USB_PHYPEN */
AnnaBridge 171:3a7713b1edbc 293 #define _USB_ROUTE_PHYPEN_MASK 0x1UL /**< Bit mask for USB_PHYPEN */
AnnaBridge 171:3a7713b1edbc 294 #define _USB_ROUTE_PHYPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTE */
AnnaBridge 171:3a7713b1edbc 295 #define USB_ROUTE_PHYPEN_DEFAULT (_USB_ROUTE_PHYPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_ROUTE */
AnnaBridge 171:3a7713b1edbc 296 #define USB_ROUTE_VBUSENPEN (0x1UL << 1) /**< VBUSEN Pin Enable */
AnnaBridge 171:3a7713b1edbc 297 #define _USB_ROUTE_VBUSENPEN_SHIFT 1 /**< Shift value for USB_VBUSENPEN */
AnnaBridge 171:3a7713b1edbc 298 #define _USB_ROUTE_VBUSENPEN_MASK 0x2UL /**< Bit mask for USB_VBUSENPEN */
AnnaBridge 171:3a7713b1edbc 299 #define _USB_ROUTE_VBUSENPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTE */
AnnaBridge 171:3a7713b1edbc 300 #define USB_ROUTE_VBUSENPEN_DEFAULT (_USB_ROUTE_VBUSENPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_ROUTE */
AnnaBridge 171:3a7713b1edbc 301 #define USB_ROUTE_DMPUPEN (0x1UL << 2) /**< DMPU Pin Enable */
AnnaBridge 171:3a7713b1edbc 302 #define _USB_ROUTE_DMPUPEN_SHIFT 2 /**< Shift value for USB_DMPUPEN */
AnnaBridge 171:3a7713b1edbc 303 #define _USB_ROUTE_DMPUPEN_MASK 0x4UL /**< Bit mask for USB_DMPUPEN */
AnnaBridge 171:3a7713b1edbc 304 #define _USB_ROUTE_DMPUPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_ROUTE */
AnnaBridge 171:3a7713b1edbc 305 #define USB_ROUTE_DMPUPEN_DEFAULT (_USB_ROUTE_DMPUPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_ROUTE */
AnnaBridge 171:3a7713b1edbc 306
AnnaBridge 171:3a7713b1edbc 307 /* Bit fields for USB GOTGCTL */
AnnaBridge 171:3a7713b1edbc 308 #define _USB_GOTGCTL_RESETVALUE 0x00010000UL /**< Default value for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 309 #define _USB_GOTGCTL_MASK 0x001F0FFFUL /**< Mask for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 310 #define USB_GOTGCTL_SESREQSCS (0x1UL << 0) /**< Session Request Success device only */
AnnaBridge 171:3a7713b1edbc 311 #define _USB_GOTGCTL_SESREQSCS_SHIFT 0 /**< Shift value for USB_SESREQSCS */
AnnaBridge 171:3a7713b1edbc 312 #define _USB_GOTGCTL_SESREQSCS_MASK 0x1UL /**< Bit mask for USB_SESREQSCS */
AnnaBridge 171:3a7713b1edbc 313 #define _USB_GOTGCTL_SESREQSCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 314 #define USB_GOTGCTL_SESREQSCS_DEFAULT (_USB_GOTGCTL_SESREQSCS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 315 #define USB_GOTGCTL_SESREQ (0x1UL << 1) /**< Session Request device only */
AnnaBridge 171:3a7713b1edbc 316 #define _USB_GOTGCTL_SESREQ_SHIFT 1 /**< Shift value for USB_SESREQ */
AnnaBridge 171:3a7713b1edbc 317 #define _USB_GOTGCTL_SESREQ_MASK 0x2UL /**< Bit mask for USB_SESREQ */
AnnaBridge 171:3a7713b1edbc 318 #define _USB_GOTGCTL_SESREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 319 #define USB_GOTGCTL_SESREQ_DEFAULT (_USB_GOTGCTL_SESREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 320 #define USB_GOTGCTL_VBVALIDOVEN (0x1UL << 2) /**< VBUS-Valid Override Enable */
AnnaBridge 171:3a7713b1edbc 321 #define _USB_GOTGCTL_VBVALIDOVEN_SHIFT 2 /**< Shift value for USB_VBVALIDOVEN */
AnnaBridge 171:3a7713b1edbc 322 #define _USB_GOTGCTL_VBVALIDOVEN_MASK 0x4UL /**< Bit mask for USB_VBVALIDOVEN */
AnnaBridge 171:3a7713b1edbc 323 #define _USB_GOTGCTL_VBVALIDOVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 324 #define USB_GOTGCTL_VBVALIDOVEN_DEFAULT (_USB_GOTGCTL_VBVALIDOVEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 325 #define USB_GOTGCTL_VBVALIDOVVAL (0x1UL << 3) /**< VBUS Valid Override Value */
AnnaBridge 171:3a7713b1edbc 326 #define _USB_GOTGCTL_VBVALIDOVVAL_SHIFT 3 /**< Shift value for USB_VBVALIDOVVAL */
AnnaBridge 171:3a7713b1edbc 327 #define _USB_GOTGCTL_VBVALIDOVVAL_MASK 0x8UL /**< Bit mask for USB_VBVALIDOVVAL */
AnnaBridge 171:3a7713b1edbc 328 #define _USB_GOTGCTL_VBVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 329 #define USB_GOTGCTL_VBVALIDOVVAL_DEFAULT (_USB_GOTGCTL_VBVALIDOVVAL_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 330 #define USB_GOTGCTL_BVALIDOVEN (0x1UL << 4) /**< BValid Override Enable */
AnnaBridge 171:3a7713b1edbc 331 #define _USB_GOTGCTL_BVALIDOVEN_SHIFT 4 /**< Shift value for USB_BVALIDOVEN */
AnnaBridge 171:3a7713b1edbc 332 #define _USB_GOTGCTL_BVALIDOVEN_MASK 0x10UL /**< Bit mask for USB_BVALIDOVEN */
AnnaBridge 171:3a7713b1edbc 333 #define _USB_GOTGCTL_BVALIDOVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 334 #define USB_GOTGCTL_BVALIDOVEN_DEFAULT (_USB_GOTGCTL_BVALIDOVEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 335 #define USB_GOTGCTL_BVALIDOVVAL (0x1UL << 5) /**< Bvalid Override Value */
AnnaBridge 171:3a7713b1edbc 336 #define _USB_GOTGCTL_BVALIDOVVAL_SHIFT 5 /**< Shift value for USB_BVALIDOVVAL */
AnnaBridge 171:3a7713b1edbc 337 #define _USB_GOTGCTL_BVALIDOVVAL_MASK 0x20UL /**< Bit mask for USB_BVALIDOVVAL */
AnnaBridge 171:3a7713b1edbc 338 #define _USB_GOTGCTL_BVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 339 #define USB_GOTGCTL_BVALIDOVVAL_DEFAULT (_USB_GOTGCTL_BVALIDOVVAL_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 340 #define USB_GOTGCTL_AVALIDOVEN (0x1UL << 6) /**< AValid Override Enable */
AnnaBridge 171:3a7713b1edbc 341 #define _USB_GOTGCTL_AVALIDOVEN_SHIFT 6 /**< Shift value for USB_AVALIDOVEN */
AnnaBridge 171:3a7713b1edbc 342 #define _USB_GOTGCTL_AVALIDOVEN_MASK 0x40UL /**< Bit mask for USB_AVALIDOVEN */
AnnaBridge 171:3a7713b1edbc 343 #define _USB_GOTGCTL_AVALIDOVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 344 #define USB_GOTGCTL_AVALIDOVEN_DEFAULT (_USB_GOTGCTL_AVALIDOVEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 345 #define USB_GOTGCTL_AVALIDOVVAL (0x1UL << 7) /**< Avalid Override Value */
AnnaBridge 171:3a7713b1edbc 346 #define _USB_GOTGCTL_AVALIDOVVAL_SHIFT 7 /**< Shift value for USB_AVALIDOVVAL */
AnnaBridge 171:3a7713b1edbc 347 #define _USB_GOTGCTL_AVALIDOVVAL_MASK 0x80UL /**< Bit mask for USB_AVALIDOVVAL */
AnnaBridge 171:3a7713b1edbc 348 #define _USB_GOTGCTL_AVALIDOVVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 349 #define USB_GOTGCTL_AVALIDOVVAL_DEFAULT (_USB_GOTGCTL_AVALIDOVVAL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 350 #define USB_GOTGCTL_HSTNEGSCS (0x1UL << 8) /**< Host Negotiation Success device only */
AnnaBridge 171:3a7713b1edbc 351 #define _USB_GOTGCTL_HSTNEGSCS_SHIFT 8 /**< Shift value for USB_HSTNEGSCS */
AnnaBridge 171:3a7713b1edbc 352 #define _USB_GOTGCTL_HSTNEGSCS_MASK 0x100UL /**< Bit mask for USB_HSTNEGSCS */
AnnaBridge 171:3a7713b1edbc 353 #define _USB_GOTGCTL_HSTNEGSCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 354 #define USB_GOTGCTL_HSTNEGSCS_DEFAULT (_USB_GOTGCTL_HSTNEGSCS_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 355 #define USB_GOTGCTL_HNPREQ (0x1UL << 9) /**< HNP Request device only */
AnnaBridge 171:3a7713b1edbc 356 #define _USB_GOTGCTL_HNPREQ_SHIFT 9 /**< Shift value for USB_HNPREQ */
AnnaBridge 171:3a7713b1edbc 357 #define _USB_GOTGCTL_HNPREQ_MASK 0x200UL /**< Bit mask for USB_HNPREQ */
AnnaBridge 171:3a7713b1edbc 358 #define _USB_GOTGCTL_HNPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 359 #define USB_GOTGCTL_HNPREQ_DEFAULT (_USB_GOTGCTL_HNPREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 360 #define USB_GOTGCTL_HSTSETHNPEN (0x1UL << 10) /**< Host Set HNP Enable host only */
AnnaBridge 171:3a7713b1edbc 361 #define _USB_GOTGCTL_HSTSETHNPEN_SHIFT 10 /**< Shift value for USB_HSTSETHNPEN */
AnnaBridge 171:3a7713b1edbc 362 #define _USB_GOTGCTL_HSTSETHNPEN_MASK 0x400UL /**< Bit mask for USB_HSTSETHNPEN */
AnnaBridge 171:3a7713b1edbc 363 #define _USB_GOTGCTL_HSTSETHNPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 364 #define USB_GOTGCTL_HSTSETHNPEN_DEFAULT (_USB_GOTGCTL_HSTSETHNPEN_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 365 #define USB_GOTGCTL_DEVHNPEN (0x1UL << 11) /**< Device HNP Enabled device only */
AnnaBridge 171:3a7713b1edbc 366 #define _USB_GOTGCTL_DEVHNPEN_SHIFT 11 /**< Shift value for USB_DEVHNPEN */
AnnaBridge 171:3a7713b1edbc 367 #define _USB_GOTGCTL_DEVHNPEN_MASK 0x800UL /**< Bit mask for USB_DEVHNPEN */
AnnaBridge 171:3a7713b1edbc 368 #define _USB_GOTGCTL_DEVHNPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 369 #define USB_GOTGCTL_DEVHNPEN_DEFAULT (_USB_GOTGCTL_DEVHNPEN_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 370 #define USB_GOTGCTL_CONIDSTS (0x1UL << 16) /**< Connector ID Status host and device */
AnnaBridge 171:3a7713b1edbc 371 #define _USB_GOTGCTL_CONIDSTS_SHIFT 16 /**< Shift value for USB_CONIDSTS */
AnnaBridge 171:3a7713b1edbc 372 #define _USB_GOTGCTL_CONIDSTS_MASK 0x10000UL /**< Bit mask for USB_CONIDSTS */
AnnaBridge 171:3a7713b1edbc 373 #define _USB_GOTGCTL_CONIDSTS_A 0x00000000UL /**< Mode A for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 374 #define _USB_GOTGCTL_CONIDSTS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 375 #define _USB_GOTGCTL_CONIDSTS_B 0x00000001UL /**< Mode B for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 376 #define USB_GOTGCTL_CONIDSTS_A (_USB_GOTGCTL_CONIDSTS_A << 16) /**< Shifted mode A for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 377 #define USB_GOTGCTL_CONIDSTS_DEFAULT (_USB_GOTGCTL_CONIDSTS_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 378 #define USB_GOTGCTL_CONIDSTS_B (_USB_GOTGCTL_CONIDSTS_B << 16) /**< Shifted mode B for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 379 #define USB_GOTGCTL_DBNCTIME (0x1UL << 17) /**< Long/Short Debounce Time host only */
AnnaBridge 171:3a7713b1edbc 380 #define _USB_GOTGCTL_DBNCTIME_SHIFT 17 /**< Shift value for USB_DBNCTIME */
AnnaBridge 171:3a7713b1edbc 381 #define _USB_GOTGCTL_DBNCTIME_MASK 0x20000UL /**< Bit mask for USB_DBNCTIME */
AnnaBridge 171:3a7713b1edbc 382 #define _USB_GOTGCTL_DBNCTIME_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 383 #define _USB_GOTGCTL_DBNCTIME_LONG 0x00000000UL /**< Mode LONG for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 384 #define _USB_GOTGCTL_DBNCTIME_SHORT 0x00000001UL /**< Mode SHORT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 385 #define USB_GOTGCTL_DBNCTIME_DEFAULT (_USB_GOTGCTL_DBNCTIME_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 386 #define USB_GOTGCTL_DBNCTIME_LONG (_USB_GOTGCTL_DBNCTIME_LONG << 17) /**< Shifted mode LONG for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 387 #define USB_GOTGCTL_DBNCTIME_SHORT (_USB_GOTGCTL_DBNCTIME_SHORT << 17) /**< Shifted mode SHORT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 388 #define USB_GOTGCTL_ASESVLD (0x1UL << 18) /**< A-Session Valid host only */
AnnaBridge 171:3a7713b1edbc 389 #define _USB_GOTGCTL_ASESVLD_SHIFT 18 /**< Shift value for USB_ASESVLD */
AnnaBridge 171:3a7713b1edbc 390 #define _USB_GOTGCTL_ASESVLD_MASK 0x40000UL /**< Bit mask for USB_ASESVLD */
AnnaBridge 171:3a7713b1edbc 391 #define _USB_GOTGCTL_ASESVLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 392 #define USB_GOTGCTL_ASESVLD_DEFAULT (_USB_GOTGCTL_ASESVLD_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 393 #define USB_GOTGCTL_BSESVLD (0x1UL << 19) /**< B-Session Valid device only */
AnnaBridge 171:3a7713b1edbc 394 #define _USB_GOTGCTL_BSESVLD_SHIFT 19 /**< Shift value for USB_BSESVLD */
AnnaBridge 171:3a7713b1edbc 395 #define _USB_GOTGCTL_BSESVLD_MASK 0x80000UL /**< Bit mask for USB_BSESVLD */
AnnaBridge 171:3a7713b1edbc 396 #define _USB_GOTGCTL_BSESVLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 397 #define USB_GOTGCTL_BSESVLD_DEFAULT (_USB_GOTGCTL_BSESVLD_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 398 #define USB_GOTGCTL_OTGVER (0x1UL << 20) /**< OTG Version */
AnnaBridge 171:3a7713b1edbc 399 #define _USB_GOTGCTL_OTGVER_SHIFT 20 /**< Shift value for USB_OTGVER */
AnnaBridge 171:3a7713b1edbc 400 #define _USB_GOTGCTL_OTGVER_MASK 0x100000UL /**< Bit mask for USB_OTGVER */
AnnaBridge 171:3a7713b1edbc 401 #define _USB_GOTGCTL_OTGVER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 402 #define _USB_GOTGCTL_OTGVER_OTG13 0x00000000UL /**< Mode OTG13 for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 403 #define _USB_GOTGCTL_OTGVER_OTG20 0x00000001UL /**< Mode OTG20 for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 404 #define USB_GOTGCTL_OTGVER_DEFAULT (_USB_GOTGCTL_OTGVER_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 405 #define USB_GOTGCTL_OTGVER_OTG13 (_USB_GOTGCTL_OTGVER_OTG13 << 20) /**< Shifted mode OTG13 for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 406 #define USB_GOTGCTL_OTGVER_OTG20 (_USB_GOTGCTL_OTGVER_OTG20 << 20) /**< Shifted mode OTG20 for USB_GOTGCTL */
AnnaBridge 171:3a7713b1edbc 407
AnnaBridge 171:3a7713b1edbc 408 /* Bit fields for USB GOTGINT */
AnnaBridge 171:3a7713b1edbc 409 #define _USB_GOTGINT_RESETVALUE 0x00000000UL /**< Default value for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 410 #define _USB_GOTGINT_MASK 0x000E0304UL /**< Mask for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 411 #define USB_GOTGINT_SESENDDET (0x1UL << 2) /**< Session End Detected host and device */
AnnaBridge 171:3a7713b1edbc 412 #define _USB_GOTGINT_SESENDDET_SHIFT 2 /**< Shift value for USB_SESENDDET */
AnnaBridge 171:3a7713b1edbc 413 #define _USB_GOTGINT_SESENDDET_MASK 0x4UL /**< Bit mask for USB_SESENDDET */
AnnaBridge 171:3a7713b1edbc 414 #define _USB_GOTGINT_SESENDDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 415 #define USB_GOTGINT_SESENDDET_DEFAULT (_USB_GOTGINT_SESENDDET_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 416 #define USB_GOTGINT_SESREQSUCSTSCHNG (0x1UL << 8) /**< Session Request Success Status Change host and device */
AnnaBridge 171:3a7713b1edbc 417 #define _USB_GOTGINT_SESREQSUCSTSCHNG_SHIFT 8 /**< Shift value for USB_SESREQSUCSTSCHNG */
AnnaBridge 171:3a7713b1edbc 418 #define _USB_GOTGINT_SESREQSUCSTSCHNG_MASK 0x100UL /**< Bit mask for USB_SESREQSUCSTSCHNG */
AnnaBridge 171:3a7713b1edbc 419 #define _USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 420 #define USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT (_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 421 #define USB_GOTGINT_HSTNEGSUCSTSCHNG (0x1UL << 9) /**< Host Negotiation Success Status Change host and device */
AnnaBridge 171:3a7713b1edbc 422 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_SHIFT 9 /**< Shift value for USB_HSTNEGSUCSTSCHNG */
AnnaBridge 171:3a7713b1edbc 423 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK 0x200UL /**< Bit mask for USB_HSTNEGSUCSTSCHNG */
AnnaBridge 171:3a7713b1edbc 424 #define _USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 425 #define USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT (_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 426 #define USB_GOTGINT_HSTNEGDET (0x1UL << 17) /**< Host Negotiation Detected host and device */
AnnaBridge 171:3a7713b1edbc 427 #define _USB_GOTGINT_HSTNEGDET_SHIFT 17 /**< Shift value for USB_HSTNEGDET */
AnnaBridge 171:3a7713b1edbc 428 #define _USB_GOTGINT_HSTNEGDET_MASK 0x20000UL /**< Bit mask for USB_HSTNEGDET */
AnnaBridge 171:3a7713b1edbc 429 #define _USB_GOTGINT_HSTNEGDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 430 #define USB_GOTGINT_HSTNEGDET_DEFAULT (_USB_GOTGINT_HSTNEGDET_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 431 #define USB_GOTGINT_ADEVTOUTCHG (0x1UL << 18) /**< A-Device Timeout Change host and device */
AnnaBridge 171:3a7713b1edbc 432 #define _USB_GOTGINT_ADEVTOUTCHG_SHIFT 18 /**< Shift value for USB_ADEVTOUTCHG */
AnnaBridge 171:3a7713b1edbc 433 #define _USB_GOTGINT_ADEVTOUTCHG_MASK 0x40000UL /**< Bit mask for USB_ADEVTOUTCHG */
AnnaBridge 171:3a7713b1edbc 434 #define _USB_GOTGINT_ADEVTOUTCHG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 435 #define USB_GOTGINT_ADEVTOUTCHG_DEFAULT (_USB_GOTGINT_ADEVTOUTCHG_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 436 #define USB_GOTGINT_DBNCEDONE (0x1UL << 19) /**< Debounce Done host only */
AnnaBridge 171:3a7713b1edbc 437 #define _USB_GOTGINT_DBNCEDONE_SHIFT 19 /**< Shift value for USB_DBNCEDONE */
AnnaBridge 171:3a7713b1edbc 438 #define _USB_GOTGINT_DBNCEDONE_MASK 0x80000UL /**< Bit mask for USB_DBNCEDONE */
AnnaBridge 171:3a7713b1edbc 439 #define _USB_GOTGINT_DBNCEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 440 #define USB_GOTGINT_DBNCEDONE_DEFAULT (_USB_GOTGINT_DBNCEDONE_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GOTGINT */
AnnaBridge 171:3a7713b1edbc 441
AnnaBridge 171:3a7713b1edbc 442 /* Bit fields for USB GAHBCFG */
AnnaBridge 171:3a7713b1edbc 443 #define _USB_GAHBCFG_RESETVALUE 0x00000000UL /**< Default value for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 444 #define _USB_GAHBCFG_MASK 0x006001BFUL /**< Mask for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 445 #define USB_GAHBCFG_GLBLINTRMSK (0x1UL << 0) /**< Global Interrupt Mask host and device */
AnnaBridge 171:3a7713b1edbc 446 #define _USB_GAHBCFG_GLBLINTRMSK_SHIFT 0 /**< Shift value for USB_GLBLINTRMSK */
AnnaBridge 171:3a7713b1edbc 447 #define _USB_GAHBCFG_GLBLINTRMSK_MASK 0x1UL /**< Bit mask for USB_GLBLINTRMSK */
AnnaBridge 171:3a7713b1edbc 448 #define _USB_GAHBCFG_GLBLINTRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 449 #define USB_GAHBCFG_GLBLINTRMSK_DEFAULT (_USB_GAHBCFG_GLBLINTRMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 450 #define _USB_GAHBCFG_HBSTLEN_SHIFT 1 /**< Shift value for USB_HBSTLEN */
AnnaBridge 171:3a7713b1edbc 451 #define _USB_GAHBCFG_HBSTLEN_MASK 0x1EUL /**< Bit mask for USB_HBSTLEN */
AnnaBridge 171:3a7713b1edbc 452 #define _USB_GAHBCFG_HBSTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 453 #define _USB_GAHBCFG_HBSTLEN_SINGLE 0x00000000UL /**< Mode SINGLE for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 454 #define _USB_GAHBCFG_HBSTLEN_INCR 0x00000001UL /**< Mode INCR for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 455 #define _USB_GAHBCFG_HBSTLEN_INCR4 0x00000003UL /**< Mode INCR4 for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 456 #define _USB_GAHBCFG_HBSTLEN_INCR8 0x00000005UL /**< Mode INCR8 for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 457 #define _USB_GAHBCFG_HBSTLEN_INCR16 0x00000007UL /**< Mode INCR16 for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 458 #define USB_GAHBCFG_HBSTLEN_DEFAULT (_USB_GAHBCFG_HBSTLEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 459 #define USB_GAHBCFG_HBSTLEN_SINGLE (_USB_GAHBCFG_HBSTLEN_SINGLE << 1) /**< Shifted mode SINGLE for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 460 #define USB_GAHBCFG_HBSTLEN_INCR (_USB_GAHBCFG_HBSTLEN_INCR << 1) /**< Shifted mode INCR for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 461 #define USB_GAHBCFG_HBSTLEN_INCR4 (_USB_GAHBCFG_HBSTLEN_INCR4 << 1) /**< Shifted mode INCR4 for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 462 #define USB_GAHBCFG_HBSTLEN_INCR8 (_USB_GAHBCFG_HBSTLEN_INCR8 << 1) /**< Shifted mode INCR8 for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 463 #define USB_GAHBCFG_HBSTLEN_INCR16 (_USB_GAHBCFG_HBSTLEN_INCR16 << 1) /**< Shifted mode INCR16 for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 464 #define USB_GAHBCFG_DMAEN (0x1UL << 5) /**< DMA Enable host and device */
AnnaBridge 171:3a7713b1edbc 465 #define _USB_GAHBCFG_DMAEN_SHIFT 5 /**< Shift value for USB_DMAEN */
AnnaBridge 171:3a7713b1edbc 466 #define _USB_GAHBCFG_DMAEN_MASK 0x20UL /**< Bit mask for USB_DMAEN */
AnnaBridge 171:3a7713b1edbc 467 #define _USB_GAHBCFG_DMAEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 468 #define USB_GAHBCFG_DMAEN_DEFAULT (_USB_GAHBCFG_DMAEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 469 #define USB_GAHBCFG_NPTXFEMPLVL (0x1UL << 7) /**< Non-Periodic TxFIFO Empty Level host and device */
AnnaBridge 171:3a7713b1edbc 470 #define _USB_GAHBCFG_NPTXFEMPLVL_SHIFT 7 /**< Shift value for USB_NPTXFEMPLVL */
AnnaBridge 171:3a7713b1edbc 471 #define _USB_GAHBCFG_NPTXFEMPLVL_MASK 0x80UL /**< Bit mask for USB_NPTXFEMPLVL */
AnnaBridge 171:3a7713b1edbc 472 #define _USB_GAHBCFG_NPTXFEMPLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 473 #define _USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY 0x00000000UL /**< Mode HALFEMPTY for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 474 #define _USB_GAHBCFG_NPTXFEMPLVL_EMPTY 0x00000001UL /**< Mode EMPTY for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 475 #define USB_GAHBCFG_NPTXFEMPLVL_DEFAULT (_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 476 #define USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY (_USB_GAHBCFG_NPTXFEMPLVL_HALFEMPTY << 7) /**< Shifted mode HALFEMPTY for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 477 #define USB_GAHBCFG_NPTXFEMPLVL_EMPTY (_USB_GAHBCFG_NPTXFEMPLVL_EMPTY << 7) /**< Shifted mode EMPTY for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 478 #define USB_GAHBCFG_PTXFEMPLVL (0x1UL << 8) /**< Periodic TxFIFO Empty Level host only */
AnnaBridge 171:3a7713b1edbc 479 #define _USB_GAHBCFG_PTXFEMPLVL_SHIFT 8 /**< Shift value for USB_PTXFEMPLVL */
AnnaBridge 171:3a7713b1edbc 480 #define _USB_GAHBCFG_PTXFEMPLVL_MASK 0x100UL /**< Bit mask for USB_PTXFEMPLVL */
AnnaBridge 171:3a7713b1edbc 481 #define _USB_GAHBCFG_PTXFEMPLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 482 #define _USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY 0x00000000UL /**< Mode HALFEMPTY for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 483 #define _USB_GAHBCFG_PTXFEMPLVL_EMPTY 0x00000001UL /**< Mode EMPTY for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 484 #define USB_GAHBCFG_PTXFEMPLVL_DEFAULT (_USB_GAHBCFG_PTXFEMPLVL_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 485 #define USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY (_USB_GAHBCFG_PTXFEMPLVL_HALFEMPTY << 8) /**< Shifted mode HALFEMPTY for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 486 #define USB_GAHBCFG_PTXFEMPLVL_EMPTY (_USB_GAHBCFG_PTXFEMPLVL_EMPTY << 8) /**< Shifted mode EMPTY for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 487 #define USB_GAHBCFG_REMMEMSUPP (0x1UL << 21) /**< Remote Memory Support */
AnnaBridge 171:3a7713b1edbc 488 #define _USB_GAHBCFG_REMMEMSUPP_SHIFT 21 /**< Shift value for USB_REMMEMSUPP */
AnnaBridge 171:3a7713b1edbc 489 #define _USB_GAHBCFG_REMMEMSUPP_MASK 0x200000UL /**< Bit mask for USB_REMMEMSUPP */
AnnaBridge 171:3a7713b1edbc 490 #define _USB_GAHBCFG_REMMEMSUPP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 491 #define USB_GAHBCFG_REMMEMSUPP_DEFAULT (_USB_GAHBCFG_REMMEMSUPP_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 492 #define USB_GAHBCFG_NOTIALLDMAWRIT (0x1UL << 22) /**< Notify All DMA Writes */
AnnaBridge 171:3a7713b1edbc 493 #define _USB_GAHBCFG_NOTIALLDMAWRIT_SHIFT 22 /**< Shift value for USB_NOTIALLDMAWRIT */
AnnaBridge 171:3a7713b1edbc 494 #define _USB_GAHBCFG_NOTIALLDMAWRIT_MASK 0x400000UL /**< Bit mask for USB_NOTIALLDMAWRIT */
AnnaBridge 171:3a7713b1edbc 495 #define _USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 496 #define USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT (_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GAHBCFG */
AnnaBridge 171:3a7713b1edbc 497
AnnaBridge 171:3a7713b1edbc 498 /* Bit fields for USB GUSBCFG */
AnnaBridge 171:3a7713b1edbc 499 #define _USB_GUSBCFG_RESETVALUE 0x00001440UL /**< Default value for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 500 #define _USB_GUSBCFG_MASK 0xF0403F27UL /**< Mask for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 501 #define _USB_GUSBCFG_TOUTCAL_SHIFT 0 /**< Shift value for USB_TOUTCAL */
AnnaBridge 171:3a7713b1edbc 502 #define _USB_GUSBCFG_TOUTCAL_MASK 0x7UL /**< Bit mask for USB_TOUTCAL */
AnnaBridge 171:3a7713b1edbc 503 #define _USB_GUSBCFG_TOUTCAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 504 #define USB_GUSBCFG_TOUTCAL_DEFAULT (_USB_GUSBCFG_TOUTCAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 505 #define USB_GUSBCFG_FSINTF (0x1UL << 5) /**< Full-Speed Serial Interface Select host and device */
AnnaBridge 171:3a7713b1edbc 506 #define _USB_GUSBCFG_FSINTF_SHIFT 5 /**< Shift value for USB_FSINTF */
AnnaBridge 171:3a7713b1edbc 507 #define _USB_GUSBCFG_FSINTF_MASK 0x20UL /**< Bit mask for USB_FSINTF */
AnnaBridge 171:3a7713b1edbc 508 #define _USB_GUSBCFG_FSINTF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 509 #define USB_GUSBCFG_FSINTF_DEFAULT (_USB_GUSBCFG_FSINTF_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 510 #define USB_GUSBCFG_SRPCAP (0x1UL << 8) /**< SRP-Capable host and device */
AnnaBridge 171:3a7713b1edbc 511 #define _USB_GUSBCFG_SRPCAP_SHIFT 8 /**< Shift value for USB_SRPCAP */
AnnaBridge 171:3a7713b1edbc 512 #define _USB_GUSBCFG_SRPCAP_MASK 0x100UL /**< Bit mask for USB_SRPCAP */
AnnaBridge 171:3a7713b1edbc 513 #define _USB_GUSBCFG_SRPCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 514 #define USB_GUSBCFG_SRPCAP_DEFAULT (_USB_GUSBCFG_SRPCAP_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 515 #define USB_GUSBCFG_HNPCAP (0x1UL << 9) /**< HNP-Capable host and device */
AnnaBridge 171:3a7713b1edbc 516 #define _USB_GUSBCFG_HNPCAP_SHIFT 9 /**< Shift value for USB_HNPCAP */
AnnaBridge 171:3a7713b1edbc 517 #define _USB_GUSBCFG_HNPCAP_MASK 0x200UL /**< Bit mask for USB_HNPCAP */
AnnaBridge 171:3a7713b1edbc 518 #define _USB_GUSBCFG_HNPCAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 519 #define USB_GUSBCFG_HNPCAP_DEFAULT (_USB_GUSBCFG_HNPCAP_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 520 #define _USB_GUSBCFG_USBTRDTIM_SHIFT 10 /**< Shift value for USB_USBTRDTIM */
AnnaBridge 171:3a7713b1edbc 521 #define _USB_GUSBCFG_USBTRDTIM_MASK 0x3C00UL /**< Bit mask for USB_USBTRDTIM */
AnnaBridge 171:3a7713b1edbc 522 #define _USB_GUSBCFG_USBTRDTIM_DEFAULT 0x00000005UL /**< Mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 523 #define USB_GUSBCFG_USBTRDTIM_DEFAULT (_USB_GUSBCFG_USBTRDTIM_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 524 #define USB_GUSBCFG_TERMSELDLPULSE (0x1UL << 22) /**< TermSel DLine Pulsing Selection device only */
AnnaBridge 171:3a7713b1edbc 525 #define _USB_GUSBCFG_TERMSELDLPULSE_SHIFT 22 /**< Shift value for USB_TERMSELDLPULSE */
AnnaBridge 171:3a7713b1edbc 526 #define _USB_GUSBCFG_TERMSELDLPULSE_MASK 0x400000UL /**< Bit mask for USB_TERMSELDLPULSE */
AnnaBridge 171:3a7713b1edbc 527 #define _USB_GUSBCFG_TERMSELDLPULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 528 #define _USB_GUSBCFG_TERMSELDLPULSE_TXVALID 0x00000000UL /**< Mode TXVALID for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 529 #define _USB_GUSBCFG_TERMSELDLPULSE_TERMSEL 0x00000001UL /**< Mode TERMSEL for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 530 #define USB_GUSBCFG_TERMSELDLPULSE_DEFAULT (_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 531 #define USB_GUSBCFG_TERMSELDLPULSE_TXVALID (_USB_GUSBCFG_TERMSELDLPULSE_TXVALID << 22) /**< Shifted mode TXVALID for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 532 #define USB_GUSBCFG_TERMSELDLPULSE_TERMSEL (_USB_GUSBCFG_TERMSELDLPULSE_TERMSEL << 22) /**< Shifted mode TERMSEL for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 533 #define USB_GUSBCFG_TXENDDELAY (0x1UL << 28) /**< Tx End Delay device only */
AnnaBridge 171:3a7713b1edbc 534 #define _USB_GUSBCFG_TXENDDELAY_SHIFT 28 /**< Shift value for USB_TXENDDELAY */
AnnaBridge 171:3a7713b1edbc 535 #define _USB_GUSBCFG_TXENDDELAY_MASK 0x10000000UL /**< Bit mask for USB_TXENDDELAY */
AnnaBridge 171:3a7713b1edbc 536 #define _USB_GUSBCFG_TXENDDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 537 #define USB_GUSBCFG_TXENDDELAY_DEFAULT (_USB_GUSBCFG_TXENDDELAY_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 538 #define USB_GUSBCFG_FORCEHSTMODE (0x1UL << 29) /**< Force Host Mode host and device */
AnnaBridge 171:3a7713b1edbc 539 #define _USB_GUSBCFG_FORCEHSTMODE_SHIFT 29 /**< Shift value for USB_FORCEHSTMODE */
AnnaBridge 171:3a7713b1edbc 540 #define _USB_GUSBCFG_FORCEHSTMODE_MASK 0x20000000UL /**< Bit mask for USB_FORCEHSTMODE */
AnnaBridge 171:3a7713b1edbc 541 #define _USB_GUSBCFG_FORCEHSTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 542 #define USB_GUSBCFG_FORCEHSTMODE_DEFAULT (_USB_GUSBCFG_FORCEHSTMODE_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 543 #define USB_GUSBCFG_FORCEDEVMODE (0x1UL << 30) /**< Force Device Mode host and device */
AnnaBridge 171:3a7713b1edbc 544 #define _USB_GUSBCFG_FORCEDEVMODE_SHIFT 30 /**< Shift value for USB_FORCEDEVMODE */
AnnaBridge 171:3a7713b1edbc 545 #define _USB_GUSBCFG_FORCEDEVMODE_MASK 0x40000000UL /**< Bit mask for USB_FORCEDEVMODE */
AnnaBridge 171:3a7713b1edbc 546 #define _USB_GUSBCFG_FORCEDEVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 547 #define USB_GUSBCFG_FORCEDEVMODE_DEFAULT (_USB_GUSBCFG_FORCEDEVMODE_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 548 #define USB_GUSBCFG_CORRUPTTXPKT (0x1UL << 31) /**< Corrupt Tx packet host and device */
AnnaBridge 171:3a7713b1edbc 549 #define _USB_GUSBCFG_CORRUPTTXPKT_SHIFT 31 /**< Shift value for USB_CORRUPTTXPKT */
AnnaBridge 171:3a7713b1edbc 550 #define _USB_GUSBCFG_CORRUPTTXPKT_MASK 0x80000000UL /**< Bit mask for USB_CORRUPTTXPKT */
AnnaBridge 171:3a7713b1edbc 551 #define _USB_GUSBCFG_CORRUPTTXPKT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 552 #define USB_GUSBCFG_CORRUPTTXPKT_DEFAULT (_USB_GUSBCFG_CORRUPTTXPKT_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GUSBCFG */
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 /* Bit fields for USB GRSTCTL */
AnnaBridge 171:3a7713b1edbc 555 #define _USB_GRSTCTL_RESETVALUE 0x80000000UL /**< Default value for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 556 #define _USB_GRSTCTL_MASK 0xC00007F5UL /**< Mask for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 557 #define USB_GRSTCTL_CSFTRST (0x1UL << 0) /**< Core Soft Reset host and device */
AnnaBridge 171:3a7713b1edbc 558 #define _USB_GRSTCTL_CSFTRST_SHIFT 0 /**< Shift value for USB_CSFTRST */
AnnaBridge 171:3a7713b1edbc 559 #define _USB_GRSTCTL_CSFTRST_MASK 0x1UL /**< Bit mask for USB_CSFTRST */
AnnaBridge 171:3a7713b1edbc 560 #define _USB_GRSTCTL_CSFTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 561 #define USB_GRSTCTL_CSFTRST_DEFAULT (_USB_GRSTCTL_CSFTRST_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 562 #define USB_GRSTCTL_FRMCNTRRST (0x1UL << 2) /**< Host Frame Counter Reset host only */
AnnaBridge 171:3a7713b1edbc 563 #define _USB_GRSTCTL_FRMCNTRRST_SHIFT 2 /**< Shift value for USB_FRMCNTRRST */
AnnaBridge 171:3a7713b1edbc 564 #define _USB_GRSTCTL_FRMCNTRRST_MASK 0x4UL /**< Bit mask for USB_FRMCNTRRST */
AnnaBridge 171:3a7713b1edbc 565 #define _USB_GRSTCTL_FRMCNTRRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 566 #define USB_GRSTCTL_FRMCNTRRST_DEFAULT (_USB_GRSTCTL_FRMCNTRRST_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 567 #define USB_GRSTCTL_RXFFLSH (0x1UL << 4) /**< RxFIFO Flush host and device */
AnnaBridge 171:3a7713b1edbc 568 #define _USB_GRSTCTL_RXFFLSH_SHIFT 4 /**< Shift value for USB_RXFFLSH */
AnnaBridge 171:3a7713b1edbc 569 #define _USB_GRSTCTL_RXFFLSH_MASK 0x10UL /**< Bit mask for USB_RXFFLSH */
AnnaBridge 171:3a7713b1edbc 570 #define _USB_GRSTCTL_RXFFLSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 571 #define USB_GRSTCTL_RXFFLSH_DEFAULT (_USB_GRSTCTL_RXFFLSH_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 572 #define USB_GRSTCTL_TXFFLSH (0x1UL << 5) /**< TxFIFO Flush host and device */
AnnaBridge 171:3a7713b1edbc 573 #define _USB_GRSTCTL_TXFFLSH_SHIFT 5 /**< Shift value for USB_TXFFLSH */
AnnaBridge 171:3a7713b1edbc 574 #define _USB_GRSTCTL_TXFFLSH_MASK 0x20UL /**< Bit mask for USB_TXFFLSH */
AnnaBridge 171:3a7713b1edbc 575 #define _USB_GRSTCTL_TXFFLSH_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 576 #define USB_GRSTCTL_TXFFLSH_DEFAULT (_USB_GRSTCTL_TXFFLSH_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 577 #define _USB_GRSTCTL_TXFNUM_SHIFT 6 /**< Shift value for USB_TXFNUM */
AnnaBridge 171:3a7713b1edbc 578 #define _USB_GRSTCTL_TXFNUM_MASK 0x7C0UL /**< Bit mask for USB_TXFNUM */
AnnaBridge 171:3a7713b1edbc 579 #define _USB_GRSTCTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 580 #define _USB_GRSTCTL_TXFNUM_F0 0x00000000UL /**< Mode F0 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 581 #define _USB_GRSTCTL_TXFNUM_F1 0x00000001UL /**< Mode F1 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 582 #define _USB_GRSTCTL_TXFNUM_F2 0x00000002UL /**< Mode F2 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 583 #define _USB_GRSTCTL_TXFNUM_F3 0x00000003UL /**< Mode F3 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 584 #define _USB_GRSTCTL_TXFNUM_F4 0x00000004UL /**< Mode F4 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 585 #define _USB_GRSTCTL_TXFNUM_F5 0x00000005UL /**< Mode F5 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 586 #define _USB_GRSTCTL_TXFNUM_F6 0x00000006UL /**< Mode F6 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 587 #define _USB_GRSTCTL_TXFNUM_FALL 0x00000010UL /**< Mode FALL for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 588 #define USB_GRSTCTL_TXFNUM_DEFAULT (_USB_GRSTCTL_TXFNUM_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 589 #define USB_GRSTCTL_TXFNUM_F0 (_USB_GRSTCTL_TXFNUM_F0 << 6) /**< Shifted mode F0 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 590 #define USB_GRSTCTL_TXFNUM_F1 (_USB_GRSTCTL_TXFNUM_F1 << 6) /**< Shifted mode F1 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 591 #define USB_GRSTCTL_TXFNUM_F2 (_USB_GRSTCTL_TXFNUM_F2 << 6) /**< Shifted mode F2 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 592 #define USB_GRSTCTL_TXFNUM_F3 (_USB_GRSTCTL_TXFNUM_F3 << 6) /**< Shifted mode F3 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 593 #define USB_GRSTCTL_TXFNUM_F4 (_USB_GRSTCTL_TXFNUM_F4 << 6) /**< Shifted mode F4 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 594 #define USB_GRSTCTL_TXFNUM_F5 (_USB_GRSTCTL_TXFNUM_F5 << 6) /**< Shifted mode F5 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 595 #define USB_GRSTCTL_TXFNUM_F6 (_USB_GRSTCTL_TXFNUM_F6 << 6) /**< Shifted mode F6 for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 596 #define USB_GRSTCTL_TXFNUM_FALL (_USB_GRSTCTL_TXFNUM_FALL << 6) /**< Shifted mode FALL for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 597 #define USB_GRSTCTL_DMAREQ (0x1UL << 30) /**< DMA Request Signal host and device */
AnnaBridge 171:3a7713b1edbc 598 #define _USB_GRSTCTL_DMAREQ_SHIFT 30 /**< Shift value for USB_DMAREQ */
AnnaBridge 171:3a7713b1edbc 599 #define _USB_GRSTCTL_DMAREQ_MASK 0x40000000UL /**< Bit mask for USB_DMAREQ */
AnnaBridge 171:3a7713b1edbc 600 #define _USB_GRSTCTL_DMAREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 601 #define USB_GRSTCTL_DMAREQ_DEFAULT (_USB_GRSTCTL_DMAREQ_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 602 #define USB_GRSTCTL_AHBIDLE (0x1UL << 31) /**< AHB Master Idle host and device */
AnnaBridge 171:3a7713b1edbc 603 #define _USB_GRSTCTL_AHBIDLE_SHIFT 31 /**< Shift value for USB_AHBIDLE */
AnnaBridge 171:3a7713b1edbc 604 #define _USB_GRSTCTL_AHBIDLE_MASK 0x80000000UL /**< Bit mask for USB_AHBIDLE */
AnnaBridge 171:3a7713b1edbc 605 #define _USB_GRSTCTL_AHBIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 606 #define USB_GRSTCTL_AHBIDLE_DEFAULT (_USB_GRSTCTL_AHBIDLE_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GRSTCTL */
AnnaBridge 171:3a7713b1edbc 607
AnnaBridge 171:3a7713b1edbc 608 /* Bit fields for USB GINTSTS */
AnnaBridge 171:3a7713b1edbc 609 #define _USB_GINTSTS_RESETVALUE 0x14000020UL /**< Default value for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 610 #define _USB_GINTSTS_MASK 0xF7FCFCFFUL /**< Mask for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 611 #define USB_GINTSTS_CURMOD (0x1UL << 0) /**< Current Mode of Operation host and device */
AnnaBridge 171:3a7713b1edbc 612 #define _USB_GINTSTS_CURMOD_SHIFT 0 /**< Shift value for USB_CURMOD */
AnnaBridge 171:3a7713b1edbc 613 #define _USB_GINTSTS_CURMOD_MASK 0x1UL /**< Bit mask for USB_CURMOD */
AnnaBridge 171:3a7713b1edbc 614 #define _USB_GINTSTS_CURMOD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 615 #define _USB_GINTSTS_CURMOD_DEVICE 0x00000000UL /**< Mode DEVICE for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 616 #define _USB_GINTSTS_CURMOD_HOST 0x00000001UL /**< Mode HOST for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 617 #define USB_GINTSTS_CURMOD_DEFAULT (_USB_GINTSTS_CURMOD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 618 #define USB_GINTSTS_CURMOD_DEVICE (_USB_GINTSTS_CURMOD_DEVICE << 0) /**< Shifted mode DEVICE for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 619 #define USB_GINTSTS_CURMOD_HOST (_USB_GINTSTS_CURMOD_HOST << 0) /**< Shifted mode HOST for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 620 #define USB_GINTSTS_MODEMIS (0x1UL << 1) /**< Mode Mismatch Interrupt host and device */
AnnaBridge 171:3a7713b1edbc 621 #define _USB_GINTSTS_MODEMIS_SHIFT 1 /**< Shift value for USB_MODEMIS */
AnnaBridge 171:3a7713b1edbc 622 #define _USB_GINTSTS_MODEMIS_MASK 0x2UL /**< Bit mask for USB_MODEMIS */
AnnaBridge 171:3a7713b1edbc 623 #define _USB_GINTSTS_MODEMIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 624 #define USB_GINTSTS_MODEMIS_DEFAULT (_USB_GINTSTS_MODEMIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 625 #define USB_GINTSTS_OTGINT (0x1UL << 2) /**< OTG Interrupt host and device */
AnnaBridge 171:3a7713b1edbc 626 #define _USB_GINTSTS_OTGINT_SHIFT 2 /**< Shift value for USB_OTGINT */
AnnaBridge 171:3a7713b1edbc 627 #define _USB_GINTSTS_OTGINT_MASK 0x4UL /**< Bit mask for USB_OTGINT */
AnnaBridge 171:3a7713b1edbc 628 #define _USB_GINTSTS_OTGINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 629 #define USB_GINTSTS_OTGINT_DEFAULT (_USB_GINTSTS_OTGINT_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 630 #define USB_GINTSTS_SOF (0x1UL << 3) /**< Start of Frame host and device */
AnnaBridge 171:3a7713b1edbc 631 #define _USB_GINTSTS_SOF_SHIFT 3 /**< Shift value for USB_SOF */
AnnaBridge 171:3a7713b1edbc 632 #define _USB_GINTSTS_SOF_MASK 0x8UL /**< Bit mask for USB_SOF */
AnnaBridge 171:3a7713b1edbc 633 #define _USB_GINTSTS_SOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 634 #define USB_GINTSTS_SOF_DEFAULT (_USB_GINTSTS_SOF_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 635 #define USB_GINTSTS_RXFLVL (0x1UL << 4) /**< RxFIFO Non-Empty host and device */
AnnaBridge 171:3a7713b1edbc 636 #define _USB_GINTSTS_RXFLVL_SHIFT 4 /**< Shift value for USB_RXFLVL */
AnnaBridge 171:3a7713b1edbc 637 #define _USB_GINTSTS_RXFLVL_MASK 0x10UL /**< Bit mask for USB_RXFLVL */
AnnaBridge 171:3a7713b1edbc 638 #define _USB_GINTSTS_RXFLVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 639 #define USB_GINTSTS_RXFLVL_DEFAULT (_USB_GINTSTS_RXFLVL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 640 #define USB_GINTSTS_NPTXFEMP (0x1UL << 5) /**< Non-Periodic TxFIFO Empty host only */
AnnaBridge 171:3a7713b1edbc 641 #define _USB_GINTSTS_NPTXFEMP_SHIFT 5 /**< Shift value for USB_NPTXFEMP */
AnnaBridge 171:3a7713b1edbc 642 #define _USB_GINTSTS_NPTXFEMP_MASK 0x20UL /**< Bit mask for USB_NPTXFEMP */
AnnaBridge 171:3a7713b1edbc 643 #define _USB_GINTSTS_NPTXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 644 #define USB_GINTSTS_NPTXFEMP_DEFAULT (_USB_GINTSTS_NPTXFEMP_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 645 #define USB_GINTSTS_GINNAKEFF (0x1UL << 6) /**< Global IN Non-periodic NAK Effective device only */
AnnaBridge 171:3a7713b1edbc 646 #define _USB_GINTSTS_GINNAKEFF_SHIFT 6 /**< Shift value for USB_GINNAKEFF */
AnnaBridge 171:3a7713b1edbc 647 #define _USB_GINTSTS_GINNAKEFF_MASK 0x40UL /**< Bit mask for USB_GINNAKEFF */
AnnaBridge 171:3a7713b1edbc 648 #define _USB_GINTSTS_GINNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 649 #define USB_GINTSTS_GINNAKEFF_DEFAULT (_USB_GINTSTS_GINNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 650 #define USB_GINTSTS_GOUTNAKEFF (0x1UL << 7) /**< Global OUT NAK Effective device only */
AnnaBridge 171:3a7713b1edbc 651 #define _USB_GINTSTS_GOUTNAKEFF_SHIFT 7 /**< Shift value for USB_GOUTNAKEFF */
AnnaBridge 171:3a7713b1edbc 652 #define _USB_GINTSTS_GOUTNAKEFF_MASK 0x80UL /**< Bit mask for USB_GOUTNAKEFF */
AnnaBridge 171:3a7713b1edbc 653 #define _USB_GINTSTS_GOUTNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 654 #define USB_GINTSTS_GOUTNAKEFF_DEFAULT (_USB_GINTSTS_GOUTNAKEFF_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 655 #define USB_GINTSTS_ERLYSUSP (0x1UL << 10) /**< Early Suspend device only */
AnnaBridge 171:3a7713b1edbc 656 #define _USB_GINTSTS_ERLYSUSP_SHIFT 10 /**< Shift value for USB_ERLYSUSP */
AnnaBridge 171:3a7713b1edbc 657 #define _USB_GINTSTS_ERLYSUSP_MASK 0x400UL /**< Bit mask for USB_ERLYSUSP */
AnnaBridge 171:3a7713b1edbc 658 #define _USB_GINTSTS_ERLYSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 659 #define USB_GINTSTS_ERLYSUSP_DEFAULT (_USB_GINTSTS_ERLYSUSP_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 660 #define USB_GINTSTS_USBSUSP (0x1UL << 11) /**< USB Suspend device only */
AnnaBridge 171:3a7713b1edbc 661 #define _USB_GINTSTS_USBSUSP_SHIFT 11 /**< Shift value for USB_USBSUSP */
AnnaBridge 171:3a7713b1edbc 662 #define _USB_GINTSTS_USBSUSP_MASK 0x800UL /**< Bit mask for USB_USBSUSP */
AnnaBridge 171:3a7713b1edbc 663 #define _USB_GINTSTS_USBSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 664 #define USB_GINTSTS_USBSUSP_DEFAULT (_USB_GINTSTS_USBSUSP_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 665 #define USB_GINTSTS_USBRST (0x1UL << 12) /**< USB Reset device only */
AnnaBridge 171:3a7713b1edbc 666 #define _USB_GINTSTS_USBRST_SHIFT 12 /**< Shift value for USB_USBRST */
AnnaBridge 171:3a7713b1edbc 667 #define _USB_GINTSTS_USBRST_MASK 0x1000UL /**< Bit mask for USB_USBRST */
AnnaBridge 171:3a7713b1edbc 668 #define _USB_GINTSTS_USBRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 669 #define USB_GINTSTS_USBRST_DEFAULT (_USB_GINTSTS_USBRST_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 670 #define USB_GINTSTS_ENUMDONE (0x1UL << 13) /**< Enumeration Done device only */
AnnaBridge 171:3a7713b1edbc 671 #define _USB_GINTSTS_ENUMDONE_SHIFT 13 /**< Shift value for USB_ENUMDONE */
AnnaBridge 171:3a7713b1edbc 672 #define _USB_GINTSTS_ENUMDONE_MASK 0x2000UL /**< Bit mask for USB_ENUMDONE */
AnnaBridge 171:3a7713b1edbc 673 #define _USB_GINTSTS_ENUMDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 674 #define USB_GINTSTS_ENUMDONE_DEFAULT (_USB_GINTSTS_ENUMDONE_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 675 #define USB_GINTSTS_ISOOUTDROP (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt device only */
AnnaBridge 171:3a7713b1edbc 676 #define _USB_GINTSTS_ISOOUTDROP_SHIFT 14 /**< Shift value for USB_ISOOUTDROP */
AnnaBridge 171:3a7713b1edbc 677 #define _USB_GINTSTS_ISOOUTDROP_MASK 0x4000UL /**< Bit mask for USB_ISOOUTDROP */
AnnaBridge 171:3a7713b1edbc 678 #define _USB_GINTSTS_ISOOUTDROP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 679 #define USB_GINTSTS_ISOOUTDROP_DEFAULT (_USB_GINTSTS_ISOOUTDROP_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 680 #define USB_GINTSTS_EOPF (0x1UL << 15) /**< End of Periodic Frame Interrupt */
AnnaBridge 171:3a7713b1edbc 681 #define _USB_GINTSTS_EOPF_SHIFT 15 /**< Shift value for USB_EOPF */
AnnaBridge 171:3a7713b1edbc 682 #define _USB_GINTSTS_EOPF_MASK 0x8000UL /**< Bit mask for USB_EOPF */
AnnaBridge 171:3a7713b1edbc 683 #define _USB_GINTSTS_EOPF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 684 #define USB_GINTSTS_EOPF_DEFAULT (_USB_GINTSTS_EOPF_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 685 #define USB_GINTSTS_IEPINT (0x1UL << 18) /**< IN Endpoints Interrupt device only */
AnnaBridge 171:3a7713b1edbc 686 #define _USB_GINTSTS_IEPINT_SHIFT 18 /**< Shift value for USB_IEPINT */
AnnaBridge 171:3a7713b1edbc 687 #define _USB_GINTSTS_IEPINT_MASK 0x40000UL /**< Bit mask for USB_IEPINT */
AnnaBridge 171:3a7713b1edbc 688 #define _USB_GINTSTS_IEPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 689 #define USB_GINTSTS_IEPINT_DEFAULT (_USB_GINTSTS_IEPINT_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 690 #define USB_GINTSTS_OEPINT (0x1UL << 19) /**< OUT Endpoints Interrupt device only */
AnnaBridge 171:3a7713b1edbc 691 #define _USB_GINTSTS_OEPINT_SHIFT 19 /**< Shift value for USB_OEPINT */
AnnaBridge 171:3a7713b1edbc 692 #define _USB_GINTSTS_OEPINT_MASK 0x80000UL /**< Bit mask for USB_OEPINT */
AnnaBridge 171:3a7713b1edbc 693 #define _USB_GINTSTS_OEPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 694 #define USB_GINTSTS_OEPINT_DEFAULT (_USB_GINTSTS_OEPINT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 695 #define USB_GINTSTS_INCOMPISOIN (0x1UL << 20) /**< Incomplete Isochronous IN Transfer device only */
AnnaBridge 171:3a7713b1edbc 696 #define _USB_GINTSTS_INCOMPISOIN_SHIFT 20 /**< Shift value for USB_INCOMPISOIN */
AnnaBridge 171:3a7713b1edbc 697 #define _USB_GINTSTS_INCOMPISOIN_MASK 0x100000UL /**< Bit mask for USB_INCOMPISOIN */
AnnaBridge 171:3a7713b1edbc 698 #define _USB_GINTSTS_INCOMPISOIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 699 #define USB_GINTSTS_INCOMPISOIN_DEFAULT (_USB_GINTSTS_INCOMPISOIN_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 700 #define USB_GINTSTS_INCOMPLP (0x1UL << 21) /**< Incomplete Periodic Transfer host and device */
AnnaBridge 171:3a7713b1edbc 701 #define _USB_GINTSTS_INCOMPLP_SHIFT 21 /**< Shift value for USB_INCOMPLP */
AnnaBridge 171:3a7713b1edbc 702 #define _USB_GINTSTS_INCOMPLP_MASK 0x200000UL /**< Bit mask for USB_INCOMPLP */
AnnaBridge 171:3a7713b1edbc 703 #define _USB_GINTSTS_INCOMPLP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 704 #define USB_GINTSTS_INCOMPLP_DEFAULT (_USB_GINTSTS_INCOMPLP_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 705 #define USB_GINTSTS_FETSUSP (0x1UL << 22) /**< Data Fetch Suspended device only */
AnnaBridge 171:3a7713b1edbc 706 #define _USB_GINTSTS_FETSUSP_SHIFT 22 /**< Shift value for USB_FETSUSP */
AnnaBridge 171:3a7713b1edbc 707 #define _USB_GINTSTS_FETSUSP_MASK 0x400000UL /**< Bit mask for USB_FETSUSP */
AnnaBridge 171:3a7713b1edbc 708 #define _USB_GINTSTS_FETSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 709 #define USB_GINTSTS_FETSUSP_DEFAULT (_USB_GINTSTS_FETSUSP_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 710 #define USB_GINTSTS_RESETDET (0x1UL << 23) /**< Reset detected Interrupt device only */
AnnaBridge 171:3a7713b1edbc 711 #define _USB_GINTSTS_RESETDET_SHIFT 23 /**< Shift value for USB_RESETDET */
AnnaBridge 171:3a7713b1edbc 712 #define _USB_GINTSTS_RESETDET_MASK 0x800000UL /**< Bit mask for USB_RESETDET */
AnnaBridge 171:3a7713b1edbc 713 #define _USB_GINTSTS_RESETDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 714 #define USB_GINTSTS_RESETDET_DEFAULT (_USB_GINTSTS_RESETDET_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 715 #define USB_GINTSTS_PRTINT (0x1UL << 24) /**< Host Port Interrupt host only */
AnnaBridge 171:3a7713b1edbc 716 #define _USB_GINTSTS_PRTINT_SHIFT 24 /**< Shift value for USB_PRTINT */
AnnaBridge 171:3a7713b1edbc 717 #define _USB_GINTSTS_PRTINT_MASK 0x1000000UL /**< Bit mask for USB_PRTINT */
AnnaBridge 171:3a7713b1edbc 718 #define _USB_GINTSTS_PRTINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 719 #define USB_GINTSTS_PRTINT_DEFAULT (_USB_GINTSTS_PRTINT_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 720 #define USB_GINTSTS_HCHINT (0x1UL << 25) /**< Host Channels Interrupt host only */
AnnaBridge 171:3a7713b1edbc 721 #define _USB_GINTSTS_HCHINT_SHIFT 25 /**< Shift value for USB_HCHINT */
AnnaBridge 171:3a7713b1edbc 722 #define _USB_GINTSTS_HCHINT_MASK 0x2000000UL /**< Bit mask for USB_HCHINT */
AnnaBridge 171:3a7713b1edbc 723 #define _USB_GINTSTS_HCHINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 724 #define USB_GINTSTS_HCHINT_DEFAULT (_USB_GINTSTS_HCHINT_DEFAULT << 25) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 725 #define USB_GINTSTS_PTXFEMP (0x1UL << 26) /**< Periodic TxFIFO Empty host only */
AnnaBridge 171:3a7713b1edbc 726 #define _USB_GINTSTS_PTXFEMP_SHIFT 26 /**< Shift value for USB_PTXFEMP */
AnnaBridge 171:3a7713b1edbc 727 #define _USB_GINTSTS_PTXFEMP_MASK 0x4000000UL /**< Bit mask for USB_PTXFEMP */
AnnaBridge 171:3a7713b1edbc 728 #define _USB_GINTSTS_PTXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 729 #define USB_GINTSTS_PTXFEMP_DEFAULT (_USB_GINTSTS_PTXFEMP_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 730 #define USB_GINTSTS_CONIDSTSCHNG (0x1UL << 28) /**< Connector ID Status Change host and device */
AnnaBridge 171:3a7713b1edbc 731 #define _USB_GINTSTS_CONIDSTSCHNG_SHIFT 28 /**< Shift value for USB_CONIDSTSCHNG */
AnnaBridge 171:3a7713b1edbc 732 #define _USB_GINTSTS_CONIDSTSCHNG_MASK 0x10000000UL /**< Bit mask for USB_CONIDSTSCHNG */
AnnaBridge 171:3a7713b1edbc 733 #define _USB_GINTSTS_CONIDSTSCHNG_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 734 #define USB_GINTSTS_CONIDSTSCHNG_DEFAULT (_USB_GINTSTS_CONIDSTSCHNG_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 735 #define USB_GINTSTS_DISCONNINT (0x1UL << 29) /**< Disconnect Detected Interrupt host only */
AnnaBridge 171:3a7713b1edbc 736 #define _USB_GINTSTS_DISCONNINT_SHIFT 29 /**< Shift value for USB_DISCONNINT */
AnnaBridge 171:3a7713b1edbc 737 #define _USB_GINTSTS_DISCONNINT_MASK 0x20000000UL /**< Bit mask for USB_DISCONNINT */
AnnaBridge 171:3a7713b1edbc 738 #define _USB_GINTSTS_DISCONNINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 739 #define USB_GINTSTS_DISCONNINT_DEFAULT (_USB_GINTSTS_DISCONNINT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 740 #define USB_GINTSTS_SESSREQINT (0x1UL << 30) /**< Session Request/New Session Detected Interrupt host and device */
AnnaBridge 171:3a7713b1edbc 741 #define _USB_GINTSTS_SESSREQINT_SHIFT 30 /**< Shift value for USB_SESSREQINT */
AnnaBridge 171:3a7713b1edbc 742 #define _USB_GINTSTS_SESSREQINT_MASK 0x40000000UL /**< Bit mask for USB_SESSREQINT */
AnnaBridge 171:3a7713b1edbc 743 #define _USB_GINTSTS_SESSREQINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 744 #define USB_GINTSTS_SESSREQINT_DEFAULT (_USB_GINTSTS_SESSREQINT_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 745 #define USB_GINTSTS_WKUPINT (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt host and device */
AnnaBridge 171:3a7713b1edbc 746 #define _USB_GINTSTS_WKUPINT_SHIFT 31 /**< Shift value for USB_WKUPINT */
AnnaBridge 171:3a7713b1edbc 747 #define _USB_GINTSTS_WKUPINT_MASK 0x80000000UL /**< Bit mask for USB_WKUPINT */
AnnaBridge 171:3a7713b1edbc 748 #define _USB_GINTSTS_WKUPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 749 #define USB_GINTSTS_WKUPINT_DEFAULT (_USB_GINTSTS_WKUPINT_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GINTSTS */
AnnaBridge 171:3a7713b1edbc 750
AnnaBridge 171:3a7713b1edbc 751 /* Bit fields for USB GINTMSK */
AnnaBridge 171:3a7713b1edbc 752 #define _USB_GINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 753 #define _USB_GINTMSK_MASK 0xF7FCFCFEUL /**< Mask for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 754 #define USB_GINTMSK_MODEMISMSK (0x1UL << 1) /**< Mode Mismatch Interrupt Mask host and device */
AnnaBridge 171:3a7713b1edbc 755 #define _USB_GINTMSK_MODEMISMSK_SHIFT 1 /**< Shift value for USB_MODEMISMSK */
AnnaBridge 171:3a7713b1edbc 756 #define _USB_GINTMSK_MODEMISMSK_MASK 0x2UL /**< Bit mask for USB_MODEMISMSK */
AnnaBridge 171:3a7713b1edbc 757 #define _USB_GINTMSK_MODEMISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 758 #define USB_GINTMSK_MODEMISMSK_DEFAULT (_USB_GINTMSK_MODEMISMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 759 #define USB_GINTMSK_OTGINTMSK (0x1UL << 2) /**< OTG Interrupt Mask host and device */
AnnaBridge 171:3a7713b1edbc 760 #define _USB_GINTMSK_OTGINTMSK_SHIFT 2 /**< Shift value for USB_OTGINTMSK */
AnnaBridge 171:3a7713b1edbc 761 #define _USB_GINTMSK_OTGINTMSK_MASK 0x4UL /**< Bit mask for USB_OTGINTMSK */
AnnaBridge 171:3a7713b1edbc 762 #define _USB_GINTMSK_OTGINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 763 #define USB_GINTMSK_OTGINTMSK_DEFAULT (_USB_GINTMSK_OTGINTMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 764 #define USB_GINTMSK_SOFMSK (0x1UL << 3) /**< Start of Frame Mask host and device */
AnnaBridge 171:3a7713b1edbc 765 #define _USB_GINTMSK_SOFMSK_SHIFT 3 /**< Shift value for USB_SOFMSK */
AnnaBridge 171:3a7713b1edbc 766 #define _USB_GINTMSK_SOFMSK_MASK 0x8UL /**< Bit mask for USB_SOFMSK */
AnnaBridge 171:3a7713b1edbc 767 #define _USB_GINTMSK_SOFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 768 #define USB_GINTMSK_SOFMSK_DEFAULT (_USB_GINTMSK_SOFMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 769 #define USB_GINTMSK_RXFLVLMSK (0x1UL << 4) /**< Receive FIFO Non-Empty Mask host and device */
AnnaBridge 171:3a7713b1edbc 770 #define _USB_GINTMSK_RXFLVLMSK_SHIFT 4 /**< Shift value for USB_RXFLVLMSK */
AnnaBridge 171:3a7713b1edbc 771 #define _USB_GINTMSK_RXFLVLMSK_MASK 0x10UL /**< Bit mask for USB_RXFLVLMSK */
AnnaBridge 171:3a7713b1edbc 772 #define _USB_GINTMSK_RXFLVLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 773 #define USB_GINTMSK_RXFLVLMSK_DEFAULT (_USB_GINTMSK_RXFLVLMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 774 #define USB_GINTMSK_NPTXFEMPMSK (0x1UL << 5) /**< Non-Periodic TxFIFO Empty Mask host only */
AnnaBridge 171:3a7713b1edbc 775 #define _USB_GINTMSK_NPTXFEMPMSK_SHIFT 5 /**< Shift value for USB_NPTXFEMPMSK */
AnnaBridge 171:3a7713b1edbc 776 #define _USB_GINTMSK_NPTXFEMPMSK_MASK 0x20UL /**< Bit mask for USB_NPTXFEMPMSK */
AnnaBridge 171:3a7713b1edbc 777 #define _USB_GINTMSK_NPTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 778 #define USB_GINTMSK_NPTXFEMPMSK_DEFAULT (_USB_GINTMSK_NPTXFEMPMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 779 #define USB_GINTMSK_GINNAKEFFMSK (0x1UL << 6) /**< Global Non-periodic IN NAK Effective Mask device only */
AnnaBridge 171:3a7713b1edbc 780 #define _USB_GINTMSK_GINNAKEFFMSK_SHIFT 6 /**< Shift value for USB_GINNAKEFFMSK */
AnnaBridge 171:3a7713b1edbc 781 #define _USB_GINTMSK_GINNAKEFFMSK_MASK 0x40UL /**< Bit mask for USB_GINNAKEFFMSK */
AnnaBridge 171:3a7713b1edbc 782 #define _USB_GINTMSK_GINNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 783 #define USB_GINTMSK_GINNAKEFFMSK_DEFAULT (_USB_GINTMSK_GINNAKEFFMSK_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 784 #define USB_GINTMSK_GOUTNAKEFFMSK (0x1UL << 7) /**< Global OUT NAK Effective Mask device only */
AnnaBridge 171:3a7713b1edbc 785 #define _USB_GINTMSK_GOUTNAKEFFMSK_SHIFT 7 /**< Shift value for USB_GOUTNAKEFFMSK */
AnnaBridge 171:3a7713b1edbc 786 #define _USB_GINTMSK_GOUTNAKEFFMSK_MASK 0x80UL /**< Bit mask for USB_GOUTNAKEFFMSK */
AnnaBridge 171:3a7713b1edbc 787 #define _USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 788 #define USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT (_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 789 #define USB_GINTMSK_ERLYSUSPMSK (0x1UL << 10) /**< Early Suspend Mask device only */
AnnaBridge 171:3a7713b1edbc 790 #define _USB_GINTMSK_ERLYSUSPMSK_SHIFT 10 /**< Shift value for USB_ERLYSUSPMSK */
AnnaBridge 171:3a7713b1edbc 791 #define _USB_GINTMSK_ERLYSUSPMSK_MASK 0x400UL /**< Bit mask for USB_ERLYSUSPMSK */
AnnaBridge 171:3a7713b1edbc 792 #define _USB_GINTMSK_ERLYSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 793 #define USB_GINTMSK_ERLYSUSPMSK_DEFAULT (_USB_GINTMSK_ERLYSUSPMSK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 794 #define USB_GINTMSK_USBSUSPMSK (0x1UL << 11) /**< USB Suspend Mask device only */
AnnaBridge 171:3a7713b1edbc 795 #define _USB_GINTMSK_USBSUSPMSK_SHIFT 11 /**< Shift value for USB_USBSUSPMSK */
AnnaBridge 171:3a7713b1edbc 796 #define _USB_GINTMSK_USBSUSPMSK_MASK 0x800UL /**< Bit mask for USB_USBSUSPMSK */
AnnaBridge 171:3a7713b1edbc 797 #define _USB_GINTMSK_USBSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 798 #define USB_GINTMSK_USBSUSPMSK_DEFAULT (_USB_GINTMSK_USBSUSPMSK_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 799 #define USB_GINTMSK_USBRSTMSK (0x1UL << 12) /**< USB Reset Mask device only */
AnnaBridge 171:3a7713b1edbc 800 #define _USB_GINTMSK_USBRSTMSK_SHIFT 12 /**< Shift value for USB_USBRSTMSK */
AnnaBridge 171:3a7713b1edbc 801 #define _USB_GINTMSK_USBRSTMSK_MASK 0x1000UL /**< Bit mask for USB_USBRSTMSK */
AnnaBridge 171:3a7713b1edbc 802 #define _USB_GINTMSK_USBRSTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 803 #define USB_GINTMSK_USBRSTMSK_DEFAULT (_USB_GINTMSK_USBRSTMSK_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 804 #define USB_GINTMSK_ENUMDONEMSK (0x1UL << 13) /**< Enumeration Done Mask device only */
AnnaBridge 171:3a7713b1edbc 805 #define _USB_GINTMSK_ENUMDONEMSK_SHIFT 13 /**< Shift value for USB_ENUMDONEMSK */
AnnaBridge 171:3a7713b1edbc 806 #define _USB_GINTMSK_ENUMDONEMSK_MASK 0x2000UL /**< Bit mask for USB_ENUMDONEMSK */
AnnaBridge 171:3a7713b1edbc 807 #define _USB_GINTMSK_ENUMDONEMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 808 #define USB_GINTMSK_ENUMDONEMSK_DEFAULT (_USB_GINTMSK_ENUMDONEMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 809 #define USB_GINTMSK_ISOOUTDROPMSK (0x1UL << 14) /**< Isochronous OUT Packet Dropped Interrupt Mask device only */
AnnaBridge 171:3a7713b1edbc 810 #define _USB_GINTMSK_ISOOUTDROPMSK_SHIFT 14 /**< Shift value for USB_ISOOUTDROPMSK */
AnnaBridge 171:3a7713b1edbc 811 #define _USB_GINTMSK_ISOOUTDROPMSK_MASK 0x4000UL /**< Bit mask for USB_ISOOUTDROPMSK */
AnnaBridge 171:3a7713b1edbc 812 #define _USB_GINTMSK_ISOOUTDROPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 813 #define USB_GINTMSK_ISOOUTDROPMSK_DEFAULT (_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT << 14) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 814 #define USB_GINTMSK_EOPFMSK (0x1UL << 15) /**< End of Periodic Frame Interrupt Mask device only */
AnnaBridge 171:3a7713b1edbc 815 #define _USB_GINTMSK_EOPFMSK_SHIFT 15 /**< Shift value for USB_EOPFMSK */
AnnaBridge 171:3a7713b1edbc 816 #define _USB_GINTMSK_EOPFMSK_MASK 0x8000UL /**< Bit mask for USB_EOPFMSK */
AnnaBridge 171:3a7713b1edbc 817 #define _USB_GINTMSK_EOPFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 818 #define USB_GINTMSK_EOPFMSK_DEFAULT (_USB_GINTMSK_EOPFMSK_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 819 #define USB_GINTMSK_IEPINTMSK (0x1UL << 18) /**< IN Endpoints Interrupt Mask device only */
AnnaBridge 171:3a7713b1edbc 820 #define _USB_GINTMSK_IEPINTMSK_SHIFT 18 /**< Shift value for USB_IEPINTMSK */
AnnaBridge 171:3a7713b1edbc 821 #define _USB_GINTMSK_IEPINTMSK_MASK 0x40000UL /**< Bit mask for USB_IEPINTMSK */
AnnaBridge 171:3a7713b1edbc 822 #define _USB_GINTMSK_IEPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 823 #define USB_GINTMSK_IEPINTMSK_DEFAULT (_USB_GINTMSK_IEPINTMSK_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 824 #define USB_GINTMSK_OEPINTMSK (0x1UL << 19) /**< OUT Endpoints Interrupt Mask device only */
AnnaBridge 171:3a7713b1edbc 825 #define _USB_GINTMSK_OEPINTMSK_SHIFT 19 /**< Shift value for USB_OEPINTMSK */
AnnaBridge 171:3a7713b1edbc 826 #define _USB_GINTMSK_OEPINTMSK_MASK 0x80000UL /**< Bit mask for USB_OEPINTMSK */
AnnaBridge 171:3a7713b1edbc 827 #define _USB_GINTMSK_OEPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 828 #define USB_GINTMSK_OEPINTMSK_DEFAULT (_USB_GINTMSK_OEPINTMSK_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 829 #define USB_GINTMSK_INCOMPISOINMSK (0x1UL << 20) /**< Incomplete Isochronous IN Transfer Mask device only */
AnnaBridge 171:3a7713b1edbc 830 #define _USB_GINTMSK_INCOMPISOINMSK_SHIFT 20 /**< Shift value for USB_INCOMPISOINMSK */
AnnaBridge 171:3a7713b1edbc 831 #define _USB_GINTMSK_INCOMPISOINMSK_MASK 0x100000UL /**< Bit mask for USB_INCOMPISOINMSK */
AnnaBridge 171:3a7713b1edbc 832 #define _USB_GINTMSK_INCOMPISOINMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 833 #define USB_GINTMSK_INCOMPISOINMSK_DEFAULT (_USB_GINTMSK_INCOMPISOINMSK_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 834 #define USB_GINTMSK_INCOMPLPMSK (0x1UL << 21) /**< Incomplete Periodic Transfer Mask host and device */
AnnaBridge 171:3a7713b1edbc 835 #define _USB_GINTMSK_INCOMPLPMSK_SHIFT 21 /**< Shift value for USB_INCOMPLPMSK */
AnnaBridge 171:3a7713b1edbc 836 #define _USB_GINTMSK_INCOMPLPMSK_MASK 0x200000UL /**< Bit mask for USB_INCOMPLPMSK */
AnnaBridge 171:3a7713b1edbc 837 #define _USB_GINTMSK_INCOMPLPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 838 #define USB_GINTMSK_INCOMPLPMSK_DEFAULT (_USB_GINTMSK_INCOMPLPMSK_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 839 #define USB_GINTMSK_FETSUSPMSK (0x1UL << 22) /**< Data Fetch Suspended Mask device only */
AnnaBridge 171:3a7713b1edbc 840 #define _USB_GINTMSK_FETSUSPMSK_SHIFT 22 /**< Shift value for USB_FETSUSPMSK */
AnnaBridge 171:3a7713b1edbc 841 #define _USB_GINTMSK_FETSUSPMSK_MASK 0x400000UL /**< Bit mask for USB_FETSUSPMSK */
AnnaBridge 171:3a7713b1edbc 842 #define _USB_GINTMSK_FETSUSPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 843 #define USB_GINTMSK_FETSUSPMSK_DEFAULT (_USB_GINTMSK_FETSUSPMSK_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 844 #define USB_GINTMSK_RESETDETMSK (0x1UL << 23) /**< Reset detected Interrupt Mask device only */
AnnaBridge 171:3a7713b1edbc 845 #define _USB_GINTMSK_RESETDETMSK_SHIFT 23 /**< Shift value for USB_RESETDETMSK */
AnnaBridge 171:3a7713b1edbc 846 #define _USB_GINTMSK_RESETDETMSK_MASK 0x800000UL /**< Bit mask for USB_RESETDETMSK */
AnnaBridge 171:3a7713b1edbc 847 #define _USB_GINTMSK_RESETDETMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 848 #define USB_GINTMSK_RESETDETMSK_DEFAULT (_USB_GINTMSK_RESETDETMSK_DEFAULT << 23) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 849 #define USB_GINTMSK_PRTINTMSK (0x1UL << 24) /**< Host Port Interrupt Mask host only */
AnnaBridge 171:3a7713b1edbc 850 #define _USB_GINTMSK_PRTINTMSK_SHIFT 24 /**< Shift value for USB_PRTINTMSK */
AnnaBridge 171:3a7713b1edbc 851 #define _USB_GINTMSK_PRTINTMSK_MASK 0x1000000UL /**< Bit mask for USB_PRTINTMSK */
AnnaBridge 171:3a7713b1edbc 852 #define _USB_GINTMSK_PRTINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 853 #define USB_GINTMSK_PRTINTMSK_DEFAULT (_USB_GINTMSK_PRTINTMSK_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 854 #define USB_GINTMSK_HCHINTMSK (0x1UL << 25) /**< Host Channels Interrupt Mask host only */
AnnaBridge 171:3a7713b1edbc 855 #define _USB_GINTMSK_HCHINTMSK_SHIFT 25 /**< Shift value for USB_HCHINTMSK */
AnnaBridge 171:3a7713b1edbc 856 #define _USB_GINTMSK_HCHINTMSK_MASK 0x2000000UL /**< Bit mask for USB_HCHINTMSK */
AnnaBridge 171:3a7713b1edbc 857 #define _USB_GINTMSK_HCHINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 858 #define USB_GINTMSK_HCHINTMSK_DEFAULT (_USB_GINTMSK_HCHINTMSK_DEFAULT << 25) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 859 #define USB_GINTMSK_PTXFEMPMSK (0x1UL << 26) /**< Periodic TxFIFO Empty Mask host only */
AnnaBridge 171:3a7713b1edbc 860 #define _USB_GINTMSK_PTXFEMPMSK_SHIFT 26 /**< Shift value for USB_PTXFEMPMSK */
AnnaBridge 171:3a7713b1edbc 861 #define _USB_GINTMSK_PTXFEMPMSK_MASK 0x4000000UL /**< Bit mask for USB_PTXFEMPMSK */
AnnaBridge 171:3a7713b1edbc 862 #define _USB_GINTMSK_PTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 863 #define USB_GINTMSK_PTXFEMPMSK_DEFAULT (_USB_GINTMSK_PTXFEMPMSK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 864 #define USB_GINTMSK_CONIDSTSCHNGMSK (0x1UL << 28) /**< Connector ID Status Change Mask host and device */
AnnaBridge 171:3a7713b1edbc 865 #define _USB_GINTMSK_CONIDSTSCHNGMSK_SHIFT 28 /**< Shift value for USB_CONIDSTSCHNGMSK */
AnnaBridge 171:3a7713b1edbc 866 #define _USB_GINTMSK_CONIDSTSCHNGMSK_MASK 0x10000000UL /**< Bit mask for USB_CONIDSTSCHNGMSK */
AnnaBridge 171:3a7713b1edbc 867 #define _USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 868 #define USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT (_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 869 #define USB_GINTMSK_DISCONNINTMSK (0x1UL << 29) /**< Disconnect Detected Interrupt Mask host and device */
AnnaBridge 171:3a7713b1edbc 870 #define _USB_GINTMSK_DISCONNINTMSK_SHIFT 29 /**< Shift value for USB_DISCONNINTMSK */
AnnaBridge 171:3a7713b1edbc 871 #define _USB_GINTMSK_DISCONNINTMSK_MASK 0x20000000UL /**< Bit mask for USB_DISCONNINTMSK */
AnnaBridge 171:3a7713b1edbc 872 #define _USB_GINTMSK_DISCONNINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 873 #define USB_GINTMSK_DISCONNINTMSK_DEFAULT (_USB_GINTMSK_DISCONNINTMSK_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 874 #define USB_GINTMSK_SESSREQINTMSK (0x1UL << 30) /**< Session Request/New Session Detected Interrupt Mask host and device */
AnnaBridge 171:3a7713b1edbc 875 #define _USB_GINTMSK_SESSREQINTMSK_SHIFT 30 /**< Shift value for USB_SESSREQINTMSK */
AnnaBridge 171:3a7713b1edbc 876 #define _USB_GINTMSK_SESSREQINTMSK_MASK 0x40000000UL /**< Bit mask for USB_SESSREQINTMSK */
AnnaBridge 171:3a7713b1edbc 877 #define _USB_GINTMSK_SESSREQINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 878 #define USB_GINTMSK_SESSREQINTMSK_DEFAULT (_USB_GINTMSK_SESSREQINTMSK_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 879 #define USB_GINTMSK_WKUPINTMSK (0x1UL << 31) /**< Resume/Remote Wakeup Detected Interrupt Mask host and device */
AnnaBridge 171:3a7713b1edbc 880 #define _USB_GINTMSK_WKUPINTMSK_SHIFT 31 /**< Shift value for USB_WKUPINTMSK */
AnnaBridge 171:3a7713b1edbc 881 #define _USB_GINTMSK_WKUPINTMSK_MASK 0x80000000UL /**< Bit mask for USB_WKUPINTMSK */
AnnaBridge 171:3a7713b1edbc 882 #define _USB_GINTMSK_WKUPINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 883 #define USB_GINTMSK_WKUPINTMSK_DEFAULT (_USB_GINTMSK_WKUPINTMSK_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_GINTMSK */
AnnaBridge 171:3a7713b1edbc 884
AnnaBridge 171:3a7713b1edbc 885 /* Bit fields for USB GRXSTSR */
AnnaBridge 171:3a7713b1edbc 886 #define _USB_GRXSTSR_RESETVALUE 0x00000000UL /**< Default value for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 887 #define _USB_GRXSTSR_MASK 0x01FFFFFFUL /**< Mask for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 888 #define _USB_GRXSTSR_CHEPNUM_SHIFT 0 /**< Shift value for USB_CHEPNUM */
AnnaBridge 171:3a7713b1edbc 889 #define _USB_GRXSTSR_CHEPNUM_MASK 0xFUL /**< Bit mask for USB_CHEPNUM */
AnnaBridge 171:3a7713b1edbc 890 #define _USB_GRXSTSR_CHEPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 891 #define USB_GRXSTSR_CHEPNUM_DEFAULT (_USB_GRXSTSR_CHEPNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 892 #define _USB_GRXSTSR_BCNT_SHIFT 4 /**< Shift value for USB_BCNT */
AnnaBridge 171:3a7713b1edbc 893 #define _USB_GRXSTSR_BCNT_MASK 0x7FF0UL /**< Bit mask for USB_BCNT */
AnnaBridge 171:3a7713b1edbc 894 #define _USB_GRXSTSR_BCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 895 #define USB_GRXSTSR_BCNT_DEFAULT (_USB_GRXSTSR_BCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 896 #define _USB_GRXSTSR_DPID_SHIFT 15 /**< Shift value for USB_DPID */
AnnaBridge 171:3a7713b1edbc 897 #define _USB_GRXSTSR_DPID_MASK 0x18000UL /**< Bit mask for USB_DPID */
AnnaBridge 171:3a7713b1edbc 898 #define _USB_GRXSTSR_DPID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 899 #define _USB_GRXSTSR_DPID_DATA0 0x00000000UL /**< Mode DATA0 for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 900 #define _USB_GRXSTSR_DPID_DATA1 0x00000001UL /**< Mode DATA1 for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 901 #define _USB_GRXSTSR_DPID_DATA2 0x00000002UL /**< Mode DATA2 for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 902 #define _USB_GRXSTSR_DPID_MDATA 0x00000003UL /**< Mode MDATA for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 903 #define USB_GRXSTSR_DPID_DEFAULT (_USB_GRXSTSR_DPID_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 904 #define USB_GRXSTSR_DPID_DATA0 (_USB_GRXSTSR_DPID_DATA0 << 15) /**< Shifted mode DATA0 for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 905 #define USB_GRXSTSR_DPID_DATA1 (_USB_GRXSTSR_DPID_DATA1 << 15) /**< Shifted mode DATA1 for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 906 #define USB_GRXSTSR_DPID_DATA2 (_USB_GRXSTSR_DPID_DATA2 << 15) /**< Shifted mode DATA2 for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 907 #define USB_GRXSTSR_DPID_MDATA (_USB_GRXSTSR_DPID_MDATA << 15) /**< Shifted mode MDATA for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 908 #define _USB_GRXSTSR_PKTSTS_SHIFT 17 /**< Shift value for USB_PKTSTS */
AnnaBridge 171:3a7713b1edbc 909 #define _USB_GRXSTSR_PKTSTS_MASK 0x1E0000UL /**< Bit mask for USB_PKTSTS */
AnnaBridge 171:3a7713b1edbc 910 #define _USB_GRXSTSR_PKTSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 911 #define _USB_GRXSTSR_PKTSTS_GOUTNAK 0x00000001UL /**< Mode GOUTNAK for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 912 #define _USB_GRXSTSR_PKTSTS_PKTRCV 0x00000002UL /**< Mode PKTRCV for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 913 #define _USB_GRXSTSR_PKTSTS_XFERCOMPL 0x00000003UL /**< Mode XFERCOMPL for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 914 #define _USB_GRXSTSR_PKTSTS_SETUPCOMPL 0x00000004UL /**< Mode SETUPCOMPL for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 915 #define _USB_GRXSTSR_PKTSTS_TGLERR 0x00000005UL /**< Mode TGLERR for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 916 #define _USB_GRXSTSR_PKTSTS_SETUPRCV 0x00000006UL /**< Mode SETUPRCV for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 917 #define _USB_GRXSTSR_PKTSTS_CHLT 0x00000007UL /**< Mode CHLT for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 918 #define USB_GRXSTSR_PKTSTS_DEFAULT (_USB_GRXSTSR_PKTSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 919 #define USB_GRXSTSR_PKTSTS_GOUTNAK (_USB_GRXSTSR_PKTSTS_GOUTNAK << 17) /**< Shifted mode GOUTNAK for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 920 #define USB_GRXSTSR_PKTSTS_PKTRCV (_USB_GRXSTSR_PKTSTS_PKTRCV << 17) /**< Shifted mode PKTRCV for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 921 #define USB_GRXSTSR_PKTSTS_XFERCOMPL (_USB_GRXSTSR_PKTSTS_XFERCOMPL << 17) /**< Shifted mode XFERCOMPL for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 922 #define USB_GRXSTSR_PKTSTS_SETUPCOMPL (_USB_GRXSTSR_PKTSTS_SETUPCOMPL << 17) /**< Shifted mode SETUPCOMPL for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 923 #define USB_GRXSTSR_PKTSTS_TGLERR (_USB_GRXSTSR_PKTSTS_TGLERR << 17) /**< Shifted mode TGLERR for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 924 #define USB_GRXSTSR_PKTSTS_SETUPRCV (_USB_GRXSTSR_PKTSTS_SETUPRCV << 17) /**< Shifted mode SETUPRCV for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 925 #define USB_GRXSTSR_PKTSTS_CHLT (_USB_GRXSTSR_PKTSTS_CHLT << 17) /**< Shifted mode CHLT for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 926 #define _USB_GRXSTSR_FN_SHIFT 21 /**< Shift value for USB_FN */
AnnaBridge 171:3a7713b1edbc 927 #define _USB_GRXSTSR_FN_MASK 0x1E00000UL /**< Bit mask for USB_FN */
AnnaBridge 171:3a7713b1edbc 928 #define _USB_GRXSTSR_FN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 929 #define USB_GRXSTSR_FN_DEFAULT (_USB_GRXSTSR_FN_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GRXSTSR */
AnnaBridge 171:3a7713b1edbc 930
AnnaBridge 171:3a7713b1edbc 931 /* Bit fields for USB GRXSTSP */
AnnaBridge 171:3a7713b1edbc 932 #define _USB_GRXSTSP_RESETVALUE 0x00000000UL /**< Default value for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 933 #define _USB_GRXSTSP_MASK 0x01FFFFFFUL /**< Mask for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 934 #define _USB_GRXSTSP_CHEPNUM_SHIFT 0 /**< Shift value for USB_CHEPNUM */
AnnaBridge 171:3a7713b1edbc 935 #define _USB_GRXSTSP_CHEPNUM_MASK 0xFUL /**< Bit mask for USB_CHEPNUM */
AnnaBridge 171:3a7713b1edbc 936 #define _USB_GRXSTSP_CHEPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 937 #define USB_GRXSTSP_CHEPNUM_DEFAULT (_USB_GRXSTSP_CHEPNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 938 #define _USB_GRXSTSP_BCNT_SHIFT 4 /**< Shift value for USB_BCNT */
AnnaBridge 171:3a7713b1edbc 939 #define _USB_GRXSTSP_BCNT_MASK 0x7FF0UL /**< Bit mask for USB_BCNT */
AnnaBridge 171:3a7713b1edbc 940 #define _USB_GRXSTSP_BCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 941 #define USB_GRXSTSP_BCNT_DEFAULT (_USB_GRXSTSP_BCNT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 942 #define _USB_GRXSTSP_DPID_SHIFT 15 /**< Shift value for USB_DPID */
AnnaBridge 171:3a7713b1edbc 943 #define _USB_GRXSTSP_DPID_MASK 0x18000UL /**< Bit mask for USB_DPID */
AnnaBridge 171:3a7713b1edbc 944 #define _USB_GRXSTSP_DPID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 945 #define _USB_GRXSTSP_DPID_DATA0 0x00000000UL /**< Mode DATA0 for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 946 #define _USB_GRXSTSP_DPID_DATA1 0x00000001UL /**< Mode DATA1 for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 947 #define _USB_GRXSTSP_DPID_DATA2 0x00000002UL /**< Mode DATA2 for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 948 #define _USB_GRXSTSP_DPID_MDATA 0x00000003UL /**< Mode MDATA for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 949 #define USB_GRXSTSP_DPID_DEFAULT (_USB_GRXSTSP_DPID_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 950 #define USB_GRXSTSP_DPID_DATA0 (_USB_GRXSTSP_DPID_DATA0 << 15) /**< Shifted mode DATA0 for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 951 #define USB_GRXSTSP_DPID_DATA1 (_USB_GRXSTSP_DPID_DATA1 << 15) /**< Shifted mode DATA1 for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 952 #define USB_GRXSTSP_DPID_DATA2 (_USB_GRXSTSP_DPID_DATA2 << 15) /**< Shifted mode DATA2 for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 953 #define USB_GRXSTSP_DPID_MDATA (_USB_GRXSTSP_DPID_MDATA << 15) /**< Shifted mode MDATA for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 954 #define _USB_GRXSTSP_PKTSTS_SHIFT 17 /**< Shift value for USB_PKTSTS */
AnnaBridge 171:3a7713b1edbc 955 #define _USB_GRXSTSP_PKTSTS_MASK 0x1E0000UL /**< Bit mask for USB_PKTSTS */
AnnaBridge 171:3a7713b1edbc 956 #define _USB_GRXSTSP_PKTSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 957 #define _USB_GRXSTSP_PKTSTS_GOUTNAK 0x00000001UL /**< Mode GOUTNAK for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 958 #define _USB_GRXSTSP_PKTSTS_PKTRCV 0x00000002UL /**< Mode PKTRCV for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 959 #define _USB_GRXSTSP_PKTSTS_XFERCOMPL 0x00000003UL /**< Mode XFERCOMPL for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 960 #define _USB_GRXSTSP_PKTSTS_SETUPCOMPL 0x00000004UL /**< Mode SETUPCOMPL for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 961 #define _USB_GRXSTSP_PKTSTS_TGLERR 0x00000005UL /**< Mode TGLERR for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 962 #define _USB_GRXSTSP_PKTSTS_SETUPRCV 0x00000006UL /**< Mode SETUPRCV for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 963 #define _USB_GRXSTSP_PKTSTS_CHLT 0x00000007UL /**< Mode CHLT for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 964 #define USB_GRXSTSP_PKTSTS_DEFAULT (_USB_GRXSTSP_PKTSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 965 #define USB_GRXSTSP_PKTSTS_GOUTNAK (_USB_GRXSTSP_PKTSTS_GOUTNAK << 17) /**< Shifted mode GOUTNAK for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 966 #define USB_GRXSTSP_PKTSTS_PKTRCV (_USB_GRXSTSP_PKTSTS_PKTRCV << 17) /**< Shifted mode PKTRCV for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 967 #define USB_GRXSTSP_PKTSTS_XFERCOMPL (_USB_GRXSTSP_PKTSTS_XFERCOMPL << 17) /**< Shifted mode XFERCOMPL for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 968 #define USB_GRXSTSP_PKTSTS_SETUPCOMPL (_USB_GRXSTSP_PKTSTS_SETUPCOMPL << 17) /**< Shifted mode SETUPCOMPL for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 969 #define USB_GRXSTSP_PKTSTS_TGLERR (_USB_GRXSTSP_PKTSTS_TGLERR << 17) /**< Shifted mode TGLERR for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 970 #define USB_GRXSTSP_PKTSTS_SETUPRCV (_USB_GRXSTSP_PKTSTS_SETUPRCV << 17) /**< Shifted mode SETUPRCV for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 971 #define USB_GRXSTSP_PKTSTS_CHLT (_USB_GRXSTSP_PKTSTS_CHLT << 17) /**< Shifted mode CHLT for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 972 #define _USB_GRXSTSP_FN_SHIFT 21 /**< Shift value for USB_FN */
AnnaBridge 171:3a7713b1edbc 973 #define _USB_GRXSTSP_FN_MASK 0x1E00000UL /**< Bit mask for USB_FN */
AnnaBridge 171:3a7713b1edbc 974 #define _USB_GRXSTSP_FN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 975 #define USB_GRXSTSP_FN_DEFAULT (_USB_GRXSTSP_FN_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_GRXSTSP */
AnnaBridge 171:3a7713b1edbc 976
AnnaBridge 171:3a7713b1edbc 977 /* Bit fields for USB GRXFSIZ */
AnnaBridge 171:3a7713b1edbc 978 #define _USB_GRXFSIZ_RESETVALUE 0x00000200UL /**< Default value for USB_GRXFSIZ */
AnnaBridge 171:3a7713b1edbc 979 #define _USB_GRXFSIZ_MASK 0x000003FFUL /**< Mask for USB_GRXFSIZ */
AnnaBridge 171:3a7713b1edbc 980 #define _USB_GRXFSIZ_RXFDEP_SHIFT 0 /**< Shift value for USB_RXFDEP */
AnnaBridge 171:3a7713b1edbc 981 #define _USB_GRXFSIZ_RXFDEP_MASK 0x3FFUL /**< Bit mask for USB_RXFDEP */
AnnaBridge 171:3a7713b1edbc 982 #define _USB_GRXFSIZ_RXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GRXFSIZ */
AnnaBridge 171:3a7713b1edbc 983 #define USB_GRXFSIZ_RXFDEP_DEFAULT (_USB_GRXFSIZ_RXFDEP_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GRXFSIZ */
AnnaBridge 171:3a7713b1edbc 984
AnnaBridge 171:3a7713b1edbc 985 /* Bit fields for USB GNPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 986 #define _USB_GNPTXFSIZ_RESETVALUE 0x02000200UL /**< Default value for USB_GNPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 987 #define _USB_GNPTXFSIZ_MASK 0xFFFF03FFUL /**< Mask for USB_GNPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 988 #define _USB_GNPTXFSIZ_NPTXFSTADDR_SHIFT 0 /**< Shift value for USB_NPTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 989 #define _USB_GNPTXFSIZ_NPTXFSTADDR_MASK 0x3FFUL /**< Bit mask for USB_NPTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 990 #define _USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 991 #define USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT (_USB_GNPTXFSIZ_NPTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GNPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 992 #define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_SHIFT 16 /**< Shift value for USB_NPTXFINEPTXF0DEP */
AnnaBridge 171:3a7713b1edbc 993 #define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_MASK 0xFFFF0000UL /**< Bit mask for USB_NPTXFINEPTXF0DEP */
AnnaBridge 171:3a7713b1edbc 994 #define _USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 995 #define USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT (_USB_GNPTXFSIZ_NPTXFINEPTXF0DEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GNPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 996
AnnaBridge 171:3a7713b1edbc 997 /* Bit fields for USB GNPTXSTS */
AnnaBridge 171:3a7713b1edbc 998 #define _USB_GNPTXSTS_RESETVALUE 0x00080200UL /**< Default value for USB_GNPTXSTS */
AnnaBridge 171:3a7713b1edbc 999 #define _USB_GNPTXSTS_MASK 0x7FFFFFFFUL /**< Mask for USB_GNPTXSTS */
AnnaBridge 171:3a7713b1edbc 1000 #define _USB_GNPTXSTS_NPTXFSPCAVAIL_SHIFT 0 /**< Shift value for USB_NPTXFSPCAVAIL */
AnnaBridge 171:3a7713b1edbc 1001 #define _USB_GNPTXSTS_NPTXFSPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_NPTXFSPCAVAIL */
AnnaBridge 171:3a7713b1edbc 1002 #define _USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GNPTXSTS */
AnnaBridge 171:3a7713b1edbc 1003 #define USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT (_USB_GNPTXSTS_NPTXFSPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GNPTXSTS */
AnnaBridge 171:3a7713b1edbc 1004 #define _USB_GNPTXSTS_NPTXQSPCAVAIL_SHIFT 16 /**< Shift value for USB_NPTXQSPCAVAIL */
AnnaBridge 171:3a7713b1edbc 1005 #define _USB_GNPTXSTS_NPTXQSPCAVAIL_MASK 0xFF0000UL /**< Bit mask for USB_NPTXQSPCAVAIL */
AnnaBridge 171:3a7713b1edbc 1006 #define _USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT 0x00000008UL /**< Mode DEFAULT for USB_GNPTXSTS */
AnnaBridge 171:3a7713b1edbc 1007 #define USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT (_USB_GNPTXSTS_NPTXQSPCAVAIL_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GNPTXSTS */
AnnaBridge 171:3a7713b1edbc 1008 #define _USB_GNPTXSTS_NPTXQTOP_SHIFT 24 /**< Shift value for USB_NPTXQTOP */
AnnaBridge 171:3a7713b1edbc 1009 #define _USB_GNPTXSTS_NPTXQTOP_MASK 0x7F000000UL /**< Bit mask for USB_NPTXQTOP */
AnnaBridge 171:3a7713b1edbc 1010 #define _USB_GNPTXSTS_NPTXQTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_GNPTXSTS */
AnnaBridge 171:3a7713b1edbc 1011 #define USB_GNPTXSTS_NPTXQTOP_DEFAULT (_USB_GNPTXSTS_NPTXQTOP_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_GNPTXSTS */
AnnaBridge 171:3a7713b1edbc 1012
AnnaBridge 171:3a7713b1edbc 1013 /* Bit fields for USB GDFIFOCFG */
AnnaBridge 171:3a7713b1edbc 1014 #define _USB_GDFIFOCFG_RESETVALUE 0x01F20200UL /**< Default value for USB_GDFIFOCFG */
AnnaBridge 171:3a7713b1edbc 1015 #define _USB_GDFIFOCFG_MASK 0xFFFFFFFFUL /**< Mask for USB_GDFIFOCFG */
AnnaBridge 171:3a7713b1edbc 1016 #define _USB_GDFIFOCFG_GDFIFOCFG_SHIFT 0 /**< Shift value for USB_GDFIFOCFG */
AnnaBridge 171:3a7713b1edbc 1017 #define _USB_GDFIFOCFG_GDFIFOCFG_MASK 0xFFFFUL /**< Bit mask for USB_GDFIFOCFG */
AnnaBridge 171:3a7713b1edbc 1018 #define _USB_GDFIFOCFG_GDFIFOCFG_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_GDFIFOCFG */
AnnaBridge 171:3a7713b1edbc 1019 #define USB_GDFIFOCFG_GDFIFOCFG_DEFAULT (_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_GDFIFOCFG */
AnnaBridge 171:3a7713b1edbc 1020 #define _USB_GDFIFOCFG_EPINFOBASEADDR_SHIFT 16 /**< Shift value for USB_EPINFOBASEADDR */
AnnaBridge 171:3a7713b1edbc 1021 #define _USB_GDFIFOCFG_EPINFOBASEADDR_MASK 0xFFFF0000UL /**< Bit mask for USB_EPINFOBASEADDR */
AnnaBridge 171:3a7713b1edbc 1022 #define _USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT 0x000001F2UL /**< Mode DEFAULT for USB_GDFIFOCFG */
AnnaBridge 171:3a7713b1edbc 1023 #define USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT (_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_GDFIFOCFG */
AnnaBridge 171:3a7713b1edbc 1024
AnnaBridge 171:3a7713b1edbc 1025 /* Bit fields for USB HPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 1026 #define _USB_HPTXFSIZ_RESETVALUE 0x02000400UL /**< Default value for USB_HPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 1027 #define _USB_HPTXFSIZ_MASK 0x03FF07FFUL /**< Mask for USB_HPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 1028 #define _USB_HPTXFSIZ_PTXFSTADDR_SHIFT 0 /**< Shift value for USB_PTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1029 #define _USB_HPTXFSIZ_PTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_PTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1030 #define _USB_HPTXFSIZ_PTXFSTADDR_DEFAULT 0x00000400UL /**< Mode DEFAULT for USB_HPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 1031 #define USB_HPTXFSIZ_PTXFSTADDR_DEFAULT (_USB_HPTXFSIZ_PTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 1032 #define _USB_HPTXFSIZ_PTXFSIZE_SHIFT 16 /**< Shift value for USB_PTXFSIZE */
AnnaBridge 171:3a7713b1edbc 1033 #define _USB_HPTXFSIZ_PTXFSIZE_MASK 0x3FF0000UL /**< Bit mask for USB_PTXFSIZE */
AnnaBridge 171:3a7713b1edbc 1034 #define _USB_HPTXFSIZ_PTXFSIZE_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_HPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 1035 #define USB_HPTXFSIZ_PTXFSIZE_DEFAULT (_USB_HPTXFSIZ_PTXFSIZE_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HPTXFSIZ */
AnnaBridge 171:3a7713b1edbc 1036
AnnaBridge 171:3a7713b1edbc 1037 /* Bit fields for USB DIEPTXF1 */
AnnaBridge 171:3a7713b1edbc 1038 #define _USB_DIEPTXF1_RESETVALUE 0x02000400UL /**< Default value for USB_DIEPTXF1 */
AnnaBridge 171:3a7713b1edbc 1039 #define _USB_DIEPTXF1_MASK 0x03FF07FFUL /**< Mask for USB_DIEPTXF1 */
AnnaBridge 171:3a7713b1edbc 1040 #define _USB_DIEPTXF1_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1041 #define _USB_DIEPTXF1_INEPNTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_INEPNTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1042 #define _USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x00000400UL /**< Mode DEFAULT for USB_DIEPTXF1 */
AnnaBridge 171:3a7713b1edbc 1043 #define USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF1 */
AnnaBridge 171:3a7713b1edbc 1044 #define _USB_DIEPTXF1_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */
AnnaBridge 171:3a7713b1edbc 1045 #define _USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */
AnnaBridge 171:3a7713b1edbc 1046 #define _USB_DIEPTXF1_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF1 */
AnnaBridge 171:3a7713b1edbc 1047 #define USB_DIEPTXF1_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF1 */
AnnaBridge 171:3a7713b1edbc 1048
AnnaBridge 171:3a7713b1edbc 1049 /* Bit fields for USB DIEPTXF2 */
AnnaBridge 171:3a7713b1edbc 1050 #define _USB_DIEPTXF2_RESETVALUE 0x02000600UL /**< Default value for USB_DIEPTXF2 */
AnnaBridge 171:3a7713b1edbc 1051 #define _USB_DIEPTXF2_MASK 0x03FF07FFUL /**< Mask for USB_DIEPTXF2 */
AnnaBridge 171:3a7713b1edbc 1052 #define _USB_DIEPTXF2_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1053 #define _USB_DIEPTXF2_INEPNTXFSTADDR_MASK 0x7FFUL /**< Bit mask for USB_INEPNTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1054 #define _USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT 0x00000600UL /**< Mode DEFAULT for USB_DIEPTXF2 */
AnnaBridge 171:3a7713b1edbc 1055 #define USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF2 */
AnnaBridge 171:3a7713b1edbc 1056 #define _USB_DIEPTXF2_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */
AnnaBridge 171:3a7713b1edbc 1057 #define _USB_DIEPTXF2_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */
AnnaBridge 171:3a7713b1edbc 1058 #define _USB_DIEPTXF2_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF2 */
AnnaBridge 171:3a7713b1edbc 1059 #define USB_DIEPTXF2_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF2 */
AnnaBridge 171:3a7713b1edbc 1060
AnnaBridge 171:3a7713b1edbc 1061 /* Bit fields for USB DIEPTXF3 */
AnnaBridge 171:3a7713b1edbc 1062 #define _USB_DIEPTXF3_RESETVALUE 0x02000800UL /**< Default value for USB_DIEPTXF3 */
AnnaBridge 171:3a7713b1edbc 1063 #define _USB_DIEPTXF3_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF3 */
AnnaBridge 171:3a7713b1edbc 1064 #define _USB_DIEPTXF3_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1065 #define _USB_DIEPTXF3_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1066 #define _USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT 0x00000800UL /**< Mode DEFAULT for USB_DIEPTXF3 */
AnnaBridge 171:3a7713b1edbc 1067 #define USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF3 */
AnnaBridge 171:3a7713b1edbc 1068 #define _USB_DIEPTXF3_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */
AnnaBridge 171:3a7713b1edbc 1069 #define _USB_DIEPTXF3_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */
AnnaBridge 171:3a7713b1edbc 1070 #define _USB_DIEPTXF3_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF3 */
AnnaBridge 171:3a7713b1edbc 1071 #define USB_DIEPTXF3_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF3 */
AnnaBridge 171:3a7713b1edbc 1072
AnnaBridge 171:3a7713b1edbc 1073 /* Bit fields for USB DIEPTXF4 */
AnnaBridge 171:3a7713b1edbc 1074 #define _USB_DIEPTXF4_RESETVALUE 0x02000A00UL /**< Default value for USB_DIEPTXF4 */
AnnaBridge 171:3a7713b1edbc 1075 #define _USB_DIEPTXF4_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF4 */
AnnaBridge 171:3a7713b1edbc 1076 #define _USB_DIEPTXF4_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1077 #define _USB_DIEPTXF4_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1078 #define _USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT 0x00000A00UL /**< Mode DEFAULT for USB_DIEPTXF4 */
AnnaBridge 171:3a7713b1edbc 1079 #define USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF4 */
AnnaBridge 171:3a7713b1edbc 1080 #define _USB_DIEPTXF4_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */
AnnaBridge 171:3a7713b1edbc 1081 #define _USB_DIEPTXF4_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */
AnnaBridge 171:3a7713b1edbc 1082 #define _USB_DIEPTXF4_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF4 */
AnnaBridge 171:3a7713b1edbc 1083 #define USB_DIEPTXF4_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF4 */
AnnaBridge 171:3a7713b1edbc 1084
AnnaBridge 171:3a7713b1edbc 1085 /* Bit fields for USB DIEPTXF5 */
AnnaBridge 171:3a7713b1edbc 1086 #define _USB_DIEPTXF5_RESETVALUE 0x02000C00UL /**< Default value for USB_DIEPTXF5 */
AnnaBridge 171:3a7713b1edbc 1087 #define _USB_DIEPTXF5_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF5 */
AnnaBridge 171:3a7713b1edbc 1088 #define _USB_DIEPTXF5_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1089 #define _USB_DIEPTXF5_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1090 #define _USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT 0x00000C00UL /**< Mode DEFAULT for USB_DIEPTXF5 */
AnnaBridge 171:3a7713b1edbc 1091 #define USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF5 */
AnnaBridge 171:3a7713b1edbc 1092 #define _USB_DIEPTXF5_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */
AnnaBridge 171:3a7713b1edbc 1093 #define _USB_DIEPTXF5_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */
AnnaBridge 171:3a7713b1edbc 1094 #define _USB_DIEPTXF5_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF5 */
AnnaBridge 171:3a7713b1edbc 1095 #define USB_DIEPTXF5_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF5 */
AnnaBridge 171:3a7713b1edbc 1096
AnnaBridge 171:3a7713b1edbc 1097 /* Bit fields for USB DIEPTXF6 */
AnnaBridge 171:3a7713b1edbc 1098 #define _USB_DIEPTXF6_RESETVALUE 0x02000E00UL /**< Default value for USB_DIEPTXF6 */
AnnaBridge 171:3a7713b1edbc 1099 #define _USB_DIEPTXF6_MASK 0x03FF0FFFUL /**< Mask for USB_DIEPTXF6 */
AnnaBridge 171:3a7713b1edbc 1100 #define _USB_DIEPTXF6_INEPNTXFSTADDR_SHIFT 0 /**< Shift value for USB_INEPNTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1101 #define _USB_DIEPTXF6_INEPNTXFSTADDR_MASK 0xFFFUL /**< Bit mask for USB_INEPNTXFSTADDR */
AnnaBridge 171:3a7713b1edbc 1102 #define _USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT 0x00000E00UL /**< Mode DEFAULT for USB_DIEPTXF6 */
AnnaBridge 171:3a7713b1edbc 1103 #define USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT (_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPTXF6 */
AnnaBridge 171:3a7713b1edbc 1104 #define _USB_DIEPTXF6_INEPNTXFDEP_SHIFT 16 /**< Shift value for USB_INEPNTXFDEP */
AnnaBridge 171:3a7713b1edbc 1105 #define _USB_DIEPTXF6_INEPNTXFDEP_MASK 0x3FF0000UL /**< Bit mask for USB_INEPNTXFDEP */
AnnaBridge 171:3a7713b1edbc 1106 #define _USB_DIEPTXF6_INEPNTXFDEP_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEPTXF6 */
AnnaBridge 171:3a7713b1edbc 1107 #define USB_DIEPTXF6_INEPNTXFDEP_DEFAULT (_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEPTXF6 */
AnnaBridge 171:3a7713b1edbc 1108
AnnaBridge 171:3a7713b1edbc 1109 /* Bit fields for USB HCFG */
AnnaBridge 171:3a7713b1edbc 1110 #define _USB_HCFG_RESETVALUE 0x00200000UL /**< Default value for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1111 #define _USB_HCFG_MASK 0x8000FF87UL /**< Mask for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1112 #define _USB_HCFG_FSLSPCLKSEL_SHIFT 0 /**< Shift value for USB_FSLSPCLKSEL */
AnnaBridge 171:3a7713b1edbc 1113 #define _USB_HCFG_FSLSPCLKSEL_MASK 0x3UL /**< Bit mask for USB_FSLSPCLKSEL */
AnnaBridge 171:3a7713b1edbc 1114 #define _USB_HCFG_FSLSPCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1115 #define _USB_HCFG_FSLSPCLKSEL_DIV1 0x00000001UL /**< Mode DIV1 for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1116 #define _USB_HCFG_FSLSPCLKSEL_DIV8 0x00000002UL /**< Mode DIV8 for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1117 #define USB_HCFG_FSLSPCLKSEL_DEFAULT (_USB_HCFG_FSLSPCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1118 #define USB_HCFG_FSLSPCLKSEL_DIV1 (_USB_HCFG_FSLSPCLKSEL_DIV1 << 0) /**< Shifted mode DIV1 for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1119 #define USB_HCFG_FSLSPCLKSEL_DIV8 (_USB_HCFG_FSLSPCLKSEL_DIV8 << 0) /**< Shifted mode DIV8 for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1120 #define USB_HCFG_FSLSSUPP (0x1UL << 2) /**< FS- and LS-Only Support */
AnnaBridge 171:3a7713b1edbc 1121 #define _USB_HCFG_FSLSSUPP_SHIFT 2 /**< Shift value for USB_FSLSSUPP */
AnnaBridge 171:3a7713b1edbc 1122 #define _USB_HCFG_FSLSSUPP_MASK 0x4UL /**< Bit mask for USB_FSLSSUPP */
AnnaBridge 171:3a7713b1edbc 1123 #define _USB_HCFG_FSLSSUPP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1124 #define _USB_HCFG_FSLSSUPP_HSFSLS 0x00000000UL /**< Mode HSFSLS for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1125 #define _USB_HCFG_FSLSSUPP_FSLS 0x00000001UL /**< Mode FSLS for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1126 #define USB_HCFG_FSLSSUPP_DEFAULT (_USB_HCFG_FSLSSUPP_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1127 #define USB_HCFG_FSLSSUPP_HSFSLS (_USB_HCFG_FSLSSUPP_HSFSLS << 2) /**< Shifted mode HSFSLS for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1128 #define USB_HCFG_FSLSSUPP_FSLS (_USB_HCFG_FSLSSUPP_FSLS << 2) /**< Shifted mode FSLS for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1129 #define USB_HCFG_ENA32KHZS (0x1UL << 7) /**< Enable 32 KHz Suspend mode */
AnnaBridge 171:3a7713b1edbc 1130 #define _USB_HCFG_ENA32KHZS_SHIFT 7 /**< Shift value for USB_ENA32KHZS */
AnnaBridge 171:3a7713b1edbc 1131 #define _USB_HCFG_ENA32KHZS_MASK 0x80UL /**< Bit mask for USB_ENA32KHZS */
AnnaBridge 171:3a7713b1edbc 1132 #define _USB_HCFG_ENA32KHZS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1133 #define USB_HCFG_ENA32KHZS_DEFAULT (_USB_HCFG_ENA32KHZS_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1134 #define _USB_HCFG_RESVALID_SHIFT 8 /**< Shift value for USB_RESVALID */
AnnaBridge 171:3a7713b1edbc 1135 #define _USB_HCFG_RESVALID_MASK 0xFF00UL /**< Bit mask for USB_RESVALID */
AnnaBridge 171:3a7713b1edbc 1136 #define _USB_HCFG_RESVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1137 #define USB_HCFG_RESVALID_DEFAULT (_USB_HCFG_RESVALID_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1138 #define USB_HCFG_MODECHTIMEN (0x1UL << 31) /**< Mode Change Time */
AnnaBridge 171:3a7713b1edbc 1139 #define _USB_HCFG_MODECHTIMEN_SHIFT 31 /**< Shift value for USB_MODECHTIMEN */
AnnaBridge 171:3a7713b1edbc 1140 #define _USB_HCFG_MODECHTIMEN_MASK 0x80000000UL /**< Bit mask for USB_MODECHTIMEN */
AnnaBridge 171:3a7713b1edbc 1141 #define _USB_HCFG_MODECHTIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1142 #define USB_HCFG_MODECHTIMEN_DEFAULT (_USB_HCFG_MODECHTIMEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_HCFG */
AnnaBridge 171:3a7713b1edbc 1143
AnnaBridge 171:3a7713b1edbc 1144 /* Bit fields for USB HFIR */
AnnaBridge 171:3a7713b1edbc 1145 #define _USB_HFIR_RESETVALUE 0x000017D7UL /**< Default value for USB_HFIR */
AnnaBridge 171:3a7713b1edbc 1146 #define _USB_HFIR_MASK 0x0001FFFFUL /**< Mask for USB_HFIR */
AnnaBridge 171:3a7713b1edbc 1147 #define _USB_HFIR_FRINT_SHIFT 0 /**< Shift value for USB_FRINT */
AnnaBridge 171:3a7713b1edbc 1148 #define _USB_HFIR_FRINT_MASK 0xFFFFUL /**< Bit mask for USB_FRINT */
AnnaBridge 171:3a7713b1edbc 1149 #define _USB_HFIR_FRINT_DEFAULT 0x000017D7UL /**< Mode DEFAULT for USB_HFIR */
AnnaBridge 171:3a7713b1edbc 1150 #define USB_HFIR_FRINT_DEFAULT (_USB_HFIR_FRINT_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HFIR */
AnnaBridge 171:3a7713b1edbc 1151 #define USB_HFIR_HFIRRLDCTRL (0x1UL << 16) /**< Reload Control */
AnnaBridge 171:3a7713b1edbc 1152 #define _USB_HFIR_HFIRRLDCTRL_SHIFT 16 /**< Shift value for USB_HFIRRLDCTRL */
AnnaBridge 171:3a7713b1edbc 1153 #define _USB_HFIR_HFIRRLDCTRL_MASK 0x10000UL /**< Bit mask for USB_HFIRRLDCTRL */
AnnaBridge 171:3a7713b1edbc 1154 #define _USB_HFIR_HFIRRLDCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HFIR */
AnnaBridge 171:3a7713b1edbc 1155 #define _USB_HFIR_HFIRRLDCTRL_STATIC 0x00000000UL /**< Mode STATIC for USB_HFIR */
AnnaBridge 171:3a7713b1edbc 1156 #define _USB_HFIR_HFIRRLDCTRL_DYNAMIC 0x00000001UL /**< Mode DYNAMIC for USB_HFIR */
AnnaBridge 171:3a7713b1edbc 1157 #define USB_HFIR_HFIRRLDCTRL_DEFAULT (_USB_HFIR_HFIRRLDCTRL_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HFIR */
AnnaBridge 171:3a7713b1edbc 1158 #define USB_HFIR_HFIRRLDCTRL_STATIC (_USB_HFIR_HFIRRLDCTRL_STATIC << 16) /**< Shifted mode STATIC for USB_HFIR */
AnnaBridge 171:3a7713b1edbc 1159 #define USB_HFIR_HFIRRLDCTRL_DYNAMIC (_USB_HFIR_HFIRRLDCTRL_DYNAMIC << 16) /**< Shifted mode DYNAMIC for USB_HFIR */
AnnaBridge 171:3a7713b1edbc 1160
AnnaBridge 171:3a7713b1edbc 1161 /* Bit fields for USB HFNUM */
AnnaBridge 171:3a7713b1edbc 1162 #define _USB_HFNUM_RESETVALUE 0x00003FFFUL /**< Default value for USB_HFNUM */
AnnaBridge 171:3a7713b1edbc 1163 #define _USB_HFNUM_MASK 0xFFFFFFFFUL /**< Mask for USB_HFNUM */
AnnaBridge 171:3a7713b1edbc 1164 #define _USB_HFNUM_FRNUM_SHIFT 0 /**< Shift value for USB_FRNUM */
AnnaBridge 171:3a7713b1edbc 1165 #define _USB_HFNUM_FRNUM_MASK 0xFFFFUL /**< Bit mask for USB_FRNUM */
AnnaBridge 171:3a7713b1edbc 1166 #define _USB_HFNUM_FRNUM_DEFAULT 0x00003FFFUL /**< Mode DEFAULT for USB_HFNUM */
AnnaBridge 171:3a7713b1edbc 1167 #define USB_HFNUM_FRNUM_DEFAULT (_USB_HFNUM_FRNUM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HFNUM */
AnnaBridge 171:3a7713b1edbc 1168 #define _USB_HFNUM_FRREM_SHIFT 16 /**< Shift value for USB_FRREM */
AnnaBridge 171:3a7713b1edbc 1169 #define _USB_HFNUM_FRREM_MASK 0xFFFF0000UL /**< Bit mask for USB_FRREM */
AnnaBridge 171:3a7713b1edbc 1170 #define _USB_HFNUM_FRREM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HFNUM */
AnnaBridge 171:3a7713b1edbc 1171 #define USB_HFNUM_FRREM_DEFAULT (_USB_HFNUM_FRREM_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HFNUM */
AnnaBridge 171:3a7713b1edbc 1172
AnnaBridge 171:3a7713b1edbc 1173 /* Bit fields for USB HPTXSTS */
AnnaBridge 171:3a7713b1edbc 1174 #define _USB_HPTXSTS_RESETVALUE 0x00080200UL /**< Default value for USB_HPTXSTS */
AnnaBridge 171:3a7713b1edbc 1175 #define _USB_HPTXSTS_MASK 0xFFFFFFFFUL /**< Mask for USB_HPTXSTS */
AnnaBridge 171:3a7713b1edbc 1176 #define _USB_HPTXSTS_PTXFSPCAVAIL_SHIFT 0 /**< Shift value for USB_PTXFSPCAVAIL */
AnnaBridge 171:3a7713b1edbc 1177 #define _USB_HPTXSTS_PTXFSPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_PTXFSPCAVAIL */
AnnaBridge 171:3a7713b1edbc 1178 #define _USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_HPTXSTS */
AnnaBridge 171:3a7713b1edbc 1179 #define USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT (_USB_HPTXSTS_PTXFSPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HPTXSTS */
AnnaBridge 171:3a7713b1edbc 1180 #define _USB_HPTXSTS_PTXQSPCAVAIL_SHIFT 16 /**< Shift value for USB_PTXQSPCAVAIL */
AnnaBridge 171:3a7713b1edbc 1181 #define _USB_HPTXSTS_PTXQSPCAVAIL_MASK 0xFF0000UL /**< Bit mask for USB_PTXQSPCAVAIL */
AnnaBridge 171:3a7713b1edbc 1182 #define _USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT 0x00000008UL /**< Mode DEFAULT for USB_HPTXSTS */
AnnaBridge 171:3a7713b1edbc 1183 #define USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT (_USB_HPTXSTS_PTXQSPCAVAIL_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_HPTXSTS */
AnnaBridge 171:3a7713b1edbc 1184 #define _USB_HPTXSTS_PTXQTOP_SHIFT 24 /**< Shift value for USB_PTXQTOP */
AnnaBridge 171:3a7713b1edbc 1185 #define _USB_HPTXSTS_PTXQTOP_MASK 0xFF000000UL /**< Bit mask for USB_PTXQTOP */
AnnaBridge 171:3a7713b1edbc 1186 #define _USB_HPTXSTS_PTXQTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPTXSTS */
AnnaBridge 171:3a7713b1edbc 1187 #define USB_HPTXSTS_PTXQTOP_DEFAULT (_USB_HPTXSTS_PTXQTOP_DEFAULT << 24) /**< Shifted mode DEFAULT for USB_HPTXSTS */
AnnaBridge 171:3a7713b1edbc 1188
AnnaBridge 171:3a7713b1edbc 1189 /* Bit fields for USB HAINT */
AnnaBridge 171:3a7713b1edbc 1190 #define _USB_HAINT_RESETVALUE 0x00000000UL /**< Default value for USB_HAINT */
AnnaBridge 171:3a7713b1edbc 1191 #define _USB_HAINT_MASK 0x00003FFFUL /**< Mask for USB_HAINT */
AnnaBridge 171:3a7713b1edbc 1192 #define _USB_HAINT_HAINT_SHIFT 0 /**< Shift value for USB_HAINT */
AnnaBridge 171:3a7713b1edbc 1193 #define _USB_HAINT_HAINT_MASK 0x3FFFUL /**< Bit mask for USB_HAINT */
AnnaBridge 171:3a7713b1edbc 1194 #define _USB_HAINT_HAINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HAINT */
AnnaBridge 171:3a7713b1edbc 1195 #define USB_HAINT_HAINT_DEFAULT (_USB_HAINT_HAINT_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HAINT */
AnnaBridge 171:3a7713b1edbc 1196
AnnaBridge 171:3a7713b1edbc 1197 /* Bit fields for USB HAINTMSK */
AnnaBridge 171:3a7713b1edbc 1198 #define _USB_HAINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_HAINTMSK */
AnnaBridge 171:3a7713b1edbc 1199 #define _USB_HAINTMSK_MASK 0x00003FFFUL /**< Mask for USB_HAINTMSK */
AnnaBridge 171:3a7713b1edbc 1200 #define _USB_HAINTMSK_HAINTMSK_SHIFT 0 /**< Shift value for USB_HAINTMSK */
AnnaBridge 171:3a7713b1edbc 1201 #define _USB_HAINTMSK_HAINTMSK_MASK 0x3FFFUL /**< Bit mask for USB_HAINTMSK */
AnnaBridge 171:3a7713b1edbc 1202 #define _USB_HAINTMSK_HAINTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HAINTMSK */
AnnaBridge 171:3a7713b1edbc 1203 #define USB_HAINTMSK_HAINTMSK_DEFAULT (_USB_HAINTMSK_HAINTMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HAINTMSK */
AnnaBridge 171:3a7713b1edbc 1204
AnnaBridge 171:3a7713b1edbc 1205 /* Bit fields for USB HPRT */
AnnaBridge 171:3a7713b1edbc 1206 #define _USB_HPRT_RESETVALUE 0x00000000UL /**< Default value for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1207 #define _USB_HPRT_MASK 0x0007FDFFUL /**< Mask for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1208 #define USB_HPRT_PRTCONNSTS (0x1UL << 0) /**< Port Connect Status */
AnnaBridge 171:3a7713b1edbc 1209 #define _USB_HPRT_PRTCONNSTS_SHIFT 0 /**< Shift value for USB_PRTCONNSTS */
AnnaBridge 171:3a7713b1edbc 1210 #define _USB_HPRT_PRTCONNSTS_MASK 0x1UL /**< Bit mask for USB_PRTCONNSTS */
AnnaBridge 171:3a7713b1edbc 1211 #define _USB_HPRT_PRTCONNSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1212 #define USB_HPRT_PRTCONNSTS_DEFAULT (_USB_HPRT_PRTCONNSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1213 #define USB_HPRT_PRTCONNDET (0x1UL << 1) /**< Port Connect Detected */
AnnaBridge 171:3a7713b1edbc 1214 #define _USB_HPRT_PRTCONNDET_SHIFT 1 /**< Shift value for USB_PRTCONNDET */
AnnaBridge 171:3a7713b1edbc 1215 #define _USB_HPRT_PRTCONNDET_MASK 0x2UL /**< Bit mask for USB_PRTCONNDET */
AnnaBridge 171:3a7713b1edbc 1216 #define _USB_HPRT_PRTCONNDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1217 #define USB_HPRT_PRTCONNDET_DEFAULT (_USB_HPRT_PRTCONNDET_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1218 #define USB_HPRT_PRTENA (0x1UL << 2) /**< Port Enable */
AnnaBridge 171:3a7713b1edbc 1219 #define _USB_HPRT_PRTENA_SHIFT 2 /**< Shift value for USB_PRTENA */
AnnaBridge 171:3a7713b1edbc 1220 #define _USB_HPRT_PRTENA_MASK 0x4UL /**< Bit mask for USB_PRTENA */
AnnaBridge 171:3a7713b1edbc 1221 #define _USB_HPRT_PRTENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1222 #define USB_HPRT_PRTENA_DEFAULT (_USB_HPRT_PRTENA_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1223 #define USB_HPRT_PRTENCHNG (0x1UL << 3) /**< Port Enable/Disable Change */
AnnaBridge 171:3a7713b1edbc 1224 #define _USB_HPRT_PRTENCHNG_SHIFT 3 /**< Shift value for USB_PRTENCHNG */
AnnaBridge 171:3a7713b1edbc 1225 #define _USB_HPRT_PRTENCHNG_MASK 0x8UL /**< Bit mask for USB_PRTENCHNG */
AnnaBridge 171:3a7713b1edbc 1226 #define _USB_HPRT_PRTENCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1227 #define USB_HPRT_PRTENCHNG_DEFAULT (_USB_HPRT_PRTENCHNG_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1228 #define USB_HPRT_PRTOVRCURRACT (0x1UL << 4) /**< Port Overcurrent Active */
AnnaBridge 171:3a7713b1edbc 1229 #define _USB_HPRT_PRTOVRCURRACT_SHIFT 4 /**< Shift value for USB_PRTOVRCURRACT */
AnnaBridge 171:3a7713b1edbc 1230 #define _USB_HPRT_PRTOVRCURRACT_MASK 0x10UL /**< Bit mask for USB_PRTOVRCURRACT */
AnnaBridge 171:3a7713b1edbc 1231 #define _USB_HPRT_PRTOVRCURRACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1232 #define USB_HPRT_PRTOVRCURRACT_DEFAULT (_USB_HPRT_PRTOVRCURRACT_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1233 #define USB_HPRT_PRTOVRCURRCHNG (0x1UL << 5) /**< Port Overcurrent Change */
AnnaBridge 171:3a7713b1edbc 1234 #define _USB_HPRT_PRTOVRCURRCHNG_SHIFT 5 /**< Shift value for USB_PRTOVRCURRCHNG */
AnnaBridge 171:3a7713b1edbc 1235 #define _USB_HPRT_PRTOVRCURRCHNG_MASK 0x20UL /**< Bit mask for USB_PRTOVRCURRCHNG */
AnnaBridge 171:3a7713b1edbc 1236 #define _USB_HPRT_PRTOVRCURRCHNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1237 #define USB_HPRT_PRTOVRCURRCHNG_DEFAULT (_USB_HPRT_PRTOVRCURRCHNG_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1238 #define USB_HPRT_PRTRES (0x1UL << 6) /**< Port Resume */
AnnaBridge 171:3a7713b1edbc 1239 #define _USB_HPRT_PRTRES_SHIFT 6 /**< Shift value for USB_PRTRES */
AnnaBridge 171:3a7713b1edbc 1240 #define _USB_HPRT_PRTRES_MASK 0x40UL /**< Bit mask for USB_PRTRES */
AnnaBridge 171:3a7713b1edbc 1241 #define _USB_HPRT_PRTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1242 #define USB_HPRT_PRTRES_DEFAULT (_USB_HPRT_PRTRES_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1243 #define USB_HPRT_PRTSUSP (0x1UL << 7) /**< Port Suspend */
AnnaBridge 171:3a7713b1edbc 1244 #define _USB_HPRT_PRTSUSP_SHIFT 7 /**< Shift value for USB_PRTSUSP */
AnnaBridge 171:3a7713b1edbc 1245 #define _USB_HPRT_PRTSUSP_MASK 0x80UL /**< Bit mask for USB_PRTSUSP */
AnnaBridge 171:3a7713b1edbc 1246 #define _USB_HPRT_PRTSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1247 #define USB_HPRT_PRTSUSP_DEFAULT (_USB_HPRT_PRTSUSP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1248 #define USB_HPRT_PRTRST (0x1UL << 8) /**< Port Reset */
AnnaBridge 171:3a7713b1edbc 1249 #define _USB_HPRT_PRTRST_SHIFT 8 /**< Shift value for USB_PRTRST */
AnnaBridge 171:3a7713b1edbc 1250 #define _USB_HPRT_PRTRST_MASK 0x100UL /**< Bit mask for USB_PRTRST */
AnnaBridge 171:3a7713b1edbc 1251 #define _USB_HPRT_PRTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1252 #define USB_HPRT_PRTRST_DEFAULT (_USB_HPRT_PRTRST_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1253 #define _USB_HPRT_PRTLNSTS_SHIFT 10 /**< Shift value for USB_PRTLNSTS */
AnnaBridge 171:3a7713b1edbc 1254 #define _USB_HPRT_PRTLNSTS_MASK 0xC00UL /**< Bit mask for USB_PRTLNSTS */
AnnaBridge 171:3a7713b1edbc 1255 #define _USB_HPRT_PRTLNSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1256 #define USB_HPRT_PRTLNSTS_DEFAULT (_USB_HPRT_PRTLNSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1257 #define USB_HPRT_PRTPWR (0x1UL << 12) /**< Port Power */
AnnaBridge 171:3a7713b1edbc 1258 #define _USB_HPRT_PRTPWR_SHIFT 12 /**< Shift value for USB_PRTPWR */
AnnaBridge 171:3a7713b1edbc 1259 #define _USB_HPRT_PRTPWR_MASK 0x1000UL /**< Bit mask for USB_PRTPWR */
AnnaBridge 171:3a7713b1edbc 1260 #define _USB_HPRT_PRTPWR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1261 #define _USB_HPRT_PRTPWR_OFF 0x00000000UL /**< Mode OFF for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1262 #define _USB_HPRT_PRTPWR_ON 0x00000001UL /**< Mode ON for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1263 #define USB_HPRT_PRTPWR_DEFAULT (_USB_HPRT_PRTPWR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1264 #define USB_HPRT_PRTPWR_OFF (_USB_HPRT_PRTPWR_OFF << 12) /**< Shifted mode OFF for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1265 #define USB_HPRT_PRTPWR_ON (_USB_HPRT_PRTPWR_ON << 12) /**< Shifted mode ON for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1266 #define _USB_HPRT_PRTTSTCTL_SHIFT 13 /**< Shift value for USB_PRTTSTCTL */
AnnaBridge 171:3a7713b1edbc 1267 #define _USB_HPRT_PRTTSTCTL_MASK 0x1E000UL /**< Bit mask for USB_PRTTSTCTL */
AnnaBridge 171:3a7713b1edbc 1268 #define _USB_HPRT_PRTTSTCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1269 #define _USB_HPRT_PRTTSTCTL_DISABLE 0x00000000UL /**< Mode DISABLE for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1270 #define _USB_HPRT_PRTTSTCTL_J 0x00000001UL /**< Mode J for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1271 #define _USB_HPRT_PRTTSTCTL_K 0x00000002UL /**< Mode K for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1272 #define _USB_HPRT_PRTTSTCTL_SE0NAK 0x00000003UL /**< Mode SE0NAK for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1273 #define _USB_HPRT_PRTTSTCTL_PACKET 0x00000004UL /**< Mode PACKET for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1274 #define _USB_HPRT_PRTTSTCTL_FORCE 0x00000005UL /**< Mode FORCE for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1275 #define USB_HPRT_PRTTSTCTL_DEFAULT (_USB_HPRT_PRTTSTCTL_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1276 #define USB_HPRT_PRTTSTCTL_DISABLE (_USB_HPRT_PRTTSTCTL_DISABLE << 13) /**< Shifted mode DISABLE for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1277 #define USB_HPRT_PRTTSTCTL_J (_USB_HPRT_PRTTSTCTL_J << 13) /**< Shifted mode J for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1278 #define USB_HPRT_PRTTSTCTL_K (_USB_HPRT_PRTTSTCTL_K << 13) /**< Shifted mode K for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1279 #define USB_HPRT_PRTTSTCTL_SE0NAK (_USB_HPRT_PRTTSTCTL_SE0NAK << 13) /**< Shifted mode SE0NAK for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1280 #define USB_HPRT_PRTTSTCTL_PACKET (_USB_HPRT_PRTTSTCTL_PACKET << 13) /**< Shifted mode PACKET for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1281 #define USB_HPRT_PRTTSTCTL_FORCE (_USB_HPRT_PRTTSTCTL_FORCE << 13) /**< Shifted mode FORCE for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1282 #define _USB_HPRT_PRTSPD_SHIFT 17 /**< Shift value for USB_PRTSPD */
AnnaBridge 171:3a7713b1edbc 1283 #define _USB_HPRT_PRTSPD_MASK 0x60000UL /**< Bit mask for USB_PRTSPD */
AnnaBridge 171:3a7713b1edbc 1284 #define _USB_HPRT_PRTSPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1285 #define _USB_HPRT_PRTSPD_HS 0x00000000UL /**< Mode HS for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1286 #define _USB_HPRT_PRTSPD_FS 0x00000001UL /**< Mode FS for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1287 #define _USB_HPRT_PRTSPD_LS 0x00000002UL /**< Mode LS for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1288 #define USB_HPRT_PRTSPD_DEFAULT (_USB_HPRT_PRTSPD_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1289 #define USB_HPRT_PRTSPD_HS (_USB_HPRT_PRTSPD_HS << 17) /**< Shifted mode HS for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1290 #define USB_HPRT_PRTSPD_FS (_USB_HPRT_PRTSPD_FS << 17) /**< Shifted mode FS for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1291 #define USB_HPRT_PRTSPD_LS (_USB_HPRT_PRTSPD_LS << 17) /**< Shifted mode LS for USB_HPRT */
AnnaBridge 171:3a7713b1edbc 1292
AnnaBridge 171:3a7713b1edbc 1293 /* Bit fields for USB HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1294 #define _USB_HC_CHAR_RESETVALUE 0x00000000UL /**< Default value for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1295 #define _USB_HC_CHAR_MASK 0xFFFEFFFFUL /**< Mask for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1296 #define _USB_HC_CHAR_MPS_SHIFT 0 /**< Shift value for USB_MPS */
AnnaBridge 171:3a7713b1edbc 1297 #define _USB_HC_CHAR_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */
AnnaBridge 171:3a7713b1edbc 1298 #define _USB_HC_CHAR_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1299 #define USB_HC_CHAR_MPS_DEFAULT (_USB_HC_CHAR_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1300 #define _USB_HC_CHAR_EPNUM_SHIFT 11 /**< Shift value for USB_EPNUM */
AnnaBridge 171:3a7713b1edbc 1301 #define _USB_HC_CHAR_EPNUM_MASK 0x7800UL /**< Bit mask for USB_EPNUM */
AnnaBridge 171:3a7713b1edbc 1302 #define _USB_HC_CHAR_EPNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1303 #define USB_HC_CHAR_EPNUM_DEFAULT (_USB_HC_CHAR_EPNUM_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1304 #define USB_HC_CHAR_EPDIR (0x1UL << 15) /**< Endpoint Direction */
AnnaBridge 171:3a7713b1edbc 1305 #define _USB_HC_CHAR_EPDIR_SHIFT 15 /**< Shift value for USB_EPDIR */
AnnaBridge 171:3a7713b1edbc 1306 #define _USB_HC_CHAR_EPDIR_MASK 0x8000UL /**< Bit mask for USB_EPDIR */
AnnaBridge 171:3a7713b1edbc 1307 #define _USB_HC_CHAR_EPDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1308 #define _USB_HC_CHAR_EPDIR_OUT 0x00000000UL /**< Mode OUT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1309 #define _USB_HC_CHAR_EPDIR_IN 0x00000001UL /**< Mode IN for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1310 #define USB_HC_CHAR_EPDIR_DEFAULT (_USB_HC_CHAR_EPDIR_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1311 #define USB_HC_CHAR_EPDIR_OUT (_USB_HC_CHAR_EPDIR_OUT << 15) /**< Shifted mode OUT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1312 #define USB_HC_CHAR_EPDIR_IN (_USB_HC_CHAR_EPDIR_IN << 15) /**< Shifted mode IN for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1313 #define USB_HC_CHAR_LSPDDEV (0x1UL << 17) /**< Low-Speed Device */
AnnaBridge 171:3a7713b1edbc 1314 #define _USB_HC_CHAR_LSPDDEV_SHIFT 17 /**< Shift value for USB_LSPDDEV */
AnnaBridge 171:3a7713b1edbc 1315 #define _USB_HC_CHAR_LSPDDEV_MASK 0x20000UL /**< Bit mask for USB_LSPDDEV */
AnnaBridge 171:3a7713b1edbc 1316 #define _USB_HC_CHAR_LSPDDEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1317 #define USB_HC_CHAR_LSPDDEV_DEFAULT (_USB_HC_CHAR_LSPDDEV_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1318 #define _USB_HC_CHAR_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */
AnnaBridge 171:3a7713b1edbc 1319 #define _USB_HC_CHAR_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */
AnnaBridge 171:3a7713b1edbc 1320 #define _USB_HC_CHAR_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1321 #define _USB_HC_CHAR_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1322 #define _USB_HC_CHAR_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1323 #define _USB_HC_CHAR_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1324 #define _USB_HC_CHAR_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1325 #define USB_HC_CHAR_EPTYPE_DEFAULT (_USB_HC_CHAR_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1326 #define USB_HC_CHAR_EPTYPE_CONTROL (_USB_HC_CHAR_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1327 #define USB_HC_CHAR_EPTYPE_ISO (_USB_HC_CHAR_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1328 #define USB_HC_CHAR_EPTYPE_BULK (_USB_HC_CHAR_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1329 #define USB_HC_CHAR_EPTYPE_INT (_USB_HC_CHAR_EPTYPE_INT << 18) /**< Shifted mode INT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1330 #define _USB_HC_CHAR_MC_SHIFT 20 /**< Shift value for USB_MC */
AnnaBridge 171:3a7713b1edbc 1331 #define _USB_HC_CHAR_MC_MASK 0x300000UL /**< Bit mask for USB_MC */
AnnaBridge 171:3a7713b1edbc 1332 #define _USB_HC_CHAR_MC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1333 #define USB_HC_CHAR_MC_DEFAULT (_USB_HC_CHAR_MC_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1334 #define _USB_HC_CHAR_DEVADDR_SHIFT 22 /**< Shift value for USB_DEVADDR */
AnnaBridge 171:3a7713b1edbc 1335 #define _USB_HC_CHAR_DEVADDR_MASK 0x1FC00000UL /**< Bit mask for USB_DEVADDR */
AnnaBridge 171:3a7713b1edbc 1336 #define _USB_HC_CHAR_DEVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1337 #define USB_HC_CHAR_DEVADDR_DEFAULT (_USB_HC_CHAR_DEVADDR_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1338 #define USB_HC_CHAR_ODDFRM (0x1UL << 29) /**< Odd Frame */
AnnaBridge 171:3a7713b1edbc 1339 #define _USB_HC_CHAR_ODDFRM_SHIFT 29 /**< Shift value for USB_ODDFRM */
AnnaBridge 171:3a7713b1edbc 1340 #define _USB_HC_CHAR_ODDFRM_MASK 0x20000000UL /**< Bit mask for USB_ODDFRM */
AnnaBridge 171:3a7713b1edbc 1341 #define _USB_HC_CHAR_ODDFRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1342 #define USB_HC_CHAR_ODDFRM_DEFAULT (_USB_HC_CHAR_ODDFRM_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1343 #define USB_HC_CHAR_CHDIS (0x1UL << 30) /**< Channel Disable */
AnnaBridge 171:3a7713b1edbc 1344 #define _USB_HC_CHAR_CHDIS_SHIFT 30 /**< Shift value for USB_CHDIS */
AnnaBridge 171:3a7713b1edbc 1345 #define _USB_HC_CHAR_CHDIS_MASK 0x40000000UL /**< Bit mask for USB_CHDIS */
AnnaBridge 171:3a7713b1edbc 1346 #define _USB_HC_CHAR_CHDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1347 #define USB_HC_CHAR_CHDIS_DEFAULT (_USB_HC_CHAR_CHDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1348 #define USB_HC_CHAR_CHENA (0x1UL << 31) /**< Channel Enable */
AnnaBridge 171:3a7713b1edbc 1349 #define _USB_HC_CHAR_CHENA_SHIFT 31 /**< Shift value for USB_CHENA */
AnnaBridge 171:3a7713b1edbc 1350 #define _USB_HC_CHAR_CHENA_MASK 0x80000000UL /**< Bit mask for USB_CHENA */
AnnaBridge 171:3a7713b1edbc 1351 #define _USB_HC_CHAR_CHENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1352 #define USB_HC_CHAR_CHENA_DEFAULT (_USB_HC_CHAR_CHENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_HC_CHAR */
AnnaBridge 171:3a7713b1edbc 1353
AnnaBridge 171:3a7713b1edbc 1354 /* Bit fields for USB HC_INT */
AnnaBridge 171:3a7713b1edbc 1355 #define _USB_HC_INT_RESETVALUE 0x00000000UL /**< Default value for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1356 #define _USB_HC_INT_MASK 0x000007BFUL /**< Mask for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1357 #define USB_HC_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed */
AnnaBridge 171:3a7713b1edbc 1358 #define _USB_HC_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */
AnnaBridge 171:3a7713b1edbc 1359 #define _USB_HC_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */
AnnaBridge 171:3a7713b1edbc 1360 #define _USB_HC_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1361 #define USB_HC_INT_XFERCOMPL_DEFAULT (_USB_HC_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1362 #define USB_HC_INT_CHHLTD (0x1UL << 1) /**< Channel Halted */
AnnaBridge 171:3a7713b1edbc 1363 #define _USB_HC_INT_CHHLTD_SHIFT 1 /**< Shift value for USB_CHHLTD */
AnnaBridge 171:3a7713b1edbc 1364 #define _USB_HC_INT_CHHLTD_MASK 0x2UL /**< Bit mask for USB_CHHLTD */
AnnaBridge 171:3a7713b1edbc 1365 #define _USB_HC_INT_CHHLTD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1366 #define USB_HC_INT_CHHLTD_DEFAULT (_USB_HC_INT_CHHLTD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1367 #define USB_HC_INT_AHBERR (0x1UL << 2) /**< AHB Error */
AnnaBridge 171:3a7713b1edbc 1368 #define _USB_HC_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */
AnnaBridge 171:3a7713b1edbc 1369 #define _USB_HC_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */
AnnaBridge 171:3a7713b1edbc 1370 #define _USB_HC_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1371 #define USB_HC_INT_AHBERR_DEFAULT (_USB_HC_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1372 #define USB_HC_INT_STALL (0x1UL << 3) /**< STALL Response Received Interrupt */
AnnaBridge 171:3a7713b1edbc 1373 #define _USB_HC_INT_STALL_SHIFT 3 /**< Shift value for USB_STALL */
AnnaBridge 171:3a7713b1edbc 1374 #define _USB_HC_INT_STALL_MASK 0x8UL /**< Bit mask for USB_STALL */
AnnaBridge 171:3a7713b1edbc 1375 #define _USB_HC_INT_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1376 #define USB_HC_INT_STALL_DEFAULT (_USB_HC_INT_STALL_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1377 #define USB_HC_INT_NAK (0x1UL << 4) /**< NAK Response Received Interrupt */
AnnaBridge 171:3a7713b1edbc 1378 #define _USB_HC_INT_NAK_SHIFT 4 /**< Shift value for USB_NAK */
AnnaBridge 171:3a7713b1edbc 1379 #define _USB_HC_INT_NAK_MASK 0x10UL /**< Bit mask for USB_NAK */
AnnaBridge 171:3a7713b1edbc 1380 #define _USB_HC_INT_NAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1381 #define USB_HC_INT_NAK_DEFAULT (_USB_HC_INT_NAK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1382 #define USB_HC_INT_ACK (0x1UL << 5) /**< ACK Response Received/Transmitted Interrupt */
AnnaBridge 171:3a7713b1edbc 1383 #define _USB_HC_INT_ACK_SHIFT 5 /**< Shift value for USB_ACK */
AnnaBridge 171:3a7713b1edbc 1384 #define _USB_HC_INT_ACK_MASK 0x20UL /**< Bit mask for USB_ACK */
AnnaBridge 171:3a7713b1edbc 1385 #define _USB_HC_INT_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1386 #define USB_HC_INT_ACK_DEFAULT (_USB_HC_INT_ACK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1387 #define USB_HC_INT_XACTERR (0x1UL << 7) /**< Transaction Error */
AnnaBridge 171:3a7713b1edbc 1388 #define _USB_HC_INT_XACTERR_SHIFT 7 /**< Shift value for USB_XACTERR */
AnnaBridge 171:3a7713b1edbc 1389 #define _USB_HC_INT_XACTERR_MASK 0x80UL /**< Bit mask for USB_XACTERR */
AnnaBridge 171:3a7713b1edbc 1390 #define _USB_HC_INT_XACTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1391 #define USB_HC_INT_XACTERR_DEFAULT (_USB_HC_INT_XACTERR_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1392 #define USB_HC_INT_BBLERR (0x1UL << 8) /**< Babble Error */
AnnaBridge 171:3a7713b1edbc 1393 #define _USB_HC_INT_BBLERR_SHIFT 8 /**< Shift value for USB_BBLERR */
AnnaBridge 171:3a7713b1edbc 1394 #define _USB_HC_INT_BBLERR_MASK 0x100UL /**< Bit mask for USB_BBLERR */
AnnaBridge 171:3a7713b1edbc 1395 #define _USB_HC_INT_BBLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1396 #define USB_HC_INT_BBLERR_DEFAULT (_USB_HC_INT_BBLERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1397 #define USB_HC_INT_FRMOVRUN (0x1UL << 9) /**< Frame Overrun */
AnnaBridge 171:3a7713b1edbc 1398 #define _USB_HC_INT_FRMOVRUN_SHIFT 9 /**< Shift value for USB_FRMOVRUN */
AnnaBridge 171:3a7713b1edbc 1399 #define _USB_HC_INT_FRMOVRUN_MASK 0x200UL /**< Bit mask for USB_FRMOVRUN */
AnnaBridge 171:3a7713b1edbc 1400 #define _USB_HC_INT_FRMOVRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1401 #define USB_HC_INT_FRMOVRUN_DEFAULT (_USB_HC_INT_FRMOVRUN_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1402 #define USB_HC_INT_DATATGLERR (0x1UL << 10) /**< Data Toggle Error */
AnnaBridge 171:3a7713b1edbc 1403 #define _USB_HC_INT_DATATGLERR_SHIFT 10 /**< Shift value for USB_DATATGLERR */
AnnaBridge 171:3a7713b1edbc 1404 #define _USB_HC_INT_DATATGLERR_MASK 0x400UL /**< Bit mask for USB_DATATGLERR */
AnnaBridge 171:3a7713b1edbc 1405 #define _USB_HC_INT_DATATGLERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1406 #define USB_HC_INT_DATATGLERR_DEFAULT (_USB_HC_INT_DATATGLERR_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_HC_INT */
AnnaBridge 171:3a7713b1edbc 1407
AnnaBridge 171:3a7713b1edbc 1408 /* Bit fields for USB HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1409 #define _USB_HC_INTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1410 #define _USB_HC_INTMSK_MASK 0x000007BFUL /**< Mask for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1411 #define USB_HC_INTMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Mask */
AnnaBridge 171:3a7713b1edbc 1412 #define _USB_HC_INTMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */
AnnaBridge 171:3a7713b1edbc 1413 #define _USB_HC_INTMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */
AnnaBridge 171:3a7713b1edbc 1414 #define _USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1415 #define USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT (_USB_HC_INTMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1416 #define USB_HC_INTMSK_CHHLTDMSK (0x1UL << 1) /**< Channel Halted Mask */
AnnaBridge 171:3a7713b1edbc 1417 #define _USB_HC_INTMSK_CHHLTDMSK_SHIFT 1 /**< Shift value for USB_CHHLTDMSK */
AnnaBridge 171:3a7713b1edbc 1418 #define _USB_HC_INTMSK_CHHLTDMSK_MASK 0x2UL /**< Bit mask for USB_CHHLTDMSK */
AnnaBridge 171:3a7713b1edbc 1419 #define _USB_HC_INTMSK_CHHLTDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1420 #define USB_HC_INTMSK_CHHLTDMSK_DEFAULT (_USB_HC_INTMSK_CHHLTDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1421 #define USB_HC_INTMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error Mask */
AnnaBridge 171:3a7713b1edbc 1422 #define _USB_HC_INTMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */
AnnaBridge 171:3a7713b1edbc 1423 #define _USB_HC_INTMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */
AnnaBridge 171:3a7713b1edbc 1424 #define _USB_HC_INTMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1425 #define USB_HC_INTMSK_AHBERRMSK_DEFAULT (_USB_HC_INTMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1426 #define USB_HC_INTMSK_STALLMSK (0x1UL << 3) /**< STALL Response Received Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 1427 #define _USB_HC_INTMSK_STALLMSK_SHIFT 3 /**< Shift value for USB_STALLMSK */
AnnaBridge 171:3a7713b1edbc 1428 #define _USB_HC_INTMSK_STALLMSK_MASK 0x8UL /**< Bit mask for USB_STALLMSK */
AnnaBridge 171:3a7713b1edbc 1429 #define _USB_HC_INTMSK_STALLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1430 #define USB_HC_INTMSK_STALLMSK_DEFAULT (_USB_HC_INTMSK_STALLMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1431 #define USB_HC_INTMSK_NAKMSK (0x1UL << 4) /**< NAK Response Received Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 1432 #define _USB_HC_INTMSK_NAKMSK_SHIFT 4 /**< Shift value for USB_NAKMSK */
AnnaBridge 171:3a7713b1edbc 1433 #define _USB_HC_INTMSK_NAKMSK_MASK 0x10UL /**< Bit mask for USB_NAKMSK */
AnnaBridge 171:3a7713b1edbc 1434 #define _USB_HC_INTMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1435 #define USB_HC_INTMSK_NAKMSK_DEFAULT (_USB_HC_INTMSK_NAKMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1436 #define USB_HC_INTMSK_ACKMSK (0x1UL << 5) /**< ACK Response Received/Transmitted Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 1437 #define _USB_HC_INTMSK_ACKMSK_SHIFT 5 /**< Shift value for USB_ACKMSK */
AnnaBridge 171:3a7713b1edbc 1438 #define _USB_HC_INTMSK_ACKMSK_MASK 0x20UL /**< Bit mask for USB_ACKMSK */
AnnaBridge 171:3a7713b1edbc 1439 #define _USB_HC_INTMSK_ACKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1440 #define USB_HC_INTMSK_ACKMSK_DEFAULT (_USB_HC_INTMSK_ACKMSK_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1441 #define USB_HC_INTMSK_XACTERRMSK (0x1UL << 7) /**< Transaction Error Mask */
AnnaBridge 171:3a7713b1edbc 1442 #define _USB_HC_INTMSK_XACTERRMSK_SHIFT 7 /**< Shift value for USB_XACTERRMSK */
AnnaBridge 171:3a7713b1edbc 1443 #define _USB_HC_INTMSK_XACTERRMSK_MASK 0x80UL /**< Bit mask for USB_XACTERRMSK */
AnnaBridge 171:3a7713b1edbc 1444 #define _USB_HC_INTMSK_XACTERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1445 #define USB_HC_INTMSK_XACTERRMSK_DEFAULT (_USB_HC_INTMSK_XACTERRMSK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1446 #define USB_HC_INTMSK_BBLERRMSK (0x1UL << 8) /**< Babble Error Mask */
AnnaBridge 171:3a7713b1edbc 1447 #define _USB_HC_INTMSK_BBLERRMSK_SHIFT 8 /**< Shift value for USB_BBLERRMSK */
AnnaBridge 171:3a7713b1edbc 1448 #define _USB_HC_INTMSK_BBLERRMSK_MASK 0x100UL /**< Bit mask for USB_BBLERRMSK */
AnnaBridge 171:3a7713b1edbc 1449 #define _USB_HC_INTMSK_BBLERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1450 #define USB_HC_INTMSK_BBLERRMSK_DEFAULT (_USB_HC_INTMSK_BBLERRMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1451 #define USB_HC_INTMSK_FRMOVRUNMSK (0x1UL << 9) /**< Frame Overrun Mask */
AnnaBridge 171:3a7713b1edbc 1452 #define _USB_HC_INTMSK_FRMOVRUNMSK_SHIFT 9 /**< Shift value for USB_FRMOVRUNMSK */
AnnaBridge 171:3a7713b1edbc 1453 #define _USB_HC_INTMSK_FRMOVRUNMSK_MASK 0x200UL /**< Bit mask for USB_FRMOVRUNMSK */
AnnaBridge 171:3a7713b1edbc 1454 #define _USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1455 #define USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT (_USB_HC_INTMSK_FRMOVRUNMSK_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1456 #define USB_HC_INTMSK_DATATGLERRMSK (0x1UL << 10) /**< Data Toggle Error Mask */
AnnaBridge 171:3a7713b1edbc 1457 #define _USB_HC_INTMSK_DATATGLERRMSK_SHIFT 10 /**< Shift value for USB_DATATGLERRMSK */
AnnaBridge 171:3a7713b1edbc 1458 #define _USB_HC_INTMSK_DATATGLERRMSK_MASK 0x400UL /**< Bit mask for USB_DATATGLERRMSK */
AnnaBridge 171:3a7713b1edbc 1459 #define _USB_HC_INTMSK_DATATGLERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1460 #define USB_HC_INTMSK_DATATGLERRMSK_DEFAULT (_USB_HC_INTMSK_DATATGLERRMSK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_HC_INTMSK */
AnnaBridge 171:3a7713b1edbc 1461
AnnaBridge 171:3a7713b1edbc 1462 /* Bit fields for USB HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1463 #define _USB_HC_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1464 #define _USB_HC_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1465 #define _USB_HC_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */
AnnaBridge 171:3a7713b1edbc 1466 #define _USB_HC_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */
AnnaBridge 171:3a7713b1edbc 1467 #define _USB_HC_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1468 #define USB_HC_TSIZ_XFERSIZE_DEFAULT (_USB_HC_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1469 #define _USB_HC_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */
AnnaBridge 171:3a7713b1edbc 1470 #define _USB_HC_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */
AnnaBridge 171:3a7713b1edbc 1471 #define _USB_HC_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1472 #define USB_HC_TSIZ_PKTCNT_DEFAULT (_USB_HC_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1473 #define _USB_HC_TSIZ_PID_SHIFT 29 /**< Shift value for USB_PID */
AnnaBridge 171:3a7713b1edbc 1474 #define _USB_HC_TSIZ_PID_MASK 0x60000000UL /**< Bit mask for USB_PID */
AnnaBridge 171:3a7713b1edbc 1475 #define _USB_HC_TSIZ_PID_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1476 #define _USB_HC_TSIZ_PID_DATA0 0x00000000UL /**< Mode DATA0 for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1477 #define _USB_HC_TSIZ_PID_DATA2 0x00000001UL /**< Mode DATA2 for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1478 #define _USB_HC_TSIZ_PID_DATA1 0x00000002UL /**< Mode DATA1 for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1479 #define _USB_HC_TSIZ_PID_MDATA 0x00000003UL /**< Mode MDATA for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1480 #define USB_HC_TSIZ_PID_DEFAULT (_USB_HC_TSIZ_PID_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1481 #define USB_HC_TSIZ_PID_DATA0 (_USB_HC_TSIZ_PID_DATA0 << 29) /**< Shifted mode DATA0 for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1482 #define USB_HC_TSIZ_PID_DATA2 (_USB_HC_TSIZ_PID_DATA2 << 29) /**< Shifted mode DATA2 for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1483 #define USB_HC_TSIZ_PID_DATA1 (_USB_HC_TSIZ_PID_DATA1 << 29) /**< Shifted mode DATA1 for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1484 #define USB_HC_TSIZ_PID_MDATA (_USB_HC_TSIZ_PID_MDATA << 29) /**< Shifted mode MDATA for USB_HC_TSIZ */
AnnaBridge 171:3a7713b1edbc 1485
AnnaBridge 171:3a7713b1edbc 1486 /* Bit fields for USB HC_DMAADDR */
AnnaBridge 171:3a7713b1edbc 1487 #define _USB_HC_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_HC_DMAADDR */
AnnaBridge 171:3a7713b1edbc 1488 #define _USB_HC_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_HC_DMAADDR */
AnnaBridge 171:3a7713b1edbc 1489 #define _USB_HC_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */
AnnaBridge 171:3a7713b1edbc 1490 #define _USB_HC_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */
AnnaBridge 171:3a7713b1edbc 1491 #define _USB_HC_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_HC_DMAADDR */
AnnaBridge 171:3a7713b1edbc 1492 #define USB_HC_DMAADDR_DMAADDR_DEFAULT (_USB_HC_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_HC_DMAADDR */
AnnaBridge 171:3a7713b1edbc 1493
AnnaBridge 171:3a7713b1edbc 1494 /* Bit fields for USB DCFG */
AnnaBridge 171:3a7713b1edbc 1495 #define _USB_DCFG_RESETVALUE 0x08200000UL /**< Default value for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1496 #define _USB_DCFG_MASK 0xFC001FFFUL /**< Mask for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1497 #define _USB_DCFG_DEVSPD_SHIFT 0 /**< Shift value for USB_DEVSPD */
AnnaBridge 171:3a7713b1edbc 1498 #define _USB_DCFG_DEVSPD_MASK 0x3UL /**< Bit mask for USB_DEVSPD */
AnnaBridge 171:3a7713b1edbc 1499 #define _USB_DCFG_DEVSPD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1500 #define _USB_DCFG_DEVSPD_LS 0x00000002UL /**< Mode LS for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1501 #define _USB_DCFG_DEVSPD_FS 0x00000003UL /**< Mode FS for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1502 #define USB_DCFG_DEVSPD_DEFAULT (_USB_DCFG_DEVSPD_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1503 #define USB_DCFG_DEVSPD_LS (_USB_DCFG_DEVSPD_LS << 0) /**< Shifted mode LS for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1504 #define USB_DCFG_DEVSPD_FS (_USB_DCFG_DEVSPD_FS << 0) /**< Shifted mode FS for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1505 #define USB_DCFG_NZSTSOUTHSHK (0x1UL << 2) /**< Non-Zero-Length Status OUT Handshake */
AnnaBridge 171:3a7713b1edbc 1506 #define _USB_DCFG_NZSTSOUTHSHK_SHIFT 2 /**< Shift value for USB_NZSTSOUTHSHK */
AnnaBridge 171:3a7713b1edbc 1507 #define _USB_DCFG_NZSTSOUTHSHK_MASK 0x4UL /**< Bit mask for USB_NZSTSOUTHSHK */
AnnaBridge 171:3a7713b1edbc 1508 #define _USB_DCFG_NZSTSOUTHSHK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1509 #define USB_DCFG_NZSTSOUTHSHK_DEFAULT (_USB_DCFG_NZSTSOUTHSHK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1510 #define USB_DCFG_ENA32KHZSUSP (0x1UL << 3) /**< Enable 32 KHz Suspend mode */
AnnaBridge 171:3a7713b1edbc 1511 #define _USB_DCFG_ENA32KHZSUSP_SHIFT 3 /**< Shift value for USB_ENA32KHZSUSP */
AnnaBridge 171:3a7713b1edbc 1512 #define _USB_DCFG_ENA32KHZSUSP_MASK 0x8UL /**< Bit mask for USB_ENA32KHZSUSP */
AnnaBridge 171:3a7713b1edbc 1513 #define _USB_DCFG_ENA32KHZSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1514 #define USB_DCFG_ENA32KHZSUSP_DEFAULT (_USB_DCFG_ENA32KHZSUSP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1515 #define _USB_DCFG_DEVADDR_SHIFT 4 /**< Shift value for USB_DEVADDR */
AnnaBridge 171:3a7713b1edbc 1516 #define _USB_DCFG_DEVADDR_MASK 0x7F0UL /**< Bit mask for USB_DEVADDR */
AnnaBridge 171:3a7713b1edbc 1517 #define _USB_DCFG_DEVADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1518 #define USB_DCFG_DEVADDR_DEFAULT (_USB_DCFG_DEVADDR_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1519 #define _USB_DCFG_PERFRINT_SHIFT 11 /**< Shift value for USB_PERFRINT */
AnnaBridge 171:3a7713b1edbc 1520 #define _USB_DCFG_PERFRINT_MASK 0x1800UL /**< Bit mask for USB_PERFRINT */
AnnaBridge 171:3a7713b1edbc 1521 #define _USB_DCFG_PERFRINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1522 #define _USB_DCFG_PERFRINT_80PCNT 0x00000000UL /**< Mode 80PCNT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1523 #define _USB_DCFG_PERFRINT_85PCNT 0x00000001UL /**< Mode 85PCNT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1524 #define _USB_DCFG_PERFRINT_90PCNT 0x00000002UL /**< Mode 90PCNT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1525 #define _USB_DCFG_PERFRINT_95PCNT 0x00000003UL /**< Mode 95PCNT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1526 #define USB_DCFG_PERFRINT_DEFAULT (_USB_DCFG_PERFRINT_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1527 #define USB_DCFG_PERFRINT_80PCNT (_USB_DCFG_PERFRINT_80PCNT << 11) /**< Shifted mode 80PCNT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1528 #define USB_DCFG_PERFRINT_85PCNT (_USB_DCFG_PERFRINT_85PCNT << 11) /**< Shifted mode 85PCNT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1529 #define USB_DCFG_PERFRINT_90PCNT (_USB_DCFG_PERFRINT_90PCNT << 11) /**< Shifted mode 90PCNT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1530 #define USB_DCFG_PERFRINT_95PCNT (_USB_DCFG_PERFRINT_95PCNT << 11) /**< Shifted mode 95PCNT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1531 #define _USB_DCFG_RESVALID_SHIFT 26 /**< Shift value for USB_RESVALID */
AnnaBridge 171:3a7713b1edbc 1532 #define _USB_DCFG_RESVALID_MASK 0xFC000000UL /**< Bit mask for USB_RESVALID */
AnnaBridge 171:3a7713b1edbc 1533 #define _USB_DCFG_RESVALID_DEFAULT 0x00000002UL /**< Mode DEFAULT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1534 #define USB_DCFG_RESVALID_DEFAULT (_USB_DCFG_RESVALID_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DCFG */
AnnaBridge 171:3a7713b1edbc 1535
AnnaBridge 171:3a7713b1edbc 1536 /* Bit fields for USB DCTL */
AnnaBridge 171:3a7713b1edbc 1537 #define _USB_DCTL_RESETVALUE 0x00000000UL /**< Default value for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1538 #define _USB_DCTL_MASK 0x00018FFFUL /**< Mask for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1539 #define USB_DCTL_RMTWKUPSIG (0x1UL << 0) /**< Remote Wakeup Signaling */
AnnaBridge 171:3a7713b1edbc 1540 #define _USB_DCTL_RMTWKUPSIG_SHIFT 0 /**< Shift value for USB_RMTWKUPSIG */
AnnaBridge 171:3a7713b1edbc 1541 #define _USB_DCTL_RMTWKUPSIG_MASK 0x1UL /**< Bit mask for USB_RMTWKUPSIG */
AnnaBridge 171:3a7713b1edbc 1542 #define _USB_DCTL_RMTWKUPSIG_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1543 #define USB_DCTL_RMTWKUPSIG_DEFAULT (_USB_DCTL_RMTWKUPSIG_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1544 #define USB_DCTL_SFTDISCON (0x1UL << 1) /**< Soft Disconnect */
AnnaBridge 171:3a7713b1edbc 1545 #define _USB_DCTL_SFTDISCON_SHIFT 1 /**< Shift value for USB_SFTDISCON */
AnnaBridge 171:3a7713b1edbc 1546 #define _USB_DCTL_SFTDISCON_MASK 0x2UL /**< Bit mask for USB_SFTDISCON */
AnnaBridge 171:3a7713b1edbc 1547 #define _USB_DCTL_SFTDISCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1548 #define USB_DCTL_SFTDISCON_DEFAULT (_USB_DCTL_SFTDISCON_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1549 #define USB_DCTL_GNPINNAKSTS (0x1UL << 2) /**< Global Non-periodic IN NAK Status */
AnnaBridge 171:3a7713b1edbc 1550 #define _USB_DCTL_GNPINNAKSTS_SHIFT 2 /**< Shift value for USB_GNPINNAKSTS */
AnnaBridge 171:3a7713b1edbc 1551 #define _USB_DCTL_GNPINNAKSTS_MASK 0x4UL /**< Bit mask for USB_GNPINNAKSTS */
AnnaBridge 171:3a7713b1edbc 1552 #define _USB_DCTL_GNPINNAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1553 #define USB_DCTL_GNPINNAKSTS_DEFAULT (_USB_DCTL_GNPINNAKSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1554 #define USB_DCTL_GOUTNAKSTS (0x1UL << 3) /**< Global OUT NAK Status */
AnnaBridge 171:3a7713b1edbc 1555 #define _USB_DCTL_GOUTNAKSTS_SHIFT 3 /**< Shift value for USB_GOUTNAKSTS */
AnnaBridge 171:3a7713b1edbc 1556 #define _USB_DCTL_GOUTNAKSTS_MASK 0x8UL /**< Bit mask for USB_GOUTNAKSTS */
AnnaBridge 171:3a7713b1edbc 1557 #define _USB_DCTL_GOUTNAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1558 #define USB_DCTL_GOUTNAKSTS_DEFAULT (_USB_DCTL_GOUTNAKSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1559 #define _USB_DCTL_TSTCTL_SHIFT 4 /**< Shift value for USB_TSTCTL */
AnnaBridge 171:3a7713b1edbc 1560 #define _USB_DCTL_TSTCTL_MASK 0x70UL /**< Bit mask for USB_TSTCTL */
AnnaBridge 171:3a7713b1edbc 1561 #define _USB_DCTL_TSTCTL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1562 #define _USB_DCTL_TSTCTL_DISABLE 0x00000000UL /**< Mode DISABLE for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1563 #define _USB_DCTL_TSTCTL_J 0x00000001UL /**< Mode J for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1564 #define _USB_DCTL_TSTCTL_K 0x00000002UL /**< Mode K for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1565 #define _USB_DCTL_TSTCTL_SE0NAK 0x00000003UL /**< Mode SE0NAK for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1566 #define _USB_DCTL_TSTCTL_PACKET 0x00000004UL /**< Mode PACKET for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1567 #define _USB_DCTL_TSTCTL_FORCE 0x00000005UL /**< Mode FORCE for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1568 #define USB_DCTL_TSTCTL_DEFAULT (_USB_DCTL_TSTCTL_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1569 #define USB_DCTL_TSTCTL_DISABLE (_USB_DCTL_TSTCTL_DISABLE << 4) /**< Shifted mode DISABLE for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1570 #define USB_DCTL_TSTCTL_J (_USB_DCTL_TSTCTL_J << 4) /**< Shifted mode J for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1571 #define USB_DCTL_TSTCTL_K (_USB_DCTL_TSTCTL_K << 4) /**< Shifted mode K for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1572 #define USB_DCTL_TSTCTL_SE0NAK (_USB_DCTL_TSTCTL_SE0NAK << 4) /**< Shifted mode SE0NAK for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1573 #define USB_DCTL_TSTCTL_PACKET (_USB_DCTL_TSTCTL_PACKET << 4) /**< Shifted mode PACKET for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1574 #define USB_DCTL_TSTCTL_FORCE (_USB_DCTL_TSTCTL_FORCE << 4) /**< Shifted mode FORCE for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1575 #define USB_DCTL_SGNPINNAK (0x1UL << 7) /**< Set Global Non-periodic IN NAK */
AnnaBridge 171:3a7713b1edbc 1576 #define _USB_DCTL_SGNPINNAK_SHIFT 7 /**< Shift value for USB_SGNPINNAK */
AnnaBridge 171:3a7713b1edbc 1577 #define _USB_DCTL_SGNPINNAK_MASK 0x80UL /**< Bit mask for USB_SGNPINNAK */
AnnaBridge 171:3a7713b1edbc 1578 #define _USB_DCTL_SGNPINNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1579 #define USB_DCTL_SGNPINNAK_DEFAULT (_USB_DCTL_SGNPINNAK_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1580 #define USB_DCTL_CGNPINNAK (0x1UL << 8) /**< Clear Global Non-periodic IN NAK */
AnnaBridge 171:3a7713b1edbc 1581 #define _USB_DCTL_CGNPINNAK_SHIFT 8 /**< Shift value for USB_CGNPINNAK */
AnnaBridge 171:3a7713b1edbc 1582 #define _USB_DCTL_CGNPINNAK_MASK 0x100UL /**< Bit mask for USB_CGNPINNAK */
AnnaBridge 171:3a7713b1edbc 1583 #define _USB_DCTL_CGNPINNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1584 #define USB_DCTL_CGNPINNAK_DEFAULT (_USB_DCTL_CGNPINNAK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1585 #define USB_DCTL_SGOUTNAK (0x1UL << 9) /**< Set Global OUT NAK */
AnnaBridge 171:3a7713b1edbc 1586 #define _USB_DCTL_SGOUTNAK_SHIFT 9 /**< Shift value for USB_SGOUTNAK */
AnnaBridge 171:3a7713b1edbc 1587 #define _USB_DCTL_SGOUTNAK_MASK 0x200UL /**< Bit mask for USB_SGOUTNAK */
AnnaBridge 171:3a7713b1edbc 1588 #define _USB_DCTL_SGOUTNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1589 #define USB_DCTL_SGOUTNAK_DEFAULT (_USB_DCTL_SGOUTNAK_DEFAULT << 9) /**< Shifted mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1590 #define USB_DCTL_CGOUTNAK (0x1UL << 10) /**< Clear Global OUT NAK */
AnnaBridge 171:3a7713b1edbc 1591 #define _USB_DCTL_CGOUTNAK_SHIFT 10 /**< Shift value for USB_CGOUTNAK */
AnnaBridge 171:3a7713b1edbc 1592 #define _USB_DCTL_CGOUTNAK_MASK 0x400UL /**< Bit mask for USB_CGOUTNAK */
AnnaBridge 171:3a7713b1edbc 1593 #define _USB_DCTL_CGOUTNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1594 #define USB_DCTL_CGOUTNAK_DEFAULT (_USB_DCTL_CGOUTNAK_DEFAULT << 10) /**< Shifted mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1595 #define USB_DCTL_PWRONPRGDONE (0x1UL << 11) /**< Power-On Programming Done */
AnnaBridge 171:3a7713b1edbc 1596 #define _USB_DCTL_PWRONPRGDONE_SHIFT 11 /**< Shift value for USB_PWRONPRGDONE */
AnnaBridge 171:3a7713b1edbc 1597 #define _USB_DCTL_PWRONPRGDONE_MASK 0x800UL /**< Bit mask for USB_PWRONPRGDONE */
AnnaBridge 171:3a7713b1edbc 1598 #define _USB_DCTL_PWRONPRGDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1599 #define USB_DCTL_PWRONPRGDONE_DEFAULT (_USB_DCTL_PWRONPRGDONE_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1600 #define USB_DCTL_IGNRFRMNUM (0x1UL << 15) /**< Ignore Frame number For Isochronous End points */
AnnaBridge 171:3a7713b1edbc 1601 #define _USB_DCTL_IGNRFRMNUM_SHIFT 15 /**< Shift value for USB_IGNRFRMNUM */
AnnaBridge 171:3a7713b1edbc 1602 #define _USB_DCTL_IGNRFRMNUM_MASK 0x8000UL /**< Bit mask for USB_IGNRFRMNUM */
AnnaBridge 171:3a7713b1edbc 1603 #define _USB_DCTL_IGNRFRMNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1604 #define USB_DCTL_IGNRFRMNUM_DEFAULT (_USB_DCTL_IGNRFRMNUM_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1605 #define USB_DCTL_NAKONBBLE (0x1UL << 16) /**< NAK on Babble Error */
AnnaBridge 171:3a7713b1edbc 1606 #define _USB_DCTL_NAKONBBLE_SHIFT 16 /**< Shift value for USB_NAKONBBLE */
AnnaBridge 171:3a7713b1edbc 1607 #define _USB_DCTL_NAKONBBLE_MASK 0x10000UL /**< Bit mask for USB_NAKONBBLE */
AnnaBridge 171:3a7713b1edbc 1608 #define _USB_DCTL_NAKONBBLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1609 #define USB_DCTL_NAKONBBLE_DEFAULT (_USB_DCTL_NAKONBBLE_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DCTL */
AnnaBridge 171:3a7713b1edbc 1610
AnnaBridge 171:3a7713b1edbc 1611 /* Bit fields for USB DSTS */
AnnaBridge 171:3a7713b1edbc 1612 #define _USB_DSTS_RESETVALUE 0x00000002UL /**< Default value for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1613 #define _USB_DSTS_MASK 0x003FFF0FUL /**< Mask for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1614 #define USB_DSTS_SUSPSTS (0x1UL << 0) /**< Suspend Status */
AnnaBridge 171:3a7713b1edbc 1615 #define _USB_DSTS_SUSPSTS_SHIFT 0 /**< Shift value for USB_SUSPSTS */
AnnaBridge 171:3a7713b1edbc 1616 #define _USB_DSTS_SUSPSTS_MASK 0x1UL /**< Bit mask for USB_SUSPSTS */
AnnaBridge 171:3a7713b1edbc 1617 #define _USB_DSTS_SUSPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1618 #define USB_DSTS_SUSPSTS_DEFAULT (_USB_DSTS_SUSPSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1619 #define _USB_DSTS_ENUMSPD_SHIFT 1 /**< Shift value for USB_ENUMSPD */
AnnaBridge 171:3a7713b1edbc 1620 #define _USB_DSTS_ENUMSPD_MASK 0x6UL /**< Bit mask for USB_ENUMSPD */
AnnaBridge 171:3a7713b1edbc 1621 #define _USB_DSTS_ENUMSPD_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1622 #define _USB_DSTS_ENUMSPD_LS 0x00000002UL /**< Mode LS for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1623 #define _USB_DSTS_ENUMSPD_FS 0x00000003UL /**< Mode FS for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1624 #define USB_DSTS_ENUMSPD_DEFAULT (_USB_DSTS_ENUMSPD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1625 #define USB_DSTS_ENUMSPD_LS (_USB_DSTS_ENUMSPD_LS << 1) /**< Shifted mode LS for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1626 #define USB_DSTS_ENUMSPD_FS (_USB_DSTS_ENUMSPD_FS << 1) /**< Shifted mode FS for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1627 #define USB_DSTS_ERRTICERR (0x1UL << 3) /**< Erratic Error */
AnnaBridge 171:3a7713b1edbc 1628 #define _USB_DSTS_ERRTICERR_SHIFT 3 /**< Shift value for USB_ERRTICERR */
AnnaBridge 171:3a7713b1edbc 1629 #define _USB_DSTS_ERRTICERR_MASK 0x8UL /**< Bit mask for USB_ERRTICERR */
AnnaBridge 171:3a7713b1edbc 1630 #define _USB_DSTS_ERRTICERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1631 #define USB_DSTS_ERRTICERR_DEFAULT (_USB_DSTS_ERRTICERR_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1632 #define _USB_DSTS_SOFFN_SHIFT 8 /**< Shift value for USB_SOFFN */
AnnaBridge 171:3a7713b1edbc 1633 #define _USB_DSTS_SOFFN_MASK 0x3FFF00UL /**< Bit mask for USB_SOFFN */
AnnaBridge 171:3a7713b1edbc 1634 #define _USB_DSTS_SOFFN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1635 #define USB_DSTS_SOFFN_DEFAULT (_USB_DSTS_SOFFN_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DSTS */
AnnaBridge 171:3a7713b1edbc 1636
AnnaBridge 171:3a7713b1edbc 1637 /* Bit fields for USB DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1638 #define _USB_DIEPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1639 #define _USB_DIEPMSK_MASK 0x0000215FUL /**< Mask for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1640 #define USB_DIEPMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 1641 #define _USB_DIEPMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */
AnnaBridge 171:3a7713b1edbc 1642 #define _USB_DIEPMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */
AnnaBridge 171:3a7713b1edbc 1643 #define _USB_DIEPMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1644 #define USB_DIEPMSK_XFERCOMPLMSK_DEFAULT (_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1645 #define USB_DIEPMSK_EPDISBLDMSK (0x1UL << 1) /**< Endpoint Disabled Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 1646 #define _USB_DIEPMSK_EPDISBLDMSK_SHIFT 1 /**< Shift value for USB_EPDISBLDMSK */
AnnaBridge 171:3a7713b1edbc 1647 #define _USB_DIEPMSK_EPDISBLDMSK_MASK 0x2UL /**< Bit mask for USB_EPDISBLDMSK */
AnnaBridge 171:3a7713b1edbc 1648 #define _USB_DIEPMSK_EPDISBLDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1649 #define USB_DIEPMSK_EPDISBLDMSK_DEFAULT (_USB_DIEPMSK_EPDISBLDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1650 #define USB_DIEPMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error Mask */
AnnaBridge 171:3a7713b1edbc 1651 #define _USB_DIEPMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */
AnnaBridge 171:3a7713b1edbc 1652 #define _USB_DIEPMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */
AnnaBridge 171:3a7713b1edbc 1653 #define _USB_DIEPMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1654 #define USB_DIEPMSK_AHBERRMSK_DEFAULT (_USB_DIEPMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1655 #define USB_DIEPMSK_TIMEOUTMSK (0x1UL << 3) /**< Timeout Condition Mask */
AnnaBridge 171:3a7713b1edbc 1656 #define _USB_DIEPMSK_TIMEOUTMSK_SHIFT 3 /**< Shift value for USB_TIMEOUTMSK */
AnnaBridge 171:3a7713b1edbc 1657 #define _USB_DIEPMSK_TIMEOUTMSK_MASK 0x8UL /**< Bit mask for USB_TIMEOUTMSK */
AnnaBridge 171:3a7713b1edbc 1658 #define _USB_DIEPMSK_TIMEOUTMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1659 #define USB_DIEPMSK_TIMEOUTMSK_DEFAULT (_USB_DIEPMSK_TIMEOUTMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1660 #define USB_DIEPMSK_INTKNTXFEMPMSK (0x1UL << 4) /**< IN Token Received When TxFIFO Empty Mask */
AnnaBridge 171:3a7713b1edbc 1661 #define _USB_DIEPMSK_INTKNTXFEMPMSK_SHIFT 4 /**< Shift value for USB_INTKNTXFEMPMSK */
AnnaBridge 171:3a7713b1edbc 1662 #define _USB_DIEPMSK_INTKNTXFEMPMSK_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMPMSK */
AnnaBridge 171:3a7713b1edbc 1663 #define _USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1664 #define USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT (_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1665 #define USB_DIEPMSK_INEPNAKEFFMSK (0x1UL << 6) /**< IN Endpoint NAK Effective Mask */
AnnaBridge 171:3a7713b1edbc 1666 #define _USB_DIEPMSK_INEPNAKEFFMSK_SHIFT 6 /**< Shift value for USB_INEPNAKEFFMSK */
AnnaBridge 171:3a7713b1edbc 1667 #define _USB_DIEPMSK_INEPNAKEFFMSK_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFFMSK */
AnnaBridge 171:3a7713b1edbc 1668 #define _USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1669 #define USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT (_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1670 #define USB_DIEPMSK_TXFIFOUNDRNMSK (0x1UL << 8) /**< Fifo Underrun Mask */
AnnaBridge 171:3a7713b1edbc 1671 #define _USB_DIEPMSK_TXFIFOUNDRNMSK_SHIFT 8 /**< Shift value for USB_TXFIFOUNDRNMSK */
AnnaBridge 171:3a7713b1edbc 1672 #define _USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100UL /**< Bit mask for USB_TXFIFOUNDRNMSK */
AnnaBridge 171:3a7713b1edbc 1673 #define _USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1674 #define USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT (_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1675 #define USB_DIEPMSK_NAKMSK (0x1UL << 13) /**< NAK interrupt Mask */
AnnaBridge 171:3a7713b1edbc 1676 #define _USB_DIEPMSK_NAKMSK_SHIFT 13 /**< Shift value for USB_NAKMSK */
AnnaBridge 171:3a7713b1edbc 1677 #define _USB_DIEPMSK_NAKMSK_MASK 0x2000UL /**< Bit mask for USB_NAKMSK */
AnnaBridge 171:3a7713b1edbc 1678 #define _USB_DIEPMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1679 #define USB_DIEPMSK_NAKMSK_DEFAULT (_USB_DIEPMSK_NAKMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEPMSK */
AnnaBridge 171:3a7713b1edbc 1680
AnnaBridge 171:3a7713b1edbc 1681 /* Bit fields for USB DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1682 #define _USB_DOEPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1683 #define _USB_DOEPMSK_MASK 0x0000315FUL /**< Mask for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1684 #define USB_DOEPMSK_XFERCOMPLMSK (0x1UL << 0) /**< Transfer Completed Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 1685 #define _USB_DOEPMSK_XFERCOMPLMSK_SHIFT 0 /**< Shift value for USB_XFERCOMPLMSK */
AnnaBridge 171:3a7713b1edbc 1686 #define _USB_DOEPMSK_XFERCOMPLMSK_MASK 0x1UL /**< Bit mask for USB_XFERCOMPLMSK */
AnnaBridge 171:3a7713b1edbc 1687 #define _USB_DOEPMSK_XFERCOMPLMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1688 #define USB_DOEPMSK_XFERCOMPLMSK_DEFAULT (_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1689 #define USB_DOEPMSK_EPDISBLDMSK (0x1UL << 1) /**< Endpoint Disabled Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 1690 #define _USB_DOEPMSK_EPDISBLDMSK_SHIFT 1 /**< Shift value for USB_EPDISBLDMSK */
AnnaBridge 171:3a7713b1edbc 1691 #define _USB_DOEPMSK_EPDISBLDMSK_MASK 0x2UL /**< Bit mask for USB_EPDISBLDMSK */
AnnaBridge 171:3a7713b1edbc 1692 #define _USB_DOEPMSK_EPDISBLDMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1693 #define USB_DOEPMSK_EPDISBLDMSK_DEFAULT (_USB_DOEPMSK_EPDISBLDMSK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1694 #define USB_DOEPMSK_AHBERRMSK (0x1UL << 2) /**< AHB Error */
AnnaBridge 171:3a7713b1edbc 1695 #define _USB_DOEPMSK_AHBERRMSK_SHIFT 2 /**< Shift value for USB_AHBERRMSK */
AnnaBridge 171:3a7713b1edbc 1696 #define _USB_DOEPMSK_AHBERRMSK_MASK 0x4UL /**< Bit mask for USB_AHBERRMSK */
AnnaBridge 171:3a7713b1edbc 1697 #define _USB_DOEPMSK_AHBERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1698 #define USB_DOEPMSK_AHBERRMSK_DEFAULT (_USB_DOEPMSK_AHBERRMSK_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1699 #define USB_DOEPMSK_SETUPMSK (0x1UL << 3) /**< SETUP Phase Done Mask */
AnnaBridge 171:3a7713b1edbc 1700 #define _USB_DOEPMSK_SETUPMSK_SHIFT 3 /**< Shift value for USB_SETUPMSK */
AnnaBridge 171:3a7713b1edbc 1701 #define _USB_DOEPMSK_SETUPMSK_MASK 0x8UL /**< Bit mask for USB_SETUPMSK */
AnnaBridge 171:3a7713b1edbc 1702 #define _USB_DOEPMSK_SETUPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1703 #define USB_DOEPMSK_SETUPMSK_DEFAULT (_USB_DOEPMSK_SETUPMSK_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1704 #define USB_DOEPMSK_OUTTKNEPDISMSK (0x1UL << 4) /**< OUT Token Received when Endpoint Disabled Mask */
AnnaBridge 171:3a7713b1edbc 1705 #define _USB_DOEPMSK_OUTTKNEPDISMSK_SHIFT 4 /**< Shift value for USB_OUTTKNEPDISMSK */
AnnaBridge 171:3a7713b1edbc 1706 #define _USB_DOEPMSK_OUTTKNEPDISMSK_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDISMSK */
AnnaBridge 171:3a7713b1edbc 1707 #define _USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1708 #define USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT (_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1709 #define USB_DOEPMSK_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received Mask */
AnnaBridge 171:3a7713b1edbc 1710 #define _USB_DOEPMSK_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */
AnnaBridge 171:3a7713b1edbc 1711 #define _USB_DOEPMSK_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */
AnnaBridge 171:3a7713b1edbc 1712 #define _USB_DOEPMSK_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1713 #define USB_DOEPMSK_BACK2BACKSETUP_DEFAULT (_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1714 #define USB_DOEPMSK_OUTPKTERRMSK (0x1UL << 8) /**< OUT Packet Error Mask */
AnnaBridge 171:3a7713b1edbc 1715 #define _USB_DOEPMSK_OUTPKTERRMSK_SHIFT 8 /**< Shift value for USB_OUTPKTERRMSK */
AnnaBridge 171:3a7713b1edbc 1716 #define _USB_DOEPMSK_OUTPKTERRMSK_MASK 0x100UL /**< Bit mask for USB_OUTPKTERRMSK */
AnnaBridge 171:3a7713b1edbc 1717 #define _USB_DOEPMSK_OUTPKTERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1718 #define USB_DOEPMSK_OUTPKTERRMSK_DEFAULT (_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1719 #define USB_DOEPMSK_BBLEERRMSK (0x1UL << 12) /**< Babble Error interrupt Mask */
AnnaBridge 171:3a7713b1edbc 1720 #define _USB_DOEPMSK_BBLEERRMSK_SHIFT 12 /**< Shift value for USB_BBLEERRMSK */
AnnaBridge 171:3a7713b1edbc 1721 #define _USB_DOEPMSK_BBLEERRMSK_MASK 0x1000UL /**< Bit mask for USB_BBLEERRMSK */
AnnaBridge 171:3a7713b1edbc 1722 #define _USB_DOEPMSK_BBLEERRMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1723 #define USB_DOEPMSK_BBLEERRMSK_DEFAULT (_USB_DOEPMSK_BBLEERRMSK_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1724 #define USB_DOEPMSK_NAKMSK (0x1UL << 13) /**< NAK interrupt Mask */
AnnaBridge 171:3a7713b1edbc 1725 #define _USB_DOEPMSK_NAKMSK_SHIFT 13 /**< Shift value for USB_NAKMSK */
AnnaBridge 171:3a7713b1edbc 1726 #define _USB_DOEPMSK_NAKMSK_MASK 0x2000UL /**< Bit mask for USB_NAKMSK */
AnnaBridge 171:3a7713b1edbc 1727 #define _USB_DOEPMSK_NAKMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1728 #define USB_DOEPMSK_NAKMSK_DEFAULT (_USB_DOEPMSK_NAKMSK_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEPMSK */
AnnaBridge 171:3a7713b1edbc 1729
AnnaBridge 171:3a7713b1edbc 1730 /* Bit fields for USB DAINT */
AnnaBridge 171:3a7713b1edbc 1731 #define _USB_DAINT_RESETVALUE 0x00000000UL /**< Default value for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1732 #define _USB_DAINT_MASK 0x007F007FUL /**< Mask for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1733 #define USB_DAINT_INEPINT0 (0x1UL << 0) /**< IN Endpoint 0 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1734 #define _USB_DAINT_INEPINT0_SHIFT 0 /**< Shift value for USB_INEPINT0 */
AnnaBridge 171:3a7713b1edbc 1735 #define _USB_DAINT_INEPINT0_MASK 0x1UL /**< Bit mask for USB_INEPINT0 */
AnnaBridge 171:3a7713b1edbc 1736 #define _USB_DAINT_INEPINT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1737 #define USB_DAINT_INEPINT0_DEFAULT (_USB_DAINT_INEPINT0_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1738 #define USB_DAINT_INEPINT1 (0x1UL << 1) /**< IN Endpoint 1 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1739 #define _USB_DAINT_INEPINT1_SHIFT 1 /**< Shift value for USB_INEPINT1 */
AnnaBridge 171:3a7713b1edbc 1740 #define _USB_DAINT_INEPINT1_MASK 0x2UL /**< Bit mask for USB_INEPINT1 */
AnnaBridge 171:3a7713b1edbc 1741 #define _USB_DAINT_INEPINT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1742 #define USB_DAINT_INEPINT1_DEFAULT (_USB_DAINT_INEPINT1_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1743 #define USB_DAINT_INEPINT2 (0x1UL << 2) /**< IN Endpoint 2 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1744 #define _USB_DAINT_INEPINT2_SHIFT 2 /**< Shift value for USB_INEPINT2 */
AnnaBridge 171:3a7713b1edbc 1745 #define _USB_DAINT_INEPINT2_MASK 0x4UL /**< Bit mask for USB_INEPINT2 */
AnnaBridge 171:3a7713b1edbc 1746 #define _USB_DAINT_INEPINT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1747 #define USB_DAINT_INEPINT2_DEFAULT (_USB_DAINT_INEPINT2_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1748 #define USB_DAINT_INEPINT3 (0x1UL << 3) /**< IN Endpoint 3 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1749 #define _USB_DAINT_INEPINT3_SHIFT 3 /**< Shift value for USB_INEPINT3 */
AnnaBridge 171:3a7713b1edbc 1750 #define _USB_DAINT_INEPINT3_MASK 0x8UL /**< Bit mask for USB_INEPINT3 */
AnnaBridge 171:3a7713b1edbc 1751 #define _USB_DAINT_INEPINT3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1752 #define USB_DAINT_INEPINT3_DEFAULT (_USB_DAINT_INEPINT3_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1753 #define USB_DAINT_INEPINT4 (0x1UL << 4) /**< IN Endpoint 4 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1754 #define _USB_DAINT_INEPINT4_SHIFT 4 /**< Shift value for USB_INEPINT4 */
AnnaBridge 171:3a7713b1edbc 1755 #define _USB_DAINT_INEPINT4_MASK 0x10UL /**< Bit mask for USB_INEPINT4 */
AnnaBridge 171:3a7713b1edbc 1756 #define _USB_DAINT_INEPINT4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1757 #define USB_DAINT_INEPINT4_DEFAULT (_USB_DAINT_INEPINT4_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1758 #define USB_DAINT_INEPINT5 (0x1UL << 5) /**< IN Endpoint 5 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1759 #define _USB_DAINT_INEPINT5_SHIFT 5 /**< Shift value for USB_INEPINT5 */
AnnaBridge 171:3a7713b1edbc 1760 #define _USB_DAINT_INEPINT5_MASK 0x20UL /**< Bit mask for USB_INEPINT5 */
AnnaBridge 171:3a7713b1edbc 1761 #define _USB_DAINT_INEPINT5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1762 #define USB_DAINT_INEPINT5_DEFAULT (_USB_DAINT_INEPINT5_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1763 #define USB_DAINT_INEPINT6 (0x1UL << 6) /**< IN Endpoint 6 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1764 #define _USB_DAINT_INEPINT6_SHIFT 6 /**< Shift value for USB_INEPINT6 */
AnnaBridge 171:3a7713b1edbc 1765 #define _USB_DAINT_INEPINT6_MASK 0x40UL /**< Bit mask for USB_INEPINT6 */
AnnaBridge 171:3a7713b1edbc 1766 #define _USB_DAINT_INEPINT6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1767 #define USB_DAINT_INEPINT6_DEFAULT (_USB_DAINT_INEPINT6_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1768 #define USB_DAINT_OUTEPINT0 (0x1UL << 16) /**< OUT Endpoint 0 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1769 #define _USB_DAINT_OUTEPINT0_SHIFT 16 /**< Shift value for USB_OUTEPINT0 */
AnnaBridge 171:3a7713b1edbc 1770 #define _USB_DAINT_OUTEPINT0_MASK 0x10000UL /**< Bit mask for USB_OUTEPINT0 */
AnnaBridge 171:3a7713b1edbc 1771 #define _USB_DAINT_OUTEPINT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1772 #define USB_DAINT_OUTEPINT0_DEFAULT (_USB_DAINT_OUTEPINT0_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1773 #define USB_DAINT_OUTEPINT1 (0x1UL << 17) /**< OUT Endpoint 1 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1774 #define _USB_DAINT_OUTEPINT1_SHIFT 17 /**< Shift value for USB_OUTEPINT1 */
AnnaBridge 171:3a7713b1edbc 1775 #define _USB_DAINT_OUTEPINT1_MASK 0x20000UL /**< Bit mask for USB_OUTEPINT1 */
AnnaBridge 171:3a7713b1edbc 1776 #define _USB_DAINT_OUTEPINT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1777 #define USB_DAINT_OUTEPINT1_DEFAULT (_USB_DAINT_OUTEPINT1_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1778 #define USB_DAINT_OUTEPINT2 (0x1UL << 18) /**< OUT Endpoint 2 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1779 #define _USB_DAINT_OUTEPINT2_SHIFT 18 /**< Shift value for USB_OUTEPINT2 */
AnnaBridge 171:3a7713b1edbc 1780 #define _USB_DAINT_OUTEPINT2_MASK 0x40000UL /**< Bit mask for USB_OUTEPINT2 */
AnnaBridge 171:3a7713b1edbc 1781 #define _USB_DAINT_OUTEPINT2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1782 #define USB_DAINT_OUTEPINT2_DEFAULT (_USB_DAINT_OUTEPINT2_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1783 #define USB_DAINT_OUTEPINT3 (0x1UL << 19) /**< OUT Endpoint 3 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1784 #define _USB_DAINT_OUTEPINT3_SHIFT 19 /**< Shift value for USB_OUTEPINT3 */
AnnaBridge 171:3a7713b1edbc 1785 #define _USB_DAINT_OUTEPINT3_MASK 0x80000UL /**< Bit mask for USB_OUTEPINT3 */
AnnaBridge 171:3a7713b1edbc 1786 #define _USB_DAINT_OUTEPINT3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1787 #define USB_DAINT_OUTEPINT3_DEFAULT (_USB_DAINT_OUTEPINT3_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1788 #define USB_DAINT_OUTEPINT4 (0x1UL << 20) /**< OUT Endpoint 4 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1789 #define _USB_DAINT_OUTEPINT4_SHIFT 20 /**< Shift value for USB_OUTEPINT4 */
AnnaBridge 171:3a7713b1edbc 1790 #define _USB_DAINT_OUTEPINT4_MASK 0x100000UL /**< Bit mask for USB_OUTEPINT4 */
AnnaBridge 171:3a7713b1edbc 1791 #define _USB_DAINT_OUTEPINT4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1792 #define USB_DAINT_OUTEPINT4_DEFAULT (_USB_DAINT_OUTEPINT4_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1793 #define USB_DAINT_OUTEPINT5 (0x1UL << 21) /**< OUT Endpoint 5 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1794 #define _USB_DAINT_OUTEPINT5_SHIFT 21 /**< Shift value for USB_OUTEPINT5 */
AnnaBridge 171:3a7713b1edbc 1795 #define _USB_DAINT_OUTEPINT5_MASK 0x200000UL /**< Bit mask for USB_OUTEPINT5 */
AnnaBridge 171:3a7713b1edbc 1796 #define _USB_DAINT_OUTEPINT5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1797 #define USB_DAINT_OUTEPINT5_DEFAULT (_USB_DAINT_OUTEPINT5_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1798 #define USB_DAINT_OUTEPINT6 (0x1UL << 22) /**< OUT Endpoint 6 Interrupt Bit */
AnnaBridge 171:3a7713b1edbc 1799 #define _USB_DAINT_OUTEPINT6_SHIFT 22 /**< Shift value for USB_OUTEPINT6 */
AnnaBridge 171:3a7713b1edbc 1800 #define _USB_DAINT_OUTEPINT6_MASK 0x400000UL /**< Bit mask for USB_OUTEPINT6 */
AnnaBridge 171:3a7713b1edbc 1801 #define _USB_DAINT_OUTEPINT6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1802 #define USB_DAINT_OUTEPINT6_DEFAULT (_USB_DAINT_OUTEPINT6_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DAINT */
AnnaBridge 171:3a7713b1edbc 1803
AnnaBridge 171:3a7713b1edbc 1804 /* Bit fields for USB DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1805 #define _USB_DAINTMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1806 #define _USB_DAINTMSK_MASK 0x007F007FUL /**< Mask for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1807 #define USB_DAINTMSK_INEPMSK0 (0x1UL << 0) /**< IN Endpoint 0 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1808 #define _USB_DAINTMSK_INEPMSK0_SHIFT 0 /**< Shift value for USB_INEPMSK0 */
AnnaBridge 171:3a7713b1edbc 1809 #define _USB_DAINTMSK_INEPMSK0_MASK 0x1UL /**< Bit mask for USB_INEPMSK0 */
AnnaBridge 171:3a7713b1edbc 1810 #define _USB_DAINTMSK_INEPMSK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1811 #define USB_DAINTMSK_INEPMSK0_DEFAULT (_USB_DAINTMSK_INEPMSK0_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1812 #define USB_DAINTMSK_INEPMSK1 (0x1UL << 1) /**< IN Endpoint 1 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1813 #define _USB_DAINTMSK_INEPMSK1_SHIFT 1 /**< Shift value for USB_INEPMSK1 */
AnnaBridge 171:3a7713b1edbc 1814 #define _USB_DAINTMSK_INEPMSK1_MASK 0x2UL /**< Bit mask for USB_INEPMSK1 */
AnnaBridge 171:3a7713b1edbc 1815 #define _USB_DAINTMSK_INEPMSK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1816 #define USB_DAINTMSK_INEPMSK1_DEFAULT (_USB_DAINTMSK_INEPMSK1_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1817 #define USB_DAINTMSK_INEPMSK2 (0x1UL << 2) /**< IN Endpoint 2 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1818 #define _USB_DAINTMSK_INEPMSK2_SHIFT 2 /**< Shift value for USB_INEPMSK2 */
AnnaBridge 171:3a7713b1edbc 1819 #define _USB_DAINTMSK_INEPMSK2_MASK 0x4UL /**< Bit mask for USB_INEPMSK2 */
AnnaBridge 171:3a7713b1edbc 1820 #define _USB_DAINTMSK_INEPMSK2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1821 #define USB_DAINTMSK_INEPMSK2_DEFAULT (_USB_DAINTMSK_INEPMSK2_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1822 #define USB_DAINTMSK_INEPMSK3 (0x1UL << 3) /**< IN Endpoint 3 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1823 #define _USB_DAINTMSK_INEPMSK3_SHIFT 3 /**< Shift value for USB_INEPMSK3 */
AnnaBridge 171:3a7713b1edbc 1824 #define _USB_DAINTMSK_INEPMSK3_MASK 0x8UL /**< Bit mask for USB_INEPMSK3 */
AnnaBridge 171:3a7713b1edbc 1825 #define _USB_DAINTMSK_INEPMSK3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1826 #define USB_DAINTMSK_INEPMSK3_DEFAULT (_USB_DAINTMSK_INEPMSK3_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1827 #define USB_DAINTMSK_INEPMSK4 (0x1UL << 4) /**< IN Endpoint 4 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1828 #define _USB_DAINTMSK_INEPMSK4_SHIFT 4 /**< Shift value for USB_INEPMSK4 */
AnnaBridge 171:3a7713b1edbc 1829 #define _USB_DAINTMSK_INEPMSK4_MASK 0x10UL /**< Bit mask for USB_INEPMSK4 */
AnnaBridge 171:3a7713b1edbc 1830 #define _USB_DAINTMSK_INEPMSK4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1831 #define USB_DAINTMSK_INEPMSK4_DEFAULT (_USB_DAINTMSK_INEPMSK4_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1832 #define USB_DAINTMSK_INEPMSK5 (0x1UL << 5) /**< IN Endpoint 5 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1833 #define _USB_DAINTMSK_INEPMSK5_SHIFT 5 /**< Shift value for USB_INEPMSK5 */
AnnaBridge 171:3a7713b1edbc 1834 #define _USB_DAINTMSK_INEPMSK5_MASK 0x20UL /**< Bit mask for USB_INEPMSK5 */
AnnaBridge 171:3a7713b1edbc 1835 #define _USB_DAINTMSK_INEPMSK5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1836 #define USB_DAINTMSK_INEPMSK5_DEFAULT (_USB_DAINTMSK_INEPMSK5_DEFAULT << 5) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1837 #define USB_DAINTMSK_INEPMSK6 (0x1UL << 6) /**< IN Endpoint 6 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1838 #define _USB_DAINTMSK_INEPMSK6_SHIFT 6 /**< Shift value for USB_INEPMSK6 */
AnnaBridge 171:3a7713b1edbc 1839 #define _USB_DAINTMSK_INEPMSK6_MASK 0x40UL /**< Bit mask for USB_INEPMSK6 */
AnnaBridge 171:3a7713b1edbc 1840 #define _USB_DAINTMSK_INEPMSK6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1841 #define USB_DAINTMSK_INEPMSK6_DEFAULT (_USB_DAINTMSK_INEPMSK6_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1842 #define USB_DAINTMSK_OUTEPMSK0 (0x1UL << 16) /**< OUT Endpoint 0 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1843 #define _USB_DAINTMSK_OUTEPMSK0_SHIFT 16 /**< Shift value for USB_OUTEPMSK0 */
AnnaBridge 171:3a7713b1edbc 1844 #define _USB_DAINTMSK_OUTEPMSK0_MASK 0x10000UL /**< Bit mask for USB_OUTEPMSK0 */
AnnaBridge 171:3a7713b1edbc 1845 #define _USB_DAINTMSK_OUTEPMSK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1846 #define USB_DAINTMSK_OUTEPMSK0_DEFAULT (_USB_DAINTMSK_OUTEPMSK0_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1847 #define USB_DAINTMSK_OUTEPMSK1 (0x1UL << 17) /**< OUT Endpoint 1 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1848 #define _USB_DAINTMSK_OUTEPMSK1_SHIFT 17 /**< Shift value for USB_OUTEPMSK1 */
AnnaBridge 171:3a7713b1edbc 1849 #define _USB_DAINTMSK_OUTEPMSK1_MASK 0x20000UL /**< Bit mask for USB_OUTEPMSK1 */
AnnaBridge 171:3a7713b1edbc 1850 #define _USB_DAINTMSK_OUTEPMSK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1851 #define USB_DAINTMSK_OUTEPMSK1_DEFAULT (_USB_DAINTMSK_OUTEPMSK1_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1852 #define USB_DAINTMSK_OUTEPMSK2 (0x1UL << 18) /**< OUT Endpoint 2 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1853 #define _USB_DAINTMSK_OUTEPMSK2_SHIFT 18 /**< Shift value for USB_OUTEPMSK2 */
AnnaBridge 171:3a7713b1edbc 1854 #define _USB_DAINTMSK_OUTEPMSK2_MASK 0x40000UL /**< Bit mask for USB_OUTEPMSK2 */
AnnaBridge 171:3a7713b1edbc 1855 #define _USB_DAINTMSK_OUTEPMSK2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1856 #define USB_DAINTMSK_OUTEPMSK2_DEFAULT (_USB_DAINTMSK_OUTEPMSK2_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1857 #define USB_DAINTMSK_OUTEPMSK3 (0x1UL << 19) /**< OUT Endpoint 3 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1858 #define _USB_DAINTMSK_OUTEPMSK3_SHIFT 19 /**< Shift value for USB_OUTEPMSK3 */
AnnaBridge 171:3a7713b1edbc 1859 #define _USB_DAINTMSK_OUTEPMSK3_MASK 0x80000UL /**< Bit mask for USB_OUTEPMSK3 */
AnnaBridge 171:3a7713b1edbc 1860 #define _USB_DAINTMSK_OUTEPMSK3_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1861 #define USB_DAINTMSK_OUTEPMSK3_DEFAULT (_USB_DAINTMSK_OUTEPMSK3_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1862 #define USB_DAINTMSK_OUTEPMSK4 (0x1UL << 20) /**< OUT Endpoint 4 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1863 #define _USB_DAINTMSK_OUTEPMSK4_SHIFT 20 /**< Shift value for USB_OUTEPMSK4 */
AnnaBridge 171:3a7713b1edbc 1864 #define _USB_DAINTMSK_OUTEPMSK4_MASK 0x100000UL /**< Bit mask for USB_OUTEPMSK4 */
AnnaBridge 171:3a7713b1edbc 1865 #define _USB_DAINTMSK_OUTEPMSK4_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1866 #define USB_DAINTMSK_OUTEPMSK4_DEFAULT (_USB_DAINTMSK_OUTEPMSK4_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1867 #define USB_DAINTMSK_OUTEPMSK5 (0x1UL << 21) /**< OUT Endpoint 5 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1868 #define _USB_DAINTMSK_OUTEPMSK5_SHIFT 21 /**< Shift value for USB_OUTEPMSK5 */
AnnaBridge 171:3a7713b1edbc 1869 #define _USB_DAINTMSK_OUTEPMSK5_MASK 0x200000UL /**< Bit mask for USB_OUTEPMSK5 */
AnnaBridge 171:3a7713b1edbc 1870 #define _USB_DAINTMSK_OUTEPMSK5_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1871 #define USB_DAINTMSK_OUTEPMSK5_DEFAULT (_USB_DAINTMSK_OUTEPMSK5_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1872 #define USB_DAINTMSK_OUTEPMSK6 (0x1UL << 22) /**< OUT Endpoint 6 Interrupt mask Bit */
AnnaBridge 171:3a7713b1edbc 1873 #define _USB_DAINTMSK_OUTEPMSK6_SHIFT 22 /**< Shift value for USB_OUTEPMSK6 */
AnnaBridge 171:3a7713b1edbc 1874 #define _USB_DAINTMSK_OUTEPMSK6_MASK 0x400000UL /**< Bit mask for USB_OUTEPMSK6 */
AnnaBridge 171:3a7713b1edbc 1875 #define _USB_DAINTMSK_OUTEPMSK6_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1876 #define USB_DAINTMSK_OUTEPMSK6_DEFAULT (_USB_DAINTMSK_OUTEPMSK6_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DAINTMSK */
AnnaBridge 171:3a7713b1edbc 1877
AnnaBridge 171:3a7713b1edbc 1878 /* Bit fields for USB DVBUSDIS */
AnnaBridge 171:3a7713b1edbc 1879 #define _USB_DVBUSDIS_RESETVALUE 0x000017D7UL /**< Default value for USB_DVBUSDIS */
AnnaBridge 171:3a7713b1edbc 1880 #define _USB_DVBUSDIS_MASK 0x0000FFFFUL /**< Mask for USB_DVBUSDIS */
AnnaBridge 171:3a7713b1edbc 1881 #define _USB_DVBUSDIS_DVBUSDIS_SHIFT 0 /**< Shift value for USB_DVBUSDIS */
AnnaBridge 171:3a7713b1edbc 1882 #define _USB_DVBUSDIS_DVBUSDIS_MASK 0xFFFFUL /**< Bit mask for USB_DVBUSDIS */
AnnaBridge 171:3a7713b1edbc 1883 #define _USB_DVBUSDIS_DVBUSDIS_DEFAULT 0x000017D7UL /**< Mode DEFAULT for USB_DVBUSDIS */
AnnaBridge 171:3a7713b1edbc 1884 #define USB_DVBUSDIS_DVBUSDIS_DEFAULT (_USB_DVBUSDIS_DVBUSDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DVBUSDIS */
AnnaBridge 171:3a7713b1edbc 1885
AnnaBridge 171:3a7713b1edbc 1886 /* Bit fields for USB DVBUSPULSE */
AnnaBridge 171:3a7713b1edbc 1887 #define _USB_DVBUSPULSE_RESETVALUE 0x000005B8UL /**< Default value for USB_DVBUSPULSE */
AnnaBridge 171:3a7713b1edbc 1888 #define _USB_DVBUSPULSE_MASK 0x00000FFFUL /**< Mask for USB_DVBUSPULSE */
AnnaBridge 171:3a7713b1edbc 1889 #define _USB_DVBUSPULSE_DVBUSPULSE_SHIFT 0 /**< Shift value for USB_DVBUSPULSE */
AnnaBridge 171:3a7713b1edbc 1890 #define _USB_DVBUSPULSE_DVBUSPULSE_MASK 0xFFFUL /**< Bit mask for USB_DVBUSPULSE */
AnnaBridge 171:3a7713b1edbc 1891 #define _USB_DVBUSPULSE_DVBUSPULSE_DEFAULT 0x000005B8UL /**< Mode DEFAULT for USB_DVBUSPULSE */
AnnaBridge 171:3a7713b1edbc 1892 #define USB_DVBUSPULSE_DVBUSPULSE_DEFAULT (_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DVBUSPULSE */
AnnaBridge 171:3a7713b1edbc 1893
AnnaBridge 171:3a7713b1edbc 1894 /* Bit fields for USB DIEPEMPMSK */
AnnaBridge 171:3a7713b1edbc 1895 #define _USB_DIEPEMPMSK_RESETVALUE 0x00000000UL /**< Default value for USB_DIEPEMPMSK */
AnnaBridge 171:3a7713b1edbc 1896 #define _USB_DIEPEMPMSK_MASK 0x0000FFFFUL /**< Mask for USB_DIEPEMPMSK */
AnnaBridge 171:3a7713b1edbc 1897 #define _USB_DIEPEMPMSK_DIEPEMPMSK_SHIFT 0 /**< Shift value for USB_DIEPEMPMSK */
AnnaBridge 171:3a7713b1edbc 1898 #define _USB_DIEPEMPMSK_DIEPEMPMSK_MASK 0xFFFFUL /**< Bit mask for USB_DIEPEMPMSK */
AnnaBridge 171:3a7713b1edbc 1899 #define _USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEPEMPMSK */
AnnaBridge 171:3a7713b1edbc 1900 #define USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT (_USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEPEMPMSK */
AnnaBridge 171:3a7713b1edbc 1901
AnnaBridge 171:3a7713b1edbc 1902 /* Bit fields for USB DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1903 #define _USB_DIEP0CTL_RESETVALUE 0x00008000UL /**< Default value for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1904 #define _USB_DIEP0CTL_MASK 0xCFEE8003UL /**< Mask for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1905 #define _USB_DIEP0CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */
AnnaBridge 171:3a7713b1edbc 1906 #define _USB_DIEP0CTL_MPS_MASK 0x3UL /**< Bit mask for USB_MPS */
AnnaBridge 171:3a7713b1edbc 1907 #define _USB_DIEP0CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1908 #define _USB_DIEP0CTL_MPS_64B 0x00000000UL /**< Mode 64B for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1909 #define _USB_DIEP0CTL_MPS_32B 0x00000001UL /**< Mode 32B for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1910 #define _USB_DIEP0CTL_MPS_16B 0x00000002UL /**< Mode 16B for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1911 #define _USB_DIEP0CTL_MPS_8B 0x00000003UL /**< Mode 8B for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1912 #define USB_DIEP0CTL_MPS_DEFAULT (_USB_DIEP0CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1913 #define USB_DIEP0CTL_MPS_64B (_USB_DIEP0CTL_MPS_64B << 0) /**< Shifted mode 64B for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1914 #define USB_DIEP0CTL_MPS_32B (_USB_DIEP0CTL_MPS_32B << 0) /**< Shifted mode 32B for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1915 #define USB_DIEP0CTL_MPS_16B (_USB_DIEP0CTL_MPS_16B << 0) /**< Shifted mode 16B for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1916 #define USB_DIEP0CTL_MPS_8B (_USB_DIEP0CTL_MPS_8B << 0) /**< Shifted mode 8B for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1917 #define USB_DIEP0CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */
AnnaBridge 171:3a7713b1edbc 1918 #define _USB_DIEP0CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */
AnnaBridge 171:3a7713b1edbc 1919 #define _USB_DIEP0CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */
AnnaBridge 171:3a7713b1edbc 1920 #define _USB_DIEP0CTL_USBACTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1921 #define USB_DIEP0CTL_USBACTEP_DEFAULT (_USB_DIEP0CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1922 #define USB_DIEP0CTL_NAKSTS (0x1UL << 17) /**< NAK Status */
AnnaBridge 171:3a7713b1edbc 1923 #define _USB_DIEP0CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */
AnnaBridge 171:3a7713b1edbc 1924 #define _USB_DIEP0CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */
AnnaBridge 171:3a7713b1edbc 1925 #define _USB_DIEP0CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1926 #define USB_DIEP0CTL_NAKSTS_DEFAULT (_USB_DIEP0CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1927 #define _USB_DIEP0CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */
AnnaBridge 171:3a7713b1edbc 1928 #define _USB_DIEP0CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */
AnnaBridge 171:3a7713b1edbc 1929 #define _USB_DIEP0CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1930 #define USB_DIEP0CTL_EPTYPE_DEFAULT (_USB_DIEP0CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1931 #define USB_DIEP0CTL_STALL (0x1UL << 21) /**< Handshake */
AnnaBridge 171:3a7713b1edbc 1932 #define _USB_DIEP0CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */
AnnaBridge 171:3a7713b1edbc 1933 #define _USB_DIEP0CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */
AnnaBridge 171:3a7713b1edbc 1934 #define _USB_DIEP0CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1935 #define USB_DIEP0CTL_STALL_DEFAULT (_USB_DIEP0CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1936 #define _USB_DIEP0CTL_TXFNUM_SHIFT 22 /**< Shift value for USB_TXFNUM */
AnnaBridge 171:3a7713b1edbc 1937 #define _USB_DIEP0CTL_TXFNUM_MASK 0x3C00000UL /**< Bit mask for USB_TXFNUM */
AnnaBridge 171:3a7713b1edbc 1938 #define _USB_DIEP0CTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1939 #define USB_DIEP0CTL_TXFNUM_DEFAULT (_USB_DIEP0CTL_TXFNUM_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1940 #define USB_DIEP0CTL_CNAK (0x1UL << 26) /**< Clear NAK */
AnnaBridge 171:3a7713b1edbc 1941 #define _USB_DIEP0CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */
AnnaBridge 171:3a7713b1edbc 1942 #define _USB_DIEP0CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */
AnnaBridge 171:3a7713b1edbc 1943 #define _USB_DIEP0CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1944 #define USB_DIEP0CTL_CNAK_DEFAULT (_USB_DIEP0CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1945 #define USB_DIEP0CTL_SNAK (0x1UL << 27) /**< Set NAK */
AnnaBridge 171:3a7713b1edbc 1946 #define _USB_DIEP0CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */
AnnaBridge 171:3a7713b1edbc 1947 #define _USB_DIEP0CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */
AnnaBridge 171:3a7713b1edbc 1948 #define _USB_DIEP0CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1949 #define USB_DIEP0CTL_SNAK_DEFAULT (_USB_DIEP0CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1950 #define USB_DIEP0CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */
AnnaBridge 171:3a7713b1edbc 1951 #define _USB_DIEP0CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */
AnnaBridge 171:3a7713b1edbc 1952 #define _USB_DIEP0CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */
AnnaBridge 171:3a7713b1edbc 1953 #define _USB_DIEP0CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1954 #define USB_DIEP0CTL_EPDIS_DEFAULT (_USB_DIEP0CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1955 #define USB_DIEP0CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */
AnnaBridge 171:3a7713b1edbc 1956 #define _USB_DIEP0CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */
AnnaBridge 171:3a7713b1edbc 1957 #define _USB_DIEP0CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */
AnnaBridge 171:3a7713b1edbc 1958 #define _USB_DIEP0CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1959 #define USB_DIEP0CTL_EPENA_DEFAULT (_USB_DIEP0CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DIEP0CTL */
AnnaBridge 171:3a7713b1edbc 1960
AnnaBridge 171:3a7713b1edbc 1961 /* Bit fields for USB DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1962 #define _USB_DIEP0INT_RESETVALUE 0x00000080UL /**< Default value for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1963 #define _USB_DIEP0INT_MASK 0x000038DFUL /**< Mask for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1964 #define USB_DIEP0INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */
AnnaBridge 171:3a7713b1edbc 1965 #define _USB_DIEP0INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */
AnnaBridge 171:3a7713b1edbc 1966 #define _USB_DIEP0INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */
AnnaBridge 171:3a7713b1edbc 1967 #define _USB_DIEP0INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1968 #define USB_DIEP0INT_XFERCOMPL_DEFAULT (_USB_DIEP0INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1969 #define USB_DIEP0INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */
AnnaBridge 171:3a7713b1edbc 1970 #define _USB_DIEP0INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */
AnnaBridge 171:3a7713b1edbc 1971 #define _USB_DIEP0INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */
AnnaBridge 171:3a7713b1edbc 1972 #define _USB_DIEP0INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1973 #define USB_DIEP0INT_EPDISBLD_DEFAULT (_USB_DIEP0INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1974 #define USB_DIEP0INT_AHBERR (0x1UL << 2) /**< AHB Error */
AnnaBridge 171:3a7713b1edbc 1975 #define _USB_DIEP0INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */
AnnaBridge 171:3a7713b1edbc 1976 #define _USB_DIEP0INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */
AnnaBridge 171:3a7713b1edbc 1977 #define _USB_DIEP0INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1978 #define USB_DIEP0INT_AHBERR_DEFAULT (_USB_DIEP0INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1979 #define USB_DIEP0INT_TIMEOUT (0x1UL << 3) /**< Timeout Condition */
AnnaBridge 171:3a7713b1edbc 1980 #define _USB_DIEP0INT_TIMEOUT_SHIFT 3 /**< Shift value for USB_TIMEOUT */
AnnaBridge 171:3a7713b1edbc 1981 #define _USB_DIEP0INT_TIMEOUT_MASK 0x8UL /**< Bit mask for USB_TIMEOUT */
AnnaBridge 171:3a7713b1edbc 1982 #define _USB_DIEP0INT_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1983 #define USB_DIEP0INT_TIMEOUT_DEFAULT (_USB_DIEP0INT_TIMEOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1984 #define USB_DIEP0INT_INTKNTXFEMP (0x1UL << 4) /**< IN Token Received When TxFIFO is Empty */
AnnaBridge 171:3a7713b1edbc 1985 #define _USB_DIEP0INT_INTKNTXFEMP_SHIFT 4 /**< Shift value for USB_INTKNTXFEMP */
AnnaBridge 171:3a7713b1edbc 1986 #define _USB_DIEP0INT_INTKNTXFEMP_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMP */
AnnaBridge 171:3a7713b1edbc 1987 #define _USB_DIEP0INT_INTKNTXFEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1988 #define USB_DIEP0INT_INTKNTXFEMP_DEFAULT (_USB_DIEP0INT_INTKNTXFEMP_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1989 #define USB_DIEP0INT_INEPNAKEFF (0x1UL << 6) /**< IN Endpoint NAK Effective */
AnnaBridge 171:3a7713b1edbc 1990 #define _USB_DIEP0INT_INEPNAKEFF_SHIFT 6 /**< Shift value for USB_INEPNAKEFF */
AnnaBridge 171:3a7713b1edbc 1991 #define _USB_DIEP0INT_INEPNAKEFF_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFF */
AnnaBridge 171:3a7713b1edbc 1992 #define _USB_DIEP0INT_INEPNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1993 #define USB_DIEP0INT_INEPNAKEFF_DEFAULT (_USB_DIEP0INT_INEPNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1994 #define USB_DIEP0INT_TXFEMP (0x1UL << 7) /**< Transmit FIFO Empty */
AnnaBridge 171:3a7713b1edbc 1995 #define _USB_DIEP0INT_TXFEMP_SHIFT 7 /**< Shift value for USB_TXFEMP */
AnnaBridge 171:3a7713b1edbc 1996 #define _USB_DIEP0INT_TXFEMP_MASK 0x80UL /**< Bit mask for USB_TXFEMP */
AnnaBridge 171:3a7713b1edbc 1997 #define _USB_DIEP0INT_TXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1998 #define USB_DIEP0INT_TXFEMP_DEFAULT (_USB_DIEP0INT_TXFEMP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 1999 #define USB_DIEP0INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */
AnnaBridge 171:3a7713b1edbc 2000 #define _USB_DIEP0INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */
AnnaBridge 171:3a7713b1edbc 2001 #define _USB_DIEP0INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */
AnnaBridge 171:3a7713b1edbc 2002 #define _USB_DIEP0INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 2003 #define USB_DIEP0INT_PKTDRPSTS_DEFAULT (_USB_DIEP0INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 2004 #define USB_DIEP0INT_BBLEERR (0x1UL << 12) /**< NAK Interrupt */
AnnaBridge 171:3a7713b1edbc 2005 #define _USB_DIEP0INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */
AnnaBridge 171:3a7713b1edbc 2006 #define _USB_DIEP0INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */
AnnaBridge 171:3a7713b1edbc 2007 #define _USB_DIEP0INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 2008 #define USB_DIEP0INT_BBLEERR_DEFAULT (_USB_DIEP0INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 2009 #define USB_DIEP0INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */
AnnaBridge 171:3a7713b1edbc 2010 #define _USB_DIEP0INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */
AnnaBridge 171:3a7713b1edbc 2011 #define _USB_DIEP0INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */
AnnaBridge 171:3a7713b1edbc 2012 #define _USB_DIEP0INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 2013 #define USB_DIEP0INT_NAKINTRPT_DEFAULT (_USB_DIEP0INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEP0INT */
AnnaBridge 171:3a7713b1edbc 2014
AnnaBridge 171:3a7713b1edbc 2015 /* Bit fields for USB DIEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2016 #define _USB_DIEP0TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2017 #define _USB_DIEP0TSIZ_MASK 0x0018007FUL /**< Mask for USB_DIEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2018 #define _USB_DIEP0TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */
AnnaBridge 171:3a7713b1edbc 2019 #define _USB_DIEP0TSIZ_XFERSIZE_MASK 0x7FUL /**< Bit mask for USB_XFERSIZE */
AnnaBridge 171:3a7713b1edbc 2020 #define _USB_DIEP0TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2021 #define USB_DIEP0TSIZ_XFERSIZE_DEFAULT (_USB_DIEP0TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2022 #define _USB_DIEP0TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */
AnnaBridge 171:3a7713b1edbc 2023 #define _USB_DIEP0TSIZ_PKTCNT_MASK 0x180000UL /**< Bit mask for USB_PKTCNT */
AnnaBridge 171:3a7713b1edbc 2024 #define _USB_DIEP0TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2025 #define USB_DIEP0TSIZ_PKTCNT_DEFAULT (_USB_DIEP0TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DIEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2026
AnnaBridge 171:3a7713b1edbc 2027 /* Bit fields for USB DIEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2028 #define _USB_DIEP0DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2029 #define _USB_DIEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DIEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2030 #define _USB_DIEP0DMAADDR_DIEP0DMAADDR_SHIFT 0 /**< Shift value for USB_DIEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2031 #define _USB_DIEP0DMAADDR_DIEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DIEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2032 #define _USB_DIEP0DMAADDR_DIEP0DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2033 #define USB_DIEP0DMAADDR_DIEP0DMAADDR_DEFAULT (_USB_DIEP0DMAADDR_DIEP0DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2034
AnnaBridge 171:3a7713b1edbc 2035 /* Bit fields for USB DIEP0TXFSTS */
AnnaBridge 171:3a7713b1edbc 2036 #define _USB_DIEP0TXFSTS_RESETVALUE 0x00000200UL /**< Default value for USB_DIEP0TXFSTS */
AnnaBridge 171:3a7713b1edbc 2037 #define _USB_DIEP0TXFSTS_MASK 0x0000FFFFUL /**< Mask for USB_DIEP0TXFSTS */
AnnaBridge 171:3a7713b1edbc 2038 #define _USB_DIEP0TXFSTS_SPCAVAIL_SHIFT 0 /**< Shift value for USB_SPCAVAIL */
AnnaBridge 171:3a7713b1edbc 2039 #define _USB_DIEP0TXFSTS_SPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_SPCAVAIL */
AnnaBridge 171:3a7713b1edbc 2040 #define _USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEP0TXFSTS */
AnnaBridge 171:3a7713b1edbc 2041 #define USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT (_USB_DIEP0TXFSTS_SPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP0TXFSTS */
AnnaBridge 171:3a7713b1edbc 2042
AnnaBridge 171:3a7713b1edbc 2043 /* Bit fields for USB DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2044 #define _USB_DIEP_CTL_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2045 #define _USB_DIEP_CTL_MASK 0xFFEF87FFUL /**< Mask for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2046 #define _USB_DIEP_CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */
AnnaBridge 171:3a7713b1edbc 2047 #define _USB_DIEP_CTL_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */
AnnaBridge 171:3a7713b1edbc 2048 #define _USB_DIEP_CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2049 #define USB_DIEP_CTL_MPS_DEFAULT (_USB_DIEP_CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2050 #define USB_DIEP_CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */
AnnaBridge 171:3a7713b1edbc 2051 #define _USB_DIEP_CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */
AnnaBridge 171:3a7713b1edbc 2052 #define _USB_DIEP_CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */
AnnaBridge 171:3a7713b1edbc 2053 #define _USB_DIEP_CTL_USBACTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2054 #define USB_DIEP_CTL_USBACTEP_DEFAULT (_USB_DIEP_CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2055 #define USB_DIEP_CTL_DPIDEOF (0x1UL << 16) /**< Endpoint Data PID / Even or Odd Frame */
AnnaBridge 171:3a7713b1edbc 2056 #define _USB_DIEP_CTL_DPIDEOF_SHIFT 16 /**< Shift value for USB_DPIDEOF */
AnnaBridge 171:3a7713b1edbc 2057 #define _USB_DIEP_CTL_DPIDEOF_MASK 0x10000UL /**< Bit mask for USB_DPIDEOF */
AnnaBridge 171:3a7713b1edbc 2058 #define _USB_DIEP_CTL_DPIDEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2059 #define _USB_DIEP_CTL_DPIDEOF_DATA0EVEN 0x00000000UL /**< Mode DATA0EVEN for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2060 #define _USB_DIEP_CTL_DPIDEOF_DATA1ODD 0x00000001UL /**< Mode DATA1ODD for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2061 #define USB_DIEP_CTL_DPIDEOF_DEFAULT (_USB_DIEP_CTL_DPIDEOF_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2062 #define USB_DIEP_CTL_DPIDEOF_DATA0EVEN (_USB_DIEP_CTL_DPIDEOF_DATA0EVEN << 16) /**< Shifted mode DATA0EVEN for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2063 #define USB_DIEP_CTL_DPIDEOF_DATA1ODD (_USB_DIEP_CTL_DPIDEOF_DATA1ODD << 16) /**< Shifted mode DATA1ODD for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2064 #define USB_DIEP_CTL_NAKSTS (0x1UL << 17) /**< NAK Status */
AnnaBridge 171:3a7713b1edbc 2065 #define _USB_DIEP_CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */
AnnaBridge 171:3a7713b1edbc 2066 #define _USB_DIEP_CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */
AnnaBridge 171:3a7713b1edbc 2067 #define _USB_DIEP_CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2068 #define USB_DIEP_CTL_NAKSTS_DEFAULT (_USB_DIEP_CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2069 #define _USB_DIEP_CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */
AnnaBridge 171:3a7713b1edbc 2070 #define _USB_DIEP_CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */
AnnaBridge 171:3a7713b1edbc 2071 #define _USB_DIEP_CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2072 #define _USB_DIEP_CTL_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2073 #define _USB_DIEP_CTL_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2074 #define _USB_DIEP_CTL_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2075 #define _USB_DIEP_CTL_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2076 #define USB_DIEP_CTL_EPTYPE_DEFAULT (_USB_DIEP_CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2077 #define USB_DIEP_CTL_EPTYPE_CONTROL (_USB_DIEP_CTL_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2078 #define USB_DIEP_CTL_EPTYPE_ISO (_USB_DIEP_CTL_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2079 #define USB_DIEP_CTL_EPTYPE_BULK (_USB_DIEP_CTL_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2080 #define USB_DIEP_CTL_EPTYPE_INT (_USB_DIEP_CTL_EPTYPE_INT << 18) /**< Shifted mode INT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2081 #define USB_DIEP_CTL_STALL (0x1UL << 21) /**< Handshake */
AnnaBridge 171:3a7713b1edbc 2082 #define _USB_DIEP_CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */
AnnaBridge 171:3a7713b1edbc 2083 #define _USB_DIEP_CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */
AnnaBridge 171:3a7713b1edbc 2084 #define _USB_DIEP_CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2085 #define USB_DIEP_CTL_STALL_DEFAULT (_USB_DIEP_CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2086 #define _USB_DIEP_CTL_TXFNUM_SHIFT 22 /**< Shift value for USB_TXFNUM */
AnnaBridge 171:3a7713b1edbc 2087 #define _USB_DIEP_CTL_TXFNUM_MASK 0x3C00000UL /**< Bit mask for USB_TXFNUM */
AnnaBridge 171:3a7713b1edbc 2088 #define _USB_DIEP_CTL_TXFNUM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2089 #define USB_DIEP_CTL_TXFNUM_DEFAULT (_USB_DIEP_CTL_TXFNUM_DEFAULT << 22) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2090 #define USB_DIEP_CTL_CNAK (0x1UL << 26) /**< Clear NAK */
AnnaBridge 171:3a7713b1edbc 2091 #define _USB_DIEP_CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */
AnnaBridge 171:3a7713b1edbc 2092 #define _USB_DIEP_CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */
AnnaBridge 171:3a7713b1edbc 2093 #define _USB_DIEP_CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2094 #define USB_DIEP_CTL_CNAK_DEFAULT (_USB_DIEP_CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2095 #define USB_DIEP_CTL_SNAK (0x1UL << 27) /**< Set NAK */
AnnaBridge 171:3a7713b1edbc 2096 #define _USB_DIEP_CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */
AnnaBridge 171:3a7713b1edbc 2097 #define _USB_DIEP_CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */
AnnaBridge 171:3a7713b1edbc 2098 #define _USB_DIEP_CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2099 #define USB_DIEP_CTL_SNAK_DEFAULT (_USB_DIEP_CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2100 #define USB_DIEP_CTL_SETD0PIDEF (0x1UL << 28) /**< Set DATA0 PID / Even Frame */
AnnaBridge 171:3a7713b1edbc 2101 #define _USB_DIEP_CTL_SETD0PIDEF_SHIFT 28 /**< Shift value for USB_SETD0PIDEF */
AnnaBridge 171:3a7713b1edbc 2102 #define _USB_DIEP_CTL_SETD0PIDEF_MASK 0x10000000UL /**< Bit mask for USB_SETD0PIDEF */
AnnaBridge 171:3a7713b1edbc 2103 #define _USB_DIEP_CTL_SETD0PIDEF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2104 #define USB_DIEP_CTL_SETD0PIDEF_DEFAULT (_USB_DIEP_CTL_SETD0PIDEF_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2105 #define USB_DIEP_CTL_SETD1PIDOF (0x1UL << 29) /**< Set DATA1 PID / Odd Frame */
AnnaBridge 171:3a7713b1edbc 2106 #define _USB_DIEP_CTL_SETD1PIDOF_SHIFT 29 /**< Shift value for USB_SETD1PIDOF */
AnnaBridge 171:3a7713b1edbc 2107 #define _USB_DIEP_CTL_SETD1PIDOF_MASK 0x20000000UL /**< Bit mask for USB_SETD1PIDOF */
AnnaBridge 171:3a7713b1edbc 2108 #define _USB_DIEP_CTL_SETD1PIDOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2109 #define USB_DIEP_CTL_SETD1PIDOF_DEFAULT (_USB_DIEP_CTL_SETD1PIDOF_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2110 #define USB_DIEP_CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */
AnnaBridge 171:3a7713b1edbc 2111 #define _USB_DIEP_CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */
AnnaBridge 171:3a7713b1edbc 2112 #define _USB_DIEP_CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */
AnnaBridge 171:3a7713b1edbc 2113 #define _USB_DIEP_CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2114 #define USB_DIEP_CTL_EPDIS_DEFAULT (_USB_DIEP_CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2115 #define USB_DIEP_CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */
AnnaBridge 171:3a7713b1edbc 2116 #define _USB_DIEP_CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */
AnnaBridge 171:3a7713b1edbc 2117 #define _USB_DIEP_CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */
AnnaBridge 171:3a7713b1edbc 2118 #define _USB_DIEP_CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2119 #define USB_DIEP_CTL_EPENA_DEFAULT (_USB_DIEP_CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DIEP_CTL */
AnnaBridge 171:3a7713b1edbc 2120
AnnaBridge 171:3a7713b1edbc 2121 /* Bit fields for USB DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2122 #define _USB_DIEP_INT_RESETVALUE 0x00000080UL /**< Default value for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2123 #define _USB_DIEP_INT_MASK 0x000038DFUL /**< Mask for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2124 #define USB_DIEP_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */
AnnaBridge 171:3a7713b1edbc 2125 #define _USB_DIEP_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */
AnnaBridge 171:3a7713b1edbc 2126 #define _USB_DIEP_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */
AnnaBridge 171:3a7713b1edbc 2127 #define _USB_DIEP_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2128 #define USB_DIEP_INT_XFERCOMPL_DEFAULT (_USB_DIEP_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2129 #define USB_DIEP_INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */
AnnaBridge 171:3a7713b1edbc 2130 #define _USB_DIEP_INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */
AnnaBridge 171:3a7713b1edbc 2131 #define _USB_DIEP_INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */
AnnaBridge 171:3a7713b1edbc 2132 #define _USB_DIEP_INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2133 #define USB_DIEP_INT_EPDISBLD_DEFAULT (_USB_DIEP_INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2134 #define USB_DIEP_INT_AHBERR (0x1UL << 2) /**< AHB Error */
AnnaBridge 171:3a7713b1edbc 2135 #define _USB_DIEP_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */
AnnaBridge 171:3a7713b1edbc 2136 #define _USB_DIEP_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */
AnnaBridge 171:3a7713b1edbc 2137 #define _USB_DIEP_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2138 #define USB_DIEP_INT_AHBERR_DEFAULT (_USB_DIEP_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2139 #define USB_DIEP_INT_TIMEOUT (0x1UL << 3) /**< Timeout Condition */
AnnaBridge 171:3a7713b1edbc 2140 #define _USB_DIEP_INT_TIMEOUT_SHIFT 3 /**< Shift value for USB_TIMEOUT */
AnnaBridge 171:3a7713b1edbc 2141 #define _USB_DIEP_INT_TIMEOUT_MASK 0x8UL /**< Bit mask for USB_TIMEOUT */
AnnaBridge 171:3a7713b1edbc 2142 #define _USB_DIEP_INT_TIMEOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2143 #define USB_DIEP_INT_TIMEOUT_DEFAULT (_USB_DIEP_INT_TIMEOUT_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2144 #define USB_DIEP_INT_INTKNTXFEMP (0x1UL << 4) /**< IN Token Received When TxFIFO is Empty */
AnnaBridge 171:3a7713b1edbc 2145 #define _USB_DIEP_INT_INTKNTXFEMP_SHIFT 4 /**< Shift value for USB_INTKNTXFEMP */
AnnaBridge 171:3a7713b1edbc 2146 #define _USB_DIEP_INT_INTKNTXFEMP_MASK 0x10UL /**< Bit mask for USB_INTKNTXFEMP */
AnnaBridge 171:3a7713b1edbc 2147 #define _USB_DIEP_INT_INTKNTXFEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2148 #define USB_DIEP_INT_INTKNTXFEMP_DEFAULT (_USB_DIEP_INT_INTKNTXFEMP_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2149 #define USB_DIEP_INT_INEPNAKEFF (0x1UL << 6) /**< IN Endpoint NAK Effective */
AnnaBridge 171:3a7713b1edbc 2150 #define _USB_DIEP_INT_INEPNAKEFF_SHIFT 6 /**< Shift value for USB_INEPNAKEFF */
AnnaBridge 171:3a7713b1edbc 2151 #define _USB_DIEP_INT_INEPNAKEFF_MASK 0x40UL /**< Bit mask for USB_INEPNAKEFF */
AnnaBridge 171:3a7713b1edbc 2152 #define _USB_DIEP_INT_INEPNAKEFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2153 #define USB_DIEP_INT_INEPNAKEFF_DEFAULT (_USB_DIEP_INT_INEPNAKEFF_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2154 #define USB_DIEP_INT_TXFEMP (0x1UL << 7) /**< Transmit FIFO Empty */
AnnaBridge 171:3a7713b1edbc 2155 #define _USB_DIEP_INT_TXFEMP_SHIFT 7 /**< Shift value for USB_TXFEMP */
AnnaBridge 171:3a7713b1edbc 2156 #define _USB_DIEP_INT_TXFEMP_MASK 0x80UL /**< Bit mask for USB_TXFEMP */
AnnaBridge 171:3a7713b1edbc 2157 #define _USB_DIEP_INT_TXFEMP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2158 #define USB_DIEP_INT_TXFEMP_DEFAULT (_USB_DIEP_INT_TXFEMP_DEFAULT << 7) /**< Shifted mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2159 #define USB_DIEP_INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */
AnnaBridge 171:3a7713b1edbc 2160 #define _USB_DIEP_INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */
AnnaBridge 171:3a7713b1edbc 2161 #define _USB_DIEP_INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */
AnnaBridge 171:3a7713b1edbc 2162 #define _USB_DIEP_INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2163 #define USB_DIEP_INT_PKTDRPSTS_DEFAULT (_USB_DIEP_INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2164 #define USB_DIEP_INT_BBLEERR (0x1UL << 12) /**< NAK Interrupt */
AnnaBridge 171:3a7713b1edbc 2165 #define _USB_DIEP_INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */
AnnaBridge 171:3a7713b1edbc 2166 #define _USB_DIEP_INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */
AnnaBridge 171:3a7713b1edbc 2167 #define _USB_DIEP_INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2168 #define USB_DIEP_INT_BBLEERR_DEFAULT (_USB_DIEP_INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2169 #define USB_DIEP_INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */
AnnaBridge 171:3a7713b1edbc 2170 #define _USB_DIEP_INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */
AnnaBridge 171:3a7713b1edbc 2171 #define _USB_DIEP_INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */
AnnaBridge 171:3a7713b1edbc 2172 #define _USB_DIEP_INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2173 #define USB_DIEP_INT_NAKINTRPT_DEFAULT (_USB_DIEP_INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DIEP_INT */
AnnaBridge 171:3a7713b1edbc 2174
AnnaBridge 171:3a7713b1edbc 2175 /* Bit fields for USB DIEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2176 #define _USB_DIEP_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2177 #define _USB_DIEP_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_DIEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2178 #define _USB_DIEP_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */
AnnaBridge 171:3a7713b1edbc 2179 #define _USB_DIEP_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */
AnnaBridge 171:3a7713b1edbc 2180 #define _USB_DIEP_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2181 #define USB_DIEP_TSIZ_XFERSIZE_DEFAULT (_USB_DIEP_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2182 #define _USB_DIEP_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */
AnnaBridge 171:3a7713b1edbc 2183 #define _USB_DIEP_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */
AnnaBridge 171:3a7713b1edbc 2184 #define _USB_DIEP_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2185 #define USB_DIEP_TSIZ_PKTCNT_DEFAULT (_USB_DIEP_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2186 #define _USB_DIEP_TSIZ_MC_SHIFT 29 /**< Shift value for USB_MC */
AnnaBridge 171:3a7713b1edbc 2187 #define _USB_DIEP_TSIZ_MC_MASK 0x60000000UL /**< Bit mask for USB_MC */
AnnaBridge 171:3a7713b1edbc 2188 #define _USB_DIEP_TSIZ_MC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2189 #define USB_DIEP_TSIZ_MC_DEFAULT (_USB_DIEP_TSIZ_MC_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DIEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2190
AnnaBridge 171:3a7713b1edbc 2191 /* Bit fields for USB DIEP_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2192 #define _USB_DIEP_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DIEP_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2193 #define _USB_DIEP_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DIEP_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2194 #define _USB_DIEP_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2195 #define _USB_DIEP_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2196 #define _USB_DIEP_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DIEP_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2197 #define USB_DIEP_DMAADDR_DMAADDR_DEFAULT (_USB_DIEP_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2198
AnnaBridge 171:3a7713b1edbc 2199 /* Bit fields for USB DIEP_TXFSTS */
AnnaBridge 171:3a7713b1edbc 2200 #define _USB_DIEP_TXFSTS_RESETVALUE 0x00000200UL /**< Default value for USB_DIEP_TXFSTS */
AnnaBridge 171:3a7713b1edbc 2201 #define _USB_DIEP_TXFSTS_MASK 0x0000FFFFUL /**< Mask for USB_DIEP_TXFSTS */
AnnaBridge 171:3a7713b1edbc 2202 #define _USB_DIEP_TXFSTS_SPCAVAIL_SHIFT 0 /**< Shift value for USB_SPCAVAIL */
AnnaBridge 171:3a7713b1edbc 2203 #define _USB_DIEP_TXFSTS_SPCAVAIL_MASK 0xFFFFUL /**< Bit mask for USB_SPCAVAIL */
AnnaBridge 171:3a7713b1edbc 2204 #define _USB_DIEP_TXFSTS_SPCAVAIL_DEFAULT 0x00000200UL /**< Mode DEFAULT for USB_DIEP_TXFSTS */
AnnaBridge 171:3a7713b1edbc 2205 #define USB_DIEP_TXFSTS_SPCAVAIL_DEFAULT (_USB_DIEP_TXFSTS_SPCAVAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DIEP_TXFSTS */
AnnaBridge 171:3a7713b1edbc 2206
AnnaBridge 171:3a7713b1edbc 2207 /* Bit fields for USB DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2208 #define _USB_DOEP0CTL_RESETVALUE 0x00008000UL /**< Default value for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2209 #define _USB_DOEP0CTL_MASK 0xCC3E8003UL /**< Mask for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2210 #define _USB_DOEP0CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */
AnnaBridge 171:3a7713b1edbc 2211 #define _USB_DOEP0CTL_MPS_MASK 0x3UL /**< Bit mask for USB_MPS */
AnnaBridge 171:3a7713b1edbc 2212 #define _USB_DOEP0CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2213 #define _USB_DOEP0CTL_MPS_64B 0x00000000UL /**< Mode 64B for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2214 #define _USB_DOEP0CTL_MPS_32B 0x00000001UL /**< Mode 32B for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2215 #define _USB_DOEP0CTL_MPS_16B 0x00000002UL /**< Mode 16B for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2216 #define _USB_DOEP0CTL_MPS_8B 0x00000003UL /**< Mode 8B for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2217 #define USB_DOEP0CTL_MPS_DEFAULT (_USB_DOEP0CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2218 #define USB_DOEP0CTL_MPS_64B (_USB_DOEP0CTL_MPS_64B << 0) /**< Shifted mode 64B for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2219 #define USB_DOEP0CTL_MPS_32B (_USB_DOEP0CTL_MPS_32B << 0) /**< Shifted mode 32B for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2220 #define USB_DOEP0CTL_MPS_16B (_USB_DOEP0CTL_MPS_16B << 0) /**< Shifted mode 16B for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2221 #define USB_DOEP0CTL_MPS_8B (_USB_DOEP0CTL_MPS_8B << 0) /**< Shifted mode 8B for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2222 #define USB_DOEP0CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */
AnnaBridge 171:3a7713b1edbc 2223 #define _USB_DOEP0CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */
AnnaBridge 171:3a7713b1edbc 2224 #define _USB_DOEP0CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */
AnnaBridge 171:3a7713b1edbc 2225 #define _USB_DOEP0CTL_USBACTEP_DEFAULT 0x00000001UL /**< Mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2226 #define USB_DOEP0CTL_USBACTEP_DEFAULT (_USB_DOEP0CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2227 #define USB_DOEP0CTL_NAKSTS (0x1UL << 17) /**< NAK Status */
AnnaBridge 171:3a7713b1edbc 2228 #define _USB_DOEP0CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */
AnnaBridge 171:3a7713b1edbc 2229 #define _USB_DOEP0CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */
AnnaBridge 171:3a7713b1edbc 2230 #define _USB_DOEP0CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2231 #define USB_DOEP0CTL_NAKSTS_DEFAULT (_USB_DOEP0CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2232 #define _USB_DOEP0CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */
AnnaBridge 171:3a7713b1edbc 2233 #define _USB_DOEP0CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */
AnnaBridge 171:3a7713b1edbc 2234 #define _USB_DOEP0CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2235 #define USB_DOEP0CTL_EPTYPE_DEFAULT (_USB_DOEP0CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2236 #define USB_DOEP0CTL_SNP (0x1UL << 20) /**< Snoop Mode */
AnnaBridge 171:3a7713b1edbc 2237 #define _USB_DOEP0CTL_SNP_SHIFT 20 /**< Shift value for USB_SNP */
AnnaBridge 171:3a7713b1edbc 2238 #define _USB_DOEP0CTL_SNP_MASK 0x100000UL /**< Bit mask for USB_SNP */
AnnaBridge 171:3a7713b1edbc 2239 #define _USB_DOEP0CTL_SNP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2240 #define USB_DOEP0CTL_SNP_DEFAULT (_USB_DOEP0CTL_SNP_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2241 #define USB_DOEP0CTL_STALL (0x1UL << 21) /**< Handshake */
AnnaBridge 171:3a7713b1edbc 2242 #define _USB_DOEP0CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */
AnnaBridge 171:3a7713b1edbc 2243 #define _USB_DOEP0CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */
AnnaBridge 171:3a7713b1edbc 2244 #define _USB_DOEP0CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2245 #define USB_DOEP0CTL_STALL_DEFAULT (_USB_DOEP0CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2246 #define USB_DOEP0CTL_CNAK (0x1UL << 26) /**< Clear NAK */
AnnaBridge 171:3a7713b1edbc 2247 #define _USB_DOEP0CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */
AnnaBridge 171:3a7713b1edbc 2248 #define _USB_DOEP0CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */
AnnaBridge 171:3a7713b1edbc 2249 #define _USB_DOEP0CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2250 #define USB_DOEP0CTL_CNAK_DEFAULT (_USB_DOEP0CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2251 #define USB_DOEP0CTL_SNAK (0x1UL << 27) /**< Set NAK */
AnnaBridge 171:3a7713b1edbc 2252 #define _USB_DOEP0CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */
AnnaBridge 171:3a7713b1edbc 2253 #define _USB_DOEP0CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */
AnnaBridge 171:3a7713b1edbc 2254 #define _USB_DOEP0CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2255 #define USB_DOEP0CTL_SNAK_DEFAULT (_USB_DOEP0CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2256 #define USB_DOEP0CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */
AnnaBridge 171:3a7713b1edbc 2257 #define _USB_DOEP0CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */
AnnaBridge 171:3a7713b1edbc 2258 #define _USB_DOEP0CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */
AnnaBridge 171:3a7713b1edbc 2259 #define _USB_DOEP0CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2260 #define USB_DOEP0CTL_EPDIS_DEFAULT (_USB_DOEP0CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2261 #define USB_DOEP0CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */
AnnaBridge 171:3a7713b1edbc 2262 #define _USB_DOEP0CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */
AnnaBridge 171:3a7713b1edbc 2263 #define _USB_DOEP0CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */
AnnaBridge 171:3a7713b1edbc 2264 #define _USB_DOEP0CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2265 #define USB_DOEP0CTL_EPENA_DEFAULT (_USB_DOEP0CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DOEP0CTL */
AnnaBridge 171:3a7713b1edbc 2266
AnnaBridge 171:3a7713b1edbc 2267 /* Bit fields for USB DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2268 #define _USB_DOEP0INT_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2269 #define _USB_DOEP0INT_MASK 0x0000385FUL /**< Mask for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2270 #define USB_DOEP0INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */
AnnaBridge 171:3a7713b1edbc 2271 #define _USB_DOEP0INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */
AnnaBridge 171:3a7713b1edbc 2272 #define _USB_DOEP0INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */
AnnaBridge 171:3a7713b1edbc 2273 #define _USB_DOEP0INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2274 #define USB_DOEP0INT_XFERCOMPL_DEFAULT (_USB_DOEP0INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2275 #define USB_DOEP0INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */
AnnaBridge 171:3a7713b1edbc 2276 #define _USB_DOEP0INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */
AnnaBridge 171:3a7713b1edbc 2277 #define _USB_DOEP0INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */
AnnaBridge 171:3a7713b1edbc 2278 #define _USB_DOEP0INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2279 #define USB_DOEP0INT_EPDISBLD_DEFAULT (_USB_DOEP0INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2280 #define USB_DOEP0INT_AHBERR (0x1UL << 2) /**< AHB Error */
AnnaBridge 171:3a7713b1edbc 2281 #define _USB_DOEP0INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */
AnnaBridge 171:3a7713b1edbc 2282 #define _USB_DOEP0INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */
AnnaBridge 171:3a7713b1edbc 2283 #define _USB_DOEP0INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2284 #define USB_DOEP0INT_AHBERR_DEFAULT (_USB_DOEP0INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2285 #define USB_DOEP0INT_SETUP (0x1UL << 3) /**< Setup Phase Done */
AnnaBridge 171:3a7713b1edbc 2286 #define _USB_DOEP0INT_SETUP_SHIFT 3 /**< Shift value for USB_SETUP */
AnnaBridge 171:3a7713b1edbc 2287 #define _USB_DOEP0INT_SETUP_MASK 0x8UL /**< Bit mask for USB_SETUP */
AnnaBridge 171:3a7713b1edbc 2288 #define _USB_DOEP0INT_SETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2289 #define USB_DOEP0INT_SETUP_DEFAULT (_USB_DOEP0INT_SETUP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2290 #define USB_DOEP0INT_OUTTKNEPDIS (0x1UL << 4) /**< OUT Token Received When Endpoint Disabled */
AnnaBridge 171:3a7713b1edbc 2291 #define _USB_DOEP0INT_OUTTKNEPDIS_SHIFT 4 /**< Shift value for USB_OUTTKNEPDIS */
AnnaBridge 171:3a7713b1edbc 2292 #define _USB_DOEP0INT_OUTTKNEPDIS_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDIS */
AnnaBridge 171:3a7713b1edbc 2293 #define _USB_DOEP0INT_OUTTKNEPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2294 #define USB_DOEP0INT_OUTTKNEPDIS_DEFAULT (_USB_DOEP0INT_OUTTKNEPDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2295 #define USB_DOEP0INT_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received */
AnnaBridge 171:3a7713b1edbc 2296 #define _USB_DOEP0INT_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */
AnnaBridge 171:3a7713b1edbc 2297 #define _USB_DOEP0INT_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */
AnnaBridge 171:3a7713b1edbc 2298 #define _USB_DOEP0INT_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2299 #define USB_DOEP0INT_BACK2BACKSETUP_DEFAULT (_USB_DOEP0INT_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2300 #define USB_DOEP0INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */
AnnaBridge 171:3a7713b1edbc 2301 #define _USB_DOEP0INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */
AnnaBridge 171:3a7713b1edbc 2302 #define _USB_DOEP0INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */
AnnaBridge 171:3a7713b1edbc 2303 #define _USB_DOEP0INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2304 #define USB_DOEP0INT_PKTDRPSTS_DEFAULT (_USB_DOEP0INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2305 #define USB_DOEP0INT_BBLEERR (0x1UL << 12) /**< NAK Interrupt */
AnnaBridge 171:3a7713b1edbc 2306 #define _USB_DOEP0INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */
AnnaBridge 171:3a7713b1edbc 2307 #define _USB_DOEP0INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */
AnnaBridge 171:3a7713b1edbc 2308 #define _USB_DOEP0INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2309 #define USB_DOEP0INT_BBLEERR_DEFAULT (_USB_DOEP0INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2310 #define USB_DOEP0INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */
AnnaBridge 171:3a7713b1edbc 2311 #define _USB_DOEP0INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */
AnnaBridge 171:3a7713b1edbc 2312 #define _USB_DOEP0INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */
AnnaBridge 171:3a7713b1edbc 2313 #define _USB_DOEP0INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2314 #define USB_DOEP0INT_NAKINTRPT_DEFAULT (_USB_DOEP0INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEP0INT */
AnnaBridge 171:3a7713b1edbc 2315
AnnaBridge 171:3a7713b1edbc 2316 /* Bit fields for USB DOEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2317 #define _USB_DOEP0TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2318 #define _USB_DOEP0TSIZ_MASK 0x6008007FUL /**< Mask for USB_DOEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2319 #define _USB_DOEP0TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */
AnnaBridge 171:3a7713b1edbc 2320 #define _USB_DOEP0TSIZ_XFERSIZE_MASK 0x7FUL /**< Bit mask for USB_XFERSIZE */
AnnaBridge 171:3a7713b1edbc 2321 #define _USB_DOEP0TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2322 #define USB_DOEP0TSIZ_XFERSIZE_DEFAULT (_USB_DOEP0TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2323 #define USB_DOEP0TSIZ_PKTCNT (0x1UL << 19) /**< Packet Count */
AnnaBridge 171:3a7713b1edbc 2324 #define _USB_DOEP0TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */
AnnaBridge 171:3a7713b1edbc 2325 #define _USB_DOEP0TSIZ_PKTCNT_MASK 0x80000UL /**< Bit mask for USB_PKTCNT */
AnnaBridge 171:3a7713b1edbc 2326 #define _USB_DOEP0TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2327 #define USB_DOEP0TSIZ_PKTCNT_DEFAULT (_USB_DOEP0TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2328 #define _USB_DOEP0TSIZ_SUPCNT_SHIFT 29 /**< Shift value for USB_SUPCNT */
AnnaBridge 171:3a7713b1edbc 2329 #define _USB_DOEP0TSIZ_SUPCNT_MASK 0x60000000UL /**< Bit mask for USB_SUPCNT */
AnnaBridge 171:3a7713b1edbc 2330 #define _USB_DOEP0TSIZ_SUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2331 #define USB_DOEP0TSIZ_SUPCNT_DEFAULT (_USB_DOEP0TSIZ_SUPCNT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP0TSIZ */
AnnaBridge 171:3a7713b1edbc 2332
AnnaBridge 171:3a7713b1edbc 2333 /* Bit fields for USB DOEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2334 #define _USB_DOEP0DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2335 #define _USB_DOEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DOEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2336 #define _USB_DOEP0DMAADDR_DOEP0DMAADDR_SHIFT 0 /**< Shift value for USB_DOEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2337 #define _USB_DOEP0DMAADDR_DOEP0DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DOEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2338 #define _USB_DOEP0DMAADDR_DOEP0DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2339 #define USB_DOEP0DMAADDR_DOEP0DMAADDR_DEFAULT (_USB_DOEP0DMAADDR_DOEP0DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP0DMAADDR */
AnnaBridge 171:3a7713b1edbc 2340
AnnaBridge 171:3a7713b1edbc 2341 /* Bit fields for USB DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2342 #define _USB_DOEP_CTL_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2343 #define _USB_DOEP_CTL_MASK 0xFC3F87FFUL /**< Mask for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2344 #define _USB_DOEP_CTL_MPS_SHIFT 0 /**< Shift value for USB_MPS */
AnnaBridge 171:3a7713b1edbc 2345 #define _USB_DOEP_CTL_MPS_MASK 0x7FFUL /**< Bit mask for USB_MPS */
AnnaBridge 171:3a7713b1edbc 2346 #define _USB_DOEP_CTL_MPS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2347 #define USB_DOEP_CTL_MPS_DEFAULT (_USB_DOEP_CTL_MPS_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2348 #define USB_DOEP_CTL_USBACTEP (0x1UL << 15) /**< USB Active Endpoint */
AnnaBridge 171:3a7713b1edbc 2349 #define _USB_DOEP_CTL_USBACTEP_SHIFT 15 /**< Shift value for USB_USBACTEP */
AnnaBridge 171:3a7713b1edbc 2350 #define _USB_DOEP_CTL_USBACTEP_MASK 0x8000UL /**< Bit mask for USB_USBACTEP */
AnnaBridge 171:3a7713b1edbc 2351 #define _USB_DOEP_CTL_USBACTEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2352 #define USB_DOEP_CTL_USBACTEP_DEFAULT (_USB_DOEP_CTL_USBACTEP_DEFAULT << 15) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2353 #define USB_DOEP_CTL_DPIDEOF (0x1UL << 16) /**< Endpoint Data PID / Even-odd Frame */
AnnaBridge 171:3a7713b1edbc 2354 #define _USB_DOEP_CTL_DPIDEOF_SHIFT 16 /**< Shift value for USB_DPIDEOF */
AnnaBridge 171:3a7713b1edbc 2355 #define _USB_DOEP_CTL_DPIDEOF_MASK 0x10000UL /**< Bit mask for USB_DPIDEOF */
AnnaBridge 171:3a7713b1edbc 2356 #define _USB_DOEP_CTL_DPIDEOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2357 #define _USB_DOEP_CTL_DPIDEOF_DATA0EVEN 0x00000000UL /**< Mode DATA0EVEN for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2358 #define _USB_DOEP_CTL_DPIDEOF_DATA1ODD 0x00000001UL /**< Mode DATA1ODD for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2359 #define USB_DOEP_CTL_DPIDEOF_DEFAULT (_USB_DOEP_CTL_DPIDEOF_DEFAULT << 16) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2360 #define USB_DOEP_CTL_DPIDEOF_DATA0EVEN (_USB_DOEP_CTL_DPIDEOF_DATA0EVEN << 16) /**< Shifted mode DATA0EVEN for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2361 #define USB_DOEP_CTL_DPIDEOF_DATA1ODD (_USB_DOEP_CTL_DPIDEOF_DATA1ODD << 16) /**< Shifted mode DATA1ODD for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2362 #define USB_DOEP_CTL_NAKSTS (0x1UL << 17) /**< NAK Status */
AnnaBridge 171:3a7713b1edbc 2363 #define _USB_DOEP_CTL_NAKSTS_SHIFT 17 /**< Shift value for USB_NAKSTS */
AnnaBridge 171:3a7713b1edbc 2364 #define _USB_DOEP_CTL_NAKSTS_MASK 0x20000UL /**< Bit mask for USB_NAKSTS */
AnnaBridge 171:3a7713b1edbc 2365 #define _USB_DOEP_CTL_NAKSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2366 #define USB_DOEP_CTL_NAKSTS_DEFAULT (_USB_DOEP_CTL_NAKSTS_DEFAULT << 17) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2367 #define _USB_DOEP_CTL_EPTYPE_SHIFT 18 /**< Shift value for USB_EPTYPE */
AnnaBridge 171:3a7713b1edbc 2368 #define _USB_DOEP_CTL_EPTYPE_MASK 0xC0000UL /**< Bit mask for USB_EPTYPE */
AnnaBridge 171:3a7713b1edbc 2369 #define _USB_DOEP_CTL_EPTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2370 #define _USB_DOEP_CTL_EPTYPE_CONTROL 0x00000000UL /**< Mode CONTROL for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2371 #define _USB_DOEP_CTL_EPTYPE_ISO 0x00000001UL /**< Mode ISO for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2372 #define _USB_DOEP_CTL_EPTYPE_BULK 0x00000002UL /**< Mode BULK for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2373 #define _USB_DOEP_CTL_EPTYPE_INT 0x00000003UL /**< Mode INT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2374 #define USB_DOEP_CTL_EPTYPE_DEFAULT (_USB_DOEP_CTL_EPTYPE_DEFAULT << 18) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2375 #define USB_DOEP_CTL_EPTYPE_CONTROL (_USB_DOEP_CTL_EPTYPE_CONTROL << 18) /**< Shifted mode CONTROL for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2376 #define USB_DOEP_CTL_EPTYPE_ISO (_USB_DOEP_CTL_EPTYPE_ISO << 18) /**< Shifted mode ISO for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2377 #define USB_DOEP_CTL_EPTYPE_BULK (_USB_DOEP_CTL_EPTYPE_BULK << 18) /**< Shifted mode BULK for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2378 #define USB_DOEP_CTL_EPTYPE_INT (_USB_DOEP_CTL_EPTYPE_INT << 18) /**< Shifted mode INT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2379 #define USB_DOEP_CTL_SNP (0x1UL << 20) /**< Snoop Mode */
AnnaBridge 171:3a7713b1edbc 2380 #define _USB_DOEP_CTL_SNP_SHIFT 20 /**< Shift value for USB_SNP */
AnnaBridge 171:3a7713b1edbc 2381 #define _USB_DOEP_CTL_SNP_MASK 0x100000UL /**< Bit mask for USB_SNP */
AnnaBridge 171:3a7713b1edbc 2382 #define _USB_DOEP_CTL_SNP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2383 #define USB_DOEP_CTL_SNP_DEFAULT (_USB_DOEP_CTL_SNP_DEFAULT << 20) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2384 #define USB_DOEP_CTL_STALL (0x1UL << 21) /**< STALL Handshake */
AnnaBridge 171:3a7713b1edbc 2385 #define _USB_DOEP_CTL_STALL_SHIFT 21 /**< Shift value for USB_STALL */
AnnaBridge 171:3a7713b1edbc 2386 #define _USB_DOEP_CTL_STALL_MASK 0x200000UL /**< Bit mask for USB_STALL */
AnnaBridge 171:3a7713b1edbc 2387 #define _USB_DOEP_CTL_STALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2388 #define USB_DOEP_CTL_STALL_DEFAULT (_USB_DOEP_CTL_STALL_DEFAULT << 21) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2389 #define USB_DOEP_CTL_CNAK (0x1UL << 26) /**< Clear NAK */
AnnaBridge 171:3a7713b1edbc 2390 #define _USB_DOEP_CTL_CNAK_SHIFT 26 /**< Shift value for USB_CNAK */
AnnaBridge 171:3a7713b1edbc 2391 #define _USB_DOEP_CTL_CNAK_MASK 0x4000000UL /**< Bit mask for USB_CNAK */
AnnaBridge 171:3a7713b1edbc 2392 #define _USB_DOEP_CTL_CNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2393 #define USB_DOEP_CTL_CNAK_DEFAULT (_USB_DOEP_CTL_CNAK_DEFAULT << 26) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2394 #define USB_DOEP_CTL_SNAK (0x1UL << 27) /**< Set NAK */
AnnaBridge 171:3a7713b1edbc 2395 #define _USB_DOEP_CTL_SNAK_SHIFT 27 /**< Shift value for USB_SNAK */
AnnaBridge 171:3a7713b1edbc 2396 #define _USB_DOEP_CTL_SNAK_MASK 0x8000000UL /**< Bit mask for USB_SNAK */
AnnaBridge 171:3a7713b1edbc 2397 #define _USB_DOEP_CTL_SNAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2398 #define USB_DOEP_CTL_SNAK_DEFAULT (_USB_DOEP_CTL_SNAK_DEFAULT << 27) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2399 #define USB_DOEP_CTL_SETD0PIDEF (0x1UL << 28) /**< Set DATA0 PID / Even Frame */
AnnaBridge 171:3a7713b1edbc 2400 #define _USB_DOEP_CTL_SETD0PIDEF_SHIFT 28 /**< Shift value for USB_SETD0PIDEF */
AnnaBridge 171:3a7713b1edbc 2401 #define _USB_DOEP_CTL_SETD0PIDEF_MASK 0x10000000UL /**< Bit mask for USB_SETD0PIDEF */
AnnaBridge 171:3a7713b1edbc 2402 #define _USB_DOEP_CTL_SETD0PIDEF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2403 #define USB_DOEP_CTL_SETD0PIDEF_DEFAULT (_USB_DOEP_CTL_SETD0PIDEF_DEFAULT << 28) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2404 #define USB_DOEP_CTL_SETD1PIDOF (0x1UL << 29) /**< Set DATA1 PID / Odd Frame */
AnnaBridge 171:3a7713b1edbc 2405 #define _USB_DOEP_CTL_SETD1PIDOF_SHIFT 29 /**< Shift value for USB_SETD1PIDOF */
AnnaBridge 171:3a7713b1edbc 2406 #define _USB_DOEP_CTL_SETD1PIDOF_MASK 0x20000000UL /**< Bit mask for USB_SETD1PIDOF */
AnnaBridge 171:3a7713b1edbc 2407 #define _USB_DOEP_CTL_SETD1PIDOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2408 #define USB_DOEP_CTL_SETD1PIDOF_DEFAULT (_USB_DOEP_CTL_SETD1PIDOF_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2409 #define USB_DOEP_CTL_EPDIS (0x1UL << 30) /**< Endpoint Disable */
AnnaBridge 171:3a7713b1edbc 2410 #define _USB_DOEP_CTL_EPDIS_SHIFT 30 /**< Shift value for USB_EPDIS */
AnnaBridge 171:3a7713b1edbc 2411 #define _USB_DOEP_CTL_EPDIS_MASK 0x40000000UL /**< Bit mask for USB_EPDIS */
AnnaBridge 171:3a7713b1edbc 2412 #define _USB_DOEP_CTL_EPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2413 #define USB_DOEP_CTL_EPDIS_DEFAULT (_USB_DOEP_CTL_EPDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2414 #define USB_DOEP_CTL_EPENA (0x1UL << 31) /**< Endpoint Enable */
AnnaBridge 171:3a7713b1edbc 2415 #define _USB_DOEP_CTL_EPENA_SHIFT 31 /**< Shift value for USB_EPENA */
AnnaBridge 171:3a7713b1edbc 2416 #define _USB_DOEP_CTL_EPENA_MASK 0x80000000UL /**< Bit mask for USB_EPENA */
AnnaBridge 171:3a7713b1edbc 2417 #define _USB_DOEP_CTL_EPENA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2418 #define USB_DOEP_CTL_EPENA_DEFAULT (_USB_DOEP_CTL_EPENA_DEFAULT << 31) /**< Shifted mode DEFAULT for USB_DOEP_CTL */
AnnaBridge 171:3a7713b1edbc 2419
AnnaBridge 171:3a7713b1edbc 2420 /* Bit fields for USB DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2421 #define _USB_DOEP_INT_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2422 #define _USB_DOEP_INT_MASK 0x0000385FUL /**< Mask for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2423 #define USB_DOEP_INT_XFERCOMPL (0x1UL << 0) /**< Transfer Completed Interrupt */
AnnaBridge 171:3a7713b1edbc 2424 #define _USB_DOEP_INT_XFERCOMPL_SHIFT 0 /**< Shift value for USB_XFERCOMPL */
AnnaBridge 171:3a7713b1edbc 2425 #define _USB_DOEP_INT_XFERCOMPL_MASK 0x1UL /**< Bit mask for USB_XFERCOMPL */
AnnaBridge 171:3a7713b1edbc 2426 #define _USB_DOEP_INT_XFERCOMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2427 #define USB_DOEP_INT_XFERCOMPL_DEFAULT (_USB_DOEP_INT_XFERCOMPL_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2428 #define USB_DOEP_INT_EPDISBLD (0x1UL << 1) /**< Endpoint Disabled Interrupt */
AnnaBridge 171:3a7713b1edbc 2429 #define _USB_DOEP_INT_EPDISBLD_SHIFT 1 /**< Shift value for USB_EPDISBLD */
AnnaBridge 171:3a7713b1edbc 2430 #define _USB_DOEP_INT_EPDISBLD_MASK 0x2UL /**< Bit mask for USB_EPDISBLD */
AnnaBridge 171:3a7713b1edbc 2431 #define _USB_DOEP_INT_EPDISBLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2432 #define USB_DOEP_INT_EPDISBLD_DEFAULT (_USB_DOEP_INT_EPDISBLD_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2433 #define USB_DOEP_INT_AHBERR (0x1UL << 2) /**< AHB Error */
AnnaBridge 171:3a7713b1edbc 2434 #define _USB_DOEP_INT_AHBERR_SHIFT 2 /**< Shift value for USB_AHBERR */
AnnaBridge 171:3a7713b1edbc 2435 #define _USB_DOEP_INT_AHBERR_MASK 0x4UL /**< Bit mask for USB_AHBERR */
AnnaBridge 171:3a7713b1edbc 2436 #define _USB_DOEP_INT_AHBERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2437 #define USB_DOEP_INT_AHBERR_DEFAULT (_USB_DOEP_INT_AHBERR_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2438 #define USB_DOEP_INT_SETUP (0x1UL << 3) /**< Setup Phase Done */
AnnaBridge 171:3a7713b1edbc 2439 #define _USB_DOEP_INT_SETUP_SHIFT 3 /**< Shift value for USB_SETUP */
AnnaBridge 171:3a7713b1edbc 2440 #define _USB_DOEP_INT_SETUP_MASK 0x8UL /**< Bit mask for USB_SETUP */
AnnaBridge 171:3a7713b1edbc 2441 #define _USB_DOEP_INT_SETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2442 #define USB_DOEP_INT_SETUP_DEFAULT (_USB_DOEP_INT_SETUP_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2443 #define USB_DOEP_INT_OUTTKNEPDIS (0x1UL << 4) /**< OUT Token Received When Endpoint Disabled */
AnnaBridge 171:3a7713b1edbc 2444 #define _USB_DOEP_INT_OUTTKNEPDIS_SHIFT 4 /**< Shift value for USB_OUTTKNEPDIS */
AnnaBridge 171:3a7713b1edbc 2445 #define _USB_DOEP_INT_OUTTKNEPDIS_MASK 0x10UL /**< Bit mask for USB_OUTTKNEPDIS */
AnnaBridge 171:3a7713b1edbc 2446 #define _USB_DOEP_INT_OUTTKNEPDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2447 #define USB_DOEP_INT_OUTTKNEPDIS_DEFAULT (_USB_DOEP_INT_OUTTKNEPDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2448 #define USB_DOEP_INT_BACK2BACKSETUP (0x1UL << 6) /**< Back-to-Back SETUP Packets Received */
AnnaBridge 171:3a7713b1edbc 2449 #define _USB_DOEP_INT_BACK2BACKSETUP_SHIFT 6 /**< Shift value for USB_BACK2BACKSETUP */
AnnaBridge 171:3a7713b1edbc 2450 #define _USB_DOEP_INT_BACK2BACKSETUP_MASK 0x40UL /**< Bit mask for USB_BACK2BACKSETUP */
AnnaBridge 171:3a7713b1edbc 2451 #define _USB_DOEP_INT_BACK2BACKSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2452 #define USB_DOEP_INT_BACK2BACKSETUP_DEFAULT (_USB_DOEP_INT_BACK2BACKSETUP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2453 #define USB_DOEP_INT_PKTDRPSTS (0x1UL << 11) /**< Packet Drop Status */
AnnaBridge 171:3a7713b1edbc 2454 #define _USB_DOEP_INT_PKTDRPSTS_SHIFT 11 /**< Shift value for USB_PKTDRPSTS */
AnnaBridge 171:3a7713b1edbc 2455 #define _USB_DOEP_INT_PKTDRPSTS_MASK 0x800UL /**< Bit mask for USB_PKTDRPSTS */
AnnaBridge 171:3a7713b1edbc 2456 #define _USB_DOEP_INT_PKTDRPSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2457 #define USB_DOEP_INT_PKTDRPSTS_DEFAULT (_USB_DOEP_INT_PKTDRPSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2458 #define USB_DOEP_INT_BBLEERR (0x1UL << 12) /**< Babble Error */
AnnaBridge 171:3a7713b1edbc 2459 #define _USB_DOEP_INT_BBLEERR_SHIFT 12 /**< Shift value for USB_BBLEERR */
AnnaBridge 171:3a7713b1edbc 2460 #define _USB_DOEP_INT_BBLEERR_MASK 0x1000UL /**< Bit mask for USB_BBLEERR */
AnnaBridge 171:3a7713b1edbc 2461 #define _USB_DOEP_INT_BBLEERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2462 #define USB_DOEP_INT_BBLEERR_DEFAULT (_USB_DOEP_INT_BBLEERR_DEFAULT << 12) /**< Shifted mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2463 #define USB_DOEP_INT_NAKINTRPT (0x1UL << 13) /**< NAK Interrupt */
AnnaBridge 171:3a7713b1edbc 2464 #define _USB_DOEP_INT_NAKINTRPT_SHIFT 13 /**< Shift value for USB_NAKINTRPT */
AnnaBridge 171:3a7713b1edbc 2465 #define _USB_DOEP_INT_NAKINTRPT_MASK 0x2000UL /**< Bit mask for USB_NAKINTRPT */
AnnaBridge 171:3a7713b1edbc 2466 #define _USB_DOEP_INT_NAKINTRPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2467 #define USB_DOEP_INT_NAKINTRPT_DEFAULT (_USB_DOEP_INT_NAKINTRPT_DEFAULT << 13) /**< Shifted mode DEFAULT for USB_DOEP_INT */
AnnaBridge 171:3a7713b1edbc 2468
AnnaBridge 171:3a7713b1edbc 2469 /* Bit fields for USB DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2470 #define _USB_DOEP_TSIZ_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2471 #define _USB_DOEP_TSIZ_MASK 0x7FFFFFFFUL /**< Mask for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2472 #define _USB_DOEP_TSIZ_XFERSIZE_SHIFT 0 /**< Shift value for USB_XFERSIZE */
AnnaBridge 171:3a7713b1edbc 2473 #define _USB_DOEP_TSIZ_XFERSIZE_MASK 0x7FFFFUL /**< Bit mask for USB_XFERSIZE */
AnnaBridge 171:3a7713b1edbc 2474 #define _USB_DOEP_TSIZ_XFERSIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2475 #define USB_DOEP_TSIZ_XFERSIZE_DEFAULT (_USB_DOEP_TSIZ_XFERSIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2476 #define _USB_DOEP_TSIZ_PKTCNT_SHIFT 19 /**< Shift value for USB_PKTCNT */
AnnaBridge 171:3a7713b1edbc 2477 #define _USB_DOEP_TSIZ_PKTCNT_MASK 0x1FF80000UL /**< Bit mask for USB_PKTCNT */
AnnaBridge 171:3a7713b1edbc 2478 #define _USB_DOEP_TSIZ_PKTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2479 #define USB_DOEP_TSIZ_PKTCNT_DEFAULT (_USB_DOEP_TSIZ_PKTCNT_DEFAULT << 19) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2480 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_SHIFT 29 /**< Shift value for USB_RXDPIDSUPCNT */
AnnaBridge 171:3a7713b1edbc 2481 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_MASK 0x60000000UL /**< Bit mask for USB_RXDPIDSUPCNT */
AnnaBridge 171:3a7713b1edbc 2482 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2483 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 0x00000000UL /**< Mode DATA0 for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2484 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 0x00000001UL /**< Mode DATA2 for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2485 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 0x00000002UL /**< Mode DATA1 for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2486 #define _USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA 0x00000003UL /**< Mode MDATA for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2487 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DEFAULT << 29) /**< Shifted mode DEFAULT for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2488 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA0 << 29) /**< Shifted mode DATA0 for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2489 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA2 << 29) /**< Shifted mode DATA2 for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2490 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 (_USB_DOEP_TSIZ_RXDPIDSUPCNT_DATA1 << 29) /**< Shifted mode DATA1 for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2491 #define USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA (_USB_DOEP_TSIZ_RXDPIDSUPCNT_MDATA << 29) /**< Shifted mode MDATA for USB_DOEP_TSIZ */
AnnaBridge 171:3a7713b1edbc 2492
AnnaBridge 171:3a7713b1edbc 2493 /* Bit fields for USB DOEP_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2494 #define _USB_DOEP_DMAADDR_RESETVALUE 0x00000000UL /**< Default value for USB_DOEP_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2495 #define _USB_DOEP_DMAADDR_MASK 0xFFFFFFFFUL /**< Mask for USB_DOEP_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2496 #define _USB_DOEP_DMAADDR_DMAADDR_SHIFT 0 /**< Shift value for USB_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2497 #define _USB_DOEP_DMAADDR_DMAADDR_MASK 0xFFFFFFFFUL /**< Bit mask for USB_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2498 #define _USB_DOEP_DMAADDR_DMAADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_DOEP_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2499 #define USB_DOEP_DMAADDR_DMAADDR_DEFAULT (_USB_DOEP_DMAADDR_DMAADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_DOEP_DMAADDR */
AnnaBridge 171:3a7713b1edbc 2500
AnnaBridge 171:3a7713b1edbc 2501 /* Bit fields for USB PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2502 #define _USB_PCGCCTL_RESETVALUE 0x00000000UL /**< Default value for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2503 #define _USB_PCGCCTL_MASK 0x0000014FUL /**< Mask for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2504 #define USB_PCGCCTL_STOPPCLK (0x1UL << 0) /**< Stop PHY clock */
AnnaBridge 171:3a7713b1edbc 2505 #define _USB_PCGCCTL_STOPPCLK_SHIFT 0 /**< Shift value for USB_STOPPCLK */
AnnaBridge 171:3a7713b1edbc 2506 #define _USB_PCGCCTL_STOPPCLK_MASK 0x1UL /**< Bit mask for USB_STOPPCLK */
AnnaBridge 171:3a7713b1edbc 2507 #define _USB_PCGCCTL_STOPPCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2508 #define USB_PCGCCTL_STOPPCLK_DEFAULT (_USB_PCGCCTL_STOPPCLK_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2509 #define USB_PCGCCTL_GATEHCLK (0x1UL << 1) /**< Gate HCLK */
AnnaBridge 171:3a7713b1edbc 2510 #define _USB_PCGCCTL_GATEHCLK_SHIFT 1 /**< Shift value for USB_GATEHCLK */
AnnaBridge 171:3a7713b1edbc 2511 #define _USB_PCGCCTL_GATEHCLK_MASK 0x2UL /**< Bit mask for USB_GATEHCLK */
AnnaBridge 171:3a7713b1edbc 2512 #define _USB_PCGCCTL_GATEHCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2513 #define USB_PCGCCTL_GATEHCLK_DEFAULT (_USB_PCGCCTL_GATEHCLK_DEFAULT << 1) /**< Shifted mode DEFAULT for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2514 #define USB_PCGCCTL_PWRCLMP (0x1UL << 2) /**< Power Clamp */
AnnaBridge 171:3a7713b1edbc 2515 #define _USB_PCGCCTL_PWRCLMP_SHIFT 2 /**< Shift value for USB_PWRCLMP */
AnnaBridge 171:3a7713b1edbc 2516 #define _USB_PCGCCTL_PWRCLMP_MASK 0x4UL /**< Bit mask for USB_PWRCLMP */
AnnaBridge 171:3a7713b1edbc 2517 #define _USB_PCGCCTL_PWRCLMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2518 #define USB_PCGCCTL_PWRCLMP_DEFAULT (_USB_PCGCCTL_PWRCLMP_DEFAULT << 2) /**< Shifted mode DEFAULT for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2519 #define USB_PCGCCTL_RSTPDWNMODULE (0x1UL << 3) /**< Reset Power-Down Modules */
AnnaBridge 171:3a7713b1edbc 2520 #define _USB_PCGCCTL_RSTPDWNMODULE_SHIFT 3 /**< Shift value for USB_RSTPDWNMODULE */
AnnaBridge 171:3a7713b1edbc 2521 #define _USB_PCGCCTL_RSTPDWNMODULE_MASK 0x8UL /**< Bit mask for USB_RSTPDWNMODULE */
AnnaBridge 171:3a7713b1edbc 2522 #define _USB_PCGCCTL_RSTPDWNMODULE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2523 #define USB_PCGCCTL_RSTPDWNMODULE_DEFAULT (_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT << 3) /**< Shifted mode DEFAULT for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2524 #define USB_PCGCCTL_PHYSLEEP (0x1UL << 6) /**< PHY In Sleep */
AnnaBridge 171:3a7713b1edbc 2525 #define _USB_PCGCCTL_PHYSLEEP_SHIFT 6 /**< Shift value for USB_PHYSLEEP */
AnnaBridge 171:3a7713b1edbc 2526 #define _USB_PCGCCTL_PHYSLEEP_MASK 0x40UL /**< Bit mask for USB_PHYSLEEP */
AnnaBridge 171:3a7713b1edbc 2527 #define _USB_PCGCCTL_PHYSLEEP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2528 #define USB_PCGCCTL_PHYSLEEP_DEFAULT (_USB_PCGCCTL_PHYSLEEP_DEFAULT << 6) /**< Shifted mode DEFAULT for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2529 #define USB_PCGCCTL_RESETAFTERSUSP (0x1UL << 8) /**< Reset after suspend */
AnnaBridge 171:3a7713b1edbc 2530 #define _USB_PCGCCTL_RESETAFTERSUSP_SHIFT 8 /**< Shift value for USB_RESETAFTERSUSP */
AnnaBridge 171:3a7713b1edbc 2531 #define _USB_PCGCCTL_RESETAFTERSUSP_MASK 0x100UL /**< Bit mask for USB_RESETAFTERSUSP */
AnnaBridge 171:3a7713b1edbc 2532 #define _USB_PCGCCTL_RESETAFTERSUSP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2533 #define USB_PCGCCTL_RESETAFTERSUSP_DEFAULT (_USB_PCGCCTL_RESETAFTERSUSP_DEFAULT << 8) /**< Shifted mode DEFAULT for USB_PCGCCTL */
AnnaBridge 171:3a7713b1edbc 2534
AnnaBridge 171:3a7713b1edbc 2535 /* Bit fields for USB FIFO0D */
AnnaBridge 171:3a7713b1edbc 2536 #define _USB_FIFO0D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO0D */
AnnaBridge 171:3a7713b1edbc 2537 #define _USB_FIFO0D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO0D */
AnnaBridge 171:3a7713b1edbc 2538 #define _USB_FIFO0D_FIFO0D_SHIFT 0 /**< Shift value for USB_FIFO0D */
AnnaBridge 171:3a7713b1edbc 2539 #define _USB_FIFO0D_FIFO0D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO0D */
AnnaBridge 171:3a7713b1edbc 2540 #define _USB_FIFO0D_FIFO0D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO0D */
AnnaBridge 171:3a7713b1edbc 2541 #define USB_FIFO0D_FIFO0D_DEFAULT (_USB_FIFO0D_FIFO0D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO0D */
AnnaBridge 171:3a7713b1edbc 2542
AnnaBridge 171:3a7713b1edbc 2543 /* Bit fields for USB FIFO1D */
AnnaBridge 171:3a7713b1edbc 2544 #define _USB_FIFO1D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO1D */
AnnaBridge 171:3a7713b1edbc 2545 #define _USB_FIFO1D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO1D */
AnnaBridge 171:3a7713b1edbc 2546 #define _USB_FIFO1D_FIFO1D_SHIFT 0 /**< Shift value for USB_FIFO1D */
AnnaBridge 171:3a7713b1edbc 2547 #define _USB_FIFO1D_FIFO1D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO1D */
AnnaBridge 171:3a7713b1edbc 2548 #define _USB_FIFO1D_FIFO1D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO1D */
AnnaBridge 171:3a7713b1edbc 2549 #define USB_FIFO1D_FIFO1D_DEFAULT (_USB_FIFO1D_FIFO1D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO1D */
AnnaBridge 171:3a7713b1edbc 2550
AnnaBridge 171:3a7713b1edbc 2551 /* Bit fields for USB FIFO2D */
AnnaBridge 171:3a7713b1edbc 2552 #define _USB_FIFO2D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO2D */
AnnaBridge 171:3a7713b1edbc 2553 #define _USB_FIFO2D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO2D */
AnnaBridge 171:3a7713b1edbc 2554 #define _USB_FIFO2D_FIFO2D_SHIFT 0 /**< Shift value for USB_FIFO2D */
AnnaBridge 171:3a7713b1edbc 2555 #define _USB_FIFO2D_FIFO2D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO2D */
AnnaBridge 171:3a7713b1edbc 2556 #define _USB_FIFO2D_FIFO2D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO2D */
AnnaBridge 171:3a7713b1edbc 2557 #define USB_FIFO2D_FIFO2D_DEFAULT (_USB_FIFO2D_FIFO2D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO2D */
AnnaBridge 171:3a7713b1edbc 2558
AnnaBridge 171:3a7713b1edbc 2559 /* Bit fields for USB FIFO3D */
AnnaBridge 171:3a7713b1edbc 2560 #define _USB_FIFO3D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO3D */
AnnaBridge 171:3a7713b1edbc 2561 #define _USB_FIFO3D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO3D */
AnnaBridge 171:3a7713b1edbc 2562 #define _USB_FIFO3D_FIFO3D_SHIFT 0 /**< Shift value for USB_FIFO3D */
AnnaBridge 171:3a7713b1edbc 2563 #define _USB_FIFO3D_FIFO3D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO3D */
AnnaBridge 171:3a7713b1edbc 2564 #define _USB_FIFO3D_FIFO3D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO3D */
AnnaBridge 171:3a7713b1edbc 2565 #define USB_FIFO3D_FIFO3D_DEFAULT (_USB_FIFO3D_FIFO3D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO3D */
AnnaBridge 171:3a7713b1edbc 2566
AnnaBridge 171:3a7713b1edbc 2567 /* Bit fields for USB FIFO4D */
AnnaBridge 171:3a7713b1edbc 2568 #define _USB_FIFO4D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO4D */
AnnaBridge 171:3a7713b1edbc 2569 #define _USB_FIFO4D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO4D */
AnnaBridge 171:3a7713b1edbc 2570 #define _USB_FIFO4D_FIFO4D_SHIFT 0 /**< Shift value for USB_FIFO4D */
AnnaBridge 171:3a7713b1edbc 2571 #define _USB_FIFO4D_FIFO4D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO4D */
AnnaBridge 171:3a7713b1edbc 2572 #define _USB_FIFO4D_FIFO4D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO4D */
AnnaBridge 171:3a7713b1edbc 2573 #define USB_FIFO4D_FIFO4D_DEFAULT (_USB_FIFO4D_FIFO4D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO4D */
AnnaBridge 171:3a7713b1edbc 2574
AnnaBridge 171:3a7713b1edbc 2575 /* Bit fields for USB FIFO5D */
AnnaBridge 171:3a7713b1edbc 2576 #define _USB_FIFO5D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO5D */
AnnaBridge 171:3a7713b1edbc 2577 #define _USB_FIFO5D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO5D */
AnnaBridge 171:3a7713b1edbc 2578 #define _USB_FIFO5D_FIFO5D_SHIFT 0 /**< Shift value for USB_FIFO5D */
AnnaBridge 171:3a7713b1edbc 2579 #define _USB_FIFO5D_FIFO5D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO5D */
AnnaBridge 171:3a7713b1edbc 2580 #define _USB_FIFO5D_FIFO5D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO5D */
AnnaBridge 171:3a7713b1edbc 2581 #define USB_FIFO5D_FIFO5D_DEFAULT (_USB_FIFO5D_FIFO5D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO5D */
AnnaBridge 171:3a7713b1edbc 2582
AnnaBridge 171:3a7713b1edbc 2583 /* Bit fields for USB FIFO6D */
AnnaBridge 171:3a7713b1edbc 2584 #define _USB_FIFO6D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO6D */
AnnaBridge 171:3a7713b1edbc 2585 #define _USB_FIFO6D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO6D */
AnnaBridge 171:3a7713b1edbc 2586 #define _USB_FIFO6D_FIFO6D_SHIFT 0 /**< Shift value for USB_FIFO6D */
AnnaBridge 171:3a7713b1edbc 2587 #define _USB_FIFO6D_FIFO6D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO6D */
AnnaBridge 171:3a7713b1edbc 2588 #define _USB_FIFO6D_FIFO6D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO6D */
AnnaBridge 171:3a7713b1edbc 2589 #define USB_FIFO6D_FIFO6D_DEFAULT (_USB_FIFO6D_FIFO6D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO6D */
AnnaBridge 171:3a7713b1edbc 2590
AnnaBridge 171:3a7713b1edbc 2591 /* Bit fields for USB FIFO7D */
AnnaBridge 171:3a7713b1edbc 2592 #define _USB_FIFO7D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO7D */
AnnaBridge 171:3a7713b1edbc 2593 #define _USB_FIFO7D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO7D */
AnnaBridge 171:3a7713b1edbc 2594 #define _USB_FIFO7D_FIFO7D_SHIFT 0 /**< Shift value for USB_FIFO7D */
AnnaBridge 171:3a7713b1edbc 2595 #define _USB_FIFO7D_FIFO7D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO7D */
AnnaBridge 171:3a7713b1edbc 2596 #define _USB_FIFO7D_FIFO7D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO7D */
AnnaBridge 171:3a7713b1edbc 2597 #define USB_FIFO7D_FIFO7D_DEFAULT (_USB_FIFO7D_FIFO7D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO7D */
AnnaBridge 171:3a7713b1edbc 2598
AnnaBridge 171:3a7713b1edbc 2599 /* Bit fields for USB FIFO8D */
AnnaBridge 171:3a7713b1edbc 2600 #define _USB_FIFO8D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO8D */
AnnaBridge 171:3a7713b1edbc 2601 #define _USB_FIFO8D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO8D */
AnnaBridge 171:3a7713b1edbc 2602 #define _USB_FIFO8D_FIFO8D_SHIFT 0 /**< Shift value for USB_FIFO8D */
AnnaBridge 171:3a7713b1edbc 2603 #define _USB_FIFO8D_FIFO8D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO8D */
AnnaBridge 171:3a7713b1edbc 2604 #define _USB_FIFO8D_FIFO8D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO8D */
AnnaBridge 171:3a7713b1edbc 2605 #define USB_FIFO8D_FIFO8D_DEFAULT (_USB_FIFO8D_FIFO8D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO8D */
AnnaBridge 171:3a7713b1edbc 2606
AnnaBridge 171:3a7713b1edbc 2607 /* Bit fields for USB FIFO9D */
AnnaBridge 171:3a7713b1edbc 2608 #define _USB_FIFO9D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO9D */
AnnaBridge 171:3a7713b1edbc 2609 #define _USB_FIFO9D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO9D */
AnnaBridge 171:3a7713b1edbc 2610 #define _USB_FIFO9D_FIFO9D_SHIFT 0 /**< Shift value for USB_FIFO9D */
AnnaBridge 171:3a7713b1edbc 2611 #define _USB_FIFO9D_FIFO9D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO9D */
AnnaBridge 171:3a7713b1edbc 2612 #define _USB_FIFO9D_FIFO9D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO9D */
AnnaBridge 171:3a7713b1edbc 2613 #define USB_FIFO9D_FIFO9D_DEFAULT (_USB_FIFO9D_FIFO9D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO9D */
AnnaBridge 171:3a7713b1edbc 2614
AnnaBridge 171:3a7713b1edbc 2615 /* Bit fields for USB FIFO10D */
AnnaBridge 171:3a7713b1edbc 2616 #define _USB_FIFO10D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO10D */
AnnaBridge 171:3a7713b1edbc 2617 #define _USB_FIFO10D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO10D */
AnnaBridge 171:3a7713b1edbc 2618 #define _USB_FIFO10D_FIFO10D_SHIFT 0 /**< Shift value for USB_FIFO10D */
AnnaBridge 171:3a7713b1edbc 2619 #define _USB_FIFO10D_FIFO10D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO10D */
AnnaBridge 171:3a7713b1edbc 2620 #define _USB_FIFO10D_FIFO10D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO10D */
AnnaBridge 171:3a7713b1edbc 2621 #define USB_FIFO10D_FIFO10D_DEFAULT (_USB_FIFO10D_FIFO10D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO10D */
AnnaBridge 171:3a7713b1edbc 2622
AnnaBridge 171:3a7713b1edbc 2623 /* Bit fields for USB FIFO11D */
AnnaBridge 171:3a7713b1edbc 2624 #define _USB_FIFO11D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO11D */
AnnaBridge 171:3a7713b1edbc 2625 #define _USB_FIFO11D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO11D */
AnnaBridge 171:3a7713b1edbc 2626 #define _USB_FIFO11D_FIFO11D_SHIFT 0 /**< Shift value for USB_FIFO11D */
AnnaBridge 171:3a7713b1edbc 2627 #define _USB_FIFO11D_FIFO11D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO11D */
AnnaBridge 171:3a7713b1edbc 2628 #define _USB_FIFO11D_FIFO11D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO11D */
AnnaBridge 171:3a7713b1edbc 2629 #define USB_FIFO11D_FIFO11D_DEFAULT (_USB_FIFO11D_FIFO11D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO11D */
AnnaBridge 171:3a7713b1edbc 2630
AnnaBridge 171:3a7713b1edbc 2631 /* Bit fields for USB FIFO12D */
AnnaBridge 171:3a7713b1edbc 2632 #define _USB_FIFO12D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO12D */
AnnaBridge 171:3a7713b1edbc 2633 #define _USB_FIFO12D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO12D */
AnnaBridge 171:3a7713b1edbc 2634 #define _USB_FIFO12D_FIFO12D_SHIFT 0 /**< Shift value for USB_FIFO12D */
AnnaBridge 171:3a7713b1edbc 2635 #define _USB_FIFO12D_FIFO12D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO12D */
AnnaBridge 171:3a7713b1edbc 2636 #define _USB_FIFO12D_FIFO12D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO12D */
AnnaBridge 171:3a7713b1edbc 2637 #define USB_FIFO12D_FIFO12D_DEFAULT (_USB_FIFO12D_FIFO12D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO12D */
AnnaBridge 171:3a7713b1edbc 2638
AnnaBridge 171:3a7713b1edbc 2639 /* Bit fields for USB FIFO13D */
AnnaBridge 171:3a7713b1edbc 2640 #define _USB_FIFO13D_RESETVALUE 0x00000000UL /**< Default value for USB_FIFO13D */
AnnaBridge 171:3a7713b1edbc 2641 #define _USB_FIFO13D_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFO13D */
AnnaBridge 171:3a7713b1edbc 2642 #define _USB_FIFO13D_FIFO13D_SHIFT 0 /**< Shift value for USB_FIFO13D */
AnnaBridge 171:3a7713b1edbc 2643 #define _USB_FIFO13D_FIFO13D_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFO13D */
AnnaBridge 171:3a7713b1edbc 2644 #define _USB_FIFO13D_FIFO13D_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFO13D */
AnnaBridge 171:3a7713b1edbc 2645 #define USB_FIFO13D_FIFO13D_DEFAULT (_USB_FIFO13D_FIFO13D_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFO13D */
AnnaBridge 171:3a7713b1edbc 2646
AnnaBridge 171:3a7713b1edbc 2647 /* Bit fields for USB FIFORAM */
AnnaBridge 171:3a7713b1edbc 2648 #define _USB_FIFORAM_RESETVALUE 0x00000000UL /**< Default value for USB_FIFORAM */
AnnaBridge 171:3a7713b1edbc 2649 #define _USB_FIFORAM_MASK 0xFFFFFFFFUL /**< Mask for USB_FIFORAM */
AnnaBridge 171:3a7713b1edbc 2650 #define _USB_FIFORAM_FIFORAM_SHIFT 0 /**< Shift value for USB_FIFORAM */
AnnaBridge 171:3a7713b1edbc 2651 #define _USB_FIFORAM_FIFORAM_MASK 0xFFFFFFFFUL /**< Bit mask for USB_FIFORAM */
AnnaBridge 171:3a7713b1edbc 2652 #define _USB_FIFORAM_FIFORAM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USB_FIFORAM */
AnnaBridge 171:3a7713b1edbc 2653 #define USB_FIFORAM_FIFORAM_DEFAULT (_USB_FIFORAM_FIFORAM_DEFAULT << 0) /**< Shifted mode DEFAULT for USB_FIFORAM */
AnnaBridge 171:3a7713b1edbc 2654
AnnaBridge 171:3a7713b1edbc 2655 /** @} End of group EFM32LG_USB */
AnnaBridge 171:3a7713b1edbc 2656 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 2657