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TARGET_EFM32LG_STK3600/TOOLCHAIN_ARM_STD/efm32lg_usart.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32lg_usart.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32LG_USART register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32LG_USART
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32LG_USART Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IOM uint32_t CTRL; /**< Control Register */
AnnaBridge 171:3a7713b1edbc 44 __IOM uint32_t FRAME; /**< USART Frame Format Register */
AnnaBridge 171:3a7713b1edbc 45 __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */
AnnaBridge 171:3a7713b1edbc 46 __IOM uint32_t CMD; /**< Command Register */
AnnaBridge 171:3a7713b1edbc 47 __IM uint32_t STATUS; /**< USART Status Register */
AnnaBridge 171:3a7713b1edbc 48 __IOM uint32_t CLKDIV; /**< Clock Control Register */
AnnaBridge 171:3a7713b1edbc 49 __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
AnnaBridge 171:3a7713b1edbc 50 __IM uint32_t RXDATA; /**< RX Buffer Data Register */
AnnaBridge 171:3a7713b1edbc 51 __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
AnnaBridge 171:3a7713b1edbc 52 __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
AnnaBridge 171:3a7713b1edbc 53 __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
AnnaBridge 171:3a7713b1edbc 54 __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */
AnnaBridge 171:3a7713b1edbc 55 __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
AnnaBridge 171:3a7713b1edbc 56 __IOM uint32_t TXDATA; /**< TX Buffer Data Register */
AnnaBridge 171:3a7713b1edbc 57 __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
AnnaBridge 171:3a7713b1edbc 58 __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
AnnaBridge 171:3a7713b1edbc 59 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 60 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 171:3a7713b1edbc 61 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 171:3a7713b1edbc 62 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 63 __IOM uint32_t IRCTRL; /**< IrDA Control Register */
AnnaBridge 171:3a7713b1edbc 64 __IOM uint32_t ROUTE; /**< I/O Routing Register */
AnnaBridge 171:3a7713b1edbc 65 __IOM uint32_t INPUT; /**< USART Input Register */
AnnaBridge 171:3a7713b1edbc 66 __IOM uint32_t I2SCTRL; /**< I2S Control Register */
AnnaBridge 171:3a7713b1edbc 67 } USART_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 70 * @defgroup EFM32LG_USART_BitFields
AnnaBridge 171:3a7713b1edbc 71 * @{
AnnaBridge 171:3a7713b1edbc 72 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 /* Bit fields for USART CTRL */
AnnaBridge 171:3a7713b1edbc 75 #define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 76 #define _USART_CTRL_MASK 0xFFFFFF7FUL /**< Mask for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 77 #define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */
AnnaBridge 171:3a7713b1edbc 78 #define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
AnnaBridge 171:3a7713b1edbc 79 #define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
AnnaBridge 171:3a7713b1edbc 80 #define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 81 #define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 82 #define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */
AnnaBridge 171:3a7713b1edbc 83 #define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
AnnaBridge 171:3a7713b1edbc 84 #define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
AnnaBridge 171:3a7713b1edbc 85 #define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 86 #define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 87 #define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */
AnnaBridge 171:3a7713b1edbc 88 #define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
AnnaBridge 171:3a7713b1edbc 89 #define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
AnnaBridge 171:3a7713b1edbc 90 #define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 91 #define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 92 #define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */
AnnaBridge 171:3a7713b1edbc 93 #define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
AnnaBridge 171:3a7713b1edbc 94 #define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
AnnaBridge 171:3a7713b1edbc 95 #define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 96 #define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 97 #define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
AnnaBridge 171:3a7713b1edbc 98 #define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
AnnaBridge 171:3a7713b1edbc 99 #define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
AnnaBridge 171:3a7713b1edbc 100 #define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 101 #define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 102 #define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
AnnaBridge 171:3a7713b1edbc 103 #define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
AnnaBridge 171:3a7713b1edbc 104 #define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 105 #define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 106 #define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 107 #define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 108 #define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 109 #define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 110 #define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 111 #define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 112 #define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 113 #define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 114 #define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */
AnnaBridge 171:3a7713b1edbc 115 #define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
AnnaBridge 171:3a7713b1edbc 116 #define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
AnnaBridge 171:3a7713b1edbc 117 #define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 118 #define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 119 #define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 120 #define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 121 #define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 122 #define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 123 #define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */
AnnaBridge 171:3a7713b1edbc 124 #define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
AnnaBridge 171:3a7713b1edbc 125 #define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
AnnaBridge 171:3a7713b1edbc 126 #define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 127 #define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 128 #define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 129 #define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 130 #define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 131 #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 132 #define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */
AnnaBridge 171:3a7713b1edbc 133 #define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
AnnaBridge 171:3a7713b1edbc 134 #define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
AnnaBridge 171:3a7713b1edbc 135 #define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 136 #define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 137 #define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */
AnnaBridge 171:3a7713b1edbc 138 #define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
AnnaBridge 171:3a7713b1edbc 139 #define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
AnnaBridge 171:3a7713b1edbc 140 #define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 141 #define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 142 #define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 143 #define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 144 #define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 145 #define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 146 #define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */
AnnaBridge 171:3a7713b1edbc 147 #define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
AnnaBridge 171:3a7713b1edbc 148 #define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
AnnaBridge 171:3a7713b1edbc 149 #define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 150 #define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 151 #define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 152 #define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 153 #define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 154 #define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 155 #define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */
AnnaBridge 171:3a7713b1edbc 156 #define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
AnnaBridge 171:3a7713b1edbc 157 #define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
AnnaBridge 171:3a7713b1edbc 158 #define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 159 #define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 160 #define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */
AnnaBridge 171:3a7713b1edbc 161 #define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
AnnaBridge 171:3a7713b1edbc 162 #define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
AnnaBridge 171:3a7713b1edbc 163 #define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 164 #define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 165 #define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */
AnnaBridge 171:3a7713b1edbc 166 #define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
AnnaBridge 171:3a7713b1edbc 167 #define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
AnnaBridge 171:3a7713b1edbc 168 #define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 169 #define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 170 #define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */
AnnaBridge 171:3a7713b1edbc 171 #define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
AnnaBridge 171:3a7713b1edbc 172 #define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
AnnaBridge 171:3a7713b1edbc 173 #define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 174 #define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 175 #define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
AnnaBridge 171:3a7713b1edbc 176 #define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
AnnaBridge 171:3a7713b1edbc 177 #define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
AnnaBridge 171:3a7713b1edbc 178 #define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 179 #define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 180 #define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */
AnnaBridge 171:3a7713b1edbc 181 #define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
AnnaBridge 171:3a7713b1edbc 182 #define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
AnnaBridge 171:3a7713b1edbc 183 #define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 184 #define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 185 #define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */
AnnaBridge 171:3a7713b1edbc 186 #define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
AnnaBridge 171:3a7713b1edbc 187 #define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
AnnaBridge 171:3a7713b1edbc 188 #define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 189 #define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 190 #define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
AnnaBridge 171:3a7713b1edbc 191 #define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
AnnaBridge 171:3a7713b1edbc 192 #define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
AnnaBridge 171:3a7713b1edbc 193 #define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 194 #define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 195 #define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */
AnnaBridge 171:3a7713b1edbc 196 #define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
AnnaBridge 171:3a7713b1edbc 197 #define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
AnnaBridge 171:3a7713b1edbc 198 #define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 199 #define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 200 #define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */
AnnaBridge 171:3a7713b1edbc 201 #define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
AnnaBridge 171:3a7713b1edbc 202 #define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
AnnaBridge 171:3a7713b1edbc 203 #define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 204 #define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 205 #define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
AnnaBridge 171:3a7713b1edbc 206 #define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
AnnaBridge 171:3a7713b1edbc 207 #define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
AnnaBridge 171:3a7713b1edbc 208 #define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 209 #define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 210 #define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
AnnaBridge 171:3a7713b1edbc 211 #define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
AnnaBridge 171:3a7713b1edbc 212 #define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
AnnaBridge 171:3a7713b1edbc 213 #define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 214 #define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 215 #define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */
AnnaBridge 171:3a7713b1edbc 216 #define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */
AnnaBridge 171:3a7713b1edbc 217 #define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */
AnnaBridge 171:3a7713b1edbc 218 #define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 219 #define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 220 #define _USART_CTRL_TXDELAY_SHIFT 26 /**< Shift value for USART_TXDELAY */
AnnaBridge 171:3a7713b1edbc 221 #define _USART_CTRL_TXDELAY_MASK 0xC000000UL /**< Bit mask for USART_TXDELAY */
AnnaBridge 171:3a7713b1edbc 222 #define _USART_CTRL_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 223 #define _USART_CTRL_TXDELAY_NONE 0x00000000UL /**< Mode NONE for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 224 #define _USART_CTRL_TXDELAY_SINGLE 0x00000001UL /**< Mode SINGLE for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 225 #define _USART_CTRL_TXDELAY_DOUBLE 0x00000002UL /**< Mode DOUBLE for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 226 #define _USART_CTRL_TXDELAY_TRIPLE 0x00000003UL /**< Mode TRIPLE for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 227 #define USART_CTRL_TXDELAY_DEFAULT (_USART_CTRL_TXDELAY_DEFAULT << 26) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 228 #define USART_CTRL_TXDELAY_NONE (_USART_CTRL_TXDELAY_NONE << 26) /**< Shifted mode NONE for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 229 #define USART_CTRL_TXDELAY_SINGLE (_USART_CTRL_TXDELAY_SINGLE << 26) /**< Shifted mode SINGLE for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 230 #define USART_CTRL_TXDELAY_DOUBLE (_USART_CTRL_TXDELAY_DOUBLE << 26) /**< Shifted mode DOUBLE for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 231 #define USART_CTRL_TXDELAY_TRIPLE (_USART_CTRL_TXDELAY_TRIPLE << 26) /**< Shifted mode TRIPLE for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 232 #define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */
AnnaBridge 171:3a7713b1edbc 233 #define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
AnnaBridge 171:3a7713b1edbc 234 #define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
AnnaBridge 171:3a7713b1edbc 235 #define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 236 #define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 237 #define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */
AnnaBridge 171:3a7713b1edbc 238 #define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */
AnnaBridge 171:3a7713b1edbc 239 #define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */
AnnaBridge 171:3a7713b1edbc 240 #define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 241 #define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 242 #define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */
AnnaBridge 171:3a7713b1edbc 243 #define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */
AnnaBridge 171:3a7713b1edbc 244 #define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */
AnnaBridge 171:3a7713b1edbc 245 #define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 246 #define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 247 #define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */
AnnaBridge 171:3a7713b1edbc 248 #define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */
AnnaBridge 171:3a7713b1edbc 249 #define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */
AnnaBridge 171:3a7713b1edbc 250 #define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 251 #define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 /* Bit fields for USART FRAME */
AnnaBridge 171:3a7713b1edbc 254 #define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 255 #define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 256 #define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
AnnaBridge 171:3a7713b1edbc 257 #define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
AnnaBridge 171:3a7713b1edbc 258 #define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 259 #define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 260 #define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 261 #define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 262 #define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 263 #define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 264 #define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 265 #define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 266 #define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 267 #define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 268 #define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 269 #define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 270 #define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 271 #define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 272 #define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 273 #define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 274 #define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 275 #define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 276 #define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 277 #define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 278 #define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 279 #define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 280 #define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 281 #define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 282 #define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 283 #define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 284 #define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 285 #define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 286 #define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
AnnaBridge 171:3a7713b1edbc 287 #define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
AnnaBridge 171:3a7713b1edbc 288 #define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 289 #define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 290 #define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 291 #define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 292 #define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 293 #define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 294 #define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 295 #define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 296 #define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
AnnaBridge 171:3a7713b1edbc 297 #define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
AnnaBridge 171:3a7713b1edbc 298 #define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 299 #define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 300 #define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 301 #define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 302 #define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 303 #define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 304 #define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 305 #define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 306 #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 307 #define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */
AnnaBridge 171:3a7713b1edbc 308
AnnaBridge 171:3a7713b1edbc 309 /* Bit fields for USART TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 310 #define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 311 #define _USART_TRIGCTRL_MASK 0x00000077UL /**< Mask for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 312 #define _USART_TRIGCTRL_TSEL_SHIFT 0 /**< Shift value for USART_TSEL */
AnnaBridge 171:3a7713b1edbc 313 #define _USART_TRIGCTRL_TSEL_MASK 0x7UL /**< Bit mask for USART_TSEL */
AnnaBridge 171:3a7713b1edbc 314 #define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 315 #define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 316 #define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 317 #define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 318 #define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 319 #define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 320 #define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 321 #define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 322 #define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 323 #define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 324 #define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 325 #define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 326 #define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 327 #define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 328 #define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 329 #define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 330 #define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 331 #define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 332 #define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */
AnnaBridge 171:3a7713b1edbc 333 #define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
AnnaBridge 171:3a7713b1edbc 334 #define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
AnnaBridge 171:3a7713b1edbc 335 #define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 336 #define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 337 #define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */
AnnaBridge 171:3a7713b1edbc 338 #define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
AnnaBridge 171:3a7713b1edbc 339 #define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
AnnaBridge 171:3a7713b1edbc 340 #define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 341 #define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 342 #define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */
AnnaBridge 171:3a7713b1edbc 343 #define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */
AnnaBridge 171:3a7713b1edbc 344 #define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
AnnaBridge 171:3a7713b1edbc 345 #define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 346 #define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
AnnaBridge 171:3a7713b1edbc 347
AnnaBridge 171:3a7713b1edbc 348 /* Bit fields for USART CMD */
AnnaBridge 171:3a7713b1edbc 349 #define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */
AnnaBridge 171:3a7713b1edbc 350 #define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */
AnnaBridge 171:3a7713b1edbc 351 #define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
AnnaBridge 171:3a7713b1edbc 352 #define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
AnnaBridge 171:3a7713b1edbc 353 #define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
AnnaBridge 171:3a7713b1edbc 354 #define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 355 #define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 356 #define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
AnnaBridge 171:3a7713b1edbc 357 #define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
AnnaBridge 171:3a7713b1edbc 358 #define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
AnnaBridge 171:3a7713b1edbc 359 #define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 360 #define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 361 #define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
AnnaBridge 171:3a7713b1edbc 362 #define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
AnnaBridge 171:3a7713b1edbc 363 #define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
AnnaBridge 171:3a7713b1edbc 364 #define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 365 #define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 366 #define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
AnnaBridge 171:3a7713b1edbc 367 #define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
AnnaBridge 171:3a7713b1edbc 368 #define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
AnnaBridge 171:3a7713b1edbc 369 #define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 370 #define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 371 #define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */
AnnaBridge 171:3a7713b1edbc 372 #define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
AnnaBridge 171:3a7713b1edbc 373 #define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
AnnaBridge 171:3a7713b1edbc 374 #define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 375 #define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 376 #define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */
AnnaBridge 171:3a7713b1edbc 377 #define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
AnnaBridge 171:3a7713b1edbc 378 #define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
AnnaBridge 171:3a7713b1edbc 379 #define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 380 #define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 381 #define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */
AnnaBridge 171:3a7713b1edbc 382 #define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
AnnaBridge 171:3a7713b1edbc 383 #define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
AnnaBridge 171:3a7713b1edbc 384 #define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 385 #define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 386 #define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */
AnnaBridge 171:3a7713b1edbc 387 #define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
AnnaBridge 171:3a7713b1edbc 388 #define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
AnnaBridge 171:3a7713b1edbc 389 #define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 390 #define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 391 #define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */
AnnaBridge 171:3a7713b1edbc 392 #define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
AnnaBridge 171:3a7713b1edbc 393 #define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
AnnaBridge 171:3a7713b1edbc 394 #define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 395 #define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 396 #define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */
AnnaBridge 171:3a7713b1edbc 397 #define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
AnnaBridge 171:3a7713b1edbc 398 #define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
AnnaBridge 171:3a7713b1edbc 399 #define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 400 #define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 401 #define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */
AnnaBridge 171:3a7713b1edbc 402 #define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
AnnaBridge 171:3a7713b1edbc 403 #define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
AnnaBridge 171:3a7713b1edbc 404 #define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 405 #define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 406 #define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */
AnnaBridge 171:3a7713b1edbc 407 #define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
AnnaBridge 171:3a7713b1edbc 408 #define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
AnnaBridge 171:3a7713b1edbc 409 #define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 410 #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */
AnnaBridge 171:3a7713b1edbc 411
AnnaBridge 171:3a7713b1edbc 412 /* Bit fields for USART STATUS */
AnnaBridge 171:3a7713b1edbc 413 #define _USART_STATUS_RESETVALUE 0x00000040UL /**< Default value for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 414 #define _USART_STATUS_MASK 0x00001FFFUL /**< Mask for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 415 #define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
AnnaBridge 171:3a7713b1edbc 416 #define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
AnnaBridge 171:3a7713b1edbc 417 #define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
AnnaBridge 171:3a7713b1edbc 418 #define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 419 #define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 420 #define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
AnnaBridge 171:3a7713b1edbc 421 #define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
AnnaBridge 171:3a7713b1edbc 422 #define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
AnnaBridge 171:3a7713b1edbc 423 #define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 424 #define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 425 #define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */
AnnaBridge 171:3a7713b1edbc 426 #define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
AnnaBridge 171:3a7713b1edbc 427 #define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
AnnaBridge 171:3a7713b1edbc 428 #define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 429 #define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 430 #define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
AnnaBridge 171:3a7713b1edbc 431 #define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
AnnaBridge 171:3a7713b1edbc 432 #define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
AnnaBridge 171:3a7713b1edbc 433 #define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 434 #define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 435 #define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
AnnaBridge 171:3a7713b1edbc 436 #define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
AnnaBridge 171:3a7713b1edbc 437 #define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
AnnaBridge 171:3a7713b1edbc 438 #define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 439 #define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 440 #define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
AnnaBridge 171:3a7713b1edbc 441 #define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
AnnaBridge 171:3a7713b1edbc 442 #define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
AnnaBridge 171:3a7713b1edbc 443 #define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 444 #define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 445 #define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */
AnnaBridge 171:3a7713b1edbc 446 #define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
AnnaBridge 171:3a7713b1edbc 447 #define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
AnnaBridge 171:3a7713b1edbc 448 #define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 449 #define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 450 #define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */
AnnaBridge 171:3a7713b1edbc 451 #define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
AnnaBridge 171:3a7713b1edbc 452 #define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
AnnaBridge 171:3a7713b1edbc 453 #define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 454 #define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 455 #define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
AnnaBridge 171:3a7713b1edbc 456 #define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
AnnaBridge 171:3a7713b1edbc 457 #define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
AnnaBridge 171:3a7713b1edbc 458 #define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 459 #define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 460 #define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */
AnnaBridge 171:3a7713b1edbc 461 #define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */
AnnaBridge 171:3a7713b1edbc 462 #define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */
AnnaBridge 171:3a7713b1edbc 463 #define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 464 #define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 465 #define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */
AnnaBridge 171:3a7713b1edbc 466 #define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */
AnnaBridge 171:3a7713b1edbc 467 #define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */
AnnaBridge 171:3a7713b1edbc 468 #define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 469 #define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 470 #define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */
AnnaBridge 171:3a7713b1edbc 471 #define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */
AnnaBridge 171:3a7713b1edbc 472 #define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */
AnnaBridge 171:3a7713b1edbc 473 #define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 474 #define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 475 #define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */
AnnaBridge 171:3a7713b1edbc 476 #define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */
AnnaBridge 171:3a7713b1edbc 477 #define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */
AnnaBridge 171:3a7713b1edbc 478 #define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 479 #define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */
AnnaBridge 171:3a7713b1edbc 480
AnnaBridge 171:3a7713b1edbc 481 /* Bit fields for USART CLKDIV */
AnnaBridge 171:3a7713b1edbc 482 #define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */
AnnaBridge 171:3a7713b1edbc 483 #define _USART_CLKDIV_MASK 0x001FFFC0UL /**< Mask for USART_CLKDIV */
AnnaBridge 171:3a7713b1edbc 484 #define _USART_CLKDIV_DIV_SHIFT 6 /**< Shift value for USART_DIV */
AnnaBridge 171:3a7713b1edbc 485 #define _USART_CLKDIV_DIV_MASK 0x1FFFC0UL /**< Bit mask for USART_DIV */
AnnaBridge 171:3a7713b1edbc 486 #define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
AnnaBridge 171:3a7713b1edbc 487 #define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CLKDIV */
AnnaBridge 171:3a7713b1edbc 488
AnnaBridge 171:3a7713b1edbc 489 /* Bit fields for USART RXDATAX */
AnnaBridge 171:3a7713b1edbc 490 #define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */
AnnaBridge 171:3a7713b1edbc 491 #define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */
AnnaBridge 171:3a7713b1edbc 492 #define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
AnnaBridge 171:3a7713b1edbc 493 #define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
AnnaBridge 171:3a7713b1edbc 494 #define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
AnnaBridge 171:3a7713b1edbc 495 #define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */
AnnaBridge 171:3a7713b1edbc 496 #define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */
AnnaBridge 171:3a7713b1edbc 497 #define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
AnnaBridge 171:3a7713b1edbc 498 #define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
AnnaBridge 171:3a7713b1edbc 499 #define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
AnnaBridge 171:3a7713b1edbc 500 #define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */
AnnaBridge 171:3a7713b1edbc 501 #define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */
AnnaBridge 171:3a7713b1edbc 502 #define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
AnnaBridge 171:3a7713b1edbc 503 #define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
AnnaBridge 171:3a7713b1edbc 504 #define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
AnnaBridge 171:3a7713b1edbc 505 #define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */
AnnaBridge 171:3a7713b1edbc 506
AnnaBridge 171:3a7713b1edbc 507 /* Bit fields for USART RXDATA */
AnnaBridge 171:3a7713b1edbc 508 #define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */
AnnaBridge 171:3a7713b1edbc 509 #define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */
AnnaBridge 171:3a7713b1edbc 510 #define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
AnnaBridge 171:3a7713b1edbc 511 #define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
AnnaBridge 171:3a7713b1edbc 512 #define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */
AnnaBridge 171:3a7713b1edbc 513 #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */
AnnaBridge 171:3a7713b1edbc 514
AnnaBridge 171:3a7713b1edbc 515 /* Bit fields for USART RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 516 #define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 517 #define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 518 #define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
AnnaBridge 171:3a7713b1edbc 519 #define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
AnnaBridge 171:3a7713b1edbc 520 #define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 521 #define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 522 #define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */
AnnaBridge 171:3a7713b1edbc 523 #define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
AnnaBridge 171:3a7713b1edbc 524 #define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
AnnaBridge 171:3a7713b1edbc 525 #define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 526 #define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 527 #define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */
AnnaBridge 171:3a7713b1edbc 528 #define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
AnnaBridge 171:3a7713b1edbc 529 #define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
AnnaBridge 171:3a7713b1edbc 530 #define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 531 #define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 532 #define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
AnnaBridge 171:3a7713b1edbc 533 #define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
AnnaBridge 171:3a7713b1edbc 534 #define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 535 #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 536 #define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */
AnnaBridge 171:3a7713b1edbc 537 #define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
AnnaBridge 171:3a7713b1edbc 538 #define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
AnnaBridge 171:3a7713b1edbc 539 #define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 540 #define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 541 #define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */
AnnaBridge 171:3a7713b1edbc 542 #define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
AnnaBridge 171:3a7713b1edbc 543 #define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
AnnaBridge 171:3a7713b1edbc 544 #define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 545 #define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547 /* Bit fields for USART RXDOUBLE */
AnnaBridge 171:3a7713b1edbc 548 #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */
AnnaBridge 171:3a7713b1edbc 549 #define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */
AnnaBridge 171:3a7713b1edbc 550 #define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
AnnaBridge 171:3a7713b1edbc 551 #define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
AnnaBridge 171:3a7713b1edbc 552 #define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
AnnaBridge 171:3a7713b1edbc 553 #define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
AnnaBridge 171:3a7713b1edbc 554 #define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
AnnaBridge 171:3a7713b1edbc 555 #define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
AnnaBridge 171:3a7713b1edbc 556 #define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
AnnaBridge 171:3a7713b1edbc 557 #define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
AnnaBridge 171:3a7713b1edbc 558
AnnaBridge 171:3a7713b1edbc 559 /* Bit fields for USART RXDATAXP */
AnnaBridge 171:3a7713b1edbc 560 #define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */
AnnaBridge 171:3a7713b1edbc 561 #define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */
AnnaBridge 171:3a7713b1edbc 562 #define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
AnnaBridge 171:3a7713b1edbc 563 #define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
AnnaBridge 171:3a7713b1edbc 564 #define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
AnnaBridge 171:3a7713b1edbc 565 #define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */
AnnaBridge 171:3a7713b1edbc 566 #define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */
AnnaBridge 171:3a7713b1edbc 567 #define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
AnnaBridge 171:3a7713b1edbc 568 #define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
AnnaBridge 171:3a7713b1edbc 569 #define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
AnnaBridge 171:3a7713b1edbc 570 #define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */
AnnaBridge 171:3a7713b1edbc 571 #define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */
AnnaBridge 171:3a7713b1edbc 572 #define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */
AnnaBridge 171:3a7713b1edbc 573 #define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */
AnnaBridge 171:3a7713b1edbc 574 #define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
AnnaBridge 171:3a7713b1edbc 575 #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */
AnnaBridge 171:3a7713b1edbc 576
AnnaBridge 171:3a7713b1edbc 577 /* Bit fields for USART RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 578 #define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 579 #define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 580 #define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */
AnnaBridge 171:3a7713b1edbc 581 #define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */
AnnaBridge 171:3a7713b1edbc 582 #define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 583 #define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 584 #define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */
AnnaBridge 171:3a7713b1edbc 585 #define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */
AnnaBridge 171:3a7713b1edbc 586 #define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */
AnnaBridge 171:3a7713b1edbc 587 #define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 588 #define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 589 #define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */
AnnaBridge 171:3a7713b1edbc 590 #define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */
AnnaBridge 171:3a7713b1edbc 591 #define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */
AnnaBridge 171:3a7713b1edbc 592 #define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 593 #define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 594 #define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */
AnnaBridge 171:3a7713b1edbc 595 #define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */
AnnaBridge 171:3a7713b1edbc 596 #define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 597 #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 598 #define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */
AnnaBridge 171:3a7713b1edbc 599 #define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */
AnnaBridge 171:3a7713b1edbc 600 #define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */
AnnaBridge 171:3a7713b1edbc 601 #define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 602 #define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 603 #define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */
AnnaBridge 171:3a7713b1edbc 604 #define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */
AnnaBridge 171:3a7713b1edbc 605 #define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */
AnnaBridge 171:3a7713b1edbc 606 #define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 607 #define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
AnnaBridge 171:3a7713b1edbc 608
AnnaBridge 171:3a7713b1edbc 609 /* Bit fields for USART TXDATAX */
AnnaBridge 171:3a7713b1edbc 610 #define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 611 #define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 612 #define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 613 #define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 614 #define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 615 #define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 616 #define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */
AnnaBridge 171:3a7713b1edbc 617 #define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */
AnnaBridge 171:3a7713b1edbc 618 #define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */
AnnaBridge 171:3a7713b1edbc 619 #define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 620 #define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 621 #define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */
AnnaBridge 171:3a7713b1edbc 622 #define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */
AnnaBridge 171:3a7713b1edbc 623 #define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
AnnaBridge 171:3a7713b1edbc 624 #define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 625 #define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 626 #define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
AnnaBridge 171:3a7713b1edbc 627 #define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
AnnaBridge 171:3a7713b1edbc 628 #define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
AnnaBridge 171:3a7713b1edbc 629 #define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 630 #define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 631 #define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */
AnnaBridge 171:3a7713b1edbc 632 #define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */
AnnaBridge 171:3a7713b1edbc 633 #define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */
AnnaBridge 171:3a7713b1edbc 634 #define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 635 #define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 636 #define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
AnnaBridge 171:3a7713b1edbc 637 #define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */
AnnaBridge 171:3a7713b1edbc 638 #define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */
AnnaBridge 171:3a7713b1edbc 639 #define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 640 #define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */
AnnaBridge 171:3a7713b1edbc 641
AnnaBridge 171:3a7713b1edbc 642 /* Bit fields for USART TXDATA */
AnnaBridge 171:3a7713b1edbc 643 #define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */
AnnaBridge 171:3a7713b1edbc 644 #define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */
AnnaBridge 171:3a7713b1edbc 645 #define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */
AnnaBridge 171:3a7713b1edbc 646 #define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */
AnnaBridge 171:3a7713b1edbc 647 #define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */
AnnaBridge 171:3a7713b1edbc 648 #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */
AnnaBridge 171:3a7713b1edbc 649
AnnaBridge 171:3a7713b1edbc 650 /* Bit fields for USART TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 651 #define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 652 #define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 653 #define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
AnnaBridge 171:3a7713b1edbc 654 #define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */
AnnaBridge 171:3a7713b1edbc 655 #define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 656 #define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 657 #define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */
AnnaBridge 171:3a7713b1edbc 658 #define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */
AnnaBridge 171:3a7713b1edbc 659 #define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */
AnnaBridge 171:3a7713b1edbc 660 #define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 661 #define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 662 #define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */
AnnaBridge 171:3a7713b1edbc 663 #define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */
AnnaBridge 171:3a7713b1edbc 664 #define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
AnnaBridge 171:3a7713b1edbc 665 #define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 666 #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 667 #define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */
AnnaBridge 171:3a7713b1edbc 668 #define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
AnnaBridge 171:3a7713b1edbc 669 #define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
AnnaBridge 171:3a7713b1edbc 670 #define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 671 #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 672 #define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */
AnnaBridge 171:3a7713b1edbc 673 #define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */
AnnaBridge 171:3a7713b1edbc 674 #define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */
AnnaBridge 171:3a7713b1edbc 675 #define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 676 #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 677 #define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */
AnnaBridge 171:3a7713b1edbc 678 #define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */
AnnaBridge 171:3a7713b1edbc 679 #define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */
AnnaBridge 171:3a7713b1edbc 680 #define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 681 #define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 682 #define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */
AnnaBridge 171:3a7713b1edbc 683 #define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */
AnnaBridge 171:3a7713b1edbc 684 #define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 685 #define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 686 #define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */
AnnaBridge 171:3a7713b1edbc 687 #define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */
AnnaBridge 171:3a7713b1edbc 688 #define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */
AnnaBridge 171:3a7713b1edbc 689 #define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 690 #define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 691 #define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */
AnnaBridge 171:3a7713b1edbc 692 #define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */
AnnaBridge 171:3a7713b1edbc 693 #define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
AnnaBridge 171:3a7713b1edbc 694 #define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 695 #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 696 #define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */
AnnaBridge 171:3a7713b1edbc 697 #define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
AnnaBridge 171:3a7713b1edbc 698 #define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
AnnaBridge 171:3a7713b1edbc 699 #define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 700 #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 701 #define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */
AnnaBridge 171:3a7713b1edbc 702 #define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */
AnnaBridge 171:3a7713b1edbc 703 #define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */
AnnaBridge 171:3a7713b1edbc 704 #define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 705 #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 706 #define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */
AnnaBridge 171:3a7713b1edbc 707 #define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */
AnnaBridge 171:3a7713b1edbc 708 #define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */
AnnaBridge 171:3a7713b1edbc 709 #define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 710 #define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
AnnaBridge 171:3a7713b1edbc 711
AnnaBridge 171:3a7713b1edbc 712 /* Bit fields for USART TXDOUBLE */
AnnaBridge 171:3a7713b1edbc 713 #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */
AnnaBridge 171:3a7713b1edbc 714 #define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */
AnnaBridge 171:3a7713b1edbc 715 #define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
AnnaBridge 171:3a7713b1edbc 716 #define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */
AnnaBridge 171:3a7713b1edbc 717 #define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
AnnaBridge 171:3a7713b1edbc 718 #define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
AnnaBridge 171:3a7713b1edbc 719 #define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */
AnnaBridge 171:3a7713b1edbc 720 #define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */
AnnaBridge 171:3a7713b1edbc 721 #define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
AnnaBridge 171:3a7713b1edbc 722 #define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
AnnaBridge 171:3a7713b1edbc 723
AnnaBridge 171:3a7713b1edbc 724 /* Bit fields for USART IF */
AnnaBridge 171:3a7713b1edbc 725 #define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */
AnnaBridge 171:3a7713b1edbc 726 #define _USART_IF_MASK 0x00001FFFUL /**< Mask for USART_IF */
AnnaBridge 171:3a7713b1edbc 727 #define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 728 #define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */
AnnaBridge 171:3a7713b1edbc 729 #define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
AnnaBridge 171:3a7713b1edbc 730 #define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 731 #define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 732 #define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 733 #define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
AnnaBridge 171:3a7713b1edbc 734 #define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
AnnaBridge 171:3a7713b1edbc 735 #define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 736 #define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 737 #define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 738 #define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
AnnaBridge 171:3a7713b1edbc 739 #define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
AnnaBridge 171:3a7713b1edbc 740 #define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 741 #define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 742 #define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 743 #define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
AnnaBridge 171:3a7713b1edbc 744 #define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
AnnaBridge 171:3a7713b1edbc 745 #define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 746 #define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 747 #define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 748 #define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
AnnaBridge 171:3a7713b1edbc 749 #define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
AnnaBridge 171:3a7713b1edbc 750 #define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 751 #define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 752 #define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 753 #define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
AnnaBridge 171:3a7713b1edbc 754 #define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
AnnaBridge 171:3a7713b1edbc 755 #define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 756 #define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 757 #define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 758 #define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
AnnaBridge 171:3a7713b1edbc 759 #define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
AnnaBridge 171:3a7713b1edbc 760 #define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 761 #define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 762 #define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 763 #define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
AnnaBridge 171:3a7713b1edbc 764 #define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
AnnaBridge 171:3a7713b1edbc 765 #define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 766 #define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 767 #define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 768 #define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */
AnnaBridge 171:3a7713b1edbc 769 #define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
AnnaBridge 171:3a7713b1edbc 770 #define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 771 #define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 772 #define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 773 #define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */
AnnaBridge 171:3a7713b1edbc 774 #define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
AnnaBridge 171:3a7713b1edbc 775 #define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 776 #define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 777 #define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 778 #define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
AnnaBridge 171:3a7713b1edbc 779 #define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
AnnaBridge 171:3a7713b1edbc 780 #define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 781 #define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 782 #define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 783 #define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
AnnaBridge 171:3a7713b1edbc 784 #define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
AnnaBridge 171:3a7713b1edbc 785 #define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 786 #define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 787 #define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 788 #define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */
AnnaBridge 171:3a7713b1edbc 789 #define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
AnnaBridge 171:3a7713b1edbc 790 #define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 791 #define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */
AnnaBridge 171:3a7713b1edbc 792
AnnaBridge 171:3a7713b1edbc 793 /* Bit fields for USART IFS */
AnnaBridge 171:3a7713b1edbc 794 #define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */
AnnaBridge 171:3a7713b1edbc 795 #define _USART_IFS_MASK 0x00001FF9UL /**< Mask for USART_IFS */
AnnaBridge 171:3a7713b1edbc 796 #define USART_IFS_TXC (0x1UL << 0) /**< Set TX Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 797 #define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */
AnnaBridge 171:3a7713b1edbc 798 #define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
AnnaBridge 171:3a7713b1edbc 799 #define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 800 #define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 801 #define USART_IFS_RXFULL (0x1UL << 3) /**< Set RX Buffer Full Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 802 #define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
AnnaBridge 171:3a7713b1edbc 803 #define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
AnnaBridge 171:3a7713b1edbc 804 #define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 805 #define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 806 #define USART_IFS_RXOF (0x1UL << 4) /**< Set RX Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 807 #define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
AnnaBridge 171:3a7713b1edbc 808 #define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
AnnaBridge 171:3a7713b1edbc 809 #define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 810 #define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 811 #define USART_IFS_RXUF (0x1UL << 5) /**< Set RX Underflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 812 #define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
AnnaBridge 171:3a7713b1edbc 813 #define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
AnnaBridge 171:3a7713b1edbc 814 #define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 815 #define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 816 #define USART_IFS_TXOF (0x1UL << 6) /**< Set TX Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 817 #define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
AnnaBridge 171:3a7713b1edbc 818 #define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
AnnaBridge 171:3a7713b1edbc 819 #define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 820 #define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 821 #define USART_IFS_TXUF (0x1UL << 7) /**< Set TX Underflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 822 #define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
AnnaBridge 171:3a7713b1edbc 823 #define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
AnnaBridge 171:3a7713b1edbc 824 #define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 825 #define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 826 #define USART_IFS_PERR (0x1UL << 8) /**< Set Parity Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 827 #define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */
AnnaBridge 171:3a7713b1edbc 828 #define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
AnnaBridge 171:3a7713b1edbc 829 #define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 830 #define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 831 #define USART_IFS_FERR (0x1UL << 9) /**< Set Framing Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 832 #define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */
AnnaBridge 171:3a7713b1edbc 833 #define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
AnnaBridge 171:3a7713b1edbc 834 #define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 835 #define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 836 #define USART_IFS_MPAF (0x1UL << 10) /**< Set Multi-Processor Address Frame Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 837 #define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
AnnaBridge 171:3a7713b1edbc 838 #define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
AnnaBridge 171:3a7713b1edbc 839 #define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 840 #define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 841 #define USART_IFS_SSM (0x1UL << 11) /**< Set Slave-Select in Master mode Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 842 #define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */
AnnaBridge 171:3a7713b1edbc 843 #define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
AnnaBridge 171:3a7713b1edbc 844 #define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 845 #define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 846 #define USART_IFS_CCF (0x1UL << 12) /**< Set Collision Check Fail Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 847 #define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */
AnnaBridge 171:3a7713b1edbc 848 #define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
AnnaBridge 171:3a7713b1edbc 849 #define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 850 #define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */
AnnaBridge 171:3a7713b1edbc 851
AnnaBridge 171:3a7713b1edbc 852 /* Bit fields for USART IFC */
AnnaBridge 171:3a7713b1edbc 853 #define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */
AnnaBridge 171:3a7713b1edbc 854 #define _USART_IFC_MASK 0x00001FF9UL /**< Mask for USART_IFC */
AnnaBridge 171:3a7713b1edbc 855 #define USART_IFC_TXC (0x1UL << 0) /**< Clear TX Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 856 #define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */
AnnaBridge 171:3a7713b1edbc 857 #define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
AnnaBridge 171:3a7713b1edbc 858 #define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 859 #define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 860 #define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RX Buffer Full Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 861 #define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
AnnaBridge 171:3a7713b1edbc 862 #define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
AnnaBridge 171:3a7713b1edbc 863 #define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 864 #define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 865 #define USART_IFC_RXOF (0x1UL << 4) /**< Clear RX Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 866 #define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
AnnaBridge 171:3a7713b1edbc 867 #define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
AnnaBridge 171:3a7713b1edbc 868 #define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 869 #define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 870 #define USART_IFC_RXUF (0x1UL << 5) /**< Clear RX Underflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 871 #define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
AnnaBridge 171:3a7713b1edbc 872 #define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
AnnaBridge 171:3a7713b1edbc 873 #define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 874 #define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 875 #define USART_IFC_TXOF (0x1UL << 6) /**< Clear TX Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 876 #define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
AnnaBridge 171:3a7713b1edbc 877 #define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
AnnaBridge 171:3a7713b1edbc 878 #define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 879 #define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 880 #define USART_IFC_TXUF (0x1UL << 7) /**< Clear TX Underflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 881 #define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
AnnaBridge 171:3a7713b1edbc 882 #define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
AnnaBridge 171:3a7713b1edbc 883 #define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 884 #define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 885 #define USART_IFC_PERR (0x1UL << 8) /**< Clear Parity Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 886 #define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */
AnnaBridge 171:3a7713b1edbc 887 #define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
AnnaBridge 171:3a7713b1edbc 888 #define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 889 #define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 890 #define USART_IFC_FERR (0x1UL << 9) /**< Clear Framing Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 891 #define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */
AnnaBridge 171:3a7713b1edbc 892 #define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
AnnaBridge 171:3a7713b1edbc 893 #define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 894 #define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 895 #define USART_IFC_MPAF (0x1UL << 10) /**< Clear Multi-Processor Address Frame Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 896 #define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
AnnaBridge 171:3a7713b1edbc 897 #define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
AnnaBridge 171:3a7713b1edbc 898 #define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 899 #define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 900 #define USART_IFC_SSM (0x1UL << 11) /**< Clear Slave-Select In Master Mode Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 901 #define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */
AnnaBridge 171:3a7713b1edbc 902 #define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
AnnaBridge 171:3a7713b1edbc 903 #define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 904 #define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 905 #define USART_IFC_CCF (0x1UL << 12) /**< Clear Collision Check Fail Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 906 #define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */
AnnaBridge 171:3a7713b1edbc 907 #define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
AnnaBridge 171:3a7713b1edbc 908 #define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 909 #define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */
AnnaBridge 171:3a7713b1edbc 910
AnnaBridge 171:3a7713b1edbc 911 /* Bit fields for USART IEN */
AnnaBridge 171:3a7713b1edbc 912 #define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */
AnnaBridge 171:3a7713b1edbc 913 #define _USART_IEN_MASK 0x00001FFFUL /**< Mask for USART_IEN */
AnnaBridge 171:3a7713b1edbc 914 #define USART_IEN_TXC (0x1UL << 0) /**< TX Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 915 #define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */
AnnaBridge 171:3a7713b1edbc 916 #define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
AnnaBridge 171:3a7713b1edbc 917 #define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 918 #define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 919 #define USART_IEN_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 920 #define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
AnnaBridge 171:3a7713b1edbc 921 #define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
AnnaBridge 171:3a7713b1edbc 922 #define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 923 #define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 924 #define USART_IEN_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 925 #define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
AnnaBridge 171:3a7713b1edbc 926 #define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
AnnaBridge 171:3a7713b1edbc 927 #define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 928 #define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 929 #define USART_IEN_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 930 #define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
AnnaBridge 171:3a7713b1edbc 931 #define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
AnnaBridge 171:3a7713b1edbc 932 #define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 933 #define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 934 #define USART_IEN_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 935 #define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
AnnaBridge 171:3a7713b1edbc 936 #define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
AnnaBridge 171:3a7713b1edbc 937 #define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 938 #define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 939 #define USART_IEN_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 940 #define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
AnnaBridge 171:3a7713b1edbc 941 #define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
AnnaBridge 171:3a7713b1edbc 942 #define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 943 #define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 944 #define USART_IEN_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 945 #define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
AnnaBridge 171:3a7713b1edbc 946 #define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
AnnaBridge 171:3a7713b1edbc 947 #define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 948 #define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 949 #define USART_IEN_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 950 #define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
AnnaBridge 171:3a7713b1edbc 951 #define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
AnnaBridge 171:3a7713b1edbc 952 #define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 953 #define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 954 #define USART_IEN_PERR (0x1UL << 8) /**< Parity Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 955 #define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */
AnnaBridge 171:3a7713b1edbc 956 #define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
AnnaBridge 171:3a7713b1edbc 957 #define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 958 #define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 959 #define USART_IEN_FERR (0x1UL << 9) /**< Framing Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 960 #define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */
AnnaBridge 171:3a7713b1edbc 961 #define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
AnnaBridge 171:3a7713b1edbc 962 #define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 963 #define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 964 #define USART_IEN_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 965 #define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
AnnaBridge 171:3a7713b1edbc 966 #define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
AnnaBridge 171:3a7713b1edbc 967 #define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 968 #define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 969 #define USART_IEN_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 970 #define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */
AnnaBridge 171:3a7713b1edbc 971 #define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
AnnaBridge 171:3a7713b1edbc 972 #define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 973 #define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 974 #define USART_IEN_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 975 #define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */
AnnaBridge 171:3a7713b1edbc 976 #define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
AnnaBridge 171:3a7713b1edbc 977 #define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 978 #define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */
AnnaBridge 171:3a7713b1edbc 979
AnnaBridge 171:3a7713b1edbc 980 /* Bit fields for USART IRCTRL */
AnnaBridge 171:3a7713b1edbc 981 #define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 982 #define _USART_IRCTRL_MASK 0x000000FFUL /**< Mask for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 983 #define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */
AnnaBridge 171:3a7713b1edbc 984 #define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */
AnnaBridge 171:3a7713b1edbc 985 #define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */
AnnaBridge 171:3a7713b1edbc 986 #define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 987 #define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 988 #define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */
AnnaBridge 171:3a7713b1edbc 989 #define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */
AnnaBridge 171:3a7713b1edbc 990 #define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 991 #define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 992 #define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 993 #define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 994 #define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 995 #define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 996 #define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 997 #define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 998 #define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 999 #define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1000 #define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */
AnnaBridge 171:3a7713b1edbc 1001 #define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */
AnnaBridge 171:3a7713b1edbc 1002 #define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */
AnnaBridge 171:3a7713b1edbc 1003 #define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1004 #define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1005 #define _USART_IRCTRL_IRPRSSEL_SHIFT 4 /**< Shift value for USART_IRPRSSEL */
AnnaBridge 171:3a7713b1edbc 1006 #define _USART_IRCTRL_IRPRSSEL_MASK 0x70UL /**< Bit mask for USART_IRPRSSEL */
AnnaBridge 171:3a7713b1edbc 1007 #define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1008 #define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1009 #define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1010 #define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1011 #define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1012 #define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1013 #define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1014 #define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1015 #define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1016 #define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1017 #define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1018 #define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1019 #define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1020 #define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1021 #define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1022 #define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1023 #define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1024 #define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1025 #define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */
AnnaBridge 171:3a7713b1edbc 1026 #define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */
AnnaBridge 171:3a7713b1edbc 1027 #define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */
AnnaBridge 171:3a7713b1edbc 1028 #define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1029 #define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */
AnnaBridge 171:3a7713b1edbc 1030
AnnaBridge 171:3a7713b1edbc 1031 /* Bit fields for USART ROUTE */
AnnaBridge 171:3a7713b1edbc 1032 #define _USART_ROUTE_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1033 #define _USART_ROUTE_MASK 0x0000070FUL /**< Mask for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1034 #define USART_ROUTE_RXPEN (0x1UL << 0) /**< RX Pin Enable */
AnnaBridge 171:3a7713b1edbc 1035 #define _USART_ROUTE_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */
AnnaBridge 171:3a7713b1edbc 1036 #define _USART_ROUTE_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */
AnnaBridge 171:3a7713b1edbc 1037 #define _USART_ROUTE_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1038 #define USART_ROUTE_RXPEN_DEFAULT (_USART_ROUTE_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1039 #define USART_ROUTE_TXPEN (0x1UL << 1) /**< TX Pin Enable */
AnnaBridge 171:3a7713b1edbc 1040 #define _USART_ROUTE_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */
AnnaBridge 171:3a7713b1edbc 1041 #define _USART_ROUTE_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */
AnnaBridge 171:3a7713b1edbc 1042 #define _USART_ROUTE_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1043 #define USART_ROUTE_TXPEN_DEFAULT (_USART_ROUTE_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1044 #define USART_ROUTE_CSPEN (0x1UL << 2) /**< CS Pin Enable */
AnnaBridge 171:3a7713b1edbc 1045 #define _USART_ROUTE_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */
AnnaBridge 171:3a7713b1edbc 1046 #define _USART_ROUTE_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */
AnnaBridge 171:3a7713b1edbc 1047 #define _USART_ROUTE_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1048 #define USART_ROUTE_CSPEN_DEFAULT (_USART_ROUTE_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1049 #define USART_ROUTE_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */
AnnaBridge 171:3a7713b1edbc 1050 #define _USART_ROUTE_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */
AnnaBridge 171:3a7713b1edbc 1051 #define _USART_ROUTE_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */
AnnaBridge 171:3a7713b1edbc 1052 #define _USART_ROUTE_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1053 #define USART_ROUTE_CLKPEN_DEFAULT (_USART_ROUTE_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1054 #define _USART_ROUTE_LOCATION_SHIFT 8 /**< Shift value for USART_LOCATION */
AnnaBridge 171:3a7713b1edbc 1055 #define _USART_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for USART_LOCATION */
AnnaBridge 171:3a7713b1edbc 1056 #define _USART_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1057 #define _USART_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1058 #define _USART_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1059 #define _USART_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1060 #define _USART_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1061 #define _USART_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1062 #define _USART_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1063 #define USART_ROUTE_LOCATION_LOC0 (_USART_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1064 #define USART_ROUTE_LOCATION_DEFAULT (_USART_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1065 #define USART_ROUTE_LOCATION_LOC1 (_USART_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1066 #define USART_ROUTE_LOCATION_LOC2 (_USART_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1067 #define USART_ROUTE_LOCATION_LOC3 (_USART_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1068 #define USART_ROUTE_LOCATION_LOC4 (_USART_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1069 #define USART_ROUTE_LOCATION_LOC5 (_USART_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTE */
AnnaBridge 171:3a7713b1edbc 1070
AnnaBridge 171:3a7713b1edbc 1071 /* Bit fields for USART INPUT */
AnnaBridge 171:3a7713b1edbc 1072 #define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1073 #define _USART_INPUT_MASK 0x0000001FUL /**< Mask for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1074 #define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */
AnnaBridge 171:3a7713b1edbc 1075 #define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */
AnnaBridge 171:3a7713b1edbc 1076 #define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1077 #define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1078 #define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1079 #define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1080 #define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1081 #define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1082 #define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1083 #define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1084 #define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1085 #define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1086 #define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1087 #define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1088 #define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1089 #define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1090 #define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1091 #define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1092 #define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1093 #define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1094 #define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1095 #define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1096 #define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1097 #define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1098 #define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1099 #define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1100 #define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1101 #define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1102 #define USART_INPUT_RXPRS (0x1UL << 4) /**< PRS RX Enable */
AnnaBridge 171:3a7713b1edbc 1103 #define _USART_INPUT_RXPRS_SHIFT 4 /**< Shift value for USART_RXPRS */
AnnaBridge 171:3a7713b1edbc 1104 #define _USART_INPUT_RXPRS_MASK 0x10UL /**< Bit mask for USART_RXPRS */
AnnaBridge 171:3a7713b1edbc 1105 #define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1106 #define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_INPUT */
AnnaBridge 171:3a7713b1edbc 1107
AnnaBridge 171:3a7713b1edbc 1108 /* Bit fields for USART I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1109 #define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1110 #define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1111 #define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */
AnnaBridge 171:3a7713b1edbc 1112 #define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */
AnnaBridge 171:3a7713b1edbc 1113 #define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */
AnnaBridge 171:3a7713b1edbc 1114 #define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1115 #define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1116 #define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */
AnnaBridge 171:3a7713b1edbc 1117 #define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */
AnnaBridge 171:3a7713b1edbc 1118 #define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */
AnnaBridge 171:3a7713b1edbc 1119 #define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1120 #define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1121 #define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */
AnnaBridge 171:3a7713b1edbc 1122 #define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */
AnnaBridge 171:3a7713b1edbc 1123 #define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */
AnnaBridge 171:3a7713b1edbc 1124 #define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1125 #define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1126 #define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1127 #define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1128 #define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1129 #define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1130 #define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */
AnnaBridge 171:3a7713b1edbc 1131 #define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
AnnaBridge 171:3a7713b1edbc 1132 #define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
AnnaBridge 171:3a7713b1edbc 1133 #define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1134 #define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1135 #define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */
AnnaBridge 171:3a7713b1edbc 1136 #define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
AnnaBridge 171:3a7713b1edbc 1137 #define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
AnnaBridge 171:3a7713b1edbc 1138 #define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1139 #define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1140 #define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */
AnnaBridge 171:3a7713b1edbc 1141 #define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */
AnnaBridge 171:3a7713b1edbc 1142 #define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1143 #define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1144 #define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1145 #define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1146 #define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1147 #define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1148 #define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1149 #define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1150 #define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1151 #define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1152 #define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1153 #define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1154 #define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1155 #define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1156 #define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1157 #define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1158 #define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */
AnnaBridge 171:3a7713b1edbc 1159 #define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */
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AnnaBridge 171:3a7713b1edbc 1161 /** @} End of group EFM32LG_USART */
AnnaBridge 171:3a7713b1edbc 1162 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 1163