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TARGET_EFM32LG_STK3600/TOOLCHAIN_ARM_STD/efm32lg_dac.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32lg_dac.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32LG_DAC register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32LG_DAC
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32LG_DAC Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IOM uint32_t CTRL; /**< Control Register */
AnnaBridge 171:3a7713b1edbc 44 __IM uint32_t STATUS; /**< Status Register */
AnnaBridge 171:3a7713b1edbc 45 __IOM uint32_t CH0CTRL; /**< Channel 0 Control Register */
AnnaBridge 171:3a7713b1edbc 46 __IOM uint32_t CH1CTRL; /**< Channel 1 Control Register */
AnnaBridge 171:3a7713b1edbc 47 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 48 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 49 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 171:3a7713b1edbc 50 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 171:3a7713b1edbc 51 __IOM uint32_t CH0DATA; /**< Channel 0 Data Register */
AnnaBridge 171:3a7713b1edbc 52 __IOM uint32_t CH1DATA; /**< Channel 1 Data Register */
AnnaBridge 171:3a7713b1edbc 53 __IOM uint32_t COMBDATA; /**< Combined Data Register */
AnnaBridge 171:3a7713b1edbc 54 __IOM uint32_t CAL; /**< Calibration Register */
AnnaBridge 171:3a7713b1edbc 55 __IOM uint32_t BIASPROG; /**< Bias Programming Register */
AnnaBridge 171:3a7713b1edbc 56 uint32_t RESERVED0[8]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 57 __IOM uint32_t OPACTRL; /**< Operational Amplifier Control Register */
AnnaBridge 171:3a7713b1edbc 58 __IOM uint32_t OPAOFFSET; /**< Operational Amplifier Offset Register */
AnnaBridge 171:3a7713b1edbc 59 __IOM uint32_t OPA0MUX; /**< Operational Amplifier Mux Configuration Register */
AnnaBridge 171:3a7713b1edbc 60 __IOM uint32_t OPA1MUX; /**< Operational Amplifier Mux Configuration Register */
AnnaBridge 171:3a7713b1edbc 61 __IOM uint32_t OPA2MUX; /**< Operational Amplifier Mux Configuration Register */
AnnaBridge 171:3a7713b1edbc 62 } DAC_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 63
AnnaBridge 171:3a7713b1edbc 64 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 65 * @defgroup EFM32LG_DAC_BitFields
AnnaBridge 171:3a7713b1edbc 66 * @{
AnnaBridge 171:3a7713b1edbc 67 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 /* Bit fields for DAC CTRL */
AnnaBridge 171:3a7713b1edbc 70 #define _DAC_CTRL_RESETVALUE 0x00000010UL /**< Default value for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 71 #define _DAC_CTRL_MASK 0x003703FFUL /**< Mask for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 72 #define DAC_CTRL_DIFF (0x1UL << 0) /**< Differential Mode */
AnnaBridge 171:3a7713b1edbc 73 #define _DAC_CTRL_DIFF_SHIFT 0 /**< Shift value for DAC_DIFF */
AnnaBridge 171:3a7713b1edbc 74 #define _DAC_CTRL_DIFF_MASK 0x1UL /**< Bit mask for DAC_DIFF */
AnnaBridge 171:3a7713b1edbc 75 #define _DAC_CTRL_DIFF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 76 #define DAC_CTRL_DIFF_DEFAULT (_DAC_CTRL_DIFF_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 77 #define DAC_CTRL_SINEMODE (0x1UL << 1) /**< Sine Mode */
AnnaBridge 171:3a7713b1edbc 78 #define _DAC_CTRL_SINEMODE_SHIFT 1 /**< Shift value for DAC_SINEMODE */
AnnaBridge 171:3a7713b1edbc 79 #define _DAC_CTRL_SINEMODE_MASK 0x2UL /**< Bit mask for DAC_SINEMODE */
AnnaBridge 171:3a7713b1edbc 80 #define _DAC_CTRL_SINEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 81 #define DAC_CTRL_SINEMODE_DEFAULT (_DAC_CTRL_SINEMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 82 #define _DAC_CTRL_CONVMODE_SHIFT 2 /**< Shift value for DAC_CONVMODE */
AnnaBridge 171:3a7713b1edbc 83 #define _DAC_CTRL_CONVMODE_MASK 0xCUL /**< Bit mask for DAC_CONVMODE */
AnnaBridge 171:3a7713b1edbc 84 #define _DAC_CTRL_CONVMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 85 #define _DAC_CTRL_CONVMODE_CONTINUOUS 0x00000000UL /**< Mode CONTINUOUS for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 86 #define _DAC_CTRL_CONVMODE_SAMPLEHOLD 0x00000001UL /**< Mode SAMPLEHOLD for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 87 #define _DAC_CTRL_CONVMODE_SAMPLEOFF 0x00000002UL /**< Mode SAMPLEOFF for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 88 #define DAC_CTRL_CONVMODE_DEFAULT (_DAC_CTRL_CONVMODE_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 89 #define DAC_CTRL_CONVMODE_CONTINUOUS (_DAC_CTRL_CONVMODE_CONTINUOUS << 2) /**< Shifted mode CONTINUOUS for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 90 #define DAC_CTRL_CONVMODE_SAMPLEHOLD (_DAC_CTRL_CONVMODE_SAMPLEHOLD << 2) /**< Shifted mode SAMPLEHOLD for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 91 #define DAC_CTRL_CONVMODE_SAMPLEOFF (_DAC_CTRL_CONVMODE_SAMPLEOFF << 2) /**< Shifted mode SAMPLEOFF for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 92 #define _DAC_CTRL_OUTMODE_SHIFT 4 /**< Shift value for DAC_OUTMODE */
AnnaBridge 171:3a7713b1edbc 93 #define _DAC_CTRL_OUTMODE_MASK 0x30UL /**< Bit mask for DAC_OUTMODE */
AnnaBridge 171:3a7713b1edbc 94 #define _DAC_CTRL_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 95 #define _DAC_CTRL_OUTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 96 #define _DAC_CTRL_OUTMODE_PIN 0x00000001UL /**< Mode PIN for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 97 #define _DAC_CTRL_OUTMODE_ADC 0x00000002UL /**< Mode ADC for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 98 #define _DAC_CTRL_OUTMODE_PINADC 0x00000003UL /**< Mode PINADC for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 99 #define DAC_CTRL_OUTMODE_DISABLE (_DAC_CTRL_OUTMODE_DISABLE << 4) /**< Shifted mode DISABLE for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 100 #define DAC_CTRL_OUTMODE_DEFAULT (_DAC_CTRL_OUTMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 101 #define DAC_CTRL_OUTMODE_PIN (_DAC_CTRL_OUTMODE_PIN << 4) /**< Shifted mode PIN for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 102 #define DAC_CTRL_OUTMODE_ADC (_DAC_CTRL_OUTMODE_ADC << 4) /**< Shifted mode ADC for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 103 #define DAC_CTRL_OUTMODE_PINADC (_DAC_CTRL_OUTMODE_PINADC << 4) /**< Shifted mode PINADC for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 104 #define DAC_CTRL_OUTENPRS (0x1UL << 6) /**< PRS Controlled Output Enable */
AnnaBridge 171:3a7713b1edbc 105 #define _DAC_CTRL_OUTENPRS_SHIFT 6 /**< Shift value for DAC_OUTENPRS */
AnnaBridge 171:3a7713b1edbc 106 #define _DAC_CTRL_OUTENPRS_MASK 0x40UL /**< Bit mask for DAC_OUTENPRS */
AnnaBridge 171:3a7713b1edbc 107 #define _DAC_CTRL_OUTENPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 108 #define DAC_CTRL_OUTENPRS_DEFAULT (_DAC_CTRL_OUTENPRS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 109 #define DAC_CTRL_CH0PRESCRST (0x1UL << 7) /**< Channel 0 Start Reset Prescaler */
AnnaBridge 171:3a7713b1edbc 110 #define _DAC_CTRL_CH0PRESCRST_SHIFT 7 /**< Shift value for DAC_CH0PRESCRST */
AnnaBridge 171:3a7713b1edbc 111 #define _DAC_CTRL_CH0PRESCRST_MASK 0x80UL /**< Bit mask for DAC_CH0PRESCRST */
AnnaBridge 171:3a7713b1edbc 112 #define _DAC_CTRL_CH0PRESCRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 113 #define DAC_CTRL_CH0PRESCRST_DEFAULT (_DAC_CTRL_CH0PRESCRST_DEFAULT << 7) /**< Shifted mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 114 #define _DAC_CTRL_REFSEL_SHIFT 8 /**< Shift value for DAC_REFSEL */
AnnaBridge 171:3a7713b1edbc 115 #define _DAC_CTRL_REFSEL_MASK 0x300UL /**< Bit mask for DAC_REFSEL */
AnnaBridge 171:3a7713b1edbc 116 #define _DAC_CTRL_REFSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 117 #define _DAC_CTRL_REFSEL_1V25 0x00000000UL /**< Mode 1V25 for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 118 #define _DAC_CTRL_REFSEL_2V5 0x00000001UL /**< Mode 2V5 for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 119 #define _DAC_CTRL_REFSEL_VDD 0x00000002UL /**< Mode VDD for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 120 #define DAC_CTRL_REFSEL_DEFAULT (_DAC_CTRL_REFSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 121 #define DAC_CTRL_REFSEL_1V25 (_DAC_CTRL_REFSEL_1V25 << 8) /**< Shifted mode 1V25 for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 122 #define DAC_CTRL_REFSEL_2V5 (_DAC_CTRL_REFSEL_2V5 << 8) /**< Shifted mode 2V5 for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 123 #define DAC_CTRL_REFSEL_VDD (_DAC_CTRL_REFSEL_VDD << 8) /**< Shifted mode VDD for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 124 #define _DAC_CTRL_PRESC_SHIFT 16 /**< Shift value for DAC_PRESC */
AnnaBridge 171:3a7713b1edbc 125 #define _DAC_CTRL_PRESC_MASK 0x70000UL /**< Bit mask for DAC_PRESC */
AnnaBridge 171:3a7713b1edbc 126 #define _DAC_CTRL_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 127 #define _DAC_CTRL_PRESC_NODIVISION 0x00000000UL /**< Mode NODIVISION for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 128 #define DAC_CTRL_PRESC_DEFAULT (_DAC_CTRL_PRESC_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 129 #define DAC_CTRL_PRESC_NODIVISION (_DAC_CTRL_PRESC_NODIVISION << 16) /**< Shifted mode NODIVISION for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 130 #define _DAC_CTRL_REFRSEL_SHIFT 20 /**< Shift value for DAC_REFRSEL */
AnnaBridge 171:3a7713b1edbc 131 #define _DAC_CTRL_REFRSEL_MASK 0x300000UL /**< Bit mask for DAC_REFRSEL */
AnnaBridge 171:3a7713b1edbc 132 #define _DAC_CTRL_REFRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 133 #define _DAC_CTRL_REFRSEL_8CYCLES 0x00000000UL /**< Mode 8CYCLES for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 134 #define _DAC_CTRL_REFRSEL_16CYCLES 0x00000001UL /**< Mode 16CYCLES for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 135 #define _DAC_CTRL_REFRSEL_32CYCLES 0x00000002UL /**< Mode 32CYCLES for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 136 #define _DAC_CTRL_REFRSEL_64CYCLES 0x00000003UL /**< Mode 64CYCLES for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 137 #define DAC_CTRL_REFRSEL_DEFAULT (_DAC_CTRL_REFRSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 138 #define DAC_CTRL_REFRSEL_8CYCLES (_DAC_CTRL_REFRSEL_8CYCLES << 20) /**< Shifted mode 8CYCLES for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 139 #define DAC_CTRL_REFRSEL_16CYCLES (_DAC_CTRL_REFRSEL_16CYCLES << 20) /**< Shifted mode 16CYCLES for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 140 #define DAC_CTRL_REFRSEL_32CYCLES (_DAC_CTRL_REFRSEL_32CYCLES << 20) /**< Shifted mode 32CYCLES for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 141 #define DAC_CTRL_REFRSEL_64CYCLES (_DAC_CTRL_REFRSEL_64CYCLES << 20) /**< Shifted mode 64CYCLES for DAC_CTRL */
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 /* Bit fields for DAC STATUS */
AnnaBridge 171:3a7713b1edbc 144 #define _DAC_STATUS_RESETVALUE 0x00000000UL /**< Default value for DAC_STATUS */
AnnaBridge 171:3a7713b1edbc 145 #define _DAC_STATUS_MASK 0x00000003UL /**< Mask for DAC_STATUS */
AnnaBridge 171:3a7713b1edbc 146 #define DAC_STATUS_CH0DV (0x1UL << 0) /**< Channel 0 Data Valid */
AnnaBridge 171:3a7713b1edbc 147 #define _DAC_STATUS_CH0DV_SHIFT 0 /**< Shift value for DAC_CH0DV */
AnnaBridge 171:3a7713b1edbc 148 #define _DAC_STATUS_CH0DV_MASK 0x1UL /**< Bit mask for DAC_CH0DV */
AnnaBridge 171:3a7713b1edbc 149 #define _DAC_STATUS_CH0DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */
AnnaBridge 171:3a7713b1edbc 150 #define DAC_STATUS_CH0DV_DEFAULT (_DAC_STATUS_CH0DV_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_STATUS */
AnnaBridge 171:3a7713b1edbc 151 #define DAC_STATUS_CH1DV (0x1UL << 1) /**< Channel 1 Data Valid */
AnnaBridge 171:3a7713b1edbc 152 #define _DAC_STATUS_CH1DV_SHIFT 1 /**< Shift value for DAC_CH1DV */
AnnaBridge 171:3a7713b1edbc 153 #define _DAC_STATUS_CH1DV_MASK 0x2UL /**< Bit mask for DAC_CH1DV */
AnnaBridge 171:3a7713b1edbc 154 #define _DAC_STATUS_CH1DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_STATUS */
AnnaBridge 171:3a7713b1edbc 155 #define DAC_STATUS_CH1DV_DEFAULT (_DAC_STATUS_CH1DV_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_STATUS */
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 /* Bit fields for DAC CH0CTRL */
AnnaBridge 171:3a7713b1edbc 158 #define _DAC_CH0CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 159 #define _DAC_CH0CTRL_MASK 0x000000F7UL /**< Mask for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 160 #define DAC_CH0CTRL_EN (0x1UL << 0) /**< Channel 0 Enable */
AnnaBridge 171:3a7713b1edbc 161 #define _DAC_CH0CTRL_EN_SHIFT 0 /**< Shift value for DAC_EN */
AnnaBridge 171:3a7713b1edbc 162 #define _DAC_CH0CTRL_EN_MASK 0x1UL /**< Bit mask for DAC_EN */
AnnaBridge 171:3a7713b1edbc 163 #define _DAC_CH0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 164 #define DAC_CH0CTRL_EN_DEFAULT (_DAC_CH0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 165 #define DAC_CH0CTRL_REFREN (0x1UL << 1) /**< Channel 0 Automatic Refresh Enable */
AnnaBridge 171:3a7713b1edbc 166 #define _DAC_CH0CTRL_REFREN_SHIFT 1 /**< Shift value for DAC_REFREN */
AnnaBridge 171:3a7713b1edbc 167 #define _DAC_CH0CTRL_REFREN_MASK 0x2UL /**< Bit mask for DAC_REFREN */
AnnaBridge 171:3a7713b1edbc 168 #define _DAC_CH0CTRL_REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 169 #define DAC_CH0CTRL_REFREN_DEFAULT (_DAC_CH0CTRL_REFREN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 170 #define DAC_CH0CTRL_PRSEN (0x1UL << 2) /**< Channel 0 PRS Trigger Enable */
AnnaBridge 171:3a7713b1edbc 171 #define _DAC_CH0CTRL_PRSEN_SHIFT 2 /**< Shift value for DAC_PRSEN */
AnnaBridge 171:3a7713b1edbc 172 #define _DAC_CH0CTRL_PRSEN_MASK 0x4UL /**< Bit mask for DAC_PRSEN */
AnnaBridge 171:3a7713b1edbc 173 #define _DAC_CH0CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 174 #define DAC_CH0CTRL_PRSEN_DEFAULT (_DAC_CH0CTRL_PRSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 175 #define _DAC_CH0CTRL_PRSSEL_SHIFT 4 /**< Shift value for DAC_PRSSEL */
AnnaBridge 171:3a7713b1edbc 176 #define _DAC_CH0CTRL_PRSSEL_MASK 0xF0UL /**< Bit mask for DAC_PRSSEL */
AnnaBridge 171:3a7713b1edbc 177 #define _DAC_CH0CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 178 #define _DAC_CH0CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 179 #define _DAC_CH0CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 180 #define _DAC_CH0CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 181 #define _DAC_CH0CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 182 #define _DAC_CH0CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 183 #define _DAC_CH0CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 184 #define _DAC_CH0CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 185 #define _DAC_CH0CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 186 #define _DAC_CH0CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 187 #define _DAC_CH0CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 188 #define _DAC_CH0CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 189 #define _DAC_CH0CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 190 #define DAC_CH0CTRL_PRSSEL_DEFAULT (_DAC_CH0CTRL_PRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 191 #define DAC_CH0CTRL_PRSSEL_PRSCH0 (_DAC_CH0CTRL_PRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 192 #define DAC_CH0CTRL_PRSSEL_PRSCH1 (_DAC_CH0CTRL_PRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 193 #define DAC_CH0CTRL_PRSSEL_PRSCH2 (_DAC_CH0CTRL_PRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 194 #define DAC_CH0CTRL_PRSSEL_PRSCH3 (_DAC_CH0CTRL_PRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 195 #define DAC_CH0CTRL_PRSSEL_PRSCH4 (_DAC_CH0CTRL_PRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 196 #define DAC_CH0CTRL_PRSSEL_PRSCH5 (_DAC_CH0CTRL_PRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 197 #define DAC_CH0CTRL_PRSSEL_PRSCH6 (_DAC_CH0CTRL_PRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 198 #define DAC_CH0CTRL_PRSSEL_PRSCH7 (_DAC_CH0CTRL_PRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 199 #define DAC_CH0CTRL_PRSSEL_PRSCH8 (_DAC_CH0CTRL_PRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 200 #define DAC_CH0CTRL_PRSSEL_PRSCH9 (_DAC_CH0CTRL_PRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 201 #define DAC_CH0CTRL_PRSSEL_PRSCH10 (_DAC_CH0CTRL_PRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 202 #define DAC_CH0CTRL_PRSSEL_PRSCH11 (_DAC_CH0CTRL_PRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for DAC_CH0CTRL */
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204 /* Bit fields for DAC CH1CTRL */
AnnaBridge 171:3a7713b1edbc 205 #define _DAC_CH1CTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 206 #define _DAC_CH1CTRL_MASK 0x000000F7UL /**< Mask for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 207 #define DAC_CH1CTRL_EN (0x1UL << 0) /**< Channel 1 Enable */
AnnaBridge 171:3a7713b1edbc 208 #define _DAC_CH1CTRL_EN_SHIFT 0 /**< Shift value for DAC_EN */
AnnaBridge 171:3a7713b1edbc 209 #define _DAC_CH1CTRL_EN_MASK 0x1UL /**< Bit mask for DAC_EN */
AnnaBridge 171:3a7713b1edbc 210 #define _DAC_CH1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 211 #define DAC_CH1CTRL_EN_DEFAULT (_DAC_CH1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 212 #define DAC_CH1CTRL_REFREN (0x1UL << 1) /**< Channel 1 Automatic Refresh Enable */
AnnaBridge 171:3a7713b1edbc 213 #define _DAC_CH1CTRL_REFREN_SHIFT 1 /**< Shift value for DAC_REFREN */
AnnaBridge 171:3a7713b1edbc 214 #define _DAC_CH1CTRL_REFREN_MASK 0x2UL /**< Bit mask for DAC_REFREN */
AnnaBridge 171:3a7713b1edbc 215 #define _DAC_CH1CTRL_REFREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 216 #define DAC_CH1CTRL_REFREN_DEFAULT (_DAC_CH1CTRL_REFREN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 217 #define DAC_CH1CTRL_PRSEN (0x1UL << 2) /**< Channel 1 PRS Trigger Enable */
AnnaBridge 171:3a7713b1edbc 218 #define _DAC_CH1CTRL_PRSEN_SHIFT 2 /**< Shift value for DAC_PRSEN */
AnnaBridge 171:3a7713b1edbc 219 #define _DAC_CH1CTRL_PRSEN_MASK 0x4UL /**< Bit mask for DAC_PRSEN */
AnnaBridge 171:3a7713b1edbc 220 #define _DAC_CH1CTRL_PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 221 #define DAC_CH1CTRL_PRSEN_DEFAULT (_DAC_CH1CTRL_PRSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 222 #define _DAC_CH1CTRL_PRSSEL_SHIFT 4 /**< Shift value for DAC_PRSSEL */
AnnaBridge 171:3a7713b1edbc 223 #define _DAC_CH1CTRL_PRSSEL_MASK 0xF0UL /**< Bit mask for DAC_PRSSEL */
AnnaBridge 171:3a7713b1edbc 224 #define _DAC_CH1CTRL_PRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 225 #define _DAC_CH1CTRL_PRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 226 #define _DAC_CH1CTRL_PRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 227 #define _DAC_CH1CTRL_PRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 228 #define _DAC_CH1CTRL_PRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 229 #define _DAC_CH1CTRL_PRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 230 #define _DAC_CH1CTRL_PRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 231 #define _DAC_CH1CTRL_PRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 232 #define _DAC_CH1CTRL_PRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 233 #define _DAC_CH1CTRL_PRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 234 #define _DAC_CH1CTRL_PRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 235 #define _DAC_CH1CTRL_PRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 236 #define _DAC_CH1CTRL_PRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 237 #define DAC_CH1CTRL_PRSSEL_DEFAULT (_DAC_CH1CTRL_PRSSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 238 #define DAC_CH1CTRL_PRSSEL_PRSCH0 (_DAC_CH1CTRL_PRSSEL_PRSCH0 << 4) /**< Shifted mode PRSCH0 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 239 #define DAC_CH1CTRL_PRSSEL_PRSCH1 (_DAC_CH1CTRL_PRSSEL_PRSCH1 << 4) /**< Shifted mode PRSCH1 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 240 #define DAC_CH1CTRL_PRSSEL_PRSCH2 (_DAC_CH1CTRL_PRSSEL_PRSCH2 << 4) /**< Shifted mode PRSCH2 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 241 #define DAC_CH1CTRL_PRSSEL_PRSCH3 (_DAC_CH1CTRL_PRSSEL_PRSCH3 << 4) /**< Shifted mode PRSCH3 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 242 #define DAC_CH1CTRL_PRSSEL_PRSCH4 (_DAC_CH1CTRL_PRSSEL_PRSCH4 << 4) /**< Shifted mode PRSCH4 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 243 #define DAC_CH1CTRL_PRSSEL_PRSCH5 (_DAC_CH1CTRL_PRSSEL_PRSCH5 << 4) /**< Shifted mode PRSCH5 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 244 #define DAC_CH1CTRL_PRSSEL_PRSCH6 (_DAC_CH1CTRL_PRSSEL_PRSCH6 << 4) /**< Shifted mode PRSCH6 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 245 #define DAC_CH1CTRL_PRSSEL_PRSCH7 (_DAC_CH1CTRL_PRSSEL_PRSCH7 << 4) /**< Shifted mode PRSCH7 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 246 #define DAC_CH1CTRL_PRSSEL_PRSCH8 (_DAC_CH1CTRL_PRSSEL_PRSCH8 << 4) /**< Shifted mode PRSCH8 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 247 #define DAC_CH1CTRL_PRSSEL_PRSCH9 (_DAC_CH1CTRL_PRSSEL_PRSCH9 << 4) /**< Shifted mode PRSCH9 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 248 #define DAC_CH1CTRL_PRSSEL_PRSCH10 (_DAC_CH1CTRL_PRSSEL_PRSCH10 << 4) /**< Shifted mode PRSCH10 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 249 #define DAC_CH1CTRL_PRSSEL_PRSCH11 (_DAC_CH1CTRL_PRSSEL_PRSCH11 << 4) /**< Shifted mode PRSCH11 for DAC_CH1CTRL */
AnnaBridge 171:3a7713b1edbc 250
AnnaBridge 171:3a7713b1edbc 251 /* Bit fields for DAC IEN */
AnnaBridge 171:3a7713b1edbc 252 #define _DAC_IEN_RESETVALUE 0x00000000UL /**< Default value for DAC_IEN */
AnnaBridge 171:3a7713b1edbc 253 #define _DAC_IEN_MASK 0x00000033UL /**< Mask for DAC_IEN */
AnnaBridge 171:3a7713b1edbc 254 #define DAC_IEN_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 255 #define _DAC_IEN_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
AnnaBridge 171:3a7713b1edbc 256 #define _DAC_IEN_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
AnnaBridge 171:3a7713b1edbc 257 #define _DAC_IEN_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
AnnaBridge 171:3a7713b1edbc 258 #define DAC_IEN_CH0_DEFAULT (_DAC_IEN_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IEN */
AnnaBridge 171:3a7713b1edbc 259 #define DAC_IEN_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 260 #define _DAC_IEN_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
AnnaBridge 171:3a7713b1edbc 261 #define _DAC_IEN_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
AnnaBridge 171:3a7713b1edbc 262 #define _DAC_IEN_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
AnnaBridge 171:3a7713b1edbc 263 #define DAC_IEN_CH1_DEFAULT (_DAC_IEN_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IEN */
AnnaBridge 171:3a7713b1edbc 264 #define DAC_IEN_CH0UF (0x1UL << 4) /**< Channel 0 Conversion Data Underflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 265 #define _DAC_IEN_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
AnnaBridge 171:3a7713b1edbc 266 #define _DAC_IEN_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
AnnaBridge 171:3a7713b1edbc 267 #define _DAC_IEN_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
AnnaBridge 171:3a7713b1edbc 268 #define DAC_IEN_CH0UF_DEFAULT (_DAC_IEN_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IEN */
AnnaBridge 171:3a7713b1edbc 269 #define DAC_IEN_CH1UF (0x1UL << 5) /**< Channel 1 Conversion Data Underflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 270 #define _DAC_IEN_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
AnnaBridge 171:3a7713b1edbc 271 #define _DAC_IEN_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
AnnaBridge 171:3a7713b1edbc 272 #define _DAC_IEN_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IEN */
AnnaBridge 171:3a7713b1edbc 273 #define DAC_IEN_CH1UF_DEFAULT (_DAC_IEN_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IEN */
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 /* Bit fields for DAC IF */
AnnaBridge 171:3a7713b1edbc 276 #define _DAC_IF_RESETVALUE 0x00000000UL /**< Default value for DAC_IF */
AnnaBridge 171:3a7713b1edbc 277 #define _DAC_IF_MASK 0x00000033UL /**< Mask for DAC_IF */
AnnaBridge 171:3a7713b1edbc 278 #define DAC_IF_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 279 #define _DAC_IF_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
AnnaBridge 171:3a7713b1edbc 280 #define _DAC_IF_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
AnnaBridge 171:3a7713b1edbc 281 #define _DAC_IF_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
AnnaBridge 171:3a7713b1edbc 282 #define DAC_IF_CH0_DEFAULT (_DAC_IF_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IF */
AnnaBridge 171:3a7713b1edbc 283 #define DAC_IF_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 284 #define _DAC_IF_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
AnnaBridge 171:3a7713b1edbc 285 #define _DAC_IF_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
AnnaBridge 171:3a7713b1edbc 286 #define _DAC_IF_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
AnnaBridge 171:3a7713b1edbc 287 #define DAC_IF_CH1_DEFAULT (_DAC_IF_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IF */
AnnaBridge 171:3a7713b1edbc 288 #define DAC_IF_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 289 #define _DAC_IF_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
AnnaBridge 171:3a7713b1edbc 290 #define _DAC_IF_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
AnnaBridge 171:3a7713b1edbc 291 #define _DAC_IF_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
AnnaBridge 171:3a7713b1edbc 292 #define DAC_IF_CH0UF_DEFAULT (_DAC_IF_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IF */
AnnaBridge 171:3a7713b1edbc 293 #define DAC_IF_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 294 #define _DAC_IF_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
AnnaBridge 171:3a7713b1edbc 295 #define _DAC_IF_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
AnnaBridge 171:3a7713b1edbc 296 #define _DAC_IF_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IF */
AnnaBridge 171:3a7713b1edbc 297 #define DAC_IF_CH1UF_DEFAULT (_DAC_IF_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IF */
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 /* Bit fields for DAC IFS */
AnnaBridge 171:3a7713b1edbc 300 #define _DAC_IFS_RESETVALUE 0x00000000UL /**< Default value for DAC_IFS */
AnnaBridge 171:3a7713b1edbc 301 #define _DAC_IFS_MASK 0x00000033UL /**< Mask for DAC_IFS */
AnnaBridge 171:3a7713b1edbc 302 #define DAC_IFS_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 303 #define _DAC_IFS_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
AnnaBridge 171:3a7713b1edbc 304 #define _DAC_IFS_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
AnnaBridge 171:3a7713b1edbc 305 #define _DAC_IFS_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
AnnaBridge 171:3a7713b1edbc 306 #define DAC_IFS_CH0_DEFAULT (_DAC_IFS_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IFS */
AnnaBridge 171:3a7713b1edbc 307 #define DAC_IFS_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 308 #define _DAC_IFS_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
AnnaBridge 171:3a7713b1edbc 309 #define _DAC_IFS_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
AnnaBridge 171:3a7713b1edbc 310 #define _DAC_IFS_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
AnnaBridge 171:3a7713b1edbc 311 #define DAC_IFS_CH1_DEFAULT (_DAC_IFS_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IFS */
AnnaBridge 171:3a7713b1edbc 312 #define DAC_IFS_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 313 #define _DAC_IFS_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
AnnaBridge 171:3a7713b1edbc 314 #define _DAC_IFS_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
AnnaBridge 171:3a7713b1edbc 315 #define _DAC_IFS_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
AnnaBridge 171:3a7713b1edbc 316 #define DAC_IFS_CH0UF_DEFAULT (_DAC_IFS_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IFS */
AnnaBridge 171:3a7713b1edbc 317 #define DAC_IFS_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 318 #define _DAC_IFS_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
AnnaBridge 171:3a7713b1edbc 319 #define _DAC_IFS_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
AnnaBridge 171:3a7713b1edbc 320 #define _DAC_IFS_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFS */
AnnaBridge 171:3a7713b1edbc 321 #define DAC_IFS_CH1UF_DEFAULT (_DAC_IFS_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IFS */
AnnaBridge 171:3a7713b1edbc 322
AnnaBridge 171:3a7713b1edbc 323 /* Bit fields for DAC IFC */
AnnaBridge 171:3a7713b1edbc 324 #define _DAC_IFC_RESETVALUE 0x00000000UL /**< Default value for DAC_IFC */
AnnaBridge 171:3a7713b1edbc 325 #define _DAC_IFC_MASK 0x00000033UL /**< Mask for DAC_IFC */
AnnaBridge 171:3a7713b1edbc 326 #define DAC_IFC_CH0 (0x1UL << 0) /**< Channel 0 Conversion Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 327 #define _DAC_IFC_CH0_SHIFT 0 /**< Shift value for DAC_CH0 */
AnnaBridge 171:3a7713b1edbc 328 #define _DAC_IFC_CH0_MASK 0x1UL /**< Bit mask for DAC_CH0 */
AnnaBridge 171:3a7713b1edbc 329 #define _DAC_IFC_CH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
AnnaBridge 171:3a7713b1edbc 330 #define DAC_IFC_CH0_DEFAULT (_DAC_IFC_CH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_IFC */
AnnaBridge 171:3a7713b1edbc 331 #define DAC_IFC_CH1 (0x1UL << 1) /**< Channel 1 Conversion Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 332 #define _DAC_IFC_CH1_SHIFT 1 /**< Shift value for DAC_CH1 */
AnnaBridge 171:3a7713b1edbc 333 #define _DAC_IFC_CH1_MASK 0x2UL /**< Bit mask for DAC_CH1 */
AnnaBridge 171:3a7713b1edbc 334 #define _DAC_IFC_CH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
AnnaBridge 171:3a7713b1edbc 335 #define DAC_IFC_CH1_DEFAULT (_DAC_IFC_CH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_IFC */
AnnaBridge 171:3a7713b1edbc 336 #define DAC_IFC_CH0UF (0x1UL << 4) /**< Channel 0 Data Underflow Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 337 #define _DAC_IFC_CH0UF_SHIFT 4 /**< Shift value for DAC_CH0UF */
AnnaBridge 171:3a7713b1edbc 338 #define _DAC_IFC_CH0UF_MASK 0x10UL /**< Bit mask for DAC_CH0UF */
AnnaBridge 171:3a7713b1edbc 339 #define _DAC_IFC_CH0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
AnnaBridge 171:3a7713b1edbc 340 #define DAC_IFC_CH0UF_DEFAULT (_DAC_IFC_CH0UF_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_IFC */
AnnaBridge 171:3a7713b1edbc 341 #define DAC_IFC_CH1UF (0x1UL << 5) /**< Channel 1 Data Underflow Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 342 #define _DAC_IFC_CH1UF_SHIFT 5 /**< Shift value for DAC_CH1UF */
AnnaBridge 171:3a7713b1edbc 343 #define _DAC_IFC_CH1UF_MASK 0x20UL /**< Bit mask for DAC_CH1UF */
AnnaBridge 171:3a7713b1edbc 344 #define _DAC_IFC_CH1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_IFC */
AnnaBridge 171:3a7713b1edbc 345 #define DAC_IFC_CH1UF_DEFAULT (_DAC_IFC_CH1UF_DEFAULT << 5) /**< Shifted mode DEFAULT for DAC_IFC */
AnnaBridge 171:3a7713b1edbc 346
AnnaBridge 171:3a7713b1edbc 347 /* Bit fields for DAC CH0DATA */
AnnaBridge 171:3a7713b1edbc 348 #define _DAC_CH0DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH0DATA */
AnnaBridge 171:3a7713b1edbc 349 #define _DAC_CH0DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH0DATA */
AnnaBridge 171:3a7713b1edbc 350 #define _DAC_CH0DATA_DATA_SHIFT 0 /**< Shift value for DAC_DATA */
AnnaBridge 171:3a7713b1edbc 351 #define _DAC_CH0DATA_DATA_MASK 0xFFFUL /**< Bit mask for DAC_DATA */
AnnaBridge 171:3a7713b1edbc 352 #define _DAC_CH0DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH0DATA */
AnnaBridge 171:3a7713b1edbc 353 #define DAC_CH0DATA_DATA_DEFAULT (_DAC_CH0DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH0DATA */
AnnaBridge 171:3a7713b1edbc 354
AnnaBridge 171:3a7713b1edbc 355 /* Bit fields for DAC CH1DATA */
AnnaBridge 171:3a7713b1edbc 356 #define _DAC_CH1DATA_RESETVALUE 0x00000000UL /**< Default value for DAC_CH1DATA */
AnnaBridge 171:3a7713b1edbc 357 #define _DAC_CH1DATA_MASK 0x00000FFFUL /**< Mask for DAC_CH1DATA */
AnnaBridge 171:3a7713b1edbc 358 #define _DAC_CH1DATA_DATA_SHIFT 0 /**< Shift value for DAC_DATA */
AnnaBridge 171:3a7713b1edbc 359 #define _DAC_CH1DATA_DATA_MASK 0xFFFUL /**< Bit mask for DAC_DATA */
AnnaBridge 171:3a7713b1edbc 360 #define _DAC_CH1DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CH1DATA */
AnnaBridge 171:3a7713b1edbc 361 #define DAC_CH1DATA_DATA_DEFAULT (_DAC_CH1DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CH1DATA */
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363 /* Bit fields for DAC COMBDATA */
AnnaBridge 171:3a7713b1edbc 364 #define _DAC_COMBDATA_RESETVALUE 0x00000000UL /**< Default value for DAC_COMBDATA */
AnnaBridge 171:3a7713b1edbc 365 #define _DAC_COMBDATA_MASK 0x0FFF0FFFUL /**< Mask for DAC_COMBDATA */
AnnaBridge 171:3a7713b1edbc 366 #define _DAC_COMBDATA_CH0DATA_SHIFT 0 /**< Shift value for DAC_CH0DATA */
AnnaBridge 171:3a7713b1edbc 367 #define _DAC_COMBDATA_CH0DATA_MASK 0xFFFUL /**< Bit mask for DAC_CH0DATA */
AnnaBridge 171:3a7713b1edbc 368 #define _DAC_COMBDATA_CH0DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */
AnnaBridge 171:3a7713b1edbc 369 #define DAC_COMBDATA_CH0DATA_DEFAULT (_DAC_COMBDATA_CH0DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_COMBDATA */
AnnaBridge 171:3a7713b1edbc 370 #define _DAC_COMBDATA_CH1DATA_SHIFT 16 /**< Shift value for DAC_CH1DATA */
AnnaBridge 171:3a7713b1edbc 371 #define _DAC_COMBDATA_CH1DATA_MASK 0xFFF0000UL /**< Bit mask for DAC_CH1DATA */
AnnaBridge 171:3a7713b1edbc 372 #define _DAC_COMBDATA_CH1DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_COMBDATA */
AnnaBridge 171:3a7713b1edbc 373 #define DAC_COMBDATA_CH1DATA_DEFAULT (_DAC_COMBDATA_CH1DATA_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_COMBDATA */
AnnaBridge 171:3a7713b1edbc 374
AnnaBridge 171:3a7713b1edbc 375 /* Bit fields for DAC CAL */
AnnaBridge 171:3a7713b1edbc 376 #define _DAC_CAL_RESETVALUE 0x00400000UL /**< Default value for DAC_CAL */
AnnaBridge 171:3a7713b1edbc 377 #define _DAC_CAL_MASK 0x007F3F3FUL /**< Mask for DAC_CAL */
AnnaBridge 171:3a7713b1edbc 378 #define _DAC_CAL_CH0OFFSET_SHIFT 0 /**< Shift value for DAC_CH0OFFSET */
AnnaBridge 171:3a7713b1edbc 379 #define _DAC_CAL_CH0OFFSET_MASK 0x3FUL /**< Bit mask for DAC_CH0OFFSET */
AnnaBridge 171:3a7713b1edbc 380 #define _DAC_CAL_CH0OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */
AnnaBridge 171:3a7713b1edbc 381 #define DAC_CAL_CH0OFFSET_DEFAULT (_DAC_CAL_CH0OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_CAL */
AnnaBridge 171:3a7713b1edbc 382 #define _DAC_CAL_CH1OFFSET_SHIFT 8 /**< Shift value for DAC_CH1OFFSET */
AnnaBridge 171:3a7713b1edbc 383 #define _DAC_CAL_CH1OFFSET_MASK 0x3F00UL /**< Bit mask for DAC_CH1OFFSET */
AnnaBridge 171:3a7713b1edbc 384 #define _DAC_CAL_CH1OFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_CAL */
AnnaBridge 171:3a7713b1edbc 385 #define DAC_CAL_CH1OFFSET_DEFAULT (_DAC_CAL_CH1OFFSET_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_CAL */
AnnaBridge 171:3a7713b1edbc 386 #define _DAC_CAL_GAIN_SHIFT 16 /**< Shift value for DAC_GAIN */
AnnaBridge 171:3a7713b1edbc 387 #define _DAC_CAL_GAIN_MASK 0x7F0000UL /**< Bit mask for DAC_GAIN */
AnnaBridge 171:3a7713b1edbc 388 #define _DAC_CAL_GAIN_DEFAULT 0x00000040UL /**< Mode DEFAULT for DAC_CAL */
AnnaBridge 171:3a7713b1edbc 389 #define DAC_CAL_GAIN_DEFAULT (_DAC_CAL_GAIN_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_CAL */
AnnaBridge 171:3a7713b1edbc 390
AnnaBridge 171:3a7713b1edbc 391 /* Bit fields for DAC BIASPROG */
AnnaBridge 171:3a7713b1edbc 392 #define _DAC_BIASPROG_RESETVALUE 0x00004747UL /**< Default value for DAC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 393 #define _DAC_BIASPROG_MASK 0x00004F4FUL /**< Mask for DAC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 394 #define _DAC_BIASPROG_BIASPROG_SHIFT 0 /**< Shift value for DAC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 395 #define _DAC_BIASPROG_BIASPROG_MASK 0xFUL /**< Bit mask for DAC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 396 #define _DAC_BIASPROG_BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for DAC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 397 #define DAC_BIASPROG_BIASPROG_DEFAULT (_DAC_BIASPROG_BIASPROG_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 398 #define DAC_BIASPROG_HALFBIAS (0x1UL << 6) /**< Half Bias Current */
AnnaBridge 171:3a7713b1edbc 399 #define _DAC_BIASPROG_HALFBIAS_SHIFT 6 /**< Shift value for DAC_HALFBIAS */
AnnaBridge 171:3a7713b1edbc 400 #define _DAC_BIASPROG_HALFBIAS_MASK 0x40UL /**< Bit mask for DAC_HALFBIAS */
AnnaBridge 171:3a7713b1edbc 401 #define _DAC_BIASPROG_HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 402 #define DAC_BIASPROG_HALFBIAS_DEFAULT (_DAC_BIASPROG_HALFBIAS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 403 #define _DAC_BIASPROG_OPA2BIASPROG_SHIFT 8 /**< Shift value for DAC_OPA2BIASPROG */
AnnaBridge 171:3a7713b1edbc 404 #define _DAC_BIASPROG_OPA2BIASPROG_MASK 0xF00UL /**< Bit mask for DAC_OPA2BIASPROG */
AnnaBridge 171:3a7713b1edbc 405 #define _DAC_BIASPROG_OPA2BIASPROG_DEFAULT 0x00000007UL /**< Mode DEFAULT for DAC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 406 #define DAC_BIASPROG_OPA2BIASPROG_DEFAULT (_DAC_BIASPROG_OPA2BIASPROG_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 407 #define DAC_BIASPROG_OPA2HALFBIAS (0x1UL << 14) /**< Half Bias Current */
AnnaBridge 171:3a7713b1edbc 408 #define _DAC_BIASPROG_OPA2HALFBIAS_SHIFT 14 /**< Shift value for DAC_OPA2HALFBIAS */
AnnaBridge 171:3a7713b1edbc 409 #define _DAC_BIASPROG_OPA2HALFBIAS_MASK 0x4000UL /**< Bit mask for DAC_OPA2HALFBIAS */
AnnaBridge 171:3a7713b1edbc 410 #define _DAC_BIASPROG_OPA2HALFBIAS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 411 #define DAC_BIASPROG_OPA2HALFBIAS_DEFAULT (_DAC_BIASPROG_OPA2HALFBIAS_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_BIASPROG */
AnnaBridge 171:3a7713b1edbc 412
AnnaBridge 171:3a7713b1edbc 413 /* Bit fields for DAC OPACTRL */
AnnaBridge 171:3a7713b1edbc 414 #define _DAC_OPACTRL_RESETVALUE 0x00000000UL /**< Default value for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 415 #define _DAC_OPACTRL_MASK 0x01C3F1C7UL /**< Mask for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 416 #define DAC_OPACTRL_OPA0EN (0x1UL << 0) /**< OPA0 Enable */
AnnaBridge 171:3a7713b1edbc 417 #define _DAC_OPACTRL_OPA0EN_SHIFT 0 /**< Shift value for DAC_OPA0EN */
AnnaBridge 171:3a7713b1edbc 418 #define _DAC_OPACTRL_OPA0EN_MASK 0x1UL /**< Bit mask for DAC_OPA0EN */
AnnaBridge 171:3a7713b1edbc 419 #define _DAC_OPACTRL_OPA0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 420 #define DAC_OPACTRL_OPA0EN_DEFAULT (_DAC_OPACTRL_OPA0EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 421 #define DAC_OPACTRL_OPA1EN (0x1UL << 1) /**< OPA1 Enable */
AnnaBridge 171:3a7713b1edbc 422 #define _DAC_OPACTRL_OPA1EN_SHIFT 1 /**< Shift value for DAC_OPA1EN */
AnnaBridge 171:3a7713b1edbc 423 #define _DAC_OPACTRL_OPA1EN_MASK 0x2UL /**< Bit mask for DAC_OPA1EN */
AnnaBridge 171:3a7713b1edbc 424 #define _DAC_OPACTRL_OPA1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 425 #define DAC_OPACTRL_OPA1EN_DEFAULT (_DAC_OPACTRL_OPA1EN_DEFAULT << 1) /**< Shifted mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 426 #define DAC_OPACTRL_OPA2EN (0x1UL << 2) /**< OPA2 Enable */
AnnaBridge 171:3a7713b1edbc 427 #define _DAC_OPACTRL_OPA2EN_SHIFT 2 /**< Shift value for DAC_OPA2EN */
AnnaBridge 171:3a7713b1edbc 428 #define _DAC_OPACTRL_OPA2EN_MASK 0x4UL /**< Bit mask for DAC_OPA2EN */
AnnaBridge 171:3a7713b1edbc 429 #define _DAC_OPACTRL_OPA2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 430 #define DAC_OPACTRL_OPA2EN_DEFAULT (_DAC_OPACTRL_OPA2EN_DEFAULT << 2) /**< Shifted mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 431 #define DAC_OPACTRL_OPA0HCMDIS (0x1UL << 6) /**< High Common Mode Disable. */
AnnaBridge 171:3a7713b1edbc 432 #define _DAC_OPACTRL_OPA0HCMDIS_SHIFT 6 /**< Shift value for DAC_OPA0HCMDIS */
AnnaBridge 171:3a7713b1edbc 433 #define _DAC_OPACTRL_OPA0HCMDIS_MASK 0x40UL /**< Bit mask for DAC_OPA0HCMDIS */
AnnaBridge 171:3a7713b1edbc 434 #define _DAC_OPACTRL_OPA0HCMDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 435 #define DAC_OPACTRL_OPA0HCMDIS_DEFAULT (_DAC_OPACTRL_OPA0HCMDIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 436 #define DAC_OPACTRL_OPA1HCMDIS (0x1UL << 7) /**< High Common Mode Disable. */
AnnaBridge 171:3a7713b1edbc 437 #define _DAC_OPACTRL_OPA1HCMDIS_SHIFT 7 /**< Shift value for DAC_OPA1HCMDIS */
AnnaBridge 171:3a7713b1edbc 438 #define _DAC_OPACTRL_OPA1HCMDIS_MASK 0x80UL /**< Bit mask for DAC_OPA1HCMDIS */
AnnaBridge 171:3a7713b1edbc 439 #define _DAC_OPACTRL_OPA1HCMDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 440 #define DAC_OPACTRL_OPA1HCMDIS_DEFAULT (_DAC_OPACTRL_OPA1HCMDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 441 #define DAC_OPACTRL_OPA2HCMDIS (0x1UL << 8) /**< High Common Mode Disable. */
AnnaBridge 171:3a7713b1edbc 442 #define _DAC_OPACTRL_OPA2HCMDIS_SHIFT 8 /**< Shift value for DAC_OPA2HCMDIS */
AnnaBridge 171:3a7713b1edbc 443 #define _DAC_OPACTRL_OPA2HCMDIS_MASK 0x100UL /**< Bit mask for DAC_OPA2HCMDIS */
AnnaBridge 171:3a7713b1edbc 444 #define _DAC_OPACTRL_OPA2HCMDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 445 #define DAC_OPACTRL_OPA2HCMDIS_DEFAULT (_DAC_OPACTRL_OPA2HCMDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 446 #define _DAC_OPACTRL_OPA0LPFDIS_SHIFT 12 /**< Shift value for DAC_OPA0LPFDIS */
AnnaBridge 171:3a7713b1edbc 447 #define _DAC_OPACTRL_OPA0LPFDIS_MASK 0x3000UL /**< Bit mask for DAC_OPA0LPFDIS */
AnnaBridge 171:3a7713b1edbc 448 #define _DAC_OPACTRL_OPA0LPFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 449 #define _DAC_OPACTRL_OPA0LPFDIS_PLPFDIS 0x00000001UL /**< Mode PLPFDIS for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 450 #define _DAC_OPACTRL_OPA0LPFDIS_NLPFDIS 0x00000002UL /**< Mode NLPFDIS for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 451 #define DAC_OPACTRL_OPA0LPFDIS_DEFAULT (_DAC_OPACTRL_OPA0LPFDIS_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 452 #define DAC_OPACTRL_OPA0LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA0LPFDIS_PLPFDIS << 12) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 453 #define DAC_OPACTRL_OPA0LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA0LPFDIS_NLPFDIS << 12) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 454 #define _DAC_OPACTRL_OPA1LPFDIS_SHIFT 14 /**< Shift value for DAC_OPA1LPFDIS */
AnnaBridge 171:3a7713b1edbc 455 #define _DAC_OPACTRL_OPA1LPFDIS_MASK 0xC000UL /**< Bit mask for DAC_OPA1LPFDIS */
AnnaBridge 171:3a7713b1edbc 456 #define _DAC_OPACTRL_OPA1LPFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 457 #define _DAC_OPACTRL_OPA1LPFDIS_PLPFDIS 0x00000001UL /**< Mode PLPFDIS for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 458 #define _DAC_OPACTRL_OPA1LPFDIS_NLPFDIS 0x00000002UL /**< Mode NLPFDIS for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 459 #define DAC_OPACTRL_OPA1LPFDIS_DEFAULT (_DAC_OPACTRL_OPA1LPFDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 460 #define DAC_OPACTRL_OPA1LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA1LPFDIS_PLPFDIS << 14) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 461 #define DAC_OPACTRL_OPA1LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA1LPFDIS_NLPFDIS << 14) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 462 #define _DAC_OPACTRL_OPA2LPFDIS_SHIFT 16 /**< Shift value for DAC_OPA2LPFDIS */
AnnaBridge 171:3a7713b1edbc 463 #define _DAC_OPACTRL_OPA2LPFDIS_MASK 0x30000UL /**< Bit mask for DAC_OPA2LPFDIS */
AnnaBridge 171:3a7713b1edbc 464 #define _DAC_OPACTRL_OPA2LPFDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 465 #define _DAC_OPACTRL_OPA2LPFDIS_PLPFDIS 0x00000001UL /**< Mode PLPFDIS for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 466 #define _DAC_OPACTRL_OPA2LPFDIS_NLPFDIS 0x00000002UL /**< Mode NLPFDIS for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 467 #define DAC_OPACTRL_OPA2LPFDIS_DEFAULT (_DAC_OPACTRL_OPA2LPFDIS_DEFAULT << 16) /**< Shifted mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 468 #define DAC_OPACTRL_OPA2LPFDIS_PLPFDIS (_DAC_OPACTRL_OPA2LPFDIS_PLPFDIS << 16) /**< Shifted mode PLPFDIS for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 469 #define DAC_OPACTRL_OPA2LPFDIS_NLPFDIS (_DAC_OPACTRL_OPA2LPFDIS_NLPFDIS << 16) /**< Shifted mode NLPFDIS for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 470 #define DAC_OPACTRL_OPA0SHORT (0x1UL << 22) /**< Short the non-inverting and inverting input. */
AnnaBridge 171:3a7713b1edbc 471 #define _DAC_OPACTRL_OPA0SHORT_SHIFT 22 /**< Shift value for DAC_OPA0SHORT */
AnnaBridge 171:3a7713b1edbc 472 #define _DAC_OPACTRL_OPA0SHORT_MASK 0x400000UL /**< Bit mask for DAC_OPA0SHORT */
AnnaBridge 171:3a7713b1edbc 473 #define _DAC_OPACTRL_OPA0SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 474 #define DAC_OPACTRL_OPA0SHORT_DEFAULT (_DAC_OPACTRL_OPA0SHORT_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 475 #define DAC_OPACTRL_OPA1SHORT (0x1UL << 23) /**< Short the non-inverting and inverting input. */
AnnaBridge 171:3a7713b1edbc 476 #define _DAC_OPACTRL_OPA1SHORT_SHIFT 23 /**< Shift value for DAC_OPA1SHORT */
AnnaBridge 171:3a7713b1edbc 477 #define _DAC_OPACTRL_OPA1SHORT_MASK 0x800000UL /**< Bit mask for DAC_OPA1SHORT */
AnnaBridge 171:3a7713b1edbc 478 #define _DAC_OPACTRL_OPA1SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 479 #define DAC_OPACTRL_OPA1SHORT_DEFAULT (_DAC_OPACTRL_OPA1SHORT_DEFAULT << 23) /**< Shifted mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 480 #define DAC_OPACTRL_OPA2SHORT (0x1UL << 24) /**< Short the non-inverting and inverting input. */
AnnaBridge 171:3a7713b1edbc 481 #define _DAC_OPACTRL_OPA2SHORT_SHIFT 24 /**< Shift value for DAC_OPA2SHORT */
AnnaBridge 171:3a7713b1edbc 482 #define _DAC_OPACTRL_OPA2SHORT_MASK 0x1000000UL /**< Bit mask for DAC_OPA2SHORT */
AnnaBridge 171:3a7713b1edbc 483 #define _DAC_OPACTRL_OPA2SHORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 484 #define DAC_OPACTRL_OPA2SHORT_DEFAULT (_DAC_OPACTRL_OPA2SHORT_DEFAULT << 24) /**< Shifted mode DEFAULT for DAC_OPACTRL */
AnnaBridge 171:3a7713b1edbc 485
AnnaBridge 171:3a7713b1edbc 486 /* Bit fields for DAC OPAOFFSET */
AnnaBridge 171:3a7713b1edbc 487 #define _DAC_OPAOFFSET_RESETVALUE 0x00000020UL /**< Default value for DAC_OPAOFFSET */
AnnaBridge 171:3a7713b1edbc 488 #define _DAC_OPAOFFSET_MASK 0x0000003FUL /**< Mask for DAC_OPAOFFSET */
AnnaBridge 171:3a7713b1edbc 489 #define _DAC_OPAOFFSET_OPA2OFFSET_SHIFT 0 /**< Shift value for DAC_OPA2OFFSET */
AnnaBridge 171:3a7713b1edbc 490 #define _DAC_OPAOFFSET_OPA2OFFSET_MASK 0x3FUL /**< Bit mask for DAC_OPA2OFFSET */
AnnaBridge 171:3a7713b1edbc 491 #define _DAC_OPAOFFSET_OPA2OFFSET_DEFAULT 0x00000020UL /**< Mode DEFAULT for DAC_OPAOFFSET */
AnnaBridge 171:3a7713b1edbc 492 #define DAC_OPAOFFSET_OPA2OFFSET_DEFAULT (_DAC_OPAOFFSET_OPA2OFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPAOFFSET */
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 /* Bit fields for DAC OPA0MUX */
AnnaBridge 171:3a7713b1edbc 495 #define _DAC_OPA0MUX_RESETVALUE 0x00400000UL /**< Default value for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 496 #define _DAC_OPA0MUX_MASK 0x74C7F737UL /**< Mask for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 497 #define _DAC_OPA0MUX_POSSEL_SHIFT 0 /**< Shift value for DAC_POSSEL */
AnnaBridge 171:3a7713b1edbc 498 #define _DAC_OPA0MUX_POSSEL_MASK 0x7UL /**< Bit mask for DAC_POSSEL */
AnnaBridge 171:3a7713b1edbc 499 #define _DAC_OPA0MUX_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 500 #define _DAC_OPA0MUX_POSSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 501 #define _DAC_OPA0MUX_POSSEL_DAC 0x00000001UL /**< Mode DAC for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 502 #define _DAC_OPA0MUX_POSSEL_POSPAD 0x00000002UL /**< Mode POSPAD for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 503 #define _DAC_OPA0MUX_POSSEL_OPA0INP 0x00000003UL /**< Mode OPA0INP for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 504 #define _DAC_OPA0MUX_POSSEL_OPATAP 0x00000004UL /**< Mode OPATAP for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 505 #define DAC_OPA0MUX_POSSEL_DEFAULT (_DAC_OPA0MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 506 #define DAC_OPA0MUX_POSSEL_DISABLE (_DAC_OPA0MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 507 #define DAC_OPA0MUX_POSSEL_DAC (_DAC_OPA0MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 508 #define DAC_OPA0MUX_POSSEL_POSPAD (_DAC_OPA0MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 509 #define DAC_OPA0MUX_POSSEL_OPA0INP (_DAC_OPA0MUX_POSSEL_OPA0INP << 0) /**< Shifted mode OPA0INP for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 510 #define DAC_OPA0MUX_POSSEL_OPATAP (_DAC_OPA0MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 511 #define _DAC_OPA0MUX_NEGSEL_SHIFT 4 /**< Shift value for DAC_NEGSEL */
AnnaBridge 171:3a7713b1edbc 512 #define _DAC_OPA0MUX_NEGSEL_MASK 0x30UL /**< Bit mask for DAC_NEGSEL */
AnnaBridge 171:3a7713b1edbc 513 #define _DAC_OPA0MUX_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 514 #define _DAC_OPA0MUX_NEGSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 515 #define _DAC_OPA0MUX_NEGSEL_UG 0x00000001UL /**< Mode UG for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 516 #define _DAC_OPA0MUX_NEGSEL_OPATAP 0x00000002UL /**< Mode OPATAP for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 517 #define _DAC_OPA0MUX_NEGSEL_NEGPAD 0x00000003UL /**< Mode NEGPAD for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 518 #define DAC_OPA0MUX_NEGSEL_DEFAULT (_DAC_OPA0MUX_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 519 #define DAC_OPA0MUX_NEGSEL_DISABLE (_DAC_OPA0MUX_NEGSEL_DISABLE << 4) /**< Shifted mode DISABLE for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 520 #define DAC_OPA0MUX_NEGSEL_UG (_DAC_OPA0MUX_NEGSEL_UG << 4) /**< Shifted mode UG for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 521 #define DAC_OPA0MUX_NEGSEL_OPATAP (_DAC_OPA0MUX_NEGSEL_OPATAP << 4) /**< Shifted mode OPATAP for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 522 #define DAC_OPA0MUX_NEGSEL_NEGPAD (_DAC_OPA0MUX_NEGSEL_NEGPAD << 4) /**< Shifted mode NEGPAD for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 523 #define _DAC_OPA0MUX_RESINMUX_SHIFT 8 /**< Shift value for DAC_RESINMUX */
AnnaBridge 171:3a7713b1edbc 524 #define _DAC_OPA0MUX_RESINMUX_MASK 0x700UL /**< Bit mask for DAC_RESINMUX */
AnnaBridge 171:3a7713b1edbc 525 #define _DAC_OPA0MUX_RESINMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 526 #define _DAC_OPA0MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 527 #define _DAC_OPA0MUX_RESINMUX_OPA0INP 0x00000001UL /**< Mode OPA0INP for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 528 #define _DAC_OPA0MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 529 #define _DAC_OPA0MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 530 #define _DAC_OPA0MUX_RESINMUX_VSS 0x00000004UL /**< Mode VSS for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 531 #define DAC_OPA0MUX_RESINMUX_DEFAULT (_DAC_OPA0MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 532 #define DAC_OPA0MUX_RESINMUX_DISABLE (_DAC_OPA0MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 533 #define DAC_OPA0MUX_RESINMUX_OPA0INP (_DAC_OPA0MUX_RESINMUX_OPA0INP << 8) /**< Shifted mode OPA0INP for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 534 #define DAC_OPA0MUX_RESINMUX_NEGPAD (_DAC_OPA0MUX_RESINMUX_NEGPAD << 8) /**< Shifted mode NEGPAD for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 535 #define DAC_OPA0MUX_RESINMUX_POSPAD (_DAC_OPA0MUX_RESINMUX_POSPAD << 8) /**< Shifted mode POSPAD for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 536 #define DAC_OPA0MUX_RESINMUX_VSS (_DAC_OPA0MUX_RESINMUX_VSS << 8) /**< Shifted mode VSS for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 537 #define DAC_OPA0MUX_PPEN (0x1UL << 12) /**< OPA0 Positive Pad Input Enable */
AnnaBridge 171:3a7713b1edbc 538 #define _DAC_OPA0MUX_PPEN_SHIFT 12 /**< Shift value for DAC_PPEN */
AnnaBridge 171:3a7713b1edbc 539 #define _DAC_OPA0MUX_PPEN_MASK 0x1000UL /**< Bit mask for DAC_PPEN */
AnnaBridge 171:3a7713b1edbc 540 #define _DAC_OPA0MUX_PPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 541 #define DAC_OPA0MUX_PPEN_DEFAULT (_DAC_OPA0MUX_PPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 542 #define DAC_OPA0MUX_NPEN (0x1UL << 13) /**< OPA0 Negative Pad Input Enable */
AnnaBridge 171:3a7713b1edbc 543 #define _DAC_OPA0MUX_NPEN_SHIFT 13 /**< Shift value for DAC_NPEN */
AnnaBridge 171:3a7713b1edbc 544 #define _DAC_OPA0MUX_NPEN_MASK 0x2000UL /**< Bit mask for DAC_NPEN */
AnnaBridge 171:3a7713b1edbc 545 #define _DAC_OPA0MUX_NPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 546 #define DAC_OPA0MUX_NPEN_DEFAULT (_DAC_OPA0MUX_NPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 547 #define _DAC_OPA0MUX_OUTPEN_SHIFT 14 /**< Shift value for DAC_OUTPEN */
AnnaBridge 171:3a7713b1edbc 548 #define _DAC_OPA0MUX_OUTPEN_MASK 0x7C000UL /**< Bit mask for DAC_OUTPEN */
AnnaBridge 171:3a7713b1edbc 549 #define _DAC_OPA0MUX_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 550 #define _DAC_OPA0MUX_OUTPEN_OUT0 0x00000001UL /**< Mode OUT0 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 551 #define _DAC_OPA0MUX_OUTPEN_OUT1 0x00000002UL /**< Mode OUT1 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 552 #define _DAC_OPA0MUX_OUTPEN_OUT2 0x00000004UL /**< Mode OUT2 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 553 #define _DAC_OPA0MUX_OUTPEN_OUT3 0x00000008UL /**< Mode OUT3 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 554 #define _DAC_OPA0MUX_OUTPEN_OUT4 0x00000010UL /**< Mode OUT4 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 555 #define DAC_OPA0MUX_OUTPEN_DEFAULT (_DAC_OPA0MUX_OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 556 #define DAC_OPA0MUX_OUTPEN_OUT0 (_DAC_OPA0MUX_OUTPEN_OUT0 << 14) /**< Shifted mode OUT0 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 557 #define DAC_OPA0MUX_OUTPEN_OUT1 (_DAC_OPA0MUX_OUTPEN_OUT1 << 14) /**< Shifted mode OUT1 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 558 #define DAC_OPA0MUX_OUTPEN_OUT2 (_DAC_OPA0MUX_OUTPEN_OUT2 << 14) /**< Shifted mode OUT2 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 559 #define DAC_OPA0MUX_OUTPEN_OUT3 (_DAC_OPA0MUX_OUTPEN_OUT3 << 14) /**< Shifted mode OUT3 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 560 #define DAC_OPA0MUX_OUTPEN_OUT4 (_DAC_OPA0MUX_OUTPEN_OUT4 << 14) /**< Shifted mode OUT4 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 561 #define _DAC_OPA0MUX_OUTMODE_SHIFT 22 /**< Shift value for DAC_OUTMODE */
AnnaBridge 171:3a7713b1edbc 562 #define _DAC_OPA0MUX_OUTMODE_MASK 0xC00000UL /**< Bit mask for DAC_OUTMODE */
AnnaBridge 171:3a7713b1edbc 563 #define _DAC_OPA0MUX_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 564 #define _DAC_OPA0MUX_OUTMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 565 #define _DAC_OPA0MUX_OUTMODE_MAIN 0x00000001UL /**< Mode MAIN for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 566 #define _DAC_OPA0MUX_OUTMODE_ALT 0x00000002UL /**< Mode ALT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 567 #define _DAC_OPA0MUX_OUTMODE_ALL 0x00000003UL /**< Mode ALL for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 568 #define DAC_OPA0MUX_OUTMODE_DISABLE (_DAC_OPA0MUX_OUTMODE_DISABLE << 22) /**< Shifted mode DISABLE for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 569 #define DAC_OPA0MUX_OUTMODE_DEFAULT (_DAC_OPA0MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 570 #define DAC_OPA0MUX_OUTMODE_MAIN (_DAC_OPA0MUX_OUTMODE_MAIN << 22) /**< Shifted mode MAIN for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 571 #define DAC_OPA0MUX_OUTMODE_ALT (_DAC_OPA0MUX_OUTMODE_ALT << 22) /**< Shifted mode ALT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 572 #define DAC_OPA0MUX_OUTMODE_ALL (_DAC_OPA0MUX_OUTMODE_ALL << 22) /**< Shifted mode ALL for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 573 #define DAC_OPA0MUX_NEXTOUT (0x1UL << 26) /**< OPA0 Next Enable */
AnnaBridge 171:3a7713b1edbc 574 #define _DAC_OPA0MUX_NEXTOUT_SHIFT 26 /**< Shift value for DAC_NEXTOUT */
AnnaBridge 171:3a7713b1edbc 575 #define _DAC_OPA0MUX_NEXTOUT_MASK 0x4000000UL /**< Bit mask for DAC_NEXTOUT */
AnnaBridge 171:3a7713b1edbc 576 #define _DAC_OPA0MUX_NEXTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 577 #define DAC_OPA0MUX_NEXTOUT_DEFAULT (_DAC_OPA0MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 578 #define _DAC_OPA0MUX_RESSEL_SHIFT 28 /**< Shift value for DAC_RESSEL */
AnnaBridge 171:3a7713b1edbc 579 #define _DAC_OPA0MUX_RESSEL_MASK 0x70000000UL /**< Bit mask for DAC_RESSEL */
AnnaBridge 171:3a7713b1edbc 580 #define _DAC_OPA0MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 581 #define _DAC_OPA0MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 582 #define _DAC_OPA0MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 583 #define _DAC_OPA0MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 584 #define _DAC_OPA0MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 585 #define _DAC_OPA0MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 586 #define _DAC_OPA0MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 587 #define _DAC_OPA0MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 588 #define _DAC_OPA0MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 589 #define DAC_OPA0MUX_RESSEL_DEFAULT (_DAC_OPA0MUX_RESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 590 #define DAC_OPA0MUX_RESSEL_RES0 (_DAC_OPA0MUX_RESSEL_RES0 << 28) /**< Shifted mode RES0 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 591 #define DAC_OPA0MUX_RESSEL_RES1 (_DAC_OPA0MUX_RESSEL_RES1 << 28) /**< Shifted mode RES1 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 592 #define DAC_OPA0MUX_RESSEL_RES2 (_DAC_OPA0MUX_RESSEL_RES2 << 28) /**< Shifted mode RES2 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 593 #define DAC_OPA0MUX_RESSEL_RES3 (_DAC_OPA0MUX_RESSEL_RES3 << 28) /**< Shifted mode RES3 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 594 #define DAC_OPA0MUX_RESSEL_RES4 (_DAC_OPA0MUX_RESSEL_RES4 << 28) /**< Shifted mode RES4 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 595 #define DAC_OPA0MUX_RESSEL_RES5 (_DAC_OPA0MUX_RESSEL_RES5 << 28) /**< Shifted mode RES5 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 596 #define DAC_OPA0MUX_RESSEL_RES6 (_DAC_OPA0MUX_RESSEL_RES6 << 28) /**< Shifted mode RES6 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 597 #define DAC_OPA0MUX_RESSEL_RES7 (_DAC_OPA0MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA0MUX */
AnnaBridge 171:3a7713b1edbc 598
AnnaBridge 171:3a7713b1edbc 599 /* Bit fields for DAC OPA1MUX */
AnnaBridge 171:3a7713b1edbc 600 #define _DAC_OPA1MUX_RESETVALUE 0x00000000UL /**< Default value for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 601 #define _DAC_OPA1MUX_MASK 0x74C7F737UL /**< Mask for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 602 #define _DAC_OPA1MUX_POSSEL_SHIFT 0 /**< Shift value for DAC_POSSEL */
AnnaBridge 171:3a7713b1edbc 603 #define _DAC_OPA1MUX_POSSEL_MASK 0x7UL /**< Bit mask for DAC_POSSEL */
AnnaBridge 171:3a7713b1edbc 604 #define _DAC_OPA1MUX_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 605 #define _DAC_OPA1MUX_POSSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 606 #define _DAC_OPA1MUX_POSSEL_DAC 0x00000001UL /**< Mode DAC for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 607 #define _DAC_OPA1MUX_POSSEL_POSPAD 0x00000002UL /**< Mode POSPAD for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 608 #define _DAC_OPA1MUX_POSSEL_OPA0INP 0x00000003UL /**< Mode OPA0INP for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 609 #define _DAC_OPA1MUX_POSSEL_OPATAP 0x00000004UL /**< Mode OPATAP for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 610 #define DAC_OPA1MUX_POSSEL_DEFAULT (_DAC_OPA1MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 611 #define DAC_OPA1MUX_POSSEL_DISABLE (_DAC_OPA1MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 612 #define DAC_OPA1MUX_POSSEL_DAC (_DAC_OPA1MUX_POSSEL_DAC << 0) /**< Shifted mode DAC for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 613 #define DAC_OPA1MUX_POSSEL_POSPAD (_DAC_OPA1MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 614 #define DAC_OPA1MUX_POSSEL_OPA0INP (_DAC_OPA1MUX_POSSEL_OPA0INP << 0) /**< Shifted mode OPA0INP for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 615 #define DAC_OPA1MUX_POSSEL_OPATAP (_DAC_OPA1MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 616 #define _DAC_OPA1MUX_NEGSEL_SHIFT 4 /**< Shift value for DAC_NEGSEL */
AnnaBridge 171:3a7713b1edbc 617 #define _DAC_OPA1MUX_NEGSEL_MASK 0x30UL /**< Bit mask for DAC_NEGSEL */
AnnaBridge 171:3a7713b1edbc 618 #define _DAC_OPA1MUX_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 619 #define _DAC_OPA1MUX_NEGSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 620 #define _DAC_OPA1MUX_NEGSEL_UG 0x00000001UL /**< Mode UG for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 621 #define _DAC_OPA1MUX_NEGSEL_OPATAP 0x00000002UL /**< Mode OPATAP for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 622 #define _DAC_OPA1MUX_NEGSEL_NEGPAD 0x00000003UL /**< Mode NEGPAD for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 623 #define DAC_OPA1MUX_NEGSEL_DEFAULT (_DAC_OPA1MUX_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 624 #define DAC_OPA1MUX_NEGSEL_DISABLE (_DAC_OPA1MUX_NEGSEL_DISABLE << 4) /**< Shifted mode DISABLE for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 625 #define DAC_OPA1MUX_NEGSEL_UG (_DAC_OPA1MUX_NEGSEL_UG << 4) /**< Shifted mode UG for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 626 #define DAC_OPA1MUX_NEGSEL_OPATAP (_DAC_OPA1MUX_NEGSEL_OPATAP << 4) /**< Shifted mode OPATAP for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 627 #define DAC_OPA1MUX_NEGSEL_NEGPAD (_DAC_OPA1MUX_NEGSEL_NEGPAD << 4) /**< Shifted mode NEGPAD for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 628 #define _DAC_OPA1MUX_RESINMUX_SHIFT 8 /**< Shift value for DAC_RESINMUX */
AnnaBridge 171:3a7713b1edbc 629 #define _DAC_OPA1MUX_RESINMUX_MASK 0x700UL /**< Bit mask for DAC_RESINMUX */
AnnaBridge 171:3a7713b1edbc 630 #define _DAC_OPA1MUX_RESINMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 631 #define _DAC_OPA1MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 632 #define _DAC_OPA1MUX_RESINMUX_OPA0INP 0x00000001UL /**< Mode OPA0INP for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 633 #define _DAC_OPA1MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 634 #define _DAC_OPA1MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 635 #define _DAC_OPA1MUX_RESINMUX_VSS 0x00000004UL /**< Mode VSS for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 636 #define DAC_OPA1MUX_RESINMUX_DEFAULT (_DAC_OPA1MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 637 #define DAC_OPA1MUX_RESINMUX_DISABLE (_DAC_OPA1MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 638 #define DAC_OPA1MUX_RESINMUX_OPA0INP (_DAC_OPA1MUX_RESINMUX_OPA0INP << 8) /**< Shifted mode OPA0INP for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 639 #define DAC_OPA1MUX_RESINMUX_NEGPAD (_DAC_OPA1MUX_RESINMUX_NEGPAD << 8) /**< Shifted mode NEGPAD for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 640 #define DAC_OPA1MUX_RESINMUX_POSPAD (_DAC_OPA1MUX_RESINMUX_POSPAD << 8) /**< Shifted mode POSPAD for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 641 #define DAC_OPA1MUX_RESINMUX_VSS (_DAC_OPA1MUX_RESINMUX_VSS << 8) /**< Shifted mode VSS for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 642 #define DAC_OPA1MUX_PPEN (0x1UL << 12) /**< OPA1 Positive Pad Input Enable */
AnnaBridge 171:3a7713b1edbc 643 #define _DAC_OPA1MUX_PPEN_SHIFT 12 /**< Shift value for DAC_PPEN */
AnnaBridge 171:3a7713b1edbc 644 #define _DAC_OPA1MUX_PPEN_MASK 0x1000UL /**< Bit mask for DAC_PPEN */
AnnaBridge 171:3a7713b1edbc 645 #define _DAC_OPA1MUX_PPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 646 #define DAC_OPA1MUX_PPEN_DEFAULT (_DAC_OPA1MUX_PPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 647 #define DAC_OPA1MUX_NPEN (0x1UL << 13) /**< OPA1 Negative Pad Input Enable */
AnnaBridge 171:3a7713b1edbc 648 #define _DAC_OPA1MUX_NPEN_SHIFT 13 /**< Shift value for DAC_NPEN */
AnnaBridge 171:3a7713b1edbc 649 #define _DAC_OPA1MUX_NPEN_MASK 0x2000UL /**< Bit mask for DAC_NPEN */
AnnaBridge 171:3a7713b1edbc 650 #define _DAC_OPA1MUX_NPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 651 #define DAC_OPA1MUX_NPEN_DEFAULT (_DAC_OPA1MUX_NPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 652 #define _DAC_OPA1MUX_OUTPEN_SHIFT 14 /**< Shift value for DAC_OUTPEN */
AnnaBridge 171:3a7713b1edbc 653 #define _DAC_OPA1MUX_OUTPEN_MASK 0x7C000UL /**< Bit mask for DAC_OUTPEN */
AnnaBridge 171:3a7713b1edbc 654 #define _DAC_OPA1MUX_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 655 #define _DAC_OPA1MUX_OUTPEN_OUT0 0x00000001UL /**< Mode OUT0 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 656 #define _DAC_OPA1MUX_OUTPEN_OUT1 0x00000002UL /**< Mode OUT1 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 657 #define _DAC_OPA1MUX_OUTPEN_OUT2 0x00000004UL /**< Mode OUT2 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 658 #define _DAC_OPA1MUX_OUTPEN_OUT3 0x00000008UL /**< Mode OUT3 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 659 #define _DAC_OPA1MUX_OUTPEN_OUT4 0x00000010UL /**< Mode OUT4 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 660 #define DAC_OPA1MUX_OUTPEN_DEFAULT (_DAC_OPA1MUX_OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 661 #define DAC_OPA1MUX_OUTPEN_OUT0 (_DAC_OPA1MUX_OUTPEN_OUT0 << 14) /**< Shifted mode OUT0 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 662 #define DAC_OPA1MUX_OUTPEN_OUT1 (_DAC_OPA1MUX_OUTPEN_OUT1 << 14) /**< Shifted mode OUT1 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 663 #define DAC_OPA1MUX_OUTPEN_OUT2 (_DAC_OPA1MUX_OUTPEN_OUT2 << 14) /**< Shifted mode OUT2 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 664 #define DAC_OPA1MUX_OUTPEN_OUT3 (_DAC_OPA1MUX_OUTPEN_OUT3 << 14) /**< Shifted mode OUT3 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 665 #define DAC_OPA1MUX_OUTPEN_OUT4 (_DAC_OPA1MUX_OUTPEN_OUT4 << 14) /**< Shifted mode OUT4 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 666 #define _DAC_OPA1MUX_OUTMODE_SHIFT 22 /**< Shift value for DAC_OUTMODE */
AnnaBridge 171:3a7713b1edbc 667 #define _DAC_OPA1MUX_OUTMODE_MASK 0xC00000UL /**< Bit mask for DAC_OUTMODE */
AnnaBridge 171:3a7713b1edbc 668 #define _DAC_OPA1MUX_OUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 669 #define _DAC_OPA1MUX_OUTMODE_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 670 #define _DAC_OPA1MUX_OUTMODE_MAIN 0x00000001UL /**< Mode MAIN for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 671 #define _DAC_OPA1MUX_OUTMODE_ALT 0x00000002UL /**< Mode ALT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 672 #define _DAC_OPA1MUX_OUTMODE_ALL 0x00000003UL /**< Mode ALL for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 673 #define DAC_OPA1MUX_OUTMODE_DEFAULT (_DAC_OPA1MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 674 #define DAC_OPA1MUX_OUTMODE_DISABLE (_DAC_OPA1MUX_OUTMODE_DISABLE << 22) /**< Shifted mode DISABLE for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 675 #define DAC_OPA1MUX_OUTMODE_MAIN (_DAC_OPA1MUX_OUTMODE_MAIN << 22) /**< Shifted mode MAIN for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 676 #define DAC_OPA1MUX_OUTMODE_ALT (_DAC_OPA1MUX_OUTMODE_ALT << 22) /**< Shifted mode ALT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 677 #define DAC_OPA1MUX_OUTMODE_ALL (_DAC_OPA1MUX_OUTMODE_ALL << 22) /**< Shifted mode ALL for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 678 #define DAC_OPA1MUX_NEXTOUT (0x1UL << 26) /**< OPA1 Next Enable */
AnnaBridge 171:3a7713b1edbc 679 #define _DAC_OPA1MUX_NEXTOUT_SHIFT 26 /**< Shift value for DAC_NEXTOUT */
AnnaBridge 171:3a7713b1edbc 680 #define _DAC_OPA1MUX_NEXTOUT_MASK 0x4000000UL /**< Bit mask for DAC_NEXTOUT */
AnnaBridge 171:3a7713b1edbc 681 #define _DAC_OPA1MUX_NEXTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 682 #define DAC_OPA1MUX_NEXTOUT_DEFAULT (_DAC_OPA1MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 683 #define _DAC_OPA1MUX_RESSEL_SHIFT 28 /**< Shift value for DAC_RESSEL */
AnnaBridge 171:3a7713b1edbc 684 #define _DAC_OPA1MUX_RESSEL_MASK 0x70000000UL /**< Bit mask for DAC_RESSEL */
AnnaBridge 171:3a7713b1edbc 685 #define _DAC_OPA1MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 686 #define _DAC_OPA1MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 687 #define _DAC_OPA1MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 688 #define _DAC_OPA1MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 689 #define _DAC_OPA1MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 690 #define _DAC_OPA1MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 691 #define _DAC_OPA1MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 692 #define _DAC_OPA1MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 693 #define _DAC_OPA1MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 694 #define DAC_OPA1MUX_RESSEL_DEFAULT (_DAC_OPA1MUX_RESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 695 #define DAC_OPA1MUX_RESSEL_RES0 (_DAC_OPA1MUX_RESSEL_RES0 << 28) /**< Shifted mode RES0 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 696 #define DAC_OPA1MUX_RESSEL_RES1 (_DAC_OPA1MUX_RESSEL_RES1 << 28) /**< Shifted mode RES1 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 697 #define DAC_OPA1MUX_RESSEL_RES2 (_DAC_OPA1MUX_RESSEL_RES2 << 28) /**< Shifted mode RES2 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 698 #define DAC_OPA1MUX_RESSEL_RES3 (_DAC_OPA1MUX_RESSEL_RES3 << 28) /**< Shifted mode RES3 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 699 #define DAC_OPA1MUX_RESSEL_RES4 (_DAC_OPA1MUX_RESSEL_RES4 << 28) /**< Shifted mode RES4 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 700 #define DAC_OPA1MUX_RESSEL_RES5 (_DAC_OPA1MUX_RESSEL_RES5 << 28) /**< Shifted mode RES5 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 701 #define DAC_OPA1MUX_RESSEL_RES6 (_DAC_OPA1MUX_RESSEL_RES6 << 28) /**< Shifted mode RES6 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 702 #define DAC_OPA1MUX_RESSEL_RES7 (_DAC_OPA1MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA1MUX */
AnnaBridge 171:3a7713b1edbc 703
AnnaBridge 171:3a7713b1edbc 704 /* Bit fields for DAC OPA2MUX */
AnnaBridge 171:3a7713b1edbc 705 #define _DAC_OPA2MUX_RESETVALUE 0x00000000UL /**< Default value for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 706 #define _DAC_OPA2MUX_MASK 0x7440F737UL /**< Mask for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 707 #define _DAC_OPA2MUX_POSSEL_SHIFT 0 /**< Shift value for DAC_POSSEL */
AnnaBridge 171:3a7713b1edbc 708 #define _DAC_OPA2MUX_POSSEL_MASK 0x7UL /**< Bit mask for DAC_POSSEL */
AnnaBridge 171:3a7713b1edbc 709 #define _DAC_OPA2MUX_POSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 710 #define _DAC_OPA2MUX_POSSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 711 #define _DAC_OPA2MUX_POSSEL_POSPAD 0x00000002UL /**< Mode POSPAD for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 712 #define _DAC_OPA2MUX_POSSEL_OPA1INP 0x00000003UL /**< Mode OPA1INP for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 713 #define _DAC_OPA2MUX_POSSEL_OPATAP 0x00000004UL /**< Mode OPATAP for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 714 #define DAC_OPA2MUX_POSSEL_DEFAULT (_DAC_OPA2MUX_POSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 715 #define DAC_OPA2MUX_POSSEL_DISABLE (_DAC_OPA2MUX_POSSEL_DISABLE << 0) /**< Shifted mode DISABLE for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 716 #define DAC_OPA2MUX_POSSEL_POSPAD (_DAC_OPA2MUX_POSSEL_POSPAD << 0) /**< Shifted mode POSPAD for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 717 #define DAC_OPA2MUX_POSSEL_OPA1INP (_DAC_OPA2MUX_POSSEL_OPA1INP << 0) /**< Shifted mode OPA1INP for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 718 #define DAC_OPA2MUX_POSSEL_OPATAP (_DAC_OPA2MUX_POSSEL_OPATAP << 0) /**< Shifted mode OPATAP for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 719 #define _DAC_OPA2MUX_NEGSEL_SHIFT 4 /**< Shift value for DAC_NEGSEL */
AnnaBridge 171:3a7713b1edbc 720 #define _DAC_OPA2MUX_NEGSEL_MASK 0x30UL /**< Bit mask for DAC_NEGSEL */
AnnaBridge 171:3a7713b1edbc 721 #define _DAC_OPA2MUX_NEGSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 722 #define _DAC_OPA2MUX_NEGSEL_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 723 #define _DAC_OPA2MUX_NEGSEL_UG 0x00000001UL /**< Mode UG for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 724 #define _DAC_OPA2MUX_NEGSEL_OPATAP 0x00000002UL /**< Mode OPATAP for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 725 #define _DAC_OPA2MUX_NEGSEL_NEGPAD 0x00000003UL /**< Mode NEGPAD for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 726 #define DAC_OPA2MUX_NEGSEL_DEFAULT (_DAC_OPA2MUX_NEGSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 727 #define DAC_OPA2MUX_NEGSEL_DISABLE (_DAC_OPA2MUX_NEGSEL_DISABLE << 4) /**< Shifted mode DISABLE for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 728 #define DAC_OPA2MUX_NEGSEL_UG (_DAC_OPA2MUX_NEGSEL_UG << 4) /**< Shifted mode UG for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 729 #define DAC_OPA2MUX_NEGSEL_OPATAP (_DAC_OPA2MUX_NEGSEL_OPATAP << 4) /**< Shifted mode OPATAP for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 730 #define DAC_OPA2MUX_NEGSEL_NEGPAD (_DAC_OPA2MUX_NEGSEL_NEGPAD << 4) /**< Shifted mode NEGPAD for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 731 #define _DAC_OPA2MUX_RESINMUX_SHIFT 8 /**< Shift value for DAC_RESINMUX */
AnnaBridge 171:3a7713b1edbc 732 #define _DAC_OPA2MUX_RESINMUX_MASK 0x700UL /**< Bit mask for DAC_RESINMUX */
AnnaBridge 171:3a7713b1edbc 733 #define _DAC_OPA2MUX_RESINMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 734 #define _DAC_OPA2MUX_RESINMUX_DISABLE 0x00000000UL /**< Mode DISABLE for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 735 #define _DAC_OPA2MUX_RESINMUX_OPA1INP 0x00000001UL /**< Mode OPA1INP for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 736 #define _DAC_OPA2MUX_RESINMUX_NEGPAD 0x00000002UL /**< Mode NEGPAD for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 737 #define _DAC_OPA2MUX_RESINMUX_POSPAD 0x00000003UL /**< Mode POSPAD for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 738 #define _DAC_OPA2MUX_RESINMUX_VSS 0x00000004UL /**< Mode VSS for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 739 #define DAC_OPA2MUX_RESINMUX_DEFAULT (_DAC_OPA2MUX_RESINMUX_DEFAULT << 8) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 740 #define DAC_OPA2MUX_RESINMUX_DISABLE (_DAC_OPA2MUX_RESINMUX_DISABLE << 8) /**< Shifted mode DISABLE for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 741 #define DAC_OPA2MUX_RESINMUX_OPA1INP (_DAC_OPA2MUX_RESINMUX_OPA1INP << 8) /**< Shifted mode OPA1INP for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 742 #define DAC_OPA2MUX_RESINMUX_NEGPAD (_DAC_OPA2MUX_RESINMUX_NEGPAD << 8) /**< Shifted mode NEGPAD for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 743 #define DAC_OPA2MUX_RESINMUX_POSPAD (_DAC_OPA2MUX_RESINMUX_POSPAD << 8) /**< Shifted mode POSPAD for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 744 #define DAC_OPA2MUX_RESINMUX_VSS (_DAC_OPA2MUX_RESINMUX_VSS << 8) /**< Shifted mode VSS for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 745 #define DAC_OPA2MUX_PPEN (0x1UL << 12) /**< OPA2 Positive Pad Input Enable */
AnnaBridge 171:3a7713b1edbc 746 #define _DAC_OPA2MUX_PPEN_SHIFT 12 /**< Shift value for DAC_PPEN */
AnnaBridge 171:3a7713b1edbc 747 #define _DAC_OPA2MUX_PPEN_MASK 0x1000UL /**< Bit mask for DAC_PPEN */
AnnaBridge 171:3a7713b1edbc 748 #define _DAC_OPA2MUX_PPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 749 #define DAC_OPA2MUX_PPEN_DEFAULT (_DAC_OPA2MUX_PPEN_DEFAULT << 12) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 750 #define DAC_OPA2MUX_NPEN (0x1UL << 13) /**< OPA2 Negative Pad Input Enable */
AnnaBridge 171:3a7713b1edbc 751 #define _DAC_OPA2MUX_NPEN_SHIFT 13 /**< Shift value for DAC_NPEN */
AnnaBridge 171:3a7713b1edbc 752 #define _DAC_OPA2MUX_NPEN_MASK 0x2000UL /**< Bit mask for DAC_NPEN */
AnnaBridge 171:3a7713b1edbc 753 #define _DAC_OPA2MUX_NPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 754 #define DAC_OPA2MUX_NPEN_DEFAULT (_DAC_OPA2MUX_NPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 755 #define _DAC_OPA2MUX_OUTPEN_SHIFT 14 /**< Shift value for DAC_OUTPEN */
AnnaBridge 171:3a7713b1edbc 756 #define _DAC_OPA2MUX_OUTPEN_MASK 0xC000UL /**< Bit mask for DAC_OUTPEN */
AnnaBridge 171:3a7713b1edbc 757 #define _DAC_OPA2MUX_OUTPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 758 #define _DAC_OPA2MUX_OUTPEN_OUT0 0x00000001UL /**< Mode OUT0 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 759 #define _DAC_OPA2MUX_OUTPEN_OUT1 0x00000002UL /**< Mode OUT1 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 760 #define DAC_OPA2MUX_OUTPEN_DEFAULT (_DAC_OPA2MUX_OUTPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 761 #define DAC_OPA2MUX_OUTPEN_OUT0 (_DAC_OPA2MUX_OUTPEN_OUT0 << 14) /**< Shifted mode OUT0 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 762 #define DAC_OPA2MUX_OUTPEN_OUT1 (_DAC_OPA2MUX_OUTPEN_OUT1 << 14) /**< Shifted mode OUT1 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 763 #define DAC_OPA2MUX_OUTMODE (0x1UL << 22) /**< Output Select */
AnnaBridge 171:3a7713b1edbc 764 #define _DAC_OPA2MUX_OUTMODE_SHIFT 22 /**< Shift value for DAC_OUTMODE */
AnnaBridge 171:3a7713b1edbc 765 #define _DAC_OPA2MUX_OUTMODE_MASK 0x400000UL /**< Bit mask for DAC_OUTMODE */
AnnaBridge 171:3a7713b1edbc 766 #define _DAC_OPA2MUX_OUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 767 #define DAC_OPA2MUX_OUTMODE_DEFAULT (_DAC_OPA2MUX_OUTMODE_DEFAULT << 22) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 768 #define DAC_OPA2MUX_NEXTOUT (0x1UL << 26) /**< OPA2 Next Enable */
AnnaBridge 171:3a7713b1edbc 769 #define _DAC_OPA2MUX_NEXTOUT_SHIFT 26 /**< Shift value for DAC_NEXTOUT */
AnnaBridge 171:3a7713b1edbc 770 #define _DAC_OPA2MUX_NEXTOUT_MASK 0x4000000UL /**< Bit mask for DAC_NEXTOUT */
AnnaBridge 171:3a7713b1edbc 771 #define _DAC_OPA2MUX_NEXTOUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 772 #define DAC_OPA2MUX_NEXTOUT_DEFAULT (_DAC_OPA2MUX_NEXTOUT_DEFAULT << 26) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 773 #define _DAC_OPA2MUX_RESSEL_SHIFT 28 /**< Shift value for DAC_RESSEL */
AnnaBridge 171:3a7713b1edbc 774 #define _DAC_OPA2MUX_RESSEL_MASK 0x70000000UL /**< Bit mask for DAC_RESSEL */
AnnaBridge 171:3a7713b1edbc 775 #define _DAC_OPA2MUX_RESSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 776 #define _DAC_OPA2MUX_RESSEL_RES0 0x00000000UL /**< Mode RES0 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 777 #define _DAC_OPA2MUX_RESSEL_RES1 0x00000001UL /**< Mode RES1 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 778 #define _DAC_OPA2MUX_RESSEL_RES2 0x00000002UL /**< Mode RES2 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 779 #define _DAC_OPA2MUX_RESSEL_RES3 0x00000003UL /**< Mode RES3 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 780 #define _DAC_OPA2MUX_RESSEL_RES4 0x00000004UL /**< Mode RES4 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 781 #define _DAC_OPA2MUX_RESSEL_RES5 0x00000005UL /**< Mode RES5 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 782 #define _DAC_OPA2MUX_RESSEL_RES6 0x00000006UL /**< Mode RES6 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 783 #define _DAC_OPA2MUX_RESSEL_RES7 0x00000007UL /**< Mode RES7 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 784 #define DAC_OPA2MUX_RESSEL_DEFAULT (_DAC_OPA2MUX_RESSEL_DEFAULT << 28) /**< Shifted mode DEFAULT for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 785 #define DAC_OPA2MUX_RESSEL_RES0 (_DAC_OPA2MUX_RESSEL_RES0 << 28) /**< Shifted mode RES0 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 786 #define DAC_OPA2MUX_RESSEL_RES1 (_DAC_OPA2MUX_RESSEL_RES1 << 28) /**< Shifted mode RES1 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 787 #define DAC_OPA2MUX_RESSEL_RES2 (_DAC_OPA2MUX_RESSEL_RES2 << 28) /**< Shifted mode RES2 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 788 #define DAC_OPA2MUX_RESSEL_RES3 (_DAC_OPA2MUX_RESSEL_RES3 << 28) /**< Shifted mode RES3 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 789 #define DAC_OPA2MUX_RESSEL_RES4 (_DAC_OPA2MUX_RESSEL_RES4 << 28) /**< Shifted mode RES4 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 790 #define DAC_OPA2MUX_RESSEL_RES5 (_DAC_OPA2MUX_RESSEL_RES5 << 28) /**< Shifted mode RES5 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 791 #define DAC_OPA2MUX_RESSEL_RES6 (_DAC_OPA2MUX_RESSEL_RES6 << 28) /**< Shifted mode RES6 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 792 #define DAC_OPA2MUX_RESSEL_RES7 (_DAC_OPA2MUX_RESSEL_RES7 << 28) /**< Shifted mode RES7 for DAC_OPA2MUX */
AnnaBridge 171:3a7713b1edbc 793
AnnaBridge 171:3a7713b1edbc 794 /** @} End of group EFM32LG_DAC */
AnnaBridge 171:3a7713b1edbc 795 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 796