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TARGET_EFM32HG_STK3400/TOOLCHAIN_GCC_ARM/efm32hg_prs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32hg_prs.h
AnnaBridge 171:3a7713b1edbc 3 * @brief EFM32HG_PRS register and bit field definitions
AnnaBridge 171:3a7713b1edbc 4 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 5 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * @section License
AnnaBridge 171:3a7713b1edbc 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 12 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 15 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 17 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 25 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 29 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 32 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 33 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 34 * @{
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 36 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 37 * @defgroup EFM32HG_PRS
AnnaBridge 171:3a7713b1edbc 38 * @{
AnnaBridge 171:3a7713b1edbc 39 * @brief EFM32HG_PRS Register Declaration
AnnaBridge 171:3a7713b1edbc 40 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 41 typedef struct
AnnaBridge 171:3a7713b1edbc 42 {
AnnaBridge 171:3a7713b1edbc 43 __IOM uint32_t SWPULSE; /**< Software Pulse Register */
AnnaBridge 171:3a7713b1edbc 44 __IOM uint32_t SWLEVEL; /**< Software Level Register */
AnnaBridge 171:3a7713b1edbc 45 __IOM uint32_t ROUTE; /**< I/O Routing Register */
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 uint32_t RESERVED0[1]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 48 PRS_CH_TypeDef CH[6]; /**< Channel registers */
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 uint32_t RESERVED1[6]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 51 __IOM uint32_t TRACECTRL; /**< MTB Trace Control Register */
AnnaBridge 171:3a7713b1edbc 52 } PRS_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 55 * @defgroup EFM32HG_PRS_BitFields
AnnaBridge 171:3a7713b1edbc 56 * @{
AnnaBridge 171:3a7713b1edbc 57 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 /* Bit fields for PRS SWPULSE */
AnnaBridge 171:3a7713b1edbc 60 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 61 #define _PRS_SWPULSE_MASK 0x0000003FUL /**< Mask for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 62 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 63 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */
AnnaBridge 171:3a7713b1edbc 64 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */
AnnaBridge 171:3a7713b1edbc 65 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 66 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 67 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 68 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */
AnnaBridge 171:3a7713b1edbc 69 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */
AnnaBridge 171:3a7713b1edbc 70 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 71 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 72 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 73 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */
AnnaBridge 171:3a7713b1edbc 74 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */
AnnaBridge 171:3a7713b1edbc 75 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 76 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 77 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 78 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */
AnnaBridge 171:3a7713b1edbc 79 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */
AnnaBridge 171:3a7713b1edbc 80 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 81 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 82 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 83 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */
AnnaBridge 171:3a7713b1edbc 84 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */
AnnaBridge 171:3a7713b1edbc 85 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 86 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 87 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 88 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */
AnnaBridge 171:3a7713b1edbc 89 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */
AnnaBridge 171:3a7713b1edbc 90 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 91 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 /* Bit fields for PRS SWLEVEL */
AnnaBridge 171:3a7713b1edbc 94 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 95 #define _PRS_SWLEVEL_MASK 0x0000003FUL /**< Mask for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 96 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */
AnnaBridge 171:3a7713b1edbc 97 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */
AnnaBridge 171:3a7713b1edbc 98 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */
AnnaBridge 171:3a7713b1edbc 99 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 100 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 101 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */
AnnaBridge 171:3a7713b1edbc 102 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */
AnnaBridge 171:3a7713b1edbc 103 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */
AnnaBridge 171:3a7713b1edbc 104 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 105 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 106 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */
AnnaBridge 171:3a7713b1edbc 107 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */
AnnaBridge 171:3a7713b1edbc 108 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */
AnnaBridge 171:3a7713b1edbc 109 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 110 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 111 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */
AnnaBridge 171:3a7713b1edbc 112 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */
AnnaBridge 171:3a7713b1edbc 113 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */
AnnaBridge 171:3a7713b1edbc 114 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 115 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 116 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */
AnnaBridge 171:3a7713b1edbc 117 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */
AnnaBridge 171:3a7713b1edbc 118 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */
AnnaBridge 171:3a7713b1edbc 119 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 120 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 121 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */
AnnaBridge 171:3a7713b1edbc 122 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */
AnnaBridge 171:3a7713b1edbc 123 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */
AnnaBridge 171:3a7713b1edbc 124 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 125 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 126
AnnaBridge 171:3a7713b1edbc 127 /* Bit fields for PRS ROUTE */
AnnaBridge 171:3a7713b1edbc 128 #define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 129 #define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 130 #define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */
AnnaBridge 171:3a7713b1edbc 131 #define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */
AnnaBridge 171:3a7713b1edbc 132 #define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */
AnnaBridge 171:3a7713b1edbc 133 #define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 134 #define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 135 #define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */
AnnaBridge 171:3a7713b1edbc 136 #define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */
AnnaBridge 171:3a7713b1edbc 137 #define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */
AnnaBridge 171:3a7713b1edbc 138 #define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 139 #define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 140 #define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */
AnnaBridge 171:3a7713b1edbc 141 #define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */
AnnaBridge 171:3a7713b1edbc 142 #define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */
AnnaBridge 171:3a7713b1edbc 143 #define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 144 #define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 145 #define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */
AnnaBridge 171:3a7713b1edbc 146 #define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */
AnnaBridge 171:3a7713b1edbc 147 #define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */
AnnaBridge 171:3a7713b1edbc 148 #define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 149 #define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 150 #define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */
AnnaBridge 171:3a7713b1edbc 151 #define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */
AnnaBridge 171:3a7713b1edbc 152 #define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 153 #define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 154 #define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 155 #define _PRS_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 156 #define _PRS_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 157 #define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 158 #define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 159 #define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 160 #define PRS_ROUTE_LOCATION_LOC2 (_PRS_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 161 #define PRS_ROUTE_LOCATION_LOC3 (_PRS_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 /* Bit fields for PRS CH_CTRL */
AnnaBridge 171:3a7713b1edbc 164 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 165 #define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 166 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
AnnaBridge 171:3a7713b1edbc 167 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
AnnaBridge 171:3a7713b1edbc 168 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 169 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 170 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 171 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 172 #define _PRS_CH_CTRL_SIGSEL_USART1IRTX 0x00000000UL /**< Mode USART1IRTX for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 173 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 174 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 175 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 176 #define _PRS_CH_CTRL_SIGSEL_USBSOF 0x00000000UL /**< Mode USBSOF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 177 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 178 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 179 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 180 #define _PRS_CH_CTRL_SIGSEL_PCNT0TCC 0x00000000UL /**< Mode PCNT0TCC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 181 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 182 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 183 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 184 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 185 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 186 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 187 #define _PRS_CH_CTRL_SIGSEL_USBSOFSR 0x00000001UL /**< Mode USBSOFSR for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 188 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 189 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 190 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 191 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 192 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 193 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 194 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 195 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 196 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 197 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 198 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 199 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 200 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 201 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 202 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 203 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 204 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 205 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 206 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 207 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 208 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 209 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 210 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 211 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 212 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 213 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 214 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 215 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 216 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 217 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 218 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 219 #define PRS_CH_CTRL_SIGSEL_USART1IRTX (_PRS_CH_CTRL_SIGSEL_USART1IRTX << 0) /**< Shifted mode USART1IRTX for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 220 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 221 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 222 #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 223 #define PRS_CH_CTRL_SIGSEL_USBSOF (_PRS_CH_CTRL_SIGSEL_USBSOF << 0) /**< Shifted mode USBSOF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 224 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 225 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 226 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 227 #define PRS_CH_CTRL_SIGSEL_PCNT0TCC (_PRS_CH_CTRL_SIGSEL_PCNT0TCC << 0) /**< Shifted mode PCNT0TCC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 228 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 229 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 230 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 231 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 232 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 233 #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 234 #define PRS_CH_CTRL_SIGSEL_USBSOFSR (_PRS_CH_CTRL_SIGSEL_USBSOFSR << 0) /**< Shifted mode USBSOFSR for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 235 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 236 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 237 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 238 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 239 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 240 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 241 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 242 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 243 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 244 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 245 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 246 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 247 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 248 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 249 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 250 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 251 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 252 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 253 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 254 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 255 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 256 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 257 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 258 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 259 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 260 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 261 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 262 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */
AnnaBridge 171:3a7713b1edbc 263 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */
AnnaBridge 171:3a7713b1edbc 264 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 265 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 266 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 267 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 268 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 269 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 270 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 271 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 272 #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 273 #define _PRS_CH_CTRL_SOURCESEL_USB 0x00000024UL /**< Mode USB for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 274 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 275 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 276 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 277 #define _PRS_CH_CTRL_SOURCESEL_PCNT0 0x00000036UL /**< Mode PCNT0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 278 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 279 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 280 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 281 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 282 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 283 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 284 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 285 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 286 #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 287 #define PRS_CH_CTRL_SOURCESEL_USB (_PRS_CH_CTRL_SOURCESEL_USB << 16) /**< Shifted mode USB for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 288 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 289 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 290 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 291 #define PRS_CH_CTRL_SOURCESEL_PCNT0 (_PRS_CH_CTRL_SOURCESEL_PCNT0 << 16) /**< Shifted mode PCNT0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 292 #define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */
AnnaBridge 171:3a7713b1edbc 293 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */
AnnaBridge 171:3a7713b1edbc 294 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 295 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 296 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 297 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 298 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 299 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 300 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 301 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 302 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 303 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 304 #define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */
AnnaBridge 171:3a7713b1edbc 305 #define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */
AnnaBridge 171:3a7713b1edbc 306 #define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */
AnnaBridge 171:3a7713b1edbc 307 #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 308 #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 /* Bit fields for PRS TRACECTRL */
AnnaBridge 171:3a7713b1edbc 311 #define _PRS_TRACECTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 312 #define _PRS_TRACECTRL_MASK 0x00000F0FUL /**< Mask for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 313 #define PRS_TRACECTRL_TSTARTEN (0x1UL << 0) /**< PRS TSTART Enable */
AnnaBridge 171:3a7713b1edbc 314 #define _PRS_TRACECTRL_TSTARTEN_SHIFT 0 /**< Shift value for PRS_TSTARTEN */
AnnaBridge 171:3a7713b1edbc 315 #define _PRS_TRACECTRL_TSTARTEN_MASK 0x1UL /**< Bit mask for PRS_TSTARTEN */
AnnaBridge 171:3a7713b1edbc 316 #define _PRS_TRACECTRL_TSTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 317 #define PRS_TRACECTRL_TSTARTEN_DEFAULT (_PRS_TRACECTRL_TSTARTEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 318 #define _PRS_TRACECTRL_TSTART_SHIFT 1 /**< Shift value for PRS_TSTART */
AnnaBridge 171:3a7713b1edbc 319 #define _PRS_TRACECTRL_TSTART_MASK 0xEUL /**< Bit mask for PRS_TSTART */
AnnaBridge 171:3a7713b1edbc 320 #define _PRS_TRACECTRL_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 321 #define _PRS_TRACECTRL_TSTART_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 322 #define _PRS_TRACECTRL_TSTART_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 323 #define _PRS_TRACECTRL_TSTART_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 324 #define _PRS_TRACECTRL_TSTART_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 325 #define _PRS_TRACECTRL_TSTART_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 326 #define _PRS_TRACECTRL_TSTART_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 327 #define PRS_TRACECTRL_TSTART_DEFAULT (_PRS_TRACECTRL_TSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 328 #define PRS_TRACECTRL_TSTART_PRSCH0 (_PRS_TRACECTRL_TSTART_PRSCH0 << 1) /**< Shifted mode PRSCH0 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 329 #define PRS_TRACECTRL_TSTART_PRSCH1 (_PRS_TRACECTRL_TSTART_PRSCH1 << 1) /**< Shifted mode PRSCH1 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 330 #define PRS_TRACECTRL_TSTART_PRSCH2 (_PRS_TRACECTRL_TSTART_PRSCH2 << 1) /**< Shifted mode PRSCH2 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 331 #define PRS_TRACECTRL_TSTART_PRSCH3 (_PRS_TRACECTRL_TSTART_PRSCH3 << 1) /**< Shifted mode PRSCH3 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 332 #define PRS_TRACECTRL_TSTART_PRSCH4 (_PRS_TRACECTRL_TSTART_PRSCH4 << 1) /**< Shifted mode PRSCH4 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 333 #define PRS_TRACECTRL_TSTART_PRSCH5 (_PRS_TRACECTRL_TSTART_PRSCH5 << 1) /**< Shifted mode PRSCH5 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 334 #define PRS_TRACECTRL_TSTOPEN (0x1UL << 8) /**< PRS TSTOP Enable */
AnnaBridge 171:3a7713b1edbc 335 #define _PRS_TRACECTRL_TSTOPEN_SHIFT 8 /**< Shift value for PRS_TSTOPEN */
AnnaBridge 171:3a7713b1edbc 336 #define _PRS_TRACECTRL_TSTOPEN_MASK 0x100UL /**< Bit mask for PRS_TSTOPEN */
AnnaBridge 171:3a7713b1edbc 337 #define _PRS_TRACECTRL_TSTOPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 338 #define PRS_TRACECTRL_TSTOPEN_DEFAULT (_PRS_TRACECTRL_TSTOPEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 339 #define _PRS_TRACECTRL_TSTOP_SHIFT 9 /**< Shift value for PRS_TSTOP */
AnnaBridge 171:3a7713b1edbc 340 #define _PRS_TRACECTRL_TSTOP_MASK 0xE00UL /**< Bit mask for PRS_TSTOP */
AnnaBridge 171:3a7713b1edbc 341 #define _PRS_TRACECTRL_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 342 #define _PRS_TRACECTRL_TSTOP_PRSCH0 0x00000000UL /**< Mode PRSCH0 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 343 #define _PRS_TRACECTRL_TSTOP_PRSCH1 0x00000001UL /**< Mode PRSCH1 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 344 #define _PRS_TRACECTRL_TSTOP_PRSCH2 0x00000002UL /**< Mode PRSCH2 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 345 #define _PRS_TRACECTRL_TSTOP_PRSCH3 0x00000003UL /**< Mode PRSCH3 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 346 #define _PRS_TRACECTRL_TSTOP_PRSCH4 0x00000004UL /**< Mode PRSCH4 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 347 #define _PRS_TRACECTRL_TSTOP_PRSCH5 0x00000005UL /**< Mode PRSCH5 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 348 #define PRS_TRACECTRL_TSTOP_DEFAULT (_PRS_TRACECTRL_TSTOP_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 349 #define PRS_TRACECTRL_TSTOP_PRSCH0 (_PRS_TRACECTRL_TSTOP_PRSCH0 << 9) /**< Shifted mode PRSCH0 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 350 #define PRS_TRACECTRL_TSTOP_PRSCH1 (_PRS_TRACECTRL_TSTOP_PRSCH1 << 9) /**< Shifted mode PRSCH1 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 351 #define PRS_TRACECTRL_TSTOP_PRSCH2 (_PRS_TRACECTRL_TSTOP_PRSCH2 << 9) /**< Shifted mode PRSCH2 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 352 #define PRS_TRACECTRL_TSTOP_PRSCH3 (_PRS_TRACECTRL_TSTOP_PRSCH3 << 9) /**< Shifted mode PRSCH3 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 353 #define PRS_TRACECTRL_TSTOP_PRSCH4 (_PRS_TRACECTRL_TSTOP_PRSCH4 << 9) /**< Shifted mode PRSCH4 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 354 #define PRS_TRACECTRL_TSTOP_PRSCH5 (_PRS_TRACECTRL_TSTOP_PRSCH5 << 9) /**< Shifted mode PRSCH5 for PRS_TRACECTRL */
AnnaBridge 171:3a7713b1edbc 355
AnnaBridge 171:3a7713b1edbc 356 /** @} End of group EFM32HG_PRS */
AnnaBridge 171:3a7713b1edbc 357 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 358