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TARGET_EFM32GG11_STK3701/TOOLCHAIN_IAR/efm32gg11b_qspi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 170:e95d10626187 1 /**************************************************************************//**
AnnaBridge 170:e95d10626187 2 * @file efm32gg11b_qspi.h
AnnaBridge 170:e95d10626187 3 * @brief EFM32GG11B_QSPI register and bit field definitions
AnnaBridge 170:e95d10626187 4 * @version 5.3.2
AnnaBridge 170:e95d10626187 5 ******************************************************************************
AnnaBridge 170:e95d10626187 6 * # License
AnnaBridge 170:e95d10626187 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 170:e95d10626187 8 ******************************************************************************
AnnaBridge 170:e95d10626187 9 *
AnnaBridge 170:e95d10626187 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 170:e95d10626187 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 170:e95d10626187 12 * freely, subject to the following restrictions:
AnnaBridge 170:e95d10626187 13 *
AnnaBridge 170:e95d10626187 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 170:e95d10626187 15 * claim that you wrote the original software.@n
AnnaBridge 170:e95d10626187 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 170:e95d10626187 17 * misrepresented as being the original software.@n
AnnaBridge 170:e95d10626187 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 170:e95d10626187 19 *
AnnaBridge 170:e95d10626187 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 170:e95d10626187 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 170:e95d10626187 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 170:e95d10626187 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 170:e95d10626187 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 170:e95d10626187 25 * infringement of any proprietary rights of a third party.
AnnaBridge 170:e95d10626187 26 *
AnnaBridge 170:e95d10626187 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 170:e95d10626187 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 170:e95d10626187 29 * any third party, arising from your use of this Software.
AnnaBridge 170:e95d10626187 30 *
AnnaBridge 170:e95d10626187 31 *****************************************************************************/
AnnaBridge 170:e95d10626187 32
AnnaBridge 170:e95d10626187 33 #if defined(__ICCARM__)
AnnaBridge 170:e95d10626187 34 #pragma system_include /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 35 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 170:e95d10626187 36 #pragma clang system_header /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 37 #endif
AnnaBridge 170:e95d10626187 38
AnnaBridge 170:e95d10626187 39 /**************************************************************************//**
AnnaBridge 170:e95d10626187 40 * @addtogroup Parts
AnnaBridge 170:e95d10626187 41 * @{
AnnaBridge 170:e95d10626187 42 ******************************************************************************/
AnnaBridge 170:e95d10626187 43 /**************************************************************************//**
AnnaBridge 170:e95d10626187 44 * @defgroup EFM32GG11B_QSPI QSPI
AnnaBridge 170:e95d10626187 45 * @{
AnnaBridge 170:e95d10626187 46 * @brief EFM32GG11B_QSPI Register Declaration
AnnaBridge 170:e95d10626187 47 *****************************************************************************/
AnnaBridge 170:e95d10626187 48 /** QSPI Register Declaration */
AnnaBridge 170:e95d10626187 49 typedef struct {
AnnaBridge 170:e95d10626187 50 __IOM uint32_t CONFIG; /**< Octal-SPI Configuration Register */
AnnaBridge 170:e95d10626187 51 __IOM uint32_t DEVINSTRRDCONFIG; /**< Device Read Instruction Configuration Register */
AnnaBridge 170:e95d10626187 52 __IOM uint32_t DEVINSTRWRCONFIG; /**< Device Write Instruction Configuration Register */
AnnaBridge 170:e95d10626187 53 __IOM uint32_t DEVDELAY; /**< Device Delay Register */
AnnaBridge 170:e95d10626187 54 __IOM uint32_t RDDATACAPTURE; /**< Read Data Capture Register */
AnnaBridge 170:e95d10626187 55 __IOM uint32_t DEVSIZECONFIG; /**< Device Size Configuration Register */
AnnaBridge 170:e95d10626187 56 __IOM uint32_t SRAMPARTITIONCFG; /**< SRAM Partition Configuration Register */
AnnaBridge 170:e95d10626187 57 __IOM uint32_t INDAHBADDRTRIGGER; /**< Indirect Address Trigger Register */
AnnaBridge 170:e95d10626187 58 uint32_t RESERVED0[1]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 59 __IOM uint32_t REMAPADDR; /**< Remap Address Register */
AnnaBridge 170:e95d10626187 60 __IOM uint32_t MODEBITCONFIG; /**< Mode Bit Configuration Register */
AnnaBridge 170:e95d10626187 61 __IM uint32_t SRAMFILL; /**< SRAM Fill Register */
AnnaBridge 170:e95d10626187 62 __IOM uint32_t TXTHRESH; /**< TX Threshold Register */
AnnaBridge 170:e95d10626187 63 __IOM uint32_t RXTHRESH; /**< RX Threshold Register */
AnnaBridge 170:e95d10626187 64 __IOM uint32_t WRITECOMPLETIONCTRL; /**< Write Completion Control Register */
AnnaBridge 170:e95d10626187 65 __IOM uint32_t NOOFPOLLSBEFEXP; /**< Polling Expiration Register */
AnnaBridge 170:e95d10626187 66 __IOM uint32_t IRQSTATUS; /**< Interrupt Status Register */
AnnaBridge 170:e95d10626187 67 __IOM uint32_t IRQMASK; /**< Interrupt Mask */
AnnaBridge 170:e95d10626187 68 uint32_t RESERVED1[2]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 69 __IOM uint32_t LOWERWRPROT; /**< Lower Write Protection Register */
AnnaBridge 170:e95d10626187 70 __IOM uint32_t UPPERWRPROT; /**< Upper Write Protection Register */
AnnaBridge 170:e95d10626187 71 __IOM uint32_t WRPROTCTRL; /**< Write Protection Control Register */
AnnaBridge 170:e95d10626187 72 uint32_t RESERVED2[1]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 73 __IOM uint32_t INDIRECTREADXFERCTRL; /**< Indirect Read Transfer Control Register */
AnnaBridge 170:e95d10626187 74 __IOM uint32_t INDIRECTREADXFERWATERMARK; /**< Indirect Read Transfer Watermark Register */
AnnaBridge 170:e95d10626187 75 __IOM uint32_t INDIRECTREADXFERSTART; /**< Indirect Read Transfer Start Address Register */
AnnaBridge 170:e95d10626187 76 __IOM uint32_t INDIRECTREADXFERNUMBYTES; /**< Indirect Read Transfer Number Bytes Register */
AnnaBridge 170:e95d10626187 77 __IOM uint32_t INDIRECTWRITEXFERCTRL; /**< Indirect Write Transfer Control Register */
AnnaBridge 170:e95d10626187 78 __IOM uint32_t INDIRECTWRITEXFERWATERMARK; /**< Indirect Write Transfer Watermark Register */
AnnaBridge 170:e95d10626187 79 __IOM uint32_t INDIRECTWRITEXFERSTART; /**< Indirect Write Transfer Start Address Register */
AnnaBridge 170:e95d10626187 80 __IOM uint32_t INDIRECTWRITEXFERNUMBYTES; /**< Indirect Write Transfer Number Bytes Register */
AnnaBridge 170:e95d10626187 81 __IOM uint32_t INDIRECTTRIGGERADDRRANGE; /**< Indirect Trigger Address Range Register */
AnnaBridge 170:e95d10626187 82 uint32_t RESERVED3[2]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 83 __IOM uint32_t FLASHCOMMANDCTRLMEM; /**< Flash Command Control Memory Register */
AnnaBridge 170:e95d10626187 84 __IOM uint32_t FLASHCMDCTRL; /**< Flash Command Control Register */
AnnaBridge 170:e95d10626187 85 __IOM uint32_t FLASHCMDADDR; /**< Flash Command Address Register */
AnnaBridge 170:e95d10626187 86 uint32_t RESERVED4[2]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 87 __IM uint32_t FLASHRDDATALOWER; /**< Flash Command Read Data Register (Lower) */
AnnaBridge 170:e95d10626187 88 __IM uint32_t FLASHRDDATAUPPER; /**< Flash Command Read Data Register (Upper) */
AnnaBridge 170:e95d10626187 89 __IOM uint32_t FLASHWRDATALOWER; /**< Flash Command Write Data Register (Lower) */
AnnaBridge 170:e95d10626187 90 __IOM uint32_t FLASHWRDATAUPPER; /**< Flash Command Write Data Register (Upper) */
AnnaBridge 170:e95d10626187 91 __IOM uint32_t POLLINGFLASHSTATUS; /**< Polling Flash Status Register */
AnnaBridge 170:e95d10626187 92 __IOM uint32_t PHYCONFIGURATION; /**< PHY Configuration Register */
AnnaBridge 170:e95d10626187 93 __IOM uint32_t PHYMASTERCONTROL; /**< PHY DLL Master Control Register */
AnnaBridge 170:e95d10626187 94 __IM uint32_t DLLOBSERVABLELOWER; /**< DLL Observable Register Lower */
AnnaBridge 170:e95d10626187 95 __IM uint32_t DLLOBSERVABLEUPPER; /**< DLL Observable Register Upper */
AnnaBridge 170:e95d10626187 96 uint32_t RESERVED5[7]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 97 __IOM uint32_t OPCODEEXTLOWER; /**< Opcode Extension Register (Lower) */
AnnaBridge 170:e95d10626187 98 __IOM uint32_t OPCODEEXTUPPER; /**< Opcode Extension Register (Upper) */
AnnaBridge 170:e95d10626187 99 uint32_t RESERVED6[5]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 100 __IM uint32_t MODULEID; /**< Module ID Register */
AnnaBridge 170:e95d10626187 101
AnnaBridge 170:e95d10626187 102 __IOM uint32_t CTRL; /**< Control Register */
AnnaBridge 170:e95d10626187 103 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
AnnaBridge 170:e95d10626187 104 __IOM uint32_t ROUTELOC0; /**< I/O Route Location Register 0 */
AnnaBridge 170:e95d10626187 105 } QSPI_TypeDef; /** @} */
AnnaBridge 170:e95d10626187 106
AnnaBridge 170:e95d10626187 107 /**************************************************************************//**
AnnaBridge 170:e95d10626187 108 * @addtogroup EFM32GG11B_QSPI
AnnaBridge 170:e95d10626187 109 * @{
AnnaBridge 170:e95d10626187 110 * @defgroup EFM32GG11B_QSPI_BitFields QSPI Bit Fields
AnnaBridge 170:e95d10626187 111 * @{
AnnaBridge 170:e95d10626187 112 *****************************************************************************/
AnnaBridge 170:e95d10626187 113
AnnaBridge 170:e95d10626187 114 /* Bit fields for QSPI CONFIG */
AnnaBridge 170:e95d10626187 115 #define _QSPI_CONFIG_RESETVALUE 0x80780081UL /**< Default value for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 116 #define _QSPI_CONFIG_MASK 0xE3FF4F8FUL /**< Mask for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 117 #define QSPI_CONFIG_ENBSPI (0x1UL << 0) /**< QSPI Enable */
AnnaBridge 170:e95d10626187 118 #define _QSPI_CONFIG_ENBSPI_SHIFT 0 /**< Shift value for QSPI_ENBSPI */
AnnaBridge 170:e95d10626187 119 #define _QSPI_CONFIG_ENBSPI_MASK 0x1UL /**< Bit mask for QSPI_ENBSPI */
AnnaBridge 170:e95d10626187 120 #define _QSPI_CONFIG_ENBSPI_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 121 #define QSPI_CONFIG_ENBSPI_DEFAULT (_QSPI_CONFIG_ENBSPI_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 122 #define QSPI_CONFIG_SELCLKPOL (0x1UL << 1) /**< Clock polarity, CPOL */
AnnaBridge 170:e95d10626187 123 #define _QSPI_CONFIG_SELCLKPOL_SHIFT 1 /**< Shift value for QSPI_SELCLKPOL */
AnnaBridge 170:e95d10626187 124 #define _QSPI_CONFIG_SELCLKPOL_MASK 0x2UL /**< Bit mask for QSPI_SELCLKPOL */
AnnaBridge 170:e95d10626187 125 #define _QSPI_CONFIG_SELCLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 126 #define QSPI_CONFIG_SELCLKPOL_DEFAULT (_QSPI_CONFIG_SELCLKPOL_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 127 #define QSPI_CONFIG_SELCLKPHASE (0x1UL << 2) /**< Clock Phase, CPHA */
AnnaBridge 170:e95d10626187 128 #define _QSPI_CONFIG_SELCLKPHASE_SHIFT 2 /**< Shift value for QSPI_SELCLKPHASE */
AnnaBridge 170:e95d10626187 129 #define _QSPI_CONFIG_SELCLKPHASE_MASK 0x4UL /**< Bit mask for QSPI_SELCLKPHASE */
AnnaBridge 170:e95d10626187 130 #define _QSPI_CONFIG_SELCLKPHASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 131 #define QSPI_CONFIG_SELCLKPHASE_DEFAULT (_QSPI_CONFIG_SELCLKPHASE_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 132 #define QSPI_CONFIG_PHYMODEENABLE (0x1UL << 3) /**< PHY mode enable */
AnnaBridge 170:e95d10626187 133 #define _QSPI_CONFIG_PHYMODEENABLE_SHIFT 3 /**< Shift value for QSPI_PHYMODEENABLE */
AnnaBridge 170:e95d10626187 134 #define _QSPI_CONFIG_PHYMODEENABLE_MASK 0x8UL /**< Bit mask for QSPI_PHYMODEENABLE */
AnnaBridge 170:e95d10626187 135 #define _QSPI_CONFIG_PHYMODEENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 136 #define QSPI_CONFIG_PHYMODEENABLE_DEFAULT (_QSPI_CONFIG_PHYMODEENABLE_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 137 #define QSPI_CONFIG_ENBDIRACCCTLR (0x1UL << 7) /**< Enable Direct Access Controller */
AnnaBridge 170:e95d10626187 138 #define _QSPI_CONFIG_ENBDIRACCCTLR_SHIFT 7 /**< Shift value for QSPI_ENBDIRACCCTLR */
AnnaBridge 170:e95d10626187 139 #define _QSPI_CONFIG_ENBDIRACCCTLR_MASK 0x80UL /**< Bit mask for QSPI_ENBDIRACCCTLR */
AnnaBridge 170:e95d10626187 140 #define _QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 141 #define QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT (_QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 142 #define QSPI_CONFIG_ENBLEGACYIPMODE (0x1UL << 8) /**< Legacy IP Mode Enable */
AnnaBridge 170:e95d10626187 143 #define _QSPI_CONFIG_ENBLEGACYIPMODE_SHIFT 8 /**< Shift value for QSPI_ENBLEGACYIPMODE */
AnnaBridge 170:e95d10626187 144 #define _QSPI_CONFIG_ENBLEGACYIPMODE_MASK 0x100UL /**< Bit mask for QSPI_ENBLEGACYIPMODE */
AnnaBridge 170:e95d10626187 145 #define _QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 146 #define QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT (_QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 147 #define QSPI_CONFIG_PERIPHSELDEC (0x1UL << 9) /**< Peripheral select decode */
AnnaBridge 170:e95d10626187 148 #define _QSPI_CONFIG_PERIPHSELDEC_SHIFT 9 /**< Shift value for QSPI_PERIPHSELDEC */
AnnaBridge 170:e95d10626187 149 #define _QSPI_CONFIG_PERIPHSELDEC_MASK 0x200UL /**< Bit mask for QSPI_PERIPHSELDEC */
AnnaBridge 170:e95d10626187 150 #define _QSPI_CONFIG_PERIPHSELDEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 151 #define QSPI_CONFIG_PERIPHSELDEC_DEFAULT (_QSPI_CONFIG_PERIPHSELDEC_DEFAULT << 9) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 152 #define _QSPI_CONFIG_PERIPHCSLINES_SHIFT 10 /**< Shift value for QSPI_PERIPHCSLINES */
AnnaBridge 170:e95d10626187 153 #define _QSPI_CONFIG_PERIPHCSLINES_MASK 0xC00UL /**< Bit mask for QSPI_PERIPHCSLINES */
AnnaBridge 170:e95d10626187 154 #define _QSPI_CONFIG_PERIPHCSLINES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 155 #define QSPI_CONFIG_PERIPHCSLINES_DEFAULT (_QSPI_CONFIG_PERIPHCSLINES_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 156 #define QSPI_CONFIG_WRPROTFLASH (0x1UL << 14) /**< Write Protect Flash Pin */
AnnaBridge 170:e95d10626187 157 #define _QSPI_CONFIG_WRPROTFLASH_SHIFT 14 /**< Shift value for QSPI_WRPROTFLASH */
AnnaBridge 170:e95d10626187 158 #define _QSPI_CONFIG_WRPROTFLASH_MASK 0x4000UL /**< Bit mask for QSPI_WRPROTFLASH */
AnnaBridge 170:e95d10626187 159 #define _QSPI_CONFIG_WRPROTFLASH_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 160 #define QSPI_CONFIG_WRPROTFLASH_DEFAULT (_QSPI_CONFIG_WRPROTFLASH_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 161 #define QSPI_CONFIG_ENBAHBADDRREMAP (0x1UL << 16) /**< Enable Address Remapping */
AnnaBridge 170:e95d10626187 162 #define _QSPI_CONFIG_ENBAHBADDRREMAP_SHIFT 16 /**< Shift value for QSPI_ENBAHBADDRREMAP */
AnnaBridge 170:e95d10626187 163 #define _QSPI_CONFIG_ENBAHBADDRREMAP_MASK 0x10000UL /**< Bit mask for QSPI_ENBAHBADDRREMAP */
AnnaBridge 170:e95d10626187 164 #define _QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 165 #define QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT (_QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 166 #define QSPI_CONFIG_ENTERXIPMODE (0x1UL << 17) /**< Enter XIP Mode on next READ */
AnnaBridge 170:e95d10626187 167 #define _QSPI_CONFIG_ENTERXIPMODE_SHIFT 17 /**< Shift value for QSPI_ENTERXIPMODE */
AnnaBridge 170:e95d10626187 168 #define _QSPI_CONFIG_ENTERXIPMODE_MASK 0x20000UL /**< Bit mask for QSPI_ENTERXIPMODE */
AnnaBridge 170:e95d10626187 169 #define _QSPI_CONFIG_ENTERXIPMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 170 #define QSPI_CONFIG_ENTERXIPMODE_DEFAULT (_QSPI_CONFIG_ENTERXIPMODE_DEFAULT << 17) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 171 #define QSPI_CONFIG_ENTERXIPMODEIMM (0x1UL << 18) /**< Enter XIP Mode immediately */
AnnaBridge 170:e95d10626187 172 #define _QSPI_CONFIG_ENTERXIPMODEIMM_SHIFT 18 /**< Shift value for QSPI_ENTERXIPMODEIMM */
AnnaBridge 170:e95d10626187 173 #define _QSPI_CONFIG_ENTERXIPMODEIMM_MASK 0x40000UL /**< Bit mask for QSPI_ENTERXIPMODEIMM */
AnnaBridge 170:e95d10626187 174 #define _QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 175 #define QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT (_QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT << 18) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 176 #define _QSPI_CONFIG_MSTRBAUDDIV_SHIFT 19 /**< Shift value for QSPI_MSTRBAUDDIV */
AnnaBridge 170:e95d10626187 177 #define _QSPI_CONFIG_MSTRBAUDDIV_MASK 0x780000UL /**< Bit mask for QSPI_MSTRBAUDDIV */
AnnaBridge 170:e95d10626187 178 #define _QSPI_CONFIG_MSTRBAUDDIV_DEFAULT 0x0000000FUL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 179 #define QSPI_CONFIG_MSTRBAUDDIV_DEFAULT (_QSPI_CONFIG_MSTRBAUDDIV_DEFAULT << 19) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 180 #define QSPI_CONFIG_ENABLEAHBDECODER (0x1UL << 23) /**< Enable Address Decoder */
AnnaBridge 170:e95d10626187 181 #define _QSPI_CONFIG_ENABLEAHBDECODER_SHIFT 23 /**< Shift value for QSPI_ENABLEAHBDECODER */
AnnaBridge 170:e95d10626187 182 #define _QSPI_CONFIG_ENABLEAHBDECODER_MASK 0x800000UL /**< Bit mask for QSPI_ENABLEAHBDECODER */
AnnaBridge 170:e95d10626187 183 #define _QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 184 #define QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT (_QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT << 23) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 185 #define QSPI_CONFIG_ENABLEDTRPROTOCOL (0x1UL << 24) /**< Enable DTR Protocol */
AnnaBridge 170:e95d10626187 186 #define _QSPI_CONFIG_ENABLEDTRPROTOCOL_SHIFT 24 /**< Shift value for QSPI_ENABLEDTRPROTOCOL */
AnnaBridge 170:e95d10626187 187 #define _QSPI_CONFIG_ENABLEDTRPROTOCOL_MASK 0x1000000UL /**< Bit mask for QSPI_ENABLEDTRPROTOCOL */
AnnaBridge 170:e95d10626187 188 #define _QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 189 #define QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT (_QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 190 #define QSPI_CONFIG_PIPELINEPHY (0x1UL << 25) /**< Pipeline PHY Mode enable */
AnnaBridge 170:e95d10626187 191 #define _QSPI_CONFIG_PIPELINEPHY_SHIFT 25 /**< Shift value for QSPI_PIPELINEPHY */
AnnaBridge 170:e95d10626187 192 #define _QSPI_CONFIG_PIPELINEPHY_MASK 0x2000000UL /**< Bit mask for QSPI_PIPELINEPHY */
AnnaBridge 170:e95d10626187 193 #define _QSPI_CONFIG_PIPELINEPHY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 194 #define QSPI_CONFIG_PIPELINEPHY_DEFAULT (_QSPI_CONFIG_PIPELINEPHY_DEFAULT << 25) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 195 #define QSPI_CONFIG_CRCENABLE (0x1UL << 29) /**< CRC enable bit */
AnnaBridge 170:e95d10626187 196 #define _QSPI_CONFIG_CRCENABLE_SHIFT 29 /**< Shift value for QSPI_CRCENABLE */
AnnaBridge 170:e95d10626187 197 #define _QSPI_CONFIG_CRCENABLE_MASK 0x20000000UL /**< Bit mask for QSPI_CRCENABLE */
AnnaBridge 170:e95d10626187 198 #define _QSPI_CONFIG_CRCENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 199 #define QSPI_CONFIG_CRCENABLE_DEFAULT (_QSPI_CONFIG_CRCENABLE_DEFAULT << 29) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 200 #define QSPI_CONFIG_DUALBYTEOPCODEEN (0x1UL << 30) /**< Dual-byte Opcode Mode enable bit */
AnnaBridge 170:e95d10626187 201 #define _QSPI_CONFIG_DUALBYTEOPCODEEN_SHIFT 30 /**< Shift value for QSPI_DUALBYTEOPCODEEN */
AnnaBridge 170:e95d10626187 202 #define _QSPI_CONFIG_DUALBYTEOPCODEEN_MASK 0x40000000UL /**< Bit mask for QSPI_DUALBYTEOPCODEEN */
AnnaBridge 170:e95d10626187 203 #define _QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 204 #define QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT (_QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT << 30) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 205 #define QSPI_CONFIG_IDLE (0x1UL << 31) /**< Serial interface and low level SPI pipeline is IDLE */
AnnaBridge 170:e95d10626187 206 #define _QSPI_CONFIG_IDLE_SHIFT 31 /**< Shift value for QSPI_IDLE */
AnnaBridge 170:e95d10626187 207 #define _QSPI_CONFIG_IDLE_MASK 0x80000000UL /**< Bit mask for QSPI_IDLE */
AnnaBridge 170:e95d10626187 208 #define _QSPI_CONFIG_IDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 209 #define QSPI_CONFIG_IDLE_DEFAULT (_QSPI_CONFIG_IDLE_DEFAULT << 31) /**< Shifted mode DEFAULT for QSPI_CONFIG */
AnnaBridge 170:e95d10626187 210
AnnaBridge 170:e95d10626187 211 /* Bit fields for QSPI DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 212 #define _QSPI_DEVINSTRRDCONFIG_RESETVALUE 0x00000003UL /**< Default value for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 213 #define _QSPI_DEVINSTRRDCONFIG_MASK 0x1F1337FFUL /**< Mask for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 214 #define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_SHIFT 0 /**< Shift value for QSPI_RDOPCODENONXIP */
AnnaBridge 170:e95d10626187 215 #define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_MASK 0xFFUL /**< Bit mask for QSPI_RDOPCODENONXIP */
AnnaBridge 170:e95d10626187 216 #define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT 0x00000003UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 217 #define QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT (_QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 218 #define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_SHIFT 8 /**< Shift value for QSPI_INSTRTYPE */
AnnaBridge 170:e95d10626187 219 #define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_MASK 0x300UL /**< Bit mask for QSPI_INSTRTYPE */
AnnaBridge 170:e95d10626187 220 #define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 221 #define QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT (_QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 222 #define QSPI_DEVINSTRRDCONFIG_DDREN (0x1UL << 10) /**< DDR Enable */
AnnaBridge 170:e95d10626187 223 #define _QSPI_DEVINSTRRDCONFIG_DDREN_SHIFT 10 /**< Shift value for QSPI_DDREN */
AnnaBridge 170:e95d10626187 224 #define _QSPI_DEVINSTRRDCONFIG_DDREN_MASK 0x400UL /**< Bit mask for QSPI_DDREN */
AnnaBridge 170:e95d10626187 225 #define _QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 226 #define QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT (_QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 227 #define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_SHIFT 12 /**< Shift value for QSPI_ADDRXFERTYPESTDMODE */
AnnaBridge 170:e95d10626187 228 #define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_MASK 0x3000UL /**< Bit mask for QSPI_ADDRXFERTYPESTDMODE */
AnnaBridge 170:e95d10626187 229 #define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 230 #define QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT (_QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 231 #define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_SHIFT 16 /**< Shift value for QSPI_DATAXFERTYPEEXTMODE */
AnnaBridge 170:e95d10626187 232 #define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_MASK 0x30000UL /**< Bit mask for QSPI_DATAXFERTYPEEXTMODE */
AnnaBridge 170:e95d10626187 233 #define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 234 #define QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT (_QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 235 #define QSPI_DEVINSTRRDCONFIG_MODEBITENABLE (0x1UL << 20) /**< Mode Bit Enable */
AnnaBridge 170:e95d10626187 236 #define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_SHIFT 20 /**< Shift value for QSPI_MODEBITENABLE */
AnnaBridge 170:e95d10626187 237 #define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_MASK 0x100000UL /**< Bit mask for QSPI_MODEBITENABLE */
AnnaBridge 170:e95d10626187 238 #define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 239 #define QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT (_QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT << 20) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 240 #define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_SHIFT 24 /**< Shift value for QSPI_DUMMYRDCLKCYCLES */
AnnaBridge 170:e95d10626187 241 #define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_MASK 0x1F000000UL /**< Bit mask for QSPI_DUMMYRDCLKCYCLES */
AnnaBridge 170:e95d10626187 242 #define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 243 #define QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT (_QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG */
AnnaBridge 170:e95d10626187 244
AnnaBridge 170:e95d10626187 245 /* Bit fields for QSPI DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 246 #define _QSPI_DEVINSTRWRCONFIG_RESETVALUE 0x00000002UL /**< Default value for QSPI_DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 247 #define _QSPI_DEVINSTRWRCONFIG_MASK 0x1F0331FFUL /**< Mask for QSPI_DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 248 #define _QSPI_DEVINSTRWRCONFIG_WROPCODE_SHIFT 0 /**< Shift value for QSPI_WROPCODE */
AnnaBridge 170:e95d10626187 249 #define _QSPI_DEVINSTRWRCONFIG_WROPCODE_MASK 0xFFUL /**< Bit mask for QSPI_WROPCODE */
AnnaBridge 170:e95d10626187 250 #define _QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT 0x00000002UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 251 #define QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT (_QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 252 #define QSPI_DEVINSTRWRCONFIG_WELDIS (0x1UL << 8) /**< WEL Disable */
AnnaBridge 170:e95d10626187 253 #define _QSPI_DEVINSTRWRCONFIG_WELDIS_SHIFT 8 /**< Shift value for QSPI_WELDIS */
AnnaBridge 170:e95d10626187 254 #define _QSPI_DEVINSTRWRCONFIG_WELDIS_MASK 0x100UL /**< Bit mask for QSPI_WELDIS */
AnnaBridge 170:e95d10626187 255 #define _QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 256 #define QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT (_QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 257 #define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_SHIFT 12 /**< Shift value for QSPI_ADDRXFERTYPESTDMODE */
AnnaBridge 170:e95d10626187 258 #define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_MASK 0x3000UL /**< Bit mask for QSPI_ADDRXFERTYPESTDMODE */
AnnaBridge 170:e95d10626187 259 #define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 260 #define QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT (_QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 261 #define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_SHIFT 16 /**< Shift value for QSPI_DATAXFERTYPEEXTMODE */
AnnaBridge 170:e95d10626187 262 #define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_MASK 0x30000UL /**< Bit mask for QSPI_DATAXFERTYPEEXTMODE */
AnnaBridge 170:e95d10626187 263 #define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 264 #define QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT (_QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 265 #define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_SHIFT 24 /**< Shift value for QSPI_DUMMYWRCLKCYCLES */
AnnaBridge 170:e95d10626187 266 #define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_MASK 0x1F000000UL /**< Bit mask for QSPI_DUMMYWRCLKCYCLES */
AnnaBridge 170:e95d10626187 267 #define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 268 #define QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT (_QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG */
AnnaBridge 170:e95d10626187 269
AnnaBridge 170:e95d10626187 270 /* Bit fields for QSPI DEVDELAY */
AnnaBridge 170:e95d10626187 271 #define _QSPI_DEVDELAY_RESETVALUE 0x00000000UL /**< Default value for QSPI_DEVDELAY */
AnnaBridge 170:e95d10626187 272 #define _QSPI_DEVDELAY_MASK 0xFFFFFFFFUL /**< Mask for QSPI_DEVDELAY */
AnnaBridge 170:e95d10626187 273 #define _QSPI_DEVDELAY_DINIT_SHIFT 0 /**< Shift value for QSPI_DINIT */
AnnaBridge 170:e95d10626187 274 #define _QSPI_DEVDELAY_DINIT_MASK 0xFFUL /**< Bit mask for QSPI_DINIT */
AnnaBridge 170:e95d10626187 275 #define _QSPI_DEVDELAY_DINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVDELAY */
AnnaBridge 170:e95d10626187 276 #define QSPI_DEVDELAY_DINIT_DEFAULT (_QSPI_DEVDELAY_DINIT_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DEVDELAY */
AnnaBridge 170:e95d10626187 277 #define _QSPI_DEVDELAY_DAFTER_SHIFT 8 /**< Shift value for QSPI_DAFTER */
AnnaBridge 170:e95d10626187 278 #define _QSPI_DEVDELAY_DAFTER_MASK 0xFF00UL /**< Bit mask for QSPI_DAFTER */
AnnaBridge 170:e95d10626187 279 #define _QSPI_DEVDELAY_DAFTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVDELAY */
AnnaBridge 170:e95d10626187 280 #define QSPI_DEVDELAY_DAFTER_DEFAULT (_QSPI_DEVDELAY_DAFTER_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_DEVDELAY */
AnnaBridge 170:e95d10626187 281 #define _QSPI_DEVDELAY_DBTWN_SHIFT 16 /**< Shift value for QSPI_DBTWN */
AnnaBridge 170:e95d10626187 282 #define _QSPI_DEVDELAY_DBTWN_MASK 0xFF0000UL /**< Bit mask for QSPI_DBTWN */
AnnaBridge 170:e95d10626187 283 #define _QSPI_DEVDELAY_DBTWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVDELAY */
AnnaBridge 170:e95d10626187 284 #define QSPI_DEVDELAY_DBTWN_DEFAULT (_QSPI_DEVDELAY_DBTWN_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DEVDELAY */
AnnaBridge 170:e95d10626187 285 #define _QSPI_DEVDELAY_DNSS_SHIFT 24 /**< Shift value for QSPI_DNSS */
AnnaBridge 170:e95d10626187 286 #define _QSPI_DEVDELAY_DNSS_MASK 0xFF000000UL /**< Bit mask for QSPI_DNSS */
AnnaBridge 170:e95d10626187 287 #define _QSPI_DEVDELAY_DNSS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVDELAY */
AnnaBridge 170:e95d10626187 288 #define QSPI_DEVDELAY_DNSS_DEFAULT (_QSPI_DEVDELAY_DNSS_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_DEVDELAY */
AnnaBridge 170:e95d10626187 289
AnnaBridge 170:e95d10626187 290 /* Bit fields for QSPI RDDATACAPTURE */
AnnaBridge 170:e95d10626187 291 #define _QSPI_RDDATACAPTURE_RESETVALUE 0x00000001UL /**< Default value for QSPI_RDDATACAPTURE */
AnnaBridge 170:e95d10626187 292 #define _QSPI_RDDATACAPTURE_MASK 0x000F011FUL /**< Mask for QSPI_RDDATACAPTURE */
AnnaBridge 170:e95d10626187 293 #define QSPI_RDDATACAPTURE_BYPASS (0x1UL << 0) /**< Bypass the adapted loopback clock circuit */
AnnaBridge 170:e95d10626187 294 #define _QSPI_RDDATACAPTURE_BYPASS_SHIFT 0 /**< Shift value for QSPI_BYPASS */
AnnaBridge 170:e95d10626187 295 #define _QSPI_RDDATACAPTURE_BYPASS_MASK 0x1UL /**< Bit mask for QSPI_BYPASS */
AnnaBridge 170:e95d10626187 296 #define _QSPI_RDDATACAPTURE_BYPASS_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_RDDATACAPTURE */
AnnaBridge 170:e95d10626187 297 #define QSPI_RDDATACAPTURE_BYPASS_DEFAULT (_QSPI_RDDATACAPTURE_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_RDDATACAPTURE */
AnnaBridge 170:e95d10626187 298 #define _QSPI_RDDATACAPTURE_DELAY_SHIFT 1 /**< Shift value for QSPI_DELAY */
AnnaBridge 170:e95d10626187 299 #define _QSPI_RDDATACAPTURE_DELAY_MASK 0x1EUL /**< Bit mask for QSPI_DELAY */
AnnaBridge 170:e95d10626187 300 #define _QSPI_RDDATACAPTURE_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_RDDATACAPTURE */
AnnaBridge 170:e95d10626187 301 #define QSPI_RDDATACAPTURE_DELAY_DEFAULT (_QSPI_RDDATACAPTURE_DELAY_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_RDDATACAPTURE */
AnnaBridge 170:e95d10626187 302 #define QSPI_RDDATACAPTURE_DQSENABLE (0x1UL << 8) /**< DQS enable bit */
AnnaBridge 170:e95d10626187 303 #define _QSPI_RDDATACAPTURE_DQSENABLE_SHIFT 8 /**< Shift value for QSPI_DQSENABLE */
AnnaBridge 170:e95d10626187 304 #define _QSPI_RDDATACAPTURE_DQSENABLE_MASK 0x100UL /**< Bit mask for QSPI_DQSENABLE */
AnnaBridge 170:e95d10626187 305 #define _QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_RDDATACAPTURE */
AnnaBridge 170:e95d10626187 306 #define QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT (_QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_RDDATACAPTURE */
AnnaBridge 170:e95d10626187 307 #define _QSPI_RDDATACAPTURE_DDRREADDELAY_SHIFT 16 /**< Shift value for QSPI_DDRREADDELAY */
AnnaBridge 170:e95d10626187 308 #define _QSPI_RDDATACAPTURE_DDRREADDELAY_MASK 0xF0000UL /**< Bit mask for QSPI_DDRREADDELAY */
AnnaBridge 170:e95d10626187 309 #define _QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_RDDATACAPTURE */
AnnaBridge 170:e95d10626187 310 #define QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT (_QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_RDDATACAPTURE */
AnnaBridge 170:e95d10626187 311
AnnaBridge 170:e95d10626187 312 /* Bit fields for QSPI DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 313 #define _QSPI_DEVSIZECONFIG_RESETVALUE 0x00101002UL /**< Default value for QSPI_DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 314 #define _QSPI_DEVSIZECONFIG_MASK 0x01FFFFFFUL /**< Mask for QSPI_DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 315 #define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_SHIFT 0 /**< Shift value for QSPI_NUMADDRBYTES */
AnnaBridge 170:e95d10626187 316 #define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_MASK 0xFUL /**< Bit mask for QSPI_NUMADDRBYTES */
AnnaBridge 170:e95d10626187 317 #define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT 0x00000002UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 318 #define QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT (_QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 319 #define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_SHIFT 4 /**< Shift value for QSPI_BYTESPERDEVICEPAGE */
AnnaBridge 170:e95d10626187 320 #define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_MASK 0xFFF0UL /**< Bit mask for QSPI_BYTESPERDEVICEPAGE */
AnnaBridge 170:e95d10626187 321 #define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT 0x00000100UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 322 #define QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT (_QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 323 #define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_SHIFT 16 /**< Shift value for QSPI_BYTESPERSUBSECTOR */
AnnaBridge 170:e95d10626187 324 #define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_MASK 0x1F0000UL /**< Bit mask for QSPI_BYTESPERSUBSECTOR */
AnnaBridge 170:e95d10626187 325 #define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT 0x00000010UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 326 #define QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT (_QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 327 #define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_SHIFT 21 /**< Shift value for QSPI_MEMSIZEONCS0 */
AnnaBridge 170:e95d10626187 328 #define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_MASK 0x600000UL /**< Bit mask for QSPI_MEMSIZEONCS0 */
AnnaBridge 170:e95d10626187 329 #define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 330 #define QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT (_QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT << 21) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 331 #define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_SHIFT 23 /**< Shift value for QSPI_MEMSIZEONCS1 */
AnnaBridge 170:e95d10626187 332 #define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_MASK 0x1800000UL /**< Bit mask for QSPI_MEMSIZEONCS1 */
AnnaBridge 170:e95d10626187 333 #define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 334 #define QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT (_QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT << 23) /**< Shifted mode DEFAULT for QSPI_DEVSIZECONFIG */
AnnaBridge 170:e95d10626187 335
AnnaBridge 170:e95d10626187 336 /* Bit fields for QSPI SRAMPARTITIONCFG */
AnnaBridge 170:e95d10626187 337 #define _QSPI_SRAMPARTITIONCFG_RESETVALUE 0x00000080UL /**< Default value for QSPI_SRAMPARTITIONCFG */
AnnaBridge 170:e95d10626187 338 #define _QSPI_SRAMPARTITIONCFG_MASK 0x000000FFUL /**< Mask for QSPI_SRAMPARTITIONCFG */
AnnaBridge 170:e95d10626187 339 #define _QSPI_SRAMPARTITIONCFG_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */
AnnaBridge 170:e95d10626187 340 #define _QSPI_SRAMPARTITIONCFG_ADDR_MASK 0xFFUL /**< Bit mask for QSPI_ADDR */
AnnaBridge 170:e95d10626187 341 #define _QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT 0x00000080UL /**< Mode DEFAULT for QSPI_SRAMPARTITIONCFG */
AnnaBridge 170:e95d10626187 342 #define QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT (_QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_SRAMPARTITIONCFG */
AnnaBridge 170:e95d10626187 343
AnnaBridge 170:e95d10626187 344 /* Bit fields for QSPI INDAHBADDRTRIGGER */
AnnaBridge 170:e95d10626187 345 #define _QSPI_INDAHBADDRTRIGGER_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDAHBADDRTRIGGER */
AnnaBridge 170:e95d10626187 346 #define _QSPI_INDAHBADDRTRIGGER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDAHBADDRTRIGGER */
AnnaBridge 170:e95d10626187 347 #define _QSPI_INDAHBADDRTRIGGER_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */
AnnaBridge 170:e95d10626187 348 #define _QSPI_INDAHBADDRTRIGGER_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_ADDR */
AnnaBridge 170:e95d10626187 349 #define _QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDAHBADDRTRIGGER */
AnnaBridge 170:e95d10626187 350 #define QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT (_QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDAHBADDRTRIGGER */
AnnaBridge 170:e95d10626187 351
AnnaBridge 170:e95d10626187 352 /* Bit fields for QSPI REMAPADDR */
AnnaBridge 170:e95d10626187 353 #define _QSPI_REMAPADDR_RESETVALUE 0x00000000UL /**< Default value for QSPI_REMAPADDR */
AnnaBridge 170:e95d10626187 354 #define _QSPI_REMAPADDR_MASK 0xFFFFFFFFUL /**< Mask for QSPI_REMAPADDR */
AnnaBridge 170:e95d10626187 355 #define _QSPI_REMAPADDR_VALUE_SHIFT 0 /**< Shift value for QSPI_VALUE */
AnnaBridge 170:e95d10626187 356 #define _QSPI_REMAPADDR_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_VALUE */
AnnaBridge 170:e95d10626187 357 #define _QSPI_REMAPADDR_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_REMAPADDR */
AnnaBridge 170:e95d10626187 358 #define QSPI_REMAPADDR_VALUE_DEFAULT (_QSPI_REMAPADDR_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_REMAPADDR */
AnnaBridge 170:e95d10626187 359
AnnaBridge 170:e95d10626187 360 /* Bit fields for QSPI MODEBITCONFIG */
AnnaBridge 170:e95d10626187 361 #define _QSPI_MODEBITCONFIG_RESETVALUE 0x00000200UL /**< Default value for QSPI_MODEBITCONFIG */
AnnaBridge 170:e95d10626187 362 #define _QSPI_MODEBITCONFIG_MASK 0xFFFF87FFUL /**< Mask for QSPI_MODEBITCONFIG */
AnnaBridge 170:e95d10626187 363 #define _QSPI_MODEBITCONFIG_MODE_SHIFT 0 /**< Shift value for QSPI_MODE */
AnnaBridge 170:e95d10626187 364 #define _QSPI_MODEBITCONFIG_MODE_MASK 0xFFUL /**< Bit mask for QSPI_MODE */
AnnaBridge 170:e95d10626187 365 #define _QSPI_MODEBITCONFIG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */
AnnaBridge 170:e95d10626187 366 #define QSPI_MODEBITCONFIG_MODE_DEFAULT (_QSPI_MODEBITCONFIG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */
AnnaBridge 170:e95d10626187 367 #define _QSPI_MODEBITCONFIG_CHUNKSIZE_SHIFT 8 /**< Shift value for QSPI_CHUNKSIZE */
AnnaBridge 170:e95d10626187 368 #define _QSPI_MODEBITCONFIG_CHUNKSIZE_MASK 0x700UL /**< Bit mask for QSPI_CHUNKSIZE */
AnnaBridge 170:e95d10626187 369 #define _QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT 0x00000002UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */
AnnaBridge 170:e95d10626187 370 #define QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT (_QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */
AnnaBridge 170:e95d10626187 371 #define QSPI_MODEBITCONFIG_CRCOUTENABLE (0x1UL << 15) /**< CRC# output enable bit */
AnnaBridge 170:e95d10626187 372 #define _QSPI_MODEBITCONFIG_CRCOUTENABLE_SHIFT 15 /**< Shift value for QSPI_CRCOUTENABLE */
AnnaBridge 170:e95d10626187 373 #define _QSPI_MODEBITCONFIG_CRCOUTENABLE_MASK 0x8000UL /**< Bit mask for QSPI_CRCOUTENABLE */
AnnaBridge 170:e95d10626187 374 #define _QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */
AnnaBridge 170:e95d10626187 375 #define QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT (_QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT << 15) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */
AnnaBridge 170:e95d10626187 376 #define _QSPI_MODEBITCONFIG_RXCRCDATAUP_SHIFT 16 /**< Shift value for QSPI_RXCRCDATAUP */
AnnaBridge 170:e95d10626187 377 #define _QSPI_MODEBITCONFIG_RXCRCDATAUP_MASK 0xFF0000UL /**< Bit mask for QSPI_RXCRCDATAUP */
AnnaBridge 170:e95d10626187 378 #define _QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */
AnnaBridge 170:e95d10626187 379 #define QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT (_QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */
AnnaBridge 170:e95d10626187 380 #define _QSPI_MODEBITCONFIG_RXCRCDATALOW_SHIFT 24 /**< Shift value for QSPI_RXCRCDATALOW */
AnnaBridge 170:e95d10626187 381 #define _QSPI_MODEBITCONFIG_RXCRCDATALOW_MASK 0xFF000000UL /**< Bit mask for QSPI_RXCRCDATALOW */
AnnaBridge 170:e95d10626187 382 #define _QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODEBITCONFIG */
AnnaBridge 170:e95d10626187 383 #define QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT (_QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_MODEBITCONFIG */
AnnaBridge 170:e95d10626187 384
AnnaBridge 170:e95d10626187 385 /* Bit fields for QSPI SRAMFILL */
AnnaBridge 170:e95d10626187 386 #define _QSPI_SRAMFILL_RESETVALUE 0x00000000UL /**< Default value for QSPI_SRAMFILL */
AnnaBridge 170:e95d10626187 387 #define _QSPI_SRAMFILL_MASK 0xFFFFFFFFUL /**< Mask for QSPI_SRAMFILL */
AnnaBridge 170:e95d10626187 388 #define _QSPI_SRAMFILL_SRAMFILLINDACREAD_SHIFT 0 /**< Shift value for QSPI_SRAMFILLINDACREAD */
AnnaBridge 170:e95d10626187 389 #define _QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK 0xFFFFUL /**< Bit mask for QSPI_SRAMFILLINDACREAD */
AnnaBridge 170:e95d10626187 390 #define _QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_SRAMFILL */
AnnaBridge 170:e95d10626187 391 #define QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT (_QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_SRAMFILL */
AnnaBridge 170:e95d10626187 392 #define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_SHIFT 16 /**< Shift value for QSPI_SRAMFILLINDACWRITE */
AnnaBridge 170:e95d10626187 393 #define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK 0xFFFF0000UL /**< Bit mask for QSPI_SRAMFILLINDACWRITE */
AnnaBridge 170:e95d10626187 394 #define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_SRAMFILL */
AnnaBridge 170:e95d10626187 395 #define QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT (_QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_SRAMFILL */
AnnaBridge 170:e95d10626187 396
AnnaBridge 170:e95d10626187 397 /* Bit fields for QSPI TXTHRESH */
AnnaBridge 170:e95d10626187 398 #define _QSPI_TXTHRESH_RESETVALUE 0x00000001UL /**< Default value for QSPI_TXTHRESH */
AnnaBridge 170:e95d10626187 399 #define _QSPI_TXTHRESH_MASK 0x0000001FUL /**< Mask for QSPI_TXTHRESH */
AnnaBridge 170:e95d10626187 400 #define _QSPI_TXTHRESH_LEVEL_SHIFT 0 /**< Shift value for QSPI_LEVEL */
AnnaBridge 170:e95d10626187 401 #define _QSPI_TXTHRESH_LEVEL_MASK 0x1FUL /**< Bit mask for QSPI_LEVEL */
AnnaBridge 170:e95d10626187 402 #define _QSPI_TXTHRESH_LEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_TXTHRESH */
AnnaBridge 170:e95d10626187 403 #define QSPI_TXTHRESH_LEVEL_DEFAULT (_QSPI_TXTHRESH_LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_TXTHRESH */
AnnaBridge 170:e95d10626187 404
AnnaBridge 170:e95d10626187 405 /* Bit fields for QSPI RXTHRESH */
AnnaBridge 170:e95d10626187 406 #define _QSPI_RXTHRESH_RESETVALUE 0x00000001UL /**< Default value for QSPI_RXTHRESH */
AnnaBridge 170:e95d10626187 407 #define _QSPI_RXTHRESH_MASK 0x0000001FUL /**< Mask for QSPI_RXTHRESH */
AnnaBridge 170:e95d10626187 408 #define _QSPI_RXTHRESH_LEVEL_SHIFT 0 /**< Shift value for QSPI_LEVEL */
AnnaBridge 170:e95d10626187 409 #define _QSPI_RXTHRESH_LEVEL_MASK 0x1FUL /**< Bit mask for QSPI_LEVEL */
AnnaBridge 170:e95d10626187 410 #define _QSPI_RXTHRESH_LEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_RXTHRESH */
AnnaBridge 170:e95d10626187 411 #define QSPI_RXTHRESH_LEVEL_DEFAULT (_QSPI_RXTHRESH_LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_RXTHRESH */
AnnaBridge 170:e95d10626187 412
AnnaBridge 170:e95d10626187 413 /* Bit fields for QSPI WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 414 #define _QSPI_WRITECOMPLETIONCTRL_RESETVALUE 0x00010005UL /**< Default value for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 415 #define _QSPI_WRITECOMPLETIONCTRL_MASK 0xFFFFE7FFUL /**< Mask for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 416 #define _QSPI_WRITECOMPLETIONCTRL_OPCODE_SHIFT 0 /**< Shift value for QSPI_OPCODE */
AnnaBridge 170:e95d10626187 417 #define _QSPI_WRITECOMPLETIONCTRL_OPCODE_MASK 0xFFUL /**< Bit mask for QSPI_OPCODE */
AnnaBridge 170:e95d10626187 418 #define _QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT 0x00000005UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 419 #define QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 420 #define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_SHIFT 8 /**< Shift value for QSPI_POLLINGBITINDEX */
AnnaBridge 170:e95d10626187 421 #define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_MASK 0x700UL /**< Bit mask for QSPI_POLLINGBITINDEX */
AnnaBridge 170:e95d10626187 422 #define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 423 #define QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 424 #define QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY (0x1UL << 13) /**< Polling Polarity */
AnnaBridge 170:e95d10626187 425 #define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_SHIFT 13 /**< Shift value for QSPI_POLLINGPOLARITY */
AnnaBridge 170:e95d10626187 426 #define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_MASK 0x2000UL /**< Bit mask for QSPI_POLLINGPOLARITY */
AnnaBridge 170:e95d10626187 427 #define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 428 #define QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT << 13) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 429 #define QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING (0x1UL << 14) /**< Disable Polling */
AnnaBridge 170:e95d10626187 430 #define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_SHIFT 14 /**< Shift value for QSPI_DISABLEPOLLING */
AnnaBridge 170:e95d10626187 431 #define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_MASK 0x4000UL /**< Bit mask for QSPI_DISABLEPOLLING */
AnnaBridge 170:e95d10626187 432 #define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 433 #define QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 434 #define QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP (0x1UL << 15) /**< Enable Polling Expiration */
AnnaBridge 170:e95d10626187 435 #define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_SHIFT 15 /**< Shift value for QSPI_ENABLEPOLLINGEXP */
AnnaBridge 170:e95d10626187 436 #define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_MASK 0x8000UL /**< Bit mask for QSPI_ENABLEPOLLINGEXP */
AnnaBridge 170:e95d10626187 437 #define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 438 #define QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT << 15) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 439 #define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_SHIFT 16 /**< Shift value for QSPI_POLLCOUNT */
AnnaBridge 170:e95d10626187 440 #define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_MASK 0xFF0000UL /**< Bit mask for QSPI_POLLCOUNT */
AnnaBridge 170:e95d10626187 441 #define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 442 #define QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 443 #define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_SHIFT 24 /**< Shift value for QSPI_POLLREPDELAY */
AnnaBridge 170:e95d10626187 444 #define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_MASK 0xFF000000UL /**< Bit mask for QSPI_POLLREPDELAY */
AnnaBridge 170:e95d10626187 445 #define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 446 #define QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT (_QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL */
AnnaBridge 170:e95d10626187 447
AnnaBridge 170:e95d10626187 448 /* Bit fields for QSPI NOOFPOLLSBEFEXP */
AnnaBridge 170:e95d10626187 449 #define _QSPI_NOOFPOLLSBEFEXP_RESETVALUE 0xFFFFFFFFUL /**< Default value for QSPI_NOOFPOLLSBEFEXP */
AnnaBridge 170:e95d10626187 450 #define _QSPI_NOOFPOLLSBEFEXP_MASK 0xFFFFFFFFUL /**< Mask for QSPI_NOOFPOLLSBEFEXP */
AnnaBridge 170:e95d10626187 451 #define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_SHIFT 0 /**< Shift value for QSPI_NOOFPOLLSBEFEXP */
AnnaBridge 170:e95d10626187 452 #define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_NOOFPOLLSBEFEXP */
AnnaBridge 170:e95d10626187 453 #define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for QSPI_NOOFPOLLSBEFEXP */
AnnaBridge 170:e95d10626187 454 #define QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT (_QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_NOOFPOLLSBEFEXP */
AnnaBridge 170:e95d10626187 455
AnnaBridge 170:e95d10626187 456 /* Bit fields for QSPI IRQSTATUS */
AnnaBridge 170:e95d10626187 457 #define _QSPI_IRQSTATUS_RESETVALUE 0x00000000UL /**< Default value for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 458 #define _QSPI_IRQSTATUS_MASK 0x00077FFFUL /**< Mask for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 459 #define QSPI_IRQSTATUS_MODEMFAIL (0x1UL << 0) /**< Mode M Failure */
AnnaBridge 170:e95d10626187 460 #define _QSPI_IRQSTATUS_MODEMFAIL_SHIFT 0 /**< Shift value for QSPI_MODEMFAIL */
AnnaBridge 170:e95d10626187 461 #define _QSPI_IRQSTATUS_MODEMFAIL_MASK 0x1UL /**< Bit mask for QSPI_MODEMFAIL */
AnnaBridge 170:e95d10626187 462 #define _QSPI_IRQSTATUS_MODEMFAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 463 #define QSPI_IRQSTATUS_MODEMFAIL_DEFAULT (_QSPI_IRQSTATUS_MODEMFAIL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 464 #define QSPI_IRQSTATUS_UNDERFLOWDET (0x1UL << 1) /**< Underflow Detected */
AnnaBridge 170:e95d10626187 465 #define _QSPI_IRQSTATUS_UNDERFLOWDET_SHIFT 1 /**< Shift value for QSPI_UNDERFLOWDET */
AnnaBridge 170:e95d10626187 466 #define _QSPI_IRQSTATUS_UNDERFLOWDET_MASK 0x2UL /**< Bit mask for QSPI_UNDERFLOWDET */
AnnaBridge 170:e95d10626187 467 #define _QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 468 #define QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT (_QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 469 #define QSPI_IRQSTATUS_INDIRECTOPDONE (0x1UL << 2) /**< Indirect Operation Complete */
AnnaBridge 170:e95d10626187 470 #define _QSPI_IRQSTATUS_INDIRECTOPDONE_SHIFT 2 /**< Shift value for QSPI_INDIRECTOPDONE */
AnnaBridge 170:e95d10626187 471 #define _QSPI_IRQSTATUS_INDIRECTOPDONE_MASK 0x4UL /**< Bit mask for QSPI_INDIRECTOPDONE */
AnnaBridge 170:e95d10626187 472 #define _QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 473 #define QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT (_QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 474 #define QSPI_IRQSTATUS_INDIRECTREADREJECT (0x1UL << 3) /**< Indirect operation was requested but could not be accepted. */
AnnaBridge 170:e95d10626187 475 #define _QSPI_IRQSTATUS_INDIRECTREADREJECT_SHIFT 3 /**< Shift value for QSPI_INDIRECTREADREJECT */
AnnaBridge 170:e95d10626187 476 #define _QSPI_IRQSTATUS_INDIRECTREADREJECT_MASK 0x8UL /**< Bit mask for QSPI_INDIRECTREADREJECT */
AnnaBridge 170:e95d10626187 477 #define _QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 478 #define QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT (_QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 479 #define QSPI_IRQSTATUS_PROTWRATTEMPT (0x1UL << 4) /**< Write to protected area was attempted and rejected. */
AnnaBridge 170:e95d10626187 480 #define _QSPI_IRQSTATUS_PROTWRATTEMPT_SHIFT 4 /**< Shift value for QSPI_PROTWRATTEMPT */
AnnaBridge 170:e95d10626187 481 #define _QSPI_IRQSTATUS_PROTWRATTEMPT_MASK 0x10UL /**< Bit mask for QSPI_PROTWRATTEMPT */
AnnaBridge 170:e95d10626187 482 #define _QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 483 #define QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT (_QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 484 #define QSPI_IRQSTATUS_ILLEGALACCESSDET (0x1UL << 5) /**< Illegal memory access has been detected. */
AnnaBridge 170:e95d10626187 485 #define _QSPI_IRQSTATUS_ILLEGALACCESSDET_SHIFT 5 /**< Shift value for QSPI_ILLEGALACCESSDET */
AnnaBridge 170:e95d10626187 486 #define _QSPI_IRQSTATUS_ILLEGALACCESSDET_MASK 0x20UL /**< Bit mask for QSPI_ILLEGALACCESSDET */
AnnaBridge 170:e95d10626187 487 #define _QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 488 #define QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT (_QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 489 #define QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH (0x1UL << 6) /**< Indirect Transfer Watermark Level Breached */
AnnaBridge 170:e95d10626187 490 #define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_SHIFT 6 /**< Shift value for QSPI_INDIRECTXFERLEVELBREACH */
AnnaBridge 170:e95d10626187 491 #define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_MASK 0x40UL /**< Bit mask for QSPI_INDIRECTXFERLEVELBREACH */
AnnaBridge 170:e95d10626187 492 #define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 493 #define QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT (_QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 494 #define QSPI_IRQSTATUS_RECVOVERFLOW (0x1UL << 7) /**< Receive Overflow */
AnnaBridge 170:e95d10626187 495 #define _QSPI_IRQSTATUS_RECVOVERFLOW_SHIFT 7 /**< Shift value for QSPI_RECVOVERFLOW */
AnnaBridge 170:e95d10626187 496 #define _QSPI_IRQSTATUS_RECVOVERFLOW_MASK 0x80UL /**< Bit mask for QSPI_RECVOVERFLOW */
AnnaBridge 170:e95d10626187 497 #define _QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 498 #define QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT (_QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 499 #define QSPI_IRQSTATUS_TXFIFONOTFULL (0x1UL << 8) /**< Small TX FIFO not full */
AnnaBridge 170:e95d10626187 500 #define _QSPI_IRQSTATUS_TXFIFONOTFULL_SHIFT 8 /**< Shift value for QSPI_TXFIFONOTFULL */
AnnaBridge 170:e95d10626187 501 #define _QSPI_IRQSTATUS_TXFIFONOTFULL_MASK 0x100UL /**< Bit mask for QSPI_TXFIFONOTFULL */
AnnaBridge 170:e95d10626187 502 #define _QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 503 #define QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT (_QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 504 #define QSPI_IRQSTATUS_TXFIFOFULL (0x1UL << 9) /**< Small TX FIFO full */
AnnaBridge 170:e95d10626187 505 #define _QSPI_IRQSTATUS_TXFIFOFULL_SHIFT 9 /**< Shift value for QSPI_TXFIFOFULL */
AnnaBridge 170:e95d10626187 506 #define _QSPI_IRQSTATUS_TXFIFOFULL_MASK 0x200UL /**< Bit mask for QSPI_TXFIFOFULL */
AnnaBridge 170:e95d10626187 507 #define _QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 508 #define QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT (_QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT << 9) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 509 #define QSPI_IRQSTATUS_RXFIFONOTEMPTY (0x1UL << 10) /**< Small RX FIFO not empty */
AnnaBridge 170:e95d10626187 510 #define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_SHIFT 10 /**< Shift value for QSPI_RXFIFONOTEMPTY */
AnnaBridge 170:e95d10626187 511 #define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_MASK 0x400UL /**< Bit mask for QSPI_RXFIFONOTEMPTY */
AnnaBridge 170:e95d10626187 512 #define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 513 #define QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT (_QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 514 #define QSPI_IRQSTATUS_RXFIFOFULL (0x1UL << 11) /**< Small RX FIFO full */
AnnaBridge 170:e95d10626187 515 #define _QSPI_IRQSTATUS_RXFIFOFULL_SHIFT 11 /**< Shift value for QSPI_RXFIFOFULL */
AnnaBridge 170:e95d10626187 516 #define _QSPI_IRQSTATUS_RXFIFOFULL_MASK 0x800UL /**< Bit mask for QSPI_RXFIFOFULL */
AnnaBridge 170:e95d10626187 517 #define _QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 518 #define QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT (_QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT << 11) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 519 #define QSPI_IRQSTATUS_INDRDSRAMFULL (0x1UL << 12) /**< Indirect Read Partition overflow */
AnnaBridge 170:e95d10626187 520 #define _QSPI_IRQSTATUS_INDRDSRAMFULL_SHIFT 12 /**< Shift value for QSPI_INDRDSRAMFULL */
AnnaBridge 170:e95d10626187 521 #define _QSPI_IRQSTATUS_INDRDSRAMFULL_MASK 0x1000UL /**< Bit mask for QSPI_INDRDSRAMFULL */
AnnaBridge 170:e95d10626187 522 #define _QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 523 #define QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT (_QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 524 #define QSPI_IRQSTATUS_POLLEXPINT (0x1UL << 13) /**< The maximum number of programmed polls cycles is expired */
AnnaBridge 170:e95d10626187 525 #define _QSPI_IRQSTATUS_POLLEXPINT_SHIFT 13 /**< Shift value for QSPI_POLLEXPINT */
AnnaBridge 170:e95d10626187 526 #define _QSPI_IRQSTATUS_POLLEXPINT_MASK 0x2000UL /**< Bit mask for QSPI_POLLEXPINT */
AnnaBridge 170:e95d10626187 527 #define _QSPI_IRQSTATUS_POLLEXPINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 528 #define QSPI_IRQSTATUS_POLLEXPINT_DEFAULT (_QSPI_IRQSTATUS_POLLEXPINT_DEFAULT << 13) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 529 #define QSPI_IRQSTATUS_STIGREQINT (0x1UL << 14) /**< The controller is ready for getting another STIG request. */
AnnaBridge 170:e95d10626187 530 #define _QSPI_IRQSTATUS_STIGREQINT_SHIFT 14 /**< Shift value for QSPI_STIGREQINT */
AnnaBridge 170:e95d10626187 531 #define _QSPI_IRQSTATUS_STIGREQINT_MASK 0x4000UL /**< Bit mask for QSPI_STIGREQINT */
AnnaBridge 170:e95d10626187 532 #define _QSPI_IRQSTATUS_STIGREQINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 533 #define QSPI_IRQSTATUS_STIGREQINT_DEFAULT (_QSPI_IRQSTATUS_STIGREQINT_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 534 #define QSPI_IRQSTATUS_RXCRCDATAERR (0x1UL << 16) /**< RX CRC Data Error */
AnnaBridge 170:e95d10626187 535 #define _QSPI_IRQSTATUS_RXCRCDATAERR_SHIFT 16 /**< Shift value for QSPI_RXCRCDATAERR */
AnnaBridge 170:e95d10626187 536 #define _QSPI_IRQSTATUS_RXCRCDATAERR_MASK 0x10000UL /**< Bit mask for QSPI_RXCRCDATAERR */
AnnaBridge 170:e95d10626187 537 #define _QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 538 #define QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT (_QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 539 #define QSPI_IRQSTATUS_RXCRCDATAVAL (0x1UL << 17) /**< RX CRC data valid */
AnnaBridge 170:e95d10626187 540 #define _QSPI_IRQSTATUS_RXCRCDATAVAL_SHIFT 17 /**< Shift value for QSPI_RXCRCDATAVAL */
AnnaBridge 170:e95d10626187 541 #define _QSPI_IRQSTATUS_RXCRCDATAVAL_MASK 0x20000UL /**< Bit mask for QSPI_RXCRCDATAVAL */
AnnaBridge 170:e95d10626187 542 #define _QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 543 #define QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT (_QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT << 17) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 544 #define QSPI_IRQSTATUS_TXCRCCHUNKBRK (0x1UL << 18) /**< TX CRC chunk was broken */
AnnaBridge 170:e95d10626187 545 #define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_SHIFT 18 /**< Shift value for QSPI_TXCRCCHUNKBRK */
AnnaBridge 170:e95d10626187 546 #define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_MASK 0x40000UL /**< Bit mask for QSPI_TXCRCCHUNKBRK */
AnnaBridge 170:e95d10626187 547 #define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 548 #define QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT (_QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT << 18) /**< Shifted mode DEFAULT for QSPI_IRQSTATUS */
AnnaBridge 170:e95d10626187 549
AnnaBridge 170:e95d10626187 550 /* Bit fields for QSPI IRQMASK */
AnnaBridge 170:e95d10626187 551 #define _QSPI_IRQMASK_RESETVALUE 0x00000000UL /**< Default value for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 552 #define _QSPI_IRQMASK_MASK 0x00077FFFUL /**< Mask for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 553 #define QSPI_IRQMASK_MODEMFAILMASK (0x1UL << 0) /**< Mode M Failure Mask */
AnnaBridge 170:e95d10626187 554 #define _QSPI_IRQMASK_MODEMFAILMASK_SHIFT 0 /**< Shift value for QSPI_MODEMFAILMASK */
AnnaBridge 170:e95d10626187 555 #define _QSPI_IRQMASK_MODEMFAILMASK_MASK 0x1UL /**< Bit mask for QSPI_MODEMFAILMASK */
AnnaBridge 170:e95d10626187 556 #define _QSPI_IRQMASK_MODEMFAILMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 557 #define QSPI_IRQMASK_MODEMFAILMASK_DEFAULT (_QSPI_IRQMASK_MODEMFAILMASK_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 558 #define QSPI_IRQMASK_UNDERFLOWDETMASK (0x1UL << 1) /**< Underflow Detected Mask */
AnnaBridge 170:e95d10626187 559 #define _QSPI_IRQMASK_UNDERFLOWDETMASK_SHIFT 1 /**< Shift value for QSPI_UNDERFLOWDETMASK */
AnnaBridge 170:e95d10626187 560 #define _QSPI_IRQMASK_UNDERFLOWDETMASK_MASK 0x2UL /**< Bit mask for QSPI_UNDERFLOWDETMASK */
AnnaBridge 170:e95d10626187 561 #define _QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 562 #define QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT (_QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 563 #define QSPI_IRQMASK_INDIRECTOPDONEMASK (0x1UL << 2) /**< Indirect Complete Mask */
AnnaBridge 170:e95d10626187 564 #define _QSPI_IRQMASK_INDIRECTOPDONEMASK_SHIFT 2 /**< Shift value for QSPI_INDIRECTOPDONEMASK */
AnnaBridge 170:e95d10626187 565 #define _QSPI_IRQMASK_INDIRECTOPDONEMASK_MASK 0x4UL /**< Bit mask for QSPI_INDIRECTOPDONEMASK */
AnnaBridge 170:e95d10626187 566 #define _QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 567 #define QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT (_QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 568 #define QSPI_IRQMASK_INDIRECTREADREJECTMASK (0x1UL << 3) /**< Indirect Read Reject Mask */
AnnaBridge 170:e95d10626187 569 #define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_SHIFT 3 /**< Shift value for QSPI_INDIRECTREADREJECTMASK */
AnnaBridge 170:e95d10626187 570 #define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_MASK 0x8UL /**< Bit mask for QSPI_INDIRECTREADREJECTMASK */
AnnaBridge 170:e95d10626187 571 #define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 572 #define QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT (_QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 573 #define QSPI_IRQMASK_PROTWRATTEMPTMASK (0x1UL << 4) /**< Protected Area Write Attempt Mask */
AnnaBridge 170:e95d10626187 574 #define _QSPI_IRQMASK_PROTWRATTEMPTMASK_SHIFT 4 /**< Shift value for QSPI_PROTWRATTEMPTMASK */
AnnaBridge 170:e95d10626187 575 #define _QSPI_IRQMASK_PROTWRATTEMPTMASK_MASK 0x10UL /**< Bit mask for QSPI_PROTWRATTEMPTMASK */
AnnaBridge 170:e95d10626187 576 #define _QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 577 #define QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT (_QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 578 #define QSPI_IRQMASK_ILLEGALACCESSDETMASK (0x1UL << 5) /**< Illegal Access Detected Mask */
AnnaBridge 170:e95d10626187 579 #define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_SHIFT 5 /**< Shift value for QSPI_ILLEGALACCESSDETMASK */
AnnaBridge 170:e95d10626187 580 #define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_MASK 0x20UL /**< Bit mask for QSPI_ILLEGALACCESSDETMASK */
AnnaBridge 170:e95d10626187 581 #define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 582 #define QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT (_QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 583 #define QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK (0x1UL << 6) /**< Transfer Watermark Breach Mask */
AnnaBridge 170:e95d10626187 584 #define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_SHIFT 6 /**< Shift value for QSPI_INDIRECTXFERLEVELBREACHMASK */
AnnaBridge 170:e95d10626187 585 #define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_MASK 0x40UL /**< Bit mask for QSPI_INDIRECTXFERLEVELBREACHMASK */
AnnaBridge 170:e95d10626187 586 #define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 587 #define QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT (_QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 588 #define QSPI_IRQMASK_RECVOVERFLOWMASK (0x1UL << 7) /**< Receive Overflow Mask */
AnnaBridge 170:e95d10626187 589 #define _QSPI_IRQMASK_RECVOVERFLOWMASK_SHIFT 7 /**< Shift value for QSPI_RECVOVERFLOWMASK */
AnnaBridge 170:e95d10626187 590 #define _QSPI_IRQMASK_RECVOVERFLOWMASK_MASK 0x80UL /**< Bit mask for QSPI_RECVOVERFLOWMASK */
AnnaBridge 170:e95d10626187 591 #define _QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 592 #define QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT (_QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 593 #define QSPI_IRQMASK_TXFIFONOTFULLMASK (0x1UL << 8) /**< Small TX FIFO not full Mask */
AnnaBridge 170:e95d10626187 594 #define _QSPI_IRQMASK_TXFIFONOTFULLMASK_SHIFT 8 /**< Shift value for QSPI_TXFIFONOTFULLMASK */
AnnaBridge 170:e95d10626187 595 #define _QSPI_IRQMASK_TXFIFONOTFULLMASK_MASK 0x100UL /**< Bit mask for QSPI_TXFIFONOTFULLMASK */
AnnaBridge 170:e95d10626187 596 #define _QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 597 #define QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT (_QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 598 #define QSPI_IRQMASK_TXFIFOFULLMASK (0x1UL << 9) /**< Small TX FIFO full Mask */
AnnaBridge 170:e95d10626187 599 #define _QSPI_IRQMASK_TXFIFOFULLMASK_SHIFT 9 /**< Shift value for QSPI_TXFIFOFULLMASK */
AnnaBridge 170:e95d10626187 600 #define _QSPI_IRQMASK_TXFIFOFULLMASK_MASK 0x200UL /**< Bit mask for QSPI_TXFIFOFULLMASK */
AnnaBridge 170:e95d10626187 601 #define _QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 602 #define QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT (_QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT << 9) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 603 #define QSPI_IRQMASK_RXFIFONOTEMPTYMASK (0x1UL << 10) /**< Small RX FIFO not empty Mask */
AnnaBridge 170:e95d10626187 604 #define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_SHIFT 10 /**< Shift value for QSPI_RXFIFONOTEMPTYMASK */
AnnaBridge 170:e95d10626187 605 #define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_MASK 0x400UL /**< Bit mask for QSPI_RXFIFONOTEMPTYMASK */
AnnaBridge 170:e95d10626187 606 #define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 607 #define QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT (_QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 608 #define QSPI_IRQMASK_RXFIFOFULLMASK (0x1UL << 11) /**< Small RX FIFO full Mask */
AnnaBridge 170:e95d10626187 609 #define _QSPI_IRQMASK_RXFIFOFULLMASK_SHIFT 11 /**< Shift value for QSPI_RXFIFOFULLMASK */
AnnaBridge 170:e95d10626187 610 #define _QSPI_IRQMASK_RXFIFOFULLMASK_MASK 0x800UL /**< Bit mask for QSPI_RXFIFOFULLMASK */
AnnaBridge 170:e95d10626187 611 #define _QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 612 #define QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT (_QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT << 11) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 613 #define QSPI_IRQMASK_INDRDSRAMFULLMASK (0x1UL << 12) /**< Indirect Read Partition overflow mask */
AnnaBridge 170:e95d10626187 614 #define _QSPI_IRQMASK_INDRDSRAMFULLMASK_SHIFT 12 /**< Shift value for QSPI_INDRDSRAMFULLMASK */
AnnaBridge 170:e95d10626187 615 #define _QSPI_IRQMASK_INDRDSRAMFULLMASK_MASK 0x1000UL /**< Bit mask for QSPI_INDRDSRAMFULLMASK */
AnnaBridge 170:e95d10626187 616 #define _QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 617 #define QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT (_QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 618 #define QSPI_IRQMASK_POLLEXPINTMASK (0x1UL << 13) /**< Polling expiration detected Mask */
AnnaBridge 170:e95d10626187 619 #define _QSPI_IRQMASK_POLLEXPINTMASK_SHIFT 13 /**< Shift value for QSPI_POLLEXPINTMASK */
AnnaBridge 170:e95d10626187 620 #define _QSPI_IRQMASK_POLLEXPINTMASK_MASK 0x2000UL /**< Bit mask for QSPI_POLLEXPINTMASK */
AnnaBridge 170:e95d10626187 621 #define _QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 622 #define QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT (_QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT << 13) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 623 #define QSPI_IRQMASK_STIGREQMASK (0x1UL << 14) /**< STIG request completion Mask */
AnnaBridge 170:e95d10626187 624 #define _QSPI_IRQMASK_STIGREQMASK_SHIFT 14 /**< Shift value for QSPI_STIGREQMASK */
AnnaBridge 170:e95d10626187 625 #define _QSPI_IRQMASK_STIGREQMASK_MASK 0x4000UL /**< Bit mask for QSPI_STIGREQMASK */
AnnaBridge 170:e95d10626187 626 #define _QSPI_IRQMASK_STIGREQMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 627 #define QSPI_IRQMASK_STIGREQMASK_DEFAULT (_QSPI_IRQMASK_STIGREQMASK_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 628 #define QSPI_IRQMASK_RXCRCDATAERRMASK (0x1UL << 16) /**< RX CRC data error Mask */
AnnaBridge 170:e95d10626187 629 #define _QSPI_IRQMASK_RXCRCDATAERRMASK_SHIFT 16 /**< Shift value for QSPI_RXCRCDATAERRMASK */
AnnaBridge 170:e95d10626187 630 #define _QSPI_IRQMASK_RXCRCDATAERRMASK_MASK 0x10000UL /**< Bit mask for QSPI_RXCRCDATAERRMASK */
AnnaBridge 170:e95d10626187 631 #define _QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 632 #define QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT (_QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 633 #define QSPI_IRQMASK_RXCRCDATAVALMASK (0x1UL << 17) /**< RX CRC data valid Mask */
AnnaBridge 170:e95d10626187 634 #define _QSPI_IRQMASK_RXCRCDATAVALMASK_SHIFT 17 /**< Shift value for QSPI_RXCRCDATAVALMASK */
AnnaBridge 170:e95d10626187 635 #define _QSPI_IRQMASK_RXCRCDATAVALMASK_MASK 0x20000UL /**< Bit mask for QSPI_RXCRCDATAVALMASK */
AnnaBridge 170:e95d10626187 636 #define _QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 637 #define QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT (_QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT << 17) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 638 #define QSPI_IRQMASK_TXCRCCHUNKBRKMASK (0x1UL << 18) /**< TX CRC chunk was broken Mask */
AnnaBridge 170:e95d10626187 639 #define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_SHIFT 18 /**< Shift value for QSPI_TXCRCCHUNKBRKMASK */
AnnaBridge 170:e95d10626187 640 #define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_MASK 0x40000UL /**< Bit mask for QSPI_TXCRCCHUNKBRKMASK */
AnnaBridge 170:e95d10626187 641 #define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 642 #define QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT (_QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT << 18) /**< Shifted mode DEFAULT for QSPI_IRQMASK */
AnnaBridge 170:e95d10626187 643
AnnaBridge 170:e95d10626187 644 /* Bit fields for QSPI LOWERWRPROT */
AnnaBridge 170:e95d10626187 645 #define _QSPI_LOWERWRPROT_RESETVALUE 0x00000000UL /**< Default value for QSPI_LOWERWRPROT */
AnnaBridge 170:e95d10626187 646 #define _QSPI_LOWERWRPROT_MASK 0xFFFFFFFFUL /**< Mask for QSPI_LOWERWRPROT */
AnnaBridge 170:e95d10626187 647 #define _QSPI_LOWERWRPROT_SUBSECTOR_SHIFT 0 /**< Shift value for QSPI_SUBSECTOR */
AnnaBridge 170:e95d10626187 648 #define _QSPI_LOWERWRPROT_SUBSECTOR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_SUBSECTOR */
AnnaBridge 170:e95d10626187 649 #define _QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_LOWERWRPROT */
AnnaBridge 170:e95d10626187 650 #define QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT (_QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_LOWERWRPROT */
AnnaBridge 170:e95d10626187 651
AnnaBridge 170:e95d10626187 652 /* Bit fields for QSPI UPPERWRPROT */
AnnaBridge 170:e95d10626187 653 #define _QSPI_UPPERWRPROT_RESETVALUE 0x00000000UL /**< Default value for QSPI_UPPERWRPROT */
AnnaBridge 170:e95d10626187 654 #define _QSPI_UPPERWRPROT_MASK 0xFFFFFFFFUL /**< Mask for QSPI_UPPERWRPROT */
AnnaBridge 170:e95d10626187 655 #define _QSPI_UPPERWRPROT_SUBSECTOR_SHIFT 0 /**< Shift value for QSPI_SUBSECTOR */
AnnaBridge 170:e95d10626187 656 #define _QSPI_UPPERWRPROT_SUBSECTOR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_SUBSECTOR */
AnnaBridge 170:e95d10626187 657 #define _QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_UPPERWRPROT */
AnnaBridge 170:e95d10626187 658 #define QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT (_QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_UPPERWRPROT */
AnnaBridge 170:e95d10626187 659
AnnaBridge 170:e95d10626187 660 /* Bit fields for QSPI WRPROTCTRL */
AnnaBridge 170:e95d10626187 661 #define _QSPI_WRPROTCTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_WRPROTCTRL */
AnnaBridge 170:e95d10626187 662 #define _QSPI_WRPROTCTRL_MASK 0x00000003UL /**< Mask for QSPI_WRPROTCTRL */
AnnaBridge 170:e95d10626187 663 #define QSPI_WRPROTCTRL_INV (0x1UL << 0) /**< Write Protection Inversion Bit */
AnnaBridge 170:e95d10626187 664 #define _QSPI_WRPROTCTRL_INV_SHIFT 0 /**< Shift value for QSPI_INV */
AnnaBridge 170:e95d10626187 665 #define _QSPI_WRPROTCTRL_INV_MASK 0x1UL /**< Bit mask for QSPI_INV */
AnnaBridge 170:e95d10626187 666 #define _QSPI_WRPROTCTRL_INV_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRPROTCTRL */
AnnaBridge 170:e95d10626187 667 #define QSPI_WRPROTCTRL_INV_DEFAULT (_QSPI_WRPROTCTRL_INV_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_WRPROTCTRL */
AnnaBridge 170:e95d10626187 668 #define QSPI_WRPROTCTRL_ENB (0x1UL << 1) /**< Write Protection Enable Bit */
AnnaBridge 170:e95d10626187 669 #define _QSPI_WRPROTCTRL_ENB_SHIFT 1 /**< Shift value for QSPI_ENB */
AnnaBridge 170:e95d10626187 670 #define _QSPI_WRPROTCTRL_ENB_MASK 0x2UL /**< Bit mask for QSPI_ENB */
AnnaBridge 170:e95d10626187 671 #define _QSPI_WRPROTCTRL_ENB_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_WRPROTCTRL */
AnnaBridge 170:e95d10626187 672 #define QSPI_WRPROTCTRL_ENB_DEFAULT (_QSPI_WRPROTCTRL_ENB_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_WRPROTCTRL */
AnnaBridge 170:e95d10626187 673
AnnaBridge 170:e95d10626187 674 /* Bit fields for QSPI INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 675 #define _QSPI_INDIRECTREADXFERCTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 676 #define _QSPI_INDIRECTREADXFERCTRL_MASK 0x000000FFUL /**< Mask for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 677 #define QSPI_INDIRECTREADXFERCTRL_START (0x1UL << 0) /**< Start Indirect Read */
AnnaBridge 170:e95d10626187 678 #define _QSPI_INDIRECTREADXFERCTRL_START_SHIFT 0 /**< Shift value for QSPI_START */
AnnaBridge 170:e95d10626187 679 #define _QSPI_INDIRECTREADXFERCTRL_START_MASK 0x1UL /**< Bit mask for QSPI_START */
AnnaBridge 170:e95d10626187 680 #define _QSPI_INDIRECTREADXFERCTRL_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 681 #define QSPI_INDIRECTREADXFERCTRL_START_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_START_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 682 #define QSPI_INDIRECTREADXFERCTRL_CANCEL (0x1UL << 1) /**< Cancel Indirect Read */
AnnaBridge 170:e95d10626187 683 #define _QSPI_INDIRECTREADXFERCTRL_CANCEL_SHIFT 1 /**< Shift value for QSPI_CANCEL */
AnnaBridge 170:e95d10626187 684 #define _QSPI_INDIRECTREADXFERCTRL_CANCEL_MASK 0x2UL /**< Bit mask for QSPI_CANCEL */
AnnaBridge 170:e95d10626187 685 #define _QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 686 #define QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 687 #define QSPI_INDIRECTREADXFERCTRL_RDSTATUS (0x1UL << 2) /**< Indirect Read Status */
AnnaBridge 170:e95d10626187 688 #define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_SHIFT 2 /**< Shift value for QSPI_RDSTATUS */
AnnaBridge 170:e95d10626187 689 #define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_MASK 0x4UL /**< Bit mask for QSPI_RDSTATUS */
AnnaBridge 170:e95d10626187 690 #define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 691 #define QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 692 #define QSPI_INDIRECTREADXFERCTRL_SRAMFULL (0x1UL << 3) /**< SRAM Full */
AnnaBridge 170:e95d10626187 693 #define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_SHIFT 3 /**< Shift value for QSPI_SRAMFULL */
AnnaBridge 170:e95d10626187 694 #define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_MASK 0x8UL /**< Bit mask for QSPI_SRAMFULL */
AnnaBridge 170:e95d10626187 695 #define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 696 #define QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 697 #define QSPI_INDIRECTREADXFERCTRL_RDQUEUED (0x1UL << 4) /**< Two indirect read operations have been queued */
AnnaBridge 170:e95d10626187 698 #define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_SHIFT 4 /**< Shift value for QSPI_RDQUEUED */
AnnaBridge 170:e95d10626187 699 #define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_MASK 0x10UL /**< Bit mask for QSPI_RDQUEUED */
AnnaBridge 170:e95d10626187 700 #define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 701 #define QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 702 #define QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS (0x1UL << 5) /**< Indirect Completion Status */
AnnaBridge 170:e95d10626187 703 #define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_SHIFT 5 /**< Shift value for QSPI_INDOPSDONESTATUS */
AnnaBridge 170:e95d10626187 704 #define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_MASK 0x20UL /**< Bit mask for QSPI_INDOPSDONESTATUS */
AnnaBridge 170:e95d10626187 705 #define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 706 #define QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 707 #define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_SHIFT 6 /**< Shift value for QSPI_NUMINDOPSDONE */
AnnaBridge 170:e95d10626187 708 #define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_MASK 0xC0UL /**< Bit mask for QSPI_NUMINDOPSDONE */
AnnaBridge 170:e95d10626187 709 #define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 710 #define QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT (_QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL */
AnnaBridge 170:e95d10626187 711
AnnaBridge 170:e95d10626187 712 /* Bit fields for QSPI INDIRECTREADXFERWATERMARK */
AnnaBridge 170:e95d10626187 713 #define _QSPI_INDIRECTREADXFERWATERMARK_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTREADXFERWATERMARK */
AnnaBridge 170:e95d10626187 714 #define _QSPI_INDIRECTREADXFERWATERMARK_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTREADXFERWATERMARK */
AnnaBridge 170:e95d10626187 715 #define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_SHIFT 0 /**< Shift value for QSPI_LEVEL */
AnnaBridge 170:e95d10626187 716 #define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_LEVEL */
AnnaBridge 170:e95d10626187 717 #define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERWATERMARK */
AnnaBridge 170:e95d10626187 718 #define QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT (_QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERWATERMARK */
AnnaBridge 170:e95d10626187 719
AnnaBridge 170:e95d10626187 720 /* Bit fields for QSPI INDIRECTREADXFERSTART */
AnnaBridge 170:e95d10626187 721 #define _QSPI_INDIRECTREADXFERSTART_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTREADXFERSTART */
AnnaBridge 170:e95d10626187 722 #define _QSPI_INDIRECTREADXFERSTART_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTREADXFERSTART */
AnnaBridge 170:e95d10626187 723 #define _QSPI_INDIRECTREADXFERSTART_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */
AnnaBridge 170:e95d10626187 724 #define _QSPI_INDIRECTREADXFERSTART_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_ADDR */
AnnaBridge 170:e95d10626187 725 #define _QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERSTART */
AnnaBridge 170:e95d10626187 726 #define QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT (_QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERSTART */
AnnaBridge 170:e95d10626187 727
AnnaBridge 170:e95d10626187 728 /* Bit fields for QSPI INDIRECTREADXFERNUMBYTES */
AnnaBridge 170:e95d10626187 729 #define _QSPI_INDIRECTREADXFERNUMBYTES_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTREADXFERNUMBYTES */
AnnaBridge 170:e95d10626187 730 #define _QSPI_INDIRECTREADXFERNUMBYTES_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTREADXFERNUMBYTES */
AnnaBridge 170:e95d10626187 731 #define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_SHIFT 0 /**< Shift value for QSPI_VALUE */
AnnaBridge 170:e95d10626187 732 #define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_VALUE */
AnnaBridge 170:e95d10626187 733 #define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTREADXFERNUMBYTES */
AnnaBridge 170:e95d10626187 734 #define QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT (_QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTREADXFERNUMBYTES */
AnnaBridge 170:e95d10626187 735
AnnaBridge 170:e95d10626187 736 /* Bit fields for QSPI INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 737 #define _QSPI_INDIRECTWRITEXFERCTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 738 #define _QSPI_INDIRECTWRITEXFERCTRL_MASK 0x000000F7UL /**< Mask for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 739 #define QSPI_INDIRECTWRITEXFERCTRL_START (0x1UL << 0) /**< Start Indirect Write */
AnnaBridge 170:e95d10626187 740 #define _QSPI_INDIRECTWRITEXFERCTRL_START_SHIFT 0 /**< Shift value for QSPI_START */
AnnaBridge 170:e95d10626187 741 #define _QSPI_INDIRECTWRITEXFERCTRL_START_MASK 0x1UL /**< Bit mask for QSPI_START */
AnnaBridge 170:e95d10626187 742 #define _QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 743 #define QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 744 #define QSPI_INDIRECTWRITEXFERCTRL_CANCEL (0x1UL << 1) /**< Cancel Indirect Write */
AnnaBridge 170:e95d10626187 745 #define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_SHIFT 1 /**< Shift value for QSPI_CANCEL */
AnnaBridge 170:e95d10626187 746 #define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_MASK 0x2UL /**< Bit mask for QSPI_CANCEL */
AnnaBridge 170:e95d10626187 747 #define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 748 #define QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 749 #define QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS (0x1UL << 2) /**< Indirect Write Status */
AnnaBridge 170:e95d10626187 750 #define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_SHIFT 2 /**< Shift value for QSPI_WRSTATUS */
AnnaBridge 170:e95d10626187 751 #define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_MASK 0x4UL /**< Bit mask for QSPI_WRSTATUS */
AnnaBridge 170:e95d10626187 752 #define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 753 #define QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 754 #define QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED (0x1UL << 4) /**< Two indirect write operations have been queued */
AnnaBridge 170:e95d10626187 755 #define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_SHIFT 4 /**< Shift value for QSPI_WRQUEUED */
AnnaBridge 170:e95d10626187 756 #define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_MASK 0x10UL /**< Bit mask for QSPI_WRQUEUED */
AnnaBridge 170:e95d10626187 757 #define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 758 #define QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT << 4) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 759 #define QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS (0x1UL << 5) /**< Indirect Completion Status */
AnnaBridge 170:e95d10626187 760 #define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_SHIFT 5 /**< Shift value for QSPI_INDOPSDONESTATUS */
AnnaBridge 170:e95d10626187 761 #define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_MASK 0x20UL /**< Bit mask for QSPI_INDOPSDONESTATUS */
AnnaBridge 170:e95d10626187 762 #define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 763 #define QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 764 #define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_SHIFT 6 /**< Shift value for QSPI_NUMINDOPSDONE */
AnnaBridge 170:e95d10626187 765 #define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_MASK 0xC0UL /**< Bit mask for QSPI_NUMINDOPSDONE */
AnnaBridge 170:e95d10626187 766 #define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 767 #define QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT (_QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL */
AnnaBridge 170:e95d10626187 768
AnnaBridge 170:e95d10626187 769 /* Bit fields for QSPI INDIRECTWRITEXFERWATERMARK */
AnnaBridge 170:e95d10626187 770 #define _QSPI_INDIRECTWRITEXFERWATERMARK_RESETVALUE 0xFFFFFFFFUL /**< Default value for QSPI_INDIRECTWRITEXFERWATERMARK */
AnnaBridge 170:e95d10626187 771 #define _QSPI_INDIRECTWRITEXFERWATERMARK_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTWRITEXFERWATERMARK */
AnnaBridge 170:e95d10626187 772 #define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_SHIFT 0 /**< Shift value for QSPI_LEVEL */
AnnaBridge 170:e95d10626187 773 #define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_LEVEL */
AnnaBridge 170:e95d10626187 774 #define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT 0xFFFFFFFFUL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERWATERMARK */
AnnaBridge 170:e95d10626187 775 #define QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT (_QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERWATERMARK */
AnnaBridge 170:e95d10626187 776
AnnaBridge 170:e95d10626187 777 /* Bit fields for QSPI INDIRECTWRITEXFERSTART */
AnnaBridge 170:e95d10626187 778 #define _QSPI_INDIRECTWRITEXFERSTART_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTWRITEXFERSTART */
AnnaBridge 170:e95d10626187 779 #define _QSPI_INDIRECTWRITEXFERSTART_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTWRITEXFERSTART */
AnnaBridge 170:e95d10626187 780 #define _QSPI_INDIRECTWRITEXFERSTART_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */
AnnaBridge 170:e95d10626187 781 #define _QSPI_INDIRECTWRITEXFERSTART_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_ADDR */
AnnaBridge 170:e95d10626187 782 #define _QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERSTART */
AnnaBridge 170:e95d10626187 783 #define QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT (_QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERSTART */
AnnaBridge 170:e95d10626187 784
AnnaBridge 170:e95d10626187 785 /* Bit fields for QSPI INDIRECTWRITEXFERNUMBYTES */
AnnaBridge 170:e95d10626187 786 #define _QSPI_INDIRECTWRITEXFERNUMBYTES_RESETVALUE 0x00000000UL /**< Default value for QSPI_INDIRECTWRITEXFERNUMBYTES */
AnnaBridge 170:e95d10626187 787 #define _QSPI_INDIRECTWRITEXFERNUMBYTES_MASK 0xFFFFFFFFUL /**< Mask for QSPI_INDIRECTWRITEXFERNUMBYTES */
AnnaBridge 170:e95d10626187 788 #define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_SHIFT 0 /**< Shift value for QSPI_VALUE */
AnnaBridge 170:e95d10626187 789 #define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_VALUE */
AnnaBridge 170:e95d10626187 790 #define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_INDIRECTWRITEXFERNUMBYTES */
AnnaBridge 170:e95d10626187 791 #define QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT (_QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERNUMBYTES */
AnnaBridge 170:e95d10626187 792
AnnaBridge 170:e95d10626187 793 /* Bit fields for QSPI INDIRECTTRIGGERADDRRANGE */
AnnaBridge 170:e95d10626187 794 #define _QSPI_INDIRECTTRIGGERADDRRANGE_RESETVALUE 0x00000004UL /**< Default value for QSPI_INDIRECTTRIGGERADDRRANGE */
AnnaBridge 170:e95d10626187 795 #define _QSPI_INDIRECTTRIGGERADDRRANGE_MASK 0x0000000FUL /**< Mask for QSPI_INDIRECTTRIGGERADDRRANGE */
AnnaBridge 170:e95d10626187 796 #define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_SHIFT 0 /**< Shift value for QSPI_INDRANGEWIDTH */
AnnaBridge 170:e95d10626187 797 #define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_MASK 0xFUL /**< Bit mask for QSPI_INDRANGEWIDTH */
AnnaBridge 170:e95d10626187 798 #define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT 0x00000004UL /**< Mode DEFAULT for QSPI_INDIRECTTRIGGERADDRRANGE */
AnnaBridge 170:e95d10626187 799 #define QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT (_QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_INDIRECTTRIGGERADDRRANGE */
AnnaBridge 170:e95d10626187 800
AnnaBridge 170:e95d10626187 801 /* Bit fields for QSPI FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 802 #define _QSPI_FLASHCOMMANDCTRLMEM_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 803 #define _QSPI_FLASHCOMMANDCTRLMEM_MASK 0x1FF7FF03UL /**< Mask for QSPI_FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 804 #define QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ (0x1UL << 0) /**< Trigger the Memory Bank data request. */
AnnaBridge 170:e95d10626187 805 #define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_SHIFT 0 /**< Shift value for QSPI_TRIGGERMEMBANKREQ */
AnnaBridge 170:e95d10626187 806 #define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_MASK 0x1UL /**< Bit mask for QSPI_TRIGGERMEMBANKREQ */
AnnaBridge 170:e95d10626187 807 #define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 808 #define QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 809 #define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS (0x1UL << 1) /**< Memory Bank data request in progress. */
AnnaBridge 170:e95d10626187 810 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_SHIFT 1 /**< Shift value for QSPI_MEMBANKREQINPROGRESS */
AnnaBridge 170:e95d10626187 811 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_MASK 0x2UL /**< Bit mask for QSPI_MEMBANKREQINPROGRESS */
AnnaBridge 170:e95d10626187 812 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 813 #define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 814 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_SHIFT 8 /**< Shift value for QSPI_MEMBANKREADDATA */
AnnaBridge 170:e95d10626187 815 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_MASK 0xFF00UL /**< Bit mask for QSPI_MEMBANKREADDATA */
AnnaBridge 170:e95d10626187 816 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 817 #define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 818 #define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_SHIFT 16 /**< Shift value for QSPI_NBOFSTIGREADBYTES */
AnnaBridge 170:e95d10626187 819 #define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_MASK 0x70000UL /**< Bit mask for QSPI_NBOFSTIGREADBYTES */
AnnaBridge 170:e95d10626187 820 #define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 821 #define QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 822 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_SHIFT 20 /**< Shift value for QSPI_MEMBANKADDR */
AnnaBridge 170:e95d10626187 823 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_MASK 0x1FF00000UL /**< Bit mask for QSPI_MEMBANKADDR */
AnnaBridge 170:e95d10626187 824 #define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 825 #define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT << 20) /**< Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM */
AnnaBridge 170:e95d10626187 826
AnnaBridge 170:e95d10626187 827 /* Bit fields for QSPI FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 828 #define _QSPI_FLASHCMDCTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 829 #define _QSPI_FLASHCMDCTRL_MASK 0xFFFFFF87UL /**< Mask for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 830 #define QSPI_FLASHCMDCTRL_CMDEXEC (0x1UL << 0) /**< Execute the command. */
AnnaBridge 170:e95d10626187 831 #define _QSPI_FLASHCMDCTRL_CMDEXEC_SHIFT 0 /**< Shift value for QSPI_CMDEXEC */
AnnaBridge 170:e95d10626187 832 #define _QSPI_FLASHCMDCTRL_CMDEXEC_MASK 0x1UL /**< Bit mask for QSPI_CMDEXEC */
AnnaBridge 170:e95d10626187 833 #define _QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 834 #define QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT (_QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 835 #define QSPI_FLASHCMDCTRL_CMDEXECSTATUS (0x1UL << 1) /**< Command execution in progress. */
AnnaBridge 170:e95d10626187 836 #define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_SHIFT 1 /**< Shift value for QSPI_CMDEXECSTATUS */
AnnaBridge 170:e95d10626187 837 #define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_MASK 0x2UL /**< Bit mask for QSPI_CMDEXECSTATUS */
AnnaBridge 170:e95d10626187 838 #define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 839 #define QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT (_QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 840 #define QSPI_FLASHCMDCTRL_STIGMEMBANKEN (0x1UL << 2) /**< STIG Memory Bank enable bit. */
AnnaBridge 170:e95d10626187 841 #define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_SHIFT 2 /**< Shift value for QSPI_STIGMEMBANKEN */
AnnaBridge 170:e95d10626187 842 #define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_MASK 0x4UL /**< Bit mask for QSPI_STIGMEMBANKEN */
AnnaBridge 170:e95d10626187 843 #define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 844 #define QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT (_QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 845 #define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_SHIFT 7 /**< Shift value for QSPI_NUMDUMMYCYCLES */
AnnaBridge 170:e95d10626187 846 #define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_MASK 0xF80UL /**< Bit mask for QSPI_NUMDUMMYCYCLES */
AnnaBridge 170:e95d10626187 847 #define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 848 #define QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT (_QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 849 #define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_SHIFT 12 /**< Shift value for QSPI_NUMWRDATABYTES */
AnnaBridge 170:e95d10626187 850 #define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_MASK 0x7000UL /**< Bit mask for QSPI_NUMWRDATABYTES */
AnnaBridge 170:e95d10626187 851 #define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 852 #define QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT (_QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 853 #define QSPI_FLASHCMDCTRL_ENBWRITEDATA (0x1UL << 15) /**< Write Data Enable */
AnnaBridge 170:e95d10626187 854 #define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_SHIFT 15 /**< Shift value for QSPI_ENBWRITEDATA */
AnnaBridge 170:e95d10626187 855 #define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_MASK 0x8000UL /**< Bit mask for QSPI_ENBWRITEDATA */
AnnaBridge 170:e95d10626187 856 #define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 857 #define QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT (_QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT << 15) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 858 #define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_SHIFT 16 /**< Shift value for QSPI_NUMADDRBYTES */
AnnaBridge 170:e95d10626187 859 #define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_MASK 0x30000UL /**< Bit mask for QSPI_NUMADDRBYTES */
AnnaBridge 170:e95d10626187 860 #define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 861 #define QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT (_QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 862 #define QSPI_FLASHCMDCTRL_ENBMODEBIT (0x1UL << 18) /**< Mode Bit Enable */
AnnaBridge 170:e95d10626187 863 #define _QSPI_FLASHCMDCTRL_ENBMODEBIT_SHIFT 18 /**< Shift value for QSPI_ENBMODEBIT */
AnnaBridge 170:e95d10626187 864 #define _QSPI_FLASHCMDCTRL_ENBMODEBIT_MASK 0x40000UL /**< Bit mask for QSPI_ENBMODEBIT */
AnnaBridge 170:e95d10626187 865 #define _QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 866 #define QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT (_QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT << 18) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 867 #define QSPI_FLASHCMDCTRL_ENBCOMDADDR (0x1UL << 19) /**< Command Address Enable */
AnnaBridge 170:e95d10626187 868 #define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_SHIFT 19 /**< Shift value for QSPI_ENBCOMDADDR */
AnnaBridge 170:e95d10626187 869 #define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_MASK 0x80000UL /**< Bit mask for QSPI_ENBCOMDADDR */
AnnaBridge 170:e95d10626187 870 #define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 871 #define QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT (_QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT << 19) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 872 #define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_SHIFT 20 /**< Shift value for QSPI_NUMRDDATABYTES */
AnnaBridge 170:e95d10626187 873 #define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_MASK 0x700000UL /**< Bit mask for QSPI_NUMRDDATABYTES */
AnnaBridge 170:e95d10626187 874 #define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 875 #define QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT (_QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT << 20) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 876 #define QSPI_FLASHCMDCTRL_ENBREADDATA (0x1UL << 23) /**< Read Data Enable */
AnnaBridge 170:e95d10626187 877 #define _QSPI_FLASHCMDCTRL_ENBREADDATA_SHIFT 23 /**< Shift value for QSPI_ENBREADDATA */
AnnaBridge 170:e95d10626187 878 #define _QSPI_FLASHCMDCTRL_ENBREADDATA_MASK 0x800000UL /**< Bit mask for QSPI_ENBREADDATA */
AnnaBridge 170:e95d10626187 879 #define _QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 880 #define QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT (_QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT << 23) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 881 #define _QSPI_FLASHCMDCTRL_CMDOPCODE_SHIFT 24 /**< Shift value for QSPI_CMDOPCODE */
AnnaBridge 170:e95d10626187 882 #define _QSPI_FLASHCMDCTRL_CMDOPCODE_MASK 0xFF000000UL /**< Bit mask for QSPI_CMDOPCODE */
AnnaBridge 170:e95d10626187 883 #define _QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 884 #define QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT (_QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_FLASHCMDCTRL */
AnnaBridge 170:e95d10626187 885
AnnaBridge 170:e95d10626187 886 /* Bit fields for QSPI FLASHCMDADDR */
AnnaBridge 170:e95d10626187 887 #define _QSPI_FLASHCMDADDR_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHCMDADDR */
AnnaBridge 170:e95d10626187 888 #define _QSPI_FLASHCMDADDR_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHCMDADDR */
AnnaBridge 170:e95d10626187 889 #define _QSPI_FLASHCMDADDR_ADDR_SHIFT 0 /**< Shift value for QSPI_ADDR */
AnnaBridge 170:e95d10626187 890 #define _QSPI_FLASHCMDADDR_ADDR_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_ADDR */
AnnaBridge 170:e95d10626187 891 #define _QSPI_FLASHCMDADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHCMDADDR */
AnnaBridge 170:e95d10626187 892 #define QSPI_FLASHCMDADDR_ADDR_DEFAULT (_QSPI_FLASHCMDADDR_ADDR_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHCMDADDR */
AnnaBridge 170:e95d10626187 893
AnnaBridge 170:e95d10626187 894 /* Bit fields for QSPI FLASHRDDATALOWER */
AnnaBridge 170:e95d10626187 895 #define _QSPI_FLASHRDDATALOWER_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHRDDATALOWER */
AnnaBridge 170:e95d10626187 896 #define _QSPI_FLASHRDDATALOWER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHRDDATALOWER */
AnnaBridge 170:e95d10626187 897 #define _QSPI_FLASHRDDATALOWER_DATA_SHIFT 0 /**< Shift value for QSPI_DATA */
AnnaBridge 170:e95d10626187 898 #define _QSPI_FLASHRDDATALOWER_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_DATA */
AnnaBridge 170:e95d10626187 899 #define _QSPI_FLASHRDDATALOWER_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHRDDATALOWER */
AnnaBridge 170:e95d10626187 900 #define QSPI_FLASHRDDATALOWER_DATA_DEFAULT (_QSPI_FLASHRDDATALOWER_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHRDDATALOWER */
AnnaBridge 170:e95d10626187 901
AnnaBridge 170:e95d10626187 902 /* Bit fields for QSPI FLASHRDDATAUPPER */
AnnaBridge 170:e95d10626187 903 #define _QSPI_FLASHRDDATAUPPER_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHRDDATAUPPER */
AnnaBridge 170:e95d10626187 904 #define _QSPI_FLASHRDDATAUPPER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHRDDATAUPPER */
AnnaBridge 170:e95d10626187 905 #define _QSPI_FLASHRDDATAUPPER_DATA_SHIFT 0 /**< Shift value for QSPI_DATA */
AnnaBridge 170:e95d10626187 906 #define _QSPI_FLASHRDDATAUPPER_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_DATA */
AnnaBridge 170:e95d10626187 907 #define _QSPI_FLASHRDDATAUPPER_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHRDDATAUPPER */
AnnaBridge 170:e95d10626187 908 #define QSPI_FLASHRDDATAUPPER_DATA_DEFAULT (_QSPI_FLASHRDDATAUPPER_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHRDDATAUPPER */
AnnaBridge 170:e95d10626187 909
AnnaBridge 170:e95d10626187 910 /* Bit fields for QSPI FLASHWRDATALOWER */
AnnaBridge 170:e95d10626187 911 #define _QSPI_FLASHWRDATALOWER_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHWRDATALOWER */
AnnaBridge 170:e95d10626187 912 #define _QSPI_FLASHWRDATALOWER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHWRDATALOWER */
AnnaBridge 170:e95d10626187 913 #define _QSPI_FLASHWRDATALOWER_DATA_SHIFT 0 /**< Shift value for QSPI_DATA */
AnnaBridge 170:e95d10626187 914 #define _QSPI_FLASHWRDATALOWER_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_DATA */
AnnaBridge 170:e95d10626187 915 #define _QSPI_FLASHWRDATALOWER_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHWRDATALOWER */
AnnaBridge 170:e95d10626187 916 #define QSPI_FLASHWRDATALOWER_DATA_DEFAULT (_QSPI_FLASHWRDATALOWER_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHWRDATALOWER */
AnnaBridge 170:e95d10626187 917
AnnaBridge 170:e95d10626187 918 /* Bit fields for QSPI FLASHWRDATAUPPER */
AnnaBridge 170:e95d10626187 919 #define _QSPI_FLASHWRDATAUPPER_RESETVALUE 0x00000000UL /**< Default value for QSPI_FLASHWRDATAUPPER */
AnnaBridge 170:e95d10626187 920 #define _QSPI_FLASHWRDATAUPPER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_FLASHWRDATAUPPER */
AnnaBridge 170:e95d10626187 921 #define _QSPI_FLASHWRDATAUPPER_DATA_SHIFT 0 /**< Shift value for QSPI_DATA */
AnnaBridge 170:e95d10626187 922 #define _QSPI_FLASHWRDATAUPPER_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for QSPI_DATA */
AnnaBridge 170:e95d10626187 923 #define _QSPI_FLASHWRDATAUPPER_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_FLASHWRDATAUPPER */
AnnaBridge 170:e95d10626187 924 #define QSPI_FLASHWRDATAUPPER_DATA_DEFAULT (_QSPI_FLASHWRDATAUPPER_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_FLASHWRDATAUPPER */
AnnaBridge 170:e95d10626187 925
AnnaBridge 170:e95d10626187 926 /* Bit fields for QSPI POLLINGFLASHSTATUS */
AnnaBridge 170:e95d10626187 927 #define _QSPI_POLLINGFLASHSTATUS_RESETVALUE 0x00000000UL /**< Default value for QSPI_POLLINGFLASHSTATUS */
AnnaBridge 170:e95d10626187 928 #define _QSPI_POLLINGFLASHSTATUS_MASK 0x000F01FFUL /**< Mask for QSPI_POLLINGFLASHSTATUS */
AnnaBridge 170:e95d10626187 929 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_SHIFT 0 /**< Shift value for QSPI_DEVICESTATUS */
AnnaBridge 170:e95d10626187 930 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_MASK 0xFFUL /**< Bit mask for QSPI_DEVICESTATUS */
AnnaBridge 170:e95d10626187 931 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_POLLINGFLASHSTATUS */
AnnaBridge 170:e95d10626187 932 #define QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_POLLINGFLASHSTATUS */
AnnaBridge 170:e95d10626187 933 #define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID (0x1UL << 8) /**< Device Status Valid */
AnnaBridge 170:e95d10626187 934 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_SHIFT 8 /**< Shift value for QSPI_DEVICESTATUSVALID */
AnnaBridge 170:e95d10626187 935 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_MASK 0x100UL /**< Bit mask for QSPI_DEVICESTATUSVALID */
AnnaBridge 170:e95d10626187 936 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_POLLINGFLASHSTATUS */
AnnaBridge 170:e95d10626187 937 #define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_POLLINGFLASHSTATUS */
AnnaBridge 170:e95d10626187 938 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_SHIFT 16 /**< Shift value for QSPI_DEVICESTATUSNBDUMMY */
AnnaBridge 170:e95d10626187 939 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_MASK 0xF0000UL /**< Bit mask for QSPI_DEVICESTATUSNBDUMMY */
AnnaBridge 170:e95d10626187 940 #define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_POLLINGFLASHSTATUS */
AnnaBridge 170:e95d10626187 941 #define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_POLLINGFLASHSTATUS */
AnnaBridge 170:e95d10626187 942
AnnaBridge 170:e95d10626187 943 /* Bit fields for QSPI PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 944 #define _QSPI_PHYCONFIGURATION_RESETVALUE 0x00000000UL /**< Default value for QSPI_PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 945 #define _QSPI_PHYCONFIGURATION_MASK 0xE07F007FUL /**< Mask for QSPI_PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 946 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_SHIFT 0 /**< Shift value for QSPI_PHYCONFIGRXDLLDELAY */
AnnaBridge 170:e95d10626187 947 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_MASK 0x7FUL /**< Bit mask for QSPI_PHYCONFIGRXDLLDELAY */
AnnaBridge 170:e95d10626187 948 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 949 #define QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT (_QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 950 #define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_SHIFT 16 /**< Shift value for QSPI_PHYCONFIGTXDLLDELAY */
AnnaBridge 170:e95d10626187 951 #define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_MASK 0x7F0000UL /**< Bit mask for QSPI_PHYCONFIGTXDLLDELAY */
AnnaBridge 170:e95d10626187 952 #define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 953 #define QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT (_QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 954 #define QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLBYPASS (0x1UL << 29) /**< RX DLL Bypass */
AnnaBridge 170:e95d10626187 955 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLBYPASS_SHIFT 29 /**< Shift value for QSPI_PHYCONFIGRXDLLBYPASS */
AnnaBridge 170:e95d10626187 956 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLBYPASS_MASK 0x20000000UL /**< Bit mask for QSPI_PHYCONFIGRXDLLBYPASS */
AnnaBridge 170:e95d10626187 957 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 958 #define QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLBYPASS_DEFAULT (_QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLBYPASS_DEFAULT << 29) /**< Shifted mode DEFAULT for QSPI_PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 959 #define QSPI_PHYCONFIGURATION_PHYCONFIGRESET (0x1UL << 30) /**< DLL Reset bit */
AnnaBridge 170:e95d10626187 960 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRESET_SHIFT 30 /**< Shift value for QSPI_PHYCONFIGRESET */
AnnaBridge 170:e95d10626187 961 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRESET_MASK 0x40000000UL /**< Bit mask for QSPI_PHYCONFIGRESET */
AnnaBridge 170:e95d10626187 962 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRESET_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 963 #define QSPI_PHYCONFIGURATION_PHYCONFIGRESET_DEFAULT (_QSPI_PHYCONFIGURATION_PHYCONFIGRESET_DEFAULT << 30) /**< Shifted mode DEFAULT for QSPI_PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 964 #define QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC (0x1UL << 31) /**< PHY Config Resync */
AnnaBridge 170:e95d10626187 965 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_SHIFT 31 /**< Shift value for QSPI_PHYCONFIGRESYNC */
AnnaBridge 170:e95d10626187 966 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_MASK 0x80000000UL /**< Bit mask for QSPI_PHYCONFIGRESYNC */
AnnaBridge 170:e95d10626187 967 #define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 968 #define QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT (_QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT << 31) /**< Shifted mode DEFAULT for QSPI_PHYCONFIGURATION */
AnnaBridge 170:e95d10626187 969
AnnaBridge 170:e95d10626187 970 /* Bit fields for QSPI PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 971 #define _QSPI_PHYMASTERCONTROL_RESETVALUE 0x00800000UL /**< Default value for QSPI_PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 972 #define _QSPI_PHYMASTERCONTROL_MASK 0x01F7007FUL /**< Mask for QSPI_PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 973 #define _QSPI_PHYMASTERCONTROL_PHYMASTERINITIALDELAY_SHIFT 0 /**< Shift value for QSPI_PHYMASTERINITIALDELAY */
AnnaBridge 170:e95d10626187 974 #define _QSPI_PHYMASTERCONTROL_PHYMASTERINITIALDELAY_MASK 0x7FUL /**< Bit mask for QSPI_PHYMASTERINITIALDELAY */
AnnaBridge 170:e95d10626187 975 #define _QSPI_PHYMASTERCONTROL_PHYMASTERINITIALDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 976 #define QSPI_PHYMASTERCONTROL_PHYMASTERINITIALDELAY_DEFAULT (_QSPI_PHYMASTERCONTROL_PHYMASTERINITIALDELAY_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 977 #define _QSPI_PHYMASTERCONTROL_PHYMASTERNBINDICATIONS_SHIFT 16 /**< Shift value for QSPI_PHYMASTERNBINDICATIONS */
AnnaBridge 170:e95d10626187 978 #define _QSPI_PHYMASTERCONTROL_PHYMASTERNBINDICATIONS_MASK 0x70000UL /**< Bit mask for QSPI_PHYMASTERNBINDICATIONS */
AnnaBridge 170:e95d10626187 979 #define _QSPI_PHYMASTERCONTROL_PHYMASTERNBINDICATIONS_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 980 #define QSPI_PHYMASTERCONTROL_PHYMASTERNBINDICATIONS_DEFAULT (_QSPI_PHYMASTERCONTROL_PHYMASTERNBINDICATIONS_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 981 #define _QSPI_PHYMASTERCONTROL_PHYMASTERPHASEDETECTSELECTOR_SHIFT 20 /**< Shift value for QSPI_PHYMASTERPHASEDETECTSELECTOR */
AnnaBridge 170:e95d10626187 982 #define _QSPI_PHYMASTERCONTROL_PHYMASTERPHASEDETECTSELECTOR_MASK 0x700000UL /**< Bit mask for QSPI_PHYMASTERPHASEDETECTSELECTOR */
AnnaBridge 170:e95d10626187 983 #define _QSPI_PHYMASTERCONTROL_PHYMASTERPHASEDETECTSELECTOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 984 #define QSPI_PHYMASTERCONTROL_PHYMASTERPHASEDETECTSELECTOR_DEFAULT (_QSPI_PHYMASTERCONTROL_PHYMASTERPHASEDETECTSELECTOR_DEFAULT << 20) /**< Shifted mode DEFAULT for QSPI_PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 985 #define QSPI_PHYMASTERCONTROL_PHYMASTERBYPASSMODE (0x1UL << 23) /**< PHY Master Bypass Mode */
AnnaBridge 170:e95d10626187 986 #define _QSPI_PHYMASTERCONTROL_PHYMASTERBYPASSMODE_SHIFT 23 /**< Shift value for QSPI_PHYMASTERBYPASSMODE */
AnnaBridge 170:e95d10626187 987 #define _QSPI_PHYMASTERCONTROL_PHYMASTERBYPASSMODE_MASK 0x800000UL /**< Bit mask for QSPI_PHYMASTERBYPASSMODE */
AnnaBridge 170:e95d10626187 988 #define _QSPI_PHYMASTERCONTROL_PHYMASTERBYPASSMODE_DEFAULT 0x00000001UL /**< Mode DEFAULT for QSPI_PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 989 #define QSPI_PHYMASTERCONTROL_PHYMASTERBYPASSMODE_DEFAULT (_QSPI_PHYMASTERCONTROL_PHYMASTERBYPASSMODE_DEFAULT << 23) /**< Shifted mode DEFAULT for QSPI_PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 990 #define QSPI_PHYMASTERCONTROL_PHYMASTERLOCKMODE (0x1UL << 24) /**< PHY Master Lock Mode */
AnnaBridge 170:e95d10626187 991 #define _QSPI_PHYMASTERCONTROL_PHYMASTERLOCKMODE_SHIFT 24 /**< Shift value for QSPI_PHYMASTERLOCKMODE */
AnnaBridge 170:e95d10626187 992 #define _QSPI_PHYMASTERCONTROL_PHYMASTERLOCKMODE_MASK 0x1000000UL /**< Bit mask for QSPI_PHYMASTERLOCKMODE */
AnnaBridge 170:e95d10626187 993 #define _QSPI_PHYMASTERCONTROL_PHYMASTERLOCKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 994 #define QSPI_PHYMASTERCONTROL_PHYMASTERLOCKMODE_DEFAULT (_QSPI_PHYMASTERCONTROL_PHYMASTERLOCKMODE_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_PHYMASTERCONTROL */
AnnaBridge 170:e95d10626187 995
AnnaBridge 170:e95d10626187 996 /* Bit fields for QSPI DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 997 #define _QSPI_DLLOBSERVABLELOWER_RESETVALUE 0x00000000UL /**< Default value for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 998 #define _QSPI_DLLOBSERVABLELOWER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 999 #define QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCK (0x1UL << 0) /**< Indicates status of DLL */
AnnaBridge 170:e95d10626187 1000 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCK_SHIFT 0 /**< Shift value for QSPI_DLLOBSERVABLELOWERDLLLOCK */
AnnaBridge 170:e95d10626187 1001 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCK_MASK 0x1UL /**< Bit mask for QSPI_DLLOBSERVABLELOWERDLLLOCK */
AnnaBridge 170:e95d10626187 1002 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1003 #define QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCK_DEFAULT (_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1004 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKMODE_SHIFT 1 /**< Shift value for QSPI_DLLOBSERVABLELOWERLOCKMODE */
AnnaBridge 170:e95d10626187 1005 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKMODE_MASK 0x6UL /**< Bit mask for QSPI_DLLOBSERVABLELOWERLOCKMODE */
AnnaBridge 170:e95d10626187 1006 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1007 #define QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKMODE_DEFAULT (_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKMODE_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1008 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERUNLOCKCOUNTER_SHIFT 3 /**< Shift value for QSPI_DLLOBSERVABLELOWERUNLOCKCOUNTER */
AnnaBridge 170:e95d10626187 1009 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERUNLOCKCOUNTER_MASK 0xF8UL /**< Bit mask for QSPI_DLLOBSERVABLELOWERUNLOCKCOUNTER */
AnnaBridge 170:e95d10626187 1010 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERUNLOCKCOUNTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1011 #define QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERUNLOCKCOUNTER_DEFAULT (_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERUNLOCKCOUNTER_DEFAULT << 3) /**< Shifted mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1012 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKVALUE_SHIFT 8 /**< Shift value for QSPI_DLLOBSERVABLELOWERLOCKVALUE */
AnnaBridge 170:e95d10626187 1013 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKVALUE_MASK 0x7F00UL /**< Bit mask for QSPI_DLLOBSERVABLELOWERLOCKVALUE */
AnnaBridge 170:e95d10626187 1014 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKVALUE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1015 #define QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKVALUE_DEFAULT (_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOCKVALUE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1016 #define QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOOPBACKLOCK (0x1UL << 15) /**< DLL Observable Lower Loopback Lock */
AnnaBridge 170:e95d10626187 1017 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOOPBACKLOCK_SHIFT 15 /**< Shift value for QSPI_DLLOBSERVABLELOWERLOOPBACKLOCK */
AnnaBridge 170:e95d10626187 1018 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOOPBACKLOCK_MASK 0x8000UL /**< Bit mask for QSPI_DLLOBSERVABLELOWERLOOPBACKLOCK */
AnnaBridge 170:e95d10626187 1019 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOOPBACKLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1020 #define QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOOPBACKLOCK_DEFAULT (_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERLOOPBACKLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1021 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKDEC_SHIFT 16 /**< Shift value for QSPI_DLLOBSERVABLELOWERDLLLOCKDEC */
AnnaBridge 170:e95d10626187 1022 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKDEC_MASK 0xFF0000UL /**< Bit mask for QSPI_DLLOBSERVABLELOWERDLLLOCKDEC */
AnnaBridge 170:e95d10626187 1023 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKDEC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1024 #define QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKDEC_DEFAULT (_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKDEC_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1025 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKINC_SHIFT 24 /**< Shift value for QSPI_DLLOBSERVABLELOWERDLLLOCKINC */
AnnaBridge 170:e95d10626187 1026 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKINC_MASK 0xFF000000UL /**< Bit mask for QSPI_DLLOBSERVABLELOWERDLLLOCKINC */
AnnaBridge 170:e95d10626187 1027 #define _QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKINC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1028 #define QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKINC_DEFAULT (_QSPI_DLLOBSERVABLELOWER_DLLOBSERVABLELOWERDLLLOCKINC_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_DLLOBSERVABLELOWER */
AnnaBridge 170:e95d10626187 1029
AnnaBridge 170:e95d10626187 1030 /* Bit fields for QSPI DLLOBSERVABLEUPPER */
AnnaBridge 170:e95d10626187 1031 #define _QSPI_DLLOBSERVABLEUPPER_RESETVALUE 0x00000000UL /**< Default value for QSPI_DLLOBSERVABLEUPPER */
AnnaBridge 170:e95d10626187 1032 #define _QSPI_DLLOBSERVABLEUPPER_MASK 0x007F007FUL /**< Mask for QSPI_DLLOBSERVABLEUPPER */
AnnaBridge 170:e95d10626187 1033 #define _QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERRXDECODEROUTPUT_SHIFT 0 /**< Shift value for QSPI_DLLOBSERVABLEUPPERRXDECODEROUTPUT */
AnnaBridge 170:e95d10626187 1034 #define _QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERRXDECODEROUTPUT_MASK 0x7FUL /**< Bit mask for QSPI_DLLOBSERVABLEUPPERRXDECODEROUTPUT */
AnnaBridge 170:e95d10626187 1035 #define _QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERRXDECODEROUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DLLOBSERVABLEUPPER */
AnnaBridge 170:e95d10626187 1036 #define QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERRXDECODEROUTPUT_DEFAULT (_QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERRXDECODEROUTPUT_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_DLLOBSERVABLEUPPER */
AnnaBridge 170:e95d10626187 1037 #define _QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERTXDECODEROUTPUT_SHIFT 16 /**< Shift value for QSPI_DLLOBSERVABLEUPPERTXDECODEROUTPUT */
AnnaBridge 170:e95d10626187 1038 #define _QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERTXDECODEROUTPUT_MASK 0x7F0000UL /**< Bit mask for QSPI_DLLOBSERVABLEUPPERTXDECODEROUTPUT */
AnnaBridge 170:e95d10626187 1039 #define _QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERTXDECODEROUTPUT_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_DLLOBSERVABLEUPPER */
AnnaBridge 170:e95d10626187 1040 #define QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERTXDECODEROUTPUT_DEFAULT (_QSPI_DLLOBSERVABLEUPPER_DLLOBSERVABLEUPPERTXDECODEROUTPUT_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_DLLOBSERVABLEUPPER */
AnnaBridge 170:e95d10626187 1041
AnnaBridge 170:e95d10626187 1042 /* Bit fields for QSPI OPCODEEXTLOWER */
AnnaBridge 170:e95d10626187 1043 #define _QSPI_OPCODEEXTLOWER_RESETVALUE 0x13EDFA00UL /**< Default value for QSPI_OPCODEEXTLOWER */
AnnaBridge 170:e95d10626187 1044 #define _QSPI_OPCODEEXTLOWER_MASK 0xFFFFFFFFUL /**< Mask for QSPI_OPCODEEXTLOWER */
AnnaBridge 170:e95d10626187 1045 #define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_SHIFT 0 /**< Shift value for QSPI_EXTSTIGOPCODE */
AnnaBridge 170:e95d10626187 1046 #define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_MASK 0xFFUL /**< Bit mask for QSPI_EXTSTIGOPCODE */
AnnaBridge 170:e95d10626187 1047 #define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_OPCODEEXTLOWER */
AnnaBridge 170:e95d10626187 1048 #define QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT (_QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER */
AnnaBridge 170:e95d10626187 1049 #define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_SHIFT 8 /**< Shift value for QSPI_EXTPOLLOPCODE */
AnnaBridge 170:e95d10626187 1050 #define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_MASK 0xFF00UL /**< Bit mask for QSPI_EXTPOLLOPCODE */
AnnaBridge 170:e95d10626187 1051 #define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT 0x000000FAUL /**< Mode DEFAULT for QSPI_OPCODEEXTLOWER */
AnnaBridge 170:e95d10626187 1052 #define QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT (_QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER */
AnnaBridge 170:e95d10626187 1053 #define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_SHIFT 16 /**< Shift value for QSPI_EXTWRITEOPCODE */
AnnaBridge 170:e95d10626187 1054 #define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_MASK 0xFF0000UL /**< Bit mask for QSPI_EXTWRITEOPCODE */
AnnaBridge 170:e95d10626187 1055 #define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT 0x000000EDUL /**< Mode DEFAULT for QSPI_OPCODEEXTLOWER */
AnnaBridge 170:e95d10626187 1056 #define QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT (_QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER */
AnnaBridge 170:e95d10626187 1057 #define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_SHIFT 24 /**< Shift value for QSPI_EXTREADOPCODE */
AnnaBridge 170:e95d10626187 1058 #define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_MASK 0xFF000000UL /**< Bit mask for QSPI_EXTREADOPCODE */
AnnaBridge 170:e95d10626187 1059 #define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT 0x00000013UL /**< Mode DEFAULT for QSPI_OPCODEEXTLOWER */
AnnaBridge 170:e95d10626187 1060 #define QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT (_QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER */
AnnaBridge 170:e95d10626187 1061
AnnaBridge 170:e95d10626187 1062 /* Bit fields for QSPI OPCODEEXTUPPER */
AnnaBridge 170:e95d10626187 1063 #define _QSPI_OPCODEEXTUPPER_RESETVALUE 0x06F90000UL /**< Default value for QSPI_OPCODEEXTUPPER */
AnnaBridge 170:e95d10626187 1064 #define _QSPI_OPCODEEXTUPPER_MASK 0xFFFF0000UL /**< Mask for QSPI_OPCODEEXTUPPER */
AnnaBridge 170:e95d10626187 1065 #define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_SHIFT 16 /**< Shift value for QSPI_EXTWELOPCODE */
AnnaBridge 170:e95d10626187 1066 #define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_MASK 0xFF0000UL /**< Bit mask for QSPI_EXTWELOPCODE */
AnnaBridge 170:e95d10626187 1067 #define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT 0x000000F9UL /**< Mode DEFAULT for QSPI_OPCODEEXTUPPER */
AnnaBridge 170:e95d10626187 1068 #define QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT (_QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT << 16) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTUPPER */
AnnaBridge 170:e95d10626187 1069 #define _QSPI_OPCODEEXTUPPER_WELOPCODE_SHIFT 24 /**< Shift value for QSPI_WELOPCODE */
AnnaBridge 170:e95d10626187 1070 #define _QSPI_OPCODEEXTUPPER_WELOPCODE_MASK 0xFF000000UL /**< Bit mask for QSPI_WELOPCODE */
AnnaBridge 170:e95d10626187 1071 #define _QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT 0x00000006UL /**< Mode DEFAULT for QSPI_OPCODEEXTUPPER */
AnnaBridge 170:e95d10626187 1072 #define QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT (_QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_OPCODEEXTUPPER */
AnnaBridge 170:e95d10626187 1073
AnnaBridge 170:e95d10626187 1074 /* Bit fields for QSPI MODULEID */
AnnaBridge 170:e95d10626187 1075 #define _QSPI_MODULEID_RESETVALUE 0x00000200UL /**< Default value for QSPI_MODULEID */
AnnaBridge 170:e95d10626187 1076 #define _QSPI_MODULEID_MASK 0xFFFFFF03UL /**< Mask for QSPI_MODULEID */
AnnaBridge 170:e95d10626187 1077 #define _QSPI_MODULEID_CONF_SHIFT 0 /**< Shift value for QSPI_CONF */
AnnaBridge 170:e95d10626187 1078 #define _QSPI_MODULEID_CONF_MASK 0x3UL /**< Bit mask for QSPI_CONF */
AnnaBridge 170:e95d10626187 1079 #define _QSPI_MODULEID_CONF_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODULEID */
AnnaBridge 170:e95d10626187 1080 #define QSPI_MODULEID_CONF_DEFAULT (_QSPI_MODULEID_CONF_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_MODULEID */
AnnaBridge 170:e95d10626187 1081 #define _QSPI_MODULEID_MODULEID_SHIFT 8 /**< Shift value for QSPI_MODULEID */
AnnaBridge 170:e95d10626187 1082 #define _QSPI_MODULEID_MODULEID_MASK 0xFFFF00UL /**< Bit mask for QSPI_MODULEID */
AnnaBridge 170:e95d10626187 1083 #define _QSPI_MODULEID_MODULEID_DEFAULT 0x00000002UL /**< Mode DEFAULT for QSPI_MODULEID */
AnnaBridge 170:e95d10626187 1084 #define QSPI_MODULEID_MODULEID_DEFAULT (_QSPI_MODULEID_MODULEID_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_MODULEID */
AnnaBridge 170:e95d10626187 1085 #define _QSPI_MODULEID_FIXPATCH_SHIFT 24 /**< Shift value for QSPI_FIXPATCH */
AnnaBridge 170:e95d10626187 1086 #define _QSPI_MODULEID_FIXPATCH_MASK 0xFF000000UL /**< Bit mask for QSPI_FIXPATCH */
AnnaBridge 170:e95d10626187 1087 #define _QSPI_MODULEID_FIXPATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_MODULEID */
AnnaBridge 170:e95d10626187 1088 #define QSPI_MODULEID_FIXPATCH_DEFAULT (_QSPI_MODULEID_FIXPATCH_DEFAULT << 24) /**< Shifted mode DEFAULT for QSPI_MODULEID */
AnnaBridge 170:e95d10626187 1089
AnnaBridge 170:e95d10626187 1090 /* Bit fields for QSPI CTRL */
AnnaBridge 170:e95d10626187 1091 #define _QSPI_CTRL_RESETVALUE 0x00000000UL /**< Default value for QSPI_CTRL */
AnnaBridge 170:e95d10626187 1092 #define _QSPI_CTRL_MASK 0x00000003UL /**< Mask for QSPI_CTRL */
AnnaBridge 170:e95d10626187 1093 #define _QSPI_CTRL_TXDLYMUXSEL_SHIFT 0 /**< Shift value for QSPI_TXDLYMUXSEL */
AnnaBridge 170:e95d10626187 1094 #define _QSPI_CTRL_TXDLYMUXSEL_MASK 0x3UL /**< Bit mask for QSPI_TXDLYMUXSEL */
AnnaBridge 170:e95d10626187 1095 #define _QSPI_CTRL_TXDLYMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_CTRL */
AnnaBridge 170:e95d10626187 1096 #define _QSPI_CTRL_TXDLYMUXSEL_NONE 0x00000000UL /**< Mode NONE for QSPI_CTRL */
AnnaBridge 170:e95d10626187 1097 #define _QSPI_CTRL_TXDLYMUXSEL_MEDIUM 0x00000002UL /**< Mode MEDIUM for QSPI_CTRL */
AnnaBridge 170:e95d10626187 1098 #define _QSPI_CTRL_TXDLYMUXSEL_LARGE 0x00000003UL /**< Mode LARGE for QSPI_CTRL */
AnnaBridge 170:e95d10626187 1099 #define QSPI_CTRL_TXDLYMUXSEL_DEFAULT (_QSPI_CTRL_TXDLYMUXSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_CTRL */
AnnaBridge 170:e95d10626187 1100 #define QSPI_CTRL_TXDLYMUXSEL_NONE (_QSPI_CTRL_TXDLYMUXSEL_NONE << 0) /**< Shifted mode NONE for QSPI_CTRL */
AnnaBridge 170:e95d10626187 1101 #define QSPI_CTRL_TXDLYMUXSEL_MEDIUM (_QSPI_CTRL_TXDLYMUXSEL_MEDIUM << 0) /**< Shifted mode MEDIUM for QSPI_CTRL */
AnnaBridge 170:e95d10626187 1102 #define QSPI_CTRL_TXDLYMUXSEL_LARGE (_QSPI_CTRL_TXDLYMUXSEL_LARGE << 0) /**< Shifted mode LARGE for QSPI_CTRL */
AnnaBridge 170:e95d10626187 1103
AnnaBridge 170:e95d10626187 1104 /* Bit fields for QSPI ROUTEPEN */
AnnaBridge 170:e95d10626187 1105 #define _QSPI_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1106 #define _QSPI_ROUTEPEN_MASK 0x00007FE7UL /**< Mask for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1107 #define QSPI_ROUTEPEN_SCLKPEN (0x1UL << 0) /**< SCLK Pin Enable */
AnnaBridge 170:e95d10626187 1108 #define _QSPI_ROUTEPEN_SCLKPEN_SHIFT 0 /**< Shift value for QSPI_SCLKPEN */
AnnaBridge 170:e95d10626187 1109 #define _QSPI_ROUTEPEN_SCLKPEN_MASK 0x1UL /**< Bit mask for QSPI_SCLKPEN */
AnnaBridge 170:e95d10626187 1110 #define _QSPI_ROUTEPEN_SCLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1111 #define QSPI_ROUTEPEN_SCLKPEN_DEFAULT (_QSPI_ROUTEPEN_SCLKPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1112 #define QSPI_ROUTEPEN_CS0PEN (0x1UL << 1) /**< CS0 Pin Enable */
AnnaBridge 170:e95d10626187 1113 #define _QSPI_ROUTEPEN_CS0PEN_SHIFT 1 /**< Shift value for QSPI_CS0PEN */
AnnaBridge 170:e95d10626187 1114 #define _QSPI_ROUTEPEN_CS0PEN_MASK 0x2UL /**< Bit mask for QSPI_CS0PEN */
AnnaBridge 170:e95d10626187 1115 #define _QSPI_ROUTEPEN_CS0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1116 #define QSPI_ROUTEPEN_CS0PEN_DEFAULT (_QSPI_ROUTEPEN_CS0PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1117 #define QSPI_ROUTEPEN_CS1PEN (0x1UL << 2) /**< CS1 Pin Enable */
AnnaBridge 170:e95d10626187 1118 #define _QSPI_ROUTEPEN_CS1PEN_SHIFT 2 /**< Shift value for QSPI_CS1PEN */
AnnaBridge 170:e95d10626187 1119 #define _QSPI_ROUTEPEN_CS1PEN_MASK 0x4UL /**< Bit mask for QSPI_CS1PEN */
AnnaBridge 170:e95d10626187 1120 #define _QSPI_ROUTEPEN_CS1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1121 #define QSPI_ROUTEPEN_CS1PEN_DEFAULT (_QSPI_ROUTEPEN_CS1PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1122 #define QSPI_ROUTEPEN_DQ0PEN (0x1UL << 5) /**< DQ0 Pin Enable */
AnnaBridge 170:e95d10626187 1123 #define _QSPI_ROUTEPEN_DQ0PEN_SHIFT 5 /**< Shift value for QSPI_DQ0PEN */
AnnaBridge 170:e95d10626187 1124 #define _QSPI_ROUTEPEN_DQ0PEN_MASK 0x20UL /**< Bit mask for QSPI_DQ0PEN */
AnnaBridge 170:e95d10626187 1125 #define _QSPI_ROUTEPEN_DQ0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1126 #define QSPI_ROUTEPEN_DQ0PEN_DEFAULT (_QSPI_ROUTEPEN_DQ0PEN_DEFAULT << 5) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1127 #define QSPI_ROUTEPEN_DQ1PEN (0x1UL << 6) /**< DQ1 Pin Enable */
AnnaBridge 170:e95d10626187 1128 #define _QSPI_ROUTEPEN_DQ1PEN_SHIFT 6 /**< Shift value for QSPI_DQ1PEN */
AnnaBridge 170:e95d10626187 1129 #define _QSPI_ROUTEPEN_DQ1PEN_MASK 0x40UL /**< Bit mask for QSPI_DQ1PEN */
AnnaBridge 170:e95d10626187 1130 #define _QSPI_ROUTEPEN_DQ1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1131 #define QSPI_ROUTEPEN_DQ1PEN_DEFAULT (_QSPI_ROUTEPEN_DQ1PEN_DEFAULT << 6) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1132 #define QSPI_ROUTEPEN_DQ2PEN (0x1UL << 7) /**< DQ2 Pin Enable */
AnnaBridge 170:e95d10626187 1133 #define _QSPI_ROUTEPEN_DQ2PEN_SHIFT 7 /**< Shift value for QSPI_DQ2PEN */
AnnaBridge 170:e95d10626187 1134 #define _QSPI_ROUTEPEN_DQ2PEN_MASK 0x80UL /**< Bit mask for QSPI_DQ2PEN */
AnnaBridge 170:e95d10626187 1135 #define _QSPI_ROUTEPEN_DQ2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1136 #define QSPI_ROUTEPEN_DQ2PEN_DEFAULT (_QSPI_ROUTEPEN_DQ2PEN_DEFAULT << 7) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1137 #define QSPI_ROUTEPEN_DQ3PEN (0x1UL << 8) /**< DQ3 Pin Enable */
AnnaBridge 170:e95d10626187 1138 #define _QSPI_ROUTEPEN_DQ3PEN_SHIFT 8 /**< Shift value for QSPI_DQ3PEN */
AnnaBridge 170:e95d10626187 1139 #define _QSPI_ROUTEPEN_DQ3PEN_MASK 0x100UL /**< Bit mask for QSPI_DQ3PEN */
AnnaBridge 170:e95d10626187 1140 #define _QSPI_ROUTEPEN_DQ3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1141 #define QSPI_ROUTEPEN_DQ3PEN_DEFAULT (_QSPI_ROUTEPEN_DQ3PEN_DEFAULT << 8) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1142 #define QSPI_ROUTEPEN_DQ4PEN (0x1UL << 9) /**< DQ4 Pin Enable */
AnnaBridge 170:e95d10626187 1143 #define _QSPI_ROUTEPEN_DQ4PEN_SHIFT 9 /**< Shift value for QSPI_DQ4PEN */
AnnaBridge 170:e95d10626187 1144 #define _QSPI_ROUTEPEN_DQ4PEN_MASK 0x200UL /**< Bit mask for QSPI_DQ4PEN */
AnnaBridge 170:e95d10626187 1145 #define _QSPI_ROUTEPEN_DQ4PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1146 #define QSPI_ROUTEPEN_DQ4PEN_DEFAULT (_QSPI_ROUTEPEN_DQ4PEN_DEFAULT << 9) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1147 #define QSPI_ROUTEPEN_DQ5PEN (0x1UL << 10) /**< DQ5 Pin Enable */
AnnaBridge 170:e95d10626187 1148 #define _QSPI_ROUTEPEN_DQ5PEN_SHIFT 10 /**< Shift value for QSPI_DQ5PEN */
AnnaBridge 170:e95d10626187 1149 #define _QSPI_ROUTEPEN_DQ5PEN_MASK 0x400UL /**< Bit mask for QSPI_DQ5PEN */
AnnaBridge 170:e95d10626187 1150 #define _QSPI_ROUTEPEN_DQ5PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1151 #define QSPI_ROUTEPEN_DQ5PEN_DEFAULT (_QSPI_ROUTEPEN_DQ5PEN_DEFAULT << 10) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1152 #define QSPI_ROUTEPEN_DQ6PEN (0x1UL << 11) /**< DQ6 Pin Enable */
AnnaBridge 170:e95d10626187 1153 #define _QSPI_ROUTEPEN_DQ6PEN_SHIFT 11 /**< Shift value for QSPI_DQ6PEN */
AnnaBridge 170:e95d10626187 1154 #define _QSPI_ROUTEPEN_DQ6PEN_MASK 0x800UL /**< Bit mask for QSPI_DQ6PEN */
AnnaBridge 170:e95d10626187 1155 #define _QSPI_ROUTEPEN_DQ6PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1156 #define QSPI_ROUTEPEN_DQ6PEN_DEFAULT (_QSPI_ROUTEPEN_DQ6PEN_DEFAULT << 11) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1157 #define QSPI_ROUTEPEN_DQ7PEN (0x1UL << 12) /**< DQ7 Pin Enable */
AnnaBridge 170:e95d10626187 1158 #define _QSPI_ROUTEPEN_DQ7PEN_SHIFT 12 /**< Shift value for QSPI_DQ7PEN */
AnnaBridge 170:e95d10626187 1159 #define _QSPI_ROUTEPEN_DQ7PEN_MASK 0x1000UL /**< Bit mask for QSPI_DQ7PEN */
AnnaBridge 170:e95d10626187 1160 #define _QSPI_ROUTEPEN_DQ7PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1161 #define QSPI_ROUTEPEN_DQ7PEN_DEFAULT (_QSPI_ROUTEPEN_DQ7PEN_DEFAULT << 12) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1162 #define QSPI_ROUTEPEN_DQSPEN (0x1UL << 13) /**< DQS Pin Enable */
AnnaBridge 170:e95d10626187 1163 #define _QSPI_ROUTEPEN_DQSPEN_SHIFT 13 /**< Shift value for QSPI_DQSPEN */
AnnaBridge 170:e95d10626187 1164 #define _QSPI_ROUTEPEN_DQSPEN_MASK 0x2000UL /**< Bit mask for QSPI_DQSPEN */
AnnaBridge 170:e95d10626187 1165 #define _QSPI_ROUTEPEN_DQSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1166 #define QSPI_ROUTEPEN_DQSPEN_DEFAULT (_QSPI_ROUTEPEN_DQSPEN_DEFAULT << 13) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1167 #define QSPI_ROUTEPEN_SCLKINPEN (0x1UL << 14) /**< SCLKIN Pin Enable */
AnnaBridge 170:e95d10626187 1168 #define _QSPI_ROUTEPEN_SCLKINPEN_SHIFT 14 /**< Shift value for QSPI_SCLKINPEN */
AnnaBridge 170:e95d10626187 1169 #define _QSPI_ROUTEPEN_SCLKINPEN_MASK 0x4000UL /**< Bit mask for QSPI_SCLKINPEN */
AnnaBridge 170:e95d10626187 1170 #define _QSPI_ROUTEPEN_SCLKINPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1171 #define QSPI_ROUTEPEN_SCLKINPEN_DEFAULT (_QSPI_ROUTEPEN_SCLKINPEN_DEFAULT << 14) /**< Shifted mode DEFAULT for QSPI_ROUTEPEN */
AnnaBridge 170:e95d10626187 1172
AnnaBridge 170:e95d10626187 1173 /* Bit fields for QSPI ROUTELOC0 */
AnnaBridge 170:e95d10626187 1174 #define _QSPI_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for QSPI_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1175 #define _QSPI_ROUTELOC0_MASK 0x00000003UL /**< Mask for QSPI_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1176 #define _QSPI_ROUTELOC0_QSPILOC_SHIFT 0 /**< Shift value for QSPI_QSPILOC */
AnnaBridge 170:e95d10626187 1177 #define _QSPI_ROUTELOC0_QSPILOC_MASK 0x3UL /**< Bit mask for QSPI_QSPILOC */
AnnaBridge 170:e95d10626187 1178 #define _QSPI_ROUTELOC0_QSPILOC_LOC0 0x00000000UL /**< Mode LOC0 for QSPI_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1179 #define _QSPI_ROUTELOC0_QSPILOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for QSPI_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1180 #define _QSPI_ROUTELOC0_QSPILOC_LOC1 0x00000001UL /**< Mode LOC1 for QSPI_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1181 #define _QSPI_ROUTELOC0_QSPILOC_LOC2 0x00000002UL /**< Mode LOC2 for QSPI_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1182 #define QSPI_ROUTELOC0_QSPILOC_LOC0 (_QSPI_ROUTELOC0_QSPILOC_LOC0 << 0) /**< Shifted mode LOC0 for QSPI_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1183 #define QSPI_ROUTELOC0_QSPILOC_DEFAULT (_QSPI_ROUTELOC0_QSPILOC_DEFAULT << 0) /**< Shifted mode DEFAULT for QSPI_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1184 #define QSPI_ROUTELOC0_QSPILOC_LOC1 (_QSPI_ROUTELOC0_QSPILOC_LOC1 << 0) /**< Shifted mode LOC1 for QSPI_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1185 #define QSPI_ROUTELOC0_QSPILOC_LOC2 (_QSPI_ROUTELOC0_QSPILOC_LOC2 << 0) /**< Shifted mode LOC2 for QSPI_ROUTELOC0 */
AnnaBridge 170:e95d10626187 1186
AnnaBridge 170:e95d10626187 1187 /** @} */
AnnaBridge 170:e95d10626187 1188 /** @} End of group EFM32GG11B_QSPI */
AnnaBridge 170:e95d10626187 1189 /** @} End of group Parts */