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TARGET_EFM32GG11_STK3701/TOOLCHAIN_ARM_STD/efm32gg11b_emu.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 170:e95d10626187 1 /**************************************************************************//**
AnnaBridge 170:e95d10626187 2 * @file efm32gg11b_emu.h
AnnaBridge 170:e95d10626187 3 * @brief EFM32GG11B_EMU register and bit field definitions
AnnaBridge 170:e95d10626187 4 * @version 5.3.2
AnnaBridge 170:e95d10626187 5 ******************************************************************************
AnnaBridge 170:e95d10626187 6 * # License
AnnaBridge 170:e95d10626187 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 170:e95d10626187 8 ******************************************************************************
AnnaBridge 170:e95d10626187 9 *
AnnaBridge 170:e95d10626187 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 170:e95d10626187 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 170:e95d10626187 12 * freely, subject to the following restrictions:
AnnaBridge 170:e95d10626187 13 *
AnnaBridge 170:e95d10626187 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 170:e95d10626187 15 * claim that you wrote the original software.@n
AnnaBridge 170:e95d10626187 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 170:e95d10626187 17 * misrepresented as being the original software.@n
AnnaBridge 170:e95d10626187 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 170:e95d10626187 19 *
AnnaBridge 170:e95d10626187 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 170:e95d10626187 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 170:e95d10626187 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 170:e95d10626187 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 170:e95d10626187 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 170:e95d10626187 25 * infringement of any proprietary rights of a third party.
AnnaBridge 170:e95d10626187 26 *
AnnaBridge 170:e95d10626187 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 170:e95d10626187 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 170:e95d10626187 29 * any third party, arising from your use of this Software.
AnnaBridge 170:e95d10626187 30 *
AnnaBridge 170:e95d10626187 31 *****************************************************************************/
AnnaBridge 170:e95d10626187 32
AnnaBridge 170:e95d10626187 33 #if defined(__ICCARM__)
AnnaBridge 170:e95d10626187 34 #pragma system_include /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 35 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 170:e95d10626187 36 #pragma clang system_header /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 37 #endif
AnnaBridge 170:e95d10626187 38
AnnaBridge 170:e95d10626187 39 /**************************************************************************//**
AnnaBridge 170:e95d10626187 40 * @addtogroup Parts
AnnaBridge 170:e95d10626187 41 * @{
AnnaBridge 170:e95d10626187 42 ******************************************************************************/
AnnaBridge 170:e95d10626187 43 /**************************************************************************//**
AnnaBridge 170:e95d10626187 44 * @defgroup EFM32GG11B_EMU EMU
AnnaBridge 170:e95d10626187 45 * @{
AnnaBridge 170:e95d10626187 46 * @brief EFM32GG11B_EMU Register Declaration
AnnaBridge 170:e95d10626187 47 *****************************************************************************/
AnnaBridge 170:e95d10626187 48 /** EMU Register Declaration */
AnnaBridge 170:e95d10626187 49 typedef struct {
AnnaBridge 170:e95d10626187 50 __IOM uint32_t CTRL; /**< Control Register */
AnnaBridge 170:e95d10626187 51 __IM uint32_t STATUS; /**< Status Register */
AnnaBridge 170:e95d10626187 52 __IOM uint32_t LOCK; /**< Configuration Lock Register */
AnnaBridge 170:e95d10626187 53 __IOM uint32_t RAM0CTRL; /**< Memory Control Register */
AnnaBridge 170:e95d10626187 54 __IOM uint32_t CMD; /**< Command Register */
AnnaBridge 170:e95d10626187 55
AnnaBridge 170:e95d10626187 56 uint32_t RESERVED0[1]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 57 __IOM uint32_t EM4CTRL; /**< EM4 Control Register */
AnnaBridge 170:e95d10626187 58 __IOM uint32_t TEMPLIMITS; /**< Temperature limits for interrupt generation */
AnnaBridge 170:e95d10626187 59 __IM uint32_t TEMP; /**< Value of last temperature measurement */
AnnaBridge 170:e95d10626187 60 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 170:e95d10626187 61 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 170:e95d10626187 62 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 170:e95d10626187 63 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 170:e95d10626187 64 __IOM uint32_t PWRLOCK; /**< Regulator and Supply Lock Register */
AnnaBridge 170:e95d10626187 65
AnnaBridge 170:e95d10626187 66 uint32_t RESERVED1[1]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 67 __IOM uint32_t PWRCTRL; /**< Power Control Register. */
AnnaBridge 170:e95d10626187 68 __IOM uint32_t DCDCCTRL; /**< DCDC Control */
AnnaBridge 170:e95d10626187 69
AnnaBridge 170:e95d10626187 70 uint32_t RESERVED2[2]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 71 __IOM uint32_t DCDCMISCCTRL; /**< DCDC Miscellaneous Control Register */
AnnaBridge 170:e95d10626187 72 __IOM uint32_t DCDCZDETCTRL; /**< DCDC Power Train NFET Zero Current Detector Control Register */
AnnaBridge 170:e95d10626187 73 __IOM uint32_t DCDCCLIMCTRL; /**< DCDC Power Train PFET Current Limiter Control Register */
AnnaBridge 170:e95d10626187 74 __IOM uint32_t DCDCLNCOMPCTRL; /**< DCDC Low Noise Compensator Control Register */
AnnaBridge 170:e95d10626187 75 __IOM uint32_t DCDCLNVCTRL; /**< DCDC Low Noise Voltage Register */
AnnaBridge 170:e95d10626187 76
AnnaBridge 170:e95d10626187 77 uint32_t RESERVED3[1]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 78 __IOM uint32_t DCDCLPVCTRL; /**< DCDC Low Power Voltage Register */
AnnaBridge 170:e95d10626187 79
AnnaBridge 170:e95d10626187 80 uint32_t RESERVED4[1]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 81 __IOM uint32_t DCDCLPCTRL; /**< DCDC Low Power Control Register */
AnnaBridge 170:e95d10626187 82 __IOM uint32_t DCDCLNFREQCTRL; /**< DCDC Low Noise Controller Frequency Control */
AnnaBridge 170:e95d10626187 83
AnnaBridge 170:e95d10626187 84 uint32_t RESERVED5[1]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 85 __IM uint32_t DCDCSYNC; /**< DCDC Read Status Register */
AnnaBridge 170:e95d10626187 86
AnnaBridge 170:e95d10626187 87 uint32_t RESERVED6[5]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 88 __IOM uint32_t VMONAVDDCTRL; /**< VMON AVDD Channel Control */
AnnaBridge 170:e95d10626187 89 __IOM uint32_t VMONALTAVDDCTRL; /**< Alternate VMON AVDD Channel Control */
AnnaBridge 170:e95d10626187 90 __IOM uint32_t VMONDVDDCTRL; /**< VMON DVDD Channel Control */
AnnaBridge 170:e95d10626187 91 __IOM uint32_t VMONIO0CTRL; /**< VMON IOVDD0 Channel Control */
AnnaBridge 170:e95d10626187 92 __IOM uint32_t VMONIO1CTRL; /**< VMON IOVDD1 Channel Control */
AnnaBridge 170:e95d10626187 93 __IOM uint32_t VMONBUVDDCTRL; /**< VMON BUVDD Channel Control */
AnnaBridge 170:e95d10626187 94
AnnaBridge 170:e95d10626187 95 uint32_t RESERVED7[3]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 96 __IOM uint32_t RAM1CTRL; /**< Memory Control Register */
AnnaBridge 170:e95d10626187 97 __IOM uint32_t RAM2CTRL; /**< Memory Control Register */
AnnaBridge 170:e95d10626187 98 __IOM uint32_t BUCTRL; /**< Backup power configuration register */
AnnaBridge 170:e95d10626187 99 uint32_t RESERVED8[2]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 100 __IOM uint32_t R5VCTRL; /**< 5V Regulator Control */
AnnaBridge 170:e95d10626187 101 __IOM uint32_t R5VADCCTRL; /**< 5V Regulator Control */
AnnaBridge 170:e95d10626187 102 __IOM uint32_t R5VOUTLEVEL; /**< 5V Regulator Voltage Select */
AnnaBridge 170:e95d10626187 103
AnnaBridge 170:e95d10626187 104 uint32_t RESERVED9[2]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 105 __IOM uint32_t R5VDETCTRL; /**< 5V Detector Enables */
AnnaBridge 170:e95d10626187 106
AnnaBridge 170:e95d10626187 107 uint32_t RESERVED10[3]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 108 __IOM uint32_t DCDCLPEM01CFG; /**< Configuration bits for low power mode to be applied during EM01, this field is only relevant if LP mode is used in EM01. */
AnnaBridge 170:e95d10626187 109 __IM uint32_t R5VSTATUS; /**< 5V Detector Status Register */
AnnaBridge 170:e95d10626187 110
AnnaBridge 170:e95d10626187 111 uint32_t RESERVED11[1]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 112 __IM uint32_t R5VSYNC; /**< 5V Read Status Register */
AnnaBridge 170:e95d10626187 113
AnnaBridge 170:e95d10626187 114 uint32_t RESERVED12[1]; /**< Reserved for future use **/
AnnaBridge 170:e95d10626187 115 __IOM uint32_t EM23PERNORETAINCMD; /**< Clears corresponding bits in EM23PERNORETAINSTATUS unlocking access to peripheral */
AnnaBridge 170:e95d10626187 116 __IM uint32_t EM23PERNORETAINSTATUS; /**< Status indicating if peripherals were powered down in EM23, subsequently locking access to it. */
AnnaBridge 170:e95d10626187 117 __IOM uint32_t EM23PERNORETAINCTRL; /**< When set corresponding peripherals may get powered down in EM23 */
AnnaBridge 170:e95d10626187 118 } EMU_TypeDef; /** @} */
AnnaBridge 170:e95d10626187 119
AnnaBridge 170:e95d10626187 120 /**************************************************************************//**
AnnaBridge 170:e95d10626187 121 * @addtogroup EFM32GG11B_EMU
AnnaBridge 170:e95d10626187 122 * @{
AnnaBridge 170:e95d10626187 123 * @defgroup EFM32GG11B_EMU_BitFields EMU Bit Fields
AnnaBridge 170:e95d10626187 124 * @{
AnnaBridge 170:e95d10626187 125 *****************************************************************************/
AnnaBridge 170:e95d10626187 126
AnnaBridge 170:e95d10626187 127 /* Bit fields for EMU CTRL */
AnnaBridge 170:e95d10626187 128 #define _EMU_CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_CTRL */
AnnaBridge 170:e95d10626187 129 #define _EMU_CTRL_MASK 0x0003031EUL /**< Mask for EMU_CTRL */
AnnaBridge 170:e95d10626187 130 #define EMU_CTRL_EM2BLOCK (0x1UL << 1) /**< Energy Mode 2 Block */
AnnaBridge 170:e95d10626187 131 #define _EMU_CTRL_EM2BLOCK_SHIFT 1 /**< Shift value for EMU_EM2BLOCK */
AnnaBridge 170:e95d10626187 132 #define _EMU_CTRL_EM2BLOCK_MASK 0x2UL /**< Bit mask for EMU_EM2BLOCK */
AnnaBridge 170:e95d10626187 133 #define _EMU_CTRL_EM2BLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
AnnaBridge 170:e95d10626187 134 #define EMU_CTRL_EM2BLOCK_DEFAULT (_EMU_CTRL_EM2BLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_CTRL */
AnnaBridge 170:e95d10626187 135 #define EMU_CTRL_EM2BODDIS (0x1UL << 2) /**< Disable BOD in EM2 */
AnnaBridge 170:e95d10626187 136 #define _EMU_CTRL_EM2BODDIS_SHIFT 2 /**< Shift value for EMU_EM2BODDIS */
AnnaBridge 170:e95d10626187 137 #define _EMU_CTRL_EM2BODDIS_MASK 0x4UL /**< Bit mask for EMU_EM2BODDIS */
AnnaBridge 170:e95d10626187 138 #define _EMU_CTRL_EM2BODDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
AnnaBridge 170:e95d10626187 139 #define EMU_CTRL_EM2BODDIS_DEFAULT (_EMU_CTRL_EM2BODDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_CTRL */
AnnaBridge 170:e95d10626187 140 #define EMU_CTRL_EM01LD (0x1UL << 3) /**< Reserved for internal use. Do not change. */
AnnaBridge 170:e95d10626187 141 #define _EMU_CTRL_EM01LD_SHIFT 3 /**< Shift value for EMU_EM01LD */
AnnaBridge 170:e95d10626187 142 #define _EMU_CTRL_EM01LD_MASK 0x8UL /**< Bit mask for EMU_EM01LD */
AnnaBridge 170:e95d10626187 143 #define _EMU_CTRL_EM01LD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
AnnaBridge 170:e95d10626187 144 #define EMU_CTRL_EM01LD_DEFAULT (_EMU_CTRL_EM01LD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_CTRL */
AnnaBridge 170:e95d10626187 145 #define EMU_CTRL_EM23VSCALEAUTOWSEN (0x1UL << 4) /**< Automatically configures Flash, Ram and Frequency to wakeup from EM2 or EM3 at low voltage */
AnnaBridge 170:e95d10626187 146 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_SHIFT 4 /**< Shift value for EMU_EM23VSCALEAUTOWSEN */
AnnaBridge 170:e95d10626187 147 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_MASK 0x10UL /**< Bit mask for EMU_EM23VSCALEAUTOWSEN */
AnnaBridge 170:e95d10626187 148 #define _EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
AnnaBridge 170:e95d10626187 149 #define EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT (_EMU_CTRL_EM23VSCALEAUTOWSEN_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CTRL */
AnnaBridge 170:e95d10626187 150 #define _EMU_CTRL_EM23VSCALE_SHIFT 8 /**< Shift value for EMU_EM23VSCALE */
AnnaBridge 170:e95d10626187 151 #define _EMU_CTRL_EM23VSCALE_MASK 0x300UL /**< Bit mask for EMU_EM23VSCALE */
AnnaBridge 170:e95d10626187 152 #define _EMU_CTRL_EM23VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
AnnaBridge 170:e95d10626187 153 #define _EMU_CTRL_EM23VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */
AnnaBridge 170:e95d10626187 154 #define _EMU_CTRL_EM23VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */
AnnaBridge 170:e95d10626187 155 #define _EMU_CTRL_EM23VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */
AnnaBridge 170:e95d10626187 156 #define EMU_CTRL_EM23VSCALE_DEFAULT (_EMU_CTRL_EM23VSCALE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_CTRL */
AnnaBridge 170:e95d10626187 157 #define EMU_CTRL_EM23VSCALE_VSCALE2 (_EMU_CTRL_EM23VSCALE_VSCALE2 << 8) /**< Shifted mode VSCALE2 for EMU_CTRL */
AnnaBridge 170:e95d10626187 158 #define EMU_CTRL_EM23VSCALE_VSCALE0 (_EMU_CTRL_EM23VSCALE_VSCALE0 << 8) /**< Shifted mode VSCALE0 for EMU_CTRL */
AnnaBridge 170:e95d10626187 159 #define EMU_CTRL_EM23VSCALE_RESV (_EMU_CTRL_EM23VSCALE_RESV << 8) /**< Shifted mode RESV for EMU_CTRL */
AnnaBridge 170:e95d10626187 160 #define _EMU_CTRL_EM4HVSCALE_SHIFT 16 /**< Shift value for EMU_EM4HVSCALE */
AnnaBridge 170:e95d10626187 161 #define _EMU_CTRL_EM4HVSCALE_MASK 0x30000UL /**< Bit mask for EMU_EM4HVSCALE */
AnnaBridge 170:e95d10626187 162 #define _EMU_CTRL_EM4HVSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CTRL */
AnnaBridge 170:e95d10626187 163 #define _EMU_CTRL_EM4HVSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_CTRL */
AnnaBridge 170:e95d10626187 164 #define _EMU_CTRL_EM4HVSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_CTRL */
AnnaBridge 170:e95d10626187 165 #define _EMU_CTRL_EM4HVSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_CTRL */
AnnaBridge 170:e95d10626187 166 #define EMU_CTRL_EM4HVSCALE_DEFAULT (_EMU_CTRL_EM4HVSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_CTRL */
AnnaBridge 170:e95d10626187 167 #define EMU_CTRL_EM4HVSCALE_VSCALE2 (_EMU_CTRL_EM4HVSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_CTRL */
AnnaBridge 170:e95d10626187 168 #define EMU_CTRL_EM4HVSCALE_VSCALE0 (_EMU_CTRL_EM4HVSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_CTRL */
AnnaBridge 170:e95d10626187 169 #define EMU_CTRL_EM4HVSCALE_RESV (_EMU_CTRL_EM4HVSCALE_RESV << 16) /**< Shifted mode RESV for EMU_CTRL */
AnnaBridge 170:e95d10626187 170
AnnaBridge 170:e95d10626187 171 /* Bit fields for EMU STATUS */
AnnaBridge 170:e95d10626187 172 #define _EMU_STATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_STATUS */
AnnaBridge 170:e95d10626187 173 #define _EMU_STATUS_MASK 0x041710BFUL /**< Mask for EMU_STATUS */
AnnaBridge 170:e95d10626187 174 #define EMU_STATUS_VMONRDY (0x1UL << 0) /**< VMON ready */
AnnaBridge 170:e95d10626187 175 #define _EMU_STATUS_VMONRDY_SHIFT 0 /**< Shift value for EMU_VMONRDY */
AnnaBridge 170:e95d10626187 176 #define _EMU_STATUS_VMONRDY_MASK 0x1UL /**< Bit mask for EMU_VMONRDY */
AnnaBridge 170:e95d10626187 177 #define _EMU_STATUS_VMONRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 178 #define EMU_STATUS_VMONRDY_DEFAULT (_EMU_STATUS_VMONRDY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 179 #define EMU_STATUS_VMONAVDD (0x1UL << 1) /**< VMON AVDD Channel. */
AnnaBridge 170:e95d10626187 180 #define _EMU_STATUS_VMONAVDD_SHIFT 1 /**< Shift value for EMU_VMONAVDD */
AnnaBridge 170:e95d10626187 181 #define _EMU_STATUS_VMONAVDD_MASK 0x2UL /**< Bit mask for EMU_VMONAVDD */
AnnaBridge 170:e95d10626187 182 #define _EMU_STATUS_VMONAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 183 #define EMU_STATUS_VMONAVDD_DEFAULT (_EMU_STATUS_VMONAVDD_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 184 #define EMU_STATUS_VMONALTAVDD (0x1UL << 2) /**< Alternate VMON AVDD Channel. */
AnnaBridge 170:e95d10626187 185 #define _EMU_STATUS_VMONALTAVDD_SHIFT 2 /**< Shift value for EMU_VMONALTAVDD */
AnnaBridge 170:e95d10626187 186 #define _EMU_STATUS_VMONALTAVDD_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDD */
AnnaBridge 170:e95d10626187 187 #define _EMU_STATUS_VMONALTAVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 188 #define EMU_STATUS_VMONALTAVDD_DEFAULT (_EMU_STATUS_VMONALTAVDD_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 189 #define EMU_STATUS_VMONDVDD (0x1UL << 3) /**< VMON DVDD Channel. */
AnnaBridge 170:e95d10626187 190 #define _EMU_STATUS_VMONDVDD_SHIFT 3 /**< Shift value for EMU_VMONDVDD */
AnnaBridge 170:e95d10626187 191 #define _EMU_STATUS_VMONDVDD_MASK 0x8UL /**< Bit mask for EMU_VMONDVDD */
AnnaBridge 170:e95d10626187 192 #define _EMU_STATUS_VMONDVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 193 #define EMU_STATUS_VMONDVDD_DEFAULT (_EMU_STATUS_VMONDVDD_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 194 #define EMU_STATUS_VMONIO0 (0x1UL << 4) /**< VMON IOVDD0 Channel. */
AnnaBridge 170:e95d10626187 195 #define _EMU_STATUS_VMONIO0_SHIFT 4 /**< Shift value for EMU_VMONIO0 */
AnnaBridge 170:e95d10626187 196 #define _EMU_STATUS_VMONIO0_MASK 0x10UL /**< Bit mask for EMU_VMONIO0 */
AnnaBridge 170:e95d10626187 197 #define _EMU_STATUS_VMONIO0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 198 #define EMU_STATUS_VMONIO0_DEFAULT (_EMU_STATUS_VMONIO0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 199 #define EMU_STATUS_VMONIO1 (0x1UL << 5) /**< VMON IOVDD1 Channel. */
AnnaBridge 170:e95d10626187 200 #define _EMU_STATUS_VMONIO1_SHIFT 5 /**< Shift value for EMU_VMONIO1 */
AnnaBridge 170:e95d10626187 201 #define _EMU_STATUS_VMONIO1_MASK 0x20UL /**< Bit mask for EMU_VMONIO1 */
AnnaBridge 170:e95d10626187 202 #define _EMU_STATUS_VMONIO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 203 #define EMU_STATUS_VMONIO1_DEFAULT (_EMU_STATUS_VMONIO1_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 204 #define EMU_STATUS_VMONBUVDD (0x1UL << 7) /**< VMON BUVDD Channel. */
AnnaBridge 170:e95d10626187 205 #define _EMU_STATUS_VMONBUVDD_SHIFT 7 /**< Shift value for EMU_VMONBUVDD */
AnnaBridge 170:e95d10626187 206 #define _EMU_STATUS_VMONBUVDD_MASK 0x80UL /**< Bit mask for EMU_VMONBUVDD */
AnnaBridge 170:e95d10626187 207 #define _EMU_STATUS_VMONBUVDD_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 208 #define EMU_STATUS_VMONBUVDD_DEFAULT (_EMU_STATUS_VMONBUVDD_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 209 #define EMU_STATUS_BURDY (0x1UL << 12) /**< Backup Mode Ready. */
AnnaBridge 170:e95d10626187 210 #define _EMU_STATUS_BURDY_SHIFT 12 /**< Shift value for EMU_BURDY */
AnnaBridge 170:e95d10626187 211 #define _EMU_STATUS_BURDY_MASK 0x1000UL /**< Bit mask for EMU_BURDY */
AnnaBridge 170:e95d10626187 212 #define _EMU_STATUS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 213 #define EMU_STATUS_BURDY_DEFAULT (_EMU_STATUS_BURDY_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 214 #define _EMU_STATUS_VSCALE_SHIFT 16 /**< Shift value for EMU_VSCALE */
AnnaBridge 170:e95d10626187 215 #define _EMU_STATUS_VSCALE_MASK 0x30000UL /**< Bit mask for EMU_VSCALE */
AnnaBridge 170:e95d10626187 216 #define _EMU_STATUS_VSCALE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 217 #define _EMU_STATUS_VSCALE_VSCALE2 0x00000000UL /**< Mode VSCALE2 for EMU_STATUS */
AnnaBridge 170:e95d10626187 218 #define _EMU_STATUS_VSCALE_VSCALE0 0x00000002UL /**< Mode VSCALE0 for EMU_STATUS */
AnnaBridge 170:e95d10626187 219 #define _EMU_STATUS_VSCALE_RESV 0x00000003UL /**< Mode RESV for EMU_STATUS */
AnnaBridge 170:e95d10626187 220 #define EMU_STATUS_VSCALE_DEFAULT (_EMU_STATUS_VSCALE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 221 #define EMU_STATUS_VSCALE_VSCALE2 (_EMU_STATUS_VSCALE_VSCALE2 << 16) /**< Shifted mode VSCALE2 for EMU_STATUS */
AnnaBridge 170:e95d10626187 222 #define EMU_STATUS_VSCALE_VSCALE0 (_EMU_STATUS_VSCALE_VSCALE0 << 16) /**< Shifted mode VSCALE0 for EMU_STATUS */
AnnaBridge 170:e95d10626187 223 #define EMU_STATUS_VSCALE_RESV (_EMU_STATUS_VSCALE_RESV << 16) /**< Shifted mode RESV for EMU_STATUS */
AnnaBridge 170:e95d10626187 224 #define EMU_STATUS_VSCALEBUSY (0x1UL << 18) /**< System is busy Scaling Voltage */
AnnaBridge 170:e95d10626187 225 #define _EMU_STATUS_VSCALEBUSY_SHIFT 18 /**< Shift value for EMU_VSCALEBUSY */
AnnaBridge 170:e95d10626187 226 #define _EMU_STATUS_VSCALEBUSY_MASK 0x40000UL /**< Bit mask for EMU_VSCALEBUSY */
AnnaBridge 170:e95d10626187 227 #define _EMU_STATUS_VSCALEBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 228 #define EMU_STATUS_VSCALEBUSY_DEFAULT (_EMU_STATUS_VSCALEBUSY_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 229 #define EMU_STATUS_EM4IORET (0x1UL << 20) /**< IO Retention Status */
AnnaBridge 170:e95d10626187 230 #define _EMU_STATUS_EM4IORET_SHIFT 20 /**< Shift value for EMU_EM4IORET */
AnnaBridge 170:e95d10626187 231 #define _EMU_STATUS_EM4IORET_MASK 0x100000UL /**< Bit mask for EMU_EM4IORET */
AnnaBridge 170:e95d10626187 232 #define _EMU_STATUS_EM4IORET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 233 #define _EMU_STATUS_EM4IORET_DISABLED 0x00000000UL /**< Mode DISABLED for EMU_STATUS */
AnnaBridge 170:e95d10626187 234 #define _EMU_STATUS_EM4IORET_ENABLED 0x00000001UL /**< Mode ENABLED for EMU_STATUS */
AnnaBridge 170:e95d10626187 235 #define EMU_STATUS_EM4IORET_DEFAULT (_EMU_STATUS_EM4IORET_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 236 #define EMU_STATUS_EM4IORET_DISABLED (_EMU_STATUS_EM4IORET_DISABLED << 20) /**< Shifted mode DISABLED for EMU_STATUS */
AnnaBridge 170:e95d10626187 237 #define EMU_STATUS_EM4IORET_ENABLED (_EMU_STATUS_EM4IORET_ENABLED << 20) /**< Shifted mode ENABLED for EMU_STATUS */
AnnaBridge 170:e95d10626187 238 #define EMU_STATUS_TEMPACTIVE (0x1UL << 26) /**< Temperature Measurement Active */
AnnaBridge 170:e95d10626187 239 #define _EMU_STATUS_TEMPACTIVE_SHIFT 26 /**< Shift value for EMU_TEMPACTIVE */
AnnaBridge 170:e95d10626187 240 #define _EMU_STATUS_TEMPACTIVE_MASK 0x4000000UL /**< Bit mask for EMU_TEMPACTIVE */
AnnaBridge 170:e95d10626187 241 #define _EMU_STATUS_TEMPACTIVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 242 #define EMU_STATUS_TEMPACTIVE_DEFAULT (_EMU_STATUS_TEMPACTIVE_DEFAULT << 26) /**< Shifted mode DEFAULT for EMU_STATUS */
AnnaBridge 170:e95d10626187 243
AnnaBridge 170:e95d10626187 244 /* Bit fields for EMU LOCK */
AnnaBridge 170:e95d10626187 245 #define _EMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_LOCK */
AnnaBridge 170:e95d10626187 246 #define _EMU_LOCK_MASK 0x0000FFFFUL /**< Mask for EMU_LOCK */
AnnaBridge 170:e95d10626187 247 #define _EMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
AnnaBridge 170:e95d10626187 248 #define _EMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
AnnaBridge 170:e95d10626187 249 #define _EMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_LOCK */
AnnaBridge 170:e95d10626187 250 #define _EMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_LOCK */
AnnaBridge 170:e95d10626187 251 #define _EMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_LOCK */
AnnaBridge 170:e95d10626187 252 #define _EMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_LOCK */
AnnaBridge 170:e95d10626187 253 #define _EMU_LOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_LOCK */
AnnaBridge 170:e95d10626187 254 #define EMU_LOCK_LOCKKEY_DEFAULT (_EMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_LOCK */
AnnaBridge 170:e95d10626187 255 #define EMU_LOCK_LOCKKEY_LOCK (_EMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_LOCK */
AnnaBridge 170:e95d10626187 256 #define EMU_LOCK_LOCKKEY_UNLOCKED (_EMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_LOCK */
AnnaBridge 170:e95d10626187 257 #define EMU_LOCK_LOCKKEY_LOCKED (_EMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_LOCK */
AnnaBridge 170:e95d10626187 258 #define EMU_LOCK_LOCKKEY_UNLOCK (_EMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_LOCK */
AnnaBridge 170:e95d10626187 259
AnnaBridge 170:e95d10626187 260 /* Bit fields for EMU RAM0CTRL */
AnnaBridge 170:e95d10626187 261 #define _EMU_RAM0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 262 #define _EMU_RAM0CTRL_MASK 0x0000007FUL /**< Mask for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 263 #define _EMU_RAM0CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */
AnnaBridge 170:e95d10626187 264 #define _EMU_RAM0CTRL_RAMPOWERDOWN_MASK 0x7FUL /**< Bit mask for EMU_RAMPOWERDOWN */
AnnaBridge 170:e95d10626187 265 #define _EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 266 #define _EMU_RAM0CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 267 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 0x00000040UL /**< Mode BLK7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 268 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 0x00000060UL /**< Mode BLK6TO7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 269 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 0x00000070UL /**< Mode BLK5TO7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 270 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 0x00000078UL /**< Mode BLK4TO7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 271 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 0x0000007CUL /**< Mode BLK3TO7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 272 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 0x0000007EUL /**< Mode BLK2TO7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 273 #define _EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 0x0000007FUL /**< Mode BLK1TO7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 274 #define EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM0CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 275 #define EMU_RAM0CTRL_RAMPOWERDOWN_NONE (_EMU_RAM0CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 276 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 277 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 278 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 279 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 280 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 281 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 282 #define EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM0CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM0CTRL */
AnnaBridge 170:e95d10626187 283
AnnaBridge 170:e95d10626187 284 /* Bit fields for EMU CMD */
AnnaBridge 170:e95d10626187 285 #define _EMU_CMD_RESETVALUE 0x00000000UL /**< Default value for EMU_CMD */
AnnaBridge 170:e95d10626187 286 #define _EMU_CMD_MASK 0x00000051UL /**< Mask for EMU_CMD */
AnnaBridge 170:e95d10626187 287 #define EMU_CMD_EM4UNLATCH (0x1UL << 0) /**< EM4 Unlatch */
AnnaBridge 170:e95d10626187 288 #define _EMU_CMD_EM4UNLATCH_SHIFT 0 /**< Shift value for EMU_EM4UNLATCH */
AnnaBridge 170:e95d10626187 289 #define _EMU_CMD_EM4UNLATCH_MASK 0x1UL /**< Bit mask for EMU_EM4UNLATCH */
AnnaBridge 170:e95d10626187 290 #define _EMU_CMD_EM4UNLATCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
AnnaBridge 170:e95d10626187 291 #define EMU_CMD_EM4UNLATCH_DEFAULT (_EMU_CMD_EM4UNLATCH_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_CMD */
AnnaBridge 170:e95d10626187 292 #define EMU_CMD_EM01VSCALE0 (0x1UL << 4) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 0 */
AnnaBridge 170:e95d10626187 293 #define _EMU_CMD_EM01VSCALE0_SHIFT 4 /**< Shift value for EMU_EM01VSCALE0 */
AnnaBridge 170:e95d10626187 294 #define _EMU_CMD_EM01VSCALE0_MASK 0x10UL /**< Bit mask for EMU_EM01VSCALE0 */
AnnaBridge 170:e95d10626187 295 #define _EMU_CMD_EM01VSCALE0_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
AnnaBridge 170:e95d10626187 296 #define EMU_CMD_EM01VSCALE0_DEFAULT (_EMU_CMD_EM01VSCALE0_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_CMD */
AnnaBridge 170:e95d10626187 297 #define EMU_CMD_EM01VSCALE2 (0x1UL << 6) /**< EM01 Voltage Scale Command to scale to Voltage Scale Level 2 */
AnnaBridge 170:e95d10626187 298 #define _EMU_CMD_EM01VSCALE2_SHIFT 6 /**< Shift value for EMU_EM01VSCALE2 */
AnnaBridge 170:e95d10626187 299 #define _EMU_CMD_EM01VSCALE2_MASK 0x40UL /**< Bit mask for EMU_EM01VSCALE2 */
AnnaBridge 170:e95d10626187 300 #define _EMU_CMD_EM01VSCALE2_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_CMD */
AnnaBridge 170:e95d10626187 301 #define EMU_CMD_EM01VSCALE2_DEFAULT (_EMU_CMD_EM01VSCALE2_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_CMD */
AnnaBridge 170:e95d10626187 302
AnnaBridge 170:e95d10626187 303 /* Bit fields for EMU EM4CTRL */
AnnaBridge 170:e95d10626187 304 #define _EMU_EM4CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 305 #define _EMU_EM4CTRL_MASK 0x0003003FUL /**< Mask for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 306 #define EMU_EM4CTRL_EM4STATE (0x1UL << 0) /**< Energy Mode 4 State */
AnnaBridge 170:e95d10626187 307 #define _EMU_EM4CTRL_EM4STATE_SHIFT 0 /**< Shift value for EMU_EM4STATE */
AnnaBridge 170:e95d10626187 308 #define _EMU_EM4CTRL_EM4STATE_MASK 0x1UL /**< Bit mask for EMU_EM4STATE */
AnnaBridge 170:e95d10626187 309 #define _EMU_EM4CTRL_EM4STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 310 #define _EMU_EM4CTRL_EM4STATE_EM4S 0x00000000UL /**< Mode EM4S for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 311 #define _EMU_EM4CTRL_EM4STATE_EM4H 0x00000001UL /**< Mode EM4H for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 312 #define EMU_EM4CTRL_EM4STATE_DEFAULT (_EMU_EM4CTRL_EM4STATE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 313 #define EMU_EM4CTRL_EM4STATE_EM4S (_EMU_EM4CTRL_EM4STATE_EM4S << 0) /**< Shifted mode EM4S for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 314 #define EMU_EM4CTRL_EM4STATE_EM4H (_EMU_EM4CTRL_EM4STATE_EM4H << 0) /**< Shifted mode EM4H for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 315 #define EMU_EM4CTRL_RETAINLFRCO (0x1UL << 1) /**< LFRCO Retain during EM4 */
AnnaBridge 170:e95d10626187 316 #define _EMU_EM4CTRL_RETAINLFRCO_SHIFT 1 /**< Shift value for EMU_RETAINLFRCO */
AnnaBridge 170:e95d10626187 317 #define _EMU_EM4CTRL_RETAINLFRCO_MASK 0x2UL /**< Bit mask for EMU_RETAINLFRCO */
AnnaBridge 170:e95d10626187 318 #define _EMU_EM4CTRL_RETAINLFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 319 #define EMU_EM4CTRL_RETAINLFRCO_DEFAULT (_EMU_EM4CTRL_RETAINLFRCO_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 320 #define EMU_EM4CTRL_RETAINLFXO (0x1UL << 2) /**< LFXO Retain during EM4 */
AnnaBridge 170:e95d10626187 321 #define _EMU_EM4CTRL_RETAINLFXO_SHIFT 2 /**< Shift value for EMU_RETAINLFXO */
AnnaBridge 170:e95d10626187 322 #define _EMU_EM4CTRL_RETAINLFXO_MASK 0x4UL /**< Bit mask for EMU_RETAINLFXO */
AnnaBridge 170:e95d10626187 323 #define _EMU_EM4CTRL_RETAINLFXO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 324 #define EMU_EM4CTRL_RETAINLFXO_DEFAULT (_EMU_EM4CTRL_RETAINLFXO_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 325 #define EMU_EM4CTRL_RETAINULFRCO (0x1UL << 3) /**< ULFRCO Retain during EM4S */
AnnaBridge 170:e95d10626187 326 #define _EMU_EM4CTRL_RETAINULFRCO_SHIFT 3 /**< Shift value for EMU_RETAINULFRCO */
AnnaBridge 170:e95d10626187 327 #define _EMU_EM4CTRL_RETAINULFRCO_MASK 0x8UL /**< Bit mask for EMU_RETAINULFRCO */
AnnaBridge 170:e95d10626187 328 #define _EMU_EM4CTRL_RETAINULFRCO_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 329 #define EMU_EM4CTRL_RETAINULFRCO_DEFAULT (_EMU_EM4CTRL_RETAINULFRCO_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 330 #define _EMU_EM4CTRL_EM4IORETMODE_SHIFT 4 /**< Shift value for EMU_EM4IORETMODE */
AnnaBridge 170:e95d10626187 331 #define _EMU_EM4CTRL_EM4IORETMODE_MASK 0x30UL /**< Bit mask for EMU_EM4IORETMODE */
AnnaBridge 170:e95d10626187 332 #define _EMU_EM4CTRL_EM4IORETMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 333 #define _EMU_EM4CTRL_EM4IORETMODE_DISABLE 0x00000000UL /**< Mode DISABLE for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 334 #define _EMU_EM4CTRL_EM4IORETMODE_EM4EXIT 0x00000001UL /**< Mode EM4EXIT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 335 #define _EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH 0x00000002UL /**< Mode SWUNLATCH for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 336 #define EMU_EM4CTRL_EM4IORETMODE_DEFAULT (_EMU_EM4CTRL_EM4IORETMODE_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 337 #define EMU_EM4CTRL_EM4IORETMODE_DISABLE (_EMU_EM4CTRL_EM4IORETMODE_DISABLE << 4) /**< Shifted mode DISABLE for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 338 #define EMU_EM4CTRL_EM4IORETMODE_EM4EXIT (_EMU_EM4CTRL_EM4IORETMODE_EM4EXIT << 4) /**< Shifted mode EM4EXIT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 339 #define EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH (_EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH << 4) /**< Shifted mode SWUNLATCH for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 340 #define _EMU_EM4CTRL_EM4ENTRY_SHIFT 16 /**< Shift value for EMU_EM4ENTRY */
AnnaBridge 170:e95d10626187 341 #define _EMU_EM4CTRL_EM4ENTRY_MASK 0x30000UL /**< Bit mask for EMU_EM4ENTRY */
AnnaBridge 170:e95d10626187 342 #define _EMU_EM4CTRL_EM4ENTRY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 343 #define EMU_EM4CTRL_EM4ENTRY_DEFAULT (_EMU_EM4CTRL_EM4ENTRY_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM4CTRL */
AnnaBridge 170:e95d10626187 344
AnnaBridge 170:e95d10626187 345 /* Bit fields for EMU TEMPLIMITS */
AnnaBridge 170:e95d10626187 346 #define _EMU_TEMPLIMITS_RESETVALUE 0x0000FF00UL /**< Default value for EMU_TEMPLIMITS */
AnnaBridge 170:e95d10626187 347 #define _EMU_TEMPLIMITS_MASK 0x0001FFFFUL /**< Mask for EMU_TEMPLIMITS */
AnnaBridge 170:e95d10626187 348 #define _EMU_TEMPLIMITS_TEMPLOW_SHIFT 0 /**< Shift value for EMU_TEMPLOW */
AnnaBridge 170:e95d10626187 349 #define _EMU_TEMPLIMITS_TEMPLOW_MASK 0xFFUL /**< Bit mask for EMU_TEMPLOW */
AnnaBridge 170:e95d10626187 350 #define _EMU_TEMPLIMITS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
AnnaBridge 170:e95d10626187 351 #define EMU_TEMPLIMITS_TEMPLOW_DEFAULT (_EMU_TEMPLIMITS_TEMPLOW_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
AnnaBridge 170:e95d10626187 352 #define _EMU_TEMPLIMITS_TEMPHIGH_SHIFT 8 /**< Shift value for EMU_TEMPHIGH */
AnnaBridge 170:e95d10626187 353 #define _EMU_TEMPLIMITS_TEMPHIGH_MASK 0xFF00UL /**< Bit mask for EMU_TEMPHIGH */
AnnaBridge 170:e95d10626187 354 #define _EMU_TEMPLIMITS_TEMPHIGH_DEFAULT 0x000000FFUL /**< Mode DEFAULT for EMU_TEMPLIMITS */
AnnaBridge 170:e95d10626187 355 #define EMU_TEMPLIMITS_TEMPHIGH_DEFAULT (_EMU_TEMPLIMITS_TEMPHIGH_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
AnnaBridge 170:e95d10626187 356 #define EMU_TEMPLIMITS_EM4WUEN (0x1UL << 16) /**< Enable EM4 Wakeup due to low/high temperature */
AnnaBridge 170:e95d10626187 357 #define _EMU_TEMPLIMITS_EM4WUEN_SHIFT 16 /**< Shift value for EMU_EM4WUEN */
AnnaBridge 170:e95d10626187 358 #define _EMU_TEMPLIMITS_EM4WUEN_MASK 0x10000UL /**< Bit mask for EMU_EM4WUEN */
AnnaBridge 170:e95d10626187 359 #define _EMU_TEMPLIMITS_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMPLIMITS */
AnnaBridge 170:e95d10626187 360 #define EMU_TEMPLIMITS_EM4WUEN_DEFAULT (_EMU_TEMPLIMITS_EM4WUEN_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_TEMPLIMITS */
AnnaBridge 170:e95d10626187 361
AnnaBridge 170:e95d10626187 362 /* Bit fields for EMU TEMP */
AnnaBridge 170:e95d10626187 363 #define _EMU_TEMP_RESETVALUE 0x00000000UL /**< Default value for EMU_TEMP */
AnnaBridge 170:e95d10626187 364 #define _EMU_TEMP_MASK 0x000000FFUL /**< Mask for EMU_TEMP */
AnnaBridge 170:e95d10626187 365 #define _EMU_TEMP_TEMP_SHIFT 0 /**< Shift value for EMU_TEMP */
AnnaBridge 170:e95d10626187 366 #define _EMU_TEMP_TEMP_MASK 0xFFUL /**< Bit mask for EMU_TEMP */
AnnaBridge 170:e95d10626187 367 #define _EMU_TEMP_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_TEMP */
AnnaBridge 170:e95d10626187 368 #define EMU_TEMP_TEMP_DEFAULT (_EMU_TEMP_TEMP_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_TEMP */
AnnaBridge 170:e95d10626187 369
AnnaBridge 170:e95d10626187 370 /* Bit fields for EMU IF */
AnnaBridge 170:e95d10626187 371 #define _EMU_IF_RESETVALUE 0x00000000UL /**< Default value for EMU_IF */
AnnaBridge 170:e95d10626187 372 #define _EMU_IF_MASK 0xE3DF37FFUL /**< Mask for EMU_IF */
AnnaBridge 170:e95d10626187 373 #define EMU_IF_VMONAVDDFALL (0x1UL << 0) /**< VMON AVDD Channel Fall */
AnnaBridge 170:e95d10626187 374 #define _EMU_IF_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
AnnaBridge 170:e95d10626187 375 #define _EMU_IF_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
AnnaBridge 170:e95d10626187 376 #define _EMU_IF_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 377 #define EMU_IF_VMONAVDDFALL_DEFAULT (_EMU_IF_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 378 #define EMU_IF_VMONAVDDRISE (0x1UL << 1) /**< VMON AVDD Channel Rise */
AnnaBridge 170:e95d10626187 379 #define _EMU_IF_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
AnnaBridge 170:e95d10626187 380 #define _EMU_IF_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
AnnaBridge 170:e95d10626187 381 #define _EMU_IF_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 382 #define EMU_IF_VMONAVDDRISE_DEFAULT (_EMU_IF_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 383 #define EMU_IF_VMONALTAVDDFALL (0x1UL << 2) /**< Alternate VMON AVDD Channel Fall */
AnnaBridge 170:e95d10626187 384 #define _EMU_IF_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
AnnaBridge 170:e95d10626187 385 #define _EMU_IF_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
AnnaBridge 170:e95d10626187 386 #define _EMU_IF_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 387 #define EMU_IF_VMONALTAVDDFALL_DEFAULT (_EMU_IF_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 388 #define EMU_IF_VMONALTAVDDRISE (0x1UL << 3) /**< Alternate VMON AVDD Channel Rise */
AnnaBridge 170:e95d10626187 389 #define _EMU_IF_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
AnnaBridge 170:e95d10626187 390 #define _EMU_IF_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
AnnaBridge 170:e95d10626187 391 #define _EMU_IF_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 392 #define EMU_IF_VMONALTAVDDRISE_DEFAULT (_EMU_IF_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 393 #define EMU_IF_VMONDVDDFALL (0x1UL << 4) /**< VMON DVDD Channel Fall */
AnnaBridge 170:e95d10626187 394 #define _EMU_IF_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
AnnaBridge 170:e95d10626187 395 #define _EMU_IF_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
AnnaBridge 170:e95d10626187 396 #define _EMU_IF_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 397 #define EMU_IF_VMONDVDDFALL_DEFAULT (_EMU_IF_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 398 #define EMU_IF_VMONDVDDRISE (0x1UL << 5) /**< VMON DVDD Channel Rise */
AnnaBridge 170:e95d10626187 399 #define _EMU_IF_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
AnnaBridge 170:e95d10626187 400 #define _EMU_IF_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
AnnaBridge 170:e95d10626187 401 #define _EMU_IF_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 402 #define EMU_IF_VMONDVDDRISE_DEFAULT (_EMU_IF_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 403 #define EMU_IF_VMONIO0FALL (0x1UL << 6) /**< VMON IOVDD0 Channel Fall */
AnnaBridge 170:e95d10626187 404 #define _EMU_IF_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
AnnaBridge 170:e95d10626187 405 #define _EMU_IF_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
AnnaBridge 170:e95d10626187 406 #define _EMU_IF_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 407 #define EMU_IF_VMONIO0FALL_DEFAULT (_EMU_IF_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 408 #define EMU_IF_VMONIO0RISE (0x1UL << 7) /**< VMON IOVDD0 Channel Rise */
AnnaBridge 170:e95d10626187 409 #define _EMU_IF_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
AnnaBridge 170:e95d10626187 410 #define _EMU_IF_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
AnnaBridge 170:e95d10626187 411 #define _EMU_IF_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 412 #define EMU_IF_VMONIO0RISE_DEFAULT (_EMU_IF_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 413 #define EMU_IF_VMONIO1FALL (0x1UL << 8) /**< VMON IOVDD1 Channel Fall */
AnnaBridge 170:e95d10626187 414 #define _EMU_IF_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */
AnnaBridge 170:e95d10626187 415 #define _EMU_IF_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */
AnnaBridge 170:e95d10626187 416 #define _EMU_IF_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 417 #define EMU_IF_VMONIO1FALL_DEFAULT (_EMU_IF_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 418 #define EMU_IF_VMONIO1RISE (0x1UL << 9) /**< VMON IOVDD1 Channel Rise */
AnnaBridge 170:e95d10626187 419 #define _EMU_IF_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */
AnnaBridge 170:e95d10626187 420 #define _EMU_IF_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */
AnnaBridge 170:e95d10626187 421 #define _EMU_IF_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 422 #define EMU_IF_VMONIO1RISE_DEFAULT (_EMU_IF_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 423 #define EMU_IF_R5VREADY (0x1UL << 10) /**< 5V regulator is ready to use. */
AnnaBridge 170:e95d10626187 424 #define _EMU_IF_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */
AnnaBridge 170:e95d10626187 425 #define _EMU_IF_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */
AnnaBridge 170:e95d10626187 426 #define _EMU_IF_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 427 #define EMU_IF_R5VREADY_DEFAULT (_EMU_IF_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 428 #define EMU_IF_VMONBUVDDFALL (0x1UL << 12) /**< VMON BACKUP Channel Fall */
AnnaBridge 170:e95d10626187 429 #define _EMU_IF_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */
AnnaBridge 170:e95d10626187 430 #define _EMU_IF_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */
AnnaBridge 170:e95d10626187 431 #define _EMU_IF_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 432 #define EMU_IF_VMONBUVDDFALL_DEFAULT (_EMU_IF_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 433 #define EMU_IF_VMONBUVDDRISE (0x1UL << 13) /**< VMON BUVDD Channel Rise */
AnnaBridge 170:e95d10626187 434 #define _EMU_IF_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */
AnnaBridge 170:e95d10626187 435 #define _EMU_IF_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */
AnnaBridge 170:e95d10626187 436 #define _EMU_IF_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 437 #define EMU_IF_VMONBUVDDRISE_DEFAULT (_EMU_IF_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 438 #define EMU_IF_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFET current limit hit */
AnnaBridge 170:e95d10626187 439 #define _EMU_IF_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 440 #define _EMU_IF_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 441 #define _EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 442 #define EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 443 #define EMU_IF_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFET current limit hit */
AnnaBridge 170:e95d10626187 444 #define _EMU_IF_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 445 #define _EMU_IF_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 446 #define _EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 447 #define EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IF_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 448 #define EMU_IF_DCDCLPRUNNING (0x1UL << 18) /**< LP mode is running */
AnnaBridge 170:e95d10626187 449 #define _EMU_IF_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
AnnaBridge 170:e95d10626187 450 #define _EMU_IF_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
AnnaBridge 170:e95d10626187 451 #define _EMU_IF_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 452 #define EMU_IF_DCDCLPRUNNING_DEFAULT (_EMU_IF_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 453 #define EMU_IF_DCDCLNRUNNING (0x1UL << 19) /**< LN mode is running */
AnnaBridge 170:e95d10626187 454 #define _EMU_IF_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
AnnaBridge 170:e95d10626187 455 #define _EMU_IF_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
AnnaBridge 170:e95d10626187 456 #define _EMU_IF_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 457 #define EMU_IF_DCDCLNRUNNING_DEFAULT (_EMU_IF_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 458 #define EMU_IF_DCDCINBYPASS (0x1UL << 20) /**< DCDC is in bypass */
AnnaBridge 170:e95d10626187 459 #define _EMU_IF_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
AnnaBridge 170:e95d10626187 460 #define _EMU_IF_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
AnnaBridge 170:e95d10626187 461 #define _EMU_IF_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 462 #define EMU_IF_DCDCINBYPASS_DEFAULT (_EMU_IF_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 463 #define EMU_IF_BURDY (0x1UL << 22) /**< Backup functionality ready Interrupt Flag */
AnnaBridge 170:e95d10626187 464 #define _EMU_IF_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */
AnnaBridge 170:e95d10626187 465 #define _EMU_IF_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */
AnnaBridge 170:e95d10626187 466 #define _EMU_IF_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 467 #define EMU_IF_BURDY_DEFAULT (_EMU_IF_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 468 #define EMU_IF_R5VVSINT (0x1UL << 23) /**< 5V regulator voltage update done. */
AnnaBridge 170:e95d10626187 469 #define _EMU_IF_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */
AnnaBridge 170:e95d10626187 470 #define _EMU_IF_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */
AnnaBridge 170:e95d10626187 471 #define _EMU_IF_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 472 #define EMU_IF_R5VVSINT_DEFAULT (_EMU_IF_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 473 #define EMU_IF_EM23WAKEUP (0x1UL << 24) /**< Wakeup IRQ from EM2 and EM3 */
AnnaBridge 170:e95d10626187 474 #define _EMU_IF_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
AnnaBridge 170:e95d10626187 475 #define _EMU_IF_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
AnnaBridge 170:e95d10626187 476 #define _EMU_IF_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 477 #define EMU_IF_EM23WAKEUP_DEFAULT (_EMU_IF_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 478 #define EMU_IF_VSCALEDONE (0x1UL << 25) /**< Voltage Scale Steps Done IRQ */
AnnaBridge 170:e95d10626187 479 #define _EMU_IF_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */
AnnaBridge 170:e95d10626187 480 #define _EMU_IF_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */
AnnaBridge 170:e95d10626187 481 #define _EMU_IF_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 482 #define EMU_IF_VSCALEDONE_DEFAULT (_EMU_IF_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 483 #define EMU_IF_TEMP (0x1UL << 29) /**< New Temperature Measurement Valid */
AnnaBridge 170:e95d10626187 484 #define _EMU_IF_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
AnnaBridge 170:e95d10626187 485 #define _EMU_IF_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
AnnaBridge 170:e95d10626187 486 #define _EMU_IF_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 487 #define EMU_IF_TEMP_DEFAULT (_EMU_IF_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 488 #define EMU_IF_TEMPLOW (0x1UL << 30) /**< Temperature Low Limit Reached */
AnnaBridge 170:e95d10626187 489 #define _EMU_IF_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
AnnaBridge 170:e95d10626187 490 #define _EMU_IF_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
AnnaBridge 170:e95d10626187 491 #define _EMU_IF_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 492 #define EMU_IF_TEMPLOW_DEFAULT (_EMU_IF_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 493 #define EMU_IF_TEMPHIGH (0x1UL << 31) /**< Temperature High Limit Reached */
AnnaBridge 170:e95d10626187 494 #define _EMU_IF_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
AnnaBridge 170:e95d10626187 495 #define _EMU_IF_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
AnnaBridge 170:e95d10626187 496 #define _EMU_IF_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 497 #define EMU_IF_TEMPHIGH_DEFAULT (_EMU_IF_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IF */
AnnaBridge 170:e95d10626187 498
AnnaBridge 170:e95d10626187 499 /* Bit fields for EMU IFS */
AnnaBridge 170:e95d10626187 500 #define _EMU_IFS_RESETVALUE 0x00000000UL /**< Default value for EMU_IFS */
AnnaBridge 170:e95d10626187 501 #define _EMU_IFS_MASK 0xE3DF37FFUL /**< Mask for EMU_IFS */
AnnaBridge 170:e95d10626187 502 #define EMU_IFS_VMONAVDDFALL (0x1UL << 0) /**< Set VMONAVDDFALL Interrupt Flag */
AnnaBridge 170:e95d10626187 503 #define _EMU_IFS_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
AnnaBridge 170:e95d10626187 504 #define _EMU_IFS_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
AnnaBridge 170:e95d10626187 505 #define _EMU_IFS_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 506 #define EMU_IFS_VMONAVDDFALL_DEFAULT (_EMU_IFS_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 507 #define EMU_IFS_VMONAVDDRISE (0x1UL << 1) /**< Set VMONAVDDRISE Interrupt Flag */
AnnaBridge 170:e95d10626187 508 #define _EMU_IFS_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
AnnaBridge 170:e95d10626187 509 #define _EMU_IFS_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
AnnaBridge 170:e95d10626187 510 #define _EMU_IFS_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 511 #define EMU_IFS_VMONAVDDRISE_DEFAULT (_EMU_IFS_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 512 #define EMU_IFS_VMONALTAVDDFALL (0x1UL << 2) /**< Set VMONALTAVDDFALL Interrupt Flag */
AnnaBridge 170:e95d10626187 513 #define _EMU_IFS_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
AnnaBridge 170:e95d10626187 514 #define _EMU_IFS_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
AnnaBridge 170:e95d10626187 515 #define _EMU_IFS_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 516 #define EMU_IFS_VMONALTAVDDFALL_DEFAULT (_EMU_IFS_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 517 #define EMU_IFS_VMONALTAVDDRISE (0x1UL << 3) /**< Set VMONALTAVDDRISE Interrupt Flag */
AnnaBridge 170:e95d10626187 518 #define _EMU_IFS_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
AnnaBridge 170:e95d10626187 519 #define _EMU_IFS_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
AnnaBridge 170:e95d10626187 520 #define _EMU_IFS_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 521 #define EMU_IFS_VMONALTAVDDRISE_DEFAULT (_EMU_IFS_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 522 #define EMU_IFS_VMONDVDDFALL (0x1UL << 4) /**< Set VMONDVDDFALL Interrupt Flag */
AnnaBridge 170:e95d10626187 523 #define _EMU_IFS_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
AnnaBridge 170:e95d10626187 524 #define _EMU_IFS_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
AnnaBridge 170:e95d10626187 525 #define _EMU_IFS_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 526 #define EMU_IFS_VMONDVDDFALL_DEFAULT (_EMU_IFS_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 527 #define EMU_IFS_VMONDVDDRISE (0x1UL << 5) /**< Set VMONDVDDRISE Interrupt Flag */
AnnaBridge 170:e95d10626187 528 #define _EMU_IFS_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
AnnaBridge 170:e95d10626187 529 #define _EMU_IFS_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
AnnaBridge 170:e95d10626187 530 #define _EMU_IFS_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 531 #define EMU_IFS_VMONDVDDRISE_DEFAULT (_EMU_IFS_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 532 #define EMU_IFS_VMONIO0FALL (0x1UL << 6) /**< Set VMONIO0FALL Interrupt Flag */
AnnaBridge 170:e95d10626187 533 #define _EMU_IFS_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
AnnaBridge 170:e95d10626187 534 #define _EMU_IFS_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
AnnaBridge 170:e95d10626187 535 #define _EMU_IFS_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 536 #define EMU_IFS_VMONIO0FALL_DEFAULT (_EMU_IFS_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 537 #define EMU_IFS_VMONIO0RISE (0x1UL << 7) /**< Set VMONIO0RISE Interrupt Flag */
AnnaBridge 170:e95d10626187 538 #define _EMU_IFS_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
AnnaBridge 170:e95d10626187 539 #define _EMU_IFS_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
AnnaBridge 170:e95d10626187 540 #define _EMU_IFS_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 541 #define EMU_IFS_VMONIO0RISE_DEFAULT (_EMU_IFS_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 542 #define EMU_IFS_VMONIO1FALL (0x1UL << 8) /**< Set VMONIO1FALL Interrupt Flag */
AnnaBridge 170:e95d10626187 543 #define _EMU_IFS_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */
AnnaBridge 170:e95d10626187 544 #define _EMU_IFS_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */
AnnaBridge 170:e95d10626187 545 #define _EMU_IFS_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 546 #define EMU_IFS_VMONIO1FALL_DEFAULT (_EMU_IFS_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 547 #define EMU_IFS_VMONIO1RISE (0x1UL << 9) /**< Set VMONIO1RISE Interrupt Flag */
AnnaBridge 170:e95d10626187 548 #define _EMU_IFS_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */
AnnaBridge 170:e95d10626187 549 #define _EMU_IFS_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */
AnnaBridge 170:e95d10626187 550 #define _EMU_IFS_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 551 #define EMU_IFS_VMONIO1RISE_DEFAULT (_EMU_IFS_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 552 #define EMU_IFS_R5VREADY (0x1UL << 10) /**< Set R5VREADY Interrupt Flag */
AnnaBridge 170:e95d10626187 553 #define _EMU_IFS_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */
AnnaBridge 170:e95d10626187 554 #define _EMU_IFS_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */
AnnaBridge 170:e95d10626187 555 #define _EMU_IFS_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 556 #define EMU_IFS_R5VREADY_DEFAULT (_EMU_IFS_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 557 #define EMU_IFS_VMONBUVDDFALL (0x1UL << 12) /**< Set VMONBUVDDFALL Interrupt Flag */
AnnaBridge 170:e95d10626187 558 #define _EMU_IFS_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */
AnnaBridge 170:e95d10626187 559 #define _EMU_IFS_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */
AnnaBridge 170:e95d10626187 560 #define _EMU_IFS_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 561 #define EMU_IFS_VMONBUVDDFALL_DEFAULT (_EMU_IFS_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 562 #define EMU_IFS_VMONBUVDDRISE (0x1UL << 13) /**< Set VMONBUVDDRISE Interrupt Flag */
AnnaBridge 170:e95d10626187 563 #define _EMU_IFS_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */
AnnaBridge 170:e95d10626187 564 #define _EMU_IFS_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */
AnnaBridge 170:e95d10626187 565 #define _EMU_IFS_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 566 #define EMU_IFS_VMONBUVDDRISE_DEFAULT (_EMU_IFS_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 567 #define EMU_IFS_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Set PFETOVERCURRENTLIMIT Interrupt Flag */
AnnaBridge 170:e95d10626187 568 #define _EMU_IFS_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 569 #define _EMU_IFS_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 570 #define _EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 571 #define EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 572 #define EMU_IFS_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Set NFETOVERCURRENTLIMIT Interrupt Flag */
AnnaBridge 170:e95d10626187 573 #define _EMU_IFS_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 574 #define _EMU_IFS_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 575 #define _EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 576 #define EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFS_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 577 #define EMU_IFS_DCDCLPRUNNING (0x1UL << 18) /**< Set DCDCLPRUNNING Interrupt Flag */
AnnaBridge 170:e95d10626187 578 #define _EMU_IFS_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
AnnaBridge 170:e95d10626187 579 #define _EMU_IFS_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
AnnaBridge 170:e95d10626187 580 #define _EMU_IFS_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 581 #define EMU_IFS_DCDCLPRUNNING_DEFAULT (_EMU_IFS_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 582 #define EMU_IFS_DCDCLNRUNNING (0x1UL << 19) /**< Set DCDCLNRUNNING Interrupt Flag */
AnnaBridge 170:e95d10626187 583 #define _EMU_IFS_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
AnnaBridge 170:e95d10626187 584 #define _EMU_IFS_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
AnnaBridge 170:e95d10626187 585 #define _EMU_IFS_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 586 #define EMU_IFS_DCDCLNRUNNING_DEFAULT (_EMU_IFS_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 587 #define EMU_IFS_DCDCINBYPASS (0x1UL << 20) /**< Set DCDCINBYPASS Interrupt Flag */
AnnaBridge 170:e95d10626187 588 #define _EMU_IFS_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
AnnaBridge 170:e95d10626187 589 #define _EMU_IFS_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
AnnaBridge 170:e95d10626187 590 #define _EMU_IFS_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 591 #define EMU_IFS_DCDCINBYPASS_DEFAULT (_EMU_IFS_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 592 #define EMU_IFS_BURDY (0x1UL << 22) /**< Set BURDY Interrupt Flag */
AnnaBridge 170:e95d10626187 593 #define _EMU_IFS_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */
AnnaBridge 170:e95d10626187 594 #define _EMU_IFS_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */
AnnaBridge 170:e95d10626187 595 #define _EMU_IFS_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 596 #define EMU_IFS_BURDY_DEFAULT (_EMU_IFS_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 597 #define EMU_IFS_R5VVSINT (0x1UL << 23) /**< Set R5VVSINT Interrupt Flag */
AnnaBridge 170:e95d10626187 598 #define _EMU_IFS_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */
AnnaBridge 170:e95d10626187 599 #define _EMU_IFS_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */
AnnaBridge 170:e95d10626187 600 #define _EMU_IFS_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 601 #define EMU_IFS_R5VVSINT_DEFAULT (_EMU_IFS_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 602 #define EMU_IFS_EM23WAKEUP (0x1UL << 24) /**< Set EM23WAKEUP Interrupt Flag */
AnnaBridge 170:e95d10626187 603 #define _EMU_IFS_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
AnnaBridge 170:e95d10626187 604 #define _EMU_IFS_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
AnnaBridge 170:e95d10626187 605 #define _EMU_IFS_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 606 #define EMU_IFS_EM23WAKEUP_DEFAULT (_EMU_IFS_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 607 #define EMU_IFS_VSCALEDONE (0x1UL << 25) /**< Set VSCALEDONE Interrupt Flag */
AnnaBridge 170:e95d10626187 608 #define _EMU_IFS_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */
AnnaBridge 170:e95d10626187 609 #define _EMU_IFS_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */
AnnaBridge 170:e95d10626187 610 #define _EMU_IFS_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 611 #define EMU_IFS_VSCALEDONE_DEFAULT (_EMU_IFS_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 612 #define EMU_IFS_TEMP (0x1UL << 29) /**< Set TEMP Interrupt Flag */
AnnaBridge 170:e95d10626187 613 #define _EMU_IFS_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
AnnaBridge 170:e95d10626187 614 #define _EMU_IFS_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
AnnaBridge 170:e95d10626187 615 #define _EMU_IFS_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 616 #define EMU_IFS_TEMP_DEFAULT (_EMU_IFS_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 617 #define EMU_IFS_TEMPLOW (0x1UL << 30) /**< Set TEMPLOW Interrupt Flag */
AnnaBridge 170:e95d10626187 618 #define _EMU_IFS_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
AnnaBridge 170:e95d10626187 619 #define _EMU_IFS_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
AnnaBridge 170:e95d10626187 620 #define _EMU_IFS_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 621 #define EMU_IFS_TEMPLOW_DEFAULT (_EMU_IFS_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 622 #define EMU_IFS_TEMPHIGH (0x1UL << 31) /**< Set TEMPHIGH Interrupt Flag */
AnnaBridge 170:e95d10626187 623 #define _EMU_IFS_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
AnnaBridge 170:e95d10626187 624 #define _EMU_IFS_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
AnnaBridge 170:e95d10626187 625 #define _EMU_IFS_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 626 #define EMU_IFS_TEMPHIGH_DEFAULT (_EMU_IFS_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFS */
AnnaBridge 170:e95d10626187 627
AnnaBridge 170:e95d10626187 628 /* Bit fields for EMU IFC */
AnnaBridge 170:e95d10626187 629 #define _EMU_IFC_RESETVALUE 0x00000000UL /**< Default value for EMU_IFC */
AnnaBridge 170:e95d10626187 630 #define _EMU_IFC_MASK 0xE3DF37FFUL /**< Mask for EMU_IFC */
AnnaBridge 170:e95d10626187 631 #define EMU_IFC_VMONAVDDFALL (0x1UL << 0) /**< Clear VMONAVDDFALL Interrupt Flag */
AnnaBridge 170:e95d10626187 632 #define _EMU_IFC_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
AnnaBridge 170:e95d10626187 633 #define _EMU_IFC_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
AnnaBridge 170:e95d10626187 634 #define _EMU_IFC_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 635 #define EMU_IFC_VMONAVDDFALL_DEFAULT (_EMU_IFC_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 636 #define EMU_IFC_VMONAVDDRISE (0x1UL << 1) /**< Clear VMONAVDDRISE Interrupt Flag */
AnnaBridge 170:e95d10626187 637 #define _EMU_IFC_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
AnnaBridge 170:e95d10626187 638 #define _EMU_IFC_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
AnnaBridge 170:e95d10626187 639 #define _EMU_IFC_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 640 #define EMU_IFC_VMONAVDDRISE_DEFAULT (_EMU_IFC_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 641 #define EMU_IFC_VMONALTAVDDFALL (0x1UL << 2) /**< Clear VMONALTAVDDFALL Interrupt Flag */
AnnaBridge 170:e95d10626187 642 #define _EMU_IFC_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
AnnaBridge 170:e95d10626187 643 #define _EMU_IFC_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
AnnaBridge 170:e95d10626187 644 #define _EMU_IFC_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 645 #define EMU_IFC_VMONALTAVDDFALL_DEFAULT (_EMU_IFC_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 646 #define EMU_IFC_VMONALTAVDDRISE (0x1UL << 3) /**< Clear VMONALTAVDDRISE Interrupt Flag */
AnnaBridge 170:e95d10626187 647 #define _EMU_IFC_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
AnnaBridge 170:e95d10626187 648 #define _EMU_IFC_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
AnnaBridge 170:e95d10626187 649 #define _EMU_IFC_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 650 #define EMU_IFC_VMONALTAVDDRISE_DEFAULT (_EMU_IFC_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 651 #define EMU_IFC_VMONDVDDFALL (0x1UL << 4) /**< Clear VMONDVDDFALL Interrupt Flag */
AnnaBridge 170:e95d10626187 652 #define _EMU_IFC_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
AnnaBridge 170:e95d10626187 653 #define _EMU_IFC_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
AnnaBridge 170:e95d10626187 654 #define _EMU_IFC_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 655 #define EMU_IFC_VMONDVDDFALL_DEFAULT (_EMU_IFC_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 656 #define EMU_IFC_VMONDVDDRISE (0x1UL << 5) /**< Clear VMONDVDDRISE Interrupt Flag */
AnnaBridge 170:e95d10626187 657 #define _EMU_IFC_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
AnnaBridge 170:e95d10626187 658 #define _EMU_IFC_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
AnnaBridge 170:e95d10626187 659 #define _EMU_IFC_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 660 #define EMU_IFC_VMONDVDDRISE_DEFAULT (_EMU_IFC_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 661 #define EMU_IFC_VMONIO0FALL (0x1UL << 6) /**< Clear VMONIO0FALL Interrupt Flag */
AnnaBridge 170:e95d10626187 662 #define _EMU_IFC_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
AnnaBridge 170:e95d10626187 663 #define _EMU_IFC_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
AnnaBridge 170:e95d10626187 664 #define _EMU_IFC_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 665 #define EMU_IFC_VMONIO0FALL_DEFAULT (_EMU_IFC_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 666 #define EMU_IFC_VMONIO0RISE (0x1UL << 7) /**< Clear VMONIO0RISE Interrupt Flag */
AnnaBridge 170:e95d10626187 667 #define _EMU_IFC_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
AnnaBridge 170:e95d10626187 668 #define _EMU_IFC_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
AnnaBridge 170:e95d10626187 669 #define _EMU_IFC_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 670 #define EMU_IFC_VMONIO0RISE_DEFAULT (_EMU_IFC_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 671 #define EMU_IFC_VMONIO1FALL (0x1UL << 8) /**< Clear VMONIO1FALL Interrupt Flag */
AnnaBridge 170:e95d10626187 672 #define _EMU_IFC_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */
AnnaBridge 170:e95d10626187 673 #define _EMU_IFC_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */
AnnaBridge 170:e95d10626187 674 #define _EMU_IFC_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 675 #define EMU_IFC_VMONIO1FALL_DEFAULT (_EMU_IFC_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 676 #define EMU_IFC_VMONIO1RISE (0x1UL << 9) /**< Clear VMONIO1RISE Interrupt Flag */
AnnaBridge 170:e95d10626187 677 #define _EMU_IFC_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */
AnnaBridge 170:e95d10626187 678 #define _EMU_IFC_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */
AnnaBridge 170:e95d10626187 679 #define _EMU_IFC_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 680 #define EMU_IFC_VMONIO1RISE_DEFAULT (_EMU_IFC_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 681 #define EMU_IFC_R5VREADY (0x1UL << 10) /**< Clear R5VREADY Interrupt Flag */
AnnaBridge 170:e95d10626187 682 #define _EMU_IFC_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */
AnnaBridge 170:e95d10626187 683 #define _EMU_IFC_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */
AnnaBridge 170:e95d10626187 684 #define _EMU_IFC_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 685 #define EMU_IFC_R5VREADY_DEFAULT (_EMU_IFC_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 686 #define EMU_IFC_VMONBUVDDFALL (0x1UL << 12) /**< Clear VMONBUVDDFALL Interrupt Flag */
AnnaBridge 170:e95d10626187 687 #define _EMU_IFC_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */
AnnaBridge 170:e95d10626187 688 #define _EMU_IFC_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */
AnnaBridge 170:e95d10626187 689 #define _EMU_IFC_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 690 #define EMU_IFC_VMONBUVDDFALL_DEFAULT (_EMU_IFC_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 691 #define EMU_IFC_VMONBUVDDRISE (0x1UL << 13) /**< Clear VMONBUVDDRISE Interrupt Flag */
AnnaBridge 170:e95d10626187 692 #define _EMU_IFC_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */
AnnaBridge 170:e95d10626187 693 #define _EMU_IFC_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */
AnnaBridge 170:e95d10626187 694 #define _EMU_IFC_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 695 #define EMU_IFC_VMONBUVDDRISE_DEFAULT (_EMU_IFC_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 696 #define EMU_IFC_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< Clear PFETOVERCURRENTLIMIT Interrupt Flag */
AnnaBridge 170:e95d10626187 697 #define _EMU_IFC_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 698 #define _EMU_IFC_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 699 #define _EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 700 #define EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 701 #define EMU_IFC_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< Clear NFETOVERCURRENTLIMIT Interrupt Flag */
AnnaBridge 170:e95d10626187 702 #define _EMU_IFC_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 703 #define _EMU_IFC_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 704 #define _EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 705 #define EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IFC_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 706 #define EMU_IFC_DCDCLPRUNNING (0x1UL << 18) /**< Clear DCDCLPRUNNING Interrupt Flag */
AnnaBridge 170:e95d10626187 707 #define _EMU_IFC_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
AnnaBridge 170:e95d10626187 708 #define _EMU_IFC_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
AnnaBridge 170:e95d10626187 709 #define _EMU_IFC_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 710 #define EMU_IFC_DCDCLPRUNNING_DEFAULT (_EMU_IFC_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 711 #define EMU_IFC_DCDCLNRUNNING (0x1UL << 19) /**< Clear DCDCLNRUNNING Interrupt Flag */
AnnaBridge 170:e95d10626187 712 #define _EMU_IFC_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
AnnaBridge 170:e95d10626187 713 #define _EMU_IFC_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
AnnaBridge 170:e95d10626187 714 #define _EMU_IFC_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 715 #define EMU_IFC_DCDCLNRUNNING_DEFAULT (_EMU_IFC_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 716 #define EMU_IFC_DCDCINBYPASS (0x1UL << 20) /**< Clear DCDCINBYPASS Interrupt Flag */
AnnaBridge 170:e95d10626187 717 #define _EMU_IFC_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
AnnaBridge 170:e95d10626187 718 #define _EMU_IFC_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
AnnaBridge 170:e95d10626187 719 #define _EMU_IFC_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 720 #define EMU_IFC_DCDCINBYPASS_DEFAULT (_EMU_IFC_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 721 #define EMU_IFC_BURDY (0x1UL << 22) /**< Clear BURDY Interrupt Flag */
AnnaBridge 170:e95d10626187 722 #define _EMU_IFC_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */
AnnaBridge 170:e95d10626187 723 #define _EMU_IFC_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */
AnnaBridge 170:e95d10626187 724 #define _EMU_IFC_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 725 #define EMU_IFC_BURDY_DEFAULT (_EMU_IFC_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 726 #define EMU_IFC_R5VVSINT (0x1UL << 23) /**< Clear R5VVSINT Interrupt Flag */
AnnaBridge 170:e95d10626187 727 #define _EMU_IFC_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */
AnnaBridge 170:e95d10626187 728 #define _EMU_IFC_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */
AnnaBridge 170:e95d10626187 729 #define _EMU_IFC_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 730 #define EMU_IFC_R5VVSINT_DEFAULT (_EMU_IFC_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 731 #define EMU_IFC_EM23WAKEUP (0x1UL << 24) /**< Clear EM23WAKEUP Interrupt Flag */
AnnaBridge 170:e95d10626187 732 #define _EMU_IFC_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
AnnaBridge 170:e95d10626187 733 #define _EMU_IFC_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
AnnaBridge 170:e95d10626187 734 #define _EMU_IFC_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 735 #define EMU_IFC_EM23WAKEUP_DEFAULT (_EMU_IFC_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 736 #define EMU_IFC_VSCALEDONE (0x1UL << 25) /**< Clear VSCALEDONE Interrupt Flag */
AnnaBridge 170:e95d10626187 737 #define _EMU_IFC_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */
AnnaBridge 170:e95d10626187 738 #define _EMU_IFC_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */
AnnaBridge 170:e95d10626187 739 #define _EMU_IFC_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 740 #define EMU_IFC_VSCALEDONE_DEFAULT (_EMU_IFC_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 741 #define EMU_IFC_TEMP (0x1UL << 29) /**< Clear TEMP Interrupt Flag */
AnnaBridge 170:e95d10626187 742 #define _EMU_IFC_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
AnnaBridge 170:e95d10626187 743 #define _EMU_IFC_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
AnnaBridge 170:e95d10626187 744 #define _EMU_IFC_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 745 #define EMU_IFC_TEMP_DEFAULT (_EMU_IFC_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 746 #define EMU_IFC_TEMPLOW (0x1UL << 30) /**< Clear TEMPLOW Interrupt Flag */
AnnaBridge 170:e95d10626187 747 #define _EMU_IFC_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
AnnaBridge 170:e95d10626187 748 #define _EMU_IFC_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
AnnaBridge 170:e95d10626187 749 #define _EMU_IFC_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 750 #define EMU_IFC_TEMPLOW_DEFAULT (_EMU_IFC_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 751 #define EMU_IFC_TEMPHIGH (0x1UL << 31) /**< Clear TEMPHIGH Interrupt Flag */
AnnaBridge 170:e95d10626187 752 #define _EMU_IFC_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
AnnaBridge 170:e95d10626187 753 #define _EMU_IFC_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
AnnaBridge 170:e95d10626187 754 #define _EMU_IFC_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 755 #define EMU_IFC_TEMPHIGH_DEFAULT (_EMU_IFC_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IFC */
AnnaBridge 170:e95d10626187 756
AnnaBridge 170:e95d10626187 757 /* Bit fields for EMU IEN */
AnnaBridge 170:e95d10626187 758 #define _EMU_IEN_RESETVALUE 0x00000000UL /**< Default value for EMU_IEN */
AnnaBridge 170:e95d10626187 759 #define _EMU_IEN_MASK 0xE3DF37FFUL /**< Mask for EMU_IEN */
AnnaBridge 170:e95d10626187 760 #define EMU_IEN_VMONAVDDFALL (0x1UL << 0) /**< VMONAVDDFALL Interrupt Enable */
AnnaBridge 170:e95d10626187 761 #define _EMU_IEN_VMONAVDDFALL_SHIFT 0 /**< Shift value for EMU_VMONAVDDFALL */
AnnaBridge 170:e95d10626187 762 #define _EMU_IEN_VMONAVDDFALL_MASK 0x1UL /**< Bit mask for EMU_VMONAVDDFALL */
AnnaBridge 170:e95d10626187 763 #define _EMU_IEN_VMONAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 764 #define EMU_IEN_VMONAVDDFALL_DEFAULT (_EMU_IEN_VMONAVDDFALL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 765 #define EMU_IEN_VMONAVDDRISE (0x1UL << 1) /**< VMONAVDDRISE Interrupt Enable */
AnnaBridge 170:e95d10626187 766 #define _EMU_IEN_VMONAVDDRISE_SHIFT 1 /**< Shift value for EMU_VMONAVDDRISE */
AnnaBridge 170:e95d10626187 767 #define _EMU_IEN_VMONAVDDRISE_MASK 0x2UL /**< Bit mask for EMU_VMONAVDDRISE */
AnnaBridge 170:e95d10626187 768 #define _EMU_IEN_VMONAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 769 #define EMU_IEN_VMONAVDDRISE_DEFAULT (_EMU_IEN_VMONAVDDRISE_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 770 #define EMU_IEN_VMONALTAVDDFALL (0x1UL << 2) /**< VMONALTAVDDFALL Interrupt Enable */
AnnaBridge 170:e95d10626187 771 #define _EMU_IEN_VMONALTAVDDFALL_SHIFT 2 /**< Shift value for EMU_VMONALTAVDDFALL */
AnnaBridge 170:e95d10626187 772 #define _EMU_IEN_VMONALTAVDDFALL_MASK 0x4UL /**< Bit mask for EMU_VMONALTAVDDFALL */
AnnaBridge 170:e95d10626187 773 #define _EMU_IEN_VMONALTAVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 774 #define EMU_IEN_VMONALTAVDDFALL_DEFAULT (_EMU_IEN_VMONALTAVDDFALL_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 775 #define EMU_IEN_VMONALTAVDDRISE (0x1UL << 3) /**< VMONALTAVDDRISE Interrupt Enable */
AnnaBridge 170:e95d10626187 776 #define _EMU_IEN_VMONALTAVDDRISE_SHIFT 3 /**< Shift value for EMU_VMONALTAVDDRISE */
AnnaBridge 170:e95d10626187 777 #define _EMU_IEN_VMONALTAVDDRISE_MASK 0x8UL /**< Bit mask for EMU_VMONALTAVDDRISE */
AnnaBridge 170:e95d10626187 778 #define _EMU_IEN_VMONALTAVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 779 #define EMU_IEN_VMONALTAVDDRISE_DEFAULT (_EMU_IEN_VMONALTAVDDRISE_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 780 #define EMU_IEN_VMONDVDDFALL (0x1UL << 4) /**< VMONDVDDFALL Interrupt Enable */
AnnaBridge 170:e95d10626187 781 #define _EMU_IEN_VMONDVDDFALL_SHIFT 4 /**< Shift value for EMU_VMONDVDDFALL */
AnnaBridge 170:e95d10626187 782 #define _EMU_IEN_VMONDVDDFALL_MASK 0x10UL /**< Bit mask for EMU_VMONDVDDFALL */
AnnaBridge 170:e95d10626187 783 #define _EMU_IEN_VMONDVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 784 #define EMU_IEN_VMONDVDDFALL_DEFAULT (_EMU_IEN_VMONDVDDFALL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 785 #define EMU_IEN_VMONDVDDRISE (0x1UL << 5) /**< VMONDVDDRISE Interrupt Enable */
AnnaBridge 170:e95d10626187 786 #define _EMU_IEN_VMONDVDDRISE_SHIFT 5 /**< Shift value for EMU_VMONDVDDRISE */
AnnaBridge 170:e95d10626187 787 #define _EMU_IEN_VMONDVDDRISE_MASK 0x20UL /**< Bit mask for EMU_VMONDVDDRISE */
AnnaBridge 170:e95d10626187 788 #define _EMU_IEN_VMONDVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 789 #define EMU_IEN_VMONDVDDRISE_DEFAULT (_EMU_IEN_VMONDVDDRISE_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 790 #define EMU_IEN_VMONIO0FALL (0x1UL << 6) /**< VMONIO0FALL Interrupt Enable */
AnnaBridge 170:e95d10626187 791 #define _EMU_IEN_VMONIO0FALL_SHIFT 6 /**< Shift value for EMU_VMONIO0FALL */
AnnaBridge 170:e95d10626187 792 #define _EMU_IEN_VMONIO0FALL_MASK 0x40UL /**< Bit mask for EMU_VMONIO0FALL */
AnnaBridge 170:e95d10626187 793 #define _EMU_IEN_VMONIO0FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 794 #define EMU_IEN_VMONIO0FALL_DEFAULT (_EMU_IEN_VMONIO0FALL_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 795 #define EMU_IEN_VMONIO0RISE (0x1UL << 7) /**< VMONIO0RISE Interrupt Enable */
AnnaBridge 170:e95d10626187 796 #define _EMU_IEN_VMONIO0RISE_SHIFT 7 /**< Shift value for EMU_VMONIO0RISE */
AnnaBridge 170:e95d10626187 797 #define _EMU_IEN_VMONIO0RISE_MASK 0x80UL /**< Bit mask for EMU_VMONIO0RISE */
AnnaBridge 170:e95d10626187 798 #define _EMU_IEN_VMONIO0RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 799 #define EMU_IEN_VMONIO0RISE_DEFAULT (_EMU_IEN_VMONIO0RISE_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 800 #define EMU_IEN_VMONIO1FALL (0x1UL << 8) /**< VMONIO1FALL Interrupt Enable */
AnnaBridge 170:e95d10626187 801 #define _EMU_IEN_VMONIO1FALL_SHIFT 8 /**< Shift value for EMU_VMONIO1FALL */
AnnaBridge 170:e95d10626187 802 #define _EMU_IEN_VMONIO1FALL_MASK 0x100UL /**< Bit mask for EMU_VMONIO1FALL */
AnnaBridge 170:e95d10626187 803 #define _EMU_IEN_VMONIO1FALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 804 #define EMU_IEN_VMONIO1FALL_DEFAULT (_EMU_IEN_VMONIO1FALL_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 805 #define EMU_IEN_VMONIO1RISE (0x1UL << 9) /**< VMONIO1RISE Interrupt Enable */
AnnaBridge 170:e95d10626187 806 #define _EMU_IEN_VMONIO1RISE_SHIFT 9 /**< Shift value for EMU_VMONIO1RISE */
AnnaBridge 170:e95d10626187 807 #define _EMU_IEN_VMONIO1RISE_MASK 0x200UL /**< Bit mask for EMU_VMONIO1RISE */
AnnaBridge 170:e95d10626187 808 #define _EMU_IEN_VMONIO1RISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 809 #define EMU_IEN_VMONIO1RISE_DEFAULT (_EMU_IEN_VMONIO1RISE_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 810 #define EMU_IEN_R5VREADY (0x1UL << 10) /**< R5VREADY Interrupt Enable */
AnnaBridge 170:e95d10626187 811 #define _EMU_IEN_R5VREADY_SHIFT 10 /**< Shift value for EMU_R5VREADY */
AnnaBridge 170:e95d10626187 812 #define _EMU_IEN_R5VREADY_MASK 0x400UL /**< Bit mask for EMU_R5VREADY */
AnnaBridge 170:e95d10626187 813 #define _EMU_IEN_R5VREADY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 814 #define EMU_IEN_R5VREADY_DEFAULT (_EMU_IEN_R5VREADY_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 815 #define EMU_IEN_VMONBUVDDFALL (0x1UL << 12) /**< VMONBUVDDFALL Interrupt Enable */
AnnaBridge 170:e95d10626187 816 #define _EMU_IEN_VMONBUVDDFALL_SHIFT 12 /**< Shift value for EMU_VMONBUVDDFALL */
AnnaBridge 170:e95d10626187 817 #define _EMU_IEN_VMONBUVDDFALL_MASK 0x1000UL /**< Bit mask for EMU_VMONBUVDDFALL */
AnnaBridge 170:e95d10626187 818 #define _EMU_IEN_VMONBUVDDFALL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 819 #define EMU_IEN_VMONBUVDDFALL_DEFAULT (_EMU_IEN_VMONBUVDDFALL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 820 #define EMU_IEN_VMONBUVDDRISE (0x1UL << 13) /**< VMONBUVDDRISE Interrupt Enable */
AnnaBridge 170:e95d10626187 821 #define _EMU_IEN_VMONBUVDDRISE_SHIFT 13 /**< Shift value for EMU_VMONBUVDDRISE */
AnnaBridge 170:e95d10626187 822 #define _EMU_IEN_VMONBUVDDRISE_MASK 0x2000UL /**< Bit mask for EMU_VMONBUVDDRISE */
AnnaBridge 170:e95d10626187 823 #define _EMU_IEN_VMONBUVDDRISE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 824 #define EMU_IEN_VMONBUVDDRISE_DEFAULT (_EMU_IEN_VMONBUVDDRISE_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 825 #define EMU_IEN_PFETOVERCURRENTLIMIT (0x1UL << 16) /**< PFETOVERCURRENTLIMIT Interrupt Enable */
AnnaBridge 170:e95d10626187 826 #define _EMU_IEN_PFETOVERCURRENTLIMIT_SHIFT 16 /**< Shift value for EMU_PFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 827 #define _EMU_IEN_PFETOVERCURRENTLIMIT_MASK 0x10000UL /**< Bit mask for EMU_PFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 828 #define _EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 829 #define EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_PFETOVERCURRENTLIMIT_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 830 #define EMU_IEN_NFETOVERCURRENTLIMIT (0x1UL << 17) /**< NFETOVERCURRENTLIMIT Interrupt Enable */
AnnaBridge 170:e95d10626187 831 #define _EMU_IEN_NFETOVERCURRENTLIMIT_SHIFT 17 /**< Shift value for EMU_NFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 832 #define _EMU_IEN_NFETOVERCURRENTLIMIT_MASK 0x20000UL /**< Bit mask for EMU_NFETOVERCURRENTLIMIT */
AnnaBridge 170:e95d10626187 833 #define _EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 834 #define EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT (_EMU_IEN_NFETOVERCURRENTLIMIT_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 835 #define EMU_IEN_DCDCLPRUNNING (0x1UL << 18) /**< DCDCLPRUNNING Interrupt Enable */
AnnaBridge 170:e95d10626187 836 #define _EMU_IEN_DCDCLPRUNNING_SHIFT 18 /**< Shift value for EMU_DCDCLPRUNNING */
AnnaBridge 170:e95d10626187 837 #define _EMU_IEN_DCDCLPRUNNING_MASK 0x40000UL /**< Bit mask for EMU_DCDCLPRUNNING */
AnnaBridge 170:e95d10626187 838 #define _EMU_IEN_DCDCLPRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 839 #define EMU_IEN_DCDCLPRUNNING_DEFAULT (_EMU_IEN_DCDCLPRUNNING_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 840 #define EMU_IEN_DCDCLNRUNNING (0x1UL << 19) /**< DCDCLNRUNNING Interrupt Enable */
AnnaBridge 170:e95d10626187 841 #define _EMU_IEN_DCDCLNRUNNING_SHIFT 19 /**< Shift value for EMU_DCDCLNRUNNING */
AnnaBridge 170:e95d10626187 842 #define _EMU_IEN_DCDCLNRUNNING_MASK 0x80000UL /**< Bit mask for EMU_DCDCLNRUNNING */
AnnaBridge 170:e95d10626187 843 #define _EMU_IEN_DCDCLNRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 844 #define EMU_IEN_DCDCLNRUNNING_DEFAULT (_EMU_IEN_DCDCLNRUNNING_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 845 #define EMU_IEN_DCDCINBYPASS (0x1UL << 20) /**< DCDCINBYPASS Interrupt Enable */
AnnaBridge 170:e95d10626187 846 #define _EMU_IEN_DCDCINBYPASS_SHIFT 20 /**< Shift value for EMU_DCDCINBYPASS */
AnnaBridge 170:e95d10626187 847 #define _EMU_IEN_DCDCINBYPASS_MASK 0x100000UL /**< Bit mask for EMU_DCDCINBYPASS */
AnnaBridge 170:e95d10626187 848 #define _EMU_IEN_DCDCINBYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 849 #define EMU_IEN_DCDCINBYPASS_DEFAULT (_EMU_IEN_DCDCINBYPASS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 850 #define EMU_IEN_BURDY (0x1UL << 22) /**< BURDY Interrupt Enable */
AnnaBridge 170:e95d10626187 851 #define _EMU_IEN_BURDY_SHIFT 22 /**< Shift value for EMU_BURDY */
AnnaBridge 170:e95d10626187 852 #define _EMU_IEN_BURDY_MASK 0x400000UL /**< Bit mask for EMU_BURDY */
AnnaBridge 170:e95d10626187 853 #define _EMU_IEN_BURDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 854 #define EMU_IEN_BURDY_DEFAULT (_EMU_IEN_BURDY_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 855 #define EMU_IEN_R5VVSINT (0x1UL << 23) /**< R5VVSINT Interrupt Enable */
AnnaBridge 170:e95d10626187 856 #define _EMU_IEN_R5VVSINT_SHIFT 23 /**< Shift value for EMU_R5VVSINT */
AnnaBridge 170:e95d10626187 857 #define _EMU_IEN_R5VVSINT_MASK 0x800000UL /**< Bit mask for EMU_R5VVSINT */
AnnaBridge 170:e95d10626187 858 #define _EMU_IEN_R5VVSINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 859 #define EMU_IEN_R5VVSINT_DEFAULT (_EMU_IEN_R5VVSINT_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 860 #define EMU_IEN_EM23WAKEUP (0x1UL << 24) /**< EM23WAKEUP Interrupt Enable */
AnnaBridge 170:e95d10626187 861 #define _EMU_IEN_EM23WAKEUP_SHIFT 24 /**< Shift value for EMU_EM23WAKEUP */
AnnaBridge 170:e95d10626187 862 #define _EMU_IEN_EM23WAKEUP_MASK 0x1000000UL /**< Bit mask for EMU_EM23WAKEUP */
AnnaBridge 170:e95d10626187 863 #define _EMU_IEN_EM23WAKEUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 864 #define EMU_IEN_EM23WAKEUP_DEFAULT (_EMU_IEN_EM23WAKEUP_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 865 #define EMU_IEN_VSCALEDONE (0x1UL << 25) /**< VSCALEDONE Interrupt Enable */
AnnaBridge 170:e95d10626187 866 #define _EMU_IEN_VSCALEDONE_SHIFT 25 /**< Shift value for EMU_VSCALEDONE */
AnnaBridge 170:e95d10626187 867 #define _EMU_IEN_VSCALEDONE_MASK 0x2000000UL /**< Bit mask for EMU_VSCALEDONE */
AnnaBridge 170:e95d10626187 868 #define _EMU_IEN_VSCALEDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 869 #define EMU_IEN_VSCALEDONE_DEFAULT (_EMU_IEN_VSCALEDONE_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 870 #define EMU_IEN_TEMP (0x1UL << 29) /**< TEMP Interrupt Enable */
AnnaBridge 170:e95d10626187 871 #define _EMU_IEN_TEMP_SHIFT 29 /**< Shift value for EMU_TEMP */
AnnaBridge 170:e95d10626187 872 #define _EMU_IEN_TEMP_MASK 0x20000000UL /**< Bit mask for EMU_TEMP */
AnnaBridge 170:e95d10626187 873 #define _EMU_IEN_TEMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 874 #define EMU_IEN_TEMP_DEFAULT (_EMU_IEN_TEMP_DEFAULT << 29) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 875 #define EMU_IEN_TEMPLOW (0x1UL << 30) /**< TEMPLOW Interrupt Enable */
AnnaBridge 170:e95d10626187 876 #define _EMU_IEN_TEMPLOW_SHIFT 30 /**< Shift value for EMU_TEMPLOW */
AnnaBridge 170:e95d10626187 877 #define _EMU_IEN_TEMPLOW_MASK 0x40000000UL /**< Bit mask for EMU_TEMPLOW */
AnnaBridge 170:e95d10626187 878 #define _EMU_IEN_TEMPLOW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 879 #define EMU_IEN_TEMPLOW_DEFAULT (_EMU_IEN_TEMPLOW_DEFAULT << 30) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 880 #define EMU_IEN_TEMPHIGH (0x1UL << 31) /**< TEMPHIGH Interrupt Enable */
AnnaBridge 170:e95d10626187 881 #define _EMU_IEN_TEMPHIGH_SHIFT 31 /**< Shift value for EMU_TEMPHIGH */
AnnaBridge 170:e95d10626187 882 #define _EMU_IEN_TEMPHIGH_MASK 0x80000000UL /**< Bit mask for EMU_TEMPHIGH */
AnnaBridge 170:e95d10626187 883 #define _EMU_IEN_TEMPHIGH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 884 #define EMU_IEN_TEMPHIGH_DEFAULT (_EMU_IEN_TEMPHIGH_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_IEN */
AnnaBridge 170:e95d10626187 885
AnnaBridge 170:e95d10626187 886 /* Bit fields for EMU PWRLOCK */
AnnaBridge 170:e95d10626187 887 #define _EMU_PWRLOCK_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRLOCK */
AnnaBridge 170:e95d10626187 888 #define _EMU_PWRLOCK_MASK 0x0000FFFFUL /**< Mask for EMU_PWRLOCK */
AnnaBridge 170:e95d10626187 889 #define _EMU_PWRLOCK_LOCKKEY_SHIFT 0 /**< Shift value for EMU_LOCKKEY */
AnnaBridge 170:e95d10626187 890 #define _EMU_PWRLOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for EMU_LOCKKEY */
AnnaBridge 170:e95d10626187 891 #define _EMU_PWRLOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRLOCK */
AnnaBridge 170:e95d10626187 892 #define _EMU_PWRLOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for EMU_PWRLOCK */
AnnaBridge 170:e95d10626187 893 #define _EMU_PWRLOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for EMU_PWRLOCK */
AnnaBridge 170:e95d10626187 894 #define _EMU_PWRLOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for EMU_PWRLOCK */
AnnaBridge 170:e95d10626187 895 #define _EMU_PWRLOCK_LOCKKEY_UNLOCK 0x0000ADE8UL /**< Mode UNLOCK for EMU_PWRLOCK */
AnnaBridge 170:e95d10626187 896 #define EMU_PWRLOCK_LOCKKEY_DEFAULT (_EMU_PWRLOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_PWRLOCK */
AnnaBridge 170:e95d10626187 897 #define EMU_PWRLOCK_LOCKKEY_LOCK (_EMU_PWRLOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for EMU_PWRLOCK */
AnnaBridge 170:e95d10626187 898 #define EMU_PWRLOCK_LOCKKEY_UNLOCKED (_EMU_PWRLOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for EMU_PWRLOCK */
AnnaBridge 170:e95d10626187 899 #define EMU_PWRLOCK_LOCKKEY_LOCKED (_EMU_PWRLOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for EMU_PWRLOCK */
AnnaBridge 170:e95d10626187 900 #define EMU_PWRLOCK_LOCKKEY_UNLOCK (_EMU_PWRLOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for EMU_PWRLOCK */
AnnaBridge 170:e95d10626187 901
AnnaBridge 170:e95d10626187 902 /* Bit fields for EMU PWRCTRL */
AnnaBridge 170:e95d10626187 903 #define _EMU_PWRCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 904 #define _EMU_PWRCTRL_MASK 0x00002420UL /**< Mask for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 905 #define EMU_PWRCTRL_ANASW (0x1UL << 5) /**< Analog Switch Selection */
AnnaBridge 170:e95d10626187 906 #define _EMU_PWRCTRL_ANASW_SHIFT 5 /**< Shift value for EMU_ANASW */
AnnaBridge 170:e95d10626187 907 #define _EMU_PWRCTRL_ANASW_MASK 0x20UL /**< Bit mask for EMU_ANASW */
AnnaBridge 170:e95d10626187 908 #define _EMU_PWRCTRL_ANASW_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 909 #define _EMU_PWRCTRL_ANASW_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 910 #define _EMU_PWRCTRL_ANASW_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 911 #define EMU_PWRCTRL_ANASW_DEFAULT (_EMU_PWRCTRL_ANASW_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 912 #define EMU_PWRCTRL_ANASW_AVDD (_EMU_PWRCTRL_ANASW_AVDD << 5) /**< Shifted mode AVDD for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 913 #define EMU_PWRCTRL_ANASW_DVDD (_EMU_PWRCTRL_ANASW_DVDD << 5) /**< Shifted mode DVDD for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 914 #define EMU_PWRCTRL_REGPWRSEL (0x1UL << 10) /**< This field selects the input supply pin for the Digital LDO. */
AnnaBridge 170:e95d10626187 915 #define _EMU_PWRCTRL_REGPWRSEL_SHIFT 10 /**< Shift value for EMU_REGPWRSEL */
AnnaBridge 170:e95d10626187 916 #define _EMU_PWRCTRL_REGPWRSEL_MASK 0x400UL /**< Bit mask for EMU_REGPWRSEL */
AnnaBridge 170:e95d10626187 917 #define _EMU_PWRCTRL_REGPWRSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 918 #define _EMU_PWRCTRL_REGPWRSEL_AVDD 0x00000000UL /**< Mode AVDD for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 919 #define _EMU_PWRCTRL_REGPWRSEL_DVDD 0x00000001UL /**< Mode DVDD for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 920 #define EMU_PWRCTRL_REGPWRSEL_DEFAULT (_EMU_PWRCTRL_REGPWRSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 921 #define EMU_PWRCTRL_REGPWRSEL_AVDD (_EMU_PWRCTRL_REGPWRSEL_AVDD << 10) /**< Shifted mode AVDD for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 922 #define EMU_PWRCTRL_REGPWRSEL_DVDD (_EMU_PWRCTRL_REGPWRSEL_DVDD << 10) /**< Shifted mode DVDD for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 923 #define EMU_PWRCTRL_IMMEDIATEPWRSWITCH (0x1UL << 13) /**< Allows immeditate switching of ANASW and REGPWRSEL bitfields */
AnnaBridge 170:e95d10626187 924 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_SHIFT 13 /**< Shift value for EMU_IMMEDIATEPWRSWITCH */
AnnaBridge 170:e95d10626187 925 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_MASK 0x2000UL /**< Bit mask for EMU_IMMEDIATEPWRSWITCH */
AnnaBridge 170:e95d10626187 926 #define _EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 927 #define EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT (_EMU_PWRCTRL_IMMEDIATEPWRSWITCH_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_PWRCTRL */
AnnaBridge 170:e95d10626187 928
AnnaBridge 170:e95d10626187 929 /* Bit fields for EMU DCDCCTRL */
AnnaBridge 170:e95d10626187 930 #define _EMU_DCDCCTRL_RESETVALUE 0x00000033UL /**< Default value for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 931 #define _EMU_DCDCCTRL_MASK 0x00000033UL /**< Mask for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 932 #define _EMU_DCDCCTRL_DCDCMODE_SHIFT 0 /**< Shift value for EMU_DCDCMODE */
AnnaBridge 170:e95d10626187 933 #define _EMU_DCDCCTRL_DCDCMODE_MASK 0x3UL /**< Bit mask for EMU_DCDCMODE */
AnnaBridge 170:e95d10626187 934 #define _EMU_DCDCCTRL_DCDCMODE_BYPASS 0x00000000UL /**< Mode BYPASS for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 935 #define _EMU_DCDCCTRL_DCDCMODE_LOWNOISE 0x00000001UL /**< Mode LOWNOISE for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 936 #define _EMU_DCDCCTRL_DCDCMODE_LOWPOWER 0x00000002UL /**< Mode LOWPOWER for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 937 #define _EMU_DCDCCTRL_DCDCMODE_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 938 #define _EMU_DCDCCTRL_DCDCMODE_OFF 0x00000003UL /**< Mode OFF for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 939 #define EMU_DCDCCTRL_DCDCMODE_BYPASS (_EMU_DCDCCTRL_DCDCMODE_BYPASS << 0) /**< Shifted mode BYPASS for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 940 #define EMU_DCDCCTRL_DCDCMODE_LOWNOISE (_EMU_DCDCCTRL_DCDCMODE_LOWNOISE << 0) /**< Shifted mode LOWNOISE for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 941 #define EMU_DCDCCTRL_DCDCMODE_LOWPOWER (_EMU_DCDCCTRL_DCDCMODE_LOWPOWER << 0) /**< Shifted mode LOWPOWER for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 942 #define EMU_DCDCCTRL_DCDCMODE_DEFAULT (_EMU_DCDCCTRL_DCDCMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 943 #define EMU_DCDCCTRL_DCDCMODE_OFF (_EMU_DCDCCTRL_DCDCMODE_OFF << 0) /**< Shifted mode OFF for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 944 #define EMU_DCDCCTRL_DCDCMODEEM23 (0x1UL << 4) /**< DCDC Mode EM23 */
AnnaBridge 170:e95d10626187 945 #define _EMU_DCDCCTRL_DCDCMODEEM23_SHIFT 4 /**< Shift value for EMU_DCDCMODEEM23 */
AnnaBridge 170:e95d10626187 946 #define _EMU_DCDCCTRL_DCDCMODEEM23_MASK 0x10UL /**< Bit mask for EMU_DCDCMODEEM23 */
AnnaBridge 170:e95d10626187 947 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23SW 0x00000000UL /**< Mode EM23SW for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 948 #define _EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 949 #define _EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER 0x00000001UL /**< Mode EM23LOWPOWER for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 950 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23SW (_EMU_DCDCCTRL_DCDCMODEEM23_EM23SW << 4) /**< Shifted mode EM23SW for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 951 #define EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM23_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 952 #define EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM23_EM23LOWPOWER << 4) /**< Shifted mode EM23LOWPOWER for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 953 #define EMU_DCDCCTRL_DCDCMODEEM4 (0x1UL << 5) /**< DCDC Mode EM4H */
AnnaBridge 170:e95d10626187 954 #define _EMU_DCDCCTRL_DCDCMODEEM4_SHIFT 5 /**< Shift value for EMU_DCDCMODEEM4 */
AnnaBridge 170:e95d10626187 955 #define _EMU_DCDCCTRL_DCDCMODEEM4_MASK 0x20UL /**< Bit mask for EMU_DCDCMODEEM4 */
AnnaBridge 170:e95d10626187 956 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4SW 0x00000000UL /**< Mode EM4SW for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 957 #define _EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 958 #define _EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER 0x00000001UL /**< Mode EM4LOWPOWER for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 959 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4SW (_EMU_DCDCCTRL_DCDCMODEEM4_EM4SW << 5) /**< Shifted mode EM4SW for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 960 #define EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT (_EMU_DCDCCTRL_DCDCMODEEM4_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 961 #define EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER (_EMU_DCDCCTRL_DCDCMODEEM4_EM4LOWPOWER << 5) /**< Shifted mode EM4LOWPOWER for EMU_DCDCCTRL */
AnnaBridge 170:e95d10626187 962
AnnaBridge 170:e95d10626187 963 /* Bit fields for EMU DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 964 #define _EMU_DCDCMISCCTRL_RESETVALUE 0x03107706UL /**< Default value for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 965 #define _EMU_DCDCMISCCTRL_MASK 0x377FFF27UL /**< Mask for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 966 #define EMU_DCDCMISCCTRL_LNFORCECCM (0x1UL << 0) /**< Force DCDC into CCM mode in low noise operation */
AnnaBridge 170:e95d10626187 967 #define _EMU_DCDCMISCCTRL_LNFORCECCM_SHIFT 0 /**< Shift value for EMU_LNFORCECCM */
AnnaBridge 170:e95d10626187 968 #define _EMU_DCDCMISCCTRL_LNFORCECCM_MASK 0x1UL /**< Bit mask for EMU_LNFORCECCM */
AnnaBridge 170:e95d10626187 969 #define _EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 970 #define EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCM_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 971 #define EMU_DCDCMISCCTRL_LPCMPHYSDIS (0x1UL << 1) /**< Disable LP mode hysteresis in the state machine control */
AnnaBridge 170:e95d10626187 972 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_SHIFT 1 /**< Shift value for EMU_LPCMPHYSDIS */
AnnaBridge 170:e95d10626187 973 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_MASK 0x2UL /**< Bit mask for EMU_LPCMPHYSDIS */
AnnaBridge 170:e95d10626187 974 #define _EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 975 #define EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 976 #define EMU_DCDCMISCCTRL_LPCMPHYSHI (0x1UL << 2) /**< Comparator threshold on the high side */
AnnaBridge 170:e95d10626187 977 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_SHIFT 2 /**< Shift value for EMU_LPCMPHYSHI */
AnnaBridge 170:e95d10626187 978 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_MASK 0x4UL /**< Bit mask for EMU_LPCMPHYSHI */
AnnaBridge 170:e95d10626187 979 #define _EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 980 #define EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPHYSHI_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 981 #define EMU_DCDCMISCCTRL_LNFORCECCMIMM (0x1UL << 5) /**< Force DCDC into CCM mode immediately, based on LNFORCECCM */
AnnaBridge 170:e95d10626187 982 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_SHIFT 5 /**< Shift value for EMU_LNFORCECCMIMM */
AnnaBridge 170:e95d10626187 983 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_MASK 0x20UL /**< Bit mask for EMU_LNFORCECCMIMM */
AnnaBridge 170:e95d10626187 984 #define _EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 985 #define EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT (_EMU_DCDCMISCCTRL_LNFORCECCMIMM_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 986 #define _EMU_DCDCMISCCTRL_PFETCNT_SHIFT 8 /**< Shift value for EMU_PFETCNT */
AnnaBridge 170:e95d10626187 987 #define _EMU_DCDCMISCCTRL_PFETCNT_MASK 0xF00UL /**< Bit mask for EMU_PFETCNT */
AnnaBridge 170:e95d10626187 988 #define _EMU_DCDCMISCCTRL_PFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 989 #define EMU_DCDCMISCCTRL_PFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_PFETCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 990 #define _EMU_DCDCMISCCTRL_NFETCNT_SHIFT 12 /**< Shift value for EMU_NFETCNT */
AnnaBridge 170:e95d10626187 991 #define _EMU_DCDCMISCCTRL_NFETCNT_MASK 0xF000UL /**< Bit mask for EMU_NFETCNT */
AnnaBridge 170:e95d10626187 992 #define _EMU_DCDCMISCCTRL_NFETCNT_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 993 #define EMU_DCDCMISCCTRL_NFETCNT_DEFAULT (_EMU_DCDCMISCCTRL_NFETCNT_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 994 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_SHIFT 16 /**< Shift value for EMU_BYPLIMSEL */
AnnaBridge 170:e95d10626187 995 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_MASK 0xF0000UL /**< Bit mask for EMU_BYPLIMSEL */
AnnaBridge 170:e95d10626187 996 #define _EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 997 #define EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_BYPLIMSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 998 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_SHIFT 20 /**< Shift value for EMU_LPCLIMILIMSEL */
AnnaBridge 170:e95d10626187 999 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_MASK 0x700000UL /**< Bit mask for EMU_LPCLIMILIMSEL */
AnnaBridge 170:e95d10626187 1000 #define _EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1001 #define EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LPCLIMILIMSEL_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1002 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_SHIFT 24 /**< Shift value for EMU_LNCLIMILIMSEL */
AnnaBridge 170:e95d10626187 1003 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_MASK 0x7000000UL /**< Bit mask for EMU_LNCLIMILIMSEL */
AnnaBridge 170:e95d10626187 1004 #define _EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1005 #define EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT (_EMU_DCDCMISCCTRL_LNCLIMILIMSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1006 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_SHIFT 28 /**< Shift value for EMU_LPCMPBIASEM234H */
AnnaBridge 170:e95d10626187 1007 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_MASK 0x30000000UL /**< Bit mask for EMU_LPCMPBIASEM234H */
AnnaBridge 170:e95d10626187 1008 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1009 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1010 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1011 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1012 #define _EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1013 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1014 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS0 << 28) /**< Shifted mode BIAS0 for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1015 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS1 << 28) /**< Shifted mode BIAS1 for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1016 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS2 << 28) /**< Shifted mode BIAS2 for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1017 #define EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 (_EMU_DCDCMISCCTRL_LPCMPBIASEM234H_BIAS3 << 28) /**< Shifted mode BIAS3 for EMU_DCDCMISCCTRL */
AnnaBridge 170:e95d10626187 1018
AnnaBridge 170:e95d10626187 1019 /* Bit fields for EMU DCDCZDETCTRL */
AnnaBridge 170:e95d10626187 1020 #define _EMU_DCDCZDETCTRL_RESETVALUE 0x00000150UL /**< Default value for EMU_DCDCZDETCTRL */
AnnaBridge 170:e95d10626187 1021 #define _EMU_DCDCZDETCTRL_MASK 0x00000370UL /**< Mask for EMU_DCDCZDETCTRL */
AnnaBridge 170:e95d10626187 1022 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_SHIFT 4 /**< Shift value for EMU_ZDETILIMSEL */
AnnaBridge 170:e95d10626187 1023 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_MASK 0x70UL /**< Bit mask for EMU_ZDETILIMSEL */
AnnaBridge 170:e95d10626187 1024 #define _EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
AnnaBridge 170:e95d10626187 1025 #define EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT (_EMU_DCDCZDETCTRL_ZDETILIMSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
AnnaBridge 170:e95d10626187 1026 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_SHIFT 8 /**< Shift value for EMU_ZDETBLANKDLY */
AnnaBridge 170:e95d10626187 1027 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_ZDETBLANKDLY */
AnnaBridge 170:e95d10626187 1028 #define _EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCZDETCTRL */
AnnaBridge 170:e95d10626187 1029 #define EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT (_EMU_DCDCZDETCTRL_ZDETBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCZDETCTRL */
AnnaBridge 170:e95d10626187 1030
AnnaBridge 170:e95d10626187 1031 /* Bit fields for EMU DCDCCLIMCTRL */
AnnaBridge 170:e95d10626187 1032 #define _EMU_DCDCCLIMCTRL_RESETVALUE 0x00000100UL /**< Default value for EMU_DCDCCLIMCTRL */
AnnaBridge 170:e95d10626187 1033 #define _EMU_DCDCCLIMCTRL_MASK 0x00002300UL /**< Mask for EMU_DCDCCLIMCTRL */
AnnaBridge 170:e95d10626187 1034 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_SHIFT 8 /**< Shift value for EMU_CLIMBLANKDLY */
AnnaBridge 170:e95d10626187 1035 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_MASK 0x300UL /**< Bit mask for EMU_CLIMBLANKDLY */
AnnaBridge 170:e95d10626187 1036 #define _EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
AnnaBridge 170:e95d10626187 1037 #define EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT (_EMU_DCDCCLIMCTRL_CLIMBLANKDLY_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
AnnaBridge 170:e95d10626187 1038 #define EMU_DCDCCLIMCTRL_BYPLIMEN (0x1UL << 13) /**< Bypass Current Limit Enable */
AnnaBridge 170:e95d10626187 1039 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_SHIFT 13 /**< Shift value for EMU_BYPLIMEN */
AnnaBridge 170:e95d10626187 1040 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_MASK 0x2000UL /**< Bit mask for EMU_BYPLIMEN */
AnnaBridge 170:e95d10626187 1041 #define _EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCCLIMCTRL */
AnnaBridge 170:e95d10626187 1042 #define EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT (_EMU_DCDCCLIMCTRL_BYPLIMEN_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_DCDCCLIMCTRL */
AnnaBridge 170:e95d10626187 1043
AnnaBridge 170:e95d10626187 1044 /* Bit fields for EMU DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1045 #define _EMU_DCDCLNCOMPCTRL_RESETVALUE 0x57204077UL /**< Default value for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1046 #define _EMU_DCDCLNCOMPCTRL_MASK 0xF730F1F7UL /**< Mask for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1047 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_SHIFT 0 /**< Shift value for EMU_COMPENR1 */
AnnaBridge 170:e95d10626187 1048 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_MASK 0x7UL /**< Bit mask for EMU_COMPENR1 */
AnnaBridge 170:e95d10626187 1049 #define _EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1050 #define EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR1_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1051 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_SHIFT 4 /**< Shift value for EMU_COMPENR2 */
AnnaBridge 170:e95d10626187 1052 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_MASK 0x1F0UL /**< Bit mask for EMU_COMPENR2 */
AnnaBridge 170:e95d10626187 1053 #define _EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1054 #define EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR2_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1055 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_SHIFT 12 /**< Shift value for EMU_COMPENR3 */
AnnaBridge 170:e95d10626187 1056 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_MASK 0xF000UL /**< Bit mask for EMU_COMPENR3 */
AnnaBridge 170:e95d10626187 1057 #define _EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT 0x00000004UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1058 #define EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENR3_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1059 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_SHIFT 20 /**< Shift value for EMU_COMPENC1 */
AnnaBridge 170:e95d10626187 1060 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_MASK 0x300000UL /**< Bit mask for EMU_COMPENC1 */
AnnaBridge 170:e95d10626187 1061 #define _EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT 0x00000002UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1062 #define EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC1_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1063 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_SHIFT 24 /**< Shift value for EMU_COMPENC2 */
AnnaBridge 170:e95d10626187 1064 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_MASK 0x7000000UL /**< Bit mask for EMU_COMPENC2 */
AnnaBridge 170:e95d10626187 1065 #define _EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT 0x00000007UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1066 #define EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC2_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1067 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_SHIFT 28 /**< Shift value for EMU_COMPENC3 */
AnnaBridge 170:e95d10626187 1068 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_MASK 0xF0000000UL /**< Bit mask for EMU_COMPENC3 */
AnnaBridge 170:e95d10626187 1069 #define _EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT 0x00000005UL /**< Mode DEFAULT for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1070 #define EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT (_EMU_DCDCLNCOMPCTRL_COMPENC3_DEFAULT << 28) /**< Shifted mode DEFAULT for EMU_DCDCLNCOMPCTRL */
AnnaBridge 170:e95d10626187 1071
AnnaBridge 170:e95d10626187 1072 /* Bit fields for EMU DCDCLNVCTRL */
AnnaBridge 170:e95d10626187 1073 #define _EMU_DCDCLNVCTRL_RESETVALUE 0x00007100UL /**< Default value for EMU_DCDCLNVCTRL */
AnnaBridge 170:e95d10626187 1074 #define _EMU_DCDCLNVCTRL_MASK 0x00007F02UL /**< Mask for EMU_DCDCLNVCTRL */
AnnaBridge 170:e95d10626187 1075 #define EMU_DCDCLNVCTRL_LNATT (0x1UL << 1) /**< Low Noise Mode Feedback Attenuation */
AnnaBridge 170:e95d10626187 1076 #define _EMU_DCDCLNVCTRL_LNATT_SHIFT 1 /**< Shift value for EMU_LNATT */
AnnaBridge 170:e95d10626187 1077 #define _EMU_DCDCLNVCTRL_LNATT_MASK 0x2UL /**< Bit mask for EMU_LNATT */
AnnaBridge 170:e95d10626187 1078 #define _EMU_DCDCLNVCTRL_LNATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
AnnaBridge 170:e95d10626187 1079 #define _EMU_DCDCLNVCTRL_LNATT_DIV3 0x00000000UL /**< Mode DIV3 for EMU_DCDCLNVCTRL */
AnnaBridge 170:e95d10626187 1080 #define _EMU_DCDCLNVCTRL_LNATT_DIV6 0x00000001UL /**< Mode DIV6 for EMU_DCDCLNVCTRL */
AnnaBridge 170:e95d10626187 1081 #define EMU_DCDCLNVCTRL_LNATT_DEFAULT (_EMU_DCDCLNVCTRL_LNATT_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
AnnaBridge 170:e95d10626187 1082 #define EMU_DCDCLNVCTRL_LNATT_DIV3 (_EMU_DCDCLNVCTRL_LNATT_DIV3 << 1) /**< Shifted mode DIV3 for EMU_DCDCLNVCTRL */
AnnaBridge 170:e95d10626187 1083 #define EMU_DCDCLNVCTRL_LNATT_DIV6 (_EMU_DCDCLNVCTRL_LNATT_DIV6 << 1) /**< Shifted mode DIV6 for EMU_DCDCLNVCTRL */
AnnaBridge 170:e95d10626187 1084 #define _EMU_DCDCLNVCTRL_LNVREF_SHIFT 8 /**< Shift value for EMU_LNVREF */
AnnaBridge 170:e95d10626187 1085 #define _EMU_DCDCLNVCTRL_LNVREF_MASK 0x7F00UL /**< Bit mask for EMU_LNVREF */
AnnaBridge 170:e95d10626187 1086 #define _EMU_DCDCLNVCTRL_LNVREF_DEFAULT 0x00000071UL /**< Mode DEFAULT for EMU_DCDCLNVCTRL */
AnnaBridge 170:e95d10626187 1087 #define EMU_DCDCLNVCTRL_LNVREF_DEFAULT (_EMU_DCDCLNVCTRL_LNVREF_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLNVCTRL */
AnnaBridge 170:e95d10626187 1088
AnnaBridge 170:e95d10626187 1089 /* Bit fields for EMU DCDCLPVCTRL */
AnnaBridge 170:e95d10626187 1090 #define _EMU_DCDCLPVCTRL_RESETVALUE 0x00000168UL /**< Default value for EMU_DCDCLPVCTRL */
AnnaBridge 170:e95d10626187 1091 #define _EMU_DCDCLPVCTRL_MASK 0x000001FFUL /**< Mask for EMU_DCDCLPVCTRL */
AnnaBridge 170:e95d10626187 1092 #define EMU_DCDCLPVCTRL_LPATT (0x1UL << 0) /**< Low power feedback attenuation */
AnnaBridge 170:e95d10626187 1093 #define _EMU_DCDCLPVCTRL_LPATT_SHIFT 0 /**< Shift value for EMU_LPATT */
AnnaBridge 170:e95d10626187 1094 #define _EMU_DCDCLPVCTRL_LPATT_MASK 0x1UL /**< Bit mask for EMU_LPATT */
AnnaBridge 170:e95d10626187 1095 #define _EMU_DCDCLPVCTRL_LPATT_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
AnnaBridge 170:e95d10626187 1096 #define _EMU_DCDCLPVCTRL_LPATT_DIV4 0x00000000UL /**< Mode DIV4 for EMU_DCDCLPVCTRL */
AnnaBridge 170:e95d10626187 1097 #define _EMU_DCDCLPVCTRL_LPATT_DIV8 0x00000001UL /**< Mode DIV8 for EMU_DCDCLPVCTRL */
AnnaBridge 170:e95d10626187 1098 #define EMU_DCDCLPVCTRL_LPATT_DEFAULT (_EMU_DCDCLPVCTRL_LPATT_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
AnnaBridge 170:e95d10626187 1099 #define EMU_DCDCLPVCTRL_LPATT_DIV4 (_EMU_DCDCLPVCTRL_LPATT_DIV4 << 0) /**< Shifted mode DIV4 for EMU_DCDCLPVCTRL */
AnnaBridge 170:e95d10626187 1100 #define EMU_DCDCLPVCTRL_LPATT_DIV8 (_EMU_DCDCLPVCTRL_LPATT_DIV8 << 0) /**< Shifted mode DIV8 for EMU_DCDCLPVCTRL */
AnnaBridge 170:e95d10626187 1101 #define _EMU_DCDCLPVCTRL_LPVREF_SHIFT 1 /**< Shift value for EMU_LPVREF */
AnnaBridge 170:e95d10626187 1102 #define _EMU_DCDCLPVCTRL_LPVREF_MASK 0x1FEUL /**< Bit mask for EMU_LPVREF */
AnnaBridge 170:e95d10626187 1103 #define _EMU_DCDCLPVCTRL_LPVREF_DEFAULT 0x000000B4UL /**< Mode DEFAULT for EMU_DCDCLPVCTRL */
AnnaBridge 170:e95d10626187 1104 #define EMU_DCDCLPVCTRL_LPVREF_DEFAULT (_EMU_DCDCLPVCTRL_LPVREF_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_DCDCLPVCTRL */
AnnaBridge 170:e95d10626187 1105
AnnaBridge 170:e95d10626187 1106 /* Bit fields for EMU DCDCLPCTRL */
AnnaBridge 170:e95d10626187 1107 #define _EMU_DCDCLPCTRL_RESETVALUE 0x03000000UL /**< Default value for EMU_DCDCLPCTRL */
AnnaBridge 170:e95d10626187 1108 #define _EMU_DCDCLPCTRL_MASK 0x0700F000UL /**< Mask for EMU_DCDCLPCTRL */
AnnaBridge 170:e95d10626187 1109 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM234H */
AnnaBridge 170:e95d10626187 1110 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM234H */
AnnaBridge 170:e95d10626187 1111 #define _EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
AnnaBridge 170:e95d10626187 1112 #define EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT (_EMU_DCDCLPCTRL_LPCMPHYSSELEM234H_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
AnnaBridge 170:e95d10626187 1113 #define EMU_DCDCLPCTRL_LPVREFDUTYEN (0x1UL << 24) /**< LP mode duty cycling enable */
AnnaBridge 170:e95d10626187 1114 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_SHIFT 24 /**< Shift value for EMU_LPVREFDUTYEN */
AnnaBridge 170:e95d10626187 1115 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_MASK 0x1000000UL /**< Bit mask for EMU_LPVREFDUTYEN */
AnnaBridge 170:e95d10626187 1116 #define _EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
AnnaBridge 170:e95d10626187 1117 #define EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT (_EMU_DCDCLPCTRL_LPVREFDUTYEN_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
AnnaBridge 170:e95d10626187 1118 #define _EMU_DCDCLPCTRL_LPBLANK_SHIFT 25 /**< Shift value for EMU_LPBLANK */
AnnaBridge 170:e95d10626187 1119 #define _EMU_DCDCLPCTRL_LPBLANK_MASK 0x6000000UL /**< Bit mask for EMU_LPBLANK */
AnnaBridge 170:e95d10626187 1120 #define _EMU_DCDCLPCTRL_LPBLANK_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_DCDCLPCTRL */
AnnaBridge 170:e95d10626187 1121 #define EMU_DCDCLPCTRL_LPBLANK_DEFAULT (_EMU_DCDCLPCTRL_LPBLANK_DEFAULT << 25) /**< Shifted mode DEFAULT for EMU_DCDCLPCTRL */
AnnaBridge 170:e95d10626187 1122
AnnaBridge 170:e95d10626187 1123 /* Bit fields for EMU DCDCLNFREQCTRL */
AnnaBridge 170:e95d10626187 1124 #define _EMU_DCDCLNFREQCTRL_RESETVALUE 0x10000000UL /**< Default value for EMU_DCDCLNFREQCTRL */
AnnaBridge 170:e95d10626187 1125 #define _EMU_DCDCLNFREQCTRL_MASK 0x1F000007UL /**< Mask for EMU_DCDCLNFREQCTRL */
AnnaBridge 170:e95d10626187 1126 #define _EMU_DCDCLNFREQCTRL_RCOBAND_SHIFT 0 /**< Shift value for EMU_RCOBAND */
AnnaBridge 170:e95d10626187 1127 #define _EMU_DCDCLNFREQCTRL_RCOBAND_MASK 0x7UL /**< Bit mask for EMU_RCOBAND */
AnnaBridge 170:e95d10626187 1128 #define _EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
AnnaBridge 170:e95d10626187 1129 #define EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOBAND_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
AnnaBridge 170:e95d10626187 1130 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_SHIFT 24 /**< Shift value for EMU_RCOTRIM */
AnnaBridge 170:e95d10626187 1131 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_MASK 0x1F000000UL /**< Bit mask for EMU_RCOTRIM */
AnnaBridge 170:e95d10626187 1132 #define _EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT 0x00000010UL /**< Mode DEFAULT for EMU_DCDCLNFREQCTRL */
AnnaBridge 170:e95d10626187 1133 #define EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT (_EMU_DCDCLNFREQCTRL_RCOTRIM_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_DCDCLNFREQCTRL */
AnnaBridge 170:e95d10626187 1134
AnnaBridge 170:e95d10626187 1135 /* Bit fields for EMU DCDCSYNC */
AnnaBridge 170:e95d10626187 1136 #define _EMU_DCDCSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_DCDCSYNC */
AnnaBridge 170:e95d10626187 1137 #define _EMU_DCDCSYNC_MASK 0x00000001UL /**< Mask for EMU_DCDCSYNC */
AnnaBridge 170:e95d10626187 1138 #define EMU_DCDCSYNC_DCDCCTRLBUSY (0x1UL << 0) /**< DCDC CTRL Register Transfer Busy. */
AnnaBridge 170:e95d10626187 1139 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_SHIFT 0 /**< Shift value for EMU_DCDCCTRLBUSY */
AnnaBridge 170:e95d10626187 1140 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_MASK 0x1UL /**< Bit mask for EMU_DCDCCTRLBUSY */
AnnaBridge 170:e95d10626187 1141 #define _EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCSYNC */
AnnaBridge 170:e95d10626187 1142 #define EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT (_EMU_DCDCSYNC_DCDCCTRLBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_DCDCSYNC */
AnnaBridge 170:e95d10626187 1143
AnnaBridge 170:e95d10626187 1144 /* Bit fields for EMU VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1145 #define _EMU_VMONAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1146 #define _EMU_VMONAVDDCTRL_MASK 0x00FFFF0DUL /**< Mask for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1147 #define EMU_VMONAVDDCTRL_EN (0x1UL << 0) /**< Enable */
AnnaBridge 170:e95d10626187 1148 #define _EMU_VMONAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
AnnaBridge 170:e95d10626187 1149 #define _EMU_VMONAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
AnnaBridge 170:e95d10626187 1150 #define _EMU_VMONAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1151 #define EMU_VMONAVDDCTRL_EN_DEFAULT (_EMU_VMONAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1152 #define EMU_VMONAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
AnnaBridge 170:e95d10626187 1153 #define _EMU_VMONAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
AnnaBridge 170:e95d10626187 1154 #define _EMU_VMONAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
AnnaBridge 170:e95d10626187 1155 #define _EMU_VMONAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1156 #define EMU_VMONAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1157 #define EMU_VMONAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
AnnaBridge 170:e95d10626187 1158 #define _EMU_VMONAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
AnnaBridge 170:e95d10626187 1159 #define _EMU_VMONAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
AnnaBridge 170:e95d10626187 1160 #define _EMU_VMONAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1161 #define EMU_VMONAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1162 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_SHIFT 8 /**< Shift value for EMU_FALLTHRESFINE */
AnnaBridge 170:e95d10626187 1163 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_MASK 0xF00UL /**< Bit mask for EMU_FALLTHRESFINE */
AnnaBridge 170:e95d10626187 1164 #define _EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1165 #define EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1166 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_SHIFT 12 /**< Shift value for EMU_FALLTHRESCOARSE */
AnnaBridge 170:e95d10626187 1167 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_FALLTHRESCOARSE */
AnnaBridge 170:e95d10626187 1168 #define _EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1169 #define EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_FALLTHRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1170 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_SHIFT 16 /**< Shift value for EMU_RISETHRESFINE */
AnnaBridge 170:e95d10626187 1171 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_MASK 0xF0000UL /**< Bit mask for EMU_RISETHRESFINE */
AnnaBridge 170:e95d10626187 1172 #define _EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1173 #define EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESFINE_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1174 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_SHIFT 20 /**< Shift value for EMU_RISETHRESCOARSE */
AnnaBridge 170:e95d10626187 1175 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_MASK 0xF00000UL /**< Bit mask for EMU_RISETHRESCOARSE */
AnnaBridge 170:e95d10626187 1176 #define _EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1177 #define EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT (_EMU_VMONAVDDCTRL_RISETHRESCOARSE_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_VMONAVDDCTRL */
AnnaBridge 170:e95d10626187 1178
AnnaBridge 170:e95d10626187 1179 /* Bit fields for EMU VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1180 #define _EMU_VMONALTAVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1181 #define _EMU_VMONALTAVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1182 #define EMU_VMONALTAVDDCTRL_EN (0x1UL << 0) /**< Enable */
AnnaBridge 170:e95d10626187 1183 #define _EMU_VMONALTAVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
AnnaBridge 170:e95d10626187 1184 #define _EMU_VMONALTAVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
AnnaBridge 170:e95d10626187 1185 #define _EMU_VMONALTAVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1186 #define EMU_VMONALTAVDDCTRL_EN_DEFAULT (_EMU_VMONALTAVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1187 #define EMU_VMONALTAVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
AnnaBridge 170:e95d10626187 1188 #define _EMU_VMONALTAVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
AnnaBridge 170:e95d10626187 1189 #define _EMU_VMONALTAVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
AnnaBridge 170:e95d10626187 1190 #define _EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1191 #define EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT (_EMU_VMONALTAVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1192 #define EMU_VMONALTAVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
AnnaBridge 170:e95d10626187 1193 #define _EMU_VMONALTAVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
AnnaBridge 170:e95d10626187 1194 #define _EMU_VMONALTAVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
AnnaBridge 170:e95d10626187 1195 #define _EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1196 #define EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT (_EMU_VMONALTAVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1197 #define _EMU_VMONALTAVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
AnnaBridge 170:e95d10626187 1198 #define _EMU_VMONALTAVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
AnnaBridge 170:e95d10626187 1199 #define _EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1200 #define EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1201 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
AnnaBridge 170:e95d10626187 1202 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
AnnaBridge 170:e95d10626187 1203 #define _EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1204 #define EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONALTAVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONALTAVDDCTRL */
AnnaBridge 170:e95d10626187 1205
AnnaBridge 170:e95d10626187 1206 /* Bit fields for EMU VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1207 #define _EMU_VMONDVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1208 #define _EMU_VMONDVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1209 #define EMU_VMONDVDDCTRL_EN (0x1UL << 0) /**< Enable */
AnnaBridge 170:e95d10626187 1210 #define _EMU_VMONDVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
AnnaBridge 170:e95d10626187 1211 #define _EMU_VMONDVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
AnnaBridge 170:e95d10626187 1212 #define _EMU_VMONDVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1213 #define EMU_VMONDVDDCTRL_EN_DEFAULT (_EMU_VMONDVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1214 #define EMU_VMONDVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
AnnaBridge 170:e95d10626187 1215 #define _EMU_VMONDVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
AnnaBridge 170:e95d10626187 1216 #define _EMU_VMONDVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
AnnaBridge 170:e95d10626187 1217 #define _EMU_VMONDVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1218 #define EMU_VMONDVDDCTRL_RISEWU_DEFAULT (_EMU_VMONDVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1219 #define EMU_VMONDVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
AnnaBridge 170:e95d10626187 1220 #define _EMU_VMONDVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
AnnaBridge 170:e95d10626187 1221 #define _EMU_VMONDVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
AnnaBridge 170:e95d10626187 1222 #define _EMU_VMONDVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1223 #define EMU_VMONDVDDCTRL_FALLWU_DEFAULT (_EMU_VMONDVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1224 #define _EMU_VMONDVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
AnnaBridge 170:e95d10626187 1225 #define _EMU_VMONDVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
AnnaBridge 170:e95d10626187 1226 #define _EMU_VMONDVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1227 #define EMU_VMONDVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONDVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1228 #define _EMU_VMONDVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
AnnaBridge 170:e95d10626187 1229 #define _EMU_VMONDVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
AnnaBridge 170:e95d10626187 1230 #define _EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1231 #define EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONDVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONDVDDCTRL */
AnnaBridge 170:e95d10626187 1232
AnnaBridge 170:e95d10626187 1233 /* Bit fields for EMU VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1234 #define _EMU_VMONIO0CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1235 #define _EMU_VMONIO0CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1236 #define EMU_VMONIO0CTRL_EN (0x1UL << 0) /**< Enable */
AnnaBridge 170:e95d10626187 1237 #define _EMU_VMONIO0CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
AnnaBridge 170:e95d10626187 1238 #define _EMU_VMONIO0CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
AnnaBridge 170:e95d10626187 1239 #define _EMU_VMONIO0CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1240 #define EMU_VMONIO0CTRL_EN_DEFAULT (_EMU_VMONIO0CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1241 #define EMU_VMONIO0CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
AnnaBridge 170:e95d10626187 1242 #define _EMU_VMONIO0CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
AnnaBridge 170:e95d10626187 1243 #define _EMU_VMONIO0CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
AnnaBridge 170:e95d10626187 1244 #define _EMU_VMONIO0CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1245 #define EMU_VMONIO0CTRL_RISEWU_DEFAULT (_EMU_VMONIO0CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1246 #define EMU_VMONIO0CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
AnnaBridge 170:e95d10626187 1247 #define _EMU_VMONIO0CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
AnnaBridge 170:e95d10626187 1248 #define _EMU_VMONIO0CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
AnnaBridge 170:e95d10626187 1249 #define _EMU_VMONIO0CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1250 #define EMU_VMONIO0CTRL_FALLWU_DEFAULT (_EMU_VMONIO0CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1251 #define EMU_VMONIO0CTRL_RETDIS (0x1UL << 4) /**< EM4 IO0 Retention disable */
AnnaBridge 170:e95d10626187 1252 #define _EMU_VMONIO0CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */
AnnaBridge 170:e95d10626187 1253 #define _EMU_VMONIO0CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */
AnnaBridge 170:e95d10626187 1254 #define _EMU_VMONIO0CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1255 #define EMU_VMONIO0CTRL_RETDIS_DEFAULT (_EMU_VMONIO0CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1256 #define _EMU_VMONIO0CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
AnnaBridge 170:e95d10626187 1257 #define _EMU_VMONIO0CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
AnnaBridge 170:e95d10626187 1258 #define _EMU_VMONIO0CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1259 #define EMU_VMONIO0CTRL_THRESFINE_DEFAULT (_EMU_VMONIO0CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1260 #define _EMU_VMONIO0CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
AnnaBridge 170:e95d10626187 1261 #define _EMU_VMONIO0CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
AnnaBridge 170:e95d10626187 1262 #define _EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1263 #define EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO0CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO0CTRL */
AnnaBridge 170:e95d10626187 1264
AnnaBridge 170:e95d10626187 1265 /* Bit fields for EMU VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1266 #define _EMU_VMONIO1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1267 #define _EMU_VMONIO1CTRL_MASK 0x0000FF1DUL /**< Mask for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1268 #define EMU_VMONIO1CTRL_EN (0x1UL << 0) /**< Enable */
AnnaBridge 170:e95d10626187 1269 #define _EMU_VMONIO1CTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
AnnaBridge 170:e95d10626187 1270 #define _EMU_VMONIO1CTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
AnnaBridge 170:e95d10626187 1271 #define _EMU_VMONIO1CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1272 #define EMU_VMONIO1CTRL_EN_DEFAULT (_EMU_VMONIO1CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1273 #define EMU_VMONIO1CTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
AnnaBridge 170:e95d10626187 1274 #define _EMU_VMONIO1CTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
AnnaBridge 170:e95d10626187 1275 #define _EMU_VMONIO1CTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
AnnaBridge 170:e95d10626187 1276 #define _EMU_VMONIO1CTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1277 #define EMU_VMONIO1CTRL_RISEWU_DEFAULT (_EMU_VMONIO1CTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1278 #define EMU_VMONIO1CTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
AnnaBridge 170:e95d10626187 1279 #define _EMU_VMONIO1CTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
AnnaBridge 170:e95d10626187 1280 #define _EMU_VMONIO1CTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
AnnaBridge 170:e95d10626187 1281 #define _EMU_VMONIO1CTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1282 #define EMU_VMONIO1CTRL_FALLWU_DEFAULT (_EMU_VMONIO1CTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1283 #define EMU_VMONIO1CTRL_RETDIS (0x1UL << 4) /**< EM4 IO1 Retention disable */
AnnaBridge 170:e95d10626187 1284 #define _EMU_VMONIO1CTRL_RETDIS_SHIFT 4 /**< Shift value for EMU_RETDIS */
AnnaBridge 170:e95d10626187 1285 #define _EMU_VMONIO1CTRL_RETDIS_MASK 0x10UL /**< Bit mask for EMU_RETDIS */
AnnaBridge 170:e95d10626187 1286 #define _EMU_VMONIO1CTRL_RETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1287 #define EMU_VMONIO1CTRL_RETDIS_DEFAULT (_EMU_VMONIO1CTRL_RETDIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1288 #define _EMU_VMONIO1CTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
AnnaBridge 170:e95d10626187 1289 #define _EMU_VMONIO1CTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
AnnaBridge 170:e95d10626187 1290 #define _EMU_VMONIO1CTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1291 #define EMU_VMONIO1CTRL_THRESFINE_DEFAULT (_EMU_VMONIO1CTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1292 #define _EMU_VMONIO1CTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
AnnaBridge 170:e95d10626187 1293 #define _EMU_VMONIO1CTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
AnnaBridge 170:e95d10626187 1294 #define _EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1295 #define EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT (_EMU_VMONIO1CTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONIO1CTRL */
AnnaBridge 170:e95d10626187 1296
AnnaBridge 170:e95d10626187 1297 /* Bit fields for EMU VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1298 #define _EMU_VMONBUVDDCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1299 #define _EMU_VMONBUVDDCTRL_MASK 0x0000FF0DUL /**< Mask for EMU_VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1300 #define EMU_VMONBUVDDCTRL_EN (0x1UL << 0) /**< Enable */
AnnaBridge 170:e95d10626187 1301 #define _EMU_VMONBUVDDCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
AnnaBridge 170:e95d10626187 1302 #define _EMU_VMONBUVDDCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
AnnaBridge 170:e95d10626187 1303 #define _EMU_VMONBUVDDCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1304 #define EMU_VMONBUVDDCTRL_EN_DEFAULT (_EMU_VMONBUVDDCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1305 #define EMU_VMONBUVDDCTRL_RISEWU (0x1UL << 2) /**< Rise Wakeup */
AnnaBridge 170:e95d10626187 1306 #define _EMU_VMONBUVDDCTRL_RISEWU_SHIFT 2 /**< Shift value for EMU_RISEWU */
AnnaBridge 170:e95d10626187 1307 #define _EMU_VMONBUVDDCTRL_RISEWU_MASK 0x4UL /**< Bit mask for EMU_RISEWU */
AnnaBridge 170:e95d10626187 1308 #define _EMU_VMONBUVDDCTRL_RISEWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1309 #define EMU_VMONBUVDDCTRL_RISEWU_DEFAULT (_EMU_VMONBUVDDCTRL_RISEWU_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1310 #define EMU_VMONBUVDDCTRL_FALLWU (0x1UL << 3) /**< Fall Wakeup */
AnnaBridge 170:e95d10626187 1311 #define _EMU_VMONBUVDDCTRL_FALLWU_SHIFT 3 /**< Shift value for EMU_FALLWU */
AnnaBridge 170:e95d10626187 1312 #define _EMU_VMONBUVDDCTRL_FALLWU_MASK 0x8UL /**< Bit mask for EMU_FALLWU */
AnnaBridge 170:e95d10626187 1313 #define _EMU_VMONBUVDDCTRL_FALLWU_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1314 #define EMU_VMONBUVDDCTRL_FALLWU_DEFAULT (_EMU_VMONBUVDDCTRL_FALLWU_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1315 #define _EMU_VMONBUVDDCTRL_THRESFINE_SHIFT 8 /**< Shift value for EMU_THRESFINE */
AnnaBridge 170:e95d10626187 1316 #define _EMU_VMONBUVDDCTRL_THRESFINE_MASK 0xF00UL /**< Bit mask for EMU_THRESFINE */
AnnaBridge 170:e95d10626187 1317 #define _EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1318 #define EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESFINE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1319 #define _EMU_VMONBUVDDCTRL_THRESCOARSE_SHIFT 12 /**< Shift value for EMU_THRESCOARSE */
AnnaBridge 170:e95d10626187 1320 #define _EMU_VMONBUVDDCTRL_THRESCOARSE_MASK 0xF000UL /**< Bit mask for EMU_THRESCOARSE */
AnnaBridge 170:e95d10626187 1321 #define _EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1322 #define EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT (_EMU_VMONBUVDDCTRL_THRESCOARSE_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_VMONBUVDDCTRL */
AnnaBridge 170:e95d10626187 1323
AnnaBridge 170:e95d10626187 1324 /* Bit fields for EMU RAM1CTRL */
AnnaBridge 170:e95d10626187 1325 #define _EMU_RAM1CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1326 #define _EMU_RAM1CTRL_MASK 0x000000FFUL /**< Mask for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1327 #define _EMU_RAM1CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */
AnnaBridge 170:e95d10626187 1328 #define _EMU_RAM1CTRL_RAMPOWERDOWN_MASK 0xFFUL /**< Bit mask for EMU_RAMPOWERDOWN */
AnnaBridge 170:e95d10626187 1329 #define _EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1330 #define _EMU_RAM1CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1331 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 0x00000080UL /**< Mode BLK7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1332 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 0x000000C0UL /**< Mode BLK6TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1333 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 0x000000E0UL /**< Mode BLK5TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1334 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 0x000000F0UL /**< Mode BLK4TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1335 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 0x000000F8UL /**< Mode BLK3TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1336 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 0x000000FCUL /**< Mode BLK2TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1337 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 0x000000FEUL /**< Mode BLK1TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1338 #define _EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 0x000000FFUL /**< Mode BLK0TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1339 #define EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM1CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1340 #define EMU_RAM1CTRL_RAMPOWERDOWN_NONE (_EMU_RAM1CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1341 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK7 << 0) /**< Shifted mode BLK7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1342 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK6TO7 << 0) /**< Shifted mode BLK6TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1343 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK5TO7 << 0) /**< Shifted mode BLK5TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1344 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK4TO7 << 0) /**< Shifted mode BLK4TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1345 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK3TO7 << 0) /**< Shifted mode BLK3TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1346 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK2TO7 << 0) /**< Shifted mode BLK2TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1347 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK1TO7 << 0) /**< Shifted mode BLK1TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1348 #define EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 (_EMU_RAM1CTRL_RAMPOWERDOWN_BLK0TO7 << 0) /**< Shifted mode BLK0TO7 for EMU_RAM1CTRL */
AnnaBridge 170:e95d10626187 1349
AnnaBridge 170:e95d10626187 1350 /* Bit fields for EMU RAM2CTRL */
AnnaBridge 170:e95d10626187 1351 #define _EMU_RAM2CTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1352 #define _EMU_RAM2CTRL_MASK 0x0000000FUL /**< Mask for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1353 #define _EMU_RAM2CTRL_RAMPOWERDOWN_SHIFT 0 /**< Shift value for EMU_RAMPOWERDOWN */
AnnaBridge 170:e95d10626187 1354 #define _EMU_RAM2CTRL_RAMPOWERDOWN_MASK 0xFUL /**< Bit mask for EMU_RAMPOWERDOWN */
AnnaBridge 170:e95d10626187 1355 #define _EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1356 #define _EMU_RAM2CTRL_RAMPOWERDOWN_NONE 0x00000000UL /**< Mode NONE for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1357 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 0x00000008UL /**< Mode BLK3 for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1358 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 0x0000000CUL /**< Mode BLK2TO3 for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1359 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 0x0000000EUL /**< Mode BLK1TO3 for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1360 #define _EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 0x0000000FUL /**< Mode BLK0TO3 for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1361 #define EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT (_EMU_RAM2CTRL_RAMPOWERDOWN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1362 #define EMU_RAM2CTRL_RAMPOWERDOWN_NONE (_EMU_RAM2CTRL_RAMPOWERDOWN_NONE << 0) /**< Shifted mode NONE for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1363 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK3 << 0) /**< Shifted mode BLK3 for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1364 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK2TO3 << 0) /**< Shifted mode BLK2TO3 for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1365 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK1TO3 << 0) /**< Shifted mode BLK1TO3 for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1366 #define EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 (_EMU_RAM2CTRL_RAMPOWERDOWN_BLK0TO3 << 0) /**< Shifted mode BLK0TO3 for EMU_RAM2CTRL */
AnnaBridge 170:e95d10626187 1367
AnnaBridge 170:e95d10626187 1368 /* Bit fields for EMU BUCTRL */
AnnaBridge 170:e95d10626187 1369 #define _EMU_BUCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1370 #define _EMU_BUCTRL_MASK 0x80333307UL /**< Mask for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1371 #define EMU_BUCTRL_EN (0x1UL << 0) /**< Enable backup mode */
AnnaBridge 170:e95d10626187 1372 #define _EMU_BUCTRL_EN_SHIFT 0 /**< Shift value for EMU_EN */
AnnaBridge 170:e95d10626187 1373 #define _EMU_BUCTRL_EN_MASK 0x1UL /**< Bit mask for EMU_EN */
AnnaBridge 170:e95d10626187 1374 #define _EMU_BUCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1375 #define EMU_BUCTRL_EN_DEFAULT (_EMU_BUCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1376 #define EMU_BUCTRL_STATEN (0x1UL << 1) /**< Enable backup mode status export. */
AnnaBridge 170:e95d10626187 1377 #define _EMU_BUCTRL_STATEN_SHIFT 1 /**< Shift value for EMU_STATEN */
AnnaBridge 170:e95d10626187 1378 #define _EMU_BUCTRL_STATEN_MASK 0x2UL /**< Bit mask for EMU_STATEN */
AnnaBridge 170:e95d10626187 1379 #define _EMU_BUCTRL_STATEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1380 #define EMU_BUCTRL_STATEN_DEFAULT (_EMU_BUCTRL_STATEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1381 #define EMU_BUCTRL_BUVINPROBEEN (0x1UL << 2) /**< Enable BU_VIN probing. */
AnnaBridge 170:e95d10626187 1382 #define _EMU_BUCTRL_BUVINPROBEEN_SHIFT 2 /**< Shift value for EMU_BUVINPROBEEN */
AnnaBridge 170:e95d10626187 1383 #define _EMU_BUCTRL_BUVINPROBEEN_MASK 0x4UL /**< Bit mask for EMU_BUVINPROBEEN */
AnnaBridge 170:e95d10626187 1384 #define _EMU_BUCTRL_BUVINPROBEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1385 #define EMU_BUCTRL_BUVINPROBEEN_DEFAULT (_EMU_BUCTRL_BUVINPROBEEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1386 #define _EMU_BUCTRL_VOUTRES_SHIFT 8 /**< Shift value for EMU_VOUTRES */
AnnaBridge 170:e95d10626187 1387 #define _EMU_BUCTRL_VOUTRES_MASK 0x300UL /**< Bit mask for EMU_VOUTRES */
AnnaBridge 170:e95d10626187 1388 #define _EMU_BUCTRL_VOUTRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1389 #define _EMU_BUCTRL_VOUTRES_DIS 0x00000000UL /**< Mode DIS for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1390 #define _EMU_BUCTRL_VOUTRES_WEAK 0x00000001UL /**< Mode WEAK for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1391 #define _EMU_BUCTRL_VOUTRES_MED 0x00000002UL /**< Mode MED for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1392 #define _EMU_BUCTRL_VOUTRES_STRONG 0x00000003UL /**< Mode STRONG for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1393 #define EMU_BUCTRL_VOUTRES_DEFAULT (_EMU_BUCTRL_VOUTRES_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1394 #define EMU_BUCTRL_VOUTRES_DIS (_EMU_BUCTRL_VOUTRES_DIS << 8) /**< Shifted mode DIS for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1395 #define EMU_BUCTRL_VOUTRES_WEAK (_EMU_BUCTRL_VOUTRES_WEAK << 8) /**< Shifted mode WEAK for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1396 #define EMU_BUCTRL_VOUTRES_MED (_EMU_BUCTRL_VOUTRES_MED << 8) /**< Shifted mode MED for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1397 #define EMU_BUCTRL_VOUTRES_STRONG (_EMU_BUCTRL_VOUTRES_STRONG << 8) /**< Shifted mode STRONG for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1398 #define _EMU_BUCTRL_PWRRES_SHIFT 12 /**< Shift value for EMU_PWRRES */
AnnaBridge 170:e95d10626187 1399 #define _EMU_BUCTRL_PWRRES_MASK 0x3000UL /**< Bit mask for EMU_PWRRES */
AnnaBridge 170:e95d10626187 1400 #define _EMU_BUCTRL_PWRRES_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1401 #define _EMU_BUCTRL_PWRRES_RES0 0x00000000UL /**< Mode RES0 for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1402 #define _EMU_BUCTRL_PWRRES_RES1 0x00000001UL /**< Mode RES1 for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1403 #define _EMU_BUCTRL_PWRRES_RES2 0x00000002UL /**< Mode RES2 for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1404 #define _EMU_BUCTRL_PWRRES_RES3 0x00000003UL /**< Mode RES3 for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1405 #define EMU_BUCTRL_PWRRES_DEFAULT (_EMU_BUCTRL_PWRRES_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1406 #define EMU_BUCTRL_PWRRES_RES0 (_EMU_BUCTRL_PWRRES_RES0 << 12) /**< Shifted mode RES0 for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1407 #define EMU_BUCTRL_PWRRES_RES1 (_EMU_BUCTRL_PWRRES_RES1 << 12) /**< Shifted mode RES1 for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1408 #define EMU_BUCTRL_PWRRES_RES2 (_EMU_BUCTRL_PWRRES_RES2 << 12) /**< Shifted mode RES2 for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1409 #define EMU_BUCTRL_PWRRES_RES3 (_EMU_BUCTRL_PWRRES_RES3 << 12) /**< Shifted mode RES3 for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1410 #define _EMU_BUCTRL_BUACTPWRCON_SHIFT 16 /**< Shift value for EMU_BUACTPWRCON */
AnnaBridge 170:e95d10626187 1411 #define _EMU_BUCTRL_BUACTPWRCON_MASK 0x30000UL /**< Bit mask for EMU_BUACTPWRCON */
AnnaBridge 170:e95d10626187 1412 #define _EMU_BUCTRL_BUACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1413 #define _EMU_BUCTRL_BUACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1414 #define _EMU_BUCTRL_BUACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1415 #define _EMU_BUCTRL_BUACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1416 #define _EMU_BUCTRL_BUACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1417 #define EMU_BUCTRL_BUACTPWRCON_DEFAULT (_EMU_BUCTRL_BUACTPWRCON_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1418 #define EMU_BUCTRL_BUACTPWRCON_NONE (_EMU_BUCTRL_BUACTPWRCON_NONE << 16) /**< Shifted mode NONE for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1419 #define EMU_BUCTRL_BUACTPWRCON_MAINBU (_EMU_BUCTRL_BUACTPWRCON_MAINBU << 16) /**< Shifted mode MAINBU for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1420 #define EMU_BUCTRL_BUACTPWRCON_BUMAIN (_EMU_BUCTRL_BUACTPWRCON_BUMAIN << 16) /**< Shifted mode BUMAIN for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1421 #define EMU_BUCTRL_BUACTPWRCON_NODIODE (_EMU_BUCTRL_BUACTPWRCON_NODIODE << 16) /**< Shifted mode NODIODE for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1422 #define _EMU_BUCTRL_BUINACTPWRCON_SHIFT 20 /**< Shift value for EMU_BUINACTPWRCON */
AnnaBridge 170:e95d10626187 1423 #define _EMU_BUCTRL_BUINACTPWRCON_MASK 0x300000UL /**< Bit mask for EMU_BUINACTPWRCON */
AnnaBridge 170:e95d10626187 1424 #define _EMU_BUCTRL_BUINACTPWRCON_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1425 #define _EMU_BUCTRL_BUINACTPWRCON_NONE 0x00000000UL /**< Mode NONE for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1426 #define _EMU_BUCTRL_BUINACTPWRCON_MAINBU 0x00000001UL /**< Mode MAINBU for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1427 #define _EMU_BUCTRL_BUINACTPWRCON_BUMAIN 0x00000002UL /**< Mode BUMAIN for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1428 #define _EMU_BUCTRL_BUINACTPWRCON_NODIODE 0x00000003UL /**< Mode NODIODE for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1429 #define EMU_BUCTRL_BUINACTPWRCON_DEFAULT (_EMU_BUCTRL_BUINACTPWRCON_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1430 #define EMU_BUCTRL_BUINACTPWRCON_NONE (_EMU_BUCTRL_BUINACTPWRCON_NONE << 20) /**< Shifted mode NONE for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1431 #define EMU_BUCTRL_BUINACTPWRCON_MAINBU (_EMU_BUCTRL_BUINACTPWRCON_MAINBU << 20) /**< Shifted mode MAINBU for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1432 #define EMU_BUCTRL_BUINACTPWRCON_BUMAIN (_EMU_BUCTRL_BUINACTPWRCON_BUMAIN << 20) /**< Shifted mode BUMAIN for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1433 #define EMU_BUCTRL_BUINACTPWRCON_NODIODE (_EMU_BUCTRL_BUINACTPWRCON_NODIODE << 20) /**< Shifted mode NODIODE for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1434 #define EMU_BUCTRL_DISMAXCOMP (0x1UL << 31) /**< Disable MAIN-BU comparator */
AnnaBridge 170:e95d10626187 1435 #define _EMU_BUCTRL_DISMAXCOMP_SHIFT 31 /**< Shift value for EMU_DISMAXCOMP */
AnnaBridge 170:e95d10626187 1436 #define _EMU_BUCTRL_DISMAXCOMP_MASK 0x80000000UL /**< Bit mask for EMU_DISMAXCOMP */
AnnaBridge 170:e95d10626187 1437 #define _EMU_BUCTRL_DISMAXCOMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1438 #define EMU_BUCTRL_DISMAXCOMP_DEFAULT (_EMU_BUCTRL_DISMAXCOMP_DEFAULT << 31) /**< Shifted mode DEFAULT for EMU_BUCTRL */
AnnaBridge 170:e95d10626187 1439
AnnaBridge 170:e95d10626187 1440 /* Bit fields for EMU R5VCTRL */
AnnaBridge 170:e95d10626187 1441 #define _EMU_R5VCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1442 #define _EMU_R5VCTRL_MASK 0x00000307UL /**< Mask for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1443 #define EMU_R5VCTRL_BYPASS (0x1UL << 0) /**< 5V Regulator Bypass */
AnnaBridge 170:e95d10626187 1444 #define _EMU_R5VCTRL_BYPASS_SHIFT 0 /**< Shift value for EMU_BYPASS */
AnnaBridge 170:e95d10626187 1445 #define _EMU_R5VCTRL_BYPASS_MASK 0x1UL /**< Bit mask for EMU_BYPASS */
AnnaBridge 170:e95d10626187 1446 #define _EMU_R5VCTRL_BYPASS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1447 #define EMU_R5VCTRL_BYPASS_DEFAULT (_EMU_R5VCTRL_BYPASS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1448 #define EMU_R5VCTRL_EM4WUEN (0x1UL << 1) /**< Enable EM4 Wakeup due to VBUS detection */
AnnaBridge 170:e95d10626187 1449 #define _EMU_R5VCTRL_EM4WUEN_SHIFT 1 /**< Shift value for EMU_EM4WUEN */
AnnaBridge 170:e95d10626187 1450 #define _EMU_R5VCTRL_EM4WUEN_MASK 0x2UL /**< Bit mask for EMU_EM4WUEN */
AnnaBridge 170:e95d10626187 1451 #define _EMU_R5VCTRL_EM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1452 #define EMU_R5VCTRL_EM4WUEN_DEFAULT (_EMU_R5VCTRL_EM4WUEN_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1453 #define EMU_R5VCTRL_IMONEN (0x1UL << 2) /**< Enable the regulator current monitor for selected current path to either VREGI or VBUS. */
AnnaBridge 170:e95d10626187 1454 #define _EMU_R5VCTRL_IMONEN_SHIFT 2 /**< Shift value for EMU_IMONEN */
AnnaBridge 170:e95d10626187 1455 #define _EMU_R5VCTRL_IMONEN_MASK 0x4UL /**< Bit mask for EMU_IMONEN */
AnnaBridge 170:e95d10626187 1456 #define _EMU_R5VCTRL_IMONEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1457 #define EMU_R5VCTRL_IMONEN_DEFAULT (_EMU_R5VCTRL_IMONEN_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1458 #define _EMU_R5VCTRL_INPUTMODE_SHIFT 8 /**< Shift value for EMU_INPUTMODE */
AnnaBridge 170:e95d10626187 1459 #define _EMU_R5VCTRL_INPUTMODE_MASK 0x300UL /**< Bit mask for EMU_INPUTMODE */
AnnaBridge 170:e95d10626187 1460 #define _EMU_R5VCTRL_INPUTMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1461 #define _EMU_R5VCTRL_INPUTMODE_AUTO 0x00000000UL /**< Mode AUTO for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1462 #define _EMU_R5VCTRL_INPUTMODE_VBUS 0x00000001UL /**< Mode VBUS for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1463 #define _EMU_R5VCTRL_INPUTMODE_VREGI 0x00000002UL /**< Mode VREGI for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1464 #define EMU_R5VCTRL_INPUTMODE_DEFAULT (_EMU_R5VCTRL_INPUTMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1465 #define EMU_R5VCTRL_INPUTMODE_AUTO (_EMU_R5VCTRL_INPUTMODE_AUTO << 8) /**< Shifted mode AUTO for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1466 #define EMU_R5VCTRL_INPUTMODE_VBUS (_EMU_R5VCTRL_INPUTMODE_VBUS << 8) /**< Shifted mode VBUS for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1467 #define EMU_R5VCTRL_INPUTMODE_VREGI (_EMU_R5VCTRL_INPUTMODE_VREGI << 8) /**< Shifted mode VREGI for EMU_R5VCTRL */
AnnaBridge 170:e95d10626187 1468
AnnaBridge 170:e95d10626187 1469 /* Bit fields for EMU R5VADCCTRL */
AnnaBridge 170:e95d10626187 1470 #define _EMU_R5VADCCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1471 #define _EMU_R5VADCCTRL_MASK 0x0000F001UL /**< Mask for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1472 #define EMU_R5VADCCTRL_ENAMUX (0x1UL << 0) /**< Enable the 5V subsystem ADC MUX. */
AnnaBridge 170:e95d10626187 1473 #define _EMU_R5VADCCTRL_ENAMUX_SHIFT 0 /**< Shift value for EMU_ENAMUX */
AnnaBridge 170:e95d10626187 1474 #define _EMU_R5VADCCTRL_ENAMUX_MASK 0x1UL /**< Bit mask for EMU_ENAMUX */
AnnaBridge 170:e95d10626187 1475 #define _EMU_R5VADCCTRL_ENAMUX_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1476 #define EMU_R5VADCCTRL_ENAMUX_DEFAULT (_EMU_R5VADCCTRL_ENAMUX_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1477 #define _EMU_R5VADCCTRL_AMUXSEL_SHIFT 12 /**< Shift value for EMU_AMUXSEL */
AnnaBridge 170:e95d10626187 1478 #define _EMU_R5VADCCTRL_AMUXSEL_MASK 0xF000UL /**< Bit mask for EMU_AMUXSEL */
AnnaBridge 170:e95d10626187 1479 #define _EMU_R5VADCCTRL_AMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1480 #define _EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 0x00000000UL /**< Mode VBUSDIV10 for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1481 #define _EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 0x00000001UL /**< Mode VREGIDIV10 for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1482 #define _EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 0x00000002UL /**< Mode VREGODIV6 for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1483 #define _EMU_R5VADCCTRL_AMUXSEL_VREGIIMON 0x00000003UL /**< Mode VREGIIMON for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1484 #define _EMU_R5VADCCTRL_AMUXSEL_VBUSIMON 0x00000004UL /**< Mode VBUSIMON for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1485 #define EMU_R5VADCCTRL_AMUXSEL_DEFAULT (_EMU_R5VADCCTRL_AMUXSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1486 #define EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VBUSDIV10 << 12) /**< Shifted mode VBUSDIV10 for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1487 #define EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 (_EMU_R5VADCCTRL_AMUXSEL_VREGIDIV10 << 12) /**< Shifted mode VREGIDIV10 for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1488 #define EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 (_EMU_R5VADCCTRL_AMUXSEL_VREGODIV6 << 12) /**< Shifted mode VREGODIV6 for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1489 #define EMU_R5VADCCTRL_AMUXSEL_VREGIIMON (_EMU_R5VADCCTRL_AMUXSEL_VREGIIMON << 12) /**< Shifted mode VREGIIMON for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1490 #define EMU_R5VADCCTRL_AMUXSEL_VBUSIMON (_EMU_R5VADCCTRL_AMUXSEL_VBUSIMON << 12) /**< Shifted mode VBUSIMON for EMU_R5VADCCTRL */
AnnaBridge 170:e95d10626187 1491
AnnaBridge 170:e95d10626187 1492 /* Bit fields for EMU R5VOUTLEVEL */
AnnaBridge 170:e95d10626187 1493 #define _EMU_R5VOUTLEVEL_RESETVALUE 0x00000001UL /**< Default value for EMU_R5VOUTLEVEL */
AnnaBridge 170:e95d10626187 1494 #define _EMU_R5VOUTLEVEL_MASK 0x0000000FUL /**< Mask for EMU_R5VOUTLEVEL */
AnnaBridge 170:e95d10626187 1495 #define _EMU_R5VOUTLEVEL_OUTLEVEL_SHIFT 0 /**< Shift value for EMU_OUTLEVEL */
AnnaBridge 170:e95d10626187 1496 #define _EMU_R5VOUTLEVEL_OUTLEVEL_MASK 0xFUL /**< Bit mask for EMU_OUTLEVEL */
AnnaBridge 170:e95d10626187 1497 #define _EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VOUTLEVEL */
AnnaBridge 170:e95d10626187 1498 #define EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT (_EMU_R5VOUTLEVEL_OUTLEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VOUTLEVEL */
AnnaBridge 170:e95d10626187 1499
AnnaBridge 170:e95d10626187 1500 /* Bit fields for EMU R5VDETCTRL */
AnnaBridge 170:e95d10626187 1501 #define _EMU_R5VDETCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VDETCTRL */
AnnaBridge 170:e95d10626187 1502 #define _EMU_R5VDETCTRL_MASK 0x00000007UL /**< Mask for EMU_R5VDETCTRL */
AnnaBridge 170:e95d10626187 1503 #define EMU_R5VDETCTRL_VREGIDETDIS (0x1UL << 0) /**< VREGI Detector Disable */
AnnaBridge 170:e95d10626187 1504 #define _EMU_R5VDETCTRL_VREGIDETDIS_SHIFT 0 /**< Shift value for EMU_VREGIDETDIS */
AnnaBridge 170:e95d10626187 1505 #define _EMU_R5VDETCTRL_VREGIDETDIS_MASK 0x1UL /**< Bit mask for EMU_VREGIDETDIS */
AnnaBridge 170:e95d10626187 1506 #define _EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */
AnnaBridge 170:e95d10626187 1507 #define EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGIDETDIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */
AnnaBridge 170:e95d10626187 1508 #define EMU_R5VDETCTRL_VBUSDETDIS (0x1UL << 1) /**< VBUS Detector Disable */
AnnaBridge 170:e95d10626187 1509 #define _EMU_R5VDETCTRL_VBUSDETDIS_SHIFT 1 /**< Shift value for EMU_VBUSDETDIS */
AnnaBridge 170:e95d10626187 1510 #define _EMU_R5VDETCTRL_VBUSDETDIS_MASK 0x2UL /**< Bit mask for EMU_VBUSDETDIS */
AnnaBridge 170:e95d10626187 1511 #define _EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */
AnnaBridge 170:e95d10626187 1512 #define EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT (_EMU_R5VDETCTRL_VBUSDETDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */
AnnaBridge 170:e95d10626187 1513 #define EMU_R5VDETCTRL_VREGODETDIS (0x1UL << 2) /**< VREGO Detector Disable */
AnnaBridge 170:e95d10626187 1514 #define _EMU_R5VDETCTRL_VREGODETDIS_SHIFT 2 /**< Shift value for EMU_VREGODETDIS */
AnnaBridge 170:e95d10626187 1515 #define _EMU_R5VDETCTRL_VREGODETDIS_MASK 0x4UL /**< Bit mask for EMU_VREGODETDIS */
AnnaBridge 170:e95d10626187 1516 #define _EMU_R5VDETCTRL_VREGODETDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VDETCTRL */
AnnaBridge 170:e95d10626187 1517 #define EMU_R5VDETCTRL_VREGODETDIS_DEFAULT (_EMU_R5VDETCTRL_VREGODETDIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VDETCTRL */
AnnaBridge 170:e95d10626187 1518
AnnaBridge 170:e95d10626187 1519 /* Bit fields for EMU DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1520 #define _EMU_DCDCLPEM01CFG_RESETVALUE 0x00000300UL /**< Default value for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1521 #define _EMU_DCDCLPEM01CFG_MASK 0x0000F300UL /**< Mask for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1522 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_SHIFT 8 /**< Shift value for EMU_LPCMPBIASEM01 */
AnnaBridge 170:e95d10626187 1523 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_MASK 0x300UL /**< Bit mask for EMU_LPCMPBIASEM01 */
AnnaBridge 170:e95d10626187 1524 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 0x00000000UL /**< Mode BIAS0 for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1525 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 0x00000001UL /**< Mode BIAS1 for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1526 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 0x00000002UL /**< Mode BIAS2 for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1527 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT 0x00000003UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1528 #define _EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 0x00000003UL /**< Mode BIAS3 for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1529 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS0 << 8) /**< Shifted mode BIAS0 for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1530 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS1 << 8) /**< Shifted mode BIAS1 for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1531 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS2 << 8) /**< Shifted mode BIAS2 for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1532 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1533 #define EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 (_EMU_DCDCLPEM01CFG_LPCMPBIASEM01_BIAS3 << 8) /**< Shifted mode BIAS3 for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1534 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_SHIFT 12 /**< Shift value for EMU_LPCMPHYSSELEM01 */
AnnaBridge 170:e95d10626187 1535 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_MASK 0xF000UL /**< Bit mask for EMU_LPCMPHYSSELEM01 */
AnnaBridge 170:e95d10626187 1536 #define _EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1537 #define EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT (_EMU_DCDCLPEM01CFG_LPCMPHYSSELEM01_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_DCDCLPEM01CFG */
AnnaBridge 170:e95d10626187 1538
AnnaBridge 170:e95d10626187 1539 /* Bit fields for EMU R5VSTATUS */
AnnaBridge 170:e95d10626187 1540 #define _EMU_R5VSTATUS_RESETVALUE 0x00000020UL /**< Default value for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1541 #define _EMU_R5VSTATUS_MASK 0x0000003FUL /**< Mask for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1542 #define EMU_R5VSTATUS_VREGIDET (0x1UL << 0) /**< VREGI detected */
AnnaBridge 170:e95d10626187 1543 #define _EMU_R5VSTATUS_VREGIDET_SHIFT 0 /**< Shift value for EMU_VREGIDET */
AnnaBridge 170:e95d10626187 1544 #define _EMU_R5VSTATUS_VREGIDET_MASK 0x1UL /**< Bit mask for EMU_VREGIDET */
AnnaBridge 170:e95d10626187 1545 #define _EMU_R5VSTATUS_VREGIDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1546 #define EMU_R5VSTATUS_VREGIDET_DEFAULT (_EMU_R5VSTATUS_VREGIDET_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1547 #define EMU_R5VSTATUS_VBUSDET (0x1UL << 1) /**< USB VBUS detected. */
AnnaBridge 170:e95d10626187 1548 #define _EMU_R5VSTATUS_VBUSDET_SHIFT 1 /**< Shift value for EMU_VBUSDET */
AnnaBridge 170:e95d10626187 1549 #define _EMU_R5VSTATUS_VBUSDET_MASK 0x2UL /**< Bit mask for EMU_VBUSDET */
AnnaBridge 170:e95d10626187 1550 #define _EMU_R5VSTATUS_VBUSDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1551 #define EMU_R5VSTATUS_VBUSDET_DEFAULT (_EMU_R5VSTATUS_VBUSDET_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1552 #define EMU_R5VSTATUS_VREGODET (0x1UL << 2) /**< VREGO detected */
AnnaBridge 170:e95d10626187 1553 #define _EMU_R5VSTATUS_VREGODET_SHIFT 2 /**< Shift value for EMU_VREGODET */
AnnaBridge 170:e95d10626187 1554 #define _EMU_R5VSTATUS_VREGODET_MASK 0x4UL /**< Bit mask for EMU_VREGODET */
AnnaBridge 170:e95d10626187 1555 #define _EMU_R5VSTATUS_VREGODET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1556 #define EMU_R5VSTATUS_VREGODET_DEFAULT (_EMU_R5VSTATUS_VREGODET_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1557 #define EMU_R5VSTATUS_VBUSGTVREGI (0x1UL << 3) /**< Output of the supply comparator between VBUS and VREGI. */
AnnaBridge 170:e95d10626187 1558 #define _EMU_R5VSTATUS_VBUSGTVREGI_SHIFT 3 /**< Shift value for EMU_VBUSGTVREGI */
AnnaBridge 170:e95d10626187 1559 #define _EMU_R5VSTATUS_VBUSGTVREGI_MASK 0x8UL /**< Bit mask for EMU_VBUSGTVREGI */
AnnaBridge 170:e95d10626187 1560 #define _EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1561 #define EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT (_EMU_R5VSTATUS_VBUSGTVREGI_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1562 #define EMU_R5VSTATUS_LDODROPOUTDET (0x1UL << 4) /**< Regulator dropout detection */
AnnaBridge 170:e95d10626187 1563 #define _EMU_R5VSTATUS_LDODROPOUTDET_SHIFT 4 /**< Shift value for EMU_LDODROPOUTDET */
AnnaBridge 170:e95d10626187 1564 #define _EMU_R5VSTATUS_LDODROPOUTDET_MASK 0x10UL /**< Bit mask for EMU_LDODROPOUTDET */
AnnaBridge 170:e95d10626187 1565 #define _EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1566 #define EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT (_EMU_R5VSTATUS_LDODROPOUTDET_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1567 #define EMU_R5VSTATUS_COLDSTART (0x1UL << 5) /**< Indicates if the regulator is going through a cold start */
AnnaBridge 170:e95d10626187 1568 #define _EMU_R5VSTATUS_COLDSTART_SHIFT 5 /**< Shift value for EMU_COLDSTART */
AnnaBridge 170:e95d10626187 1569 #define _EMU_R5VSTATUS_COLDSTART_MASK 0x20UL /**< Bit mask for EMU_COLDSTART */
AnnaBridge 170:e95d10626187 1570 #define _EMU_R5VSTATUS_COLDSTART_DEFAULT 0x00000001UL /**< Mode DEFAULT for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1571 #define EMU_R5VSTATUS_COLDSTART_DEFAULT (_EMU_R5VSTATUS_COLDSTART_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_R5VSTATUS */
AnnaBridge 170:e95d10626187 1572
AnnaBridge 170:e95d10626187 1573 /* Bit fields for EMU R5VSYNC */
AnnaBridge 170:e95d10626187 1574 #define _EMU_R5VSYNC_RESETVALUE 0x00000000UL /**< Default value for EMU_R5VSYNC */
AnnaBridge 170:e95d10626187 1575 #define _EMU_R5VSYNC_MASK 0x00000001UL /**< Mask for EMU_R5VSYNC */
AnnaBridge 170:e95d10626187 1576 #define EMU_R5VSYNC_OUTLEVELBUSY (0x1UL << 0) /**< 5V Regulator Voltage Register Transfer Busy. */
AnnaBridge 170:e95d10626187 1577 #define _EMU_R5VSYNC_OUTLEVELBUSY_SHIFT 0 /**< Shift value for EMU_OUTLEVELBUSY */
AnnaBridge 170:e95d10626187 1578 #define _EMU_R5VSYNC_OUTLEVELBUSY_MASK 0x1UL /**< Bit mask for EMU_OUTLEVELBUSY */
AnnaBridge 170:e95d10626187 1579 #define _EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_R5VSYNC */
AnnaBridge 170:e95d10626187 1580 #define EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT (_EMU_R5VSYNC_OUTLEVELBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_R5VSYNC */
AnnaBridge 170:e95d10626187 1581
AnnaBridge 170:e95d10626187 1582 /* Bit fields for EMU EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1583 #define _EMU_EM23PERNORETAINCMD_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1584 #define _EMU_EM23PERNORETAINCMD_MASK 0x01FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1585 #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK (0x1UL << 0) /**< Clears status bit of ACMP0 and unlocks access to it */
AnnaBridge 170:e95d10626187 1586 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_SHIFT 0 /**< Shift value for EMU_ACMP0UNLOCK */
AnnaBridge 170:e95d10626187 1587 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_MASK 0x1UL /**< Bit mask for EMU_ACMP0UNLOCK */
AnnaBridge 170:e95d10626187 1588 #define _EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1589 #define EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP0UNLOCK_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1590 #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK (0x1UL << 1) /**< Clears status bit of ACMP1 and unlocks access to it */
AnnaBridge 170:e95d10626187 1591 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_SHIFT 1 /**< Shift value for EMU_ACMP1UNLOCK */
AnnaBridge 170:e95d10626187 1592 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_MASK 0x2UL /**< Bit mask for EMU_ACMP1UNLOCK */
AnnaBridge 170:e95d10626187 1593 #define _EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1594 #define EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP1UNLOCK_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1595 #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK (0x1UL << 2) /**< Clears status bit of PCNT0 and unlocks access to it */
AnnaBridge 170:e95d10626187 1596 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_SHIFT 2 /**< Shift value for EMU_PCNT0UNLOCK */
AnnaBridge 170:e95d10626187 1597 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_MASK 0x4UL /**< Bit mask for EMU_PCNT0UNLOCK */
AnnaBridge 170:e95d10626187 1598 #define _EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1599 #define EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT0UNLOCK_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1600 #define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK (0x1UL << 3) /**< Clears status bit of PCNT1 and unlocks access to it */
AnnaBridge 170:e95d10626187 1601 #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_SHIFT 3 /**< Shift value for EMU_PCNT1UNLOCK */
AnnaBridge 170:e95d10626187 1602 #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_MASK 0x8UL /**< Bit mask for EMU_PCNT1UNLOCK */
AnnaBridge 170:e95d10626187 1603 #define _EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1604 #define EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT1UNLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1605 #define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK (0x1UL << 4) /**< Clears status bit of PCNT2 and unlocks access to it */
AnnaBridge 170:e95d10626187 1606 #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_SHIFT 4 /**< Shift value for EMU_PCNT2UNLOCK */
AnnaBridge 170:e95d10626187 1607 #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_MASK 0x10UL /**< Bit mask for EMU_PCNT2UNLOCK */
AnnaBridge 170:e95d10626187 1608 #define _EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1609 #define EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_PCNT2UNLOCK_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1610 #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK (0x1UL << 5) /**< Clears status bit of I2C0 and unlocks access to it */
AnnaBridge 170:e95d10626187 1611 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_SHIFT 5 /**< Shift value for EMU_I2C0UNLOCK */
AnnaBridge 170:e95d10626187 1612 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_MASK 0x20UL /**< Bit mask for EMU_I2C0UNLOCK */
AnnaBridge 170:e95d10626187 1613 #define _EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1614 #define EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C0UNLOCK_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1615 #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK (0x1UL << 6) /**< Clears status bit of I2C1 and unlocks access to it */
AnnaBridge 170:e95d10626187 1616 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_SHIFT 6 /**< Shift value for EMU_I2C1UNLOCK */
AnnaBridge 170:e95d10626187 1617 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_MASK 0x40UL /**< Bit mask for EMU_I2C1UNLOCK */
AnnaBridge 170:e95d10626187 1618 #define _EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1619 #define EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C1UNLOCK_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1620 #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK (0x1UL << 7) /**< Clears status bit of DAC0 and unlocks access to it */
AnnaBridge 170:e95d10626187 1621 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_SHIFT 7 /**< Shift value for EMU_DAC0UNLOCK */
AnnaBridge 170:e95d10626187 1622 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_MASK 0x80UL /**< Bit mask for EMU_DAC0UNLOCK */
AnnaBridge 170:e95d10626187 1623 #define _EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1624 #define EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_DAC0UNLOCK_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1625 #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK (0x1UL << 8) /**< Clears status bit of IDAC0 and unlocks access to it */
AnnaBridge 170:e95d10626187 1626 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_SHIFT 8 /**< Shift value for EMU_IDAC0UNLOCK */
AnnaBridge 170:e95d10626187 1627 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_MASK 0x100UL /**< Bit mask for EMU_IDAC0UNLOCK */
AnnaBridge 170:e95d10626187 1628 #define _EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1629 #define EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_IDAC0UNLOCK_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1630 #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK (0x1UL << 9) /**< Clears status bit of ADC0 and unlocks access to it */
AnnaBridge 170:e95d10626187 1631 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_SHIFT 9 /**< Shift value for EMU_ADC0UNLOCK */
AnnaBridge 170:e95d10626187 1632 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_MASK 0x200UL /**< Bit mask for EMU_ADC0UNLOCK */
AnnaBridge 170:e95d10626187 1633 #define _EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1634 #define EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC0UNLOCK_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1635 #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK (0x1UL << 10) /**< Clears status bit of LETIMER0 and unlocks access to it */
AnnaBridge 170:e95d10626187 1636 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_SHIFT 10 /**< Shift value for EMU_LETIMER0UNLOCK */
AnnaBridge 170:e95d10626187 1637 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_MASK 0x400UL /**< Bit mask for EMU_LETIMER0UNLOCK */
AnnaBridge 170:e95d10626187 1638 #define _EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1639 #define EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER0UNLOCK_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1640 #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK (0x1UL << 11) /**< Clears status bit of WDOG0 and unlocks access to it */
AnnaBridge 170:e95d10626187 1641 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_SHIFT 11 /**< Shift value for EMU_WDOG0UNLOCK */
AnnaBridge 170:e95d10626187 1642 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_MASK 0x800UL /**< Bit mask for EMU_WDOG0UNLOCK */
AnnaBridge 170:e95d10626187 1643 #define _EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1644 #define EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG0UNLOCK_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1645 #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK (0x1UL << 12) /**< Clears status bit of WDOG1 and unlocks access to it */
AnnaBridge 170:e95d10626187 1646 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_SHIFT 12 /**< Shift value for EMU_WDOG1UNLOCK */
AnnaBridge 170:e95d10626187 1647 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_MASK 0x1000UL /**< Bit mask for EMU_WDOG1UNLOCK */
AnnaBridge 170:e95d10626187 1648 #define _EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1649 #define EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_WDOG1UNLOCK_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1650 #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK (0x1UL << 13) /**< Clears status bit of LESENSE0 and unlocks access to it */
AnnaBridge 170:e95d10626187 1651 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_SHIFT 13 /**< Shift value for EMU_LESENSE0UNLOCK */
AnnaBridge 170:e95d10626187 1652 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0UNLOCK */
AnnaBridge 170:e95d10626187 1653 #define _EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1654 #define EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LESENSE0UNLOCK_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1655 #define EMU_EM23PERNORETAINCMD_CSENUNLOCK (0x1UL << 14) /**< Clears status bit of CSEN and unlocks access to it */
AnnaBridge 170:e95d10626187 1656 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_SHIFT 14 /**< Shift value for EMU_CSENUNLOCK */
AnnaBridge 170:e95d10626187 1657 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_MASK 0x4000UL /**< Bit mask for EMU_CSENUNLOCK */
AnnaBridge 170:e95d10626187 1658 #define _EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1659 #define EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_CSENUNLOCK_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1660 #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK (0x1UL << 15) /**< Clears status bit of LEUART0 and unlocks access to it */
AnnaBridge 170:e95d10626187 1661 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_SHIFT 15 /**< Shift value for EMU_LEUART0UNLOCK */
AnnaBridge 170:e95d10626187 1662 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_MASK 0x8000UL /**< Bit mask for EMU_LEUART0UNLOCK */
AnnaBridge 170:e95d10626187 1663 #define _EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1664 #define EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART0UNLOCK_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1665 #define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK (0x1UL << 16) /**< Clears status bit of LEUART1 and unlocks access to it */
AnnaBridge 170:e95d10626187 1666 #define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_SHIFT 16 /**< Shift value for EMU_LEUART1UNLOCK */
AnnaBridge 170:e95d10626187 1667 #define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_MASK 0x10000UL /**< Bit mask for EMU_LEUART1UNLOCK */
AnnaBridge 170:e95d10626187 1668 #define _EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1669 #define EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LEUART1UNLOCK_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1670 #define EMU_EM23PERNORETAINCMD_LCDUNLOCK (0x1UL << 17) /**< Clears status bit of LCD and unlocks access to it */
AnnaBridge 170:e95d10626187 1671 #define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_SHIFT 17 /**< Shift value for EMU_LCDUNLOCK */
AnnaBridge 170:e95d10626187 1672 #define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_MASK 0x20000UL /**< Bit mask for EMU_LCDUNLOCK */
AnnaBridge 170:e95d10626187 1673 #define _EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1674 #define EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LCDUNLOCK_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1675 #define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK (0x1UL << 18) /**< Clears status bit of LETIMER1 and unlocks access to it */
AnnaBridge 170:e95d10626187 1676 #define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_SHIFT 18 /**< Shift value for EMU_LETIMER1UNLOCK */
AnnaBridge 170:e95d10626187 1677 #define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1UNLOCK */
AnnaBridge 170:e95d10626187 1678 #define _EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1679 #define EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_LETIMER1UNLOCK_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1680 #define EMU_EM23PERNORETAINCMD_I2C2UNLOCK (0x1UL << 19) /**< Clears status bit of I2C2 and unlocks access to it */
AnnaBridge 170:e95d10626187 1681 #define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_SHIFT 19 /**< Shift value for EMU_I2C2UNLOCK */
AnnaBridge 170:e95d10626187 1682 #define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_MASK 0x80000UL /**< Bit mask for EMU_I2C2UNLOCK */
AnnaBridge 170:e95d10626187 1683 #define _EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1684 #define EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_I2C2UNLOCK_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1685 #define EMU_EM23PERNORETAINCMD_ADC1UNLOCK (0x1UL << 20) /**< Clears status bit of ADC1 and unlocks access to it */
AnnaBridge 170:e95d10626187 1686 #define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_SHIFT 20 /**< Shift value for EMU_ADC1UNLOCK */
AnnaBridge 170:e95d10626187 1687 #define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_MASK 0x100000UL /**< Bit mask for EMU_ADC1UNLOCK */
AnnaBridge 170:e95d10626187 1688 #define _EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1689 #define EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ADC1UNLOCK_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1690 #define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK (0x1UL << 21) /**< Clears status bit of ACMP2 and unlocks access to it */
AnnaBridge 170:e95d10626187 1691 #define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_SHIFT 21 /**< Shift value for EMU_ACMP2UNLOCK */
AnnaBridge 170:e95d10626187 1692 #define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_MASK 0x200000UL /**< Bit mask for EMU_ACMP2UNLOCK */
AnnaBridge 170:e95d10626187 1693 #define _EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1694 #define EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP2UNLOCK_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1695 #define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK (0x1UL << 22) /**< Clears status bit of ACMP3 and unlocks access to it */
AnnaBridge 170:e95d10626187 1696 #define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_SHIFT 22 /**< Shift value for EMU_ACMP3UNLOCK */
AnnaBridge 170:e95d10626187 1697 #define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_MASK 0x400000UL /**< Bit mask for EMU_ACMP3UNLOCK */
AnnaBridge 170:e95d10626187 1698 #define _EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1699 #define EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_ACMP3UNLOCK_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1700 #define EMU_EM23PERNORETAINCMD_RTCUNLOCK (0x1UL << 23) /**< Clears status bit of RTC and unlocks access to it */
AnnaBridge 170:e95d10626187 1701 #define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_SHIFT 23 /**< Shift value for EMU_RTCUNLOCK */
AnnaBridge 170:e95d10626187 1702 #define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_MASK 0x800000UL /**< Bit mask for EMU_RTCUNLOCK */
AnnaBridge 170:e95d10626187 1703 #define _EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1704 #define EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_RTCUNLOCK_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1705 #define EMU_EM23PERNORETAINCMD_USBUNLOCK (0x1UL << 24) /**< clears status bit of USB and ulocks access to it */
AnnaBridge 170:e95d10626187 1706 #define _EMU_EM23PERNORETAINCMD_USBUNLOCK_SHIFT 24 /**< Shift value for EMU_USBUNLOCK */
AnnaBridge 170:e95d10626187 1707 #define _EMU_EM23PERNORETAINCMD_USBUNLOCK_MASK 0x1000000UL /**< Bit mask for EMU_USBUNLOCK */
AnnaBridge 170:e95d10626187 1708 #define _EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1709 #define EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT (_EMU_EM23PERNORETAINCMD_USBUNLOCK_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1710
AnnaBridge 170:e95d10626187 1711 /* Bit fields for EMU EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1712 #define _EMU_EM23PERNORETAINSTATUS_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1713 #define _EMU_EM23PERNORETAINSTATUS_MASK 0x01FFFFFFUL /**< Mask for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1714 #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED (0x1UL << 0) /**< Indicates if ACMP0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1715 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_SHIFT 0 /**< Shift value for EMU_ACMP0LOCKED */
AnnaBridge 170:e95d10626187 1716 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_MASK 0x1UL /**< Bit mask for EMU_ACMP0LOCKED */
AnnaBridge 170:e95d10626187 1717 #define _EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1718 #define EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP0LOCKED_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1719 #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED (0x1UL << 1) /**< Indicates if ACMP1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1720 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_SHIFT 1 /**< Shift value for EMU_ACMP1LOCKED */
AnnaBridge 170:e95d10626187 1721 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_MASK 0x2UL /**< Bit mask for EMU_ACMP1LOCKED */
AnnaBridge 170:e95d10626187 1722 #define _EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1723 #define EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP1LOCKED_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1724 #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED (0x1UL << 2) /**< Indicates if PCNT0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1725 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_SHIFT 2 /**< Shift value for EMU_PCNT0LOCKED */
AnnaBridge 170:e95d10626187 1726 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_MASK 0x4UL /**< Bit mask for EMU_PCNT0LOCKED */
AnnaBridge 170:e95d10626187 1727 #define _EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1728 #define EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT0LOCKED_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1729 #define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED (0x1UL << 3) /**< Indicates if PCNT1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1730 #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_SHIFT 3 /**< Shift value for EMU_PCNT1LOCKED */
AnnaBridge 170:e95d10626187 1731 #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_MASK 0x8UL /**< Bit mask for EMU_PCNT1LOCKED */
AnnaBridge 170:e95d10626187 1732 #define _EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1733 #define EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT1LOCKED_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1734 #define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED (0x1UL << 4) /**< Indicates if PCNT2 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1735 #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_SHIFT 4 /**< Shift value for EMU_PCNT2LOCKED */
AnnaBridge 170:e95d10626187 1736 #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_MASK 0x10UL /**< Bit mask for EMU_PCNT2LOCKED */
AnnaBridge 170:e95d10626187 1737 #define _EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1738 #define EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_PCNT2LOCKED_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1739 #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED (0x1UL << 5) /**< Indicates if I2C0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1740 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_SHIFT 5 /**< Shift value for EMU_I2C0LOCKED */
AnnaBridge 170:e95d10626187 1741 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_MASK 0x20UL /**< Bit mask for EMU_I2C0LOCKED */
AnnaBridge 170:e95d10626187 1742 #define _EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1743 #define EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C0LOCKED_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1744 #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED (0x1UL << 6) /**< Indicates if I2C1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1745 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_SHIFT 6 /**< Shift value for EMU_I2C1LOCKED */
AnnaBridge 170:e95d10626187 1746 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_MASK 0x40UL /**< Bit mask for EMU_I2C1LOCKED */
AnnaBridge 170:e95d10626187 1747 #define _EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1748 #define EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C1LOCKED_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1749 #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED (0x1UL << 7) /**< Indicates if DAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1750 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_SHIFT 7 /**< Shift value for EMU_DAC0LOCKED */
AnnaBridge 170:e95d10626187 1751 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_MASK 0x80UL /**< Bit mask for EMU_DAC0LOCKED */
AnnaBridge 170:e95d10626187 1752 #define _EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1753 #define EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_DAC0LOCKED_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1754 #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED (0x1UL << 8) /**< Indicates if IDAC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1755 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_SHIFT 8 /**< Shift value for EMU_IDAC0LOCKED */
AnnaBridge 170:e95d10626187 1756 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_MASK 0x100UL /**< Bit mask for EMU_IDAC0LOCKED */
AnnaBridge 170:e95d10626187 1757 #define _EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1758 #define EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_IDAC0LOCKED_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1759 #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED (0x1UL << 9) /**< Indicates if ADC0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1760 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_SHIFT 9 /**< Shift value for EMU_ADC0LOCKED */
AnnaBridge 170:e95d10626187 1761 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_MASK 0x200UL /**< Bit mask for EMU_ADC0LOCKED */
AnnaBridge 170:e95d10626187 1762 #define _EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1763 #define EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC0LOCKED_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1764 #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED (0x1UL << 10) /**< Indicates if LETIMER0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1765 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_SHIFT 10 /**< Shift value for EMU_LETIMER0LOCKED */
AnnaBridge 170:e95d10626187 1766 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_MASK 0x400UL /**< Bit mask for EMU_LETIMER0LOCKED */
AnnaBridge 170:e95d10626187 1767 #define _EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1768 #define EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER0LOCKED_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1769 #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED (0x1UL << 11) /**< Indicates if WDOG0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1770 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_SHIFT 11 /**< Shift value for EMU_WDOG0LOCKED */
AnnaBridge 170:e95d10626187 1771 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_MASK 0x800UL /**< Bit mask for EMU_WDOG0LOCKED */
AnnaBridge 170:e95d10626187 1772 #define _EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1773 #define EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG0LOCKED_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1774 #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED (0x1UL << 12) /**< Indicates if WDOG1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1775 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_SHIFT 12 /**< Shift value for EMU_WDOG1LOCKED */
AnnaBridge 170:e95d10626187 1776 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_MASK 0x1000UL /**< Bit mask for EMU_WDOG1LOCKED */
AnnaBridge 170:e95d10626187 1777 #define _EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1778 #define EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_WDOG1LOCKED_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1779 #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED (0x1UL << 13) /**< Indicates if LESENSE0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1780 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_SHIFT 13 /**< Shift value for EMU_LESENSE0LOCKED */
AnnaBridge 170:e95d10626187 1781 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0LOCKED */
AnnaBridge 170:e95d10626187 1782 #define _EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1783 #define EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LESENSE0LOCKED_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1784 #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED (0x1UL << 14) /**< Indicates if CSEN powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1785 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_SHIFT 14 /**< Shift value for EMU_CSENLOCKED */
AnnaBridge 170:e95d10626187 1786 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_MASK 0x4000UL /**< Bit mask for EMU_CSENLOCKED */
AnnaBridge 170:e95d10626187 1787 #define _EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1788 #define EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_CSENLOCKED_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1789 #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED (0x1UL << 15) /**< Indicates if LEUART0 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1790 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_SHIFT 15 /**< Shift value for EMU_LEUART0LOCKED */
AnnaBridge 170:e95d10626187 1791 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_MASK 0x8000UL /**< Bit mask for EMU_LEUART0LOCKED */
AnnaBridge 170:e95d10626187 1792 #define _EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1793 #define EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART0LOCKED_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1794 #define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED (0x1UL << 16) /**< Indicates if LEUART1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1795 #define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_SHIFT 16 /**< Shift value for EMU_LEUART1LOCKED */
AnnaBridge 170:e95d10626187 1796 #define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_MASK 0x10000UL /**< Bit mask for EMU_LEUART1LOCKED */
AnnaBridge 170:e95d10626187 1797 #define _EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1798 #define EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LEUART1LOCKED_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1799 #define EMU_EM23PERNORETAINSTATUS_LCDLOCKED (0x1UL << 17) /**< Indicates if LCD powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1800 #define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_SHIFT 17 /**< Shift value for EMU_LCDLOCKED */
AnnaBridge 170:e95d10626187 1801 #define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_MASK 0x20000UL /**< Bit mask for EMU_LCDLOCKED */
AnnaBridge 170:e95d10626187 1802 #define _EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1803 #define EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LCDLOCKED_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1804 #define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED (0x1UL << 18) /**< Indicates if LETIMER1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1805 #define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_SHIFT 18 /**< Shift value for EMU_LETIMER1LOCKED */
AnnaBridge 170:e95d10626187 1806 #define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1LOCKED */
AnnaBridge 170:e95d10626187 1807 #define _EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1808 #define EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_LETIMER1LOCKED_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1809 #define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED (0x1UL << 19) /**< Indicates if I2C2 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1810 #define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_SHIFT 19 /**< Shift value for EMU_I2C2LOCKED */
AnnaBridge 170:e95d10626187 1811 #define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_MASK 0x80000UL /**< Bit mask for EMU_I2C2LOCKED */
AnnaBridge 170:e95d10626187 1812 #define _EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1813 #define EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_I2C2LOCKED_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1814 #define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED (0x1UL << 20) /**< Indicates if ADC1 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1815 #define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_SHIFT 20 /**< Shift value for EMU_ADC1LOCKED */
AnnaBridge 170:e95d10626187 1816 #define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_MASK 0x100000UL /**< Bit mask for EMU_ADC1LOCKED */
AnnaBridge 170:e95d10626187 1817 #define _EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1818 #define EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ADC1LOCKED_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1819 #define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED (0x1UL << 21) /**< Indicates if ACMP2 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1820 #define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_SHIFT 21 /**< Shift value for EMU_ACMP2LOCKED */
AnnaBridge 170:e95d10626187 1821 #define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_MASK 0x200000UL /**< Bit mask for EMU_ACMP2LOCKED */
AnnaBridge 170:e95d10626187 1822 #define _EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1823 #define EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP2LOCKED_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1824 #define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED (0x1UL << 22) /**< Indicates if ACMP3 powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1825 #define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_SHIFT 22 /**< Shift value for EMU_ACMP3LOCKED */
AnnaBridge 170:e95d10626187 1826 #define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_MASK 0x400000UL /**< Bit mask for EMU_ACMP3LOCKED */
AnnaBridge 170:e95d10626187 1827 #define _EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1828 #define EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_ACMP3LOCKED_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1829 #define EMU_EM23PERNORETAINSTATUS_RTCLOCKED (0x1UL << 23) /**< Indicates if RTC powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1830 #define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_SHIFT 23 /**< Shift value for EMU_RTCLOCKED */
AnnaBridge 170:e95d10626187 1831 #define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_MASK 0x800000UL /**< Bit mask for EMU_RTCLOCKED */
AnnaBridge 170:e95d10626187 1832 #define _EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1833 #define EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_RTCLOCKED_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1834 #define EMU_EM23PERNORETAINSTATUS_USBLOCKED (0x1UL << 24) /**< Indicates if USB powered down during EM23. Access to this peripheral locked until this bit cleared using EM23PERNORETAINCMD */
AnnaBridge 170:e95d10626187 1835 #define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_SHIFT 24 /**< Shift value for EMU_USBLOCKED */
AnnaBridge 170:e95d10626187 1836 #define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_MASK 0x1000000UL /**< Bit mask for EMU_USBLOCKED */
AnnaBridge 170:e95d10626187 1837 #define _EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1838 #define EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT (_EMU_EM23PERNORETAINSTATUS_USBLOCKED_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINSTATUS */
AnnaBridge 170:e95d10626187 1839
AnnaBridge 170:e95d10626187 1840 /* Bit fields for EMU EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1841 #define _EMU_EM23PERNORETAINCTRL_RESETVALUE 0x00000000UL /**< Default value for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1842 #define _EMU_EM23PERNORETAINCTRL_MASK 0x01FFFFFFUL /**< Mask for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1843 #define EMU_EM23PERNORETAINCTRL_ACMP0DIS (0x1UL << 0) /**< Allow power down of ACMP0 during EM23 */
AnnaBridge 170:e95d10626187 1844 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_SHIFT 0 /**< Shift value for EMU_ACMP0DIS */
AnnaBridge 170:e95d10626187 1845 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK 0x1UL /**< Bit mask for EMU_ACMP0DIS */
AnnaBridge 170:e95d10626187 1846 #define _EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1847 #define EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP0DIS_DEFAULT << 0) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1848 #define EMU_EM23PERNORETAINCTRL_ACMP1DIS (0x1UL << 1) /**< Allow power down of ACMP1 during EM23 */
AnnaBridge 170:e95d10626187 1849 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_SHIFT 1 /**< Shift value for EMU_ACMP1DIS */
AnnaBridge 170:e95d10626187 1850 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK 0x2UL /**< Bit mask for EMU_ACMP1DIS */
AnnaBridge 170:e95d10626187 1851 #define _EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1852 #define EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP1DIS_DEFAULT << 1) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1853 #define EMU_EM23PERNORETAINCTRL_PCNT0DIS (0x1UL << 2) /**< Allow power down of PCNT0 during EM23 */
AnnaBridge 170:e95d10626187 1854 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_SHIFT 2 /**< Shift value for EMU_PCNT0DIS */
AnnaBridge 170:e95d10626187 1855 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK 0x4UL /**< Bit mask for EMU_PCNT0DIS */
AnnaBridge 170:e95d10626187 1856 #define _EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1857 #define EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT0DIS_DEFAULT << 2) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1858 #define EMU_EM23PERNORETAINCTRL_PCNT1DIS (0x1UL << 3) /**< Allow power down of PCNT1 during EM23 */
AnnaBridge 170:e95d10626187 1859 #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_SHIFT 3 /**< Shift value for EMU_PCNT1DIS */
AnnaBridge 170:e95d10626187 1860 #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK 0x8UL /**< Bit mask for EMU_PCNT1DIS */
AnnaBridge 170:e95d10626187 1861 #define _EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1862 #define EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT1DIS_DEFAULT << 3) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1863 #define EMU_EM23PERNORETAINCTRL_PCNT2DIS (0x1UL << 4) /**< Allow power down of PCNT2 during EM23 */
AnnaBridge 170:e95d10626187 1864 #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_SHIFT 4 /**< Shift value for EMU_PCNT2DIS */
AnnaBridge 170:e95d10626187 1865 #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK 0x10UL /**< Bit mask for EMU_PCNT2DIS */
AnnaBridge 170:e95d10626187 1866 #define _EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1867 #define EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_PCNT2DIS_DEFAULT << 4) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1868 #define EMU_EM23PERNORETAINCTRL_I2C0DIS (0x1UL << 5) /**< Allow power down of I2C0 during EM23 */
AnnaBridge 170:e95d10626187 1869 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_SHIFT 5 /**< Shift value for EMU_I2C0DIS */
AnnaBridge 170:e95d10626187 1870 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK 0x20UL /**< Bit mask for EMU_I2C0DIS */
AnnaBridge 170:e95d10626187 1871 #define _EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1872 #define EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C0DIS_DEFAULT << 5) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1873 #define EMU_EM23PERNORETAINCTRL_I2C1DIS (0x1UL << 6) /**< Allow power down of I2C1 during EM23 */
AnnaBridge 170:e95d10626187 1874 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_SHIFT 6 /**< Shift value for EMU_I2C1DIS */
AnnaBridge 170:e95d10626187 1875 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK 0x40UL /**< Bit mask for EMU_I2C1DIS */
AnnaBridge 170:e95d10626187 1876 #define _EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1877 #define EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C1DIS_DEFAULT << 6) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1878 #define EMU_EM23PERNORETAINCTRL_DAC0DIS (0x1UL << 7) /**< Allow power down of DAC0 during EM23 */
AnnaBridge 170:e95d10626187 1879 #define _EMU_EM23PERNORETAINCTRL_DAC0DIS_SHIFT 7 /**< Shift value for EMU_DAC0DIS */
AnnaBridge 170:e95d10626187 1880 #define _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK 0x80UL /**< Bit mask for EMU_DAC0DIS */
AnnaBridge 170:e95d10626187 1881 #define _EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1882 #define EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_DAC0DIS_DEFAULT << 7) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1883 #define EMU_EM23PERNORETAINCTRL_IDAC0DIS (0x1UL << 8) /**< Allow power down of IDAC0 during EM23 */
AnnaBridge 170:e95d10626187 1884 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_SHIFT 8 /**< Shift value for EMU_IDAC0DIS */
AnnaBridge 170:e95d10626187 1885 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK 0x100UL /**< Bit mask for EMU_IDAC0DIS */
AnnaBridge 170:e95d10626187 1886 #define _EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1887 #define EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_IDAC0DIS_DEFAULT << 8) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1888 #define EMU_EM23PERNORETAINCTRL_ADC0DIS (0x1UL << 9) /**< Allow power down of ADC0 during EM23 */
AnnaBridge 170:e95d10626187 1889 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_SHIFT 9 /**< Shift value for EMU_ADC0DIS */
AnnaBridge 170:e95d10626187 1890 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK 0x200UL /**< Bit mask for EMU_ADC0DIS */
AnnaBridge 170:e95d10626187 1891 #define _EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1892 #define EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC0DIS_DEFAULT << 9) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1893 #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS (0x1UL << 10) /**< Allow power down of LETIMER0 during EM23 */
AnnaBridge 170:e95d10626187 1894 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_SHIFT 10 /**< Shift value for EMU_LETIMER0DIS */
AnnaBridge 170:e95d10626187 1895 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK 0x400UL /**< Bit mask for EMU_LETIMER0DIS */
AnnaBridge 170:e95d10626187 1896 #define _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1897 #define EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER0DIS_DEFAULT << 10) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1898 #define EMU_EM23PERNORETAINCTRL_WDOG0DIS (0x1UL << 11) /**< Allow power down of WDOG0 during EM23 */
AnnaBridge 170:e95d10626187 1899 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_SHIFT 11 /**< Shift value for EMU_WDOG0DIS */
AnnaBridge 170:e95d10626187 1900 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_MASK 0x800UL /**< Bit mask for EMU_WDOG0DIS */
AnnaBridge 170:e95d10626187 1901 #define _EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1902 #define EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG0DIS_DEFAULT << 11) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1903 #define EMU_EM23PERNORETAINCTRL_WDOG1DIS (0x1UL << 12) /**< Allow power down of WDOG1 during EM23 */
AnnaBridge 170:e95d10626187 1904 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_SHIFT 12 /**< Shift value for EMU_WDOG1DIS */
AnnaBridge 170:e95d10626187 1905 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_MASK 0x1000UL /**< Bit mask for EMU_WDOG1DIS */
AnnaBridge 170:e95d10626187 1906 #define _EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1907 #define EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_WDOG1DIS_DEFAULT << 12) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1908 #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS (0x1UL << 13) /**< Allow power down of LESENSE0 during EM23 */
AnnaBridge 170:e95d10626187 1909 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_SHIFT 13 /**< Shift value for EMU_LESENSE0DIS */
AnnaBridge 170:e95d10626187 1910 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK 0x2000UL /**< Bit mask for EMU_LESENSE0DIS */
AnnaBridge 170:e95d10626187 1911 #define _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1912 #define EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LESENSE0DIS_DEFAULT << 13) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1913 #define EMU_EM23PERNORETAINCTRL_CSENDIS (0x1UL << 14) /**< Allow power down of CSEN during EM23 */
AnnaBridge 170:e95d10626187 1914 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_SHIFT 14 /**< Shift value for EMU_CSENDIS */
AnnaBridge 170:e95d10626187 1915 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK 0x4000UL /**< Bit mask for EMU_CSENDIS */
AnnaBridge 170:e95d10626187 1916 #define _EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1917 #define EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_CSENDIS_DEFAULT << 14) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1918 #define EMU_EM23PERNORETAINCTRL_LEUART0DIS (0x1UL << 15) /**< Allow power down of LEUART0 during EM23 */
AnnaBridge 170:e95d10626187 1919 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_SHIFT 15 /**< Shift value for EMU_LEUART0DIS */
AnnaBridge 170:e95d10626187 1920 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK 0x8000UL /**< Bit mask for EMU_LEUART0DIS */
AnnaBridge 170:e95d10626187 1921 #define _EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1922 #define EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART0DIS_DEFAULT << 15) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1923 #define EMU_EM23PERNORETAINCTRL_LEUART1DIS (0x1UL << 16) /**< Allow power down of LEUART1 during EM23 */
AnnaBridge 170:e95d10626187 1924 #define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_SHIFT 16 /**< Shift value for EMU_LEUART1DIS */
AnnaBridge 170:e95d10626187 1925 #define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_MASK 0x10000UL /**< Bit mask for EMU_LEUART1DIS */
AnnaBridge 170:e95d10626187 1926 #define _EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1927 #define EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LEUART1DIS_DEFAULT << 16) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1928 #define EMU_EM23PERNORETAINCTRL_LCDDIS (0x1UL << 17) /**< Allow power down of LCD during EM23 */
AnnaBridge 170:e95d10626187 1929 #define _EMU_EM23PERNORETAINCTRL_LCDDIS_SHIFT 17 /**< Shift value for EMU_LCDDIS */
AnnaBridge 170:e95d10626187 1930 #define _EMU_EM23PERNORETAINCTRL_LCDDIS_MASK 0x20000UL /**< Bit mask for EMU_LCDDIS */
AnnaBridge 170:e95d10626187 1931 #define _EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1932 #define EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LCDDIS_DEFAULT << 17) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1933 #define EMU_EM23PERNORETAINCTRL_LETIMER1DIS (0x1UL << 18) /**< Allow power down of LETIMER1 during EM23 */
AnnaBridge 170:e95d10626187 1934 #define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_SHIFT 18 /**< Shift value for EMU_LETIMER1DIS */
AnnaBridge 170:e95d10626187 1935 #define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_MASK 0x40000UL /**< Bit mask for EMU_LETIMER1DIS */
AnnaBridge 170:e95d10626187 1936 #define _EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1937 #define EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_LETIMER1DIS_DEFAULT << 18) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1938 #define EMU_EM23PERNORETAINCTRL_I2C2DIS (0x1UL << 19) /**< Allow power down of I2C2 during EM23 */
AnnaBridge 170:e95d10626187 1939 #define _EMU_EM23PERNORETAINCTRL_I2C2DIS_SHIFT 19 /**< Shift value for EMU_I2C2DIS */
AnnaBridge 170:e95d10626187 1940 #define _EMU_EM23PERNORETAINCTRL_I2C2DIS_MASK 0x80000UL /**< Bit mask for EMU_I2C2DIS */
AnnaBridge 170:e95d10626187 1941 #define _EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1942 #define EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_I2C2DIS_DEFAULT << 19) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1943 #define EMU_EM23PERNORETAINCTRL_ADC1DIS (0x1UL << 20) /**< Allow power down of ADC1 during EM23 */
AnnaBridge 170:e95d10626187 1944 #define _EMU_EM23PERNORETAINCTRL_ADC1DIS_SHIFT 20 /**< Shift value for EMU_ADC1DIS */
AnnaBridge 170:e95d10626187 1945 #define _EMU_EM23PERNORETAINCTRL_ADC1DIS_MASK 0x100000UL /**< Bit mask for EMU_ADC1DIS */
AnnaBridge 170:e95d10626187 1946 #define _EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1947 #define EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ADC1DIS_DEFAULT << 20) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1948 #define EMU_EM23PERNORETAINCTRL_ACMP2DIS (0x1UL << 21) /**< Allow power down of ACMP2 during EM23 */
AnnaBridge 170:e95d10626187 1949 #define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_SHIFT 21 /**< Shift value for EMU_ACMP2DIS */
AnnaBridge 170:e95d10626187 1950 #define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_MASK 0x200000UL /**< Bit mask for EMU_ACMP2DIS */
AnnaBridge 170:e95d10626187 1951 #define _EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1952 #define EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP2DIS_DEFAULT << 21) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1953 #define EMU_EM23PERNORETAINCTRL_ACMP3DIS (0x1UL << 22) /**< Allow power down of ACMP3 during EM23 */
AnnaBridge 170:e95d10626187 1954 #define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_SHIFT 22 /**< Shift value for EMU_ACMP3DIS */
AnnaBridge 170:e95d10626187 1955 #define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_MASK 0x400000UL /**< Bit mask for EMU_ACMP3DIS */
AnnaBridge 170:e95d10626187 1956 #define _EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1957 #define EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_ACMP3DIS_DEFAULT << 22) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1958 #define EMU_EM23PERNORETAINCTRL_RTCDIS (0x1UL << 23) /**< Allow power down of RTC during EM23 */
AnnaBridge 170:e95d10626187 1959 #define _EMU_EM23PERNORETAINCTRL_RTCDIS_SHIFT 23 /**< Shift value for EMU_RTCDIS */
AnnaBridge 170:e95d10626187 1960 #define _EMU_EM23PERNORETAINCTRL_RTCDIS_MASK 0x800000UL /**< Bit mask for EMU_RTCDIS */
AnnaBridge 170:e95d10626187 1961 #define _EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1962 #define EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_RTCDIS_DEFAULT << 23) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1963 #define EMU_EM23PERNORETAINCTRL_USBDIS (0x1UL << 24) /**< Allow power down of USB during EM23 */
AnnaBridge 170:e95d10626187 1964 #define _EMU_EM23PERNORETAINCTRL_USBDIS_SHIFT 24 /**< Shift value for EMU_USBDIS */
AnnaBridge 170:e95d10626187 1965 #define _EMU_EM23PERNORETAINCTRL_USBDIS_MASK 0x1000000UL /**< Bit mask for EMU_USBDIS */
AnnaBridge 170:e95d10626187 1966 #define _EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1967 #define EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT (_EMU_EM23PERNORETAINCTRL_USBDIS_DEFAULT << 24) /**< Shifted mode DEFAULT for EMU_EM23PERNORETAINCTRL */
AnnaBridge 170:e95d10626187 1968
AnnaBridge 170:e95d10626187 1969 /** @} */
AnnaBridge 170:e95d10626187 1970 /** @} End of group EFM32GG11B_EMU */
AnnaBridge 170:e95d10626187 1971 /** @} End of group Parts */