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TARGET_EFM32GG11_STK3701/TOOLCHAIN_ARM_MICRO/efm32gg11b_dmareq.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 170:e95d10626187 1 /**************************************************************************//**
AnnaBridge 170:e95d10626187 2 * @file efm32gg11b_dmareq.h
AnnaBridge 170:e95d10626187 3 * @brief EFM32GG11B_DMAREQ register and bit field definitions
AnnaBridge 170:e95d10626187 4 * @version 5.3.2
AnnaBridge 170:e95d10626187 5 ******************************************************************************
AnnaBridge 170:e95d10626187 6 * # License
AnnaBridge 170:e95d10626187 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 170:e95d10626187 8 ******************************************************************************
AnnaBridge 170:e95d10626187 9 *
AnnaBridge 170:e95d10626187 10 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 170:e95d10626187 11 * including commercial applications, and to alter it and redistribute it
AnnaBridge 170:e95d10626187 12 * freely, subject to the following restrictions:
AnnaBridge 170:e95d10626187 13 *
AnnaBridge 170:e95d10626187 14 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 170:e95d10626187 15 * claim that you wrote the original software.@n
AnnaBridge 170:e95d10626187 16 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 170:e95d10626187 17 * misrepresented as being the original software.@n
AnnaBridge 170:e95d10626187 18 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 170:e95d10626187 19 *
AnnaBridge 170:e95d10626187 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 170:e95d10626187 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 170:e95d10626187 22 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 170:e95d10626187 23 * kind, including, but not limited to, any implied warranties of
AnnaBridge 170:e95d10626187 24 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 170:e95d10626187 25 * infringement of any proprietary rights of a third party.
AnnaBridge 170:e95d10626187 26 *
AnnaBridge 170:e95d10626187 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 170:e95d10626187 28 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 170:e95d10626187 29 * any third party, arising from your use of this Software.
AnnaBridge 170:e95d10626187 30 *
AnnaBridge 170:e95d10626187 31 *****************************************************************************/
AnnaBridge 170:e95d10626187 32
AnnaBridge 170:e95d10626187 33 #if defined(__ICCARM__)
AnnaBridge 170:e95d10626187 34 #pragma system_include /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 35 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 170:e95d10626187 36 #pragma clang system_header /* Treat file as system include file. */
AnnaBridge 170:e95d10626187 37 #endif
AnnaBridge 170:e95d10626187 38
AnnaBridge 170:e95d10626187 39 /**************************************************************************//**
AnnaBridge 170:e95d10626187 40 * @addtogroup Parts
AnnaBridge 170:e95d10626187 41 * @{
AnnaBridge 170:e95d10626187 42 ******************************************************************************/
AnnaBridge 170:e95d10626187 43
AnnaBridge 170:e95d10626187 44 /**************************************************************************//**
AnnaBridge 170:e95d10626187 45 * @addtogroup EFM32GG11B_DMAREQ DMAREQ
AnnaBridge 170:e95d10626187 46 * @{
AnnaBridge 170:e95d10626187 47 * @defgroup EFM32GG11B_DMAREQ_BitFields DMAREQ Bit Fields
AnnaBridge 170:e95d10626187 48 * @{
AnnaBridge 170:e95d10626187 49 *****************************************************************************/
AnnaBridge 170:e95d10626187 50 #define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */
AnnaBridge 170:e95d10626187 51 #define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */
AnnaBridge 170:e95d10626187 52 #define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
AnnaBridge 170:e95d10626187 53 #define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
AnnaBridge 170:e95d10626187 54 #define DMAREQ_ADC1_SINGLE ((9 << 16) + 0) /**< DMA channel select for ADC1_SINGLE */
AnnaBridge 170:e95d10626187 55 #define DMAREQ_ADC1_SCAN ((9 << 16) + 1) /**< DMA channel select for ADC1_SCAN */
AnnaBridge 170:e95d10626187 56 #define DMAREQ_VDAC0_CH0 ((10 << 16) + 0) /**< DMA channel select for VDAC0_CH0 */
AnnaBridge 170:e95d10626187 57 #define DMAREQ_VDAC0_CH1 ((10 << 16) + 1) /**< DMA channel select for VDAC0_CH1 */
AnnaBridge 170:e95d10626187 58 #define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
AnnaBridge 170:e95d10626187 59 #define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
AnnaBridge 170:e95d10626187 60 #define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
AnnaBridge 170:e95d10626187 61 #define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
AnnaBridge 170:e95d10626187 62 #define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
AnnaBridge 170:e95d10626187 63 #define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
AnnaBridge 170:e95d10626187 64 #define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
AnnaBridge 170:e95d10626187 65 #define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
AnnaBridge 170:e95d10626187 66 #define DMAREQ_USART2_RXDATAV ((14 << 16) + 0) /**< DMA channel select for USART2_RXDATAV */
AnnaBridge 170:e95d10626187 67 #define DMAREQ_USART2_TXBL ((14 << 16) + 1) /**< DMA channel select for USART2_TXBL */
AnnaBridge 170:e95d10626187 68 #define DMAREQ_USART2_TXEMPTY ((14 << 16) + 2) /**< DMA channel select for USART2_TXEMPTY */
AnnaBridge 170:e95d10626187 69 #define DMAREQ_USART3_RXDATAV ((15 << 16) + 0) /**< DMA channel select for USART3_RXDATAV */
AnnaBridge 170:e95d10626187 70 #define DMAREQ_USART3_TXBL ((15 << 16) + 1) /**< DMA channel select for USART3_TXBL */
AnnaBridge 170:e95d10626187 71 #define DMAREQ_USART3_TXEMPTY ((15 << 16) + 2) /**< DMA channel select for USART3_TXEMPTY */
AnnaBridge 170:e95d10626187 72 #define DMAREQ_USART3_RXDATAVRIGHT ((15 << 16) + 3) /**< DMA channel select for USART3_RXDATAVRIGHT */
AnnaBridge 170:e95d10626187 73 #define DMAREQ_USART3_TXBLRIGHT ((15 << 16) + 4) /**< DMA channel select for USART3_TXBLRIGHT */
AnnaBridge 170:e95d10626187 74 #define DMAREQ_USART4_RXDATAV ((16 << 16) + 0) /**< DMA channel select for USART4_RXDATAV */
AnnaBridge 170:e95d10626187 75 #define DMAREQ_USART4_TXBL ((16 << 16) + 1) /**< DMA channel select for USART4_TXBL */
AnnaBridge 170:e95d10626187 76 #define DMAREQ_USART4_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for USART4_TXEMPTY */
AnnaBridge 170:e95d10626187 77 #define DMAREQ_USART4_RXDATAVRIGHT ((16 << 16) + 3) /**< DMA channel select for USART4_RXDATAVRIGHT */
AnnaBridge 170:e95d10626187 78 #define DMAREQ_USART4_TXBLRIGHT ((16 << 16) + 4) /**< DMA channel select for USART4_TXBLRIGHT */
AnnaBridge 170:e95d10626187 79 #define DMAREQ_USART5_RXDATAV ((17 << 16) + 0) /**< DMA channel select for USART5_RXDATAV */
AnnaBridge 170:e95d10626187 80 #define DMAREQ_USART5_TXBL ((17 << 16) + 1) /**< DMA channel select for USART5_TXBL */
AnnaBridge 170:e95d10626187 81 #define DMAREQ_USART5_TXEMPTY ((17 << 16) + 2) /**< DMA channel select for USART5_TXEMPTY */
AnnaBridge 170:e95d10626187 82 #define DMAREQ_UART0_RXDATAV ((18 << 16) + 0) /**< DMA channel select for UART0_RXDATAV */
AnnaBridge 170:e95d10626187 83 #define DMAREQ_UART0_TXBL ((18 << 16) + 1) /**< DMA channel select for UART0_TXBL */
AnnaBridge 170:e95d10626187 84 #define DMAREQ_UART0_TXEMPTY ((18 << 16) + 2) /**< DMA channel select for UART0_TXEMPTY */
AnnaBridge 170:e95d10626187 85 #define DMAREQ_UART1_RXDATAV ((19 << 16) + 0) /**< DMA channel select for UART1_RXDATAV */
AnnaBridge 170:e95d10626187 86 #define DMAREQ_UART1_TXBL ((19 << 16) + 1) /**< DMA channel select for UART1_TXBL */
AnnaBridge 170:e95d10626187 87 #define DMAREQ_UART1_TXEMPTY ((19 << 16) + 2) /**< DMA channel select for UART1_TXEMPTY */
AnnaBridge 170:e95d10626187 88 #define DMAREQ_LEUART0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
AnnaBridge 170:e95d10626187 89 #define DMAREQ_LEUART0_TXBL ((20 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
AnnaBridge 170:e95d10626187 90 #define DMAREQ_LEUART0_TXEMPTY ((20 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
AnnaBridge 170:e95d10626187 91 #define DMAREQ_LEUART1_RXDATAV ((21 << 16) + 0) /**< DMA channel select for LEUART1_RXDATAV */
AnnaBridge 170:e95d10626187 92 #define DMAREQ_LEUART1_TXBL ((21 << 16) + 1) /**< DMA channel select for LEUART1_TXBL */
AnnaBridge 170:e95d10626187 93 #define DMAREQ_LEUART1_TXEMPTY ((21 << 16) + 2) /**< DMA channel select for LEUART1_TXEMPTY */
AnnaBridge 170:e95d10626187 94 #define DMAREQ_I2C0_RXDATAV ((22 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
AnnaBridge 170:e95d10626187 95 #define DMAREQ_I2C0_TXBL ((22 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
AnnaBridge 170:e95d10626187 96 #define DMAREQ_I2C1_RXDATAV ((23 << 16) + 0) /**< DMA channel select for I2C1_RXDATAV */
AnnaBridge 170:e95d10626187 97 #define DMAREQ_I2C1_TXBL ((23 << 16) + 1) /**< DMA channel select for I2C1_TXBL */
AnnaBridge 170:e95d10626187 98 #define DMAREQ_I2C2_RXDATAV ((24 << 16) + 0) /**< DMA channel select for I2C2_RXDATAV */
AnnaBridge 170:e95d10626187 99 #define DMAREQ_I2C2_TXBL ((24 << 16) + 1) /**< DMA channel select for I2C2_TXBL */
AnnaBridge 170:e95d10626187 100 #define DMAREQ_TIMER0_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
AnnaBridge 170:e95d10626187 101 #define DMAREQ_TIMER0_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
AnnaBridge 170:e95d10626187 102 #define DMAREQ_TIMER0_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
AnnaBridge 170:e95d10626187 103 #define DMAREQ_TIMER0_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
AnnaBridge 170:e95d10626187 104 #define DMAREQ_TIMER1_UFOF ((26 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
AnnaBridge 170:e95d10626187 105 #define DMAREQ_TIMER1_CC0 ((26 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
AnnaBridge 170:e95d10626187 106 #define DMAREQ_TIMER1_CC1 ((26 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
AnnaBridge 170:e95d10626187 107 #define DMAREQ_TIMER1_CC2 ((26 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
AnnaBridge 170:e95d10626187 108 #define DMAREQ_TIMER1_CC3 ((26 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */
AnnaBridge 170:e95d10626187 109 #define DMAREQ_TIMER2_UFOF ((27 << 16) + 0) /**< DMA channel select for TIMER2_UFOF */
AnnaBridge 170:e95d10626187 110 #define DMAREQ_TIMER2_CC0 ((27 << 16) + 1) /**< DMA channel select for TIMER2_CC0 */
AnnaBridge 170:e95d10626187 111 #define DMAREQ_TIMER2_CC1 ((27 << 16) + 2) /**< DMA channel select for TIMER2_CC1 */
AnnaBridge 170:e95d10626187 112 #define DMAREQ_TIMER2_CC2 ((27 << 16) + 3) /**< DMA channel select for TIMER2_CC2 */
AnnaBridge 170:e95d10626187 113 #define DMAREQ_TIMER3_UFOF ((28 << 16) + 0) /**< DMA channel select for TIMER3_UFOF */
AnnaBridge 170:e95d10626187 114 #define DMAREQ_TIMER3_CC0 ((28 << 16) + 1) /**< DMA channel select for TIMER3_CC0 */
AnnaBridge 170:e95d10626187 115 #define DMAREQ_TIMER3_CC1 ((28 << 16) + 2) /**< DMA channel select for TIMER3_CC1 */
AnnaBridge 170:e95d10626187 116 #define DMAREQ_TIMER3_CC2 ((28 << 16) + 3) /**< DMA channel select for TIMER3_CC2 */
AnnaBridge 170:e95d10626187 117 #define DMAREQ_TIMER4_UFOF ((29 << 16) + 0) /**< DMA channel select for TIMER4_UFOF */
AnnaBridge 170:e95d10626187 118 #define DMAREQ_TIMER4_CC0 ((29 << 16) + 1) /**< DMA channel select for TIMER4_CC0 */
AnnaBridge 170:e95d10626187 119 #define DMAREQ_TIMER4_CC1 ((29 << 16) + 2) /**< DMA channel select for TIMER4_CC1 */
AnnaBridge 170:e95d10626187 120 #define DMAREQ_TIMER4_CC2 ((29 << 16) + 3) /**< DMA channel select for TIMER4_CC2 */
AnnaBridge 170:e95d10626187 121 #define DMAREQ_TIMER5_UFOF ((30 << 16) + 0) /**< DMA channel select for TIMER5_UFOF */
AnnaBridge 170:e95d10626187 122 #define DMAREQ_TIMER5_CC0 ((30 << 16) + 1) /**< DMA channel select for TIMER5_CC0 */
AnnaBridge 170:e95d10626187 123 #define DMAREQ_TIMER5_CC1 ((30 << 16) + 2) /**< DMA channel select for TIMER5_CC1 */
AnnaBridge 170:e95d10626187 124 #define DMAREQ_TIMER5_CC2 ((30 << 16) + 3) /**< DMA channel select for TIMER5_CC2 */
AnnaBridge 170:e95d10626187 125 #define DMAREQ_TIMER6_UFOF ((31 << 16) + 0) /**< DMA channel select for TIMER6_UFOF */
AnnaBridge 170:e95d10626187 126 #define DMAREQ_TIMER6_CC0 ((31 << 16) + 1) /**< DMA channel select for TIMER6_CC0 */
AnnaBridge 170:e95d10626187 127 #define DMAREQ_TIMER6_CC1 ((31 << 16) + 2) /**< DMA channel select for TIMER6_CC1 */
AnnaBridge 170:e95d10626187 128 #define DMAREQ_TIMER6_CC2 ((31 << 16) + 3) /**< DMA channel select for TIMER6_CC2 */
AnnaBridge 170:e95d10626187 129 #define DMAREQ_WTIMER0_UFOF ((32 << 16) + 0) /**< DMA channel select for WTIMER0_UFOF */
AnnaBridge 170:e95d10626187 130 #define DMAREQ_WTIMER0_CC0 ((32 << 16) + 1) /**< DMA channel select for WTIMER0_CC0 */
AnnaBridge 170:e95d10626187 131 #define DMAREQ_WTIMER0_CC1 ((32 << 16) + 2) /**< DMA channel select for WTIMER0_CC1 */
AnnaBridge 170:e95d10626187 132 #define DMAREQ_WTIMER0_CC2 ((32 << 16) + 3) /**< DMA channel select for WTIMER0_CC2 */
AnnaBridge 170:e95d10626187 133 #define DMAREQ_WTIMER1_UFOF ((33 << 16) + 0) /**< DMA channel select for WTIMER1_UFOF */
AnnaBridge 170:e95d10626187 134 #define DMAREQ_WTIMER1_CC0 ((33 << 16) + 1) /**< DMA channel select for WTIMER1_CC0 */
AnnaBridge 170:e95d10626187 135 #define DMAREQ_WTIMER1_CC1 ((33 << 16) + 2) /**< DMA channel select for WTIMER1_CC1 */
AnnaBridge 170:e95d10626187 136 #define DMAREQ_WTIMER1_CC2 ((33 << 16) + 3) /**< DMA channel select for WTIMER1_CC2 */
AnnaBridge 170:e95d10626187 137 #define DMAREQ_WTIMER1_CC3 ((33 << 16) + 4) /**< DMA channel select for WTIMER1_CC3 */
AnnaBridge 170:e95d10626187 138 #define DMAREQ_WTIMER2_UFOF ((34 << 16) + 0) /**< DMA channel select for WTIMER2_UFOF */
AnnaBridge 170:e95d10626187 139 #define DMAREQ_WTIMER2_CC0 ((34 << 16) + 1) /**< DMA channel select for WTIMER2_CC0 */
AnnaBridge 170:e95d10626187 140 #define DMAREQ_WTIMER2_CC1 ((34 << 16) + 2) /**< DMA channel select for WTIMER2_CC1 */
AnnaBridge 170:e95d10626187 141 #define DMAREQ_WTIMER2_CC2 ((34 << 16) + 3) /**< DMA channel select for WTIMER2_CC2 */
AnnaBridge 170:e95d10626187 142 #define DMAREQ_WTIMER3_UFOF ((35 << 16) + 0) /**< DMA channel select for WTIMER3_UFOF */
AnnaBridge 170:e95d10626187 143 #define DMAREQ_WTIMER3_CC0 ((35 << 16) + 1) /**< DMA channel select for WTIMER3_CC0 */
AnnaBridge 170:e95d10626187 144 #define DMAREQ_WTIMER3_CC1 ((35 << 16) + 2) /**< DMA channel select for WTIMER3_CC1 */
AnnaBridge 170:e95d10626187 145 #define DMAREQ_WTIMER3_CC2 ((35 << 16) + 3) /**< DMA channel select for WTIMER3_CC2 */
AnnaBridge 170:e95d10626187 146 #define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
AnnaBridge 170:e95d10626187 147 #define DMAREQ_CRYPTO0_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO0_DATA0WR */
AnnaBridge 170:e95d10626187 148 #define DMAREQ_CRYPTO0_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO0_DATA0XWR */
AnnaBridge 170:e95d10626187 149 #define DMAREQ_CRYPTO0_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO0_DATA0RD */
AnnaBridge 170:e95d10626187 150 #define DMAREQ_CRYPTO0_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO0_DATA1WR */
AnnaBridge 170:e95d10626187 151 #define DMAREQ_CRYPTO0_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO0_DATA1RD */
AnnaBridge 170:e95d10626187 152 #define DMAREQ_EBI_PXL0EMPTY ((50 << 16) + 0) /**< DMA channel select for EBI_PXL0EMPTY */
AnnaBridge 170:e95d10626187 153 #define DMAREQ_EBI_PXL1EMPTY ((50 << 16) + 1) /**< DMA channel select for EBI_PXL1EMPTY */
AnnaBridge 170:e95d10626187 154 #define DMAREQ_EBI_PXLFULL ((50 << 16) + 2) /**< DMA channel select for EBI_PXLFULL */
AnnaBridge 170:e95d10626187 155 #define DMAREQ_EBI_DDEMPTY ((50 << 16) + 3) /**< DMA channel select for EBI_DDEMPTY */
AnnaBridge 170:e95d10626187 156 #define DMAREQ_EBI_VSYNC ((50 << 16) + 4) /**< DMA channel select for EBI_VSYNC */
AnnaBridge 170:e95d10626187 157 #define DMAREQ_EBI_HSYNC ((50 << 16) + 5) /**< DMA channel select for EBI_HSYNC */
AnnaBridge 170:e95d10626187 158 #define DMAREQ_CSEN_DATA ((61 << 16) + 0) /**< DMA channel select for CSEN_DATA */
AnnaBridge 170:e95d10626187 159 #define DMAREQ_CSEN_BSLN ((61 << 16) + 1) /**< DMA channel select for CSEN_BSLN */
AnnaBridge 170:e95d10626187 160 #define DMAREQ_LESENSE_BUFDATAV ((62 << 16) + 0) /**< DMA channel select for LESENSE_BUFDATAV */
AnnaBridge 170:e95d10626187 161
AnnaBridge 170:e95d10626187 162 /** @} */
AnnaBridge 170:e95d10626187 163 /** @} End of group EFM32GG11B_DMAREQ */
AnnaBridge 170:e95d10626187 164 /** @} End of group Parts */