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TARGET_DISCO_F769NI/TOOLCHAIN_IAR/stm32f7xx_hal_tim_ex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_hal_tim_ex.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of TIM HAL Extension module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F7xx_HAL_TIM_EX_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F7xx_HAL_TIM_EX_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f7xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F7xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 49 | */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | |
| AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup TIMEx |
| AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 53 | */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | |
| AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 56 | /** @defgroup TIMEx_Exported_Types TIM Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 57 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 58 | */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | |
| AnnaBridge | 171:3a7713b1edbc | 60 | /** |
| AnnaBridge | 171:3a7713b1edbc | 61 | * @brief TIM Hall sensor Configuration Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 62 | */ |
| AnnaBridge | 171:3a7713b1edbc | 63 | |
| AnnaBridge | 171:3a7713b1edbc | 64 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 65 | { |
| AnnaBridge | 171:3a7713b1edbc | 66 | |
| AnnaBridge | 171:3a7713b1edbc | 67 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
| AnnaBridge | 171:3a7713b1edbc | 68 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | |
| AnnaBridge | 171:3a7713b1edbc | 70 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
| AnnaBridge | 171:3a7713b1edbc | 71 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | |
| AnnaBridge | 171:3a7713b1edbc | 73 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
| AnnaBridge | 171:3a7713b1edbc | 74 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
| AnnaBridge | 171:3a7713b1edbc | 76 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | } TIM_HallSensor_InitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 78 | |
| AnnaBridge | 171:3a7713b1edbc | 79 | /** |
| AnnaBridge | 171:3a7713b1edbc | 80 | * @brief TIM Master configuration Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 81 | */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 83 | uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection. |
| AnnaBridge | 171:3a7713b1edbc | 84 | This parameter can be a value of @ref TIM_Master_Mode_Selection */ |
| AnnaBridge | 171:3a7713b1edbc | 85 | uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection |
| AnnaBridge | 171:3a7713b1edbc | 86 | This parameter can be a value of @ref TIMEx_Master_Mode_Selection_2 */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | uint32_t MasterSlaveMode; /*!< Master/slave mode selection. |
| AnnaBridge | 171:3a7713b1edbc | 88 | This parameter can be a value of @ref TIM_Master_Slave_Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | }TIM_MasterConfigTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 90 | |
| AnnaBridge | 171:3a7713b1edbc | 91 | /** |
| AnnaBridge | 171:3a7713b1edbc | 92 | * @brief TIM Break input(s) and Dead time configuration Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 93 | * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable |
| AnnaBridge | 171:3a7713b1edbc | 94 | * filter and polarity. |
| AnnaBridge | 171:3a7713b1edbc | 95 | */ |
| AnnaBridge | 171:3a7713b1edbc | 96 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 97 | { |
| AnnaBridge | 171:3a7713b1edbc | 98 | uint32_t OffStateRunMode; /*!< TIM off state in run mode. |
| AnnaBridge | 171:3a7713b1edbc | 99 | This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode. |
| AnnaBridge | 171:3a7713b1edbc | 101 | This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | uint32_t LockLevel; /*!< TIM Lock level. |
| AnnaBridge | 171:3a7713b1edbc | 103 | This parameter can be a value of @ref TIM_Lock_level */ |
| AnnaBridge | 171:3a7713b1edbc | 104 | uint32_t DeadTime; /*!< TIM dead Time. |
| AnnaBridge | 171:3a7713b1edbc | 105 | This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | uint32_t BreakState; /*!< TIM Break State. |
| AnnaBridge | 171:3a7713b1edbc | 107 | This parameter can be a value of @ref TIM_Break_Input_enable_disable */ |
| AnnaBridge | 171:3a7713b1edbc | 108 | uint32_t BreakPolarity; /*!< TIM Break input polarity. |
| AnnaBridge | 171:3a7713b1edbc | 109 | This parameter can be a value of @ref TIM_Break_Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | uint32_t BreakFilter; /*!< Specifies the break input filter. |
| AnnaBridge | 171:3a7713b1edbc | 111 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| AnnaBridge | 171:3a7713b1edbc | 112 | uint32_t Break2State; /*!< TIM Break2 State |
| AnnaBridge | 171:3a7713b1edbc | 113 | This parameter can be a value of @ref TIMEx_Break2_Input_enable_disable */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | uint32_t Break2Polarity; /*!< TIM Break2 input polarity |
| AnnaBridge | 171:3a7713b1edbc | 115 | This parameter can be a value of @ref TIMEx_Break2_Polarity */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | uint32_t Break2Filter; /*!< TIM break2 input filter. |
| AnnaBridge | 171:3a7713b1edbc | 117 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state |
| AnnaBridge | 171:3a7713b1edbc | 119 | This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | } TIM_BreakDeadTimeConfigTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 121 | |
| AnnaBridge | 171:3a7713b1edbc | 122 | #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) |
| AnnaBridge | 171:3a7713b1edbc | 123 | /** |
| AnnaBridge | 171:3a7713b1edbc | 124 | * @brief TIM Break/Break2 input configuration |
| AnnaBridge | 171:3a7713b1edbc | 125 | */ |
| AnnaBridge | 171:3a7713b1edbc | 126 | typedef struct { |
| AnnaBridge | 171:3a7713b1edbc | 127 | uint32_t Source; /*!< Specifies the source of the timer break input. |
| AnnaBridge | 171:3a7713b1edbc | 128 | This parameter can be a value of @ref TIMEx_Break_Input_Source */ |
| AnnaBridge | 171:3a7713b1edbc | 129 | uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. |
| AnnaBridge | 171:3a7713b1edbc | 130 | This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | uint32_t Polarity; /*!< Specifies the break input source polarity. |
| AnnaBridge | 171:3a7713b1edbc | 132 | This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity |
| AnnaBridge | 171:3a7713b1edbc | 133 | Not relevant when analog watchdog output of the DFSDM1 used as break input source */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | } TIMEx_BreakInputConfigTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 135 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | /** |
| AnnaBridge | 171:3a7713b1edbc | 137 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 138 | */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 140 | /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 141 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 142 | */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | |
| AnnaBridge | 171:3a7713b1edbc | 144 | /** @defgroup TIMEx_Channel TIMEx Channel |
| AnnaBridge | 171:3a7713b1edbc | 145 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 146 | */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define TIM_CHANNEL_1 ((uint32_t)0x0000U) |
| AnnaBridge | 171:3a7713b1edbc | 149 | #define TIM_CHANNEL_2 ((uint32_t)0x0004U) |
| AnnaBridge | 171:3a7713b1edbc | 150 | #define TIM_CHANNEL_3 ((uint32_t)0x0008U) |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define TIM_CHANNEL_4 ((uint32_t)0x000CU) |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define TIM_CHANNEL_5 ((uint32_t)0x0010U) |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define TIM_CHANNEL_6 ((uint32_t)0x0014U) |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define TIM_CHANNEL_ALL ((uint32_t)0x003CU) |
| AnnaBridge | 171:3a7713b1edbc | 155 | |
| AnnaBridge | 171:3a7713b1edbc | 156 | /** |
| AnnaBridge | 171:3a7713b1edbc | 157 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 158 | */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | |
| AnnaBridge | 171:3a7713b1edbc | 160 | /** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes |
| AnnaBridge | 171:3a7713b1edbc | 161 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 162 | */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define TIM_OCMODE_TIMING ((uint32_t)0x0000U) |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) |
| AnnaBridge | 171:3a7713b1edbc | 171 | |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3) |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) |
| AnnaBridge | 171:3a7713b1edbc | 178 | /** |
| AnnaBridge | 171:3a7713b1edbc | 179 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 180 | */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | |
| AnnaBridge | 171:3a7713b1edbc | 182 | /** @defgroup TIMEx_Remap TIMEx Remap |
| AnnaBridge | 171:3a7713b1edbc | 183 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 184 | */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define TIM_TIM2_TIM8_TRGO (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define TIM_TIM2_ETH_PTP (0x00000400U) |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define TIM_TIM2_USBFS_SOF (0x00000800U) |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define TIM_TIM2_USBHS_SOF (0x00000C00U) |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define TIM_TIM5_GPIO (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define TIM_TIM5_LSI (0x00000040U) |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define TIM_TIM5_LSE (0x00000080U) |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define TIM_TIM5_RTC (0x000000C0U) |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define TIM_TIM11_GPIO (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define TIM_TIM11_SPDIFRX (0x00000001U) |
| AnnaBridge | 171:3a7713b1edbc | 195 | #define TIM_TIM11_HSE (0x00000002U) |
| AnnaBridge | 171:3a7713b1edbc | 196 | #define TIM_TIM11_MCO1 (0x00000003U) |
| AnnaBridge | 171:3a7713b1edbc | 197 | /** |
| AnnaBridge | 171:3a7713b1edbc | 198 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 199 | */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | |
| AnnaBridge | 171:3a7713b1edbc | 201 | /** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source |
| AnnaBridge | 171:3a7713b1edbc | 202 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 203 | */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U) |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U) |
| AnnaBridge | 171:3a7713b1edbc | 206 | /** |
| AnnaBridge | 171:3a7713b1edbc | 207 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 208 | */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | |
| AnnaBridge | 171:3a7713b1edbc | 210 | /** @defgroup TIMEx_Break2_Input_enable_disable TIMEx Break input 2 Enable |
| AnnaBridge | 171:3a7713b1edbc | 211 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 212 | */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | #define TIM_BREAK2_DISABLE ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) |
| AnnaBridge | 171:3a7713b1edbc | 215 | /** |
| AnnaBridge | 171:3a7713b1edbc | 216 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 217 | */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | |
| AnnaBridge | 171:3a7713b1edbc | 219 | /** @defgroup TIMEx_Break2_Polarity TIMEx Break2 Polarity |
| AnnaBridge | 171:3a7713b1edbc | 220 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 221 | */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define TIM_BREAK2POLARITY_HIGH (TIM_BDTR_BK2P) |
| AnnaBridge | 171:3a7713b1edbc | 224 | /** |
| AnnaBridge | 171:3a7713b1edbc | 225 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 226 | */ |
| AnnaBridge | 171:3a7713b1edbc | 227 | |
| AnnaBridge | 171:3a7713b1edbc | 228 | /** @defgroup TIMEx_Group_Channel5 TIMEx Group Channel 5 and Channel 1, 2 or 3 |
| AnnaBridge | 171:3a7713b1edbc | 229 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 230 | */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define TIM_GROUPCH5_NONE ((uint32_t)0x00000000U) /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | /** |
| AnnaBridge | 171:3a7713b1edbc | 236 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 237 | */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | |
| AnnaBridge | 171:3a7713b1edbc | 239 | /** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2) |
| AnnaBridge | 171:3a7713b1edbc | 240 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 241 | */ |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define TIM_TRGO2_RESET ((uint32_t)0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 243 | #define TIM_TRGO2_ENABLE ((uint32_t)(TIM_CR2_MMS2_0)) |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define TIM_TRGO2_UPDATE ((uint32_t)(TIM_CR2_MMS2_1)) |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define TIM_TRGO2_OC1 ((uint32_t)(TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define TIM_TRGO2_OC1REF ((uint32_t)(TIM_CR2_MMS2_2)) |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define TIM_TRGO2_OC2REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define TIM_TRGO2_OC3REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)) |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define TIM_TRGO2_OC4REF ((uint32_t)(TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define TIM_TRGO2_OC5REF ((uint32_t)(TIM_CR2_MMS2_3)) |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define TIM_TRGO2_OC6REF ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)) |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define TIM_TRGO2_OC4REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)) |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define TIM_TRGO2_OC6REF_RISINGFALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
| AnnaBridge | 171:3a7713b1edbc | 254 | #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)) |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)) |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)) |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING ((uint32_t)(TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)) |
| AnnaBridge | 171:3a7713b1edbc | 258 | /** |
| AnnaBridge | 171:3a7713b1edbc | 259 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 260 | */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | |
| AnnaBridge | 171:3a7713b1edbc | 262 | /** @defgroup TIMEx_Slave_Mode TIMEx Slave mode |
| AnnaBridge | 171:3a7713b1edbc | 263 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 264 | */ |
| AnnaBridge | 171:3a7713b1edbc | 265 | #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U) |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define TIM_SLAVEMODE_RESET ((uint32_t)(TIM_SMCR_SMS_2)) |
| AnnaBridge | 171:3a7713b1edbc | 267 | #define TIM_SLAVEMODE_GATED ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)) |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define TIM_SLAVEMODE_TRIGGER ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)) |
| AnnaBridge | 171:3a7713b1edbc | 269 | #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)(TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)) |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER ((uint32_t)(TIM_SMCR_SMS_3)) |
| AnnaBridge | 171:3a7713b1edbc | 271 | /** |
| AnnaBridge | 171:3a7713b1edbc | 272 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 273 | */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | #if defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) |
| AnnaBridge | 171:3a7713b1edbc | 275 | /** @defgroup TIMEx_Break_Input TIM Extended Break input |
| AnnaBridge | 171:3a7713b1edbc | 276 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 277 | */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define TIM_BREAKINPUT_BRK ((uint32_t)0x00000001U) /* !< Timer break input */ |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define TIM_BREAKINPUT_BRK2 ((uint32_t)0x00000002U) /* !< Timer break2 input */ |
| AnnaBridge | 171:3a7713b1edbc | 280 | /** |
| AnnaBridge | 171:3a7713b1edbc | 281 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 282 | */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | |
| AnnaBridge | 171:3a7713b1edbc | 284 | /** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source |
| AnnaBridge | 171:3a7713b1edbc | 285 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 286 | */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | #define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | /** |
| AnnaBridge | 171:3a7713b1edbc | 290 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 291 | */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | |
| AnnaBridge | 171:3a7713b1edbc | 293 | /** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling |
| AnnaBridge | 171:3a7713b1edbc | 294 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 295 | */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)0x00000000U) /* !< Break input source is disabled */ |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)0x00000001U) /* !< Break input source is enabled */ |
| AnnaBridge | 171:3a7713b1edbc | 298 | /** |
| AnnaBridge | 171:3a7713b1edbc | 299 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 300 | */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | |
| AnnaBridge | 171:3a7713b1edbc | 302 | /** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity |
| AnnaBridge | 171:3a7713b1edbc | 303 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 304 | */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | /** |
| AnnaBridge | 171:3a7713b1edbc | 308 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 309 | */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | |
| AnnaBridge | 171:3a7713b1edbc | 311 | /** |
| AnnaBridge | 171:3a7713b1edbc | 312 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 313 | */ |
| AnnaBridge | 171:3a7713b1edbc | 314 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | /** |
| AnnaBridge | 171:3a7713b1edbc | 316 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 317 | */ |
| AnnaBridge | 171:3a7713b1edbc | 318 | |
| AnnaBridge | 171:3a7713b1edbc | 319 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 320 | /** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 321 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 322 | */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | |
| AnnaBridge | 171:3a7713b1edbc | 324 | /** |
| AnnaBridge | 171:3a7713b1edbc | 325 | * @brief Sets the TIM Capture Compare Register value on runtime without |
| AnnaBridge | 171:3a7713b1edbc | 326 | * calling another time ConfigChannel function. |
| AnnaBridge | 171:3a7713b1edbc | 327 | * @param __HANDLE__ TIM handle. |
| AnnaBridge | 171:3a7713b1edbc | 328 | * @param __CHANNEL__ TIM Channels to be configured. |
| AnnaBridge | 171:3a7713b1edbc | 329 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 330 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| AnnaBridge | 171:3a7713b1edbc | 331 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| AnnaBridge | 171:3a7713b1edbc | 332 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| AnnaBridge | 171:3a7713b1edbc | 333 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| AnnaBridge | 171:3a7713b1edbc | 334 | * @arg TIM_CHANNEL_5: TIM Channel 5 selected |
| AnnaBridge | 171:3a7713b1edbc | 335 | * @arg TIM_CHANNEL_6: TIM Channel 6 selected |
| AnnaBridge | 171:3a7713b1edbc | 336 | * @param __COMPARE__ specifies the Capture Compare register new value. |
| AnnaBridge | 171:3a7713b1edbc | 337 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 338 | */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 340 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ |
| AnnaBridge | 171:3a7713b1edbc | 341 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ |
| AnnaBridge | 171:3a7713b1edbc | 342 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ |
| AnnaBridge | 171:3a7713b1edbc | 343 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ |
| AnnaBridge | 171:3a7713b1edbc | 344 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ |
| AnnaBridge | 171:3a7713b1edbc | 345 | ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) |
| AnnaBridge | 171:3a7713b1edbc | 346 | |
| AnnaBridge | 171:3a7713b1edbc | 347 | /** |
| AnnaBridge | 171:3a7713b1edbc | 348 | * @brief Gets the TIM Capture Compare Register value on runtime |
| AnnaBridge | 171:3a7713b1edbc | 349 | * @param __HANDLE__ TIM handle. |
| AnnaBridge | 171:3a7713b1edbc | 350 | * @param __CHANNEL__ TIM Channel associated with the capture compare register |
| AnnaBridge | 171:3a7713b1edbc | 351 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 352 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
| AnnaBridge | 171:3a7713b1edbc | 353 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
| AnnaBridge | 171:3a7713b1edbc | 354 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
| AnnaBridge | 171:3a7713b1edbc | 355 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
| AnnaBridge | 171:3a7713b1edbc | 356 | * @arg TIM_CHANNEL_5: get capture/compare 5 register value |
| AnnaBridge | 171:3a7713b1edbc | 357 | * @arg TIM_CHANNEL_6: get capture/compare 6 register value |
| AnnaBridge | 171:3a7713b1edbc | 358 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 359 | */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ |
| AnnaBridge | 171:3a7713b1edbc | 361 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ |
| AnnaBridge | 171:3a7713b1edbc | 362 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ |
| AnnaBridge | 171:3a7713b1edbc | 363 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ |
| AnnaBridge | 171:3a7713b1edbc | 364 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ |
| AnnaBridge | 171:3a7713b1edbc | 365 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ |
| AnnaBridge | 171:3a7713b1edbc | 366 | ((__HANDLE__)->Instance->CCR6)) |
| AnnaBridge | 171:3a7713b1edbc | 367 | |
| AnnaBridge | 171:3a7713b1edbc | 368 | /** |
| AnnaBridge | 171:3a7713b1edbc | 369 | * @brief Sets the TIM Output compare preload. |
| AnnaBridge | 171:3a7713b1edbc | 370 | * @param __HANDLE__ TIM handle. |
| AnnaBridge | 171:3a7713b1edbc | 371 | * @param __CHANNEL__ TIM Channels to be configured. |
| AnnaBridge | 171:3a7713b1edbc | 372 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 373 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| AnnaBridge | 171:3a7713b1edbc | 374 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| AnnaBridge | 171:3a7713b1edbc | 375 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| AnnaBridge | 171:3a7713b1edbc | 376 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| AnnaBridge | 171:3a7713b1edbc | 377 | * @arg TIM_CHANNEL_5: TIM Channel 5 selected |
| AnnaBridge | 171:3a7713b1edbc | 378 | * @arg TIM_CHANNEL_6: TIM Channel 6 selected |
| AnnaBridge | 171:3a7713b1edbc | 379 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 380 | */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
| AnnaBridge | 171:3a7713b1edbc | 382 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ |
| AnnaBridge | 171:3a7713b1edbc | 383 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ |
| AnnaBridge | 171:3a7713b1edbc | 384 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ |
| AnnaBridge | 171:3a7713b1edbc | 385 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ |
| AnnaBridge | 171:3a7713b1edbc | 386 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ |
| AnnaBridge | 171:3a7713b1edbc | 387 | ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) |
| AnnaBridge | 171:3a7713b1edbc | 388 | |
| AnnaBridge | 171:3a7713b1edbc | 389 | /** |
| AnnaBridge | 171:3a7713b1edbc | 390 | * @brief Resets the TIM Output compare preload. |
| AnnaBridge | 171:3a7713b1edbc | 391 | * @param __HANDLE__ TIM handle. |
| AnnaBridge | 171:3a7713b1edbc | 392 | * @param __CHANNEL__ TIM Channels to be configured. |
| AnnaBridge | 171:3a7713b1edbc | 393 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 394 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| AnnaBridge | 171:3a7713b1edbc | 395 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| AnnaBridge | 171:3a7713b1edbc | 396 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| AnnaBridge | 171:3a7713b1edbc | 397 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| AnnaBridge | 171:3a7713b1edbc | 398 | * @arg TIM_CHANNEL_5: TIM Channel 5 selected |
| AnnaBridge | 171:3a7713b1edbc | 399 | * @arg TIM_CHANNEL_6: TIM Channel 6 selected |
| AnnaBridge | 171:3a7713b1edbc | 400 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 401 | */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ |
| AnnaBridge | 171:3a7713b1edbc | 403 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ |
| AnnaBridge | 171:3a7713b1edbc | 404 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ |
| AnnaBridge | 171:3a7713b1edbc | 405 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ |
| AnnaBridge | 171:3a7713b1edbc | 406 | ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ |
| AnnaBridge | 171:3a7713b1edbc | 407 | ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ |
| AnnaBridge | 171:3a7713b1edbc | 408 | ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) |
| AnnaBridge | 171:3a7713b1edbc | 409 | |
| AnnaBridge | 171:3a7713b1edbc | 410 | /** |
| AnnaBridge | 171:3a7713b1edbc | 411 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 412 | */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | |
| AnnaBridge | 171:3a7713b1edbc | 414 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 415 | /** @addtogroup TIMEx_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 416 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 417 | */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | |
| AnnaBridge | 171:3a7713b1edbc | 419 | /** @addtogroup TIMEx_Exported_Functions_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 420 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 421 | */ |
| AnnaBridge | 171:3a7713b1edbc | 422 | /* Timer Hall Sensor functions **********************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 423 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef* htim, TIM_HallSensor_InitTypeDef* sConfig); |
| AnnaBridge | 171:3a7713b1edbc | 424 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef* htim); |
| AnnaBridge | 171:3a7713b1edbc | 425 | |
| AnnaBridge | 171:3a7713b1edbc | 426 | void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef* htim); |
| AnnaBridge | 171:3a7713b1edbc | 427 | void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef* htim); |
| AnnaBridge | 171:3a7713b1edbc | 428 | |
| AnnaBridge | 171:3a7713b1edbc | 429 | /* Blocking mode: Polling */ |
| AnnaBridge | 171:3a7713b1edbc | 430 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef* htim); |
| AnnaBridge | 171:3a7713b1edbc | 431 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef* htim); |
| AnnaBridge | 171:3a7713b1edbc | 432 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 433 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef* htim); |
| AnnaBridge | 171:3a7713b1edbc | 434 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef* htim); |
| AnnaBridge | 171:3a7713b1edbc | 435 | /* Non-Blocking mode: DMA */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef* htim, uint32_t *pData, uint16_t Length); |
| AnnaBridge | 171:3a7713b1edbc | 437 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef* htim); |
| AnnaBridge | 171:3a7713b1edbc | 438 | /** |
| AnnaBridge | 171:3a7713b1edbc | 439 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 440 | */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | |
| AnnaBridge | 171:3a7713b1edbc | 442 | /** @addtogroup TIMEx_Exported_Functions_Group2 |
| AnnaBridge | 171:3a7713b1edbc | 443 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 444 | */ |
| AnnaBridge | 171:3a7713b1edbc | 445 | /* Timer Complementary Output Compare functions *****************************/ |
| AnnaBridge | 171:3a7713b1edbc | 446 | /* Blocking mode: Polling */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef* htim, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 448 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 449 | |
| AnnaBridge | 171:3a7713b1edbc | 450 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 452 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 453 | |
| AnnaBridge | 171:3a7713b1edbc | 454 | /* Non-Blocking mode: DMA */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
| AnnaBridge | 171:3a7713b1edbc | 456 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 457 | /** |
| AnnaBridge | 171:3a7713b1edbc | 458 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 459 | */ |
| AnnaBridge | 171:3a7713b1edbc | 460 | |
| AnnaBridge | 171:3a7713b1edbc | 461 | /** @addtogroup TIMEx_Exported_Functions_Group3 |
| AnnaBridge | 171:3a7713b1edbc | 462 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 463 | */ |
| AnnaBridge | 171:3a7713b1edbc | 464 | /* Timer Complementary PWM functions ****************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 465 | /* Blocking mode: Polling */ |
| AnnaBridge | 171:3a7713b1edbc | 466 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef* htim, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 467 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef* htim, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 468 | |
| AnnaBridge | 171:3a7713b1edbc | 469 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 470 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef* htim, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 471 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 472 | /* Non-Blocking mode: DMA */ |
| AnnaBridge | 171:3a7713b1edbc | 473 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef* htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
| AnnaBridge | 171:3a7713b1edbc | 474 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef* htim, uint32_t Channel); |
| AnnaBridge | 171:3a7713b1edbc | 475 | /** |
| AnnaBridge | 171:3a7713b1edbc | 476 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 477 | */ |
| AnnaBridge | 171:3a7713b1edbc | 478 | |
| AnnaBridge | 171:3a7713b1edbc | 479 | /** @addtogroup TIMEx_Exported_Functions_Group4 |
| AnnaBridge | 171:3a7713b1edbc | 480 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 481 | */ |
| AnnaBridge | 171:3a7713b1edbc | 482 | /* Timer Complementary One Pulse functions **********************************/ |
| AnnaBridge | 171:3a7713b1edbc | 483 | /* Blocking mode: Polling */ |
| AnnaBridge | 171:3a7713b1edbc | 484 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef* htim, uint32_t OutputChannel); |
| AnnaBridge | 171:3a7713b1edbc | 485 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef* htim, uint32_t OutputChannel); |
| AnnaBridge | 171:3a7713b1edbc | 486 | |
| AnnaBridge | 171:3a7713b1edbc | 487 | /* Non-Blocking mode: Interrupt */ |
| AnnaBridge | 171:3a7713b1edbc | 488 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel); |
| AnnaBridge | 171:3a7713b1edbc | 489 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef* htim, uint32_t OutputChannel); |
| AnnaBridge | 171:3a7713b1edbc | 490 | /** |
| AnnaBridge | 171:3a7713b1edbc | 491 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 492 | */ |
| AnnaBridge | 171:3a7713b1edbc | 493 | |
| AnnaBridge | 171:3a7713b1edbc | 494 | /** @addtogroup TIMEx_Exported_Functions_Group5 |
| AnnaBridge | 171:3a7713b1edbc | 495 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 496 | */ |
| AnnaBridge | 171:3a7713b1edbc | 497 | /* Extension Control functions ************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 498 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource); |
| AnnaBridge | 171:3a7713b1edbc | 499 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource); |
| AnnaBridge | 171:3a7713b1edbc | 500 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef* htim, uint32_t InputTrigger, uint32_t CommutationSource); |
| AnnaBridge | 171:3a7713b1edbc | 501 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef* htim, TIM_MasterConfigTypeDef * sMasterConfig); |
| AnnaBridge | 171:3a7713b1edbc | 502 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef* htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); |
| AnnaBridge | 171:3a7713b1edbc | 503 | #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) |
| AnnaBridge | 171:3a7713b1edbc | 504 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); |
| AnnaBridge | 171:3a7713b1edbc | 505 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
| AnnaBridge | 171:3a7713b1edbc | 506 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef* htim, uint32_t Remap); |
| AnnaBridge | 171:3a7713b1edbc | 507 | HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t OCRef); |
| AnnaBridge | 171:3a7713b1edbc | 508 | /** |
| AnnaBridge | 171:3a7713b1edbc | 509 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 510 | */ |
| AnnaBridge | 171:3a7713b1edbc | 511 | |
| AnnaBridge | 171:3a7713b1edbc | 512 | /** @addtogroup TIMEx_Exported_Functions_Group6 |
| AnnaBridge | 171:3a7713b1edbc | 513 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 514 | */ |
| AnnaBridge | 171:3a7713b1edbc | 515 | /* Extension Callback *********************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 516 | void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef* htim); |
| AnnaBridge | 171:3a7713b1edbc | 517 | void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef* htim); |
| AnnaBridge | 171:3a7713b1edbc | 518 | void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); |
| AnnaBridge | 171:3a7713b1edbc | 519 | /** |
| AnnaBridge | 171:3a7713b1edbc | 520 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 521 | */ |
| AnnaBridge | 171:3a7713b1edbc | 522 | |
| AnnaBridge | 171:3a7713b1edbc | 523 | /** @addtogroup TIMEx_Exported_Functions_Group7 |
| AnnaBridge | 171:3a7713b1edbc | 524 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 525 | */ |
| AnnaBridge | 171:3a7713b1edbc | 526 | /* Extension Peripheral State functions **************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 527 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim); |
| AnnaBridge | 171:3a7713b1edbc | 528 | /** |
| AnnaBridge | 171:3a7713b1edbc | 529 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 530 | */ |
| AnnaBridge | 171:3a7713b1edbc | 531 | |
| AnnaBridge | 171:3a7713b1edbc | 532 | /** |
| AnnaBridge | 171:3a7713b1edbc | 533 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 534 | */ |
| AnnaBridge | 171:3a7713b1edbc | 535 | |
| AnnaBridge | 171:3a7713b1edbc | 536 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 537 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 538 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 539 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 540 | /** @defgroup TIMEx_Private_Macros TIMEx Private Macros |
| AnnaBridge | 171:3a7713b1edbc | 541 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 542 | */ |
| AnnaBridge | 171:3a7713b1edbc | 543 | #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 544 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 545 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| AnnaBridge | 171:3a7713b1edbc | 546 | ((CHANNEL) == TIM_CHANNEL_4) || \ |
| AnnaBridge | 171:3a7713b1edbc | 547 | ((CHANNEL) == TIM_CHANNEL_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 548 | ((CHANNEL) == TIM_CHANNEL_6) || \ |
| AnnaBridge | 171:3a7713b1edbc | 549 | ((CHANNEL) == TIM_CHANNEL_ALL)) |
| AnnaBridge | 171:3a7713b1edbc | 550 | |
| AnnaBridge | 171:3a7713b1edbc | 551 | #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 552 | ((CHANNEL) == TIM_CHANNEL_2)) |
| AnnaBridge | 171:3a7713b1edbc | 553 | |
| AnnaBridge | 171:3a7713b1edbc | 554 | #define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 555 | ((CHANNEL) == TIM_CHANNEL_2)) |
| AnnaBridge | 171:3a7713b1edbc | 556 | |
| AnnaBridge | 171:3a7713b1edbc | 557 | #define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 558 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 559 | ((CHANNEL) == TIM_CHANNEL_3)) |
| AnnaBridge | 171:3a7713b1edbc | 560 | #define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 561 | ((MODE) == TIM_OCMODE_PWM2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 562 | ((MODE) == TIM_OCMODE_COMBINED_PWM1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 563 | ((MODE) == TIM_OCMODE_COMBINED_PWM2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 564 | ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 565 | ((MODE) == TIM_OCMODE_ASSYMETRIC_PWM2)) |
| AnnaBridge | 171:3a7713b1edbc | 566 | |
| AnnaBridge | 171:3a7713b1edbc | 567 | #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 568 | ((MODE) == TIM_OCMODE_ACTIVE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 569 | ((MODE) == TIM_OCMODE_INACTIVE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 570 | ((MODE) == TIM_OCMODE_TOGGLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 571 | ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 572 | ((MODE) == TIM_OCMODE_FORCED_INACTIVE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 573 | ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 574 | ((MODE) == TIM_OCMODE_RETRIGERRABLE_OPM2)) |
| AnnaBridge | 171:3a7713b1edbc | 575 | #define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\ |
| AnnaBridge | 171:3a7713b1edbc | 576 | ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP)||\ |
| AnnaBridge | 171:3a7713b1edbc | 577 | ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\ |
| AnnaBridge | 171:3a7713b1edbc | 578 | ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\ |
| AnnaBridge | 171:3a7713b1edbc | 579 | ((__TIM_REMAP__) == TIM_TIM5_GPIO)||\ |
| AnnaBridge | 171:3a7713b1edbc | 580 | ((__TIM_REMAP__) == TIM_TIM5_LSI)||\ |
| AnnaBridge | 171:3a7713b1edbc | 581 | ((__TIM_REMAP__) == TIM_TIM5_LSE)||\ |
| AnnaBridge | 171:3a7713b1edbc | 582 | ((__TIM_REMAP__) == TIM_TIM5_RTC)||\ |
| AnnaBridge | 171:3a7713b1edbc | 583 | ((__TIM_REMAP__) == TIM_TIM11_GPIO)||\ |
| AnnaBridge | 171:3a7713b1edbc | 584 | ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX)||\ |
| AnnaBridge | 171:3a7713b1edbc | 585 | ((__TIM_REMAP__) == TIM_TIM11_HSE)||\ |
| AnnaBridge | 171:3a7713b1edbc | 586 | ((__TIM_REMAP__) == TIM_TIM11_MCO1)) |
| AnnaBridge | 171:3a7713b1edbc | 587 | #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFF) |
| AnnaBridge | 171:3a7713b1edbc | 588 | #define IS_TIM_BREAK_FILTER(__FILTER__) ((__FILTER__) <= 0xF) |
| AnnaBridge | 171:3a7713b1edbc | 589 | #define IS_TIM_CLEARINPUT_SOURCE(MODE) (((MODE) == TIM_CLEARINPUTSOURCE_ETR) || \ |
| AnnaBridge | 171:3a7713b1edbc | 590 | ((MODE) == TIM_CLEARINPUTSOURCE_NONE)) |
| AnnaBridge | 171:3a7713b1edbc | 591 | #define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_BREAK2_ENABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 592 | ((STATE) == TIM_BREAK2_DISABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 593 | #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ |
| AnnaBridge | 171:3a7713b1edbc | 594 | ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) |
| AnnaBridge | 171:3a7713b1edbc | 595 | #define IS_TIM_GROUPCH5(OCREF) ((((OCREF) & 0x1FFFFFFF) == 0x00000000)) |
| AnnaBridge | 171:3a7713b1edbc | 596 | #define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2_RESET) || \ |
| AnnaBridge | 171:3a7713b1edbc | 597 | ((SOURCE) == TIM_TRGO2_ENABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 598 | ((SOURCE) == TIM_TRGO2_UPDATE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 599 | ((SOURCE) == TIM_TRGO2_OC1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 600 | ((SOURCE) == TIM_TRGO2_OC1REF) || \ |
| AnnaBridge | 171:3a7713b1edbc | 601 | ((SOURCE) == TIM_TRGO2_OC2REF) || \ |
| AnnaBridge | 171:3a7713b1edbc | 602 | ((SOURCE) == TIM_TRGO2_OC3REF) || \ |
| AnnaBridge | 171:3a7713b1edbc | 603 | ((SOURCE) == TIM_TRGO2_OC3REF) || \ |
| AnnaBridge | 171:3a7713b1edbc | 604 | ((SOURCE) == TIM_TRGO2_OC4REF) || \ |
| AnnaBridge | 171:3a7713b1edbc | 605 | ((SOURCE) == TIM_TRGO2_OC5REF) || \ |
| AnnaBridge | 171:3a7713b1edbc | 606 | ((SOURCE) == TIM_TRGO2_OC6REF) || \ |
| AnnaBridge | 171:3a7713b1edbc | 607 | ((SOURCE) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 608 | ((SOURCE) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 609 | ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 610 | ((SOURCE) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 611 | ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 612 | ((SOURCE) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) |
| AnnaBridge | 171:3a7713b1edbc | 613 | #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 614 | ((MODE) == TIM_SLAVEMODE_RESET) || \ |
| AnnaBridge | 171:3a7713b1edbc | 615 | ((MODE) == TIM_SLAVEMODE_GATED) || \ |
| AnnaBridge | 171:3a7713b1edbc | 616 | ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ |
| AnnaBridge | 171:3a7713b1edbc | 617 | ((MODE) == TIM_SLAVEMODE_EXTERNAL1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 618 | ((MODE) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) |
| AnnaBridge | 171:3a7713b1edbc | 619 | |
| AnnaBridge | 171:3a7713b1edbc | 620 | #if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) |
| AnnaBridge | 171:3a7713b1edbc | 621 | #define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ |
| AnnaBridge | 171:3a7713b1edbc | 622 | ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) |
| AnnaBridge | 171:3a7713b1edbc | 623 | |
| AnnaBridge | 171:3a7713b1edbc | 624 | #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ |
| AnnaBridge | 171:3a7713b1edbc | 625 | ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM)) |
| AnnaBridge | 171:3a7713b1edbc | 626 | |
| AnnaBridge | 171:3a7713b1edbc | 627 | #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 628 | ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 629 | |
| AnnaBridge | 171:3a7713b1edbc | 630 | #define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ |
| AnnaBridge | 171:3a7713b1edbc | 631 | ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) |
| AnnaBridge | 171:3a7713b1edbc | 632 | |
| AnnaBridge | 171:3a7713b1edbc | 633 | #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ |
| AnnaBridge | 171:3a7713b1edbc | 634 | /** |
| AnnaBridge | 171:3a7713b1edbc | 635 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 636 | */ |
| AnnaBridge | 171:3a7713b1edbc | 637 | |
| AnnaBridge | 171:3a7713b1edbc | 638 | /* Private functions ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 639 | /** @defgroup TIMEx_Private_Functions TIMEx Private Functions |
| AnnaBridge | 171:3a7713b1edbc | 640 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 641 | */ |
| AnnaBridge | 171:3a7713b1edbc | 642 | |
| AnnaBridge | 171:3a7713b1edbc | 643 | /** |
| AnnaBridge | 171:3a7713b1edbc | 644 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 645 | */ |
| AnnaBridge | 171:3a7713b1edbc | 646 | |
| AnnaBridge | 171:3a7713b1edbc | 647 | /** |
| AnnaBridge | 171:3a7713b1edbc | 648 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 649 | */ |
| AnnaBridge | 171:3a7713b1edbc | 650 | |
| AnnaBridge | 171:3a7713b1edbc | 651 | /** |
| AnnaBridge | 171:3a7713b1edbc | 652 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 653 | */ |
| AnnaBridge | 171:3a7713b1edbc | 654 | |
| AnnaBridge | 171:3a7713b1edbc | 655 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 656 | } |
| AnnaBridge | 171:3a7713b1edbc | 657 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 658 | |
| AnnaBridge | 171:3a7713b1edbc | 659 | #endif /* __STM32F7xx_HAL_TIM_EX_H */ |
| AnnaBridge | 171:3a7713b1edbc | 660 | |
| AnnaBridge | 171:3a7713b1edbc | 661 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
