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TARGET_DISCO_F769NI/TOOLCHAIN_GCC_ARM/stm32f7xx_ll_fmc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f7xx_ll_fmc.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of FMC HAL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32F7xx_LL_FMC_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32F7xx_LL_FMC_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32f7xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32F7xx_HAL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	/** @addtogroup FMC_LL
AnnaBridge	171:3a7713b1edbc	52	* @{
AnnaBridge	171:3a7713b1edbc	53	*/
AnnaBridge	171:3a7713b1edbc	54
AnnaBridge	171:3a7713b1edbc	55	/** @addtogroup FMC_LL_Private_Macros
AnnaBridge	171:3a7713b1edbc	56	* @{
AnnaBridge	171:3a7713b1edbc	57	*/
AnnaBridge	171:3a7713b1edbc	58	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
AnnaBridge	171:3a7713b1edbc	59	((BANK) == FMC_NORSRAM_BANK2) \|\| \
AnnaBridge	171:3a7713b1edbc	60	((BANK) == FMC_NORSRAM_BANK3) \|\| \
AnnaBridge	171:3a7713b1edbc	61	((BANK) == FMC_NORSRAM_BANK4))
AnnaBridge	171:3a7713b1edbc	62
AnnaBridge	171:3a7713b1edbc	63	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	64	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
AnnaBridge	171:3a7713b1edbc	65
AnnaBridge	171:3a7713b1edbc	66	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
AnnaBridge	171:3a7713b1edbc	67	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
AnnaBridge	171:3a7713b1edbc	68	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
AnnaBridge	171:3a7713b1edbc	69
AnnaBridge	171:3a7713b1edbc	70	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	171:3a7713b1edbc	71	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
AnnaBridge	171:3a7713b1edbc	72	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
AnnaBridge	171:3a7713b1edbc	73
AnnaBridge	171:3a7713b1edbc	74	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
AnnaBridge	171:3a7713b1edbc	75	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
AnnaBridge	171:3a7713b1edbc	76	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
AnnaBridge	171:3a7713b1edbc	77	((__MODE__) == FMC_ACCESS_MODE_D))
AnnaBridge	171:3a7713b1edbc	78
AnnaBridge	171:3a7713b1edbc	79	#define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)
AnnaBridge	171:3a7713b1edbc	80
AnnaBridge	171:3a7713b1edbc	81	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	82	((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))
AnnaBridge	171:3a7713b1edbc	83
AnnaBridge	171:3a7713b1edbc	84	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	171:3a7713b1edbc	85	((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))
AnnaBridge	171:3a7713b1edbc	86
AnnaBridge	171:3a7713b1edbc	87	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	88	((STATE) == FMC_NAND_ECC_ENABLE))
AnnaBridge	171:3a7713b1edbc	89
AnnaBridge	171:3a7713b1edbc	90	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	91	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	92	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	93	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	94	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	95	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
AnnaBridge	171:3a7713b1edbc	96
AnnaBridge	171:3a7713b1edbc	97	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	171:3a7713b1edbc	98	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
AnnaBridge	171:3a7713b1edbc	99	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
AnnaBridge	171:3a7713b1edbc	100
AnnaBridge	171:3a7713b1edbc	101	#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	102	((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
AnnaBridge	171:3a7713b1edbc	103
AnnaBridge	171:3a7713b1edbc	104	#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	105	((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
AnnaBridge	171:3a7713b1edbc	106	((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
AnnaBridge	171:3a7713b1edbc	107
AnnaBridge	171:3a7713b1edbc	108	#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	109	((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
AnnaBridge	171:3a7713b1edbc	110
AnnaBridge	171:3a7713b1edbc	111	#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
AnnaBridge	171:3a7713b1edbc	112	((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
AnnaBridge	171:3a7713b1edbc	113	((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
AnnaBridge	171:3a7713b1edbc	114
AnnaBridge	171:3a7713b1edbc	115	#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
AnnaBridge	171:3a7713b1edbc	116	((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	117	((__COMMAND__) == FMC_SDRAM_CMD_PALL) \|\| \
AnnaBridge	171:3a7713b1edbc	118	((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
AnnaBridge	171:3a7713b1edbc	119	((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
AnnaBridge	171:3a7713b1edbc	120	((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
AnnaBridge	171:3a7713b1edbc	121	((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
AnnaBridge	171:3a7713b1edbc	122
AnnaBridge	171:3a7713b1edbc	123	#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
AnnaBridge	171:3a7713b1edbc	124	((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
AnnaBridge	171:3a7713b1edbc	125	((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
AnnaBridge	171:3a7713b1edbc	126
AnnaBridge	171:3a7713b1edbc	127	/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
AnnaBridge	171:3a7713b1edbc	128	* @{
AnnaBridge	171:3a7713b1edbc	129	*/
AnnaBridge	171:3a7713b1edbc	130	#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
AnnaBridge	171:3a7713b1edbc	131	/**
AnnaBridge	171:3a7713b1edbc	132	* @}
AnnaBridge	171:3a7713b1edbc	133	*/
AnnaBridge	171:3a7713b1edbc	134
AnnaBridge	171:3a7713b1edbc	135	/** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time
AnnaBridge	171:3a7713b1edbc	136	* @{
AnnaBridge	171:3a7713b1edbc	137	*/
AnnaBridge	171:3a7713b1edbc	138	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
AnnaBridge	171:3a7713b1edbc	139	/**
AnnaBridge	171:3a7713b1edbc	140	* @}
AnnaBridge	171:3a7713b1edbc	141	*/
AnnaBridge	171:3a7713b1edbc	142
AnnaBridge	171:3a7713b1edbc	143	/** @defgroup FMC_Setup_Time FMC Setup Time
AnnaBridge	171:3a7713b1edbc	144	* @{
AnnaBridge	171:3a7713b1edbc	145	*/
AnnaBridge	171:3a7713b1edbc	146	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254)
AnnaBridge	171:3a7713b1edbc	147	/**
AnnaBridge	171:3a7713b1edbc	148	* @}
AnnaBridge	171:3a7713b1edbc	149	*/
AnnaBridge	171:3a7713b1edbc	150
AnnaBridge	171:3a7713b1edbc	151	/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time
AnnaBridge	171:3a7713b1edbc	152	* @{
AnnaBridge	171:3a7713b1edbc	153	*/
AnnaBridge	171:3a7713b1edbc	154	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254)
AnnaBridge	171:3a7713b1edbc	155	/**
AnnaBridge	171:3a7713b1edbc	156	* @}
AnnaBridge	171:3a7713b1edbc	157	*/
AnnaBridge	171:3a7713b1edbc	158
AnnaBridge	171:3a7713b1edbc	159	/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time
AnnaBridge	171:3a7713b1edbc	160	* @{
AnnaBridge	171:3a7713b1edbc	161	*/
AnnaBridge	171:3a7713b1edbc	162	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254)
AnnaBridge	171:3a7713b1edbc	163	/**
AnnaBridge	171:3a7713b1edbc	164	* @}
AnnaBridge	171:3a7713b1edbc	165	*/
AnnaBridge	171:3a7713b1edbc	166
AnnaBridge	171:3a7713b1edbc	167	/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time
AnnaBridge	171:3a7713b1edbc	168	* @{
AnnaBridge	171:3a7713b1edbc	169	*/
AnnaBridge	171:3a7713b1edbc	170	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254)
AnnaBridge	171:3a7713b1edbc	171	/**
AnnaBridge	171:3a7713b1edbc	172	* @}
AnnaBridge	171:3a7713b1edbc	173	*/
AnnaBridge	171:3a7713b1edbc	174
AnnaBridge	171:3a7713b1edbc	175	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	176	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
AnnaBridge	171:3a7713b1edbc	177
AnnaBridge	171:3a7713b1edbc	178	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
AnnaBridge	171:3a7713b1edbc	179	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
AnnaBridge	171:3a7713b1edbc	180
AnnaBridge	171:3a7713b1edbc	181	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
AnnaBridge	171:3a7713b1edbc	182	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
AnnaBridge	171:3a7713b1edbc	183
AnnaBridge	171:3a7713b1edbc	184	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	185	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
AnnaBridge	171:3a7713b1edbc	186
AnnaBridge	171:3a7713b1edbc	187	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	188	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
AnnaBridge	171:3a7713b1edbc	189
AnnaBridge	171:3a7713b1edbc	190	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	191	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
AnnaBridge	171:3a7713b1edbc	192
AnnaBridge	171:3a7713b1edbc	193	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	194	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
AnnaBridge	171:3a7713b1edbc	195
AnnaBridge	171:3a7713b1edbc	196	/** @defgroup FMC_Data_Latency FMC Data Latency
AnnaBridge	171:3a7713b1edbc	197	* @{
AnnaBridge	171:3a7713b1edbc	198	*/
AnnaBridge	171:3a7713b1edbc	199	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
AnnaBridge	171:3a7713b1edbc	200	/**
AnnaBridge	171:3a7713b1edbc	201	* @}
AnnaBridge	171:3a7713b1edbc	202	*/
AnnaBridge	171:3a7713b1edbc	203
AnnaBridge	171:3a7713b1edbc	204	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	205	((__BURST__) == FMC_WRITE_BURST_ENABLE))
AnnaBridge	171:3a7713b1edbc	206
AnnaBridge	171:3a7713b1edbc	207	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
AnnaBridge	171:3a7713b1edbc	208	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
AnnaBridge	171:3a7713b1edbc	209
AnnaBridge	171:3a7713b1edbc	210
AnnaBridge	171:3a7713b1edbc	211	/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
AnnaBridge	171:3a7713b1edbc	212	* @{
AnnaBridge	171:3a7713b1edbc	213	*/
AnnaBridge	171:3a7713b1edbc	214	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
AnnaBridge	171:3a7713b1edbc	215	/**
AnnaBridge	171:3a7713b1edbc	216	* @}
AnnaBridge	171:3a7713b1edbc	217	*/
AnnaBridge	171:3a7713b1edbc	218
AnnaBridge	171:3a7713b1edbc	219	/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
AnnaBridge	171:3a7713b1edbc	220	* @{
AnnaBridge	171:3a7713b1edbc	221	*/
AnnaBridge	171:3a7713b1edbc	222	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
AnnaBridge	171:3a7713b1edbc	223	/**
AnnaBridge	171:3a7713b1edbc	224	* @}
AnnaBridge	171:3a7713b1edbc	225	*/
AnnaBridge	171:3a7713b1edbc	226
AnnaBridge	171:3a7713b1edbc	227	/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
AnnaBridge	171:3a7713b1edbc	228	* @{
AnnaBridge	171:3a7713b1edbc	229	*/
AnnaBridge	171:3a7713b1edbc	230	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
AnnaBridge	171:3a7713b1edbc	231	/**
AnnaBridge	171:3a7713b1edbc	232	* @}
AnnaBridge	171:3a7713b1edbc	233	*/
AnnaBridge	171:3a7713b1edbc	234
AnnaBridge	171:3a7713b1edbc	235	/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
AnnaBridge	171:3a7713b1edbc	236	* @{
AnnaBridge	171:3a7713b1edbc	237	*/
AnnaBridge	171:3a7713b1edbc	238	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
AnnaBridge	171:3a7713b1edbc	239	/**
AnnaBridge	171:3a7713b1edbc	240	* @}
AnnaBridge	171:3a7713b1edbc	241	*/
AnnaBridge	171:3a7713b1edbc	242
AnnaBridge	171:3a7713b1edbc	243	/** @defgroup FMC_CLK_Division FMC CLK Division
AnnaBridge	171:3a7713b1edbc	244	* @{
AnnaBridge	171:3a7713b1edbc	245	*/
AnnaBridge	171:3a7713b1edbc	246	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
AnnaBridge	171:3a7713b1edbc	247	/**
AnnaBridge	171:3a7713b1edbc	248	* @}
AnnaBridge	171:3a7713b1edbc	249	*/
AnnaBridge	171:3a7713b1edbc	250
AnnaBridge	171:3a7713b1edbc	251	/** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay
AnnaBridge	171:3a7713b1edbc	252	* @{
AnnaBridge	171:3a7713b1edbc	253	*/
AnnaBridge	171:3a7713b1edbc	254	#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
AnnaBridge	171:3a7713b1edbc	255	/**
AnnaBridge	171:3a7713b1edbc	256	* @}
AnnaBridge	171:3a7713b1edbc	257	*/
AnnaBridge	171:3a7713b1edbc	258
AnnaBridge	171:3a7713b1edbc	259	/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay
AnnaBridge	171:3a7713b1edbc	260	* @{
AnnaBridge	171:3a7713b1edbc	261	*/
AnnaBridge	171:3a7713b1edbc	262	#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
AnnaBridge	171:3a7713b1edbc	263	/**
AnnaBridge	171:3a7713b1edbc	264	* @}
AnnaBridge	171:3a7713b1edbc	265	*/
AnnaBridge	171:3a7713b1edbc	266
AnnaBridge	171:3a7713b1edbc	267	/** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time
AnnaBridge	171:3a7713b1edbc	268	* @{
AnnaBridge	171:3a7713b1edbc	269	*/
AnnaBridge	171:3a7713b1edbc	270	#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
AnnaBridge	171:3a7713b1edbc	271	/**
AnnaBridge	171:3a7713b1edbc	272	* @}
AnnaBridge	171:3a7713b1edbc	273	*/
AnnaBridge	171:3a7713b1edbc	274
AnnaBridge	171:3a7713b1edbc	275	/** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay
AnnaBridge	171:3a7713b1edbc	276	* @{
AnnaBridge	171:3a7713b1edbc	277	*/
AnnaBridge	171:3a7713b1edbc	278	#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
AnnaBridge	171:3a7713b1edbc	279	/**
AnnaBridge	171:3a7713b1edbc	280	* @}
AnnaBridge	171:3a7713b1edbc	281	*/
AnnaBridge	171:3a7713b1edbc	282
AnnaBridge	171:3a7713b1edbc	283	/** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time
AnnaBridge	171:3a7713b1edbc	284	* @{
AnnaBridge	171:3a7713b1edbc	285	*/
AnnaBridge	171:3a7713b1edbc	286	#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
AnnaBridge	171:3a7713b1edbc	287	/**
AnnaBridge	171:3a7713b1edbc	288	* @}
AnnaBridge	171:3a7713b1edbc	289	*/
AnnaBridge	171:3a7713b1edbc	290
AnnaBridge	171:3a7713b1edbc	291	/** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay
AnnaBridge	171:3a7713b1edbc	292	* @{
AnnaBridge	171:3a7713b1edbc	293	*/
AnnaBridge	171:3a7713b1edbc	294	#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
AnnaBridge	171:3a7713b1edbc	295	/**
AnnaBridge	171:3a7713b1edbc	296	* @}
AnnaBridge	171:3a7713b1edbc	297	*/
AnnaBridge	171:3a7713b1edbc	298
AnnaBridge	171:3a7713b1edbc	299	/** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay
AnnaBridge	171:3a7713b1edbc	300	* @{
AnnaBridge	171:3a7713b1edbc	301	*/
AnnaBridge	171:3a7713b1edbc	302	#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
AnnaBridge	171:3a7713b1edbc	303	/**
AnnaBridge	171:3a7713b1edbc	304	* @}
AnnaBridge	171:3a7713b1edbc	305	*/
AnnaBridge	171:3a7713b1edbc	306
AnnaBridge	171:3a7713b1edbc	307	/** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number
AnnaBridge	171:3a7713b1edbc	308	* @{
AnnaBridge	171:3a7713b1edbc	309	*/
AnnaBridge	171:3a7713b1edbc	310	#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))
AnnaBridge	171:3a7713b1edbc	311	/**
AnnaBridge	171:3a7713b1edbc	312	* @}
AnnaBridge	171:3a7713b1edbc	313	*/
AnnaBridge	171:3a7713b1edbc	314
AnnaBridge	171:3a7713b1edbc	315	/** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition
AnnaBridge	171:3a7713b1edbc	316	* @{
AnnaBridge	171:3a7713b1edbc	317	*/
AnnaBridge	171:3a7713b1edbc	318	#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)
AnnaBridge	171:3a7713b1edbc	319	/**
AnnaBridge	171:3a7713b1edbc	320	* @}
AnnaBridge	171:3a7713b1edbc	321	*/
AnnaBridge	171:3a7713b1edbc	322
AnnaBridge	171:3a7713b1edbc	323	/** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate
AnnaBridge	171:3a7713b1edbc	324	* @{
AnnaBridge	171:3a7713b1edbc	325	*/
AnnaBridge	171:3a7713b1edbc	326	#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)
AnnaBridge	171:3a7713b1edbc	327	/**
AnnaBridge	171:3a7713b1edbc	328	* @}
AnnaBridge	171:3a7713b1edbc	329	*/
AnnaBridge	171:3a7713b1edbc	330
AnnaBridge	171:3a7713b1edbc	331	/** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance
AnnaBridge	171:3a7713b1edbc	332	* @{
AnnaBridge	171:3a7713b1edbc	333	*/
AnnaBridge	171:3a7713b1edbc	334	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
AnnaBridge	171:3a7713b1edbc	335	/**
AnnaBridge	171:3a7713b1edbc	336	* @}
AnnaBridge	171:3a7713b1edbc	337	*/
AnnaBridge	171:3a7713b1edbc	338
AnnaBridge	171:3a7713b1edbc	339	/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance
AnnaBridge	171:3a7713b1edbc	340	* @{
AnnaBridge	171:3a7713b1edbc	341	*/
AnnaBridge	171:3a7713b1edbc	342	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
AnnaBridge	171:3a7713b1edbc	343	/**
AnnaBridge	171:3a7713b1edbc	344	* @}
AnnaBridge	171:3a7713b1edbc	345	*/
AnnaBridge	171:3a7713b1edbc	346
AnnaBridge	171:3a7713b1edbc	347	/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
AnnaBridge	171:3a7713b1edbc	348	* @{
AnnaBridge	171:3a7713b1edbc	349	*/
AnnaBridge	171:3a7713b1edbc	350	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
AnnaBridge	171:3a7713b1edbc	351	/**
AnnaBridge	171:3a7713b1edbc	352	* @}
AnnaBridge	171:3a7713b1edbc	353	*/
AnnaBridge	171:3a7713b1edbc	354
AnnaBridge	171:3a7713b1edbc	355	/** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance
AnnaBridge	171:3a7713b1edbc	356	* @{
AnnaBridge	171:3a7713b1edbc	357	*/
AnnaBridge	171:3a7713b1edbc	358	#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
AnnaBridge	171:3a7713b1edbc	359	/**
AnnaBridge	171:3a7713b1edbc	360	* @}
AnnaBridge	171:3a7713b1edbc	361	*/
AnnaBridge	171:3a7713b1edbc	362
AnnaBridge	171:3a7713b1edbc	363	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
AnnaBridge	171:3a7713b1edbc	364	((BANK) == FMC_SDRAM_BANK2))
AnnaBridge	171:3a7713b1edbc	365
AnnaBridge	171:3a7713b1edbc	366	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
AnnaBridge	171:3a7713b1edbc	367	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
AnnaBridge	171:3a7713b1edbc	368	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
AnnaBridge	171:3a7713b1edbc	369	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
AnnaBridge	171:3a7713b1edbc	370
AnnaBridge	171:3a7713b1edbc	371	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
AnnaBridge	171:3a7713b1edbc	372	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
AnnaBridge	171:3a7713b1edbc	373	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
AnnaBridge	171:3a7713b1edbc	374
AnnaBridge	171:3a7713b1edbc	375	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
AnnaBridge	171:3a7713b1edbc	376	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
AnnaBridge	171:3a7713b1edbc	377
AnnaBridge	171:3a7713b1edbc	378
AnnaBridge	171:3a7713b1edbc	379	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
AnnaBridge	171:3a7713b1edbc	380	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
AnnaBridge	171:3a7713b1edbc	381	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
AnnaBridge	171:3a7713b1edbc	382
AnnaBridge	171:3a7713b1edbc	383	#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) \|\| \
AnnaBridge	171:3a7713b1edbc	384	((__SIZE__) == FMC_PAGE_SIZE_128) \|\| \
AnnaBridge	171:3a7713b1edbc	385	((__SIZE__) == FMC_PAGE_SIZE_256) \|\| \
AnnaBridge	171:3a7713b1edbc	386	((__SIZE__) == FMC_PAGE_SIZE_512) \|\| \
AnnaBridge	171:3a7713b1edbc	387	((__SIZE__) == FMC_PAGE_SIZE_1024))
AnnaBridge	171:3a7713b1edbc	388
AnnaBridge	171:3a7713b1edbc	389	#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	390	((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
AnnaBridge	171:3a7713b1edbc	391	/**
AnnaBridge	171:3a7713b1edbc	392	* @}
AnnaBridge	171:3a7713b1edbc	393	*/
AnnaBridge	171:3a7713b1edbc	394
AnnaBridge	171:3a7713b1edbc	395	/* Exported typedef ----------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	396	/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types
AnnaBridge	171:3a7713b1edbc	397	* @{
AnnaBridge	171:3a7713b1edbc	398	*/
AnnaBridge	171:3a7713b1edbc	399	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
AnnaBridge	171:3a7713b1edbc	400	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
AnnaBridge	171:3a7713b1edbc	401	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
AnnaBridge	171:3a7713b1edbc	402	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
AnnaBridge	171:3a7713b1edbc	403
AnnaBridge	171:3a7713b1edbc	404	#define FMC_NORSRAM_DEVICE FMC_Bank1
AnnaBridge	171:3a7713b1edbc	405	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
AnnaBridge	171:3a7713b1edbc	406	#define FMC_NAND_DEVICE FMC_Bank3
AnnaBridge	171:3a7713b1edbc	407	#define FMC_SDRAM_DEVICE FMC_Bank5_6
AnnaBridge	171:3a7713b1edbc	408
AnnaBridge	171:3a7713b1edbc	409	/**
AnnaBridge	171:3a7713b1edbc	410	* @brief FMC NORSRAM Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	411	*/
AnnaBridge	171:3a7713b1edbc	412	typedef struct
AnnaBridge	171:3a7713b1edbc	413	{
AnnaBridge	171:3a7713b1edbc	414	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
AnnaBridge	171:3a7713b1edbc	415	This parameter can be a value of @ref FMC_NORSRAM_Bank */
AnnaBridge	171:3a7713b1edbc	416
AnnaBridge	171:3a7713b1edbc	417	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
AnnaBridge	171:3a7713b1edbc	418	multiplexed on the data bus or not.
AnnaBridge	171:3a7713b1edbc	419	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
AnnaBridge	171:3a7713b1edbc	420
AnnaBridge	171:3a7713b1edbc	421	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
AnnaBridge	171:3a7713b1edbc	422	the corresponding memory device.
AnnaBridge	171:3a7713b1edbc	423	This parameter can be a value of @ref FMC_Memory_Type */
AnnaBridge	171:3a7713b1edbc	424
AnnaBridge	171:3a7713b1edbc	425	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	171:3a7713b1edbc	426	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
AnnaBridge	171:3a7713b1edbc	427
AnnaBridge	171:3a7713b1edbc	428	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
AnnaBridge	171:3a7713b1edbc	429	valid only with synchronous burst Flash memories.
AnnaBridge	171:3a7713b1edbc	430	This parameter can be a value of @ref FMC_Burst_Access_Mode */
AnnaBridge	171:3a7713b1edbc	431
AnnaBridge	171:3a7713b1edbc	432	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
AnnaBridge	171:3a7713b1edbc	433	the Flash memory in burst mode.
AnnaBridge	171:3a7713b1edbc	434	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
AnnaBridge	171:3a7713b1edbc	435
AnnaBridge	171:3a7713b1edbc	436	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
AnnaBridge	171:3a7713b1edbc	437	clock cycle before the wait state or during the wait state,
AnnaBridge	171:3a7713b1edbc	438	valid only when accessing memories in burst mode.
AnnaBridge	171:3a7713b1edbc	439	This parameter can be a value of @ref FMC_Wait_Timing */
AnnaBridge	171:3a7713b1edbc	440
AnnaBridge	171:3a7713b1edbc	441	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
AnnaBridge	171:3a7713b1edbc	442	This parameter can be a value of @ref FMC_Write_Operation */
AnnaBridge	171:3a7713b1edbc	443
AnnaBridge	171:3a7713b1edbc	444	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
AnnaBridge	171:3a7713b1edbc	445	signal, valid for Flash memory access in burst mode.
AnnaBridge	171:3a7713b1edbc	446	This parameter can be a value of @ref FMC_Wait_Signal */
AnnaBridge	171:3a7713b1edbc	447
AnnaBridge	171:3a7713b1edbc	448	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
AnnaBridge	171:3a7713b1edbc	449	This parameter can be a value of @ref FMC_Extended_Mode */
AnnaBridge	171:3a7713b1edbc	450
AnnaBridge	171:3a7713b1edbc	451	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
AnnaBridge	171:3a7713b1edbc	452	valid only with asynchronous Flash memories.
AnnaBridge	171:3a7713b1edbc	453	This parameter can be a value of @ref FMC_AsynchronousWait */
AnnaBridge	171:3a7713b1edbc	454
AnnaBridge	171:3a7713b1edbc	455	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
AnnaBridge	171:3a7713b1edbc	456	This parameter can be a value of @ref FMC_Write_Burst */
AnnaBridge	171:3a7713b1edbc	457
AnnaBridge	171:3a7713b1edbc	458	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
AnnaBridge	171:3a7713b1edbc	459	This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge	171:3a7713b1edbc	460	through FMC_BCR2..4 registers.
AnnaBridge	171:3a7713b1edbc	461	This parameter can be a value of @ref FMC_Continous_Clock */
AnnaBridge	171:3a7713b1edbc	462
AnnaBridge	171:3a7713b1edbc	463	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
AnnaBridge	171:3a7713b1edbc	464	This parameter is only enabled through the FMC_BCR1 register, and don't care
AnnaBridge	171:3a7713b1edbc	465	through FMC_BCR2..4 registers.
AnnaBridge	171:3a7713b1edbc	466	This parameter can be a value of @ref FMC_Write_FIFO */
AnnaBridge	171:3a7713b1edbc	467
AnnaBridge	171:3a7713b1edbc	468	uint32_t PageSize; /*!< Specifies the memory page size.
AnnaBridge	171:3a7713b1edbc	469	This parameter can be a value of @ref FMC_Page_Size */
AnnaBridge	171:3a7713b1edbc	470
AnnaBridge	171:3a7713b1edbc	471	}FMC_NORSRAM_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	472
AnnaBridge	171:3a7713b1edbc	473	/**
AnnaBridge	171:3a7713b1edbc	474	* @brief FMC NORSRAM Timing parameters structure definition
AnnaBridge	171:3a7713b1edbc	475	*/
AnnaBridge	171:3a7713b1edbc	476	typedef struct
AnnaBridge	171:3a7713b1edbc	477	{
AnnaBridge	171:3a7713b1edbc	478	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	171:3a7713b1edbc	479	the duration of the address setup time.
AnnaBridge	171:3a7713b1edbc	480	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	171:3a7713b1edbc	481	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	171:3a7713b1edbc	482
AnnaBridge	171:3a7713b1edbc	483	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	171:3a7713b1edbc	484	the duration of the address hold time.
AnnaBridge	171:3a7713b1edbc	485	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
AnnaBridge	171:3a7713b1edbc	486	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	171:3a7713b1edbc	487
AnnaBridge	171:3a7713b1edbc	488	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	171:3a7713b1edbc	489	the duration of the data setup time.
AnnaBridge	171:3a7713b1edbc	490	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
AnnaBridge	171:3a7713b1edbc	491	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
AnnaBridge	171:3a7713b1edbc	492	NOR Flash memories. */
AnnaBridge	171:3a7713b1edbc	493
AnnaBridge	171:3a7713b1edbc	494	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	171:3a7713b1edbc	495	the duration of the bus turnaround.
AnnaBridge	171:3a7713b1edbc	496	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	171:3a7713b1edbc	497	@note This parameter is only used for multiplexed NOR Flash memories. */
AnnaBridge	171:3a7713b1edbc	498
AnnaBridge	171:3a7713b1edbc	499	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
AnnaBridge	171:3a7713b1edbc	500	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
AnnaBridge	171:3a7713b1edbc	501	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
AnnaBridge	171:3a7713b1edbc	502	accesses. */
AnnaBridge	171:3a7713b1edbc	503
AnnaBridge	171:3a7713b1edbc	504	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
AnnaBridge	171:3a7713b1edbc	505	to the memory before getting the first data.
AnnaBridge	171:3a7713b1edbc	506	The parameter value depends on the memory type as shown below:
AnnaBridge	171:3a7713b1edbc	507	- It must be set to 0 in case of a CRAM
AnnaBridge	171:3a7713b1edbc	508	- It is don't care in asynchronous NOR, SRAM or ROM accesses
AnnaBridge	171:3a7713b1edbc	509	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
AnnaBridge	171:3a7713b1edbc	510	with synchronous burst mode enable */
AnnaBridge	171:3a7713b1edbc	511
AnnaBridge	171:3a7713b1edbc	512	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
AnnaBridge	171:3a7713b1edbc	513	This parameter can be a value of @ref FMC_Access_Mode */
AnnaBridge	171:3a7713b1edbc	514	}FMC_NORSRAM_TimingTypeDef;
AnnaBridge	171:3a7713b1edbc	515
AnnaBridge	171:3a7713b1edbc	516	/**
AnnaBridge	171:3a7713b1edbc	517	* @brief FMC NAND Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	518	*/
AnnaBridge	171:3a7713b1edbc	519	typedef struct
AnnaBridge	171:3a7713b1edbc	520	{
AnnaBridge	171:3a7713b1edbc	521	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
AnnaBridge	171:3a7713b1edbc	522	This parameter can be a value of @ref FMC_NAND_Bank */
AnnaBridge	171:3a7713b1edbc	523
AnnaBridge	171:3a7713b1edbc	524	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
AnnaBridge	171:3a7713b1edbc	525	This parameter can be any value of @ref FMC_Wait_feature */
AnnaBridge	171:3a7713b1edbc	526
AnnaBridge	171:3a7713b1edbc	527	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	171:3a7713b1edbc	528	This parameter can be any value of @ref FMC_NAND_Data_Width */
AnnaBridge	171:3a7713b1edbc	529
AnnaBridge	171:3a7713b1edbc	530	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
AnnaBridge	171:3a7713b1edbc	531	This parameter can be any value of @ref FMC_ECC */
AnnaBridge	171:3a7713b1edbc	532
AnnaBridge	171:3a7713b1edbc	533	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
AnnaBridge	171:3a7713b1edbc	534	This parameter can be any value of @ref FMC_ECC_Page_Size */
AnnaBridge	171:3a7713b1edbc	535
AnnaBridge	171:3a7713b1edbc	536	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	171:3a7713b1edbc	537	delay between CLE low and RE low.
AnnaBridge	171:3a7713b1edbc	538	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	539
AnnaBridge	171:3a7713b1edbc	540	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	171:3a7713b1edbc	541	delay between ALE low and RE low.
AnnaBridge	171:3a7713b1edbc	542	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	543	}FMC_NAND_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	544
AnnaBridge	171:3a7713b1edbc	545	/**
AnnaBridge	171:3a7713b1edbc	546	* @brief FMC NAND Timing parameters structure definition
AnnaBridge	171:3a7713b1edbc	547	*/
AnnaBridge	171:3a7713b1edbc	548	typedef struct
AnnaBridge	171:3a7713b1edbc	549	{
AnnaBridge	171:3a7713b1edbc	550	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
AnnaBridge	171:3a7713b1edbc	551	the command assertion for NAND-Flash read or write access
AnnaBridge	171:3a7713b1edbc	552	to common/Attribute or I/O memory space (depending on
AnnaBridge	171:3a7713b1edbc	553	the memory space timing to be configured).
AnnaBridge	171:3a7713b1edbc	554	This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
AnnaBridge	171:3a7713b1edbc	555
AnnaBridge	171:3a7713b1edbc	556	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
AnnaBridge	171:3a7713b1edbc	557	command for NAND-Flash read or write access to
AnnaBridge	171:3a7713b1edbc	558	common/Attribute or I/O memory space (depending on the
AnnaBridge	171:3a7713b1edbc	559	memory space timing to be configured).
AnnaBridge	171:3a7713b1edbc	560	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
AnnaBridge	171:3a7713b1edbc	561
AnnaBridge	171:3a7713b1edbc	562	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
AnnaBridge	171:3a7713b1edbc	563	(and data for write access) after the command de-assertion
AnnaBridge	171:3a7713b1edbc	564	for NAND-Flash read or write access to common/Attribute
AnnaBridge	171:3a7713b1edbc	565	or I/O memory space (depending on the memory space timing
AnnaBridge	171:3a7713b1edbc	566	to be configured).
AnnaBridge	171:3a7713b1edbc	567	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
AnnaBridge	171:3a7713b1edbc	568
AnnaBridge	171:3a7713b1edbc	569	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
AnnaBridge	171:3a7713b1edbc	570	data bus is kept in HiZ after the start of a NAND-Flash
AnnaBridge	171:3a7713b1edbc	571	write access to common/Attribute or I/O memory space (depending
AnnaBridge	171:3a7713b1edbc	572	on the memory space timing to be configured).
AnnaBridge	171:3a7713b1edbc	573	This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
AnnaBridge	171:3a7713b1edbc	574	}FMC_NAND_PCC_TimingTypeDef;
AnnaBridge	171:3a7713b1edbc	575
AnnaBridge	171:3a7713b1edbc	576	/**
AnnaBridge	171:3a7713b1edbc	577	* @brief FMC SDRAM Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	578	*/
AnnaBridge	171:3a7713b1edbc	579	typedef struct
AnnaBridge	171:3a7713b1edbc	580	{
AnnaBridge	171:3a7713b1edbc	581	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
AnnaBridge	171:3a7713b1edbc	582	This parameter can be a value of @ref FMC_SDRAM_Bank */
AnnaBridge	171:3a7713b1edbc	583
AnnaBridge	171:3a7713b1edbc	584	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
AnnaBridge	171:3a7713b1edbc	585	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
AnnaBridge	171:3a7713b1edbc	586
AnnaBridge	171:3a7713b1edbc	587	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
AnnaBridge	171:3a7713b1edbc	588	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
AnnaBridge	171:3a7713b1edbc	589
AnnaBridge	171:3a7713b1edbc	590	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
AnnaBridge	171:3a7713b1edbc	591	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
AnnaBridge	171:3a7713b1edbc	592
AnnaBridge	171:3a7713b1edbc	593	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
AnnaBridge	171:3a7713b1edbc	594	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
AnnaBridge	171:3a7713b1edbc	595
AnnaBridge	171:3a7713b1edbc	596	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
AnnaBridge	171:3a7713b1edbc	597	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
AnnaBridge	171:3a7713b1edbc	598
AnnaBridge	171:3a7713b1edbc	599	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
AnnaBridge	171:3a7713b1edbc	600	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
AnnaBridge	171:3a7713b1edbc	601
AnnaBridge	171:3a7713b1edbc	602	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
AnnaBridge	171:3a7713b1edbc	603	to disable the clock before changing frequency.
AnnaBridge	171:3a7713b1edbc	604	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
AnnaBridge	171:3a7713b1edbc	605
AnnaBridge	171:3a7713b1edbc	606	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
AnnaBridge	171:3a7713b1edbc	607	commands during the CAS latency and stores data in the Read FIFO.
AnnaBridge	171:3a7713b1edbc	608	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
AnnaBridge	171:3a7713b1edbc	609
AnnaBridge	171:3a7713b1edbc	610	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
AnnaBridge	171:3a7713b1edbc	611	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
AnnaBridge	171:3a7713b1edbc	612	}FMC_SDRAM_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	613
AnnaBridge	171:3a7713b1edbc	614	/**
AnnaBridge	171:3a7713b1edbc	615	* @brief FMC SDRAM Timing parameters structure definition
AnnaBridge	171:3a7713b1edbc	616	*/
AnnaBridge	171:3a7713b1edbc	617	typedef struct
AnnaBridge	171:3a7713b1edbc	618	{
AnnaBridge	171:3a7713b1edbc	619	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
AnnaBridge	171:3a7713b1edbc	620	an active or Refresh command in number of memory clock cycles.
AnnaBridge	171:3a7713b1edbc	621	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	171:3a7713b1edbc	622
AnnaBridge	171:3a7713b1edbc	623	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
AnnaBridge	171:3a7713b1edbc	624	issuing the Activate command in number of memory clock cycles.
AnnaBridge	171:3a7713b1edbc	625	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	171:3a7713b1edbc	626
AnnaBridge	171:3a7713b1edbc	627	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
AnnaBridge	171:3a7713b1edbc	628	cycles.
AnnaBridge	171:3a7713b1edbc	629	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	171:3a7713b1edbc	630
AnnaBridge	171:3a7713b1edbc	631	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
AnnaBridge	171:3a7713b1edbc	632	and the delay between two consecutive Refresh commands in number of
AnnaBridge	171:3a7713b1edbc	633	memory clock cycles.
AnnaBridge	171:3a7713b1edbc	634	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	171:3a7713b1edbc	635
AnnaBridge	171:3a7713b1edbc	636	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
AnnaBridge	171:3a7713b1edbc	637	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	171:3a7713b1edbc	638
AnnaBridge	171:3a7713b1edbc	639	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
AnnaBridge	171:3a7713b1edbc	640	in number of memory clock cycles.
AnnaBridge	171:3a7713b1edbc	641	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	171:3a7713b1edbc	642
AnnaBridge	171:3a7713b1edbc	643	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
AnnaBridge	171:3a7713b1edbc	644	command in number of memory clock cycles.
AnnaBridge	171:3a7713b1edbc	645	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	171:3a7713b1edbc	646	}FMC_SDRAM_TimingTypeDef;
AnnaBridge	171:3a7713b1edbc	647
AnnaBridge	171:3a7713b1edbc	648	/**
AnnaBridge	171:3a7713b1edbc	649	* @brief SDRAM command parameters structure definition
AnnaBridge	171:3a7713b1edbc	650	*/
AnnaBridge	171:3a7713b1edbc	651	typedef struct
AnnaBridge	171:3a7713b1edbc	652	{
AnnaBridge	171:3a7713b1edbc	653	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
AnnaBridge	171:3a7713b1edbc	654	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
AnnaBridge	171:3a7713b1edbc	655
AnnaBridge	171:3a7713b1edbc	656	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
AnnaBridge	171:3a7713b1edbc	657	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
AnnaBridge	171:3a7713b1edbc	658
AnnaBridge	171:3a7713b1edbc	659	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
AnnaBridge	171:3a7713b1edbc	660	in auto refresh mode.
AnnaBridge	171:3a7713b1edbc	661	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
AnnaBridge	171:3a7713b1edbc	662	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
AnnaBridge	171:3a7713b1edbc	663	}FMC_SDRAM_CommandTypeDef;
AnnaBridge	171:3a7713b1edbc	664	/**
AnnaBridge	171:3a7713b1edbc	665	* @}
AnnaBridge	171:3a7713b1edbc	666	*/
AnnaBridge	171:3a7713b1edbc	667
AnnaBridge	171:3a7713b1edbc	668	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	669	/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
AnnaBridge	171:3a7713b1edbc	670	* @{
AnnaBridge	171:3a7713b1edbc	671	*/
AnnaBridge	171:3a7713b1edbc	672
AnnaBridge	171:3a7713b1edbc	673	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
AnnaBridge	171:3a7713b1edbc	674	* @{
AnnaBridge	171:3a7713b1edbc	675	*/
AnnaBridge	171:3a7713b1edbc	676
AnnaBridge	171:3a7713b1edbc	677	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
AnnaBridge	171:3a7713b1edbc	678	* @{
AnnaBridge	171:3a7713b1edbc	679	*/
AnnaBridge	171:3a7713b1edbc	680	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	681	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
AnnaBridge	171:3a7713b1edbc	682	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
AnnaBridge	171:3a7713b1edbc	683	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
AnnaBridge	171:3a7713b1edbc	684	/**
AnnaBridge	171:3a7713b1edbc	685	* @}
AnnaBridge	171:3a7713b1edbc	686	*/
AnnaBridge	171:3a7713b1edbc	687
AnnaBridge	171:3a7713b1edbc	688	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
AnnaBridge	171:3a7713b1edbc	689	* @{
AnnaBridge	171:3a7713b1edbc	690	*/
AnnaBridge	171:3a7713b1edbc	691	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	692	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
AnnaBridge	171:3a7713b1edbc	693	/**
AnnaBridge	171:3a7713b1edbc	694	* @}
AnnaBridge	171:3a7713b1edbc	695	*/
AnnaBridge	171:3a7713b1edbc	696
AnnaBridge	171:3a7713b1edbc	697	/** @defgroup FMC_Memory_Type FMC Memory Type
AnnaBridge	171:3a7713b1edbc	698	* @{
AnnaBridge	171:3a7713b1edbc	699	*/
AnnaBridge	171:3a7713b1edbc	700	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	701	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
AnnaBridge	171:3a7713b1edbc	702	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
AnnaBridge	171:3a7713b1edbc	703	/**
AnnaBridge	171:3a7713b1edbc	704	* @}
AnnaBridge	171:3a7713b1edbc	705	*/
AnnaBridge	171:3a7713b1edbc	706
AnnaBridge	171:3a7713b1edbc	707	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
AnnaBridge	171:3a7713b1edbc	708	* @{
AnnaBridge	171:3a7713b1edbc	709	*/
AnnaBridge	171:3a7713b1edbc	710	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	711	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
AnnaBridge	171:3a7713b1edbc	712	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
AnnaBridge	171:3a7713b1edbc	713	/**
AnnaBridge	171:3a7713b1edbc	714	* @}
AnnaBridge	171:3a7713b1edbc	715	*/
AnnaBridge	171:3a7713b1edbc	716
AnnaBridge	171:3a7713b1edbc	717	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
AnnaBridge	171:3a7713b1edbc	718	* @{
AnnaBridge	171:3a7713b1edbc	719	*/
AnnaBridge	171:3a7713b1edbc	720	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
AnnaBridge	171:3a7713b1edbc	721	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	722	/**
AnnaBridge	171:3a7713b1edbc	723	* @}
AnnaBridge	171:3a7713b1edbc	724	*/
AnnaBridge	171:3a7713b1edbc	725
AnnaBridge	171:3a7713b1edbc	726	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
AnnaBridge	171:3a7713b1edbc	727	* @{
AnnaBridge	171:3a7713b1edbc	728	*/
AnnaBridge	171:3a7713b1edbc	729	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	730	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
AnnaBridge	171:3a7713b1edbc	731	/**
AnnaBridge	171:3a7713b1edbc	732	* @}
AnnaBridge	171:3a7713b1edbc	733	*/
AnnaBridge	171:3a7713b1edbc	734
AnnaBridge	171:3a7713b1edbc	735	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
AnnaBridge	171:3a7713b1edbc	736	* @{
AnnaBridge	171:3a7713b1edbc	737	*/
AnnaBridge	171:3a7713b1edbc	738	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	739	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
AnnaBridge	171:3a7713b1edbc	740	/**
AnnaBridge	171:3a7713b1edbc	741	* @}
AnnaBridge	171:3a7713b1edbc	742	*/
AnnaBridge	171:3a7713b1edbc	743
AnnaBridge	171:3a7713b1edbc	744	/** @defgroup FMC_Wait_Timing FMC Wait Timing
AnnaBridge	171:3a7713b1edbc	745	* @{
AnnaBridge	171:3a7713b1edbc	746	*/
AnnaBridge	171:3a7713b1edbc	747	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	748	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
AnnaBridge	171:3a7713b1edbc	749	/**
AnnaBridge	171:3a7713b1edbc	750	* @}
AnnaBridge	171:3a7713b1edbc	751	*/
AnnaBridge	171:3a7713b1edbc	752
AnnaBridge	171:3a7713b1edbc	753	/** @defgroup FMC_Write_Operation FMC Write Operation
AnnaBridge	171:3a7713b1edbc	754	* @{
AnnaBridge	171:3a7713b1edbc	755	*/
AnnaBridge	171:3a7713b1edbc	756	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	757	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
AnnaBridge	171:3a7713b1edbc	758	/**
AnnaBridge	171:3a7713b1edbc	759	* @}
AnnaBridge	171:3a7713b1edbc	760	*/
AnnaBridge	171:3a7713b1edbc	761
AnnaBridge	171:3a7713b1edbc	762	/** @defgroup FMC_Wait_Signal FMC Wait Signal
AnnaBridge	171:3a7713b1edbc	763	* @{
AnnaBridge	171:3a7713b1edbc	764	*/
AnnaBridge	171:3a7713b1edbc	765	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	766	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
AnnaBridge	171:3a7713b1edbc	767	/**
AnnaBridge	171:3a7713b1edbc	768	* @}
AnnaBridge	171:3a7713b1edbc	769	*/
AnnaBridge	171:3a7713b1edbc	770
AnnaBridge	171:3a7713b1edbc	771	/** @defgroup FMC_Extended_Mode FMC Extended Mode
AnnaBridge	171:3a7713b1edbc	772	* @{
AnnaBridge	171:3a7713b1edbc	773	*/
AnnaBridge	171:3a7713b1edbc	774	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	775	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
AnnaBridge	171:3a7713b1edbc	776	/**
AnnaBridge	171:3a7713b1edbc	777	* @}
AnnaBridge	171:3a7713b1edbc	778	*/
AnnaBridge	171:3a7713b1edbc	779
AnnaBridge	171:3a7713b1edbc	780	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
AnnaBridge	171:3a7713b1edbc	781	* @{
AnnaBridge	171:3a7713b1edbc	782	*/
AnnaBridge	171:3a7713b1edbc	783	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	784	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
AnnaBridge	171:3a7713b1edbc	785	/**
AnnaBridge	171:3a7713b1edbc	786	* @}
AnnaBridge	171:3a7713b1edbc	787	*/
AnnaBridge	171:3a7713b1edbc	788
AnnaBridge	171:3a7713b1edbc	789	/** @defgroup FMC_Page_Size FMC Page Size
AnnaBridge	171:3a7713b1edbc	790	* @{
AnnaBridge	171:3a7713b1edbc	791	*/
AnnaBridge	171:3a7713b1edbc	792	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	793	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
AnnaBridge	171:3a7713b1edbc	794	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
AnnaBridge	171:3a7713b1edbc	795	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 \| FMC_BCR1_CPSIZE_1))
AnnaBridge	171:3a7713b1edbc	796	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
AnnaBridge	171:3a7713b1edbc	797	/**
AnnaBridge	171:3a7713b1edbc	798	* @}
AnnaBridge	171:3a7713b1edbc	799	*/
AnnaBridge	171:3a7713b1edbc	800
AnnaBridge	171:3a7713b1edbc	801	/** @defgroup FMC_Write_Burst FMC Write Burst
AnnaBridge	171:3a7713b1edbc	802	* @{
AnnaBridge	171:3a7713b1edbc	803	*/
AnnaBridge	171:3a7713b1edbc	804	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	805	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
AnnaBridge	171:3a7713b1edbc	806	/**
AnnaBridge	171:3a7713b1edbc	807	* @}
AnnaBridge	171:3a7713b1edbc	808	*/
AnnaBridge	171:3a7713b1edbc	809
AnnaBridge	171:3a7713b1edbc	810	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
AnnaBridge	171:3a7713b1edbc	811	* @{
AnnaBridge	171:3a7713b1edbc	812	*/
AnnaBridge	171:3a7713b1edbc	813	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	814	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
AnnaBridge	171:3a7713b1edbc	815	/**
AnnaBridge	171:3a7713b1edbc	816	* @}
AnnaBridge	171:3a7713b1edbc	817	*/
AnnaBridge	171:3a7713b1edbc	818
AnnaBridge	171:3a7713b1edbc	819	/** @defgroup FMC_Write_FIFO FMC Write FIFO
AnnaBridge	171:3a7713b1edbc	820	* @{
AnnaBridge	171:3a7713b1edbc	821	*/
AnnaBridge	171:3a7713b1edbc	822	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
AnnaBridge	171:3a7713b1edbc	823	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	824	/**
AnnaBridge	171:3a7713b1edbc	825	* @}
AnnaBridge	171:3a7713b1edbc	826	*/
AnnaBridge	171:3a7713b1edbc	827
AnnaBridge	171:3a7713b1edbc	828	/** @defgroup FMC_Access_Mode FMC Access Mode
AnnaBridge	171:3a7713b1edbc	829	* @{
AnnaBridge	171:3a7713b1edbc	830	*/
AnnaBridge	171:3a7713b1edbc	831	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	832	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
AnnaBridge	171:3a7713b1edbc	833	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
AnnaBridge	171:3a7713b1edbc	834	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
AnnaBridge	171:3a7713b1edbc	835	/**
AnnaBridge	171:3a7713b1edbc	836	* @}
AnnaBridge	171:3a7713b1edbc	837	*/
AnnaBridge	171:3a7713b1edbc	838
AnnaBridge	171:3a7713b1edbc	839	/**
AnnaBridge	171:3a7713b1edbc	840	* @}
AnnaBridge	171:3a7713b1edbc	841	*/
AnnaBridge	171:3a7713b1edbc	842
AnnaBridge	171:3a7713b1edbc	843	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
AnnaBridge	171:3a7713b1edbc	844	* @{
AnnaBridge	171:3a7713b1edbc	845	*/
AnnaBridge	171:3a7713b1edbc	846	/** @defgroup FMC_NAND_Bank FMC NAND Bank
AnnaBridge	171:3a7713b1edbc	847	* @{
AnnaBridge	171:3a7713b1edbc	848	*/
AnnaBridge	171:3a7713b1edbc	849	#define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
AnnaBridge	171:3a7713b1edbc	850	/**
AnnaBridge	171:3a7713b1edbc	851	* @}
AnnaBridge	171:3a7713b1edbc	852	*/
AnnaBridge	171:3a7713b1edbc	853
AnnaBridge	171:3a7713b1edbc	854	/** @defgroup FMC_Wait_feature FMC Wait feature
AnnaBridge	171:3a7713b1edbc	855	* @{
AnnaBridge	171:3a7713b1edbc	856	*/
AnnaBridge	171:3a7713b1edbc	857	#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	858	#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
AnnaBridge	171:3a7713b1edbc	859	/**
AnnaBridge	171:3a7713b1edbc	860	* @}
AnnaBridge	171:3a7713b1edbc	861	*/
AnnaBridge	171:3a7713b1edbc	862
AnnaBridge	171:3a7713b1edbc	863	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
AnnaBridge	171:3a7713b1edbc	864	* @{
AnnaBridge	171:3a7713b1edbc	865	*/
AnnaBridge	171:3a7713b1edbc	866	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
AnnaBridge	171:3a7713b1edbc	867	/**
AnnaBridge	171:3a7713b1edbc	868	* @}
AnnaBridge	171:3a7713b1edbc	869	*/
AnnaBridge	171:3a7713b1edbc	870
AnnaBridge	171:3a7713b1edbc	871	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
AnnaBridge	171:3a7713b1edbc	872	* @{
AnnaBridge	171:3a7713b1edbc	873	*/
AnnaBridge	171:3a7713b1edbc	874	#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	875	#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
AnnaBridge	171:3a7713b1edbc	876	/**
AnnaBridge	171:3a7713b1edbc	877	* @}
AnnaBridge	171:3a7713b1edbc	878	*/
AnnaBridge	171:3a7713b1edbc	879
AnnaBridge	171:3a7713b1edbc	880	/** @defgroup FMC_ECC FMC ECC
AnnaBridge	171:3a7713b1edbc	881	* @{
AnnaBridge	171:3a7713b1edbc	882	*/
AnnaBridge	171:3a7713b1edbc	883	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	884	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
AnnaBridge	171:3a7713b1edbc	885	/**
AnnaBridge	171:3a7713b1edbc	886	* @}
AnnaBridge	171:3a7713b1edbc	887	*/
AnnaBridge	171:3a7713b1edbc	888
AnnaBridge	171:3a7713b1edbc	889	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
AnnaBridge	171:3a7713b1edbc	890	* @{
AnnaBridge	171:3a7713b1edbc	891	*/
AnnaBridge	171:3a7713b1edbc	892	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	893	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
AnnaBridge	171:3a7713b1edbc	894	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
AnnaBridge	171:3a7713b1edbc	895	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
AnnaBridge	171:3a7713b1edbc	896	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
AnnaBridge	171:3a7713b1edbc	897	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
AnnaBridge	171:3a7713b1edbc	898	/**
AnnaBridge	171:3a7713b1edbc	899	* @}
AnnaBridge	171:3a7713b1edbc	900	*/
AnnaBridge	171:3a7713b1edbc	901
AnnaBridge	171:3a7713b1edbc	902	/**
AnnaBridge	171:3a7713b1edbc	903	* @}
AnnaBridge	171:3a7713b1edbc	904	*/
AnnaBridge	171:3a7713b1edbc	905
AnnaBridge	171:3a7713b1edbc	906	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
AnnaBridge	171:3a7713b1edbc	907	* @{
AnnaBridge	171:3a7713b1edbc	908	*/
AnnaBridge	171:3a7713b1edbc	909	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
AnnaBridge	171:3a7713b1edbc	910	* @{
AnnaBridge	171:3a7713b1edbc	911	*/
AnnaBridge	171:3a7713b1edbc	912	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	913	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
AnnaBridge	171:3a7713b1edbc	914	/**
AnnaBridge	171:3a7713b1edbc	915	* @}
AnnaBridge	171:3a7713b1edbc	916	*/
AnnaBridge	171:3a7713b1edbc	917
AnnaBridge	171:3a7713b1edbc	918	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
AnnaBridge	171:3a7713b1edbc	919	* @{
AnnaBridge	171:3a7713b1edbc	920	*/
AnnaBridge	171:3a7713b1edbc	921	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	922	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
AnnaBridge	171:3a7713b1edbc	923	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
AnnaBridge	171:3a7713b1edbc	924	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
AnnaBridge	171:3a7713b1edbc	925	/**
AnnaBridge	171:3a7713b1edbc	926	* @}
AnnaBridge	171:3a7713b1edbc	927	*/
AnnaBridge	171:3a7713b1edbc	928
AnnaBridge	171:3a7713b1edbc	929	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
AnnaBridge	171:3a7713b1edbc	930	* @{
AnnaBridge	171:3a7713b1edbc	931	*/
AnnaBridge	171:3a7713b1edbc	932	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	933	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
AnnaBridge	171:3a7713b1edbc	934	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
AnnaBridge	171:3a7713b1edbc	935	/**
AnnaBridge	171:3a7713b1edbc	936	* @}
AnnaBridge	171:3a7713b1edbc	937	*/
AnnaBridge	171:3a7713b1edbc	938
AnnaBridge	171:3a7713b1edbc	939	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
AnnaBridge	171:3a7713b1edbc	940	* @{
AnnaBridge	171:3a7713b1edbc	941	*/
AnnaBridge	171:3a7713b1edbc	942	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	943	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
AnnaBridge	171:3a7713b1edbc	944	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
AnnaBridge	171:3a7713b1edbc	945	/**
AnnaBridge	171:3a7713b1edbc	946	* @}
AnnaBridge	171:3a7713b1edbc	947	*/
AnnaBridge	171:3a7713b1edbc	948
AnnaBridge	171:3a7713b1edbc	949	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
AnnaBridge	171:3a7713b1edbc	950	* @{
AnnaBridge	171:3a7713b1edbc	951	*/
AnnaBridge	171:3a7713b1edbc	952	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	953	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
AnnaBridge	171:3a7713b1edbc	954	/**
AnnaBridge	171:3a7713b1edbc	955	* @}
AnnaBridge	171:3a7713b1edbc	956	*/
AnnaBridge	171:3a7713b1edbc	957
AnnaBridge	171:3a7713b1edbc	958	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
AnnaBridge	171:3a7713b1edbc	959	* @{
AnnaBridge	171:3a7713b1edbc	960	*/
AnnaBridge	171:3a7713b1edbc	961	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
AnnaBridge	171:3a7713b1edbc	962	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
AnnaBridge	171:3a7713b1edbc	963	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
AnnaBridge	171:3a7713b1edbc	964	/**
AnnaBridge	171:3a7713b1edbc	965	* @}
AnnaBridge	171:3a7713b1edbc	966	*/
AnnaBridge	171:3a7713b1edbc	967
AnnaBridge	171:3a7713b1edbc	968	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
AnnaBridge	171:3a7713b1edbc	969	* @{
AnnaBridge	171:3a7713b1edbc	970	*/
AnnaBridge	171:3a7713b1edbc	971	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	972	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
AnnaBridge	171:3a7713b1edbc	973	/**
AnnaBridge	171:3a7713b1edbc	974	* @}
AnnaBridge	171:3a7713b1edbc	975	*/
AnnaBridge	171:3a7713b1edbc	976
AnnaBridge	171:3a7713b1edbc	977	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
AnnaBridge	171:3a7713b1edbc	978	* @{
AnnaBridge	171:3a7713b1edbc	979	*/
AnnaBridge	171:3a7713b1edbc	980	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	981	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
AnnaBridge	171:3a7713b1edbc	982	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
AnnaBridge	171:3a7713b1edbc	983	/**
AnnaBridge	171:3a7713b1edbc	984	* @}
AnnaBridge	171:3a7713b1edbc	985	*/
AnnaBridge	171:3a7713b1edbc	986
AnnaBridge	171:3a7713b1edbc	987	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
AnnaBridge	171:3a7713b1edbc	988	* @{
AnnaBridge	171:3a7713b1edbc	989	*/
AnnaBridge	171:3a7713b1edbc	990	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	991	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
AnnaBridge	171:3a7713b1edbc	992	/**
AnnaBridge	171:3a7713b1edbc	993	* @}
AnnaBridge	171:3a7713b1edbc	994	*/
AnnaBridge	171:3a7713b1edbc	995
AnnaBridge	171:3a7713b1edbc	996	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
AnnaBridge	171:3a7713b1edbc	997	* @{
AnnaBridge	171:3a7713b1edbc	998	*/
AnnaBridge	171:3a7713b1edbc	999	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	1000	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
AnnaBridge	171:3a7713b1edbc	1001	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
AnnaBridge	171:3a7713b1edbc	1002	/**
AnnaBridge	171:3a7713b1edbc	1003	* @}
AnnaBridge	171:3a7713b1edbc	1004	*/
AnnaBridge	171:3a7713b1edbc	1005
AnnaBridge	171:3a7713b1edbc	1006	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
AnnaBridge	171:3a7713b1edbc	1007	* @{
AnnaBridge	171:3a7713b1edbc	1008	*/
AnnaBridge	171:3a7713b1edbc	1009	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	1010	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
AnnaBridge	171:3a7713b1edbc	1011	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
AnnaBridge	171:3a7713b1edbc	1012	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
AnnaBridge	171:3a7713b1edbc	1013	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
AnnaBridge	171:3a7713b1edbc	1014	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
AnnaBridge	171:3a7713b1edbc	1015	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
AnnaBridge	171:3a7713b1edbc	1016	/**
AnnaBridge	171:3a7713b1edbc	1017	* @}
AnnaBridge	171:3a7713b1edbc	1018	*/
AnnaBridge	171:3a7713b1edbc	1019
AnnaBridge	171:3a7713b1edbc	1020	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
AnnaBridge	171:3a7713b1edbc	1021	* @{
AnnaBridge	171:3a7713b1edbc	1022	*/
AnnaBridge	171:3a7713b1edbc	1023	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
AnnaBridge	171:3a7713b1edbc	1024	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
AnnaBridge	171:3a7713b1edbc	1025	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
AnnaBridge	171:3a7713b1edbc	1026	/**
AnnaBridge	171:3a7713b1edbc	1027	* @}
AnnaBridge	171:3a7713b1edbc	1028	*/
AnnaBridge	171:3a7713b1edbc	1029
AnnaBridge	171:3a7713b1edbc	1030	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
AnnaBridge	171:3a7713b1edbc	1031	* @{
AnnaBridge	171:3a7713b1edbc	1032	*/
AnnaBridge	171:3a7713b1edbc	1033	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
AnnaBridge	171:3a7713b1edbc	1034	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
AnnaBridge	171:3a7713b1edbc	1035	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
AnnaBridge	171:3a7713b1edbc	1036	/**
AnnaBridge	171:3a7713b1edbc	1037	* @}
AnnaBridge	171:3a7713b1edbc	1038	*/
AnnaBridge	171:3a7713b1edbc	1039
AnnaBridge	171:3a7713b1edbc	1040	/**
AnnaBridge	171:3a7713b1edbc	1041	* @}
AnnaBridge	171:3a7713b1edbc	1042	*/
AnnaBridge	171:3a7713b1edbc	1043
AnnaBridge	171:3a7713b1edbc	1044	/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
AnnaBridge	171:3a7713b1edbc	1045	* @{
AnnaBridge	171:3a7713b1edbc	1046	*/
AnnaBridge	171:3a7713b1edbc	1047	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
AnnaBridge	171:3a7713b1edbc	1048	#define FMC_IT_LEVEL ((uint32_t)0x00000010U)
AnnaBridge	171:3a7713b1edbc	1049	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
AnnaBridge	171:3a7713b1edbc	1050	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
AnnaBridge	171:3a7713b1edbc	1051	/**
AnnaBridge	171:3a7713b1edbc	1052	* @}
AnnaBridge	171:3a7713b1edbc	1053	*/
AnnaBridge	171:3a7713b1edbc	1054
AnnaBridge	171:3a7713b1edbc	1055	/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
AnnaBridge	171:3a7713b1edbc	1056	* @{
AnnaBridge	171:3a7713b1edbc	1057	*/
AnnaBridge	171:3a7713b1edbc	1058	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
AnnaBridge	171:3a7713b1edbc	1059	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
AnnaBridge	171:3a7713b1edbc	1060	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
AnnaBridge	171:3a7713b1edbc	1061	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
AnnaBridge	171:3a7713b1edbc	1062	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
AnnaBridge	171:3a7713b1edbc	1063	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
AnnaBridge	171:3a7713b1edbc	1064	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
AnnaBridge	171:3a7713b1edbc	1065	/**
AnnaBridge	171:3a7713b1edbc	1066	* @}
AnnaBridge	171:3a7713b1edbc	1067	*/
AnnaBridge	171:3a7713b1edbc	1068	/**
AnnaBridge	171:3a7713b1edbc	1069	* @}
AnnaBridge	171:3a7713b1edbc	1070	*/
AnnaBridge	171:3a7713b1edbc	1071
AnnaBridge	171:3a7713b1edbc	1072	/**
AnnaBridge	171:3a7713b1edbc	1073	* @}
AnnaBridge	171:3a7713b1edbc	1074	*/
AnnaBridge	171:3a7713b1edbc	1075
AnnaBridge	171:3a7713b1edbc	1076	/* Private macro -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1077	/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
AnnaBridge	171:3a7713b1edbc	1078	* @{
AnnaBridge	171:3a7713b1edbc	1079	*/
AnnaBridge	171:3a7713b1edbc	1080
AnnaBridge	171:3a7713b1edbc	1081	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
AnnaBridge	171:3a7713b1edbc	1082	* @brief macros to handle NOR device enable/disable and read/write operations
AnnaBridge	171:3a7713b1edbc	1083	* @{
AnnaBridge	171:3a7713b1edbc	1084	*/
AnnaBridge	171:3a7713b1edbc	1085
AnnaBridge	171:3a7713b1edbc	1086	/**
AnnaBridge	171:3a7713b1edbc	1087	* @brief Enable the NORSRAM device access.
AnnaBridge	171:3a7713b1edbc	1088	* @param __INSTANCE__ FMC_NORSRAM Instance
AnnaBridge	171:3a7713b1edbc	1089	* @param __BANK__ FMC_NORSRAM Bank
AnnaBridge	171:3a7713b1edbc	1090	* @retval None
AnnaBridge	171:3a7713b1edbc	1091	*/
AnnaBridge	171:3a7713b1edbc	1092	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
AnnaBridge	171:3a7713b1edbc	1093
AnnaBridge	171:3a7713b1edbc	1094	/**
AnnaBridge	171:3a7713b1edbc	1095	* @brief Disable the NORSRAM device access.
AnnaBridge	171:3a7713b1edbc	1096	* @param __INSTANCE__ FMC_NORSRAM Instance
AnnaBridge	171:3a7713b1edbc	1097	* @param __BANK__ FMC_NORSRAM Bank
AnnaBridge	171:3a7713b1edbc	1098	* @retval None
AnnaBridge	171:3a7713b1edbc	1099	*/
AnnaBridge	171:3a7713b1edbc	1100	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
AnnaBridge	171:3a7713b1edbc	1101
AnnaBridge	171:3a7713b1edbc	1102	/**
AnnaBridge	171:3a7713b1edbc	1103	* @}
AnnaBridge	171:3a7713b1edbc	1104	*/
AnnaBridge	171:3a7713b1edbc	1105
AnnaBridge	171:3a7713b1edbc	1106	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
AnnaBridge	171:3a7713b1edbc	1107	* @brief macros to handle NAND device enable/disable
AnnaBridge	171:3a7713b1edbc	1108	* @{
AnnaBridge	171:3a7713b1edbc	1109	*/
AnnaBridge	171:3a7713b1edbc	1110
AnnaBridge	171:3a7713b1edbc	1111	/**
AnnaBridge	171:3a7713b1edbc	1112	* @brief Enable the NAND device access.
AnnaBridge	171:3a7713b1edbc	1113	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	1114	* @retval None
AnnaBridge	171:3a7713b1edbc	1115	*/
AnnaBridge	171:3a7713b1edbc	1116	#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
AnnaBridge	171:3a7713b1edbc	1117
AnnaBridge	171:3a7713b1edbc	1118	/**
AnnaBridge	171:3a7713b1edbc	1119	* @brief Disable the NAND device access.
AnnaBridge	171:3a7713b1edbc	1120	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	1121	* @retval None
AnnaBridge	171:3a7713b1edbc	1122	*/
AnnaBridge	171:3a7713b1edbc	1123	#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
AnnaBridge	171:3a7713b1edbc	1124
AnnaBridge	171:3a7713b1edbc	1125	/**
AnnaBridge	171:3a7713b1edbc	1126	* @}
AnnaBridge	171:3a7713b1edbc	1127	*/
AnnaBridge	171:3a7713b1edbc	1128
AnnaBridge	171:3a7713b1edbc	1129	/** @defgroup FMC_Interrupt FMC Interrupt
AnnaBridge	171:3a7713b1edbc	1130	* @brief macros to handle FMC interrupts
AnnaBridge	171:3a7713b1edbc	1131	* @{
AnnaBridge	171:3a7713b1edbc	1132	*/
AnnaBridge	171:3a7713b1edbc	1133
AnnaBridge	171:3a7713b1edbc	1134	/**
AnnaBridge	171:3a7713b1edbc	1135	* @brief Enable the NAND device interrupt.
AnnaBridge	171:3a7713b1edbc	1136	* @param __INSTANCE__ FMC_NAND instance
AnnaBridge	171:3a7713b1edbc	1137	* @param __INTERRUPT__ FMC_NAND interrupt
AnnaBridge	171:3a7713b1edbc	1138	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1139	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	171:3a7713b1edbc	1140	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	171:3a7713b1edbc	1141	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	171:3a7713b1edbc	1142	* @retval None
AnnaBridge	171:3a7713b1edbc	1143	*/
AnnaBridge	171:3a7713b1edbc	1144	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1145
AnnaBridge	171:3a7713b1edbc	1146	/**
AnnaBridge	171:3a7713b1edbc	1147	* @brief Disable the NAND device interrupt.
AnnaBridge	171:3a7713b1edbc	1148	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	1149	* @param __INTERRUPT__ FMC_NAND interrupt
AnnaBridge	171:3a7713b1edbc	1150	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1151	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	171:3a7713b1edbc	1152	* @arg FMC_IT_LEVEL: Interrupt level.
AnnaBridge	171:3a7713b1edbc	1153	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	171:3a7713b1edbc	1154	* @retval None
AnnaBridge	171:3a7713b1edbc	1155	*/
AnnaBridge	171:3a7713b1edbc	1156	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1157
AnnaBridge	171:3a7713b1edbc	1158	/**
AnnaBridge	171:3a7713b1edbc	1159	* @brief Get flag status of the NAND device.
AnnaBridge	171:3a7713b1edbc	1160	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	1161	* @param __BANK__ FMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	1162	* @param __FLAG__ FMC_NAND flag
AnnaBridge	171:3a7713b1edbc	1163	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1164	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	171:3a7713b1edbc	1165	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	171:3a7713b1edbc	1166	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	171:3a7713b1edbc	1167	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	171:3a7713b1edbc	1168	* @retval The state of FLAG (SET or RESET).
AnnaBridge	171:3a7713b1edbc	1169	*/
AnnaBridge	171:3a7713b1edbc	1170	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
AnnaBridge	171:3a7713b1edbc	1171
AnnaBridge	171:3a7713b1edbc	1172	/**
AnnaBridge	171:3a7713b1edbc	1173	* @brief Clear flag status of the NAND device.
AnnaBridge	171:3a7713b1edbc	1174	* @param __INSTANCE__ FMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	1175	* @param __FLAG__ FMC_NAND flag
AnnaBridge	171:3a7713b1edbc	1176	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1177	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	171:3a7713b1edbc	1178	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	171:3a7713b1edbc	1179	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	171:3a7713b1edbc	1180	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	171:3a7713b1edbc	1181	* @retval None
AnnaBridge	171:3a7713b1edbc	1182	*/
AnnaBridge	171:3a7713b1edbc	1183	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
AnnaBridge	171:3a7713b1edbc	1184
AnnaBridge	171:3a7713b1edbc	1185	/**
AnnaBridge	171:3a7713b1edbc	1186	* @brief Enable the SDRAM device interrupt.
AnnaBridge	171:3a7713b1edbc	1187	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	171:3a7713b1edbc	1188	* @param __INTERRUPT__ FMC_SDRAM interrupt
AnnaBridge	171:3a7713b1edbc	1189	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1190	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
AnnaBridge	171:3a7713b1edbc	1191	* @retval None
AnnaBridge	171:3a7713b1edbc	1192	*/
AnnaBridge	171:3a7713b1edbc	1193	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1194
AnnaBridge	171:3a7713b1edbc	1195	/**
AnnaBridge	171:3a7713b1edbc	1196	* @brief Disable the SDRAM device interrupt.
AnnaBridge	171:3a7713b1edbc	1197	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	171:3a7713b1edbc	1198	* @param __INTERRUPT__ FMC_SDRAM interrupt
AnnaBridge	171:3a7713b1edbc	1199	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1200	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
AnnaBridge	171:3a7713b1edbc	1201	* @retval None
AnnaBridge	171:3a7713b1edbc	1202	*/
AnnaBridge	171:3a7713b1edbc	1203	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1204
AnnaBridge	171:3a7713b1edbc	1205	/**
AnnaBridge	171:3a7713b1edbc	1206	* @brief Get flag status of the SDRAM device.
AnnaBridge	171:3a7713b1edbc	1207	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	171:3a7713b1edbc	1208	* @param __FLAG__ FMC_SDRAM flag
AnnaBridge	171:3a7713b1edbc	1209	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1210	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
AnnaBridge	171:3a7713b1edbc	1211	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
AnnaBridge	171:3a7713b1edbc	1212	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
AnnaBridge	171:3a7713b1edbc	1213	* @retval The state of FLAG (SET or RESET).
AnnaBridge	171:3a7713b1edbc	1214	*/
AnnaBridge	171:3a7713b1edbc	1215	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
AnnaBridge	171:3a7713b1edbc	1216
AnnaBridge	171:3a7713b1edbc	1217	/**
AnnaBridge	171:3a7713b1edbc	1218	* @brief Clear flag status of the SDRAM device.
AnnaBridge	171:3a7713b1edbc	1219	* @param __INSTANCE__ FMC_SDRAM instance
AnnaBridge	171:3a7713b1edbc	1220	* @param __FLAG__ FMC_SDRAM flag
AnnaBridge	171:3a7713b1edbc	1221	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1222	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
AnnaBridge	171:3a7713b1edbc	1223	* @retval None
AnnaBridge	171:3a7713b1edbc	1224	*/
AnnaBridge	171:3a7713b1edbc	1225	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
AnnaBridge	171:3a7713b1edbc	1226	/**
AnnaBridge	171:3a7713b1edbc	1227	* @}
AnnaBridge	171:3a7713b1edbc	1228	*/
AnnaBridge	171:3a7713b1edbc	1229
AnnaBridge	171:3a7713b1edbc	1230	/**
AnnaBridge	171:3a7713b1edbc	1231	* @}
AnnaBridge	171:3a7713b1edbc	1232	*/
AnnaBridge	171:3a7713b1edbc	1233
AnnaBridge	171:3a7713b1edbc	1234	/* Private functions ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1235	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
AnnaBridge	171:3a7713b1edbc	1236	* @{
AnnaBridge	171:3a7713b1edbc	1237	*/
AnnaBridge	171:3a7713b1edbc	1238
AnnaBridge	171:3a7713b1edbc	1239	/** @defgroup FMC_LL_NORSRAM NOR SRAM
AnnaBridge	171:3a7713b1edbc	1240	* @{
AnnaBridge	171:3a7713b1edbc	1241	*/
AnnaBridge	171:3a7713b1edbc	1242	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
AnnaBridge	171:3a7713b1edbc	1243	* @{
AnnaBridge	171:3a7713b1edbc	1244	*/
AnnaBridge	171:3a7713b1edbc	1245	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
AnnaBridge	171:3a7713b1edbc	1246	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1247	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
AnnaBridge	171:3a7713b1edbc	1248	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1249	/**
AnnaBridge	171:3a7713b1edbc	1250	* @}
AnnaBridge	171:3a7713b1edbc	1251	*/
AnnaBridge	171:3a7713b1edbc	1252
AnnaBridge	171:3a7713b1edbc	1253	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
AnnaBridge	171:3a7713b1edbc	1254	* @{
AnnaBridge	171:3a7713b1edbc	1255	*/
AnnaBridge	171:3a7713b1edbc	1256	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1257	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1258	/**
AnnaBridge	171:3a7713b1edbc	1259	* @}
AnnaBridge	171:3a7713b1edbc	1260	*/
AnnaBridge	171:3a7713b1edbc	1261	/**
AnnaBridge	171:3a7713b1edbc	1262	* @}
AnnaBridge	171:3a7713b1edbc	1263	*/
AnnaBridge	171:3a7713b1edbc	1264
AnnaBridge	171:3a7713b1edbc	1265	/** @defgroup FMC_LL_NAND NAND
AnnaBridge	171:3a7713b1edbc	1266	* @{
AnnaBridge	171:3a7713b1edbc	1267	*/
AnnaBridge	171:3a7713b1edbc	1268	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
AnnaBridge	171:3a7713b1edbc	1269	* @{
AnnaBridge	171:3a7713b1edbc	1270	*/
AnnaBridge	171:3a7713b1edbc	1271	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
AnnaBridge	171:3a7713b1edbc	1272	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1273	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1274	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1275	/**
AnnaBridge	171:3a7713b1edbc	1276	* @}
AnnaBridge	171:3a7713b1edbc	1277	*/
AnnaBridge	171:3a7713b1edbc	1278
AnnaBridge	171:3a7713b1edbc	1279	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
AnnaBridge	171:3a7713b1edbc	1280	* @{
AnnaBridge	171:3a7713b1edbc	1281	*/
AnnaBridge	171:3a7713b1edbc	1282	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1283	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1284	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
AnnaBridge	171:3a7713b1edbc	1285	/**
AnnaBridge	171:3a7713b1edbc	1286	* @}
AnnaBridge	171:3a7713b1edbc	1287	*/
AnnaBridge	171:3a7713b1edbc	1288
AnnaBridge	171:3a7713b1edbc	1289	/** @defgroup FMC_LL_SDRAM SDRAM
AnnaBridge	171:3a7713b1edbc	1290	* @{
AnnaBridge	171:3a7713b1edbc	1291	*/
AnnaBridge	171:3a7713b1edbc	1292	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
AnnaBridge	171:3a7713b1edbc	1293	* @{
AnnaBridge	171:3a7713b1edbc	1294	*/
AnnaBridge	171:3a7713b1edbc	1295	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
AnnaBridge	171:3a7713b1edbc	1296	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1297	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1298
AnnaBridge	171:3a7713b1edbc	1299	/**
AnnaBridge	171:3a7713b1edbc	1300	* @}
AnnaBridge	171:3a7713b1edbc	1301	*/
AnnaBridge	171:3a7713b1edbc	1302
AnnaBridge	171:3a7713b1edbc	1303	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
AnnaBridge	171:3a7713b1edbc	1304	* @{
AnnaBridge	171:3a7713b1edbc	1305	*/
AnnaBridge	171:3a7713b1edbc	1306	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1307	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1308	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
AnnaBridge	171:3a7713b1edbc	1309	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
AnnaBridge	171:3a7713b1edbc	1310	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
AnnaBridge	171:3a7713b1edbc	1311	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	1312	/**
AnnaBridge	171:3a7713b1edbc	1313	* @}
AnnaBridge	171:3a7713b1edbc	1314	*/
AnnaBridge	171:3a7713b1edbc	1315
AnnaBridge	171:3a7713b1edbc	1316	/**
AnnaBridge	171:3a7713b1edbc	1317	* @}
AnnaBridge	171:3a7713b1edbc	1318	*/
AnnaBridge	171:3a7713b1edbc	1319
AnnaBridge	171:3a7713b1edbc	1320	/**
AnnaBridge	171:3a7713b1edbc	1321	* @}
AnnaBridge	171:3a7713b1edbc	1322	*/
AnnaBridge	171:3a7713b1edbc	1323
AnnaBridge	171:3a7713b1edbc	1324	/**
AnnaBridge	171:3a7713b1edbc	1325	* @}
AnnaBridge	171:3a7713b1edbc	1326	*/
AnnaBridge	171:3a7713b1edbc	1327
AnnaBridge	171:3a7713b1edbc	1328	/**
AnnaBridge	171:3a7713b1edbc	1329	* @}
AnnaBridge	171:3a7713b1edbc	1330	*/
AnnaBridge	171:3a7713b1edbc	1331	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1332	}
AnnaBridge	171:3a7713b1edbc	1333	#endif
AnnaBridge	171:3a7713b1edbc	1334
AnnaBridge	171:3a7713b1edbc	1335	#endif /* __STM32F7xx_LL_FMC_H */
AnnaBridge	171:3a7713b1edbc	1336
AnnaBridge	171:3a7713b1edbc	1337	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/