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TARGET_DISCO_F769NI/TOOLCHAIN_GCC_ARM/stm32f7xx_hal_adc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f7xx_hal_adc.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of ADC HAL extension module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F7xx_ADC_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F7xx_ADC_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32f7xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* Include low level driver */
AnnaBridge 171:3a7713b1edbc 48 #include "stm32f7xx_ll_adc.h"
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 /** @addtogroup STM32F7xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 51 * @{
AnnaBridge 171:3a7713b1edbc 52 */
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54 /** @addtogroup ADC
AnnaBridge 171:3a7713b1edbc 55 * @{
AnnaBridge 171:3a7713b1edbc 56 */
AnnaBridge 171:3a7713b1edbc 57
AnnaBridge 171:3a7713b1edbc 58 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 59 /** @defgroup ADC_Exported_Types ADC Exported Types
AnnaBridge 171:3a7713b1edbc 60 * @{
AnnaBridge 171:3a7713b1edbc 61 */
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 /**
AnnaBridge 171:3a7713b1edbc 64 * @brief Structure definition of ADC and regular group initialization
AnnaBridge 171:3a7713b1edbc 65 * @note Parameters of this structure are shared within 2 scopes:
AnnaBridge 171:3a7713b1edbc 66 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
AnnaBridge 171:3a7713b1edbc 67 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
AnnaBridge 171:3a7713b1edbc 68 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
AnnaBridge 171:3a7713b1edbc 69 * ADC state can be either:
AnnaBridge 171:3a7713b1edbc 70 * - For all parameters: ADC disabled
AnnaBridge 171:3a7713b1edbc 71 * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
AnnaBridge 171:3a7713b1edbc 72 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
AnnaBridge 171:3a7713b1edbc 73 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
AnnaBridge 171:3a7713b1edbc 74 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
AnnaBridge 171:3a7713b1edbc 75 */
AnnaBridge 171:3a7713b1edbc 76 typedef struct
AnnaBridge 171:3a7713b1edbc 77 {
AnnaBridge 171:3a7713b1edbc 78 uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
AnnaBridge 171:3a7713b1edbc 79 all the ADCs.
AnnaBridge 171:3a7713b1edbc 80 This parameter can be a value of @ref ADC_ClockPrescaler */
AnnaBridge 171:3a7713b1edbc 81 uint32_t Resolution; /*!< Configures the ADC resolution.
AnnaBridge 171:3a7713b1edbc 82 This parameter can be a value of @ref ADC_Resolution */
AnnaBridge 171:3a7713b1edbc 83 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
AnnaBridge 171:3a7713b1edbc 84 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
AnnaBridge 171:3a7713b1edbc 85 This parameter can be a value of @ref ADC_Data_Align */
AnnaBridge 171:3a7713b1edbc 86 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
AnnaBridge 171:3a7713b1edbc 87 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
AnnaBridge 171:3a7713b1edbc 88 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
AnnaBridge 171:3a7713b1edbc 89 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
AnnaBridge 171:3a7713b1edbc 90 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
AnnaBridge 171:3a7713b1edbc 91 Scan direction is upward: from rank1 to rank 'n'.
AnnaBridge 171:3a7713b1edbc 92 This parameter can be a value of @ref ADC_Scan_mode.
AnnaBridge 171:3a7713b1edbc 93 This parameter can be set to ENABLE or DISABLE */
AnnaBridge 171:3a7713b1edbc 94 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
AnnaBridge 171:3a7713b1edbc 95 This parameter can be a value of @ref ADC_EOCSelection.
AnnaBridge 171:3a7713b1edbc 96 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
AnnaBridge 171:3a7713b1edbc 97 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
AnnaBridge 171:3a7713b1edbc 98 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
AnnaBridge 171:3a7713b1edbc 99 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
AnnaBridge 171:3a7713b1edbc 100 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
AnnaBridge 171:3a7713b1edbc 101 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
AnnaBridge 171:3a7713b1edbc 102 after the selected trigger occurred (software start or external trigger).
AnnaBridge 171:3a7713b1edbc 103 This parameter can be set to ENABLE or DISABLE. */
AnnaBridge 171:3a7713b1edbc 104 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
AnnaBridge 171:3a7713b1edbc 105 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
AnnaBridge 171:3a7713b1edbc 106 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
AnnaBridge 171:3a7713b1edbc 107 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
AnnaBridge 171:3a7713b1edbc 108 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
AnnaBridge 171:3a7713b1edbc 109 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
AnnaBridge 171:3a7713b1edbc 110 This parameter can be set to ENABLE or DISABLE. */
AnnaBridge 171:3a7713b1edbc 111 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
AnnaBridge 171:3a7713b1edbc 112 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
AnnaBridge 171:3a7713b1edbc 113 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
AnnaBridge 171:3a7713b1edbc 114 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
AnnaBridge 171:3a7713b1edbc 115 If set to ADC_SOFTWARE_START, external triggers are disabled.
AnnaBridge 171:3a7713b1edbc 116 If set to external trigger source, triggering is on event rising edge by default.
AnnaBridge 171:3a7713b1edbc 117 This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
AnnaBridge 171:3a7713b1edbc 118 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
AnnaBridge 171:3a7713b1edbc 119 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
AnnaBridge 171:3a7713b1edbc 120 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
AnnaBridge 171:3a7713b1edbc 121 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
AnnaBridge 171:3a7713b1edbc 122 or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
AnnaBridge 171:3a7713b1edbc 123 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
AnnaBridge 171:3a7713b1edbc 124 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
AnnaBridge 171:3a7713b1edbc 125 This parameter can be set to ENABLE or DISABLE. */
AnnaBridge 171:3a7713b1edbc 126 }ADC_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /**
AnnaBridge 171:3a7713b1edbc 131 * @brief Structure definition of ADC channel for regular group
AnnaBridge 171:3a7713b1edbc 132 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
AnnaBridge 171:3a7713b1edbc 133 * ADC can be either disabled or enabled without conversion on going on regular group.
AnnaBridge 171:3a7713b1edbc 134 */
AnnaBridge 171:3a7713b1edbc 135 typedef struct
AnnaBridge 171:3a7713b1edbc 136 {
AnnaBridge 171:3a7713b1edbc 137 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
AnnaBridge 171:3a7713b1edbc 138 This parameter can be a value of @ref ADC_channels */
AnnaBridge 171:3a7713b1edbc 139 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
AnnaBridge 171:3a7713b1edbc 140 This parameter must be a number between Min_Data = 1 and Max_Data = 16
AnnaBridge 171:3a7713b1edbc 141 This parameter can be a value of @ref ADC_regular_rank */
AnnaBridge 171:3a7713b1edbc 142 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
AnnaBridge 171:3a7713b1edbc 143 Unit: ADC clock cycles
AnnaBridge 171:3a7713b1edbc 144 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
AnnaBridge 171:3a7713b1edbc 145 This parameter can be a value of @ref ADC_sampling_times
AnnaBridge 171:3a7713b1edbc 146 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
AnnaBridge 171:3a7713b1edbc 147 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
AnnaBridge 171:3a7713b1edbc 148 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
AnnaBridge 171:3a7713b1edbc 149 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
AnnaBridge 171:3a7713b1edbc 150 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
AnnaBridge 171:3a7713b1edbc 151 uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
AnnaBridge 171:3a7713b1edbc 152 }ADC_ChannelConfTypeDef;
AnnaBridge 171:3a7713b1edbc 153
AnnaBridge 171:3a7713b1edbc 154 /**
AnnaBridge 171:3a7713b1edbc 155 * @brief ADC Configuration multi-mode structure definition
AnnaBridge 171:3a7713b1edbc 156 */
AnnaBridge 171:3a7713b1edbc 157 typedef struct
AnnaBridge 171:3a7713b1edbc 158 {
AnnaBridge 171:3a7713b1edbc 159 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
AnnaBridge 171:3a7713b1edbc 160 This parameter can be a value of @ref ADC_analog_watchdog_selection */
AnnaBridge 171:3a7713b1edbc 161 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
AnnaBridge 171:3a7713b1edbc 162 This parameter must be a 12-bit value. */
AnnaBridge 171:3a7713b1edbc 163 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
AnnaBridge 171:3a7713b1edbc 164 This parameter must be a 12-bit value. */
AnnaBridge 171:3a7713b1edbc 165 uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
AnnaBridge 171:3a7713b1edbc 166 This parameter has an effect only if watchdog mode is configured on single channel
AnnaBridge 171:3a7713b1edbc 167 This parameter can be a value of @ref ADC_channels */
AnnaBridge 171:3a7713b1edbc 168 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
AnnaBridge 171:3a7713b1edbc 169 is interrupt mode or in polling mode.
AnnaBridge 171:3a7713b1edbc 170 This parameter can be set to ENABLE or DISABLE */
AnnaBridge 171:3a7713b1edbc 171 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
AnnaBridge 171:3a7713b1edbc 172 }ADC_AnalogWDGConfTypeDef;
AnnaBridge 171:3a7713b1edbc 173
AnnaBridge 171:3a7713b1edbc 174 /**
AnnaBridge 171:3a7713b1edbc 175 * @brief HAL ADC state machine: ADC states definition (bitfields)
AnnaBridge 171:3a7713b1edbc 176 */
AnnaBridge 171:3a7713b1edbc 177 /* States of ADC global scope */
AnnaBridge 171:3a7713b1edbc 178 #define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
AnnaBridge 171:3a7713b1edbc 179 #define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
AnnaBridge 171:3a7713b1edbc 180 #define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
AnnaBridge 171:3a7713b1edbc 181 #define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
AnnaBridge 171:3a7713b1edbc 182
AnnaBridge 171:3a7713b1edbc 183 /* States of ADC errors */
AnnaBridge 171:3a7713b1edbc 184 #define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
AnnaBridge 171:3a7713b1edbc 185 #define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
AnnaBridge 171:3a7713b1edbc 186 #define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
AnnaBridge 171:3a7713b1edbc 187
AnnaBridge 171:3a7713b1edbc 188 /* States of ADC group regular */
AnnaBridge 171:3a7713b1edbc 189 #define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
AnnaBridge 171:3a7713b1edbc 190 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
AnnaBridge 171:3a7713b1edbc 191 #define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
AnnaBridge 171:3a7713b1edbc 192 #define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
AnnaBridge 171:3a7713b1edbc 193
AnnaBridge 171:3a7713b1edbc 194 /* States of ADC group injected */
AnnaBridge 171:3a7713b1edbc 195 #define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
AnnaBridge 171:3a7713b1edbc 196 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
AnnaBridge 171:3a7713b1edbc 197 #define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */
AnnaBridge 171:3a7713b1edbc 198
AnnaBridge 171:3a7713b1edbc 199 /* States of ADC analog watchdogs */
AnnaBridge 171:3a7713b1edbc 200 #define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
AnnaBridge 171:3a7713b1edbc 201 #define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
AnnaBridge 171:3a7713b1edbc 202 #define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204 /* States of ADC multi-mode */
AnnaBridge 171:3a7713b1edbc 205 #define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */
AnnaBridge 171:3a7713b1edbc 206
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 /**
AnnaBridge 171:3a7713b1edbc 209 * @brief ADC handle Structure definition
AnnaBridge 171:3a7713b1edbc 210 */
AnnaBridge 171:3a7713b1edbc 211 typedef struct
AnnaBridge 171:3a7713b1edbc 212 {
AnnaBridge 171:3a7713b1edbc 213 ADC_TypeDef *Instance; /*!< Register base address */
AnnaBridge 171:3a7713b1edbc 214
AnnaBridge 171:3a7713b1edbc 215 ADC_InitTypeDef Init; /*!< ADC required parameters */
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
AnnaBridge 171:3a7713b1edbc 218
AnnaBridge 171:3a7713b1edbc 219 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 HAL_LockTypeDef Lock; /*!< ADC locking object */
AnnaBridge 171:3a7713b1edbc 222
AnnaBridge 171:3a7713b1edbc 223 __IO uint32_t State; /*!< ADC communication state */
AnnaBridge 171:3a7713b1edbc 224
AnnaBridge 171:3a7713b1edbc 225 __IO uint32_t ErrorCode; /*!< ADC Error code */
AnnaBridge 171:3a7713b1edbc 226 }ADC_HandleTypeDef;
AnnaBridge 171:3a7713b1edbc 227 /**
AnnaBridge 171:3a7713b1edbc 228 * @}
AnnaBridge 171:3a7713b1edbc 229 */
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 232 /** @defgroup ADC_Exported_Constants ADC Exported Constants
AnnaBridge 171:3a7713b1edbc 233 * @{
AnnaBridge 171:3a7713b1edbc 234 */
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 /** @defgroup ADC_Error_Code ADC Error Code
AnnaBridge 171:3a7713b1edbc 237 * @{
AnnaBridge 171:3a7713b1edbc 238 */
AnnaBridge 171:3a7713b1edbc 239 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
AnnaBridge 171:3a7713b1edbc 240 #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
AnnaBridge 171:3a7713b1edbc 241 enable/disable, erroneous state */
AnnaBridge 171:3a7713b1edbc 242 #define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
AnnaBridge 171:3a7713b1edbc 243 #define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
AnnaBridge 171:3a7713b1edbc 244 /**
AnnaBridge 171:3a7713b1edbc 245 * @}
AnnaBridge 171:3a7713b1edbc 246 */
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248
AnnaBridge 171:3a7713b1edbc 249 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
AnnaBridge 171:3a7713b1edbc 250 * @{
AnnaBridge 171:3a7713b1edbc 251 */
AnnaBridge 171:3a7713b1edbc 252 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 253 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
AnnaBridge 171:3a7713b1edbc 254 #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
AnnaBridge 171:3a7713b1edbc 255 #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
AnnaBridge 171:3a7713b1edbc 256 /**
AnnaBridge 171:3a7713b1edbc 257 * @}
AnnaBridge 171:3a7713b1edbc 258 */
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
AnnaBridge 171:3a7713b1edbc 261 * @{
AnnaBridge 171:3a7713b1edbc 262 */
AnnaBridge 171:3a7713b1edbc 263 #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 264 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
AnnaBridge 171:3a7713b1edbc 265 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
AnnaBridge 171:3a7713b1edbc 266 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
AnnaBridge 171:3a7713b1edbc 267 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
AnnaBridge 171:3a7713b1edbc 268 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
AnnaBridge 171:3a7713b1edbc 269 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
AnnaBridge 171:3a7713b1edbc 270 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
AnnaBridge 171:3a7713b1edbc 271 #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
AnnaBridge 171:3a7713b1edbc 272 #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
AnnaBridge 171:3a7713b1edbc 273 #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
AnnaBridge 171:3a7713b1edbc 274 #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
AnnaBridge 171:3a7713b1edbc 275 #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
AnnaBridge 171:3a7713b1edbc 276 #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
AnnaBridge 171:3a7713b1edbc 277 #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
AnnaBridge 171:3a7713b1edbc 278 #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
AnnaBridge 171:3a7713b1edbc 279 /**
AnnaBridge 171:3a7713b1edbc 280 * @}
AnnaBridge 171:3a7713b1edbc 281 */
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 /** @defgroup ADC_Resolution ADC Resolution
AnnaBridge 171:3a7713b1edbc 284 * @{
AnnaBridge 171:3a7713b1edbc 285 */
AnnaBridge 171:3a7713b1edbc 286 #define ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 287 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
AnnaBridge 171:3a7713b1edbc 288 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
AnnaBridge 171:3a7713b1edbc 289 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
AnnaBridge 171:3a7713b1edbc 290 /**
AnnaBridge 171:3a7713b1edbc 291 * @}
AnnaBridge 171:3a7713b1edbc 292 */
AnnaBridge 171:3a7713b1edbc 293
AnnaBridge 171:3a7713b1edbc 294 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
AnnaBridge 171:3a7713b1edbc 295 * @{
AnnaBridge 171:3a7713b1edbc 296 */
AnnaBridge 171:3a7713b1edbc 297 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 298 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
AnnaBridge 171:3a7713b1edbc 299 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
AnnaBridge 171:3a7713b1edbc 300 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
AnnaBridge 171:3a7713b1edbc 301 /**
AnnaBridge 171:3a7713b1edbc 302 * @}
AnnaBridge 171:3a7713b1edbc 303 */
AnnaBridge 171:3a7713b1edbc 304
AnnaBridge 171:3a7713b1edbc 305 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
AnnaBridge 171:3a7713b1edbc 306 * @{
AnnaBridge 171:3a7713b1edbc 307 */
AnnaBridge 171:3a7713b1edbc 308 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
AnnaBridge 171:3a7713b1edbc 309 /* compatibility with other STM32 devices. */
AnnaBridge 171:3a7713b1edbc 310
AnnaBridge 171:3a7713b1edbc 311
AnnaBridge 171:3a7713b1edbc 312 #define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 313 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
AnnaBridge 171:3a7713b1edbc 314 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
AnnaBridge 171:3a7713b1edbc 315 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 316 #define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
AnnaBridge 171:3a7713b1edbc 317 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 318 #define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
AnnaBridge 171:3a7713b1edbc 319 #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 320 #define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3)
AnnaBridge 171:3a7713b1edbc 321 #define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 322 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
AnnaBridge 171:3a7713b1edbc 323 #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 324 #define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
AnnaBridge 171:3a7713b1edbc 325 #define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL)
AnnaBridge 171:3a7713b1edbc 328 #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 /**
AnnaBridge 171:3a7713b1edbc 331 * @}
AnnaBridge 171:3a7713b1edbc 332 */
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334 /** @defgroup ADC_Data_Align ADC Data Align
AnnaBridge 171:3a7713b1edbc 335 * @{
AnnaBridge 171:3a7713b1edbc 336 */
AnnaBridge 171:3a7713b1edbc 337 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 338 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
AnnaBridge 171:3a7713b1edbc 339 /**
AnnaBridge 171:3a7713b1edbc 340 * @}
AnnaBridge 171:3a7713b1edbc 341 */
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 /** @defgroup ADC_Scan_mode ADC sequencer scan mode
AnnaBridge 171:3a7713b1edbc 344 * @{
AnnaBridge 171:3a7713b1edbc 345 */
AnnaBridge 171:3a7713b1edbc 346 #define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */
AnnaBridge 171:3a7713b1edbc 347 #define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */
AnnaBridge 171:3a7713b1edbc 348 /**
AnnaBridge 171:3a7713b1edbc 349 * @}
AnnaBridge 171:3a7713b1edbc 350 */
AnnaBridge 171:3a7713b1edbc 351
AnnaBridge 171:3a7713b1edbc 352 /** @defgroup ADC_regular_rank ADC group regular sequencer rank
AnnaBridge 171:3a7713b1edbc 353 * @{
AnnaBridge 171:3a7713b1edbc 354 */
AnnaBridge 171:3a7713b1edbc 355 #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */
AnnaBridge 171:3a7713b1edbc 356 #define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */
AnnaBridge 171:3a7713b1edbc 357 #define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */
AnnaBridge 171:3a7713b1edbc 358 #define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */
AnnaBridge 171:3a7713b1edbc 359 #define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */
AnnaBridge 171:3a7713b1edbc 360 #define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */
AnnaBridge 171:3a7713b1edbc 361 #define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */
AnnaBridge 171:3a7713b1edbc 362 #define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */
AnnaBridge 171:3a7713b1edbc 363 #define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */
AnnaBridge 171:3a7713b1edbc 364 #define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */
AnnaBridge 171:3a7713b1edbc 365 #define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */
AnnaBridge 171:3a7713b1edbc 366 #define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */
AnnaBridge 171:3a7713b1edbc 367 #define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */
AnnaBridge 171:3a7713b1edbc 368 #define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */
AnnaBridge 171:3a7713b1edbc 369 #define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */
AnnaBridge 171:3a7713b1edbc 370 #define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */
AnnaBridge 171:3a7713b1edbc 371 /**
AnnaBridge 171:3a7713b1edbc 372 * @}
AnnaBridge 171:3a7713b1edbc 373 */
AnnaBridge 171:3a7713b1edbc 374
AnnaBridge 171:3a7713b1edbc 375 /** @defgroup ADC_channels ADC Common Channels
AnnaBridge 171:3a7713b1edbc 376 * @{
AnnaBridge 171:3a7713b1edbc 377 */
AnnaBridge 171:3a7713b1edbc 378 #define ADC_CHANNEL_0 ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 379 #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
AnnaBridge 171:3a7713b1edbc 380 #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
AnnaBridge 171:3a7713b1edbc 381 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 382 #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
AnnaBridge 171:3a7713b1edbc 383 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 384 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
AnnaBridge 171:3a7713b1edbc 385 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 386 #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
AnnaBridge 171:3a7713b1edbc 387 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 388 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
AnnaBridge 171:3a7713b1edbc 389 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 390 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
AnnaBridge 171:3a7713b1edbc 391 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 392 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
AnnaBridge 171:3a7713b1edbc 393 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 394 #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
AnnaBridge 171:3a7713b1edbc 395 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 396 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
AnnaBridge 171:3a7713b1edbc 399 #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
AnnaBridge 171:3a7713b1edbc 400 /**
AnnaBridge 171:3a7713b1edbc 401 * @}
AnnaBridge 171:3a7713b1edbc 402 */
AnnaBridge 171:3a7713b1edbc 403
AnnaBridge 171:3a7713b1edbc 404 /** @defgroup ADC_sampling_times ADC Sampling Times
AnnaBridge 171:3a7713b1edbc 405 * @{
AnnaBridge 171:3a7713b1edbc 406 */
AnnaBridge 171:3a7713b1edbc 407 #define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 408 #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
AnnaBridge 171:3a7713b1edbc 409 #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
AnnaBridge 171:3a7713b1edbc 410 #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
AnnaBridge 171:3a7713b1edbc 411 #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
AnnaBridge 171:3a7713b1edbc 412 #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
AnnaBridge 171:3a7713b1edbc 413 #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
AnnaBridge 171:3a7713b1edbc 414 #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
AnnaBridge 171:3a7713b1edbc 415 /**
AnnaBridge 171:3a7713b1edbc 416 * @}
AnnaBridge 171:3a7713b1edbc 417 */
AnnaBridge 171:3a7713b1edbc 418
AnnaBridge 171:3a7713b1edbc 419 /** @defgroup ADC_EOCSelection ADC EOC Selection
AnnaBridge 171:3a7713b1edbc 420 * @{
AnnaBridge 171:3a7713b1edbc 421 */
AnnaBridge 171:3a7713b1edbc 422 #define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 423 #define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
AnnaBridge 171:3a7713b1edbc 424 #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */
AnnaBridge 171:3a7713b1edbc 425 /**
AnnaBridge 171:3a7713b1edbc 426 * @}
AnnaBridge 171:3a7713b1edbc 427 */
AnnaBridge 171:3a7713b1edbc 428
AnnaBridge 171:3a7713b1edbc 429 /** @defgroup ADC_Event_type ADC Event Type
AnnaBridge 171:3a7713b1edbc 430 * @{
AnnaBridge 171:3a7713b1edbc 431 */
AnnaBridge 171:3a7713b1edbc 432 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
AnnaBridge 171:3a7713b1edbc 433 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
AnnaBridge 171:3a7713b1edbc 434 /**
AnnaBridge 171:3a7713b1edbc 435 * @}
AnnaBridge 171:3a7713b1edbc 436 */
AnnaBridge 171:3a7713b1edbc 437
AnnaBridge 171:3a7713b1edbc 438 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
AnnaBridge 171:3a7713b1edbc 439 * @{
AnnaBridge 171:3a7713b1edbc 440 */
AnnaBridge 171:3a7713b1edbc 441 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
AnnaBridge 171:3a7713b1edbc 442 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
AnnaBridge 171:3a7713b1edbc 443 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
AnnaBridge 171:3a7713b1edbc 444 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
AnnaBridge 171:3a7713b1edbc 445 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
AnnaBridge 171:3a7713b1edbc 446 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
AnnaBridge 171:3a7713b1edbc 447 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 448 /**
AnnaBridge 171:3a7713b1edbc 449 * @}
AnnaBridge 171:3a7713b1edbc 450 */
AnnaBridge 171:3a7713b1edbc 451
AnnaBridge 171:3a7713b1edbc 452 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
AnnaBridge 171:3a7713b1edbc 453 * @{
AnnaBridge 171:3a7713b1edbc 454 */
AnnaBridge 171:3a7713b1edbc 455 #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
AnnaBridge 171:3a7713b1edbc 456 #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
AnnaBridge 171:3a7713b1edbc 457 #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
AnnaBridge 171:3a7713b1edbc 458 #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
AnnaBridge 171:3a7713b1edbc 459 /**
AnnaBridge 171:3a7713b1edbc 460 * @}
AnnaBridge 171:3a7713b1edbc 461 */
AnnaBridge 171:3a7713b1edbc 462
AnnaBridge 171:3a7713b1edbc 463 /** @defgroup ADC_flags_definition ADC Flags Definition
AnnaBridge 171:3a7713b1edbc 464 * @{
AnnaBridge 171:3a7713b1edbc 465 */
AnnaBridge 171:3a7713b1edbc 466 #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
AnnaBridge 171:3a7713b1edbc 467 #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
AnnaBridge 171:3a7713b1edbc 468 #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
AnnaBridge 171:3a7713b1edbc 469 #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
AnnaBridge 171:3a7713b1edbc 470 #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
AnnaBridge 171:3a7713b1edbc 471 #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
AnnaBridge 171:3a7713b1edbc 472 /**
AnnaBridge 171:3a7713b1edbc 473 * @}
AnnaBridge 171:3a7713b1edbc 474 */
AnnaBridge 171:3a7713b1edbc 475
AnnaBridge 171:3a7713b1edbc 476 /** @defgroup ADC_channels_type ADC Channels Type
AnnaBridge 171:3a7713b1edbc 477 * @{
AnnaBridge 171:3a7713b1edbc 478 */
AnnaBridge 171:3a7713b1edbc 479 #define ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
AnnaBridge 171:3a7713b1edbc 480 #define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */
AnnaBridge 171:3a7713b1edbc 481 #define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
AnnaBridge 171:3a7713b1edbc 482 /**
AnnaBridge 171:3a7713b1edbc 483 * @}
AnnaBridge 171:3a7713b1edbc 484 */
AnnaBridge 171:3a7713b1edbc 485
AnnaBridge 171:3a7713b1edbc 486 /**
AnnaBridge 171:3a7713b1edbc 487 * @}
AnnaBridge 171:3a7713b1edbc 488 */
AnnaBridge 171:3a7713b1edbc 489
AnnaBridge 171:3a7713b1edbc 490 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 491 /** @defgroup ADC_Exported_Macros ADC Exported Macros
AnnaBridge 171:3a7713b1edbc 492 * @{
AnnaBridge 171:3a7713b1edbc 493 */
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 /** @brief Reset ADC handle state
AnnaBridge 171:3a7713b1edbc 496 * @param __HANDLE__ ADC handle
AnnaBridge 171:3a7713b1edbc 497 * @retval None
AnnaBridge 171:3a7713b1edbc 498 */
AnnaBridge 171:3a7713b1edbc 499 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
AnnaBridge 171:3a7713b1edbc 500
AnnaBridge 171:3a7713b1edbc 501 /**
AnnaBridge 171:3a7713b1edbc 502 * @brief Enable the ADC peripheral.
AnnaBridge 171:3a7713b1edbc 503 * @param __HANDLE__ ADC handle
AnnaBridge 171:3a7713b1edbc 504 * @retval None
AnnaBridge 171:3a7713b1edbc 505 */
AnnaBridge 171:3a7713b1edbc 506 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
AnnaBridge 171:3a7713b1edbc 507
AnnaBridge 171:3a7713b1edbc 508 /**
AnnaBridge 171:3a7713b1edbc 509 * @brief Disable the ADC peripheral.
AnnaBridge 171:3a7713b1edbc 510 * @param __HANDLE__ ADC handle
AnnaBridge 171:3a7713b1edbc 511 * @retval None
AnnaBridge 171:3a7713b1edbc 512 */
AnnaBridge 171:3a7713b1edbc 513 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
AnnaBridge 171:3a7713b1edbc 514
AnnaBridge 171:3a7713b1edbc 515 /**
AnnaBridge 171:3a7713b1edbc 516 * @brief Enable the ADC end of conversion interrupt.
AnnaBridge 171:3a7713b1edbc 517 * @param __HANDLE__ specifies the ADC Handle.
AnnaBridge 171:3a7713b1edbc 518 * @param __INTERRUPT__ ADC Interrupt.
AnnaBridge 171:3a7713b1edbc 519 * @retval None
AnnaBridge 171:3a7713b1edbc 520 */
AnnaBridge 171:3a7713b1edbc 521 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 522
AnnaBridge 171:3a7713b1edbc 523 /**
AnnaBridge 171:3a7713b1edbc 524 * @brief Disable the ADC end of conversion interrupt.
AnnaBridge 171:3a7713b1edbc 525 * @param __HANDLE__ specifies the ADC Handle.
AnnaBridge 171:3a7713b1edbc 526 * @param __INTERRUPT__ ADC interrupt.
AnnaBridge 171:3a7713b1edbc 527 * @retval None
AnnaBridge 171:3a7713b1edbc 528 */
AnnaBridge 171:3a7713b1edbc 529 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 530
AnnaBridge 171:3a7713b1edbc 531 /** @brief Check if the specified ADC interrupt source is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 532 * @param __HANDLE__ specifies the ADC Handle.
AnnaBridge 171:3a7713b1edbc 533 * @param __INTERRUPT__ specifies the ADC interrupt source to check.
AnnaBridge 171:3a7713b1edbc 534 * @retval The new state of __IT__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 535 */
AnnaBridge 171:3a7713b1edbc 536 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 537
AnnaBridge 171:3a7713b1edbc 538 /**
AnnaBridge 171:3a7713b1edbc 539 * @brief Clear the ADC's pending flags.
AnnaBridge 171:3a7713b1edbc 540 * @param __HANDLE__ specifies the ADC Handle.
AnnaBridge 171:3a7713b1edbc 541 * @param __FLAG__ ADC flag.
AnnaBridge 171:3a7713b1edbc 542 * @retval None
AnnaBridge 171:3a7713b1edbc 543 */
AnnaBridge 171:3a7713b1edbc 544 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
AnnaBridge 171:3a7713b1edbc 545
AnnaBridge 171:3a7713b1edbc 546 /**
AnnaBridge 171:3a7713b1edbc 547 * @brief Get the selected ADC's flag status.
AnnaBridge 171:3a7713b1edbc 548 * @param __HANDLE__ specifies the ADC Handle.
AnnaBridge 171:3a7713b1edbc 549 * @param __FLAG__ ADC flag.
AnnaBridge 171:3a7713b1edbc 550 * @retval None
AnnaBridge 171:3a7713b1edbc 551 */
AnnaBridge 171:3a7713b1edbc 552 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 /**
AnnaBridge 171:3a7713b1edbc 555 * @}
AnnaBridge 171:3a7713b1edbc 556 */
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 /* Include ADC HAL Extension module */
AnnaBridge 171:3a7713b1edbc 559 #include "stm32f7xx_hal_adc_ex.h"
AnnaBridge 171:3a7713b1edbc 560
AnnaBridge 171:3a7713b1edbc 561 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 562 /** @addtogroup ADC_Exported_Functions
AnnaBridge 171:3a7713b1edbc 563 * @{
AnnaBridge 171:3a7713b1edbc 564 */
AnnaBridge 171:3a7713b1edbc 565
AnnaBridge 171:3a7713b1edbc 566 /** @addtogroup ADC_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 567 * @{
AnnaBridge 171:3a7713b1edbc 568 */
AnnaBridge 171:3a7713b1edbc 569 /* Initialization/de-initialization functions ***********************************/
AnnaBridge 171:3a7713b1edbc 570 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 571 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
AnnaBridge 171:3a7713b1edbc 572 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 573 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 574 /**
AnnaBridge 171:3a7713b1edbc 575 * @}
AnnaBridge 171:3a7713b1edbc 576 */
AnnaBridge 171:3a7713b1edbc 577
AnnaBridge 171:3a7713b1edbc 578 /** @addtogroup ADC_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 579 * @{
AnnaBridge 171:3a7713b1edbc 580 */
AnnaBridge 171:3a7713b1edbc 581 /* I/O operation functions ******************************************************/
AnnaBridge 171:3a7713b1edbc 582 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 583 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 584 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 585
AnnaBridge 171:3a7713b1edbc 586 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 587
AnnaBridge 171:3a7713b1edbc 588 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 589 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 590
AnnaBridge 171:3a7713b1edbc 591 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 592
AnnaBridge 171:3a7713b1edbc 593 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
AnnaBridge 171:3a7713b1edbc 594 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 595
AnnaBridge 171:3a7713b1edbc 596 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 597
AnnaBridge 171:3a7713b1edbc 598 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 599 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 600 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 601 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
AnnaBridge 171:3a7713b1edbc 602 /**
AnnaBridge 171:3a7713b1edbc 603 * @}
AnnaBridge 171:3a7713b1edbc 604 */
AnnaBridge 171:3a7713b1edbc 605
AnnaBridge 171:3a7713b1edbc 606 /** @addtogroup ADC_Exported_Functions_Group3
AnnaBridge 171:3a7713b1edbc 607 * @{
AnnaBridge 171:3a7713b1edbc 608 */
AnnaBridge 171:3a7713b1edbc 609 /* Peripheral Control functions *************************************************/
AnnaBridge 171:3a7713b1edbc 610 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
AnnaBridge 171:3a7713b1edbc 611 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
AnnaBridge 171:3a7713b1edbc 612 /**
AnnaBridge 171:3a7713b1edbc 613 * @}
AnnaBridge 171:3a7713b1edbc 614 */
AnnaBridge 171:3a7713b1edbc 615
AnnaBridge 171:3a7713b1edbc 616 /** @addtogroup ADC_Exported_Functions_Group4
AnnaBridge 171:3a7713b1edbc 617 * @{
AnnaBridge 171:3a7713b1edbc 618 */
AnnaBridge 171:3a7713b1edbc 619 /* Peripheral State functions ***************************************************/
AnnaBridge 171:3a7713b1edbc 620 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 621 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
AnnaBridge 171:3a7713b1edbc 622 /**
AnnaBridge 171:3a7713b1edbc 623 * @}
AnnaBridge 171:3a7713b1edbc 624 */
AnnaBridge 171:3a7713b1edbc 625
AnnaBridge 171:3a7713b1edbc 626 /**
AnnaBridge 171:3a7713b1edbc 627 * @}
AnnaBridge 171:3a7713b1edbc 628 */
AnnaBridge 171:3a7713b1edbc 629
AnnaBridge 171:3a7713b1edbc 630 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 631 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 632 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 633 /** @defgroup ADC_Private_Constants ADC Private Constants
AnnaBridge 171:3a7713b1edbc 634 * @{
AnnaBridge 171:3a7713b1edbc 635 */
AnnaBridge 171:3a7713b1edbc 636 /* Delay for ADC stabilization time. */
AnnaBridge 171:3a7713b1edbc 637 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
AnnaBridge 171:3a7713b1edbc 638 /* Unit: us */
AnnaBridge 171:3a7713b1edbc 639 #define ADC_STAB_DELAY_US ((uint32_t) 3U)
AnnaBridge 171:3a7713b1edbc 640 /* Delay for temperature sensor stabilization time. */
AnnaBridge 171:3a7713b1edbc 641 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
AnnaBridge 171:3a7713b1edbc 642 /* Unit: us */
AnnaBridge 171:3a7713b1edbc 643 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
AnnaBridge 171:3a7713b1edbc 644 /**
AnnaBridge 171:3a7713b1edbc 645 * @}
AnnaBridge 171:3a7713b1edbc 646 */
AnnaBridge 171:3a7713b1edbc 647
AnnaBridge 171:3a7713b1edbc 648 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 649 /** @defgroup ADC_Private_Macros ADC Private Macros
AnnaBridge 171:3a7713b1edbc 650 * @{
AnnaBridge 171:3a7713b1edbc 651 */
AnnaBridge 171:3a7713b1edbc 652 /* Macro reserved for internal HAL driver usage, not intended to be used in
AnnaBridge 171:3a7713b1edbc 653 code of final user */
AnnaBridge 171:3a7713b1edbc 654
AnnaBridge 171:3a7713b1edbc 655 /**
AnnaBridge 171:3a7713b1edbc 656 * @brief Verification of ADC state: enabled or disabled
AnnaBridge 171:3a7713b1edbc 657 * @param __HANDLE__ ADC handle
AnnaBridge 171:3a7713b1edbc 658 * @retval SET (ADC enabled) or RESET (ADC disabled)
AnnaBridge 171:3a7713b1edbc 659 */
AnnaBridge 171:3a7713b1edbc 660 #define ADC_IS_ENABLE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 661 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
AnnaBridge 171:3a7713b1edbc 662 ) ? SET : RESET)
AnnaBridge 171:3a7713b1edbc 663
AnnaBridge 171:3a7713b1edbc 664 /**
AnnaBridge 171:3a7713b1edbc 665 * @brief Test if conversion trigger of regular group is software start
AnnaBridge 171:3a7713b1edbc 666 * or external trigger.
AnnaBridge 171:3a7713b1edbc 667 * @param __HANDLE__ ADC handle
AnnaBridge 171:3a7713b1edbc 668 * @retval SET (software start) or RESET (external trigger)
AnnaBridge 171:3a7713b1edbc 669 */
AnnaBridge 171:3a7713b1edbc 670 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 671 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
AnnaBridge 171:3a7713b1edbc 672
AnnaBridge 171:3a7713b1edbc 673 /**
AnnaBridge 171:3a7713b1edbc 674 * @brief Test if conversion trigger of injected group is software start
AnnaBridge 171:3a7713b1edbc 675 * or external trigger.
AnnaBridge 171:3a7713b1edbc 676 * @param __HANDLE__ ADC handle
AnnaBridge 171:3a7713b1edbc 677 * @retval SET (software start) or RESET (external trigger)
AnnaBridge 171:3a7713b1edbc 678 */
AnnaBridge 171:3a7713b1edbc 679 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 680 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
AnnaBridge 171:3a7713b1edbc 681
AnnaBridge 171:3a7713b1edbc 682 /**
AnnaBridge 171:3a7713b1edbc 683 * @brief Simultaneously clears and sets specific bits of the handle State
AnnaBridge 171:3a7713b1edbc 684 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
AnnaBridge 171:3a7713b1edbc 685 * the first parameter is the ADC handle State, the second parameter is the
AnnaBridge 171:3a7713b1edbc 686 * bit field to clear, the third and last parameter is the bit field to set.
AnnaBridge 171:3a7713b1edbc 687 * @retval None
AnnaBridge 171:3a7713b1edbc 688 */
AnnaBridge 171:3a7713b1edbc 689 #define ADC_STATE_CLR_SET MODIFY_REG
AnnaBridge 171:3a7713b1edbc 690
AnnaBridge 171:3a7713b1edbc 691 /**
AnnaBridge 171:3a7713b1edbc 692 * @brief Clear ADC error code (set it to error code: "no error")
AnnaBridge 171:3a7713b1edbc 693 * @param __HANDLE__ ADC handle
AnnaBridge 171:3a7713b1edbc 694 * @retval None
AnnaBridge 171:3a7713b1edbc 695 */
AnnaBridge 171:3a7713b1edbc 696 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 697 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
AnnaBridge 171:3a7713b1edbc 698 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
AnnaBridge 171:3a7713b1edbc 699 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
AnnaBridge 171:3a7713b1edbc 700 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
AnnaBridge 171:3a7713b1edbc 701 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))
AnnaBridge 171:3a7713b1edbc 702 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
AnnaBridge 171:3a7713b1edbc 703 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
AnnaBridge 171:3a7713b1edbc 704 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
AnnaBridge 171:3a7713b1edbc 705 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
AnnaBridge 171:3a7713b1edbc 706 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
AnnaBridge 171:3a7713b1edbc 707 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
AnnaBridge 171:3a7713b1edbc 708 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
AnnaBridge 171:3a7713b1edbc 709 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
AnnaBridge 171:3a7713b1edbc 710 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
AnnaBridge 171:3a7713b1edbc 711 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
AnnaBridge 171:3a7713b1edbc 712 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
AnnaBridge 171:3a7713b1edbc 713 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
AnnaBridge 171:3a7713b1edbc 714 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
AnnaBridge 171:3a7713b1edbc 715 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
AnnaBridge 171:3a7713b1edbc 716 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
AnnaBridge 171:3a7713b1edbc 717 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))
AnnaBridge 171:3a7713b1edbc 718 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
AnnaBridge 171:3a7713b1edbc 719 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
AnnaBridge 171:3a7713b1edbc 720 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
AnnaBridge 171:3a7713b1edbc 721 ((__RESOLUTION__) == ADC_RESOLUTION_6B))
AnnaBridge 171:3a7713b1edbc 722 #define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
AnnaBridge 171:3a7713b1edbc 723 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
AnnaBridge 171:3a7713b1edbc 724 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
AnnaBridge 171:3a7713b1edbc 725 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
AnnaBridge 171:3a7713b1edbc 726 #define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
AnnaBridge 171:3a7713b1edbc 727 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
AnnaBridge 171:3a7713b1edbc 728 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
AnnaBridge 171:3a7713b1edbc 729 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
AnnaBridge 171:3a7713b1edbc 730 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) || \
AnnaBridge 171:3a7713b1edbc 731 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
AnnaBridge 171:3a7713b1edbc 732 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
AnnaBridge 171:3a7713b1edbc 733 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
AnnaBridge 171:3a7713b1edbc 734 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
AnnaBridge 171:3a7713b1edbc 735 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
AnnaBridge 171:3a7713b1edbc 736 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
AnnaBridge 171:3a7713b1edbc 737 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
AnnaBridge 171:3a7713b1edbc 738 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
AnnaBridge 171:3a7713b1edbc 739 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
AnnaBridge 171:3a7713b1edbc 740 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
AnnaBridge 171:3a7713b1edbc 741 ((__REGTRIG__) == ADC_SOFTWARE_START))
AnnaBridge 171:3a7713b1edbc 742 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
AnnaBridge 171:3a7713b1edbc 743 ((__ALIGN__) == ADC_DATAALIGN_LEFT))
AnnaBridge 171:3a7713b1edbc 744
AnnaBridge 171:3a7713b1edbc 745
AnnaBridge 171:3a7713b1edbc 746 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \
AnnaBridge 171:3a7713b1edbc 747 ((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \
AnnaBridge 171:3a7713b1edbc 748 ((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \
AnnaBridge 171:3a7713b1edbc 749 ((__TIME__) == ADC_SAMPLETIME_56CYCLES) || \
AnnaBridge 171:3a7713b1edbc 750 ((__TIME__) == ADC_SAMPLETIME_84CYCLES) || \
AnnaBridge 171:3a7713b1edbc 751 ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \
AnnaBridge 171:3a7713b1edbc 752 ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \
AnnaBridge 171:3a7713b1edbc 753 ((__TIME__) == ADC_SAMPLETIME_480CYCLES))
AnnaBridge 171:3a7713b1edbc 754 #define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) || \
AnnaBridge 171:3a7713b1edbc 755 ((__EOCSelection__) == ADC_EOC_SEQ_CONV) || \
AnnaBridge 171:3a7713b1edbc 756 ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))
AnnaBridge 171:3a7713b1edbc 757 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \
AnnaBridge 171:3a7713b1edbc 758 ((__EVENT__) == ADC_OVR_EVENT))
AnnaBridge 171:3a7713b1edbc 759 #define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
AnnaBridge 171:3a7713b1edbc 760 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
AnnaBridge 171:3a7713b1edbc 761 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
AnnaBridge 171:3a7713b1edbc 762 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
AnnaBridge 171:3a7713b1edbc 763 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
AnnaBridge 171:3a7713b1edbc 764 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
AnnaBridge 171:3a7713b1edbc 765 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))
AnnaBridge 171:3a7713b1edbc 766 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
AnnaBridge 171:3a7713b1edbc 767 ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
AnnaBridge 171:3a7713b1edbc 768 ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
AnnaBridge 171:3a7713b1edbc 769
AnnaBridge 171:3a7713b1edbc 770 #define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \
AnnaBridge 171:3a7713b1edbc 771 ((__RANK__) == ADC_REGULAR_RANK_2 ) || \
AnnaBridge 171:3a7713b1edbc 772 ((__RANK__) == ADC_REGULAR_RANK_3 ) || \
AnnaBridge 171:3a7713b1edbc 773 ((__RANK__) == ADC_REGULAR_RANK_4 ) || \
AnnaBridge 171:3a7713b1edbc 774 ((__RANK__) == ADC_REGULAR_RANK_5 ) || \
AnnaBridge 171:3a7713b1edbc 775 ((__RANK__) == ADC_REGULAR_RANK_6 ) || \
AnnaBridge 171:3a7713b1edbc 776 ((__RANK__) == ADC_REGULAR_RANK_7 ) || \
AnnaBridge 171:3a7713b1edbc 777 ((__RANK__) == ADC_REGULAR_RANK_8 ) || \
AnnaBridge 171:3a7713b1edbc 778 ((__RANK__) == ADC_REGULAR_RANK_9 ) || \
AnnaBridge 171:3a7713b1edbc 779 ((__RANK__) == ADC_REGULAR_RANK_10) || \
AnnaBridge 171:3a7713b1edbc 780 ((__RANK__) == ADC_REGULAR_RANK_11) || \
AnnaBridge 171:3a7713b1edbc 781 ((__RANK__) == ADC_REGULAR_RANK_12) || \
AnnaBridge 171:3a7713b1edbc 782 ((__RANK__) == ADC_REGULAR_RANK_13) || \
AnnaBridge 171:3a7713b1edbc 783 ((__RANK__) == ADC_REGULAR_RANK_14) || \
AnnaBridge 171:3a7713b1edbc 784 ((__RANK__) == ADC_REGULAR_RANK_15) || \
AnnaBridge 171:3a7713b1edbc 785 ((__RANK__) == ADC_REGULAR_RANK_16))
AnnaBridge 171:3a7713b1edbc 786
AnnaBridge 171:3a7713b1edbc 787 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
AnnaBridge 171:3a7713b1edbc 788 ((__SCAN_MODE__) == ADC_SCAN_ENABLE))
AnnaBridge 171:3a7713b1edbc 789
AnnaBridge 171:3a7713b1edbc 790 #define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
AnnaBridge 171:3a7713b1edbc 791 #define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
AnnaBridge 171:3a7713b1edbc 792 #define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
AnnaBridge 171:3a7713b1edbc 793 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
AnnaBridge 171:3a7713b1edbc 794 ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
AnnaBridge 171:3a7713b1edbc 795 (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
AnnaBridge 171:3a7713b1edbc 796 (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
AnnaBridge 171:3a7713b1edbc 797 (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))
AnnaBridge 171:3a7713b1edbc 798
AnnaBridge 171:3a7713b1edbc 799 /**
AnnaBridge 171:3a7713b1edbc 800 * @brief Set ADC Regular channel sequence length.
AnnaBridge 171:3a7713b1edbc 801 * @param _NbrOfConversion_ Regular channel sequence length.
AnnaBridge 171:3a7713b1edbc 802 * @retval None
AnnaBridge 171:3a7713b1edbc 803 */
AnnaBridge 171:3a7713b1edbc 804 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
AnnaBridge 171:3a7713b1edbc 805
AnnaBridge 171:3a7713b1edbc 806 /**
AnnaBridge 171:3a7713b1edbc 807 * @brief Set the ADC's sample time for channel numbers between 10 and 18.
AnnaBridge 171:3a7713b1edbc 808 * @param _SAMPLETIME_ Sample time parameter.
AnnaBridge 171:3a7713b1edbc 809 * @param _CHANNELNB_ Channel number.
AnnaBridge 171:3a7713b1edbc 810 * @retval None
AnnaBridge 171:3a7713b1edbc 811 */
AnnaBridge 171:3a7713b1edbc 812 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
AnnaBridge 171:3a7713b1edbc 813
AnnaBridge 171:3a7713b1edbc 814 /**
AnnaBridge 171:3a7713b1edbc 815 * @brief Set the ADC's sample time for channel numbers between 0 and 9.
AnnaBridge 171:3a7713b1edbc 816 * @param _SAMPLETIME_ Sample time parameter.
AnnaBridge 171:3a7713b1edbc 817 * @param _CHANNELNB_ Channel number.
AnnaBridge 171:3a7713b1edbc 818 * @retval None
AnnaBridge 171:3a7713b1edbc 819 */
AnnaBridge 171:3a7713b1edbc 820 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
AnnaBridge 171:3a7713b1edbc 821
AnnaBridge 171:3a7713b1edbc 822 /**
AnnaBridge 171:3a7713b1edbc 823 * @brief Set the selected regular channel rank for rank between 1 and 6.
AnnaBridge 171:3a7713b1edbc 824 * @param _CHANNELNB_ Channel number.
AnnaBridge 171:3a7713b1edbc 825 * @param _RANKNB_ Rank number.
AnnaBridge 171:3a7713b1edbc 826 * @retval None
AnnaBridge 171:3a7713b1edbc 827 */
AnnaBridge 171:3a7713b1edbc 828 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
AnnaBridge 171:3a7713b1edbc 829
AnnaBridge 171:3a7713b1edbc 830 /**
AnnaBridge 171:3a7713b1edbc 831 * @brief Set the selected regular channel rank for rank between 7 and 12.
AnnaBridge 171:3a7713b1edbc 832 * @param _CHANNELNB_ Channel number.
AnnaBridge 171:3a7713b1edbc 833 * @param _RANKNB_ Rank number.
AnnaBridge 171:3a7713b1edbc 834 * @retval None
AnnaBridge 171:3a7713b1edbc 835 */
AnnaBridge 171:3a7713b1edbc 836 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
AnnaBridge 171:3a7713b1edbc 837
AnnaBridge 171:3a7713b1edbc 838 /**
AnnaBridge 171:3a7713b1edbc 839 * @brief Set the selected regular channel rank for rank between 13 and 16.
AnnaBridge 171:3a7713b1edbc 840 * @param _CHANNELNB_ Channel number.
AnnaBridge 171:3a7713b1edbc 841 * @param _RANKNB_ Rank number.
AnnaBridge 171:3a7713b1edbc 842 * @retval None
AnnaBridge 171:3a7713b1edbc 843 */
AnnaBridge 171:3a7713b1edbc 844 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
AnnaBridge 171:3a7713b1edbc 845
AnnaBridge 171:3a7713b1edbc 846 /**
AnnaBridge 171:3a7713b1edbc 847 * @brief Enable ADC continuous conversion mode.
AnnaBridge 171:3a7713b1edbc 848 * @param _CONTINUOUS_MODE_ Continuous mode.
AnnaBridge 171:3a7713b1edbc 849 * @retval None
AnnaBridge 171:3a7713b1edbc 850 */
AnnaBridge 171:3a7713b1edbc 851 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
AnnaBridge 171:3a7713b1edbc 852
AnnaBridge 171:3a7713b1edbc 853 /**
AnnaBridge 171:3a7713b1edbc 854 * @brief Configures the number of discontinuous conversions for the regular group channels.
AnnaBridge 171:3a7713b1edbc 855 * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions.
AnnaBridge 171:3a7713b1edbc 856 * @retval None
AnnaBridge 171:3a7713b1edbc 857 */
AnnaBridge 171:3a7713b1edbc 858 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << ADC_CR1_DISCNUM_Pos)
AnnaBridge 171:3a7713b1edbc 859
AnnaBridge 171:3a7713b1edbc 860 /**
AnnaBridge 171:3a7713b1edbc 861 * @brief Enable ADC scan mode.
AnnaBridge 171:3a7713b1edbc 862 * @param _SCANCONV_MODE_ Scan conversion mode.
AnnaBridge 171:3a7713b1edbc 863 * @retval None
AnnaBridge 171:3a7713b1edbc 864 */
AnnaBridge 171:3a7713b1edbc 865 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
AnnaBridge 171:3a7713b1edbc 866
AnnaBridge 171:3a7713b1edbc 867 /**
AnnaBridge 171:3a7713b1edbc 868 * @brief Enable the ADC end of conversion selection.
AnnaBridge 171:3a7713b1edbc 869 * @param _EOCSelection_MODE_ End of conversion selection mode.
AnnaBridge 171:3a7713b1edbc 870 * @retval None
AnnaBridge 171:3a7713b1edbc 871 */
AnnaBridge 171:3a7713b1edbc 872 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
AnnaBridge 171:3a7713b1edbc 873
AnnaBridge 171:3a7713b1edbc 874 /**
AnnaBridge 171:3a7713b1edbc 875 * @brief Enable the ADC DMA continuous request.
AnnaBridge 171:3a7713b1edbc 876 * @param _DMAContReq_MODE_ DMA continuous request mode.
AnnaBridge 171:3a7713b1edbc 877 * @retval None
AnnaBridge 171:3a7713b1edbc 878 */
AnnaBridge 171:3a7713b1edbc 879 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
AnnaBridge 171:3a7713b1edbc 880
AnnaBridge 171:3a7713b1edbc 881 /**
AnnaBridge 171:3a7713b1edbc 882 * @brief Return resolution bits in CR1 register.
AnnaBridge 171:3a7713b1edbc 883 * @param __HANDLE__ ADC handle
AnnaBridge 171:3a7713b1edbc 884 * @retval None
AnnaBridge 171:3a7713b1edbc 885 */
AnnaBridge 171:3a7713b1edbc 886 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
AnnaBridge 171:3a7713b1edbc 887
AnnaBridge 171:3a7713b1edbc 888 /**
AnnaBridge 171:3a7713b1edbc 889 * @}
AnnaBridge 171:3a7713b1edbc 890 */
AnnaBridge 171:3a7713b1edbc 891
AnnaBridge 171:3a7713b1edbc 892 /* Private functions ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 893 /** @defgroup ADC_Private_Functions ADC Private Functions
AnnaBridge 171:3a7713b1edbc 894 * @{
AnnaBridge 171:3a7713b1edbc 895 */
AnnaBridge 171:3a7713b1edbc 896
AnnaBridge 171:3a7713b1edbc 897 /**
AnnaBridge 171:3a7713b1edbc 898 * @}
AnnaBridge 171:3a7713b1edbc 899 */
AnnaBridge 171:3a7713b1edbc 900
AnnaBridge 171:3a7713b1edbc 901 /**
AnnaBridge 171:3a7713b1edbc 902 * @}
AnnaBridge 171:3a7713b1edbc 903 */
AnnaBridge 171:3a7713b1edbc 904
AnnaBridge 171:3a7713b1edbc 905 /**
AnnaBridge 171:3a7713b1edbc 906 * @}
AnnaBridge 171:3a7713b1edbc 907 */
AnnaBridge 171:3a7713b1edbc 908
AnnaBridge 171:3a7713b1edbc 909 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 910 }
AnnaBridge 171:3a7713b1edbc 911 #endif
AnnaBridge 171:3a7713b1edbc 912
AnnaBridge 171:3a7713b1edbc 913 #endif /*__STM32F7xx_ADC_H */
AnnaBridge 171:3a7713b1edbc 914
AnnaBridge 171:3a7713b1edbc 915
AnnaBridge 171:3a7713b1edbc 916 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/