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TARGET_DISCO_F746NG/TOOLCHAIN_IAR/stm32f7xx_ll_bus.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_ll_bus.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of BUS LL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | |
| AnnaBridge | 171:3a7713b1edbc | 7 | @verbatim |
| AnnaBridge | 171:3a7713b1edbc | 8 | ##### RCC Limitations ##### |
| AnnaBridge | 171:3a7713b1edbc | 9 | ============================================================================== |
| AnnaBridge | 171:3a7713b1edbc | 10 | [..] |
| AnnaBridge | 171:3a7713b1edbc | 11 | A delay between an RCC peripheral clock enable and the effective peripheral |
| AnnaBridge | 171:3a7713b1edbc | 12 | enabling should be taken into account in order to manage the peripheral read/write |
| AnnaBridge | 171:3a7713b1edbc | 13 | from/to registers. |
| AnnaBridge | 171:3a7713b1edbc | 14 | (+) This delay depends on the peripheral mapping. |
| AnnaBridge | 171:3a7713b1edbc | 15 | (++) AHB & APB peripherals, 1 dummy read is necessary |
| AnnaBridge | 171:3a7713b1edbc | 16 | |
| AnnaBridge | 171:3a7713b1edbc | 17 | [..] |
| AnnaBridge | 171:3a7713b1edbc | 18 | Workarounds: |
| AnnaBridge | 171:3a7713b1edbc | 19 | (#) For AHB & APB peripherals, a dummy read to the peripheral register has been |
| AnnaBridge | 171:3a7713b1edbc | 20 | inserted in each LL_{BUS}_GRP{x}_EnableClock() function. |
| AnnaBridge | 171:3a7713b1edbc | 21 | |
| AnnaBridge | 171:3a7713b1edbc | 22 | @endverbatim |
| AnnaBridge | 171:3a7713b1edbc | 23 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 24 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 25 | * |
| AnnaBridge | 171:3a7713b1edbc | 26 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 27 | * |
| AnnaBridge | 171:3a7713b1edbc | 28 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 29 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 30 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 31 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 33 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 34 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 35 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 36 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 37 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 38 | * |
| AnnaBridge | 171:3a7713b1edbc | 39 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 40 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 41 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 42 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 43 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 44 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 45 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 46 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 47 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 48 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 49 | * |
| AnnaBridge | 171:3a7713b1edbc | 50 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 51 | */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | |
| AnnaBridge | 171:3a7713b1edbc | 53 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 54 | #ifndef __STM32F7xx_LL_BUS_H |
| AnnaBridge | 171:3a7713b1edbc | 55 | #define __STM32F7xx_LL_BUS_H |
| AnnaBridge | 171:3a7713b1edbc | 56 | |
| AnnaBridge | 171:3a7713b1edbc | 57 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 58 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 59 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 60 | |
| AnnaBridge | 171:3a7713b1edbc | 61 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 62 | #include "stm32f7xx.h" |
| AnnaBridge | 171:3a7713b1edbc | 63 | |
| AnnaBridge | 171:3a7713b1edbc | 64 | /** @addtogroup STM32F7xx_LL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 65 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 66 | */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | |
| AnnaBridge | 171:3a7713b1edbc | 68 | #if defined(RCC) |
| AnnaBridge | 171:3a7713b1edbc | 69 | |
| AnnaBridge | 171:3a7713b1edbc | 70 | /** @defgroup BUS_LL BUS |
| AnnaBridge | 171:3a7713b1edbc | 71 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 72 | */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | |
| AnnaBridge | 171:3a7713b1edbc | 74 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 75 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 76 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 77 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 78 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 79 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 80 | /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 81 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 82 | */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | |
| AnnaBridge | 171:3a7713b1edbc | 84 | /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH |
| AnnaBridge | 171:3a7713b1edbc | 85 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 86 | */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 171:3a7713b1edbc | 88 | #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN |
| AnnaBridge | 171:3a7713b1edbc | 89 | #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN |
| AnnaBridge | 171:3a7713b1edbc | 90 | #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN |
| AnnaBridge | 171:3a7713b1edbc | 91 | #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN |
| AnnaBridge | 171:3a7713b1edbc | 92 | #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN |
| AnnaBridge | 171:3a7713b1edbc | 97 | #if defined(GPIOJ) |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN |
| AnnaBridge | 171:3a7713b1edbc | 99 | #endif /* GPIOJ */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | #if defined(GPIOK) |
| AnnaBridge | 171:3a7713b1edbc | 101 | #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN |
| AnnaBridge | 171:3a7713b1edbc | 102 | #endif /* GPIOK */ |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN |
| AnnaBridge | 171:3a7713b1edbc | 108 | #if defined(DMA2D) |
| AnnaBridge | 171:3a7713b1edbc | 109 | #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN |
| AnnaBridge | 171:3a7713b1edbc | 110 | #endif /* DMA2D */ |
| AnnaBridge | 171:3a7713b1edbc | 111 | #if defined(ETH) |
| AnnaBridge | 171:3a7713b1edbc | 112 | #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN |
| AnnaBridge | 171:3a7713b1edbc | 116 | #endif /* ETH */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN |
| AnnaBridge | 171:3a7713b1edbc | 123 | /** |
| AnnaBridge | 171:3a7713b1edbc | 124 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 125 | */ |
| AnnaBridge | 171:3a7713b1edbc | 126 | |
| AnnaBridge | 171:3a7713b1edbc | 127 | /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH |
| AnnaBridge | 171:3a7713b1edbc | 128 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 129 | */ |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 171:3a7713b1edbc | 131 | #if defined(DCMI) |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN |
| AnnaBridge | 171:3a7713b1edbc | 133 | #endif /* DCMI */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | #if defined(JPEG) |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN |
| AnnaBridge | 171:3a7713b1edbc | 136 | #endif /* JPEG */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | #if defined(CRYP) |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN |
| AnnaBridge | 171:3a7713b1edbc | 139 | #endif /* CRYP */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #if defined(AES) |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN |
| AnnaBridge | 171:3a7713b1edbc | 142 | #endif /* AES */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #if defined(HASH) |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN |
| AnnaBridge | 171:3a7713b1edbc | 145 | #endif /* HASH */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN |
| AnnaBridge | 171:3a7713b1edbc | 148 | /** |
| AnnaBridge | 171:3a7713b1edbc | 149 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 150 | */ |
| AnnaBridge | 171:3a7713b1edbc | 151 | |
| AnnaBridge | 171:3a7713b1edbc | 152 | /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH |
| AnnaBridge | 171:3a7713b1edbc | 153 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 154 | */ |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN |
| AnnaBridge | 171:3a7713b1edbc | 158 | /** |
| AnnaBridge | 171:3a7713b1edbc | 159 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 160 | */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | |
| AnnaBridge | 171:3a7713b1edbc | 162 | /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH |
| AnnaBridge | 171:3a7713b1edbc | 163 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 164 | */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN |
| AnnaBridge | 171:3a7713b1edbc | 178 | #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN |
| AnnaBridge | 171:3a7713b1edbc | 179 | #if defined(SPDIFRX) |
| AnnaBridge | 171:3a7713b1edbc | 180 | #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN |
| AnnaBridge | 171:3a7713b1edbc | 181 | #endif /* SPDIFRX */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN |
| AnnaBridge | 171:3a7713b1edbc | 189 | #if defined(I2C4) |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN |
| AnnaBridge | 171:3a7713b1edbc | 191 | #endif /* I2C4 */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN |
| AnnaBridge | 171:3a7713b1edbc | 193 | #if defined(CAN2) |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN |
| AnnaBridge | 171:3a7713b1edbc | 195 | #endif /* CAN2 */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | #if defined(CAN3) |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN |
| AnnaBridge | 171:3a7713b1edbc | 198 | #endif /* CAN3 */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | #if defined(CEC) |
| AnnaBridge | 171:3a7713b1edbc | 200 | #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN |
| AnnaBridge | 171:3a7713b1edbc | 201 | #endif /* CEC */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN |
| AnnaBridge | 171:3a7713b1edbc | 206 | #if defined(RCC_APB1ENR_RTCEN) |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN |
| AnnaBridge | 171:3a7713b1edbc | 208 | #endif /* RCC_APB1ENR_RTCEN */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | /** |
| AnnaBridge | 171:3a7713b1edbc | 210 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 211 | */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | |
| AnnaBridge | 171:3a7713b1edbc | 213 | /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH |
| AnnaBridge | 171:3a7713b1edbc | 214 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 215 | */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN |
| AnnaBridge | 171:3a7713b1edbc | 218 | #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN |
| AnnaBridge | 171:3a7713b1edbc | 219 | #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN |
| AnnaBridge | 171:3a7713b1edbc | 223 | #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN |
| AnnaBridge | 171:3a7713b1edbc | 224 | #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN |
| AnnaBridge | 171:3a7713b1edbc | 225 | #if defined(SDMMC2) |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN |
| AnnaBridge | 171:3a7713b1edbc | 227 | #endif /* SDMMC2 */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN |
| AnnaBridge | 171:3a7713b1edbc | 235 | #if defined(SPI6) |
| AnnaBridge | 171:3a7713b1edbc | 236 | #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN |
| AnnaBridge | 171:3a7713b1edbc | 237 | #endif /* SPI6 */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN |
| AnnaBridge | 171:3a7713b1edbc | 240 | #if defined(LTDC) |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN |
| AnnaBridge | 171:3a7713b1edbc | 242 | #endif /* LTDC */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | #if defined(DSI) |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN |
| AnnaBridge | 171:3a7713b1edbc | 245 | #endif /* DSI */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | #if defined(DFSDM1_Channel0) |
| AnnaBridge | 171:3a7713b1edbc | 247 | #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN |
| AnnaBridge | 171:3a7713b1edbc | 248 | #endif /* DFSDM1_Channel0 */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | #if defined(MDIOS) |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN |
| AnnaBridge | 171:3a7713b1edbc | 251 | #endif /* MDIOS */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #if defined(USB_HS_PHYC) |
| AnnaBridge | 171:3a7713b1edbc | 253 | #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN |
| AnnaBridge | 171:3a7713b1edbc | 254 | #endif /* USB_HS_PHYC */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST |
| AnnaBridge | 171:3a7713b1edbc | 256 | /** |
| AnnaBridge | 171:3a7713b1edbc | 257 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 258 | */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | |
| AnnaBridge | 171:3a7713b1edbc | 260 | /** |
| AnnaBridge | 171:3a7713b1edbc | 261 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 262 | */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | |
| AnnaBridge | 171:3a7713b1edbc | 264 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 265 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 266 | /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions |
| AnnaBridge | 171:3a7713b1edbc | 267 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 268 | */ |
| AnnaBridge | 171:3a7713b1edbc | 269 | |
| AnnaBridge | 171:3a7713b1edbc | 270 | /** @defgroup BUS_LL_EF_AHB1 AHB1 |
| AnnaBridge | 171:3a7713b1edbc | 271 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 272 | */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | |
| AnnaBridge | 171:3a7713b1edbc | 274 | /** |
| AnnaBridge | 171:3a7713b1edbc | 275 | * @brief Enable AHB1 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 276 | * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 277 | * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 278 | * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 279 | * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 280 | * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 281 | * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 282 | * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 283 | * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 284 | * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 285 | * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 286 | * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 287 | * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 288 | * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 289 | * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 290 | * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 291 | * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 292 | * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 293 | * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 294 | * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 295 | * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 296 | * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 297 | * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 298 | * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock |
| AnnaBridge | 171:3a7713b1edbc | 299 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 300 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 301 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 302 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 303 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 304 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 171:3a7713b1edbc | 305 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 171:3a7713b1edbc | 306 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 171:3a7713b1edbc | 307 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 308 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 171:3a7713b1edbc | 309 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| AnnaBridge | 171:3a7713b1edbc | 310 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| AnnaBridge | 171:3a7713b1edbc | 311 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 312 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM |
| AnnaBridge | 171:3a7713b1edbc | 313 | * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM |
| AnnaBridge | 171:3a7713b1edbc | 314 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 315 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 171:3a7713b1edbc | 316 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 171:3a7713b1edbc | 317 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 171:3a7713b1edbc | 318 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| AnnaBridge | 171:3a7713b1edbc | 319 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| AnnaBridge | 171:3a7713b1edbc | 320 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| AnnaBridge | 171:3a7713b1edbc | 321 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 171:3a7713b1edbc | 322 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI |
| AnnaBridge | 171:3a7713b1edbc | 323 | * |
| AnnaBridge | 171:3a7713b1edbc | 324 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 325 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 326 | */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 328 | { |
| AnnaBridge | 171:3a7713b1edbc | 329 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 330 | SET_BIT(RCC->AHB1ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 331 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 333 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 334 | } |
| AnnaBridge | 171:3a7713b1edbc | 335 | |
| AnnaBridge | 171:3a7713b1edbc | 336 | /** |
| AnnaBridge | 171:3a7713b1edbc | 337 | * @brief Check if AHB1 peripheral clock is enabled or not |
| AnnaBridge | 171:3a7713b1edbc | 338 | * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 339 | * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 340 | * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 341 | * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 342 | * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 343 | * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 344 | * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 345 | * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 346 | * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 347 | * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 348 | * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 349 | * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 350 | * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 351 | * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 352 | * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 353 | * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 354 | * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 355 | * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 356 | * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 357 | * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 358 | * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 359 | * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 360 | * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock |
| AnnaBridge | 171:3a7713b1edbc | 361 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 362 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 363 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 364 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 365 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 366 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 171:3a7713b1edbc | 367 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 171:3a7713b1edbc | 368 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 171:3a7713b1edbc | 369 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 370 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 171:3a7713b1edbc | 371 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| AnnaBridge | 171:3a7713b1edbc | 372 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| AnnaBridge | 171:3a7713b1edbc | 373 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 374 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM |
| AnnaBridge | 171:3a7713b1edbc | 375 | * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM |
| AnnaBridge | 171:3a7713b1edbc | 376 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 377 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 171:3a7713b1edbc | 378 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 171:3a7713b1edbc | 379 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 171:3a7713b1edbc | 380 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| AnnaBridge | 171:3a7713b1edbc | 381 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| AnnaBridge | 171:3a7713b1edbc | 382 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| AnnaBridge | 171:3a7713b1edbc | 383 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 171:3a7713b1edbc | 384 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI |
| AnnaBridge | 171:3a7713b1edbc | 385 | * |
| AnnaBridge | 171:3a7713b1edbc | 386 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 387 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 388 | */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 390 | { |
| AnnaBridge | 171:3a7713b1edbc | 391 | return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 392 | } |
| AnnaBridge | 171:3a7713b1edbc | 393 | |
| AnnaBridge | 171:3a7713b1edbc | 394 | /** |
| AnnaBridge | 171:3a7713b1edbc | 395 | * @brief Disable AHB1 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 396 | * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 397 | * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 398 | * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 399 | * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 400 | * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 401 | * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 402 | * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 403 | * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 404 | * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 405 | * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 406 | * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 407 | * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 408 | * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 409 | * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 410 | * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 411 | * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 412 | * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 413 | * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 414 | * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 415 | * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 416 | * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 417 | * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 418 | * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock |
| AnnaBridge | 171:3a7713b1edbc | 419 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 420 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 421 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 422 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 423 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 424 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 171:3a7713b1edbc | 425 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 171:3a7713b1edbc | 426 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 171:3a7713b1edbc | 427 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 428 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 171:3a7713b1edbc | 429 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| AnnaBridge | 171:3a7713b1edbc | 430 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| AnnaBridge | 171:3a7713b1edbc | 431 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 432 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM |
| AnnaBridge | 171:3a7713b1edbc | 433 | * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM |
| AnnaBridge | 171:3a7713b1edbc | 434 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 435 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 171:3a7713b1edbc | 436 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 171:3a7713b1edbc | 437 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 171:3a7713b1edbc | 438 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| AnnaBridge | 171:3a7713b1edbc | 439 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| AnnaBridge | 171:3a7713b1edbc | 440 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| AnnaBridge | 171:3a7713b1edbc | 441 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 171:3a7713b1edbc | 442 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI |
| AnnaBridge | 171:3a7713b1edbc | 443 | * |
| AnnaBridge | 171:3a7713b1edbc | 444 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 445 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 446 | */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 448 | { |
| AnnaBridge | 171:3a7713b1edbc | 449 | CLEAR_BIT(RCC->AHB1ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 450 | } |
| AnnaBridge | 171:3a7713b1edbc | 451 | |
| AnnaBridge | 171:3a7713b1edbc | 452 | /** |
| AnnaBridge | 171:3a7713b1edbc | 453 | * @brief Force AHB1 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 454 | * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 455 | * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 456 | * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 457 | * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 458 | * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 459 | * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 460 | * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 461 | * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 462 | * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 463 | * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 464 | * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 465 | * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 466 | * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 467 | * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 468 | * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 469 | * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 470 | * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset |
| AnnaBridge | 171:3a7713b1edbc | 471 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 472 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 473 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 474 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 475 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 476 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 477 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 171:3a7713b1edbc | 478 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 171:3a7713b1edbc | 479 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 171:3a7713b1edbc | 480 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 481 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 171:3a7713b1edbc | 482 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| AnnaBridge | 171:3a7713b1edbc | 483 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| AnnaBridge | 171:3a7713b1edbc | 484 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 485 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 486 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 171:3a7713b1edbc | 487 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 171:3a7713b1edbc | 488 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 171:3a7713b1edbc | 489 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 171:3a7713b1edbc | 490 | * |
| AnnaBridge | 171:3a7713b1edbc | 491 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 492 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 493 | */ |
| AnnaBridge | 171:3a7713b1edbc | 494 | __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 495 | { |
| AnnaBridge | 171:3a7713b1edbc | 496 | SET_BIT(RCC->AHB1RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 497 | } |
| AnnaBridge | 171:3a7713b1edbc | 498 | |
| AnnaBridge | 171:3a7713b1edbc | 499 | /** |
| AnnaBridge | 171:3a7713b1edbc | 500 | * @brief Release AHB1 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 501 | * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 502 | * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 503 | * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 504 | * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 505 | * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 506 | * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 507 | * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 508 | * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 509 | * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 510 | * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 511 | * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 512 | * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 513 | * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 514 | * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 515 | * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 516 | * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 517 | * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset |
| AnnaBridge | 171:3a7713b1edbc | 518 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 519 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 520 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 521 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 522 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 523 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 524 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 171:3a7713b1edbc | 525 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 171:3a7713b1edbc | 526 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 171:3a7713b1edbc | 527 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 528 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 171:3a7713b1edbc | 529 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| AnnaBridge | 171:3a7713b1edbc | 530 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| AnnaBridge | 171:3a7713b1edbc | 531 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 532 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 533 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 171:3a7713b1edbc | 534 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 171:3a7713b1edbc | 535 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 171:3a7713b1edbc | 536 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 171:3a7713b1edbc | 537 | * |
| AnnaBridge | 171:3a7713b1edbc | 538 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 539 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 540 | */ |
| AnnaBridge | 171:3a7713b1edbc | 541 | __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 542 | { |
| AnnaBridge | 171:3a7713b1edbc | 543 | CLEAR_BIT(RCC->AHB1RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 544 | } |
| AnnaBridge | 171:3a7713b1edbc | 545 | |
| AnnaBridge | 171:3a7713b1edbc | 546 | /** |
| AnnaBridge | 171:3a7713b1edbc | 547 | * @brief Enable AHB1 peripheral clocks in low-power mode |
| AnnaBridge | 171:3a7713b1edbc | 548 | * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 549 | * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 550 | * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 551 | * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 552 | * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 553 | * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 554 | * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 555 | * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 556 | * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 557 | * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 558 | * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 559 | * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 560 | * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 561 | * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 562 | * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 563 | * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 564 | * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 565 | * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 566 | * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 567 | * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 568 | * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 569 | * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 570 | * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 571 | * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 572 | * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 573 | * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 574 | * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower |
| AnnaBridge | 171:3a7713b1edbc | 575 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 576 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 577 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 578 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 579 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 580 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 171:3a7713b1edbc | 581 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 171:3a7713b1edbc | 582 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 171:3a7713b1edbc | 583 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 584 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 171:3a7713b1edbc | 585 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| AnnaBridge | 171:3a7713b1edbc | 586 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| AnnaBridge | 171:3a7713b1edbc | 587 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 588 | * @arg @ref LL_AHB1_GRP1_PERIPH_AXI |
| AnnaBridge | 171:3a7713b1edbc | 589 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF |
| AnnaBridge | 171:3a7713b1edbc | 590 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 |
| AnnaBridge | 171:3a7713b1edbc | 591 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 |
| AnnaBridge | 171:3a7713b1edbc | 592 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM |
| AnnaBridge | 171:3a7713b1edbc | 593 | * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM |
| AnnaBridge | 171:3a7713b1edbc | 594 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 595 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 171:3a7713b1edbc | 596 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 171:3a7713b1edbc | 597 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 171:3a7713b1edbc | 598 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| AnnaBridge | 171:3a7713b1edbc | 599 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| AnnaBridge | 171:3a7713b1edbc | 600 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| AnnaBridge | 171:3a7713b1edbc | 601 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 171:3a7713b1edbc | 602 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI |
| AnnaBridge | 171:3a7713b1edbc | 603 | * |
| AnnaBridge | 171:3a7713b1edbc | 604 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 605 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 606 | */ |
| AnnaBridge | 171:3a7713b1edbc | 607 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 608 | { |
| AnnaBridge | 171:3a7713b1edbc | 609 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 610 | SET_BIT(RCC->AHB1LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 611 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 612 | tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 613 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 614 | } |
| AnnaBridge | 171:3a7713b1edbc | 615 | |
| AnnaBridge | 171:3a7713b1edbc | 616 | /** |
| AnnaBridge | 171:3a7713b1edbc | 617 | * @brief Disable AHB1 peripheral clocks in low-power mode |
| AnnaBridge | 171:3a7713b1edbc | 618 | * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 619 | * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 620 | * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 621 | * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 622 | * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 623 | * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 624 | * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 625 | * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 626 | * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 627 | * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 628 | * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 629 | * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 630 | * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 631 | * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 632 | * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 633 | * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 634 | * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 635 | * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 636 | * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 637 | * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 638 | * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 639 | * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 640 | * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 641 | * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 642 | * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 643 | * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 644 | * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower |
| AnnaBridge | 171:3a7713b1edbc | 645 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 646 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 647 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 648 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 649 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 650 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE |
| AnnaBridge | 171:3a7713b1edbc | 651 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 171:3a7713b1edbc | 652 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG |
| AnnaBridge | 171:3a7713b1edbc | 653 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 654 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI |
| AnnaBridge | 171:3a7713b1edbc | 655 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) |
| AnnaBridge | 171:3a7713b1edbc | 656 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) |
| AnnaBridge | 171:3a7713b1edbc | 657 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 658 | * @arg @ref LL_AHB1_GRP1_PERIPH_AXI |
| AnnaBridge | 171:3a7713b1edbc | 659 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF |
| AnnaBridge | 171:3a7713b1edbc | 660 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 |
| AnnaBridge | 171:3a7713b1edbc | 661 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 |
| AnnaBridge | 171:3a7713b1edbc | 662 | * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM |
| AnnaBridge | 171:3a7713b1edbc | 663 | * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM |
| AnnaBridge | 171:3a7713b1edbc | 664 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 665 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 171:3a7713b1edbc | 666 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 171:3a7713b1edbc | 667 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) |
| AnnaBridge | 171:3a7713b1edbc | 668 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) |
| AnnaBridge | 171:3a7713b1edbc | 669 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) |
| AnnaBridge | 171:3a7713b1edbc | 670 | * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) |
| AnnaBridge | 171:3a7713b1edbc | 671 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS |
| AnnaBridge | 171:3a7713b1edbc | 672 | * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI |
| AnnaBridge | 171:3a7713b1edbc | 673 | * |
| AnnaBridge | 171:3a7713b1edbc | 674 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 675 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 676 | */ |
| AnnaBridge | 171:3a7713b1edbc | 677 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 678 | { |
| AnnaBridge | 171:3a7713b1edbc | 679 | CLEAR_BIT(RCC->AHB1LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 680 | } |
| AnnaBridge | 171:3a7713b1edbc | 681 | |
| AnnaBridge | 171:3a7713b1edbc | 682 | /** |
| AnnaBridge | 171:3a7713b1edbc | 683 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 684 | */ |
| AnnaBridge | 171:3a7713b1edbc | 685 | |
| AnnaBridge | 171:3a7713b1edbc | 686 | /** @defgroup BUS_LL_EF_AHB2 AHB2 |
| AnnaBridge | 171:3a7713b1edbc | 687 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 688 | */ |
| AnnaBridge | 171:3a7713b1edbc | 689 | |
| AnnaBridge | 171:3a7713b1edbc | 690 | /** |
| AnnaBridge | 171:3a7713b1edbc | 691 | * @brief Enable AHB2 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 692 | * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 693 | * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 694 | * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 695 | * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 696 | * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 697 | * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 698 | * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock |
| AnnaBridge | 171:3a7713b1edbc | 699 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 700 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 171:3a7713b1edbc | 701 | * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) |
| AnnaBridge | 171:3a7713b1edbc | 702 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 703 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 171:3a7713b1edbc | 704 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 171:3a7713b1edbc | 705 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 171:3a7713b1edbc | 706 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 171:3a7713b1edbc | 707 | * |
| AnnaBridge | 171:3a7713b1edbc | 708 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 709 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 710 | */ |
| AnnaBridge | 171:3a7713b1edbc | 711 | __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 712 | { |
| AnnaBridge | 171:3a7713b1edbc | 713 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 714 | SET_BIT(RCC->AHB2ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 715 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 716 | tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 717 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 718 | } |
| AnnaBridge | 171:3a7713b1edbc | 719 | |
| AnnaBridge | 171:3a7713b1edbc | 720 | /** |
| AnnaBridge | 171:3a7713b1edbc | 721 | * @brief Check if AHB2 peripheral clock is enabled or not |
| AnnaBridge | 171:3a7713b1edbc | 722 | * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 723 | * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 724 | * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 725 | * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 726 | * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 727 | * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 728 | * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock |
| AnnaBridge | 171:3a7713b1edbc | 729 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 730 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 171:3a7713b1edbc | 731 | * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) |
| AnnaBridge | 171:3a7713b1edbc | 732 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 733 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 171:3a7713b1edbc | 734 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 171:3a7713b1edbc | 735 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 171:3a7713b1edbc | 736 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 171:3a7713b1edbc | 737 | * |
| AnnaBridge | 171:3a7713b1edbc | 738 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 739 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 740 | */ |
| AnnaBridge | 171:3a7713b1edbc | 741 | __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 742 | { |
| AnnaBridge | 171:3a7713b1edbc | 743 | return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 744 | } |
| AnnaBridge | 171:3a7713b1edbc | 745 | |
| AnnaBridge | 171:3a7713b1edbc | 746 | /** |
| AnnaBridge | 171:3a7713b1edbc | 747 | * @brief Disable AHB2 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 748 | * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 749 | * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 750 | * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 751 | * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 752 | * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 753 | * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 754 | * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock |
| AnnaBridge | 171:3a7713b1edbc | 755 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 756 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 171:3a7713b1edbc | 757 | * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) |
| AnnaBridge | 171:3a7713b1edbc | 758 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 759 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 171:3a7713b1edbc | 760 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 171:3a7713b1edbc | 761 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 171:3a7713b1edbc | 762 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 171:3a7713b1edbc | 763 | * |
| AnnaBridge | 171:3a7713b1edbc | 764 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 765 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 766 | */ |
| AnnaBridge | 171:3a7713b1edbc | 767 | __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 768 | { |
| AnnaBridge | 171:3a7713b1edbc | 769 | CLEAR_BIT(RCC->AHB2ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 770 | } |
| AnnaBridge | 171:3a7713b1edbc | 771 | |
| AnnaBridge | 171:3a7713b1edbc | 772 | /** |
| AnnaBridge | 171:3a7713b1edbc | 773 | * @brief Force AHB2 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 774 | * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 775 | * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 776 | * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 777 | * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 778 | * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 779 | * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 780 | * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset |
| AnnaBridge | 171:3a7713b1edbc | 781 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 782 | * @arg @ref LL_AHB2_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 783 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 171:3a7713b1edbc | 784 | * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) |
| AnnaBridge | 171:3a7713b1edbc | 785 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 786 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 171:3a7713b1edbc | 787 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 171:3a7713b1edbc | 788 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 171:3a7713b1edbc | 789 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 171:3a7713b1edbc | 790 | * |
| AnnaBridge | 171:3a7713b1edbc | 791 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 792 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 793 | */ |
| AnnaBridge | 171:3a7713b1edbc | 794 | __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 795 | { |
| AnnaBridge | 171:3a7713b1edbc | 796 | SET_BIT(RCC->AHB2RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 797 | } |
| AnnaBridge | 171:3a7713b1edbc | 798 | |
| AnnaBridge | 171:3a7713b1edbc | 799 | /** |
| AnnaBridge | 171:3a7713b1edbc | 800 | * @brief Release AHB2 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 801 | * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 802 | * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 803 | * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 804 | * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 805 | * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 806 | * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 807 | * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset |
| AnnaBridge | 171:3a7713b1edbc | 808 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 809 | * @arg @ref LL_AHB2_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 810 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 171:3a7713b1edbc | 811 | * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) |
| AnnaBridge | 171:3a7713b1edbc | 812 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 813 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 171:3a7713b1edbc | 814 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 171:3a7713b1edbc | 815 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 171:3a7713b1edbc | 816 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 171:3a7713b1edbc | 817 | * |
| AnnaBridge | 171:3a7713b1edbc | 818 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 819 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 820 | */ |
| AnnaBridge | 171:3a7713b1edbc | 821 | __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 822 | { |
| AnnaBridge | 171:3a7713b1edbc | 823 | CLEAR_BIT(RCC->AHB2RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 824 | } |
| AnnaBridge | 171:3a7713b1edbc | 825 | |
| AnnaBridge | 171:3a7713b1edbc | 826 | /** |
| AnnaBridge | 171:3a7713b1edbc | 827 | * @brief Enable AHB2 peripheral clocks in low-power mode |
| AnnaBridge | 171:3a7713b1edbc | 828 | * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 829 | * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 830 | * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 831 | * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 832 | * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 833 | * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 834 | * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower |
| AnnaBridge | 171:3a7713b1edbc | 835 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 836 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 171:3a7713b1edbc | 837 | * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) |
| AnnaBridge | 171:3a7713b1edbc | 838 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 839 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 171:3a7713b1edbc | 840 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 171:3a7713b1edbc | 841 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 171:3a7713b1edbc | 842 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 171:3a7713b1edbc | 843 | * |
| AnnaBridge | 171:3a7713b1edbc | 844 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 845 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 846 | */ |
| AnnaBridge | 171:3a7713b1edbc | 847 | __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 848 | { |
| AnnaBridge | 171:3a7713b1edbc | 849 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 850 | SET_BIT(RCC->AHB2LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 851 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 852 | tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 853 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 854 | } |
| AnnaBridge | 171:3a7713b1edbc | 855 | |
| AnnaBridge | 171:3a7713b1edbc | 856 | /** |
| AnnaBridge | 171:3a7713b1edbc | 857 | * @brief Disable AHB2 peripheral clocks in low-power mode |
| AnnaBridge | 171:3a7713b1edbc | 858 | * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 859 | * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 860 | * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 861 | * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 862 | * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 863 | * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 864 | * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower |
| AnnaBridge | 171:3a7713b1edbc | 865 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 866 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 171:3a7713b1edbc | 867 | * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) |
| AnnaBridge | 171:3a7713b1edbc | 868 | * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 869 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 171:3a7713b1edbc | 870 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 171:3a7713b1edbc | 871 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 171:3a7713b1edbc | 872 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS |
| AnnaBridge | 171:3a7713b1edbc | 873 | * |
| AnnaBridge | 171:3a7713b1edbc | 874 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 875 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 876 | */ |
| AnnaBridge | 171:3a7713b1edbc | 877 | __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 878 | { |
| AnnaBridge | 171:3a7713b1edbc | 879 | CLEAR_BIT(RCC->AHB2LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 880 | } |
| AnnaBridge | 171:3a7713b1edbc | 881 | |
| AnnaBridge | 171:3a7713b1edbc | 882 | /** |
| AnnaBridge | 171:3a7713b1edbc | 883 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 884 | */ |
| AnnaBridge | 171:3a7713b1edbc | 885 | |
| AnnaBridge | 171:3a7713b1edbc | 886 | /** @defgroup BUS_LL_EF_AHB3 AHB3 |
| AnnaBridge | 171:3a7713b1edbc | 887 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 888 | */ |
| AnnaBridge | 171:3a7713b1edbc | 889 | |
| AnnaBridge | 171:3a7713b1edbc | 890 | /** |
| AnnaBridge | 171:3a7713b1edbc | 891 | * @brief Enable AHB3 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 892 | * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 893 | * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock |
| AnnaBridge | 171:3a7713b1edbc | 894 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 895 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 896 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 171:3a7713b1edbc | 897 | * |
| AnnaBridge | 171:3a7713b1edbc | 898 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 899 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 900 | */ |
| AnnaBridge | 171:3a7713b1edbc | 901 | __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 902 | { |
| AnnaBridge | 171:3a7713b1edbc | 903 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 904 | SET_BIT(RCC->AHB3ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 905 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 906 | tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 907 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 908 | } |
| AnnaBridge | 171:3a7713b1edbc | 909 | |
| AnnaBridge | 171:3a7713b1edbc | 910 | /** |
| AnnaBridge | 171:3a7713b1edbc | 911 | * @brief Check if AHB3 peripheral clock is enabled or not |
| AnnaBridge | 171:3a7713b1edbc | 912 | * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 913 | * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock |
| AnnaBridge | 171:3a7713b1edbc | 914 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 915 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 916 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 171:3a7713b1edbc | 917 | * |
| AnnaBridge | 171:3a7713b1edbc | 918 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 919 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 920 | */ |
| AnnaBridge | 171:3a7713b1edbc | 921 | __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 922 | { |
| AnnaBridge | 171:3a7713b1edbc | 923 | return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 924 | } |
| AnnaBridge | 171:3a7713b1edbc | 925 | |
| AnnaBridge | 171:3a7713b1edbc | 926 | /** |
| AnnaBridge | 171:3a7713b1edbc | 927 | * @brief Disable AHB3 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 928 | * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 929 | * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock |
| AnnaBridge | 171:3a7713b1edbc | 930 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 931 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 932 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 171:3a7713b1edbc | 933 | * |
| AnnaBridge | 171:3a7713b1edbc | 934 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 935 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 936 | */ |
| AnnaBridge | 171:3a7713b1edbc | 937 | __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 938 | { |
| AnnaBridge | 171:3a7713b1edbc | 939 | CLEAR_BIT(RCC->AHB3ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 940 | } |
| AnnaBridge | 171:3a7713b1edbc | 941 | |
| AnnaBridge | 171:3a7713b1edbc | 942 | /** |
| AnnaBridge | 171:3a7713b1edbc | 943 | * @brief Force AHB3 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 944 | * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 945 | * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset |
| AnnaBridge | 171:3a7713b1edbc | 946 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 947 | * @arg @ref LL_AHB3_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 948 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 949 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 171:3a7713b1edbc | 950 | * |
| AnnaBridge | 171:3a7713b1edbc | 951 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 952 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 953 | */ |
| AnnaBridge | 171:3a7713b1edbc | 954 | __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 955 | { |
| AnnaBridge | 171:3a7713b1edbc | 956 | SET_BIT(RCC->AHB3RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 957 | } |
| AnnaBridge | 171:3a7713b1edbc | 958 | |
| AnnaBridge | 171:3a7713b1edbc | 959 | /** |
| AnnaBridge | 171:3a7713b1edbc | 960 | * @brief Release AHB3 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 961 | * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 962 | * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset |
| AnnaBridge | 171:3a7713b1edbc | 963 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 964 | * @arg @ref LL_AHB2_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 965 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 966 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 171:3a7713b1edbc | 967 | * |
| AnnaBridge | 171:3a7713b1edbc | 968 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 969 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 970 | */ |
| AnnaBridge | 171:3a7713b1edbc | 971 | __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 972 | { |
| AnnaBridge | 171:3a7713b1edbc | 973 | CLEAR_BIT(RCC->AHB3RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 974 | } |
| AnnaBridge | 171:3a7713b1edbc | 975 | |
| AnnaBridge | 171:3a7713b1edbc | 976 | /** |
| AnnaBridge | 171:3a7713b1edbc | 977 | * @brief Enable AHB3 peripheral clocks in low-power mode |
| AnnaBridge | 171:3a7713b1edbc | 978 | * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 979 | * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower |
| AnnaBridge | 171:3a7713b1edbc | 980 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 981 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 982 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 171:3a7713b1edbc | 983 | * |
| AnnaBridge | 171:3a7713b1edbc | 984 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 985 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 986 | */ |
| AnnaBridge | 171:3a7713b1edbc | 987 | __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 988 | { |
| AnnaBridge | 171:3a7713b1edbc | 989 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 990 | SET_BIT(RCC->AHB3LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 991 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 992 | tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 993 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 994 | } |
| AnnaBridge | 171:3a7713b1edbc | 995 | |
| AnnaBridge | 171:3a7713b1edbc | 996 | /** |
| AnnaBridge | 171:3a7713b1edbc | 997 | * @brief Disable AHB3 peripheral clocks in low-power mode |
| AnnaBridge | 171:3a7713b1edbc | 998 | * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 999 | * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower |
| AnnaBridge | 171:3a7713b1edbc | 1000 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1001 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1002 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 171:3a7713b1edbc | 1003 | * |
| AnnaBridge | 171:3a7713b1edbc | 1004 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1005 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1006 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1007 | __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1008 | { |
| AnnaBridge | 171:3a7713b1edbc | 1009 | CLEAR_BIT(RCC->AHB3LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1010 | } |
| AnnaBridge | 171:3a7713b1edbc | 1011 | |
| AnnaBridge | 171:3a7713b1edbc | 1012 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1013 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1014 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1015 | |
| AnnaBridge | 171:3a7713b1edbc | 1016 | /** @defgroup BUS_LL_EF_APB1 APB1 |
| AnnaBridge | 171:3a7713b1edbc | 1017 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 1018 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1019 | |
| AnnaBridge | 171:3a7713b1edbc | 1020 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1021 | * @brief Enable APB1 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 1022 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1023 | * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1024 | * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1025 | * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1026 | * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1027 | * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1028 | * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1029 | * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1030 | * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1031 | * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1032 | * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1033 | * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1034 | * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1035 | * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1036 | * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1037 | * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1038 | * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1039 | * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1040 | * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1041 | * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1042 | * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1043 | * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1044 | * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1045 | * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1046 | * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1047 | * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1048 | * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1049 | * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1050 | * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1051 | * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1052 | * APB1ENR RTCEN LL_APB1_GRP1_EnableClock |
| AnnaBridge | 171:3a7713b1edbc | 1053 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1054 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 1055 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 1056 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 1057 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 171:3a7713b1edbc | 1058 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 1059 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 1060 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 171:3a7713b1edbc | 1061 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 171:3a7713b1edbc | 1062 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 171:3a7713b1edbc | 1063 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1064 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 1065 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 1066 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 171:3a7713b1edbc | 1067 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| AnnaBridge | 171:3a7713b1edbc | 1068 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 1069 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 1070 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 171:3a7713b1edbc | 1071 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 171:3a7713b1edbc | 1072 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 1073 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 1074 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 171:3a7713b1edbc | 1075 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1076 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 171:3a7713b1edbc | 1077 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1078 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1079 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1080 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 1081 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 1082 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 |
| AnnaBridge | 171:3a7713b1edbc | 1083 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 |
| AnnaBridge | 171:3a7713b1edbc | 1084 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| AnnaBridge | 171:3a7713b1edbc | 1085 | * |
| AnnaBridge | 171:3a7713b1edbc | 1086 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1087 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1088 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1089 | __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1090 | { |
| AnnaBridge | 171:3a7713b1edbc | 1091 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 1092 | SET_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1093 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 1094 | tmpreg = READ_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1095 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 1096 | } |
| AnnaBridge | 171:3a7713b1edbc | 1097 | |
| AnnaBridge | 171:3a7713b1edbc | 1098 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1099 | * @brief Check if APB1 peripheral clock is enabled or not |
| AnnaBridge | 171:3a7713b1edbc | 1100 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1101 | * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1102 | * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1103 | * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1104 | * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1105 | * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1106 | * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1107 | * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1108 | * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1109 | * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1110 | * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1111 | * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1112 | * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1113 | * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1114 | * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1115 | * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1116 | * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1117 | * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1118 | * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1119 | * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1120 | * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1121 | * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1122 | * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1123 | * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1124 | * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1125 | * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1126 | * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1127 | * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1128 | * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1129 | * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1130 | * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock |
| AnnaBridge | 171:3a7713b1edbc | 1131 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1132 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 1133 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 1134 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 1135 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 171:3a7713b1edbc | 1136 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 1137 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 1138 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 171:3a7713b1edbc | 1139 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 171:3a7713b1edbc | 1140 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 171:3a7713b1edbc | 1141 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1142 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 1143 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 1144 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 171:3a7713b1edbc | 1145 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| AnnaBridge | 171:3a7713b1edbc | 1146 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 1147 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 1148 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 171:3a7713b1edbc | 1149 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 171:3a7713b1edbc | 1150 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 1151 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 1152 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 171:3a7713b1edbc | 1153 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1154 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 171:3a7713b1edbc | 1155 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1156 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1157 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1158 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 1159 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 1160 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 |
| AnnaBridge | 171:3a7713b1edbc | 1161 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 |
| AnnaBridge | 171:3a7713b1edbc | 1162 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| AnnaBridge | 171:3a7713b1edbc | 1163 | * |
| AnnaBridge | 171:3a7713b1edbc | 1164 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1165 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 1166 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1167 | __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1168 | { |
| AnnaBridge | 171:3a7713b1edbc | 1169 | return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1170 | } |
| AnnaBridge | 171:3a7713b1edbc | 1171 | |
| AnnaBridge | 171:3a7713b1edbc | 1172 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1173 | * @brief Disable APB1 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 1174 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1175 | * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1176 | * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1177 | * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1178 | * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1179 | * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1180 | * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1181 | * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1182 | * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1183 | * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1184 | * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1185 | * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1186 | * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1187 | * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1188 | * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1189 | * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1190 | * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1191 | * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1192 | * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1193 | * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1194 | * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1195 | * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1196 | * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1197 | * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1198 | * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1199 | * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1200 | * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1201 | * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1202 | * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1203 | * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1204 | * APB1ENR RTCEN LL_APB1_GRP1_DisableClock |
| AnnaBridge | 171:3a7713b1edbc | 1205 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1206 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 1207 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 1208 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 1209 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 171:3a7713b1edbc | 1210 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 1211 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 1212 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 171:3a7713b1edbc | 1213 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 171:3a7713b1edbc | 1214 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 171:3a7713b1edbc | 1215 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1216 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 1217 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 1218 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 171:3a7713b1edbc | 1219 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| AnnaBridge | 171:3a7713b1edbc | 1220 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 1221 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 1222 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 171:3a7713b1edbc | 1223 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 171:3a7713b1edbc | 1224 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 1225 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 1226 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 171:3a7713b1edbc | 1227 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1228 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 171:3a7713b1edbc | 1229 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1230 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1231 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1232 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 1233 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 1234 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 |
| AnnaBridge | 171:3a7713b1edbc | 1235 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 |
| AnnaBridge | 171:3a7713b1edbc | 1236 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| AnnaBridge | 171:3a7713b1edbc | 1237 | * |
| AnnaBridge | 171:3a7713b1edbc | 1238 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1239 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1240 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1241 | __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1242 | { |
| AnnaBridge | 171:3a7713b1edbc | 1243 | CLEAR_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1244 | } |
| AnnaBridge | 171:3a7713b1edbc | 1245 | |
| AnnaBridge | 171:3a7713b1edbc | 1246 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1247 | * @brief Force APB1 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 1248 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1249 | * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1250 | * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1251 | * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1252 | * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1253 | * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1254 | * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1255 | * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1256 | * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1257 | * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1258 | * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1259 | * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1260 | * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1261 | * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1262 | * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1263 | * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1264 | * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1265 | * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1266 | * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1267 | * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1268 | * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1269 | * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1270 | * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1271 | * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1272 | * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1273 | * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1274 | * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1275 | * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1276 | * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1277 | * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset |
| AnnaBridge | 171:3a7713b1edbc | 1278 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1279 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 1280 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 1281 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 1282 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 171:3a7713b1edbc | 1283 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 1284 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 1285 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 171:3a7713b1edbc | 1286 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 171:3a7713b1edbc | 1287 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 171:3a7713b1edbc | 1288 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1289 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 1290 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 1291 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 171:3a7713b1edbc | 1292 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| AnnaBridge | 171:3a7713b1edbc | 1293 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 1294 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 1295 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 171:3a7713b1edbc | 1296 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 171:3a7713b1edbc | 1297 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 1298 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 1299 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 171:3a7713b1edbc | 1300 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1301 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 171:3a7713b1edbc | 1302 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1303 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1304 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1305 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 1306 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 1307 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 |
| AnnaBridge | 171:3a7713b1edbc | 1308 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 |
| AnnaBridge | 171:3a7713b1edbc | 1309 | * |
| AnnaBridge | 171:3a7713b1edbc | 1310 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1311 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1312 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1313 | __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1314 | { |
| AnnaBridge | 171:3a7713b1edbc | 1315 | SET_BIT(RCC->APB1RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1316 | } |
| AnnaBridge | 171:3a7713b1edbc | 1317 | |
| AnnaBridge | 171:3a7713b1edbc | 1318 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1319 | * @brief Release APB1 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 1320 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1321 | * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1322 | * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1323 | * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1324 | * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1325 | * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1326 | * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1327 | * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1328 | * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1329 | * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1330 | * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1331 | * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1332 | * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1333 | * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1334 | * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1335 | * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1336 | * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1337 | * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1338 | * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1339 | * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1340 | * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1341 | * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1342 | * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1343 | * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1344 | * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1345 | * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1346 | * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1347 | * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1348 | * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1349 | * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset |
| AnnaBridge | 171:3a7713b1edbc | 1350 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1351 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 1352 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 1353 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 1354 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 171:3a7713b1edbc | 1355 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 1356 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 1357 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 171:3a7713b1edbc | 1358 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 171:3a7713b1edbc | 1359 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 171:3a7713b1edbc | 1360 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1361 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 1362 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 1363 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 171:3a7713b1edbc | 1364 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| AnnaBridge | 171:3a7713b1edbc | 1365 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 1366 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 1367 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 171:3a7713b1edbc | 1368 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 171:3a7713b1edbc | 1369 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 1370 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 1371 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 171:3a7713b1edbc | 1372 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1373 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 171:3a7713b1edbc | 1374 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1375 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1376 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1377 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 1378 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 1379 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 |
| AnnaBridge | 171:3a7713b1edbc | 1380 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 |
| AnnaBridge | 171:3a7713b1edbc | 1381 | * |
| AnnaBridge | 171:3a7713b1edbc | 1382 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1383 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1384 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1385 | __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1386 | { |
| AnnaBridge | 171:3a7713b1edbc | 1387 | CLEAR_BIT(RCC->APB1RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1388 | } |
| AnnaBridge | 171:3a7713b1edbc | 1389 | |
| AnnaBridge | 171:3a7713b1edbc | 1390 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1391 | * @brief Enable APB1 peripheral clocks in low-power mode |
| AnnaBridge | 171:3a7713b1edbc | 1392 | * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1393 | * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1394 | * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1395 | * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1396 | * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1397 | * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1398 | * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1399 | * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1400 | * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1401 | * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1402 | * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1403 | * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1404 | * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1405 | * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1406 | * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1407 | * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1408 | * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1409 | * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1410 | * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1411 | * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1412 | * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1413 | * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1414 | * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1415 | * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1416 | * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1417 | * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1418 | * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1419 | * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1420 | * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1421 | * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1422 | * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower |
| AnnaBridge | 171:3a7713b1edbc | 1423 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1424 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 1425 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 1426 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 1427 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 171:3a7713b1edbc | 1428 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 1429 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 1430 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 171:3a7713b1edbc | 1431 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 171:3a7713b1edbc | 1432 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 171:3a7713b1edbc | 1433 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1434 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 1435 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 1436 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 171:3a7713b1edbc | 1437 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| AnnaBridge | 171:3a7713b1edbc | 1438 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 1439 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 1440 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 171:3a7713b1edbc | 1441 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 171:3a7713b1edbc | 1442 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 1443 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 1444 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 171:3a7713b1edbc | 1445 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1446 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 171:3a7713b1edbc | 1447 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1448 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1449 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1450 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 1451 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 1452 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 |
| AnnaBridge | 171:3a7713b1edbc | 1453 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 |
| AnnaBridge | 171:3a7713b1edbc | 1454 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| AnnaBridge | 171:3a7713b1edbc | 1455 | * |
| AnnaBridge | 171:3a7713b1edbc | 1456 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1457 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1458 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1459 | __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1460 | { |
| AnnaBridge | 171:3a7713b1edbc | 1461 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 1462 | SET_BIT(RCC->APB1LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1463 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 1464 | tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1465 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 1466 | } |
| AnnaBridge | 171:3a7713b1edbc | 1467 | |
| AnnaBridge | 171:3a7713b1edbc | 1468 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1469 | * @brief Disable APB1 peripheral clocks in low-power mode |
| AnnaBridge | 171:3a7713b1edbc | 1470 | * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1471 | * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1472 | * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1473 | * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1474 | * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1475 | * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1476 | * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1477 | * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1478 | * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1479 | * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1480 | * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1481 | * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1482 | * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1483 | * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1484 | * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1485 | * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1486 | * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1487 | * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1488 | * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1489 | * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1490 | * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1491 | * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1492 | * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1493 | * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1494 | * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1495 | * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1496 | * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1497 | * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1498 | * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1499 | * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1500 | * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower |
| AnnaBridge | 171:3a7713b1edbc | 1501 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1502 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 1503 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 1504 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 1505 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 |
| AnnaBridge | 171:3a7713b1edbc | 1506 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 1507 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 1508 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 |
| AnnaBridge | 171:3a7713b1edbc | 1509 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 |
| AnnaBridge | 171:3a7713b1edbc | 1510 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 171:3a7713b1edbc | 1511 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1512 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 1513 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 1514 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 171:3a7713b1edbc | 1515 | * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) |
| AnnaBridge | 171:3a7713b1edbc | 1516 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 1517 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 1518 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 |
| AnnaBridge | 171:3a7713b1edbc | 1519 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 |
| AnnaBridge | 171:3a7713b1edbc | 1520 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 1521 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 1522 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 171:3a7713b1edbc | 1523 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1524 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 171:3a7713b1edbc | 1525 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1526 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1527 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1528 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 1529 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 1530 | * @arg @ref LL_APB1_GRP1_PERIPH_UART7 |
| AnnaBridge | 171:3a7713b1edbc | 1531 | * @arg @ref LL_APB1_GRP1_PERIPH_UART8 |
| AnnaBridge | 171:3a7713b1edbc | 1532 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| AnnaBridge | 171:3a7713b1edbc | 1533 | * |
| AnnaBridge | 171:3a7713b1edbc | 1534 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1535 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1536 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1537 | __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1538 | { |
| AnnaBridge | 171:3a7713b1edbc | 1539 | CLEAR_BIT(RCC->APB1LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1540 | } |
| AnnaBridge | 171:3a7713b1edbc | 1541 | |
| AnnaBridge | 171:3a7713b1edbc | 1542 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1543 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1544 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1545 | |
| AnnaBridge | 171:3a7713b1edbc | 1546 | /** @defgroup BUS_LL_EF_APB2 APB2 |
| AnnaBridge | 171:3a7713b1edbc | 1547 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 1548 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1549 | |
| AnnaBridge | 171:3a7713b1edbc | 1550 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1551 | * @brief Enable APB2 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 1552 | * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1553 | * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1554 | * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1555 | * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1556 | * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1557 | * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1558 | * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1559 | * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1560 | * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1561 | * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1562 | * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1563 | * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1564 | * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1565 | * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1566 | * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1567 | * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1568 | * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1569 | * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1570 | * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1571 | * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1572 | * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1573 | * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1574 | * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1575 | * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock |
| AnnaBridge | 171:3a7713b1edbc | 1576 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1577 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1578 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 171:3a7713b1edbc | 1579 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 1580 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 171:3a7713b1edbc | 1581 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 1582 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 |
| AnnaBridge | 171:3a7713b1edbc | 1583 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 |
| AnnaBridge | 171:3a7713b1edbc | 1584 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 |
| AnnaBridge | 171:3a7713b1edbc | 1585 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1586 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 1587 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 |
| AnnaBridge | 171:3a7713b1edbc | 1588 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 1589 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 1590 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 1591 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 1592 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 |
| AnnaBridge | 171:3a7713b1edbc | 1593 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1594 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 171:3a7713b1edbc | 1595 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 |
| AnnaBridge | 171:3a7713b1edbc | 1596 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1597 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| AnnaBridge | 171:3a7713b1edbc | 1598 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1599 | * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 1600 | * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1601 | * |
| AnnaBridge | 171:3a7713b1edbc | 1602 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1603 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1604 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1605 | __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1606 | { |
| AnnaBridge | 171:3a7713b1edbc | 1607 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 1608 | SET_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1609 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 1610 | tmpreg = READ_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1611 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 1612 | } |
| AnnaBridge | 171:3a7713b1edbc | 1613 | |
| AnnaBridge | 171:3a7713b1edbc | 1614 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1615 | * @brief Check if APB2 peripheral clock is enabled or not |
| AnnaBridge | 171:3a7713b1edbc | 1616 | * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1617 | * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1618 | * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1619 | * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1620 | * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1621 | * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1622 | * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1623 | * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1624 | * APB2ENR SDMMC2EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1625 | * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1626 | * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1627 | * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1628 | * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1629 | * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1630 | * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1631 | * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1632 | * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1633 | * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1634 | * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1635 | * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1636 | * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1637 | * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1638 | * APB2ENR MDIOEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1639 | * APB2ENR OTGPHYCEN LL_APB2_GRP1_IsEnabledClock |
| AnnaBridge | 171:3a7713b1edbc | 1640 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1641 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1642 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 171:3a7713b1edbc | 1643 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 1644 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 171:3a7713b1edbc | 1645 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 1646 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 |
| AnnaBridge | 171:3a7713b1edbc | 1647 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 |
| AnnaBridge | 171:3a7713b1edbc | 1648 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 |
| AnnaBridge | 171:3a7713b1edbc | 1649 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1650 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 1651 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 |
| AnnaBridge | 171:3a7713b1edbc | 1652 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 1653 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 1654 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 1655 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 1656 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 |
| AnnaBridge | 171:3a7713b1edbc | 1657 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1658 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 171:3a7713b1edbc | 1659 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 |
| AnnaBridge | 171:3a7713b1edbc | 1660 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1661 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| AnnaBridge | 171:3a7713b1edbc | 1662 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1663 | * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 1664 | * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1665 | * |
| AnnaBridge | 171:3a7713b1edbc | 1666 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1667 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 1668 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1669 | __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1670 | { |
| AnnaBridge | 171:3a7713b1edbc | 1671 | return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1672 | } |
| AnnaBridge | 171:3a7713b1edbc | 1673 | |
| AnnaBridge | 171:3a7713b1edbc | 1674 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1675 | * @brief Disable APB2 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 1676 | * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1677 | * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1678 | * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1679 | * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1680 | * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1681 | * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1682 | * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1683 | * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1684 | * APB2ENR SDMMC2EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1685 | * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1686 | * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1687 | * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1688 | * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1689 | * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1690 | * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1691 | * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1692 | * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1693 | * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1694 | * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1695 | * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1696 | * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1697 | * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1698 | * APB2ENR MDIOEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 1699 | * APB2ENR OTGPHYCEN LL_APB2_GRP1_DisableClock |
| AnnaBridge | 171:3a7713b1edbc | 1700 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1701 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1702 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 171:3a7713b1edbc | 1703 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 1704 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 171:3a7713b1edbc | 1705 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 1706 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 |
| AnnaBridge | 171:3a7713b1edbc | 1707 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 |
| AnnaBridge | 171:3a7713b1edbc | 1708 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 |
| AnnaBridge | 171:3a7713b1edbc | 1709 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1710 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 1711 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 |
| AnnaBridge | 171:3a7713b1edbc | 1712 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 1713 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 1714 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 1715 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 1716 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 |
| AnnaBridge | 171:3a7713b1edbc | 1717 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1718 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 171:3a7713b1edbc | 1719 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 |
| AnnaBridge | 171:3a7713b1edbc | 1720 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1721 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| AnnaBridge | 171:3a7713b1edbc | 1722 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1723 | * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 1724 | * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1725 | * |
| AnnaBridge | 171:3a7713b1edbc | 1726 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1727 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1728 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1729 | __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1730 | { |
| AnnaBridge | 171:3a7713b1edbc | 1731 | CLEAR_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1732 | } |
| AnnaBridge | 171:3a7713b1edbc | 1733 | |
| AnnaBridge | 171:3a7713b1edbc | 1734 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1735 | * @brief Force APB2 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 1736 | * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1737 | * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1738 | * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1739 | * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1740 | * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1741 | * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1742 | * APB2RSTR SDMMC2RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1743 | * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1744 | * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1745 | * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1746 | * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1747 | * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1748 | * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1749 | * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1750 | * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1751 | * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1752 | * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1753 | * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1754 | * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1755 | * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1756 | * APB2RSTR MDIORST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1757 | * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ForceReset |
| AnnaBridge | 171:3a7713b1edbc | 1758 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1759 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 1760 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1761 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 171:3a7713b1edbc | 1762 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 1763 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 171:3a7713b1edbc | 1764 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC |
| AnnaBridge | 171:3a7713b1edbc | 1765 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 |
| AnnaBridge | 171:3a7713b1edbc | 1766 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1767 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 1768 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 |
| AnnaBridge | 171:3a7713b1edbc | 1769 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 1770 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 1771 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 1772 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 1773 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 |
| AnnaBridge | 171:3a7713b1edbc | 1774 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1775 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 171:3a7713b1edbc | 1776 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 |
| AnnaBridge | 171:3a7713b1edbc | 1777 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1778 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| AnnaBridge | 171:3a7713b1edbc | 1779 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1780 | * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 1781 | * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1782 | * |
| AnnaBridge | 171:3a7713b1edbc | 1783 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1784 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1785 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1786 | __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1787 | { |
| AnnaBridge | 171:3a7713b1edbc | 1788 | SET_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1789 | } |
| AnnaBridge | 171:3a7713b1edbc | 1790 | |
| AnnaBridge | 171:3a7713b1edbc | 1791 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1792 | * @brief Release APB2 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 1793 | * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1794 | * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1795 | * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1796 | * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1797 | * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1798 | * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1799 | * APB2RSTR SDMMC2RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1800 | * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1801 | * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1802 | * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1803 | * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1804 | * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1805 | * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1806 | * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1807 | * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1808 | * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1809 | * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1810 | * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1811 | * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1812 | * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1813 | * APB2RSTR MDIORST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1814 | * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ReleaseReset |
| AnnaBridge | 171:3a7713b1edbc | 1815 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1816 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 1817 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1818 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 171:3a7713b1edbc | 1819 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 1820 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 171:3a7713b1edbc | 1821 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC |
| AnnaBridge | 171:3a7713b1edbc | 1822 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 |
| AnnaBridge | 171:3a7713b1edbc | 1823 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1824 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 1825 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 |
| AnnaBridge | 171:3a7713b1edbc | 1826 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 1827 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 1828 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 1829 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 1830 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 |
| AnnaBridge | 171:3a7713b1edbc | 1831 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1832 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 171:3a7713b1edbc | 1833 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 |
| AnnaBridge | 171:3a7713b1edbc | 1834 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1835 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| AnnaBridge | 171:3a7713b1edbc | 1836 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1837 | * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 1838 | * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1839 | * |
| AnnaBridge | 171:3a7713b1edbc | 1840 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1841 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1842 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1843 | __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1844 | { |
| AnnaBridge | 171:3a7713b1edbc | 1845 | CLEAR_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1846 | } |
| AnnaBridge | 171:3a7713b1edbc | 1847 | |
| AnnaBridge | 171:3a7713b1edbc | 1848 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1849 | * @brief Enable APB2 peripheral clocks in low-power mode |
| AnnaBridge | 171:3a7713b1edbc | 1850 | * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1851 | * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1852 | * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1853 | * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1854 | * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1855 | * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1856 | * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1857 | * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1858 | * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1859 | * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1860 | * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1861 | * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1862 | * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1863 | * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1864 | * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1865 | * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1866 | * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1867 | * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1868 | * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1869 | * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1870 | * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1871 | * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1872 | * APB2LPENR MDIOLPEN LL_APB2_GRP1_EnableClockLowPower |
| AnnaBridge | 171:3a7713b1edbc | 1873 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1874 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1875 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 171:3a7713b1edbc | 1876 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 1877 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 171:3a7713b1edbc | 1878 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 1879 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 |
| AnnaBridge | 171:3a7713b1edbc | 1880 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 |
| AnnaBridge | 171:3a7713b1edbc | 1881 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 |
| AnnaBridge | 171:3a7713b1edbc | 1882 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1883 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 1884 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 |
| AnnaBridge | 171:3a7713b1edbc | 1885 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 1886 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 1887 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 1888 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 1889 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 |
| AnnaBridge | 171:3a7713b1edbc | 1890 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1891 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 171:3a7713b1edbc | 1892 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 |
| AnnaBridge | 171:3a7713b1edbc | 1893 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1894 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| AnnaBridge | 171:3a7713b1edbc | 1895 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1896 | * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 1897 | * |
| AnnaBridge | 171:3a7713b1edbc | 1898 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1899 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1900 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1901 | __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1902 | { |
| AnnaBridge | 171:3a7713b1edbc | 1903 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 1904 | SET_BIT(RCC->APB2LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1905 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 1906 | tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1907 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 1908 | } |
| AnnaBridge | 171:3a7713b1edbc | 1909 | |
| AnnaBridge | 171:3a7713b1edbc | 1910 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1911 | * @brief Disable APB2 peripheral clocks in low-power mode |
| AnnaBridge | 171:3a7713b1edbc | 1912 | * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1913 | * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1914 | * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1915 | * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1916 | * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1917 | * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1918 | * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1919 | * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1920 | * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1921 | * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1922 | * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1923 | * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1924 | * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1925 | * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1926 | * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1927 | * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1928 | * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1929 | * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1930 | * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1931 | * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1932 | * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1933 | * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n |
| AnnaBridge | 171:3a7713b1edbc | 1934 | * APB2LPENR MDIOLPEN LL_APB2_GRP1_DisableClockLowPower |
| AnnaBridge | 171:3a7713b1edbc | 1935 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1936 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 171:3a7713b1edbc | 1937 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 |
| AnnaBridge | 171:3a7713b1edbc | 1938 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 1939 | * @arg @ref LL_APB2_GRP1_PERIPH_USART6 |
| AnnaBridge | 171:3a7713b1edbc | 1940 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 1941 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 |
| AnnaBridge | 171:3a7713b1edbc | 1942 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 |
| AnnaBridge | 171:3a7713b1edbc | 1943 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 |
| AnnaBridge | 171:3a7713b1edbc | 1944 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1945 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 1946 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 |
| AnnaBridge | 171:3a7713b1edbc | 1947 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 1948 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 1949 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 1950 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 1951 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 |
| AnnaBridge | 171:3a7713b1edbc | 1952 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1953 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 171:3a7713b1edbc | 1954 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 |
| AnnaBridge | 171:3a7713b1edbc | 1955 | * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) |
| AnnaBridge | 171:3a7713b1edbc | 1956 | * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) |
| AnnaBridge | 171:3a7713b1edbc | 1957 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 1958 | * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 1959 | * |
| AnnaBridge | 171:3a7713b1edbc | 1960 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1961 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1962 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1963 | __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1964 | { |
| AnnaBridge | 171:3a7713b1edbc | 1965 | CLEAR_BIT(RCC->APB2LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1966 | } |
| AnnaBridge | 171:3a7713b1edbc | 1967 | |
| AnnaBridge | 171:3a7713b1edbc | 1968 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1969 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1970 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1971 | |
| AnnaBridge | 171:3a7713b1edbc | 1972 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1973 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1974 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1975 | |
| AnnaBridge | 171:3a7713b1edbc | 1976 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1977 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1978 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1979 | |
| AnnaBridge | 171:3a7713b1edbc | 1980 | #endif /* defined(RCC) */ |
| AnnaBridge | 171:3a7713b1edbc | 1981 | |
| AnnaBridge | 171:3a7713b1edbc | 1982 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1983 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1984 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1985 | |
| AnnaBridge | 171:3a7713b1edbc | 1986 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 1987 | } |
| AnnaBridge | 171:3a7713b1edbc | 1988 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 1989 | |
| AnnaBridge | 171:3a7713b1edbc | 1990 | #endif /* __STM32F7xx_LL_BUS_H */ |
| AnnaBridge | 171:3a7713b1edbc | 1991 | |
| AnnaBridge | 171:3a7713b1edbc | 1992 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
