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TARGET_DISCO_F746NG/TOOLCHAIN_IAR/stm32f7xx_hal_rcc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f7xx_hal_rcc.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of RCC HAL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F7xx_HAL_RCC_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F7xx_HAL_RCC_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32f7xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* Include RCC HAL Extended module */
AnnaBridge 171:3a7713b1edbc 48 /* (include on top of file since RCC structures are defined in extended file) */
AnnaBridge 171:3a7713b1edbc 49 #include "stm32f7xx_hal_rcc_ex.h"
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /** @addtogroup STM32F7xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 52 * @{
AnnaBridge 171:3a7713b1edbc 53 */
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /** @addtogroup RCC
AnnaBridge 171:3a7713b1edbc 56 * @{
AnnaBridge 171:3a7713b1edbc 57 */
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge 171:3a7713b1edbc 62 * @{
AnnaBridge 171:3a7713b1edbc 63 */
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 /**
AnnaBridge 171:3a7713b1edbc 66 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
AnnaBridge 171:3a7713b1edbc 67 */
AnnaBridge 171:3a7713b1edbc 68 typedef struct
AnnaBridge 171:3a7713b1edbc 69 {
AnnaBridge 171:3a7713b1edbc 70 uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge 171:3a7713b1edbc 71 This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge 171:3a7713b1edbc 74 This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge 171:3a7713b1edbc 75
AnnaBridge 171:3a7713b1edbc 76 uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge 171:3a7713b1edbc 77 This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge 171:3a7713b1edbc 80 This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge 171:3a7713b1edbc 83 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge 171:3a7713b1edbc 86 This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 }RCC_OscInitTypeDef;
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 /**
AnnaBridge 171:3a7713b1edbc 93 * @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge 171:3a7713b1edbc 94 */
AnnaBridge 171:3a7713b1edbc 95 typedef struct
AnnaBridge 171:3a7713b1edbc 96 {
AnnaBridge 171:3a7713b1edbc 97 uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge 171:3a7713b1edbc 98 This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
AnnaBridge 171:3a7713b1edbc 101 This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge 171:3a7713b1edbc 104 This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge 171:3a7713b1edbc 107 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge 171:3a7713b1edbc 108
AnnaBridge 171:3a7713b1edbc 109 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge 171:3a7713b1edbc 110 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 }RCC_ClkInitTypeDef;
AnnaBridge 171:3a7713b1edbc 113
AnnaBridge 171:3a7713b1edbc 114 /**
AnnaBridge 171:3a7713b1edbc 115 * @}
AnnaBridge 171:3a7713b1edbc 116 */
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 119 /** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge 171:3a7713b1edbc 120 * @{
AnnaBridge 171:3a7713b1edbc 121 */
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123 /** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge 171:3a7713b1edbc 124 * @{
AnnaBridge 171:3a7713b1edbc 125 */
AnnaBridge 171:3a7713b1edbc 126 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 127 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
AnnaBridge 171:3a7713b1edbc 128 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
AnnaBridge 171:3a7713b1edbc 129 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
AnnaBridge 171:3a7713b1edbc 130 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
AnnaBridge 171:3a7713b1edbc 131 /**
AnnaBridge 171:3a7713b1edbc 132 * @}
AnnaBridge 171:3a7713b1edbc 133 */
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 /** @defgroup RCC_HSE_Config RCC HSE Config
AnnaBridge 171:3a7713b1edbc 136 * @{
AnnaBridge 171:3a7713b1edbc 137 */
AnnaBridge 171:3a7713b1edbc 138 #define RCC_HSE_OFF ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 139 #define RCC_HSE_ON RCC_CR_HSEON
AnnaBridge 171:3a7713b1edbc 140 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
AnnaBridge 171:3a7713b1edbc 141 /**
AnnaBridge 171:3a7713b1edbc 142 * @}
AnnaBridge 171:3a7713b1edbc 143 */
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 /** @defgroup RCC_LSE_Config RCC LSE Config
AnnaBridge 171:3a7713b1edbc 146 * @{
AnnaBridge 171:3a7713b1edbc 147 */
AnnaBridge 171:3a7713b1edbc 148 #define RCC_LSE_OFF ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 149 #define RCC_LSE_ON RCC_BDCR_LSEON
AnnaBridge 171:3a7713b1edbc 150 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
AnnaBridge 171:3a7713b1edbc 151 /**
AnnaBridge 171:3a7713b1edbc 152 * @}
AnnaBridge 171:3a7713b1edbc 153 */
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 /** @defgroup RCC_HSI_Config RCC HSI Config
AnnaBridge 171:3a7713b1edbc 156 * @{
AnnaBridge 171:3a7713b1edbc 157 */
AnnaBridge 171:3a7713b1edbc 158 #define RCC_HSI_OFF ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 159 #define RCC_HSI_ON RCC_CR_HSION
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 #define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
AnnaBridge 171:3a7713b1edbc 162 /**
AnnaBridge 171:3a7713b1edbc 163 * @}
AnnaBridge 171:3a7713b1edbc 164 */
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 /** @defgroup RCC_LSI_Config RCC LSI Config
AnnaBridge 171:3a7713b1edbc 167 * @{
AnnaBridge 171:3a7713b1edbc 168 */
AnnaBridge 171:3a7713b1edbc 169 #define RCC_LSI_OFF ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 170 #define RCC_LSI_ON RCC_CSR_LSION
AnnaBridge 171:3a7713b1edbc 171 /**
AnnaBridge 171:3a7713b1edbc 172 * @}
AnnaBridge 171:3a7713b1edbc 173 */
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 /** @defgroup RCC_PLL_Config RCC PLL Config
AnnaBridge 171:3a7713b1edbc 176 * @{
AnnaBridge 171:3a7713b1edbc 177 */
AnnaBridge 171:3a7713b1edbc 178 #define RCC_PLL_NONE ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 179 #define RCC_PLL_OFF ((uint32_t)0x00000001U)
AnnaBridge 171:3a7713b1edbc 180 #define RCC_PLL_ON ((uint32_t)0x00000002U)
AnnaBridge 171:3a7713b1edbc 181 /**
AnnaBridge 171:3a7713b1edbc 182 * @}
AnnaBridge 171:3a7713b1edbc 183 */
AnnaBridge 171:3a7713b1edbc 184
AnnaBridge 171:3a7713b1edbc 185 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
AnnaBridge 171:3a7713b1edbc 186 * @{
AnnaBridge 171:3a7713b1edbc 187 */
AnnaBridge 171:3a7713b1edbc 188 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
AnnaBridge 171:3a7713b1edbc 189 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
AnnaBridge 171:3a7713b1edbc 190 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
AnnaBridge 171:3a7713b1edbc 191 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
AnnaBridge 171:3a7713b1edbc 192 /**
AnnaBridge 171:3a7713b1edbc 193 * @}
AnnaBridge 171:3a7713b1edbc 194 */
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
AnnaBridge 171:3a7713b1edbc 197 * @{
AnnaBridge 171:3a7713b1edbc 198 */
AnnaBridge 171:3a7713b1edbc 199 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
AnnaBridge 171:3a7713b1edbc 200 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
AnnaBridge 171:3a7713b1edbc 201 /**
AnnaBridge 171:3a7713b1edbc 202 * @}
AnnaBridge 171:3a7713b1edbc 203 */
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 /** @defgroup RCC_System_Clock_Type RCC System Clock Type
AnnaBridge 171:3a7713b1edbc 206 * @{
AnnaBridge 171:3a7713b1edbc 207 */
AnnaBridge 171:3a7713b1edbc 208 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
AnnaBridge 171:3a7713b1edbc 209 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
AnnaBridge 171:3a7713b1edbc 210 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
AnnaBridge 171:3a7713b1edbc 211 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
AnnaBridge 171:3a7713b1edbc 212 /**
AnnaBridge 171:3a7713b1edbc 213 * @}
AnnaBridge 171:3a7713b1edbc 214 */
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 /** @defgroup RCC_System_Clock_Source RCC System Clock Source
AnnaBridge 171:3a7713b1edbc 217 * @{
AnnaBridge 171:3a7713b1edbc 218 */
AnnaBridge 171:3a7713b1edbc 219 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
AnnaBridge 171:3a7713b1edbc 220 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
AnnaBridge 171:3a7713b1edbc 221 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
AnnaBridge 171:3a7713b1edbc 222 /**
AnnaBridge 171:3a7713b1edbc 223 * @}
AnnaBridge 171:3a7713b1edbc 224 */
AnnaBridge 171:3a7713b1edbc 225
AnnaBridge 171:3a7713b1edbc 226
AnnaBridge 171:3a7713b1edbc 227 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge 171:3a7713b1edbc 228 * @{
AnnaBridge 171:3a7713b1edbc 229 */
AnnaBridge 171:3a7713b1edbc 230 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
AnnaBridge 171:3a7713b1edbc 231 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
AnnaBridge 171:3a7713b1edbc 232 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
AnnaBridge 171:3a7713b1edbc 233 /**
AnnaBridge 171:3a7713b1edbc 234 * @}
AnnaBridge 171:3a7713b1edbc 235 */
AnnaBridge 171:3a7713b1edbc 236
AnnaBridge 171:3a7713b1edbc 237 /** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
AnnaBridge 171:3a7713b1edbc 238 * @{
AnnaBridge 171:3a7713b1edbc 239 */
AnnaBridge 171:3a7713b1edbc 240 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
AnnaBridge 171:3a7713b1edbc 241 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
AnnaBridge 171:3a7713b1edbc 242 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
AnnaBridge 171:3a7713b1edbc 243 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
AnnaBridge 171:3a7713b1edbc 244 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
AnnaBridge 171:3a7713b1edbc 245 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
AnnaBridge 171:3a7713b1edbc 246 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
AnnaBridge 171:3a7713b1edbc 247 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
AnnaBridge 171:3a7713b1edbc 248 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
AnnaBridge 171:3a7713b1edbc 249 /**
AnnaBridge 171:3a7713b1edbc 250 * @}
AnnaBridge 171:3a7713b1edbc 251 */
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 /** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source
AnnaBridge 171:3a7713b1edbc 254 * @{
AnnaBridge 171:3a7713b1edbc 255 */
AnnaBridge 171:3a7713b1edbc 256 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
AnnaBridge 171:3a7713b1edbc 257 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
AnnaBridge 171:3a7713b1edbc 258 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
AnnaBridge 171:3a7713b1edbc 259 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
AnnaBridge 171:3a7713b1edbc 260 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
AnnaBridge 171:3a7713b1edbc 261 /**
AnnaBridge 171:3a7713b1edbc 262 * @}
AnnaBridge 171:3a7713b1edbc 263 */
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 /** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
AnnaBridge 171:3a7713b1edbc 266 * @{
AnnaBridge 171:3a7713b1edbc 267 */
AnnaBridge 171:3a7713b1edbc 268 #define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 269 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
AnnaBridge 171:3a7713b1edbc 270 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
AnnaBridge 171:3a7713b1edbc 271 #define RCC_RTCCLKSOURCE_HSE_DIVX ((uint32_t)0x00000300U)
AnnaBridge 171:3a7713b1edbc 272 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
AnnaBridge 171:3a7713b1edbc 273 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
AnnaBridge 171:3a7713b1edbc 274 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
AnnaBridge 171:3a7713b1edbc 275 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
AnnaBridge 171:3a7713b1edbc 276 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
AnnaBridge 171:3a7713b1edbc 277 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
AnnaBridge 171:3a7713b1edbc 278 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
AnnaBridge 171:3a7713b1edbc 279 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
AnnaBridge 171:3a7713b1edbc 280 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
AnnaBridge 171:3a7713b1edbc 281 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
AnnaBridge 171:3a7713b1edbc 282 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
AnnaBridge 171:3a7713b1edbc 283 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
AnnaBridge 171:3a7713b1edbc 284 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
AnnaBridge 171:3a7713b1edbc 285 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
AnnaBridge 171:3a7713b1edbc 286 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
AnnaBridge 171:3a7713b1edbc 287 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
AnnaBridge 171:3a7713b1edbc 288 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
AnnaBridge 171:3a7713b1edbc 289 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
AnnaBridge 171:3a7713b1edbc 290 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
AnnaBridge 171:3a7713b1edbc 291 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
AnnaBridge 171:3a7713b1edbc 292 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
AnnaBridge 171:3a7713b1edbc 293 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
AnnaBridge 171:3a7713b1edbc 294 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
AnnaBridge 171:3a7713b1edbc 295 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
AnnaBridge 171:3a7713b1edbc 296 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
AnnaBridge 171:3a7713b1edbc 297 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
AnnaBridge 171:3a7713b1edbc 298 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
AnnaBridge 171:3a7713b1edbc 299 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
AnnaBridge 171:3a7713b1edbc 300 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
AnnaBridge 171:3a7713b1edbc 301 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
AnnaBridge 171:3a7713b1edbc 302 /**
AnnaBridge 171:3a7713b1edbc 303 * @}
AnnaBridge 171:3a7713b1edbc 304 */
AnnaBridge 171:3a7713b1edbc 305
AnnaBridge 171:3a7713b1edbc 306
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 /** @defgroup RCC_MCO_Index RCC MCO Index
AnnaBridge 171:3a7713b1edbc 309 * @{
AnnaBridge 171:3a7713b1edbc 310 */
AnnaBridge 171:3a7713b1edbc 311 #define RCC_MCO1 ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 312 #define RCC_MCO2 ((uint32_t)0x00000001U)
AnnaBridge 171:3a7713b1edbc 313 /**
AnnaBridge 171:3a7713b1edbc 314 * @}
AnnaBridge 171:3a7713b1edbc 315 */
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 /** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
AnnaBridge 171:3a7713b1edbc 318 * @{
AnnaBridge 171:3a7713b1edbc 319 */
AnnaBridge 171:3a7713b1edbc 320 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 321 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
AnnaBridge 171:3a7713b1edbc 322 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
AnnaBridge 171:3a7713b1edbc 323 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
AnnaBridge 171:3a7713b1edbc 324 /**
AnnaBridge 171:3a7713b1edbc 325 * @}
AnnaBridge 171:3a7713b1edbc 326 */
AnnaBridge 171:3a7713b1edbc 327
AnnaBridge 171:3a7713b1edbc 328 /** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
AnnaBridge 171:3a7713b1edbc 329 * @{
AnnaBridge 171:3a7713b1edbc 330 */
AnnaBridge 171:3a7713b1edbc 331 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 332 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
AnnaBridge 171:3a7713b1edbc 333 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
AnnaBridge 171:3a7713b1edbc 334 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
AnnaBridge 171:3a7713b1edbc 335 /**
AnnaBridge 171:3a7713b1edbc 336 * @}
AnnaBridge 171:3a7713b1edbc 337 */
AnnaBridge 171:3a7713b1edbc 338
AnnaBridge 171:3a7713b1edbc 339 /** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
AnnaBridge 171:3a7713b1edbc 340 * @{
AnnaBridge 171:3a7713b1edbc 341 */
AnnaBridge 171:3a7713b1edbc 342 #define RCC_MCODIV_1 ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 343 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
AnnaBridge 171:3a7713b1edbc 344 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
AnnaBridge 171:3a7713b1edbc 345 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
AnnaBridge 171:3a7713b1edbc 346 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
AnnaBridge 171:3a7713b1edbc 347 /**
AnnaBridge 171:3a7713b1edbc 348 * @}
AnnaBridge 171:3a7713b1edbc 349 */
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 /** @defgroup RCC_Interrupt RCC Interrupt
AnnaBridge 171:3a7713b1edbc 352 * @{
AnnaBridge 171:3a7713b1edbc 353 */
AnnaBridge 171:3a7713b1edbc 354 #define RCC_IT_LSIRDY ((uint8_t)0x01U)
AnnaBridge 171:3a7713b1edbc 355 #define RCC_IT_LSERDY ((uint8_t)0x02U)
AnnaBridge 171:3a7713b1edbc 356 #define RCC_IT_HSIRDY ((uint8_t)0x04U)
AnnaBridge 171:3a7713b1edbc 357 #define RCC_IT_HSERDY ((uint8_t)0x08U)
AnnaBridge 171:3a7713b1edbc 358 #define RCC_IT_PLLRDY ((uint8_t)0x10U)
AnnaBridge 171:3a7713b1edbc 359 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
AnnaBridge 171:3a7713b1edbc 360 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40U)
AnnaBridge 171:3a7713b1edbc 361 #define RCC_IT_CSS ((uint8_t)0x80U)
AnnaBridge 171:3a7713b1edbc 362 /**
AnnaBridge 171:3a7713b1edbc 363 * @}
AnnaBridge 171:3a7713b1edbc 364 */
AnnaBridge 171:3a7713b1edbc 365
AnnaBridge 171:3a7713b1edbc 366 /** @defgroup RCC_Flag RCC Flags
AnnaBridge 171:3a7713b1edbc 367 * Elements values convention: 0XXYYYYYb
AnnaBridge 171:3a7713b1edbc 368 * - YYYYY : Flag position in the register
AnnaBridge 171:3a7713b1edbc 369 * - 0XX : Register index
AnnaBridge 171:3a7713b1edbc 370 * - 01: CR register
AnnaBridge 171:3a7713b1edbc 371 * - 10: BDCR register
AnnaBridge 171:3a7713b1edbc 372 * - 11: CSR register
AnnaBridge 171:3a7713b1edbc 373 * @{
AnnaBridge 171:3a7713b1edbc 374 */
AnnaBridge 171:3a7713b1edbc 375 /* Flags in the CR register */
AnnaBridge 171:3a7713b1edbc 376 #define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
AnnaBridge 171:3a7713b1edbc 377 #define RCC_FLAG_HSERDY ((uint8_t)0x31U)
AnnaBridge 171:3a7713b1edbc 378 #define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
AnnaBridge 171:3a7713b1edbc 379 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
AnnaBridge 171:3a7713b1edbc 380 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU)
AnnaBridge 171:3a7713b1edbc 381
AnnaBridge 171:3a7713b1edbc 382 /* Flags in the BDCR register */
AnnaBridge 171:3a7713b1edbc 383 #define RCC_FLAG_LSERDY ((uint8_t)0x41U)
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385 /* Flags in the CSR register */
AnnaBridge 171:3a7713b1edbc 386 #define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
AnnaBridge 171:3a7713b1edbc 387 #define RCC_FLAG_BORRST ((uint8_t)0x79U)
AnnaBridge 171:3a7713b1edbc 388 #define RCC_FLAG_PINRST ((uint8_t)0x7AU)
AnnaBridge 171:3a7713b1edbc 389 #define RCC_FLAG_PORRST ((uint8_t)0x7BU)
AnnaBridge 171:3a7713b1edbc 390 #define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
AnnaBridge 171:3a7713b1edbc 391 #define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
AnnaBridge 171:3a7713b1edbc 392 #define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
AnnaBridge 171:3a7713b1edbc 393 #define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
AnnaBridge 171:3a7713b1edbc 394 /**
AnnaBridge 171:3a7713b1edbc 395 * @}
AnnaBridge 171:3a7713b1edbc 396 */
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 /** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
AnnaBridge 171:3a7713b1edbc 399 * @{
AnnaBridge 171:3a7713b1edbc 400 */
AnnaBridge 171:3a7713b1edbc 401 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
AnnaBridge 171:3a7713b1edbc 402 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
AnnaBridge 171:3a7713b1edbc 403 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
AnnaBridge 171:3a7713b1edbc 404 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
AnnaBridge 171:3a7713b1edbc 405 /**
AnnaBridge 171:3a7713b1edbc 406 * @}
AnnaBridge 171:3a7713b1edbc 407 */
AnnaBridge 171:3a7713b1edbc 408
AnnaBridge 171:3a7713b1edbc 409 /**
AnnaBridge 171:3a7713b1edbc 410 * @}
AnnaBridge 171:3a7713b1edbc 411 */
AnnaBridge 171:3a7713b1edbc 412
AnnaBridge 171:3a7713b1edbc 413 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 414 /** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge 171:3a7713b1edbc 415 * @{
AnnaBridge 171:3a7713b1edbc 416 */
AnnaBridge 171:3a7713b1edbc 417
AnnaBridge 171:3a7713b1edbc 418 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge 171:3a7713b1edbc 419 * @brief Enable or disable the AHB1 peripheral clock.
AnnaBridge 171:3a7713b1edbc 420 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 171:3a7713b1edbc 421 * is disabled and the application software has to enable this clock before
AnnaBridge 171:3a7713b1edbc 422 * using it.
AnnaBridge 171:3a7713b1edbc 423 * @{
AnnaBridge 171:3a7713b1edbc 424 */
AnnaBridge 171:3a7713b1edbc 425 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 426 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 427 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge 171:3a7713b1edbc 428 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 171:3a7713b1edbc 429 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge 171:3a7713b1edbc 430 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 431 } while(0)
AnnaBridge 171:3a7713b1edbc 432
AnnaBridge 171:3a7713b1edbc 433 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 434 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 435 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
AnnaBridge 171:3a7713b1edbc 436 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 171:3a7713b1edbc 437 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
AnnaBridge 171:3a7713b1edbc 438 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 439 } while(0)
AnnaBridge 171:3a7713b1edbc 440
AnnaBridge 171:3a7713b1edbc 441 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge 171:3a7713b1edbc 442 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
AnnaBridge 171:3a7713b1edbc 443
AnnaBridge 171:3a7713b1edbc 444 /**
AnnaBridge 171:3a7713b1edbc 445 * @}
AnnaBridge 171:3a7713b1edbc 446 */
AnnaBridge 171:3a7713b1edbc 447
AnnaBridge 171:3a7713b1edbc 448 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge 171:3a7713b1edbc 449 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge 171:3a7713b1edbc 450 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 171:3a7713b1edbc 451 * is disabled and the application software has to enable this clock before
AnnaBridge 171:3a7713b1edbc 452 * using it.
AnnaBridge 171:3a7713b1edbc 453 * @{
AnnaBridge 171:3a7713b1edbc 454 */
AnnaBridge 171:3a7713b1edbc 455 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 456 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 457 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge 171:3a7713b1edbc 458 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 171:3a7713b1edbc 459 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge 171:3a7713b1edbc 460 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 461 } while(0)
AnnaBridge 171:3a7713b1edbc 462
AnnaBridge 171:3a7713b1edbc 463 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 464 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 465 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge 171:3a7713b1edbc 466 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 171:3a7713b1edbc 467 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge 171:3a7713b1edbc 468 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 469 } while(0)
AnnaBridge 171:3a7713b1edbc 470
AnnaBridge 171:3a7713b1edbc 471 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
AnnaBridge 171:3a7713b1edbc 472 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
AnnaBridge 171:3a7713b1edbc 473 /**
AnnaBridge 171:3a7713b1edbc 474 * @}
AnnaBridge 171:3a7713b1edbc 475 */
AnnaBridge 171:3a7713b1edbc 476
AnnaBridge 171:3a7713b1edbc 477 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge 171:3a7713b1edbc 478 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge 171:3a7713b1edbc 479 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 171:3a7713b1edbc 480 * is disabled and the application software has to enable this clock before
AnnaBridge 171:3a7713b1edbc 481 * using it.
AnnaBridge 171:3a7713b1edbc 482 * @{
AnnaBridge 171:3a7713b1edbc 483 */
AnnaBridge 171:3a7713b1edbc 484 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 485 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 486 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge 171:3a7713b1edbc 487 /* Delay after an RCC peripheral clock enabling */ \
AnnaBridge 171:3a7713b1edbc 488 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge 171:3a7713b1edbc 489 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 490 } while(0)
AnnaBridge 171:3a7713b1edbc 491
AnnaBridge 171:3a7713b1edbc 492 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 /**
AnnaBridge 171:3a7713b1edbc 495 * @}
AnnaBridge 171:3a7713b1edbc 496 */
AnnaBridge 171:3a7713b1edbc 497
AnnaBridge 171:3a7713b1edbc 498 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge 171:3a7713b1edbc 499 * @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge 171:3a7713b1edbc 500 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 171:3a7713b1edbc 501 * is disabled and the application software has to enable this clock before
AnnaBridge 171:3a7713b1edbc 502 * using it.
AnnaBridge 171:3a7713b1edbc 503 * @{
AnnaBridge 171:3a7713b1edbc 504 */
AnnaBridge 171:3a7713b1edbc 505 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 506 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET)
AnnaBridge 171:3a7713b1edbc 507
AnnaBridge 171:3a7713b1edbc 508 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 509 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET)
AnnaBridge 171:3a7713b1edbc 510 /**
AnnaBridge 171:3a7713b1edbc 511 * @}
AnnaBridge 171:3a7713b1edbc 512 */
AnnaBridge 171:3a7713b1edbc 513
AnnaBridge 171:3a7713b1edbc 514 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge 171:3a7713b1edbc 515 * @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge 171:3a7713b1edbc 516 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 171:3a7713b1edbc 517 * is disabled and the application software has to enable this clock before
AnnaBridge 171:3a7713b1edbc 518 * using it.
AnnaBridge 171:3a7713b1edbc 519 * @{
AnnaBridge 171:3a7713b1edbc 520 */
AnnaBridge 171:3a7713b1edbc 521 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 522 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
AnnaBridge 171:3a7713b1edbc 523
AnnaBridge 171:3a7713b1edbc 524 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 525 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
AnnaBridge 171:3a7713b1edbc 526 /**
AnnaBridge 171:3a7713b1edbc 527 * @}
AnnaBridge 171:3a7713b1edbc 528 */
AnnaBridge 171:3a7713b1edbc 529
AnnaBridge 171:3a7713b1edbc 530 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge 171:3a7713b1edbc 531 * @brief EGet the enable or disable status of the APB2 peripheral clock.
AnnaBridge 171:3a7713b1edbc 532 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 171:3a7713b1edbc 533 * is disabled and the application software has to enable this clock before
AnnaBridge 171:3a7713b1edbc 534 * using it.
AnnaBridge 171:3a7713b1edbc 535 * @{
AnnaBridge 171:3a7713b1edbc 536 */
AnnaBridge 171:3a7713b1edbc 537 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 538 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 539 /**
AnnaBridge 171:3a7713b1edbc 540 * @}
AnnaBridge 171:3a7713b1edbc 541 */
AnnaBridge 171:3a7713b1edbc 542
AnnaBridge 171:3a7713b1edbc 543 /** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
AnnaBridge 171:3a7713b1edbc 544 * @brief Force or release AHB peripheral reset.
AnnaBridge 171:3a7713b1edbc 545 * @{
AnnaBridge 171:3a7713b1edbc 546 */
AnnaBridge 171:3a7713b1edbc 547 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 548 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
AnnaBridge 171:3a7713b1edbc 549 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
AnnaBridge 171:3a7713b1edbc 550
AnnaBridge 171:3a7713b1edbc 551 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
AnnaBridge 171:3a7713b1edbc 552 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge 171:3a7713b1edbc 553 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
AnnaBridge 171:3a7713b1edbc 554 /**
AnnaBridge 171:3a7713b1edbc 555 * @}
AnnaBridge 171:3a7713b1edbc 556 */
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge 171:3a7713b1edbc 559 * @brief Force or release APB1 peripheral reset.
AnnaBridge 171:3a7713b1edbc 560 * @{
AnnaBridge 171:3a7713b1edbc 561 */
AnnaBridge 171:3a7713b1edbc 562 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 563 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
AnnaBridge 171:3a7713b1edbc 564 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
AnnaBridge 171:3a7713b1edbc 565
AnnaBridge 171:3a7713b1edbc 566 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
AnnaBridge 171:3a7713b1edbc 567 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
AnnaBridge 171:3a7713b1edbc 568 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
AnnaBridge 171:3a7713b1edbc 569 /**
AnnaBridge 171:3a7713b1edbc 570 * @}
AnnaBridge 171:3a7713b1edbc 571 */
AnnaBridge 171:3a7713b1edbc 572
AnnaBridge 171:3a7713b1edbc 573 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge 171:3a7713b1edbc 574 * @brief Force or release APB2 peripheral reset.
AnnaBridge 171:3a7713b1edbc 575 * @{
AnnaBridge 171:3a7713b1edbc 576 */
AnnaBridge 171:3a7713b1edbc 577 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 578 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
AnnaBridge 171:3a7713b1edbc 579
AnnaBridge 171:3a7713b1edbc 580 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
AnnaBridge 171:3a7713b1edbc 581 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
AnnaBridge 171:3a7713b1edbc 582
AnnaBridge 171:3a7713b1edbc 583 /**
AnnaBridge 171:3a7713b1edbc 584 * @}
AnnaBridge 171:3a7713b1edbc 585 */
AnnaBridge 171:3a7713b1edbc 586
AnnaBridge 171:3a7713b1edbc 587 /** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
AnnaBridge 171:3a7713b1edbc 588 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 171:3a7713b1edbc 589 * power consumption.
AnnaBridge 171:3a7713b1edbc 590 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 171:3a7713b1edbc 591 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 171:3a7713b1edbc 592 * @{
AnnaBridge 171:3a7713b1edbc 593 */
AnnaBridge 171:3a7713b1edbc 594 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge 171:3a7713b1edbc 595 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge 171:3a7713b1edbc 598 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
AnnaBridge 171:3a7713b1edbc 599
AnnaBridge 171:3a7713b1edbc 600 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 171:3a7713b1edbc 601 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 171:3a7713b1edbc 602 * power consumption.
AnnaBridge 171:3a7713b1edbc 603 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 171:3a7713b1edbc 604 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 171:3a7713b1edbc 605 */
AnnaBridge 171:3a7713b1edbc 606 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
AnnaBridge 171:3a7713b1edbc 607 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
AnnaBridge 171:3a7713b1edbc 608
AnnaBridge 171:3a7713b1edbc 609 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
AnnaBridge 171:3a7713b1edbc 610 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
AnnaBridge 171:3a7713b1edbc 611
AnnaBridge 171:3a7713b1edbc 612 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 171:3a7713b1edbc 613 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 171:3a7713b1edbc 614 * power consumption.
AnnaBridge 171:3a7713b1edbc 615 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 171:3a7713b1edbc 616 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 171:3a7713b1edbc 617 */
AnnaBridge 171:3a7713b1edbc 618 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
AnnaBridge 171:3a7713b1edbc 619 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
AnnaBridge 171:3a7713b1edbc 620
AnnaBridge 171:3a7713b1edbc 621 /**
AnnaBridge 171:3a7713b1edbc 622 * @}
AnnaBridge 171:3a7713b1edbc 623 */
AnnaBridge 171:3a7713b1edbc 624
AnnaBridge 171:3a7713b1edbc 625 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status
AnnaBridge 171:3a7713b1edbc 626 * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 171:3a7713b1edbc 627 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 171:3a7713b1edbc 628 * power consumption.
AnnaBridge 171:3a7713b1edbc 629 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 171:3a7713b1edbc 630 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 171:3a7713b1edbc 631 * @{
AnnaBridge 171:3a7713b1edbc 632 */
AnnaBridge 171:3a7713b1edbc 633 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 634 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 635
AnnaBridge 171:3a7713b1edbc 636 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 637 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 638 /**
AnnaBridge 171:3a7713b1edbc 639 * @}
AnnaBridge 171:3a7713b1edbc 640 */
AnnaBridge 171:3a7713b1edbc 641
AnnaBridge 171:3a7713b1edbc 642 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status
AnnaBridge 171:3a7713b1edbc 643 * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 171:3a7713b1edbc 644 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 171:3a7713b1edbc 645 * power consumption.
AnnaBridge 171:3a7713b1edbc 646 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 171:3a7713b1edbc 647 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 171:3a7713b1edbc 648 * @{
AnnaBridge 171:3a7713b1edbc 649 */
AnnaBridge 171:3a7713b1edbc 650 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 651 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 652
AnnaBridge 171:3a7713b1edbc 653 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 654 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 655 /**
AnnaBridge 171:3a7713b1edbc 656 * @}
AnnaBridge 171:3a7713b1edbc 657 */
AnnaBridge 171:3a7713b1edbc 658
AnnaBridge 171:3a7713b1edbc 659 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status
AnnaBridge 171:3a7713b1edbc 660 * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge 171:3a7713b1edbc 661 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge 171:3a7713b1edbc 662 * power consumption.
AnnaBridge 171:3a7713b1edbc 663 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge 171:3a7713b1edbc 664 * @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge 171:3a7713b1edbc 665 * @{
AnnaBridge 171:3a7713b1edbc 666 */
AnnaBridge 171:3a7713b1edbc 667 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 668 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 669 /**
AnnaBridge 171:3a7713b1edbc 670 * @}
AnnaBridge 171:3a7713b1edbc 671 */
AnnaBridge 171:3a7713b1edbc 672
AnnaBridge 171:3a7713b1edbc 673 /** @defgroup RCC_HSI_Configuration HSI Configuration
AnnaBridge 171:3a7713b1edbc 674 * @{
AnnaBridge 171:3a7713b1edbc 675 */
AnnaBridge 171:3a7713b1edbc 676
AnnaBridge 171:3a7713b1edbc 677 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
AnnaBridge 171:3a7713b1edbc 678 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 171:3a7713b1edbc 679 * It is used (enabled by hardware) as system clock source after startup
AnnaBridge 171:3a7713b1edbc 680 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
AnnaBridge 171:3a7713b1edbc 681 * of the HSE used directly or indirectly as system clock (if the Clock
AnnaBridge 171:3a7713b1edbc 682 * Security System CSS is enabled).
AnnaBridge 171:3a7713b1edbc 683 * @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge 171:3a7713b1edbc 684 * you have to select another source of the system clock then stop the HSI.
AnnaBridge 171:3a7713b1edbc 685 * @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge 171:3a7713b1edbc 686 * flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge 171:3a7713b1edbc 687 * system clock source.
AnnaBridge 171:3a7713b1edbc 688 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge 171:3a7713b1edbc 689 * clock cycles.
AnnaBridge 171:3a7713b1edbc 690 */
AnnaBridge 171:3a7713b1edbc 691 #define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION))
AnnaBridge 171:3a7713b1edbc 692 #define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION))
AnnaBridge 171:3a7713b1edbc 693
AnnaBridge 171:3a7713b1edbc 694 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
AnnaBridge 171:3a7713b1edbc 695 * @note The calibration is used to compensate for the variations in voltage
AnnaBridge 171:3a7713b1edbc 696 * and temperature that influence the frequency of the internal HSI RC.
AnnaBridge 171:3a7713b1edbc 697 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value.
AnnaBridge 171:3a7713b1edbc 698 * (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge 171:3a7713b1edbc 699 */
AnnaBridge 171:3a7713b1edbc 700 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
AnnaBridge 171:3a7713b1edbc 701 RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos))
AnnaBridge 171:3a7713b1edbc 702 /**
AnnaBridge 171:3a7713b1edbc 703 * @}
AnnaBridge 171:3a7713b1edbc 704 */
AnnaBridge 171:3a7713b1edbc 705
AnnaBridge 171:3a7713b1edbc 706 /** @defgroup RCC_LSI_Configuration LSI Configuration
AnnaBridge 171:3a7713b1edbc 707 * @{
AnnaBridge 171:3a7713b1edbc 708 */
AnnaBridge 171:3a7713b1edbc 709
AnnaBridge 171:3a7713b1edbc 710 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
AnnaBridge 171:3a7713b1edbc 711 * @note After enabling the LSI, the application software should wait on
AnnaBridge 171:3a7713b1edbc 712 * LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge 171:3a7713b1edbc 713 * be used to clock the IWDG and/or the RTC.
AnnaBridge 171:3a7713b1edbc 714 * @note LSI can not be disabled if the IWDG is running.
AnnaBridge 171:3a7713b1edbc 715 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge 171:3a7713b1edbc 716 * clock cycles.
AnnaBridge 171:3a7713b1edbc 717 */
AnnaBridge 171:3a7713b1edbc 718 #define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION))
AnnaBridge 171:3a7713b1edbc 719 #define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION))
AnnaBridge 171:3a7713b1edbc 720 /**
AnnaBridge 171:3a7713b1edbc 721 * @}
AnnaBridge 171:3a7713b1edbc 722 */
AnnaBridge 171:3a7713b1edbc 723
AnnaBridge 171:3a7713b1edbc 724 /** @defgroup RCC_HSE_Configuration HSE Configuration
AnnaBridge 171:3a7713b1edbc 725 * @{
AnnaBridge 171:3a7713b1edbc 726 */
AnnaBridge 171:3a7713b1edbc 727 /**
AnnaBridge 171:3a7713b1edbc 728 * @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge 171:3a7713b1edbc 729 * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not
AnnaBridge 171:3a7713b1edbc 730 * supported by this macro. User should request a transition to HSE Off
AnnaBridge 171:3a7713b1edbc 731 * first and then HSE On or HSE Bypass.
AnnaBridge 171:3a7713b1edbc 732 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge 171:3a7713b1edbc 733 * software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge 171:3a7713b1edbc 734 * is stable and can be used to clock the PLL and/or system clock.
AnnaBridge 171:3a7713b1edbc 735 * @note HSE state can not be changed if it is used directly or through the
AnnaBridge 171:3a7713b1edbc 736 * PLL as system clock. In this case, you have to select another source
AnnaBridge 171:3a7713b1edbc 737 * of the system clock then change the HSE state (ex. disable it).
AnnaBridge 171:3a7713b1edbc 738 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 171:3a7713b1edbc 739 * @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge 171:3a7713b1edbc 740 * was previously enabled you have to enable it again after calling this
AnnaBridge 171:3a7713b1edbc 741 * function.
AnnaBridge 171:3a7713b1edbc 742 * @param __STATE__ specifies the new state of the HSE.
AnnaBridge 171:3a7713b1edbc 743 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 744 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge 171:3a7713b1edbc 745 * 6 HSE oscillator clock cycles.
AnnaBridge 171:3a7713b1edbc 746 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
AnnaBridge 171:3a7713b1edbc 747 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
AnnaBridge 171:3a7713b1edbc 748 */
AnnaBridge 171:3a7713b1edbc 749 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge 171:3a7713b1edbc 750 do { \
AnnaBridge 171:3a7713b1edbc 751 if ((__STATE__) == RCC_HSE_ON) \
AnnaBridge 171:3a7713b1edbc 752 { \
AnnaBridge 171:3a7713b1edbc 753 SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 171:3a7713b1edbc 754 } \
AnnaBridge 171:3a7713b1edbc 755 else if ((__STATE__) == RCC_HSE_OFF) \
AnnaBridge 171:3a7713b1edbc 756 { \
AnnaBridge 171:3a7713b1edbc 757 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 171:3a7713b1edbc 758 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 171:3a7713b1edbc 759 } \
AnnaBridge 171:3a7713b1edbc 760 else if ((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge 171:3a7713b1edbc 761 { \
AnnaBridge 171:3a7713b1edbc 762 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 171:3a7713b1edbc 763 SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 171:3a7713b1edbc 764 } \
AnnaBridge 171:3a7713b1edbc 765 else \
AnnaBridge 171:3a7713b1edbc 766 { \
AnnaBridge 171:3a7713b1edbc 767 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 171:3a7713b1edbc 768 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 171:3a7713b1edbc 769 } \
AnnaBridge 171:3a7713b1edbc 770 } while(0)
AnnaBridge 171:3a7713b1edbc 771 /**
AnnaBridge 171:3a7713b1edbc 772 * @}
AnnaBridge 171:3a7713b1edbc 773 */
AnnaBridge 171:3a7713b1edbc 774
AnnaBridge 171:3a7713b1edbc 775 /** @defgroup RCC_LSE_Configuration LSE Configuration
AnnaBridge 171:3a7713b1edbc 776 * @{
AnnaBridge 171:3a7713b1edbc 777 */
AnnaBridge 171:3a7713b1edbc 778
AnnaBridge 171:3a7713b1edbc 779 /**
AnnaBridge 171:3a7713b1edbc 780 * @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge 171:3a7713b1edbc 781 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
AnnaBridge 171:3a7713b1edbc 782 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
AnnaBridge 171:3a7713b1edbc 783 * @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge 171:3a7713b1edbc 784 * this domain after reset, you have to enable write access using
AnnaBridge 171:3a7713b1edbc 785 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge 171:3a7713b1edbc 786 * (to be done once after reset).
AnnaBridge 171:3a7713b1edbc 787 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge 171:3a7713b1edbc 788 * software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge 171:3a7713b1edbc 789 * is stable and can be used to clock the RTC.
AnnaBridge 171:3a7713b1edbc 790 * @param __STATE__ specifies the new state of the LSE.
AnnaBridge 171:3a7713b1edbc 791 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 792 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge 171:3a7713b1edbc 793 * 6 LSE oscillator clock cycles.
AnnaBridge 171:3a7713b1edbc 794 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
AnnaBridge 171:3a7713b1edbc 795 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
AnnaBridge 171:3a7713b1edbc 796 */
AnnaBridge 171:3a7713b1edbc 797 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge 171:3a7713b1edbc 798 do { \
AnnaBridge 171:3a7713b1edbc 799 if((__STATE__) == RCC_LSE_ON) \
AnnaBridge 171:3a7713b1edbc 800 { \
AnnaBridge 171:3a7713b1edbc 801 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 171:3a7713b1edbc 802 } \
AnnaBridge 171:3a7713b1edbc 803 else if((__STATE__) == RCC_LSE_OFF) \
AnnaBridge 171:3a7713b1edbc 804 { \
AnnaBridge 171:3a7713b1edbc 805 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 171:3a7713b1edbc 806 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 171:3a7713b1edbc 807 } \
AnnaBridge 171:3a7713b1edbc 808 else if((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge 171:3a7713b1edbc 809 { \
AnnaBridge 171:3a7713b1edbc 810 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 171:3a7713b1edbc 811 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 171:3a7713b1edbc 812 } \
AnnaBridge 171:3a7713b1edbc 813 else \
AnnaBridge 171:3a7713b1edbc 814 { \
AnnaBridge 171:3a7713b1edbc 815 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 171:3a7713b1edbc 816 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 171:3a7713b1edbc 817 } \
AnnaBridge 171:3a7713b1edbc 818 } while(0)
AnnaBridge 171:3a7713b1edbc 819 /**
AnnaBridge 171:3a7713b1edbc 820 * @}
AnnaBridge 171:3a7713b1edbc 821 */
AnnaBridge 171:3a7713b1edbc 822
AnnaBridge 171:3a7713b1edbc 823 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
AnnaBridge 171:3a7713b1edbc 824 * @{
AnnaBridge 171:3a7713b1edbc 825 */
AnnaBridge 171:3a7713b1edbc 826
AnnaBridge 171:3a7713b1edbc 827 /** @brief Macros to enable or disable the RTC clock.
AnnaBridge 171:3a7713b1edbc 828 * @note These macros must be used only after the RTC clock source was selected.
AnnaBridge 171:3a7713b1edbc 829 */
AnnaBridge 171:3a7713b1edbc 830 #define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN))
AnnaBridge 171:3a7713b1edbc 831 #define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN))
AnnaBridge 171:3a7713b1edbc 832
AnnaBridge 171:3a7713b1edbc 833 /** @brief Macros to configure the RTC clock (RTCCLK).
AnnaBridge 171:3a7713b1edbc 834 * @note As the RTC clock configuration bits are in the Backup domain and write
AnnaBridge 171:3a7713b1edbc 835 * access is denied to this domain after reset, you have to enable write
AnnaBridge 171:3a7713b1edbc 836 * access using the Power Backup Access macro before to configure
AnnaBridge 171:3a7713b1edbc 837 * the RTC clock source (to be done once after reset).
AnnaBridge 171:3a7713b1edbc 838 * @note Once the RTC clock is configured it can't be changed unless the
AnnaBridge 171:3a7713b1edbc 839 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
AnnaBridge 171:3a7713b1edbc 840 * a Power On Reset (POR).
AnnaBridge 171:3a7713b1edbc 841 * @param __RTCCLKSource__ specifies the RTC clock source.
AnnaBridge 171:3a7713b1edbc 842 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 843 @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
AnnaBridge 171:3a7713b1edbc 844 * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
AnnaBridge 171:3a7713b1edbc 845 * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
AnnaBridge 171:3a7713b1edbc 846 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
AnnaBridge 171:3a7713b1edbc 847 * as RTC clock, where x:[2,31]
AnnaBridge 171:3a7713b1edbc 848 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge 171:3a7713b1edbc 849 * work in STOP and STANDBY modes, and can be used as wakeup source.
AnnaBridge 171:3a7713b1edbc 850 * However, when the HSE clock is used as RTC clock source, the RTC
AnnaBridge 171:3a7713b1edbc 851 * cannot be used in STOP and STANDBY modes.
AnnaBridge 171:3a7713b1edbc 852 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
AnnaBridge 171:3a7713b1edbc 853 * RTC clock source).
AnnaBridge 171:3a7713b1edbc 854 */
AnnaBridge 171:3a7713b1edbc 855 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
AnnaBridge 171:3a7713b1edbc 856 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
AnnaBridge 171:3a7713b1edbc 857
AnnaBridge 171:3a7713b1edbc 858 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
AnnaBridge 171:3a7713b1edbc 859 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
AnnaBridge 171:3a7713b1edbc 860 } while (0)
AnnaBridge 171:3a7713b1edbc 861
AnnaBridge 171:3a7713b1edbc 862 /** @brief Macro to get the RTC clock source.
AnnaBridge 171:3a7713b1edbc 863 * @retval The clock source can be one of the following values:
AnnaBridge 171:3a7713b1edbc 864 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge 171:3a7713b1edbc 865 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge 171:3a7713b1edbc 866 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge 171:3a7713b1edbc 867 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
AnnaBridge 171:3a7713b1edbc 868 */
AnnaBridge 171:3a7713b1edbc 869 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
AnnaBridge 171:3a7713b1edbc 870
AnnaBridge 171:3a7713b1edbc 871 /**
AnnaBridge 171:3a7713b1edbc 872 * @brief Get the RTC and HSE clock divider (RTCPRE).
AnnaBridge 171:3a7713b1edbc 873 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 874 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
AnnaBridge 171:3a7713b1edbc 875 * as RTC clock, where x:[2,31]
AnnaBridge 171:3a7713b1edbc 876 */
AnnaBridge 171:3a7713b1edbc 877 #define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
AnnaBridge 171:3a7713b1edbc 878
AnnaBridge 171:3a7713b1edbc 879 /** @brief Macros to force or release the Backup domain reset.
AnnaBridge 171:3a7713b1edbc 880 * @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge 171:3a7713b1edbc 881 * and the RTC clock source selection in RCC_CSR register.
AnnaBridge 171:3a7713b1edbc 882 * @note The BKPSRAM is not affected by this reset.
AnnaBridge 171:3a7713b1edbc 883 */
AnnaBridge 171:3a7713b1edbc 884 #define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST))
AnnaBridge 171:3a7713b1edbc 885 #define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST))
AnnaBridge 171:3a7713b1edbc 886 /**
AnnaBridge 171:3a7713b1edbc 887 * @}
AnnaBridge 171:3a7713b1edbc 888 */
AnnaBridge 171:3a7713b1edbc 889
AnnaBridge 171:3a7713b1edbc 890 /** @defgroup RCC_PLL_Configuration PLL Configuration
AnnaBridge 171:3a7713b1edbc 891 * @{
AnnaBridge 171:3a7713b1edbc 892 */
AnnaBridge 171:3a7713b1edbc 893
AnnaBridge 171:3a7713b1edbc 894 /** @brief Macros to enable or disable the main PLL.
AnnaBridge 171:3a7713b1edbc 895 * @note After enabling the main PLL, the application software should wait on
AnnaBridge 171:3a7713b1edbc 896 * PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge 171:3a7713b1edbc 897 * be used as system clock source.
AnnaBridge 171:3a7713b1edbc 898 * @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge 171:3a7713b1edbc 899 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge 171:3a7713b1edbc 900 */
AnnaBridge 171:3a7713b1edbc 901 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge 171:3a7713b1edbc 902 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge 171:3a7713b1edbc 903
AnnaBridge 171:3a7713b1edbc 904 /** @brief Macro to configure the PLL clock source.
AnnaBridge 171:3a7713b1edbc 905 * @note This function must be used only when the main PLL is disabled.
AnnaBridge 171:3a7713b1edbc 906 * @param __PLLSOURCE__ specifies the PLL entry clock source.
AnnaBridge 171:3a7713b1edbc 907 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 908 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge 171:3a7713b1edbc 909 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge 171:3a7713b1edbc 910 *
AnnaBridge 171:3a7713b1edbc 911 */
AnnaBridge 171:3a7713b1edbc 912 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
AnnaBridge 171:3a7713b1edbc 913
AnnaBridge 171:3a7713b1edbc 914 /** @brief Macro to configure the PLL multiplication factor.
AnnaBridge 171:3a7713b1edbc 915 * @note This function must be used only when the main PLL is disabled.
AnnaBridge 171:3a7713b1edbc 916 * @param __PLLM__ specifies the division factor for PLL VCO input clock
AnnaBridge 171:3a7713b1edbc 917 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge 171:3a7713b1edbc 918 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge 171:3a7713b1edbc 919 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge 171:3a7713b1edbc 920 * of 2 MHz to limit PLL jitter.
AnnaBridge 171:3a7713b1edbc 921 *
AnnaBridge 171:3a7713b1edbc 922 */
AnnaBridge 171:3a7713b1edbc 923 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
AnnaBridge 171:3a7713b1edbc 924 /**
AnnaBridge 171:3a7713b1edbc 925 * @}
AnnaBridge 171:3a7713b1edbc 926 */
AnnaBridge 171:3a7713b1edbc 927
AnnaBridge 171:3a7713b1edbc 928 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
AnnaBridge 171:3a7713b1edbc 929 * @{
AnnaBridge 171:3a7713b1edbc 930 */
AnnaBridge 171:3a7713b1edbc 931
AnnaBridge 171:3a7713b1edbc 932 /** @brief Macro to configure the I2S clock source (I2SCLK).
AnnaBridge 171:3a7713b1edbc 933 * @note This function must be called before enabling the I2S APB clock.
AnnaBridge 171:3a7713b1edbc 934 * @param __SOURCE__ specifies the I2S clock source.
AnnaBridge 171:3a7713b1edbc 935 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 936 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
AnnaBridge 171:3a7713b1edbc 937 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
AnnaBridge 171:3a7713b1edbc 938 * used as I2S clock source.
AnnaBridge 171:3a7713b1edbc 939 */
AnnaBridge 171:3a7713b1edbc 940 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \
AnnaBridge 171:3a7713b1edbc 941 RCC->CFGR |= (__SOURCE__); \
AnnaBridge 171:3a7713b1edbc 942 }while(0)
AnnaBridge 171:3a7713b1edbc 943
AnnaBridge 171:3a7713b1edbc 944 /** @brief Macros to enable or disable the PLLI2S.
AnnaBridge 171:3a7713b1edbc 945 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge 171:3a7713b1edbc 946 */
AnnaBridge 171:3a7713b1edbc 947 #define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON))
AnnaBridge 171:3a7713b1edbc 948 #define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON))
AnnaBridge 171:3a7713b1edbc 949 /**
AnnaBridge 171:3a7713b1edbc 950 * @}
AnnaBridge 171:3a7713b1edbc 951 */
AnnaBridge 171:3a7713b1edbc 952
AnnaBridge 171:3a7713b1edbc 953 /** @defgroup RCC_Get_Clock_source Get Clock source
AnnaBridge 171:3a7713b1edbc 954 * @{
AnnaBridge 171:3a7713b1edbc 955 */
AnnaBridge 171:3a7713b1edbc 956 /**
AnnaBridge 171:3a7713b1edbc 957 * @brief Macro to configure the system clock source.
AnnaBridge 171:3a7713b1edbc 958 * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
AnnaBridge 171:3a7713b1edbc 959 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 960 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
AnnaBridge 171:3a7713b1edbc 961 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
AnnaBridge 171:3a7713b1edbc 962 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
AnnaBridge 171:3a7713b1edbc 963 */
AnnaBridge 171:3a7713b1edbc 964 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
AnnaBridge 171:3a7713b1edbc 965
AnnaBridge 171:3a7713b1edbc 966 /** @brief Macro to get the clock source used as system clock.
AnnaBridge 171:3a7713b1edbc 967 * @retval The clock source used as system clock. The returned value can be one
AnnaBridge 171:3a7713b1edbc 968 * of the following:
AnnaBridge 171:3a7713b1edbc 969 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
AnnaBridge 171:3a7713b1edbc 970 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
AnnaBridge 171:3a7713b1edbc 971 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
AnnaBridge 171:3a7713b1edbc 972 */
AnnaBridge 171:3a7713b1edbc 973 #define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
AnnaBridge 171:3a7713b1edbc 974
AnnaBridge 171:3a7713b1edbc 975 /**
AnnaBridge 171:3a7713b1edbc 976 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
AnnaBridge 171:3a7713b1edbc 977 * @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge 171:3a7713b1edbc 978 * this domain after reset, you have to enable write access using
AnnaBridge 171:3a7713b1edbc 979 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge 171:3a7713b1edbc 980 * (to be done once after reset).
AnnaBridge 171:3a7713b1edbc 981 * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
AnnaBridge 171:3a7713b1edbc 982 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 983 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
AnnaBridge 171:3a7713b1edbc 984 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
AnnaBridge 171:3a7713b1edbc 985 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
AnnaBridge 171:3a7713b1edbc 986 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
AnnaBridge 171:3a7713b1edbc 987 * @retval None
AnnaBridge 171:3a7713b1edbc 988 */
AnnaBridge 171:3a7713b1edbc 989 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \
AnnaBridge 171:3a7713b1edbc 990 (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) ))
AnnaBridge 171:3a7713b1edbc 991
AnnaBridge 171:3a7713b1edbc 992 /** @brief Macro to get the oscillator used as PLL clock source.
AnnaBridge 171:3a7713b1edbc 993 * @retval The oscillator used as PLL clock source. The returned value can be one
AnnaBridge 171:3a7713b1edbc 994 * of the following:
AnnaBridge 171:3a7713b1edbc 995 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
AnnaBridge 171:3a7713b1edbc 996 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
AnnaBridge 171:3a7713b1edbc 997 */
AnnaBridge 171:3a7713b1edbc 998 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
AnnaBridge 171:3a7713b1edbc 999 /**
AnnaBridge 171:3a7713b1edbc 1000 * @}
AnnaBridge 171:3a7713b1edbc 1001 */
AnnaBridge 171:3a7713b1edbc 1002
AnnaBridge 171:3a7713b1edbc 1003 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
AnnaBridge 171:3a7713b1edbc 1004 * @{
AnnaBridge 171:3a7713b1edbc 1005 */
AnnaBridge 171:3a7713b1edbc 1006
AnnaBridge 171:3a7713b1edbc 1007 /** @brief Macro to configure the MCO1 clock.
AnnaBridge 171:3a7713b1edbc 1008 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge 171:3a7713b1edbc 1009 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1010 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
AnnaBridge 171:3a7713b1edbc 1011 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
AnnaBridge 171:3a7713b1edbc 1012 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
AnnaBridge 171:3a7713b1edbc 1013 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
AnnaBridge 171:3a7713b1edbc 1014 * @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge 171:3a7713b1edbc 1015 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1016 * @arg RCC_MCODIV_1: no division applied to MCOx clock
AnnaBridge 171:3a7713b1edbc 1017 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
AnnaBridge 171:3a7713b1edbc 1018 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
AnnaBridge 171:3a7713b1edbc 1019 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
AnnaBridge 171:3a7713b1edbc 1020 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
AnnaBridge 171:3a7713b1edbc 1021 */
AnnaBridge 171:3a7713b1edbc 1022
AnnaBridge 171:3a7713b1edbc 1023 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge 171:3a7713b1edbc 1024 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
AnnaBridge 171:3a7713b1edbc 1025
AnnaBridge 171:3a7713b1edbc 1026 /** @brief Macro to configure the MCO2 clock.
AnnaBridge 171:3a7713b1edbc 1027 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge 171:3a7713b1edbc 1028 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1029 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
AnnaBridge 171:3a7713b1edbc 1030 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
AnnaBridge 171:3a7713b1edbc 1031 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
AnnaBridge 171:3a7713b1edbc 1032 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
AnnaBridge 171:3a7713b1edbc 1033 * @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge 171:3a7713b1edbc 1034 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1035 * @arg RCC_MCODIV_1: no division applied to MCOx clock
AnnaBridge 171:3a7713b1edbc 1036 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
AnnaBridge 171:3a7713b1edbc 1037 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
AnnaBridge 171:3a7713b1edbc 1038 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
AnnaBridge 171:3a7713b1edbc 1039 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
AnnaBridge 171:3a7713b1edbc 1040 */
AnnaBridge 171:3a7713b1edbc 1041
AnnaBridge 171:3a7713b1edbc 1042 #define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge 171:3a7713b1edbc 1043 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3)));
AnnaBridge 171:3a7713b1edbc 1044 /**
AnnaBridge 171:3a7713b1edbc 1045 * @}
AnnaBridge 171:3a7713b1edbc 1046 */
AnnaBridge 171:3a7713b1edbc 1047
AnnaBridge 171:3a7713b1edbc 1048 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge 171:3a7713b1edbc 1049 * @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge 171:3a7713b1edbc 1050 * @{
AnnaBridge 171:3a7713b1edbc 1051 */
AnnaBridge 171:3a7713b1edbc 1052
AnnaBridge 171:3a7713b1edbc 1053 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
AnnaBridge 171:3a7713b1edbc 1054 * the selected interrupts).
AnnaBridge 171:3a7713b1edbc 1055 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
AnnaBridge 171:3a7713b1edbc 1056 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 1057 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
AnnaBridge 171:3a7713b1edbc 1058 * @arg RCC_IT_LSERDY: LSE ready interrupt.
AnnaBridge 171:3a7713b1edbc 1059 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
AnnaBridge 171:3a7713b1edbc 1060 * @arg RCC_IT_HSERDY: HSE ready interrupt.
AnnaBridge 171:3a7713b1edbc 1061 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
AnnaBridge 171:3a7713b1edbc 1062 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
AnnaBridge 171:3a7713b1edbc 1063 */
AnnaBridge 171:3a7713b1edbc 1064 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 1065
AnnaBridge 171:3a7713b1edbc 1066 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
AnnaBridge 171:3a7713b1edbc 1067 * the selected interrupts).
AnnaBridge 171:3a7713b1edbc 1068 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
AnnaBridge 171:3a7713b1edbc 1069 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 1070 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
AnnaBridge 171:3a7713b1edbc 1071 * @arg RCC_IT_LSERDY: LSE ready interrupt.
AnnaBridge 171:3a7713b1edbc 1072 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
AnnaBridge 171:3a7713b1edbc 1073 * @arg RCC_IT_HSERDY: HSE ready interrupt.
AnnaBridge 171:3a7713b1edbc 1074 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
AnnaBridge 171:3a7713b1edbc 1075 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
AnnaBridge 171:3a7713b1edbc 1076 */
AnnaBridge 171:3a7713b1edbc 1077 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
AnnaBridge 171:3a7713b1edbc 1078
AnnaBridge 171:3a7713b1edbc 1079 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
AnnaBridge 171:3a7713b1edbc 1080 * bits to clear the selected interrupt pending bits.
AnnaBridge 171:3a7713b1edbc 1081 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge 171:3a7713b1edbc 1082 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 1083 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
AnnaBridge 171:3a7713b1edbc 1084 * @arg RCC_IT_LSERDY: LSE ready interrupt.
AnnaBridge 171:3a7713b1edbc 1085 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
AnnaBridge 171:3a7713b1edbc 1086 * @arg RCC_IT_HSERDY: HSE ready interrupt.
AnnaBridge 171:3a7713b1edbc 1087 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
AnnaBridge 171:3a7713b1edbc 1088 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
AnnaBridge 171:3a7713b1edbc 1089 * @arg RCC_IT_CSS: Clock Security System interrupt
AnnaBridge 171:3a7713b1edbc 1090 */
AnnaBridge 171:3a7713b1edbc 1091 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 1092
AnnaBridge 171:3a7713b1edbc 1093 /** @brief Check the RCC's interrupt has occurred or not.
AnnaBridge 171:3a7713b1edbc 1094 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
AnnaBridge 171:3a7713b1edbc 1095 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1096 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
AnnaBridge 171:3a7713b1edbc 1097 * @arg RCC_IT_LSERDY: LSE ready interrupt.
AnnaBridge 171:3a7713b1edbc 1098 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
AnnaBridge 171:3a7713b1edbc 1099 * @arg RCC_IT_HSERDY: HSE ready interrupt.
AnnaBridge 171:3a7713b1edbc 1100 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
AnnaBridge 171:3a7713b1edbc 1101 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
AnnaBridge 171:3a7713b1edbc 1102 * @arg RCC_IT_CSS: Clock Security System interrupt
AnnaBridge 171:3a7713b1edbc 1103 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 1104 */
AnnaBridge 171:3a7713b1edbc 1105 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 1106
AnnaBridge 171:3a7713b1edbc 1107 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
AnnaBridge 171:3a7713b1edbc 1108 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
AnnaBridge 171:3a7713b1edbc 1109 */
AnnaBridge 171:3a7713b1edbc 1110 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
AnnaBridge 171:3a7713b1edbc 1111
AnnaBridge 171:3a7713b1edbc 1112 /** @brief Check RCC flag is set or not.
AnnaBridge 171:3a7713b1edbc 1113 * @param __FLAG__ specifies the flag to check.
AnnaBridge 171:3a7713b1edbc 1114 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1115 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
AnnaBridge 171:3a7713b1edbc 1116 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
AnnaBridge 171:3a7713b1edbc 1117 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
AnnaBridge 171:3a7713b1edbc 1118 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
AnnaBridge 171:3a7713b1edbc 1119 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
AnnaBridge 171:3a7713b1edbc 1120 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
AnnaBridge 171:3a7713b1edbc 1121 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
AnnaBridge 171:3a7713b1edbc 1122 * @arg RCC_FLAG_PINRST: Pin reset.
AnnaBridge 171:3a7713b1edbc 1123 * @arg RCC_FLAG_PORRST: POR/PDR reset.
AnnaBridge 171:3a7713b1edbc 1124 * @arg RCC_FLAG_SFTRST: Software reset.
AnnaBridge 171:3a7713b1edbc 1125 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
AnnaBridge 171:3a7713b1edbc 1126 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
AnnaBridge 171:3a7713b1edbc 1127 * @arg RCC_FLAG_LPWRRST: Low Power reset.
AnnaBridge 171:3a7713b1edbc 1128 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 1129 */
AnnaBridge 171:3a7713b1edbc 1130 #define RCC_FLAG_MASK ((uint8_t)0x1F)
AnnaBridge 171:3a7713b1edbc 1131 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
AnnaBridge 171:3a7713b1edbc 1132
AnnaBridge 171:3a7713b1edbc 1133 /**
AnnaBridge 171:3a7713b1edbc 1134 * @}
AnnaBridge 171:3a7713b1edbc 1135 */
AnnaBridge 171:3a7713b1edbc 1136
AnnaBridge 171:3a7713b1edbc 1137 /**
AnnaBridge 171:3a7713b1edbc 1138 * @}
AnnaBridge 171:3a7713b1edbc 1139 */
AnnaBridge 171:3a7713b1edbc 1140
AnnaBridge 171:3a7713b1edbc 1141 /* Include RCC HAL Extension module */
AnnaBridge 171:3a7713b1edbc 1142 #include "stm32f7xx_hal_rcc_ex.h"
AnnaBridge 171:3a7713b1edbc 1143
AnnaBridge 171:3a7713b1edbc 1144 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1145 /** @addtogroup RCC_Exported_Functions
AnnaBridge 171:3a7713b1edbc 1146 * @{
AnnaBridge 171:3a7713b1edbc 1147 */
AnnaBridge 171:3a7713b1edbc 1148
AnnaBridge 171:3a7713b1edbc 1149 /** @addtogroup RCC_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 1150 * @{
AnnaBridge 171:3a7713b1edbc 1151 */
AnnaBridge 171:3a7713b1edbc 1152 /* Initialization and de-initialization functions ******************************/
AnnaBridge 171:3a7713b1edbc 1153 HAL_StatusTypeDef HAL_RCC_DeInit(void);
AnnaBridge 171:3a7713b1edbc 1154 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge 171:3a7713b1edbc 1155 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge 171:3a7713b1edbc 1156 /**
AnnaBridge 171:3a7713b1edbc 1157 * @}
AnnaBridge 171:3a7713b1edbc 1158 */
AnnaBridge 171:3a7713b1edbc 1159
AnnaBridge 171:3a7713b1edbc 1160 /** @addtogroup RCC_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 1161 * @{
AnnaBridge 171:3a7713b1edbc 1162 */
AnnaBridge 171:3a7713b1edbc 1163 /* Peripheral Control functions ************************************************/
AnnaBridge 171:3a7713b1edbc 1164 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge 171:3a7713b1edbc 1165 void HAL_RCC_EnableCSS(void);
AnnaBridge 171:3a7713b1edbc 1166 void HAL_RCC_DisableCSS(void);
AnnaBridge 171:3a7713b1edbc 1167 uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge 171:3a7713b1edbc 1168 uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge 171:3a7713b1edbc 1169 uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge 171:3a7713b1edbc 1170 uint32_t HAL_RCC_GetPCLK2Freq(void);
AnnaBridge 171:3a7713b1edbc 1171 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge 171:3a7713b1edbc 1172 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
AnnaBridge 171:3a7713b1edbc 1173
AnnaBridge 171:3a7713b1edbc 1174 /* CSS NMI IRQ handler */
AnnaBridge 171:3a7713b1edbc 1175 void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge 171:3a7713b1edbc 1176
AnnaBridge 171:3a7713b1edbc 1177 /* User Callbacks in non blocking mode (IT mode) */
AnnaBridge 171:3a7713b1edbc 1178 void HAL_RCC_CSSCallback(void);
AnnaBridge 171:3a7713b1edbc 1179 /**
AnnaBridge 171:3a7713b1edbc 1180 * @}
AnnaBridge 171:3a7713b1edbc 1181 */
AnnaBridge 171:3a7713b1edbc 1182
AnnaBridge 171:3a7713b1edbc 1183 /**
AnnaBridge 171:3a7713b1edbc 1184 * @}
AnnaBridge 171:3a7713b1edbc 1185 */
AnnaBridge 171:3a7713b1edbc 1186
AnnaBridge 171:3a7713b1edbc 1187 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1188 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1189 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1190 /** @defgroup RCC_Private_Constants RCC Private Constants
AnnaBridge 171:3a7713b1edbc 1191 * @{
AnnaBridge 171:3a7713b1edbc 1192 */
AnnaBridge 171:3a7713b1edbc 1193 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge 171:3a7713b1edbc 1194 #define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
AnnaBridge 171:3a7713b1edbc 1195 #define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
AnnaBridge 171:3a7713b1edbc 1196 #define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
AnnaBridge 171:3a7713b1edbc 1197 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
AnnaBridge 171:3a7713b1edbc 1198 #define PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */
AnnaBridge 171:3a7713b1edbc 1199 #define PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */
AnnaBridge 171:3a7713b1edbc 1200
AnnaBridge 171:3a7713b1edbc 1201 /** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
AnnaBridge 171:3a7713b1edbc 1202 * @brief RCC registers bit address alias
AnnaBridge 171:3a7713b1edbc 1203 * @{
AnnaBridge 171:3a7713b1edbc 1204 */
AnnaBridge 171:3a7713b1edbc 1205 /* CIR register byte 2 (Bits[15:8]) base address */
AnnaBridge 171:3a7713b1edbc 1206 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
AnnaBridge 171:3a7713b1edbc 1207
AnnaBridge 171:3a7713b1edbc 1208 /* CIR register byte 3 (Bits[23:16]) base address */
AnnaBridge 171:3a7713b1edbc 1209 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
AnnaBridge 171:3a7713b1edbc 1210
AnnaBridge 171:3a7713b1edbc 1211 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
AnnaBridge 171:3a7713b1edbc 1212 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge 171:3a7713b1edbc 1213 /**
AnnaBridge 171:3a7713b1edbc 1214 * @}
AnnaBridge 171:3a7713b1edbc 1215 */
AnnaBridge 171:3a7713b1edbc 1216 /**
AnnaBridge 171:3a7713b1edbc 1217 * @}
AnnaBridge 171:3a7713b1edbc 1218 */
AnnaBridge 171:3a7713b1edbc 1219
AnnaBridge 171:3a7713b1edbc 1220 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1221 /** @addtogroup RCC_Private_Macros RCC Private Macros
AnnaBridge 171:3a7713b1edbc 1222 * @{
AnnaBridge 171:3a7713b1edbc 1223 */
AnnaBridge 171:3a7713b1edbc 1224
AnnaBridge 171:3a7713b1edbc 1225 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
AnnaBridge 171:3a7713b1edbc 1226 * @{
AnnaBridge 171:3a7713b1edbc 1227 */
AnnaBridge 171:3a7713b1edbc 1228 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
AnnaBridge 171:3a7713b1edbc 1229
AnnaBridge 171:3a7713b1edbc 1230 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
AnnaBridge 171:3a7713b1edbc 1231 ((HSE) == RCC_HSE_BYPASS))
AnnaBridge 171:3a7713b1edbc 1232
AnnaBridge 171:3a7713b1edbc 1233 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
AnnaBridge 171:3a7713b1edbc 1234 ((LSE) == RCC_LSE_BYPASS))
AnnaBridge 171:3a7713b1edbc 1235
AnnaBridge 171:3a7713b1edbc 1236 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
AnnaBridge 171:3a7713b1edbc 1237
AnnaBridge 171:3a7713b1edbc 1238 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
AnnaBridge 171:3a7713b1edbc 1239
AnnaBridge 171:3a7713b1edbc 1240 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
AnnaBridge 171:3a7713b1edbc 1241
AnnaBridge 171:3a7713b1edbc 1242 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
AnnaBridge 171:3a7713b1edbc 1243 ((SOURCE) == RCC_PLLSOURCE_HSE))
AnnaBridge 171:3a7713b1edbc 1244
AnnaBridge 171:3a7713b1edbc 1245 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
AnnaBridge 171:3a7713b1edbc 1246 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
AnnaBridge 171:3a7713b1edbc 1247 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge 171:3a7713b1edbc 1248 #define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
AnnaBridge 171:3a7713b1edbc 1249
AnnaBridge 171:3a7713b1edbc 1250 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
AnnaBridge 171:3a7713b1edbc 1251
AnnaBridge 171:3a7713b1edbc 1252 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \
AnnaBridge 171:3a7713b1edbc 1253 ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8))
AnnaBridge 171:3a7713b1edbc 1254 #define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
AnnaBridge 171:3a7713b1edbc 1255
AnnaBridge 171:3a7713b1edbc 1256 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
AnnaBridge 171:3a7713b1edbc 1257 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
AnnaBridge 171:3a7713b1edbc 1258 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
AnnaBridge 171:3a7713b1edbc 1259 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
AnnaBridge 171:3a7713b1edbc 1260 ((HCLK) == RCC_SYSCLK_DIV512))
AnnaBridge 171:3a7713b1edbc 1261
AnnaBridge 171:3a7713b1edbc 1262 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
AnnaBridge 171:3a7713b1edbc 1263
AnnaBridge 171:3a7713b1edbc 1264 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
AnnaBridge 171:3a7713b1edbc 1265 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
AnnaBridge 171:3a7713b1edbc 1266 ((PCLK) == RCC_HCLK_DIV16))
AnnaBridge 171:3a7713b1edbc 1267
AnnaBridge 171:3a7713b1edbc 1268 #define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2))
AnnaBridge 171:3a7713b1edbc 1269
AnnaBridge 171:3a7713b1edbc 1270
AnnaBridge 171:3a7713b1edbc 1271 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
AnnaBridge 171:3a7713b1edbc 1272 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
AnnaBridge 171:3a7713b1edbc 1273
AnnaBridge 171:3a7713b1edbc 1274 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
AnnaBridge 171:3a7713b1edbc 1275 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
AnnaBridge 171:3a7713b1edbc 1276
AnnaBridge 171:3a7713b1edbc 1277 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
AnnaBridge 171:3a7713b1edbc 1278 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
AnnaBridge 171:3a7713b1edbc 1279 ((DIV) == RCC_MCODIV_5))
AnnaBridge 171:3a7713b1edbc 1280 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
AnnaBridge 171:3a7713b1edbc 1281
AnnaBridge 171:3a7713b1edbc 1282 #define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
AnnaBridge 171:3a7713b1edbc 1283 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
AnnaBridge 171:3a7713b1edbc 1284 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
AnnaBridge 171:3a7713b1edbc 1285 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
AnnaBridge 171:3a7713b1edbc 1286 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
AnnaBridge 171:3a7713b1edbc 1287 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
AnnaBridge 171:3a7713b1edbc 1288 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
AnnaBridge 171:3a7713b1edbc 1289 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
AnnaBridge 171:3a7713b1edbc 1290 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
AnnaBridge 171:3a7713b1edbc 1291 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
AnnaBridge 171:3a7713b1edbc 1292 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
AnnaBridge 171:3a7713b1edbc 1293 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
AnnaBridge 171:3a7713b1edbc 1294 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
AnnaBridge 171:3a7713b1edbc 1295 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
AnnaBridge 171:3a7713b1edbc 1296 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
AnnaBridge 171:3a7713b1edbc 1297 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31))
AnnaBridge 171:3a7713b1edbc 1298
AnnaBridge 171:3a7713b1edbc 1299
AnnaBridge 171:3a7713b1edbc 1300 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \
AnnaBridge 171:3a7713b1edbc 1301 ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \
AnnaBridge 171:3a7713b1edbc 1302 ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \
AnnaBridge 171:3a7713b1edbc 1303 ((DRIVE) == RCC_LSEDRIVE_HIGH))
AnnaBridge 171:3a7713b1edbc 1304 /**
AnnaBridge 171:3a7713b1edbc 1305 * @}
AnnaBridge 171:3a7713b1edbc 1306 */
AnnaBridge 171:3a7713b1edbc 1307
AnnaBridge 171:3a7713b1edbc 1308 /**
AnnaBridge 171:3a7713b1edbc 1309 * @}
AnnaBridge 171:3a7713b1edbc 1310 */
AnnaBridge 171:3a7713b1edbc 1311
AnnaBridge 171:3a7713b1edbc 1312 /**
AnnaBridge 171:3a7713b1edbc 1313 * @}
AnnaBridge 171:3a7713b1edbc 1314 */
AnnaBridge 171:3a7713b1edbc 1315
AnnaBridge 171:3a7713b1edbc 1316 /**
AnnaBridge 171:3a7713b1edbc 1317 * @}
AnnaBridge 171:3a7713b1edbc 1318 */
AnnaBridge 171:3a7713b1edbc 1319
AnnaBridge 171:3a7713b1edbc 1320 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 1321 }
AnnaBridge 171:3a7713b1edbc 1322 #endif
AnnaBridge 171:3a7713b1edbc 1323
AnnaBridge 171:3a7713b1edbc 1324 #endif /* __STM32F7xx_HAL_RCC_H */
AnnaBridge 171:3a7713b1edbc 1325
AnnaBridge 171:3a7713b1edbc 1326 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/