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TARGET_DISCO_F746NG/TOOLCHAIN_IAR/stm32f7xx_hal_pwr_ex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f7xx_hal_pwr_ex.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of PWR HAL Extension module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F7xx_HAL_PWR_EX_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F7xx_HAL_PWR_EX_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32f7xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32F7xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /** @addtogroup PWREx
AnnaBridge 171:3a7713b1edbc 52 * @{
AnnaBridge 171:3a7713b1edbc 53 */
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 56 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 57 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
AnnaBridge 171:3a7713b1edbc 58 * @{
AnnaBridge 171:3a7713b1edbc 59 */
AnnaBridge 171:3a7713b1edbc 60 /** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins
AnnaBridge 171:3a7713b1edbc 61 * @{
AnnaBridge 171:3a7713b1edbc 62 */
AnnaBridge 171:3a7713b1edbc 63 #define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1
AnnaBridge 171:3a7713b1edbc 64 #define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2
AnnaBridge 171:3a7713b1edbc 65 #define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3
AnnaBridge 171:3a7713b1edbc 66 #define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4
AnnaBridge 171:3a7713b1edbc 67 #define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5
AnnaBridge 171:3a7713b1edbc 68 #define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6
AnnaBridge 171:3a7713b1edbc 69 #define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1
AnnaBridge 171:3a7713b1edbc 70 #define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2
AnnaBridge 171:3a7713b1edbc 71 #define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3
AnnaBridge 171:3a7713b1edbc 72 #define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4
AnnaBridge 171:3a7713b1edbc 73 #define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5
AnnaBridge 171:3a7713b1edbc 74 #define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6
AnnaBridge 171:3a7713b1edbc 75 #define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1)
AnnaBridge 171:3a7713b1edbc 76 #define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2)
AnnaBridge 171:3a7713b1edbc 77 #define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3)
AnnaBridge 171:3a7713b1edbc 78 #define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4)
AnnaBridge 171:3a7713b1edbc 79 #define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5)
AnnaBridge 171:3a7713b1edbc 80 #define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6)
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 /**
AnnaBridge 171:3a7713b1edbc 83 * @}
AnnaBridge 171:3a7713b1edbc 84 */
AnnaBridge 171:3a7713b1edbc 85
AnnaBridge 171:3a7713b1edbc 86 /** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
AnnaBridge 171:3a7713b1edbc 87 * @{
AnnaBridge 171:3a7713b1edbc 88 */
AnnaBridge 171:3a7713b1edbc 89 #define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS
AnnaBridge 171:3a7713b1edbc 90 #define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS))
AnnaBridge 171:3a7713b1edbc 91 /**
AnnaBridge 171:3a7713b1edbc 92 * @}
AnnaBridge 171:3a7713b1edbc 93 */
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 /** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
AnnaBridge 171:3a7713b1edbc 96 * @{
AnnaBridge 171:3a7713b1edbc 97 */
AnnaBridge 171:3a7713b1edbc 98 #define PWR_FLAG_ODRDY PWR_CSR1_ODRDY
AnnaBridge 171:3a7713b1edbc 99 #define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY
AnnaBridge 171:3a7713b1edbc 100 #define PWR_FLAG_UDRDY PWR_CSR1_UDRDY
AnnaBridge 171:3a7713b1edbc 101 /**
AnnaBridge 171:3a7713b1edbc 102 * @}
AnnaBridge 171:3a7713b1edbc 103 */
AnnaBridge 171:3a7713b1edbc 104
AnnaBridge 171:3a7713b1edbc 105 /** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags
AnnaBridge 171:3a7713b1edbc 106 * @{
AnnaBridge 171:3a7713b1edbc 107 */
AnnaBridge 171:3a7713b1edbc 108 #define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1
AnnaBridge 171:3a7713b1edbc 109 #define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2
AnnaBridge 171:3a7713b1edbc 110 #define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3
AnnaBridge 171:3a7713b1edbc 111 #define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4
AnnaBridge 171:3a7713b1edbc 112 #define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5
AnnaBridge 171:3a7713b1edbc 113 #define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6
AnnaBridge 171:3a7713b1edbc 114 /**
AnnaBridge 171:3a7713b1edbc 115 * @}
AnnaBridge 171:3a7713b1edbc 116 */
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 /**
AnnaBridge 171:3a7713b1edbc 119 * @}
AnnaBridge 171:3a7713b1edbc 120 */
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 123 /** @defgroup PWREx_Exported_Macro PWREx Exported Macro
AnnaBridge 171:3a7713b1edbc 124 * @{
AnnaBridge 171:3a7713b1edbc 125 */
AnnaBridge 171:3a7713b1edbc 126 /** @brief Macros to enable or disable the Over drive mode.
AnnaBridge 171:3a7713b1edbc 127 */
AnnaBridge 171:3a7713b1edbc 128 #define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN)
AnnaBridge 171:3a7713b1edbc 129 #define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN))
AnnaBridge 171:3a7713b1edbc 130
AnnaBridge 171:3a7713b1edbc 131 /** @brief Macros to enable or disable the Over drive switching.
AnnaBridge 171:3a7713b1edbc 132 */
AnnaBridge 171:3a7713b1edbc 133 #define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN)
AnnaBridge 171:3a7713b1edbc 134 #define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN))
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136 /** @brief Macros to enable or disable the Under drive mode.
AnnaBridge 171:3a7713b1edbc 137 * @note This mode is enabled only with STOP low power mode.
AnnaBridge 171:3a7713b1edbc 138 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
AnnaBridge 171:3a7713b1edbc 139 * mode is only available when the main regulator or the low power regulator
AnnaBridge 171:3a7713b1edbc 140 * is in low voltage mode.
AnnaBridge 171:3a7713b1edbc 141 * @note If the Under-drive mode was enabled, it is automatically disabled after
AnnaBridge 171:3a7713b1edbc 142 * exiting Stop mode.
AnnaBridge 171:3a7713b1edbc 143 * When the voltage regulator operates in Under-drive mode, an additional
AnnaBridge 171:3a7713b1edbc 144 * startup delay is induced when waking up from Stop mode.
AnnaBridge 171:3a7713b1edbc 145 */
AnnaBridge 171:3a7713b1edbc 146 #define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN)
AnnaBridge 171:3a7713b1edbc 147 #define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN))
AnnaBridge 171:3a7713b1edbc 148
AnnaBridge 171:3a7713b1edbc 149 /** @brief Check PWR flag is set or not.
AnnaBridge 171:3a7713b1edbc 150 * @param __FLAG__ specifies the flag to check.
AnnaBridge 171:3a7713b1edbc 151 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 152 * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
AnnaBridge 171:3a7713b1edbc 153 * is ready
AnnaBridge 171:3a7713b1edbc 154 * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
AnnaBridge 171:3a7713b1edbc 155 * switching is ready
AnnaBridge 171:3a7713b1edbc 156 * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
AnnaBridge 171:3a7713b1edbc 157 * is enabled in Stop mode
AnnaBridge 171:3a7713b1edbc 158 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 159 */
AnnaBridge 171:3a7713b1edbc 160 #define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__))
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 /** @brief Clear the Under-Drive Ready flag.
AnnaBridge 171:3a7713b1edbc 163 */
AnnaBridge 171:3a7713b1edbc 164 #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY)
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 /** @brief Check Wake Up flag is set or not.
AnnaBridge 171:3a7713b1edbc 167 * @param __WUFLAG__ specifies the Wake Up flag to check.
AnnaBridge 171:3a7713b1edbc 168 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 169 * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
AnnaBridge 171:3a7713b1edbc 170 * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
AnnaBridge 171:3a7713b1edbc 171 * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
AnnaBridge 171:3a7713b1edbc 172 * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
AnnaBridge 171:3a7713b1edbc 173 * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
AnnaBridge 171:3a7713b1edbc 174 * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11
AnnaBridge 171:3a7713b1edbc 175 */
AnnaBridge 171:3a7713b1edbc 176 #define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__))
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 /** @brief Clear the WakeUp pins flags.
AnnaBridge 171:3a7713b1edbc 179 * @param __WUFLAG__ specifies the Wake Up pin flag to clear.
AnnaBridge 171:3a7713b1edbc 180 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 181 * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0
AnnaBridge 171:3a7713b1edbc 182 * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
AnnaBridge 171:3a7713b1edbc 183 * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1
AnnaBridge 171:3a7713b1edbc 184 * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13
AnnaBridge 171:3a7713b1edbc 185 * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8
AnnaBridge 171:3a7713b1edbc 186 * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11
AnnaBridge 171:3a7713b1edbc 187 */
AnnaBridge 171:3a7713b1edbc 188 #define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__))
AnnaBridge 171:3a7713b1edbc 189 /**
AnnaBridge 171:3a7713b1edbc 190 * @}
AnnaBridge 171:3a7713b1edbc 191 */
AnnaBridge 171:3a7713b1edbc 192 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 193 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
AnnaBridge 171:3a7713b1edbc 194 * @{
AnnaBridge 171:3a7713b1edbc 195 */
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 /** @addtogroup PWREx_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 198 * @{
AnnaBridge 171:3a7713b1edbc 199 */
AnnaBridge 171:3a7713b1edbc 200 uint32_t HAL_PWREx_GetVoltageRange(void);
AnnaBridge 171:3a7713b1edbc 201 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 void HAL_PWREx_EnableFlashPowerDown(void);
AnnaBridge 171:3a7713b1edbc 204 void HAL_PWREx_DisableFlashPowerDown(void);
AnnaBridge 171:3a7713b1edbc 205 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
AnnaBridge 171:3a7713b1edbc 206 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
AnnaBridge 171:3a7713b1edbc 209 void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
AnnaBridge 171:3a7713b1edbc 210 void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
AnnaBridge 171:3a7713b1edbc 211 void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
AnnaBridge 171:3a7713b1edbc 214 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
AnnaBridge 171:3a7713b1edbc 215 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 /**
AnnaBridge 171:3a7713b1edbc 218 * @}
AnnaBridge 171:3a7713b1edbc 219 */
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 /**
AnnaBridge 171:3a7713b1edbc 222 * @}
AnnaBridge 171:3a7713b1edbc 223 */
AnnaBridge 171:3a7713b1edbc 224 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 225 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 226 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 227 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 228 /** @defgroup PWREx_Private_Macros PWREx Private Macros
AnnaBridge 171:3a7713b1edbc 229 * @{
AnnaBridge 171:3a7713b1edbc 230 */
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
AnnaBridge 171:3a7713b1edbc 233 * @{
AnnaBridge 171:3a7713b1edbc 234 */
AnnaBridge 171:3a7713b1edbc 235 #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
AnnaBridge 171:3a7713b1edbc 236 ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
AnnaBridge 171:3a7713b1edbc 237 #define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || \
AnnaBridge 171:3a7713b1edbc 238 ((__PIN__) == PWR_WAKEUP_PIN2) || \
AnnaBridge 171:3a7713b1edbc 239 ((__PIN__) == PWR_WAKEUP_PIN3) || \
AnnaBridge 171:3a7713b1edbc 240 ((__PIN__) == PWR_WAKEUP_PIN4) || \
AnnaBridge 171:3a7713b1edbc 241 ((__PIN__) == PWR_WAKEUP_PIN5) || \
AnnaBridge 171:3a7713b1edbc 242 ((__PIN__) == PWR_WAKEUP_PIN6) || \
AnnaBridge 171:3a7713b1edbc 243 ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || \
AnnaBridge 171:3a7713b1edbc 244 ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || \
AnnaBridge 171:3a7713b1edbc 245 ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || \
AnnaBridge 171:3a7713b1edbc 246 ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || \
AnnaBridge 171:3a7713b1edbc 247 ((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || \
AnnaBridge 171:3a7713b1edbc 248 ((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || \
AnnaBridge 171:3a7713b1edbc 249 ((__PIN__) == PWR_WAKEUP_PIN1_LOW) || \
AnnaBridge 171:3a7713b1edbc 250 ((__PIN__) == PWR_WAKEUP_PIN2_LOW) || \
AnnaBridge 171:3a7713b1edbc 251 ((__PIN__) == PWR_WAKEUP_PIN3_LOW) || \
AnnaBridge 171:3a7713b1edbc 252 ((__PIN__) == PWR_WAKEUP_PIN4_LOW) || \
AnnaBridge 171:3a7713b1edbc 253 ((__PIN__) == PWR_WAKEUP_PIN5_LOW) || \
AnnaBridge 171:3a7713b1edbc 254 ((__PIN__) == PWR_WAKEUP_PIN6_LOW))
AnnaBridge 171:3a7713b1edbc 255 /**
AnnaBridge 171:3a7713b1edbc 256 * @}
AnnaBridge 171:3a7713b1edbc 257 */
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 /**
AnnaBridge 171:3a7713b1edbc 260 * @}
AnnaBridge 171:3a7713b1edbc 261 */
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 /**
AnnaBridge 171:3a7713b1edbc 264 * @}
AnnaBridge 171:3a7713b1edbc 265 */
AnnaBridge 171:3a7713b1edbc 266
AnnaBridge 171:3a7713b1edbc 267 /**
AnnaBridge 171:3a7713b1edbc 268 * @}
AnnaBridge 171:3a7713b1edbc 269 */
AnnaBridge 171:3a7713b1edbc 270
AnnaBridge 171:3a7713b1edbc 271 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 272 }
AnnaBridge 171:3a7713b1edbc 273 #endif
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 #endif /* __STM32F7xx_HAL_PWR_EX_H */
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/