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TARGET_DISCO_F746NG/TOOLCHAIN_IAR/stm32f7xx_hal_flash_ex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_hal_flash_ex.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of FLASH HAL Extension module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F7xx_HAL_FLASH_EX_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F7xx_HAL_FLASH_EX_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f7xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F7xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 49 | */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | |
| AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup FLASHEx |
| AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 53 | */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | |
| AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 56 | /** @defgroup FLASHEx_Exported_Types FLASH Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 57 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 58 | */ |
| AnnaBridge | 171:3a7713b1edbc | 59 | |
| AnnaBridge | 171:3a7713b1edbc | 60 | /** |
| AnnaBridge | 171:3a7713b1edbc | 61 | * @brief FLASH Erase structure definition |
| AnnaBridge | 171:3a7713b1edbc | 62 | */ |
| AnnaBridge | 171:3a7713b1edbc | 63 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 64 | { |
| AnnaBridge | 171:3a7713b1edbc | 65 | uint32_t TypeErase; /*!< Mass erase or sector Erase. |
| AnnaBridge | 171:3a7713b1edbc | 66 | This parameter can be a value of @ref FLASHEx_Type_Erase */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | |
| AnnaBridge | 171:3a7713b1edbc | 68 | #if defined (FLASH_OPTCR_nDBANK) |
| AnnaBridge | 171:3a7713b1edbc | 69 | uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. |
| AnnaBridge | 171:3a7713b1edbc | 70 | This parameter must be a value of @ref FLASHEx_Banks */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | #endif /* FLASH_OPTCR_nDBANK */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | |
| AnnaBridge | 171:3a7713b1edbc | 73 | uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled |
| AnnaBridge | 171:3a7713b1edbc | 74 | This parameter must be a value of @ref FLASHEx_Sectors */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | |
| AnnaBridge | 171:3a7713b1edbc | 76 | uint32_t NbSectors; /*!< Number of sectors to be erased. |
| AnnaBridge | 171:3a7713b1edbc | 77 | This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ |
| AnnaBridge | 171:3a7713b1edbc | 78 | |
| AnnaBridge | 171:3a7713b1edbc | 79 | uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism |
| AnnaBridge | 171:3a7713b1edbc | 80 | This parameter must be a value of @ref FLASHEx_Voltage_Range */ |
| AnnaBridge | 171:3a7713b1edbc | 81 | |
| AnnaBridge | 171:3a7713b1edbc | 82 | } FLASH_EraseInitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 83 | |
| AnnaBridge | 171:3a7713b1edbc | 84 | /** |
| AnnaBridge | 171:3a7713b1edbc | 85 | * @brief FLASH Option Bytes Program structure definition |
| AnnaBridge | 171:3a7713b1edbc | 86 | */ |
| AnnaBridge | 171:3a7713b1edbc | 87 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 88 | { |
| AnnaBridge | 171:3a7713b1edbc | 89 | uint32_t OptionType; /*!< Option byte to be configured. |
| AnnaBridge | 171:3a7713b1edbc | 90 | This parameter can be a value of @ref FLASHEx_Option_Type */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | |
| AnnaBridge | 171:3a7713b1edbc | 92 | uint32_t WRPState; /*!< Write protection activation or deactivation. |
| AnnaBridge | 171:3a7713b1edbc | 93 | This parameter can be a value of @ref FLASHEx_WRP_State */ |
| AnnaBridge | 171:3a7713b1edbc | 94 | |
| AnnaBridge | 171:3a7713b1edbc | 95 | uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. |
| AnnaBridge | 171:3a7713b1edbc | 96 | The value of this parameter depend on device used within the same series */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | |
| AnnaBridge | 171:3a7713b1edbc | 98 | uint32_t RDPLevel; /*!< Set the read protection level. |
| AnnaBridge | 171:3a7713b1edbc | 99 | This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ |
| AnnaBridge | 171:3a7713b1edbc | 100 | |
| AnnaBridge | 171:3a7713b1edbc | 101 | uint32_t BORLevel; /*!< Set the BOR Level. |
| AnnaBridge | 171:3a7713b1edbc | 102 | This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ |
| AnnaBridge | 171:3a7713b1edbc | 103 | |
| AnnaBridge | 171:3a7713b1edbc | 104 | uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / |
| AnnaBridge | 171:3a7713b1edbc | 105 | IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT. |
| AnnaBridge | 171:3a7713b1edbc | 106 | nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */ |
| AnnaBridge | 171:3a7713b1edbc | 107 | |
| AnnaBridge | 171:3a7713b1edbc | 108 | uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0. |
| AnnaBridge | 171:3a7713b1edbc | 109 | This parameter can be a value of @ref FLASHEx_Boot_Address */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | |
| AnnaBridge | 171:3a7713b1edbc | 111 | uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1. |
| AnnaBridge | 171:3a7713b1edbc | 112 | This parameter can be a value of @ref FLASHEx_Boot_Address */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | |
| AnnaBridge | 171:3a7713b1edbc | 114 | #if defined (FLASH_OPTCR2_PCROP) |
| AnnaBridge | 171:3a7713b1edbc | 115 | uint32_t PCROPSector; /*!< Set the PCROP sector. |
| AnnaBridge | 171:3a7713b1edbc | 116 | This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | |
| AnnaBridge | 171:3a7713b1edbc | 118 | uint32_t PCROPRdp; /*!< Set the PCROP_RDP option. |
| AnnaBridge | 171:3a7713b1edbc | 119 | This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | #endif /* FLASH_OPTCR2_PCROP */ |
| AnnaBridge | 171:3a7713b1edbc | 121 | |
| AnnaBridge | 171:3a7713b1edbc | 122 | } FLASH_OBProgramInitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 123 | |
| AnnaBridge | 171:3a7713b1edbc | 124 | /** |
| AnnaBridge | 171:3a7713b1edbc | 125 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 126 | */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 128 | |
| AnnaBridge | 171:3a7713b1edbc | 129 | /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 130 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 131 | */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | |
| AnnaBridge | 171:3a7713b1edbc | 133 | /** @defgroup FLASHEx_Type_Erase FLASH Type Erase |
| AnnaBridge | 171:3a7713b1edbc | 134 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 135 | */ |
| AnnaBridge | 171:3a7713b1edbc | 136 | #define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | /** |
| AnnaBridge | 171:3a7713b1edbc | 139 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 140 | */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | |
| AnnaBridge | 171:3a7713b1edbc | 142 | /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range |
| AnnaBridge | 171:3a7713b1edbc | 143 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 144 | */ |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */ |
| AnnaBridge | 171:3a7713b1edbc | 147 | #define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */ |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | /** |
| AnnaBridge | 171:3a7713b1edbc | 150 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 151 | */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | |
| AnnaBridge | 171:3a7713b1edbc | 153 | /** @defgroup FLASHEx_WRP_State FLASH WRP State |
| AnnaBridge | 171:3a7713b1edbc | 154 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 155 | */ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */ |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | /** |
| AnnaBridge | 171:3a7713b1edbc | 159 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 160 | */ |
| AnnaBridge | 171:3a7713b1edbc | 161 | |
| AnnaBridge | 171:3a7713b1edbc | 162 | /** @defgroup FLASHEx_Option_Type FLASH Option Type |
| AnnaBridge | 171:3a7713b1edbc | 163 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 164 | */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */ |
| AnnaBridge | 171:3a7713b1edbc | 166 | #define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */ |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */ |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | #if defined (FLASH_OPTCR2_PCROP) |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define OPTIONBYTE_PCROP ((uint32_t)0x40U) /*!< PCROP configuration */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define OPTIONBYTE_PCROP_RDP ((uint32_t)0x80U) /*!< PCROP_RDP configuration */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | #endif /* FLASH_OPTCR2_PCROP */ |
| AnnaBridge | 171:3a7713b1edbc | 175 | /** |
| AnnaBridge | 171:3a7713b1edbc | 176 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 177 | */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | |
| AnnaBridge | 171:3a7713b1edbc | 179 | /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection |
| AnnaBridge | 171:3a7713b1edbc | 180 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 181 | */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define OB_RDP_LEVEL_1 ((uint8_t)0x55U) |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 |
| AnnaBridge | 171:3a7713b1edbc | 185 | it s no more possible to go back to level 1 or 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 186 | /** |
| AnnaBridge | 171:3a7713b1edbc | 187 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 188 | */ |
| AnnaBridge | 171:3a7713b1edbc | 189 | |
| AnnaBridge | 171:3a7713b1edbc | 190 | /** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog |
| AnnaBridge | 171:3a7713b1edbc | 191 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 192 | */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */ |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | /** |
| AnnaBridge | 171:3a7713b1edbc | 196 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 197 | */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | |
| AnnaBridge | 171:3a7713b1edbc | 199 | |
| AnnaBridge | 171:3a7713b1edbc | 200 | /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog |
| AnnaBridge | 171:3a7713b1edbc | 201 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 202 | */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | /** |
| AnnaBridge | 171:3a7713b1edbc | 206 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 207 | */ |
| AnnaBridge | 171:3a7713b1edbc | 208 | |
| AnnaBridge | 171:3a7713b1edbc | 209 | /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP |
| AnnaBridge | 171:3a7713b1edbc | 210 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 211 | */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | #define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | /** |
| AnnaBridge | 171:3a7713b1edbc | 215 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 216 | */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | |
| AnnaBridge | 171:3a7713b1edbc | 218 | /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY |
| AnnaBridge | 171:3a7713b1edbc | 219 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 220 | */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | #define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */ |
| AnnaBridge | 171:3a7713b1edbc | 223 | /** |
| AnnaBridge | 171:3a7713b1edbc | 224 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 225 | */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | |
| AnnaBridge | 171:3a7713b1edbc | 227 | /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP |
| AnnaBridge | 171:3a7713b1edbc | 228 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 229 | */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | /** |
| AnnaBridge | 171:3a7713b1edbc | 233 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 234 | */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | |
| AnnaBridge | 171:3a7713b1edbc | 236 | /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY |
| AnnaBridge | 171:3a7713b1edbc | 237 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 238 | */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | #define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */ |
| AnnaBridge | 171:3a7713b1edbc | 241 | /** |
| AnnaBridge | 171:3a7713b1edbc | 242 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 243 | */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | |
| AnnaBridge | 171:3a7713b1edbc | 245 | /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level |
| AnnaBridge | 171:3a7713b1edbc | 246 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 247 | */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */ |
| AnnaBridge | 171:3a7713b1edbc | 249 | #define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | #define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */ |
| AnnaBridge | 171:3a7713b1edbc | 251 | #define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | /** |
| AnnaBridge | 171:3a7713b1edbc | 253 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 254 | */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | |
| AnnaBridge | 171:3a7713b1edbc | 256 | #if defined (FLASH_OPTCR_nDBOOT) |
| AnnaBridge | 171:3a7713b1edbc | 257 | /** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT |
| AnnaBridge | 171:3a7713b1edbc | 258 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 259 | */ |
| AnnaBridge | 171:3a7713b1edbc | 260 | #define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */ |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash |
| AnnaBridge | 171:3a7713b1edbc | 262 | (Dual bank Boot mode), or RAM if Boot address option in RAM */ |
| AnnaBridge | 171:3a7713b1edbc | 263 | /** |
| AnnaBridge | 171:3a7713b1edbc | 264 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 265 | */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | #endif /* FLASH_OPTCR_nDBOOT */ |
| AnnaBridge | 171:3a7713b1edbc | 267 | |
| AnnaBridge | 171:3a7713b1edbc | 268 | #if defined (FLASH_OPTCR_nDBANK) |
| AnnaBridge | 171:3a7713b1edbc | 269 | /** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank |
| AnnaBridge | 171:3a7713b1edbc | 270 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 271 | */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */ |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | /** |
| AnnaBridge | 171:3a7713b1edbc | 275 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 276 | */ |
| AnnaBridge | 171:3a7713b1edbc | 277 | #endif /* FLASH_OPTCR_nDBANK */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | |
| AnnaBridge | 171:3a7713b1edbc | 279 | /** @defgroup FLASHEx_Boot_Address FLASH Boot Address |
| AnnaBridge | 171:3a7713b1edbc | 280 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 281 | */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */ |
| AnnaBridge | 171:3a7713b1edbc | 285 | #define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */ |
| AnnaBridge | 171:3a7713b1edbc | 288 | #if (SRAM2_BASE == 0x2003C000U) |
| AnnaBridge | 171:3a7713b1edbc | 289 | #define OB_BOOTADDR_SRAM2 ((uint32_t)0x800FU) /*!< Boot from SRAM2 (0x2003C000) */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #else |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */ |
| AnnaBridge | 171:3a7713b1edbc | 292 | #endif /* SRAM2_BASE == 0x2003C000U */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | /** |
| AnnaBridge | 171:3a7713b1edbc | 294 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 295 | */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | |
| AnnaBridge | 171:3a7713b1edbc | 297 | /** @defgroup FLASH_Latency FLASH Latency |
| AnnaBridge | 171:3a7713b1edbc | 298 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 299 | */ |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 313 | #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | /** |
| AnnaBridge | 171:3a7713b1edbc | 317 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 318 | */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | |
| AnnaBridge | 171:3a7713b1edbc | 320 | #if defined (FLASH_OPTCR_nDBANK) |
| AnnaBridge | 171:3a7713b1edbc | 321 | /** @defgroup FLASHEx_Banks FLASH Banks |
| AnnaBridge | 171:3a7713b1edbc | 322 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 323 | */ |
| AnnaBridge | 171:3a7713b1edbc | 324 | #define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | /** |
| AnnaBridge | 171:3a7713b1edbc | 328 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 329 | */ |
| AnnaBridge | 171:3a7713b1edbc | 330 | #endif /* FLASH_OPTCR_nDBANK */ |
| AnnaBridge | 171:3a7713b1edbc | 331 | |
| AnnaBridge | 171:3a7713b1edbc | 332 | /** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit |
| AnnaBridge | 171:3a7713b1edbc | 333 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 334 | */ |
| AnnaBridge | 171:3a7713b1edbc | 335 | #if defined (FLASH_OPTCR_nDBANK) |
| AnnaBridge | 171:3a7713b1edbc | 336 | #define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | #else |
| AnnaBridge | 171:3a7713b1edbc | 338 | #define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #endif /* FLASH_OPTCR_nDBANK */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | /** |
| AnnaBridge | 171:3a7713b1edbc | 341 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 342 | */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | |
| AnnaBridge | 171:3a7713b1edbc | 344 | /** @defgroup FLASHEx_Sectors FLASH Sectors |
| AnnaBridge | 171:3a7713b1edbc | 345 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 346 | */ |
| AnnaBridge | 171:3a7713b1edbc | 347 | #if (FLASH_SECTOR_TOTAL == 24) |
| AnnaBridge | 171:3a7713b1edbc | 348 | #define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */ |
| AnnaBridge | 171:3a7713b1edbc | 349 | #define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */ |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */ |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | #define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */ |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */ |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */ |
| AnnaBridge | 171:3a7713b1edbc | 360 | #define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | #define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | #define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | #define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | #endif /* FLASH_SECTOR_TOTAL == 24 */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | /** |
| AnnaBridge | 171:3a7713b1edbc | 366 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 367 | */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | |
| AnnaBridge | 171:3a7713b1edbc | 369 | #if (FLASH_SECTOR_TOTAL == 24) |
| AnnaBridge | 171:3a7713b1edbc | 370 | /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection |
| AnnaBridge | 171:3a7713b1edbc | 371 | * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register, |
| AnnaBridge | 171:3a7713b1edbc | 372 | * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11. |
| AnnaBridge | 171:3a7713b1edbc | 373 | * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register, |
| AnnaBridge | 171:3a7713b1edbc | 374 | * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and |
| AnnaBridge | 171:3a7713b1edbc | 375 | * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1). |
| AnnaBridge | 171:3a7713b1edbc | 376 | * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices. |
| AnnaBridge | 171:3a7713b1edbc | 377 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 378 | */ |
| AnnaBridge | 171:3a7713b1edbc | 379 | /* Single Bank Sectors */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */ |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */ |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */ |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | #define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */ |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */ |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */ |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ |
| AnnaBridge | 171:3a7713b1edbc | 392 | #define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | |
| AnnaBridge | 171:3a7713b1edbc | 394 | /* Dual Bank Sectors */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | #define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */ |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */ |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */ |
| AnnaBridge | 171:3a7713b1edbc | 404 | #define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | #define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */ |
| AnnaBridge | 171:3a7713b1edbc | 406 | #define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ |
| AnnaBridge | 171:3a7713b1edbc | 407 | #define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | #define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */ |
| AnnaBridge | 171:3a7713b1edbc | 409 | #define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */ |
| AnnaBridge | 171:3a7713b1edbc | 410 | #define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */ |
| AnnaBridge | 171:3a7713b1edbc | 411 | #define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */ |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */ |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | #define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */ |
| AnnaBridge | 171:3a7713b1edbc | 419 | #define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | /** |
| AnnaBridge | 171:3a7713b1edbc | 421 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 422 | */ |
| AnnaBridge | 171:3a7713b1edbc | 423 | #endif /* FLASH_SECTOR_TOTAL == 24 */ |
| AnnaBridge | 171:3a7713b1edbc | 424 | |
| AnnaBridge | 171:3a7713b1edbc | 425 | #if (FLASH_SECTOR_TOTAL == 8) |
| AnnaBridge | 171:3a7713b1edbc | 426 | /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection |
| AnnaBridge | 171:3a7713b1edbc | 427 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 428 | */ |
| AnnaBridge | 171:3a7713b1edbc | 429 | #define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ |
| AnnaBridge | 171:3a7713b1edbc | 430 | #define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ |
| AnnaBridge | 171:3a7713b1edbc | 431 | #define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ |
| AnnaBridge | 171:3a7713b1edbc | 432 | #define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ |
| AnnaBridge | 171:3a7713b1edbc | 433 | #define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */ |
| AnnaBridge | 171:3a7713b1edbc | 434 | #define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */ |
| AnnaBridge | 171:3a7713b1edbc | 435 | #define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | #define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */ |
| AnnaBridge | 171:3a7713b1edbc | 437 | #define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | /** |
| AnnaBridge | 171:3a7713b1edbc | 439 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 440 | */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | #endif /* FLASH_SECTOR_TOTAL == 8 */ |
| AnnaBridge | 171:3a7713b1edbc | 442 | |
| AnnaBridge | 171:3a7713b1edbc | 443 | #if defined (FLASH_OPTCR2_PCROP) |
| AnnaBridge | 171:3a7713b1edbc | 444 | /** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors |
| AnnaBridge | 171:3a7713b1edbc | 445 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 446 | */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | #define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */ |
| AnnaBridge | 171:3a7713b1edbc | 448 | #define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */ |
| AnnaBridge | 171:3a7713b1edbc | 449 | #define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */ |
| AnnaBridge | 171:3a7713b1edbc | 450 | #define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4 */ |
| AnnaBridge | 171:3a7713b1edbc | 452 | #define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5 */ |
| AnnaBridge | 171:3a7713b1edbc | 453 | #define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6 */ |
| AnnaBridge | 171:3a7713b1edbc | 454 | #define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7 */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | #define OB_PCROP_SECTOR_All ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors */ |
| AnnaBridge | 171:3a7713b1edbc | 456 | /** |
| AnnaBridge | 171:3a7713b1edbc | 457 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 458 | */ |
| AnnaBridge | 171:3a7713b1edbc | 459 | |
| AnnaBridge | 171:3a7713b1edbc | 460 | /** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit |
| AnnaBridge | 171:3a7713b1edbc | 461 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 462 | */ |
| AnnaBridge | 171:3a7713b1edbc | 463 | #define OB_PCROP_RDP_ENABLE ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable */ |
| AnnaBridge | 171:3a7713b1edbc | 464 | #define OB_PCROP_RDP_DISABLE ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable */ |
| AnnaBridge | 171:3a7713b1edbc | 465 | /** |
| AnnaBridge | 171:3a7713b1edbc | 466 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 467 | */ |
| AnnaBridge | 171:3a7713b1edbc | 468 | #endif /* FLASH_OPTCR2_PCROP */ |
| AnnaBridge | 171:3a7713b1edbc | 469 | |
| AnnaBridge | 171:3a7713b1edbc | 470 | /** |
| AnnaBridge | 171:3a7713b1edbc | 471 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 472 | */ |
| AnnaBridge | 171:3a7713b1edbc | 473 | |
| AnnaBridge | 171:3a7713b1edbc | 474 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 475 | /** @defgroup FLASH_Exported_Macros FLASH Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 476 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 477 | */ |
| AnnaBridge | 171:3a7713b1edbc | 478 | /** |
| AnnaBridge | 171:3a7713b1edbc | 479 | * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) |
| AnnaBridge | 171:3a7713b1edbc | 480 | * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. |
| AnnaBridge | 171:3a7713b1edbc | 481 | * @param __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) |
| AnnaBridge | 171:3a7713b1edbc | 482 | * @retval The FLASH Boot Base Adress |
| AnnaBridge | 171:3a7713b1edbc | 483 | */ |
| AnnaBridge | 171:3a7713b1edbc | 484 | #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14) |
| AnnaBridge | 171:3a7713b1edbc | 485 | /** |
| AnnaBridge | 171:3a7713b1edbc | 486 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 487 | */ |
| AnnaBridge | 171:3a7713b1edbc | 488 | |
| AnnaBridge | 171:3a7713b1edbc | 489 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 490 | /** @addtogroup FLASHEx_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 491 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 492 | */ |
| AnnaBridge | 171:3a7713b1edbc | 493 | |
| AnnaBridge | 171:3a7713b1edbc | 494 | /** @addtogroup FLASHEx_Exported_Functions_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 495 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 496 | */ |
| AnnaBridge | 171:3a7713b1edbc | 497 | /* Extension Program operation functions *************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 498 | HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); |
| AnnaBridge | 171:3a7713b1edbc | 499 | HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); |
| AnnaBridge | 171:3a7713b1edbc | 500 | HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); |
| AnnaBridge | 171:3a7713b1edbc | 501 | void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); |
| AnnaBridge | 171:3a7713b1edbc | 502 | |
| AnnaBridge | 171:3a7713b1edbc | 503 | /** |
| AnnaBridge | 171:3a7713b1edbc | 504 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 505 | */ |
| AnnaBridge | 171:3a7713b1edbc | 506 | |
| AnnaBridge | 171:3a7713b1edbc | 507 | /** |
| AnnaBridge | 171:3a7713b1edbc | 508 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 509 | */ |
| AnnaBridge | 171:3a7713b1edbc | 510 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 511 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 512 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 513 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 514 | /** @defgroup FLASHEx_Private_Macros FLASH Private Macros |
| AnnaBridge | 171:3a7713b1edbc | 515 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 516 | */ |
| AnnaBridge | 171:3a7713b1edbc | 517 | |
| AnnaBridge | 171:3a7713b1edbc | 518 | /** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters |
| AnnaBridge | 171:3a7713b1edbc | 519 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 520 | */ |
| AnnaBridge | 171:3a7713b1edbc | 521 | |
| AnnaBridge | 171:3a7713b1edbc | 522 | #define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \ |
| AnnaBridge | 171:3a7713b1edbc | 523 | ((VALUE) == FLASH_TYPEERASE_MASSERASE)) |
| AnnaBridge | 171:3a7713b1edbc | 524 | |
| AnnaBridge | 171:3a7713b1edbc | 525 | #define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 526 | ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 527 | ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ |
| AnnaBridge | 171:3a7713b1edbc | 528 | ((RANGE) == FLASH_VOLTAGE_RANGE_4)) |
| AnnaBridge | 171:3a7713b1edbc | 529 | |
| AnnaBridge | 171:3a7713b1edbc | 530 | #define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 531 | ((VALUE) == OB_WRPSTATE_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 532 | |
| AnnaBridge | 171:3a7713b1edbc | 533 | #if defined (FLASH_OPTCR2_PCROP) |
| AnnaBridge | 171:3a7713b1edbc | 534 | #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ |
| AnnaBridge | 171:3a7713b1edbc | 535 | OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\ |
| AnnaBridge | 171:3a7713b1edbc | 536 | OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP))) |
| AnnaBridge | 171:3a7713b1edbc | 537 | #else |
| AnnaBridge | 171:3a7713b1edbc | 538 | #define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ |
| AnnaBridge | 171:3a7713b1edbc | 539 | OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1))) |
| AnnaBridge | 171:3a7713b1edbc | 540 | #endif /* FLASH_OPTCR2_PCROP */ |
| AnnaBridge | 171:3a7713b1edbc | 541 | |
| AnnaBridge | 171:3a7713b1edbc | 542 | #define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013) |
| AnnaBridge | 171:3a7713b1edbc | 543 | |
| AnnaBridge | 171:3a7713b1edbc | 544 | #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 545 | ((LEVEL) == OB_RDP_LEVEL_1) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 546 | ((LEVEL) == OB_RDP_LEVEL_2)) |
| AnnaBridge | 171:3a7713b1edbc | 547 | |
| AnnaBridge | 171:3a7713b1edbc | 548 | #define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW)) |
| AnnaBridge | 171:3a7713b1edbc | 549 | |
| AnnaBridge | 171:3a7713b1edbc | 550 | #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) |
| AnnaBridge | 171:3a7713b1edbc | 551 | |
| AnnaBridge | 171:3a7713b1edbc | 552 | #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) |
| AnnaBridge | 171:3a7713b1edbc | 553 | |
| AnnaBridge | 171:3a7713b1edbc | 554 | #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) |
| AnnaBridge | 171:3a7713b1edbc | 555 | |
| AnnaBridge | 171:3a7713b1edbc | 556 | #define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) |
| AnnaBridge | 171:3a7713b1edbc | 557 | |
| AnnaBridge | 171:3a7713b1edbc | 558 | #define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) |
| AnnaBridge | 171:3a7713b1edbc | 559 | |
| AnnaBridge | 171:3a7713b1edbc | 560 | #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 561 | ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) |
| AnnaBridge | 171:3a7713b1edbc | 562 | |
| AnnaBridge | 171:3a7713b1edbc | 563 | #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ |
| AnnaBridge | 171:3a7713b1edbc | 564 | ((LATENCY) == FLASH_LATENCY_1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 565 | ((LATENCY) == FLASH_LATENCY_2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 566 | ((LATENCY) == FLASH_LATENCY_3) || \ |
| AnnaBridge | 171:3a7713b1edbc | 567 | ((LATENCY) == FLASH_LATENCY_4) || \ |
| AnnaBridge | 171:3a7713b1edbc | 568 | ((LATENCY) == FLASH_LATENCY_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 569 | ((LATENCY) == FLASH_LATENCY_6) || \ |
| AnnaBridge | 171:3a7713b1edbc | 570 | ((LATENCY) == FLASH_LATENCY_7) || \ |
| AnnaBridge | 171:3a7713b1edbc | 571 | ((LATENCY) == FLASH_LATENCY_8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 572 | ((LATENCY) == FLASH_LATENCY_9) || \ |
| AnnaBridge | 171:3a7713b1edbc | 573 | ((LATENCY) == FLASH_LATENCY_10) || \ |
| AnnaBridge | 171:3a7713b1edbc | 574 | ((LATENCY) == FLASH_LATENCY_11) || \ |
| AnnaBridge | 171:3a7713b1edbc | 575 | ((LATENCY) == FLASH_LATENCY_12) || \ |
| AnnaBridge | 171:3a7713b1edbc | 576 | ((LATENCY) == FLASH_LATENCY_13) || \ |
| AnnaBridge | 171:3a7713b1edbc | 577 | ((LATENCY) == FLASH_LATENCY_14) || \ |
| AnnaBridge | 171:3a7713b1edbc | 578 | ((LATENCY) == FLASH_LATENCY_15)) |
| AnnaBridge | 171:3a7713b1edbc | 579 | |
| AnnaBridge | 171:3a7713b1edbc | 580 | #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ |
| AnnaBridge | 171:3a7713b1edbc | 581 | (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END))) |
| AnnaBridge | 171:3a7713b1edbc | 582 | #define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) |
| AnnaBridge | 171:3a7713b1edbc | 583 | |
| AnnaBridge | 171:3a7713b1edbc | 584 | #if (FLASH_SECTOR_TOTAL == 8) |
| AnnaBridge | 171:3a7713b1edbc | 585 | #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 586 | ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 587 | ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 588 | ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) |
| AnnaBridge | 171:3a7713b1edbc | 589 | |
| AnnaBridge | 171:3a7713b1edbc | 590 | #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) |
| AnnaBridge | 171:3a7713b1edbc | 591 | #endif /* FLASH_SECTOR_TOTAL == 8 */ |
| AnnaBridge | 171:3a7713b1edbc | 592 | |
| AnnaBridge | 171:3a7713b1edbc | 593 | #if (FLASH_SECTOR_TOTAL == 24) |
| AnnaBridge | 171:3a7713b1edbc | 594 | #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 595 | ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 596 | ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 597 | ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 598 | ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 599 | ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 600 | ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 601 | ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 602 | ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 603 | ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 604 | ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 605 | ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23)) |
| AnnaBridge | 171:3a7713b1edbc | 606 | |
| AnnaBridge | 171:3a7713b1edbc | 607 | #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) |
| AnnaBridge | 171:3a7713b1edbc | 608 | #endif /* FLASH_SECTOR_TOTAL == 24 */ |
| AnnaBridge | 171:3a7713b1edbc | 609 | |
| AnnaBridge | 171:3a7713b1edbc | 610 | #if defined (FLASH_OPTCR_nDBANK) |
| AnnaBridge | 171:3a7713b1edbc | 611 | #define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \ |
| AnnaBridge | 171:3a7713b1edbc | 612 | ((VALUE) == OB_NDBANK_DUAL_BANK)) |
| AnnaBridge | 171:3a7713b1edbc | 613 | |
| AnnaBridge | 171:3a7713b1edbc | 614 | #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 615 | ((BANK) == FLASH_BANK_2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 616 | ((BANK) == FLASH_BANK_BOTH)) |
| AnnaBridge | 171:3a7713b1edbc | 617 | #endif /* FLASH_OPTCR_nDBANK */ |
| AnnaBridge | 171:3a7713b1edbc | 618 | |
| AnnaBridge | 171:3a7713b1edbc | 619 | #if defined (FLASH_OPTCR_nDBOOT) |
| AnnaBridge | 171:3a7713b1edbc | 620 | #define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 621 | ((VALUE) == OB_DUAL_BOOT_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 622 | #endif /* FLASH_OPTCR_nDBOOT */ |
| AnnaBridge | 171:3a7713b1edbc | 623 | |
| AnnaBridge | 171:3a7713b1edbc | 624 | #if defined (FLASH_OPTCR2_PCROP) |
| AnnaBridge | 171:3a7713b1edbc | 625 | #define IS_OB_PCROP_SECTOR(SECTOR) (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 626 | #define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 627 | ((VALUE) == OB_PCROP_RDP_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 628 | #endif /* FLASH_OPTCR2_PCROP */ |
| AnnaBridge | 171:3a7713b1edbc | 629 | |
| AnnaBridge | 171:3a7713b1edbc | 630 | /** |
| AnnaBridge | 171:3a7713b1edbc | 631 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 632 | */ |
| AnnaBridge | 171:3a7713b1edbc | 633 | |
| AnnaBridge | 171:3a7713b1edbc | 634 | /** |
| AnnaBridge | 171:3a7713b1edbc | 635 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 636 | */ |
| AnnaBridge | 171:3a7713b1edbc | 637 | |
| AnnaBridge | 171:3a7713b1edbc | 638 | /* Private functions ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 639 | /** @defgroup FLASHEx_Private_Functions FLASH Private Functions |
| AnnaBridge | 171:3a7713b1edbc | 640 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 641 | */ |
| AnnaBridge | 171:3a7713b1edbc | 642 | void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); |
| AnnaBridge | 171:3a7713b1edbc | 643 | /** |
| AnnaBridge | 171:3a7713b1edbc | 644 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 645 | */ |
| AnnaBridge | 171:3a7713b1edbc | 646 | |
| AnnaBridge | 171:3a7713b1edbc | 647 | /** |
| AnnaBridge | 171:3a7713b1edbc | 648 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 649 | */ |
| AnnaBridge | 171:3a7713b1edbc | 650 | |
| AnnaBridge | 171:3a7713b1edbc | 651 | /** |
| AnnaBridge | 171:3a7713b1edbc | 652 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 653 | */ |
| AnnaBridge | 171:3a7713b1edbc | 654 | |
| AnnaBridge | 171:3a7713b1edbc | 655 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 656 | } |
| AnnaBridge | 171:3a7713b1edbc | 657 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 658 | |
| AnnaBridge | 171:3a7713b1edbc | 659 | #endif /* __STM32F7xx_HAL_FLASH_EX_H */ |
| AnnaBridge | 171:3a7713b1edbc | 660 | |
| AnnaBridge | 171:3a7713b1edbc | 661 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
